Data arrangement support device, and data arrangement support method

Abstract

To suppress a performance deterioration in software by enhancing the locality of data and cache utilization efficiency.SOLUTION: A data arrangement support device includes a source code analysis part for outputting variable reading / writing and variable definition information, an access sequence generation part for generating an executable path on the basis of branch information and outputting an access sequence on the basis of the variable reading / writing, an access sequence learning part for generating a learned model for inferring an appearance probability of a variable identifier, a learned model storage part 6 for storing the learned model, a variable order inference part for inferring an adjacent sequence on the basis of the learned model, and a variable order display part for displaying an order of the variable identifiers in the adjacent sequence with the variable on the basis of the variable definition information.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a data placement technology in software. [Background technology]

[0002] 2. Description of the Related Art In order to improve software processing performance, there are processors that have multiple processor cores (hereinafter also referred to as cores) (hereinafter also referred to as multi-core processors).

[0003] Here, the access from the processor to the main memory is slower than the processor's calculation speed. Therefore, in order to reduce the access time between the processor and the main memory, a cache, which is a storage element that has a smaller capacity than the main memory but can operate at high speed, is provided for each processor or for each core within the processor.

[0004] A cache holds data in fixed-length units called cache lines. In a multi-core processor, the cache usage efficiency decreases due to inter-core synchronization processing to maintain data consistency between the cores. For this reason, there are cache memory devices that increase the usage efficiency of the cache (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2001-34597 A Summary of the Invention [Problem to be solved by the invention]

[0006] Such a cache memory device has the characteristic of preventing a decrease in software performance by increasing the efficiency of cache utilization without relying on software.

[0007] However, because the data used by the software is scattered and has low locality, the amount of data that could be stored in a single cache line may be distributed across multiple cache lines, which may induce capacity-related cache misses and reduce the performance of software processing.

[0008] Furthermore, data that is shared between cores (threads) and data that is not shared may be allocated to the same cache line, resulting in false sharing of the cache, which may degrade the performance of software processing.

[0009] The technology disclosed in this specification has been made in consideration of the problems described above, and is a technology for suppressing software performance degradation by improving data locality and cache utilization efficiency. [Means for solving the problem]

[0010] A data placement assistance device that is a first aspect of the technology disclosed in the present specification includes a source code analysis unit for outputting, from a source code, variable reads and writes that represent accesses to a plurality of variables in a function with unique variable identifiers, branch information that is information regarding the branching of the function, and variable definition information that is information regarding the definitions of the variables, an access sequence generation unit for generating an executable path that is an executable processing order of at least one of the functions based on the branch information and outputting the order of the variables referenced in the executable path as an access sequence based on the variable reads and writes, an access sequence learning unit for generating a learned model for inferring the occurrence probability of the variable identifiers corresponding to the variables referenced in the order in the access sequence, a variable order inference unit for inferring an adjacent sequence including the variable identifiers arranged in an order that is most likely to be concatenated based on the learned model, and a variable order display unit for displaying the order of the variable identifiers in the adjacent sequence with the corresponding variables based on the variable definition information. Effect of the Invention

[0011] According to at least a first aspect of the technology disclosed in the present specification, by inferring an adjacent series in which processes are arranged in the order most likely to be connected and displaying variables in the order in the adjacent series, data locality and cache utilization efficiency can be improved, thereby suppressing software performance degradation.

[0012] Furthermore, objects, features, aspects and advantages associated with the technology disclosed herein will become more apparent from the detailed description set forth below and the accompanying drawings. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of a learning device related to the data placement assistance device according to the present embodiment. [Diagram 2] FIG. 13 is a diagram illustrating an example of variable definition information. [Diagram 3] 13A and 13B are diagrams illustrating examples of variable read / write and branch information. [Figure 4] FIG. 13 is a diagram illustrating an example of an access sequence. [Diagram 5] 13 is a flowchart illustrating an example of a method for generating an access sequence. [Figure 6] 6 is a flowchart showing an example of a method (step ST1) for generating executable paths for the function in FIG. 5. [Figure 7] 6 is a flowchart showing an example of a method (step ST2) for generating a reference sequence for the function in FIG. 5. [Figure 8] 6 is a flowchart showing an example of a method (step ST5) of generating an access sequence spanning functions in FIG. 5. [Figure 9] FIG. 2 illustrates an example of a configuration of an inference device related to a data placement support apparatus according to an embodiment. [Figure 10] 5 is a diagram showing an example of an adjacent sequence of variable identifiers arranged in order of highest probability of concatenation, corresponding to the access sequence in FIG. 4. FIG. [Figure 11] 10 is a flowchart illustrating an example of a method for generating a contiguous sequence of variable identifiers in an order that is most likely to be concatenated. [Figure 12] FIG. 2 illustrates an example of a configuration of a learning device related to the data placement support device according to the embodiment; [Figure 13] FIG. 13 is a diagram illustrating an example of a termination condition. [Figure 14] 11 is a flowchart illustrating an example of a method for generating a feasible path, among methods for generating access sequences by an access sequence generating unit according to the embodiment. [Figure 15] FIG. 2 illustrates an example of a configuration of a learning device related to the data placement support device according to the embodiment; [Figure 16] FIG. 2 illustrates an example of a configuration of an inference device related to a data placement support apparatus according to an embodiment. [Figure 17] FIG. 13 illustrates an example of a shared variable. [Figure 18] FIG. 17 is a diagram illustrating a schematic example of a hardware configuration when the data placement support device, examples of which are shown in FIGS. 1, 9, 12, 15, and 16, is actually operated. [Figure 19] FIG. 17 is a diagram illustrating a schematic example of a hardware configuration when the data placement support device, examples of which are shown in FIGS. 1, 9, 12, 15, and 16, is actually operated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but they are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0015] The drawings are schematic, and for the sake of convenience, configurations may be omitted or simplified as appropriate. The size and positional relationship of the configurations shown in different drawings are not necessarily described accurately, and may be changed as appropriate. Hatching may be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the contents of the embodiments.

[0016] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted to avoid duplication.

[0017] Furthermore, in the description in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0018] Furthermore, even if ordinal numbers such as "first" or "second" are used in the description of this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the orders that may result from these ordinal numbers.

[0019] <First embodiment> The data placement support device and the data placement support method according to this embodiment will be described below.

[0020] <Learning Phase> 1 is a diagram showing an example of the configuration of a learning device related to the data placement assistance device of this embodiment. As shown in the example in Fig. 1, the learning device includes a source code analysis unit 1, a function information storage unit 2, an access sequence generation unit 3, an access sequence storage unit 4, an access sequence learning unit 5, and a learned model storage unit 6.

[0021] An input of the function information storage unit 2 is connected to an output of the source code analysis unit 1. An input of the access sequence generation unit 3 is connected to an output of the function information storage unit 2. An input of the access sequence storage unit 4 is connected to an output of the access sequence generation unit 3. An input of the access sequence learning unit 5 is connected to an output of the access sequence storage unit 4. An input of the learned model storage unit 6 is connected to an output of the access sequence learning unit 5.

[0022] The source code analysis unit 1 is a tool that outputs, from the source code, variable read / write 7, which indicates variable access within a function with a unique variable identifier 9, branch information 8, and variable definition information 10. Here, variable access refers to access to a variable, and the variable identifier 9 is an identifier that indicates access to a certain variable. The source code analysis unit 1 is a static analysis tool that analyzes the lexical content of the source code, or a static analysis tool that analyzes the syntax of the source code.

[0023] The variable identifier 9 is a variable identifier that is uniquely assigned throughout all source code to be analyzed. The variable definition information 10 is information regarding the definition of a variable, and is information indicating the relationship between the variable identifier 9 and the variable entity.

[0024] Fig. 2 is a diagram showing an example of variable definition information 10. Fig. 2 shows that variable identifiers 9 1, 2, and 3 are assigned to int type variables a, b, and c, respectively.

[0025] Variable reads and writes 7 indicate variable accesses within a function using unique variable identifiers 9. Branch information 8 indicates branches within and outside the function. Branches outside the function include indirect references using function pointers.

[0026] Fig. 3 is a diagram showing an example of variable read / write 7 and branch information 8. In Fig. 3, a process number 11 is assigned to a line that accesses a variable of function func, starting with 1. Note that in Fig. 3, the corresponding process number 11 is commented out at the end of each line of function func.

[0027] In Figure 3, the variable identifiers 9 that access the variables shown in Figure 2 for process number 11 are written in the order of access. For example, the line with process number 11 being 2 reads the contents of variable c and assigns it to variable a, so the sequence of variable identifiers 9 is 3,1.

[0028] Branch destination process number 12 is branch information 8, and describes process number 11 that can be executed next. For example, in a line where process number 11 is 4, there is no branch, so the branch destination process number 12 is uniquely process number 11 = 5. In contrast, in a line where process number 11 is 1, there is a branch, so the branch destination process number 12 is process number 11 = 2 or process number 11 = 3.

[0029] If the line involves a function call, the called function and the process number 11 after the function returns should be written in branch destination process number 12. For example, the line where process number 11 is 5 involves a function call, so branch destination process number 12 is funcB followed by process number 11, 6.

[0030] Finally, the end of the function or function exit sets the branch destination process number 12 to 0. Then, the executable path 13 is a sequence of process numbers 11 generated based on the branch destination process number 12 from the first process number 11, which are 1,2,4,5,6(,0), 1,2,4,5,6,7(,0), 1,3,4,5,6(,0), and 1,3,4,5,6,7(,0) in FIG.

[0031] The function information storage unit 2 in FIG. 1 accumulates the function call relationships, variable read / write 7, and branch information 8 acquired by the source code analysis unit 1.

[0032] The access sequence generating unit 3 in FIG. 1 generates an access sequence 14 from variable read / write 7 and branch information 8 stored in the function information storage unit 2 .

[0033] The access sequence 14 is a sequence of variable reads and writes 7 taking into account the executable paths 13. Fig. 4 is a diagram showing an example of the access sequence 14. Fig. 4 shows the access sequence 14 for the function func in Figs. 2 and 3.

[0034] The access sequence 14 is generated by listing the variable identifiers 9 corresponding to the process numbers 11 of the executable path 13 in order of appearance. Also, the access sequence 14 describes only one consecutive access to the same variable. For example, the access sequence 14 for 1 and 2 of process number 11 is not 3,3,1, but 3,1 by eliminating the consecutive (duplicate) 3,3.

[0035] Also, when another function is called, the access sequence 14 of the other function is inserted to generate the access sequence 14. In Fig. 4, if the access sequence 14 of funcB is 3,2, there are only two access sequences 14, 3,1,2,3,2 and 3,1,2,3,2,1, which do not match the number of executable paths 13. This is because, for example, the sequence of variable identifiers 9 referenced by 1,2,4,5,6 and 1,3,4,5,6 as executable paths 13 is the same. That is, when the executable path 13 is 1,2,4,5,6(,0), the variable identifiers 9 are 3,3,1,1,2,3,2,2, so the access sequence 14 is 3,1,2,3,2. Furthermore, when the feasible path 13 is 1, 3, 4, 5, 6(, 0), the variable identifiers 9 are 3, 1, 1, 2, 3, 2, 2, so the access sequence 14 is 3, 1, 2, 3, 2.

[0036] Next, a method for generating an access sequence 14 by the access sequence generating unit 3 will be described with reference to Fig. 5. Here, Fig. 5 is a flowchart showing an example of a method for generating an access sequence.

[0037] First, in step ST1, executable paths 13 of the function are generated based on the branch information 8. Next, in step ST2, a reference sequence within the function is generated. Next, in step ST3, the top function is obtained.

[0038] Next, in step ST4, one of the top functions obtained in step ST3 is selected. Next, in step ST5, an access sequence 14 across functions is generated for the one top function obtained in step ST4. Then, the process proceeds to step ST6.

[0039] Finally, in step ST6, it is determined whether or not there is any unprocessed top function among the top functions acquired in step ST3. If there is any unprocessed top function, the process returns to step ST4, and if there is no unprocessed top function, the process ends.

[0040] FIG. 6 is a flow chart showing an example of a method (step ST1) for generating executable paths 13 for the function in FIG.

[0041] First, in step ST7, one unprocessed function is obtained from the function information storage unit 2. Next, in step ST8, one path whose process number 11 is simply 1 indicating the beginning of the function is added to the executable path 13.

[0042] Next, in step ST9, it is determined whether or not there is a path stored in the executable path 13 whose final process number 11 is not 0. If there is a path whose final process number 11 is not 0, the process proceeds to step ST10, and if there is no path whose final process number 11 is not 0, the process proceeds to step ST16.

[0043] In step ST16, it is determined whether or not there is an unprocessed function in the function information storage unit 2. If there is an unprocessed function in the function information storage unit 2, the process proceeds to step ST7, and if there is no unprocessed function in the function information storage unit 2, the process ends.

[0044] Next, in step ST10, one path whose trailing process number 11 is not 0 is extracted from the executable path 13. Next, in step ST11, the trailing process number 11 of the path extracted in step ST10 is obtained.

[0045] Next, in step ST12, the branch destination process numbers 12 of the process number 11 obtained in step ST11 are obtained. Next, in step ST13, unprocessed branch destination process numbers 12 are extracted from the branch destination process numbers 12 obtained in step ST12.

[0046] Next, in step ST14, the relevant called function and the branch destination process number 12 extracted in step ST13 are added to the end of the path extracted in step ST10 in the order of the called function, branch destination process number 12. Furthermore, this path is added to the executable path 13.

[0047] Next, in step ST15, it is determined whether or not there is an unprocessed branch destination process number 12 among the branch destination process numbers 12 acquired in step ST12. If there is an unprocessed branch destination process number 12, the process proceeds to step ST13, and if there is no unprocessed branch destination process number 12, the process proceeds to step ST9.

[0048] FIG. 7 is a flowchart showing an example of a method (step ST2) for generating a reference sequence for the function in FIG.

[0049] First, in step ST17, one unprocessed function is obtained from the function information storage unit 2. Next, in step ST18, the reference sequence 15 of the function obtained in step ST17 is emptied.

[0050] Next, in step ST19, one executable path 13 of the unprocessed function obtained in step ST17 is obtained. Next, in step ST20, the reference sequence 16 is emptied.

[0051] Next, in step ST21, the process number 11 of the executable path 13 obtained in step ST19 is obtained from the top. Next, in step ST22, the variable identifier 9 corresponding to the process number 11 obtained in step ST21 is obtained from the variable read / write 7 in the function information storage unit 2, and added to the reference sequence 16. Next, in step ST23, consecutive (duplicate) variable identifiers 9 in the reference sequence 16 are deleted.

[0052] Next, in step ST24, it is determined whether or not there is a function call corresponding to the process number 11 obtained in step ST21. If there is a function call corresponding to the process number 11, the process proceeds to step ST25, and if there is no function call corresponding to the process number 11, the process proceeds to step ST26.

[0053] In step ST25, the function reference found in step ST24 is added to the reference sequence 16. Then, the process proceeds to step ST26.

[0054] Next, in step ST26, it is determined whether or not there is a process number 11 of another feasible path 13. If there is a process number 11 of another feasible path 13, the process proceeds to step ST21, and if there is no process number 11 of another feasible path 13, the process proceeds to step ST27. Next, in step ST27, a reference sequence 16 is added to the reference sequence 15 of the function.

[0055] Next, in step ST28, it is determined whether or not there is overlap in the function reference sequence 15. If there is overlap in the function reference sequence 15, the process proceeds to step ST29, and if there is no overlap in the function reference sequence 15, the process proceeds to step ST30.

[0056] In step ST29, the overlapping reference sequence 16 is deleted from the function reference sequence 15. Then, the process proceeds to step ST30.

[0057] Next, in step ST30, it is determined whether or not there is an executable path 13 of the unprocessed function acquired in step ST19. If there is an executable path 13 of the unprocessed function, the process proceeds to step ST19, and if there is no executable path 13 of the unprocessed function, the process proceeds to step ST31.

[0058] Finally, in step ST31, it is determined whether or not there is an unprocessed function in the function information storage unit 2. If there is an unprocessed function, the process proceeds to step ST17, and if there is no unprocessed function, the process ends.

[0059] FIG. 8 is a flow chart showing an example of a method (step ST5) of generating the access sequence 14 across functions in FIG.

[0060] First, in step ST32, the additional access sequence is set as the reference sequence 15 of the leading function. Next, in step ST33, it is determined whether the additional access sequence includes a function reference. If the additional access sequence includes a function reference, the process proceeds to step ST34, and if the additional access sequence does not include a function reference, the process proceeds to step ST40.

[0061] In step ST34, one function reference sequence 15 including the function reference is extracted from the additional access sequence. Next, in step ST35, one function reference is selected from the function reference sequence 15 extracted in step ST34.

[0062] Next, in step ST36, one reference sequence 15 of the function selected in step ST35 is obtained. Here, if a function is directly called, the reference destination of the function is determined to be one and only one, but if a function pointer table or polymorphism exists, multiple functions are obtained as reference destinations.

[0063] Next, in step ST37, the reference sequence 15 of the function extracted in step ST34 is added to the additional access sequence. Next, in step ST38, one function reference in the reference sequence 15 of the function added in step ST37 is replaced with the reference sequence 15 of the function obtained in step ST36.

[0064] Next, in step ST39, it is determined whether or not there is another reference series 15 for the function acquired in step ST36. If there is another reference series 15, the process proceeds to step ST36, and if there is no other reference series 15, the process proceeds to step ST33.

[0065] In step ST40, the additional access sequence is added to the access sequence 14, and the process ends.

[0066] The access sequence storage unit 4 in FIG. 1 accumulates the access sequence 14 generated by the access sequence generation unit 3.

[0067] 1 learns the occurrence probability of adjacent variable identifiers (adjacent variable identifiers) using the access sequences 14 stored in the access sequence storage unit 4. Then, the access sequence learning unit 5 outputs a learned model for inferring the occurrence probability of the adjacent variable identifiers.

[0068] The appearance probability of adjacent variable identifiers is the probability that another variable identifier 9 appears next to a variable identifier 9 that corresponds to a variable referenced in the order in the access sequence 14. For example, in FIG. 4, the probability that the variable identifier 9 is 2 after 1 is the highest, the probability that the variable identifier 9 is 3 after 2 is the highest, the probability that the variable identifier 9 is 1 after 2 is the next highest, and so on.

[0069] A known algorithm such as a neural network or a deep neural network can be used as the learning algorithm used by the access sequence learning unit 5. In the following, a case where a neural network is applied will be described as an example.

[0070] The access sequence learning unit 5 learns the occurrence probability of adjacent variable identifiers by so-called supervised learning, for example, according to the CBoW model or skip gram model used in word2vec. Here, supervised learning refers to learning the occurrence probability of neighboring variable identifiers 9 for a certain variable identifier 9 by providing the access sequence 14 to the access sequence learning unit 5.

[0071] The learning algorithm used in the access sequence learning unit 5 may be Bidirectional Encoder Representations from Transformers (BERT), or other known methods for learning occurrence probabilities may be applied.

[0072] The learned model storage unit 6 in FIG. 1 stores the learned model output from the access sequence learning unit 5.

[0073] <Utilization phase> 9 is a diagram showing an example of the configuration of an inference device related to the data placement support device of this embodiment. As shown in the example in FIG. 9, the inference device includes a source code analysis unit 1, a variable information storage unit 20, a trained model storage unit 6, a variable order inference unit 21, and a variable order display unit 22.

[0074] An input of the variable information storage unit 20 is connected to an output of the source code analysis unit 1. An input of the variable order inference unit 21 is connected to an output of the trained model storage unit 6. An input of the variable order display unit 22 is connected to the output of the variable information storage unit 20 and the output of the variable order inference unit 21.

[0075] The variable information storage unit 20 accumulates the variable definition information 10 output by the source code analysis unit 1.

[0076] The variable order inference unit 21 infers an adjacent sequence of variable identifiers 9 arranged in an order that is most likely to be connected, using the occurrence probability of adjacent variable identifiers obtained by utilizing the trained model stored in the trained model storage unit 6.

[0077] FIG. 10 is a diagram showing an example of an adjacent sequence of variable identifiers 9 arranged in order of the highest probability of concatenation, corresponding to the access sequence 14 in FIG.

[0078] The two sequences of the access sequence 14 in Fig. 4 start with 3. Therefore, when the sequences are arranged in order of the likelihood of concatenation from 3, they become 3, 1, 2 (see Fig. 10).

[0079] FIG. 11 is a flow chart showing an example of a method for generating an adjacent sequence of variable identifiers 9 arranged in order of the highest probability of concatenation.

[0080] First, in step ST41, a learned model is obtained from the learned model storage unit 6, and the occurrence probability of adjacent variable identifiers is obtained. Next, in step ST42, all variable identifiers 9 stored in the variable information storage unit 20 are added to the variable identifier list 24.

[0081] Next, in step ST43, the variable identifier 9 most likely to be accessed first is obtained from the appearance probability of the adjacent variable identifiers. Next, in step ST44, the variable identifier 9 obtained in step ST43 is deleted from the variable identifier list 24.

[0082] Next, in step ST45, the variable identifier 9 acquired in step ST43 is substituted into the adjacent series. Next, in step ST46, it is determined whether or not the variable identifier list 24 is empty. If the variable identifier list 24 is empty, the process ends, and if the variable identifier list 24 is not empty, the process proceeds to step ST47.

[0083] Next, in step ST47, the last variable identifier 9 in the adjacent series is obtained. Next, in step ST48, the variable identifier 9 that is most likely to be adjacent to the variable identifier 9 obtained in step ST47 based on the occurrence probability of the adjacent variable identifiers obtained in step ST41 and that exists in the variable identifier list 24 is obtained.

[0084] Next, in step ST49, the variable identifier 9 obtained in step ST48 is deleted from the variable identifier list 24. Next, in step ST50, the variable identifier 9 obtained in step ST48 is added to the end of the adjacent series, and the process proceeds to step ST46.

[0085] The variable order display unit 22 in FIG. 9 replaces the variable identifiers 9 of the adjacent series output by the variable order inference unit 21 with variable entities based on the variable definition information 10 stored in the variable information storage unit 20, thereby displaying the variable order arranged in the order that is most likely to be connected.

[0086] In this way, by learning the variable access sequence 14 that can be analyzed from the source code, data locality can be improved and degradation of software performance can be suppressed.

[0087] <Second embodiment> A data placement support device and a data placement support method according to the present embodiment will be described. In the following description, components similar to those described in the above embodiment will be illustrated with the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0088] <Learning Phase> In the first embodiment, a function reference sequence is generated based on branch information 8 that can be obtained from the source code analysis unit 1, so when using a loop using a for statement, a while statement, or a goto statement, or a recursive call between functions, the access sequence 14 may continue infinitely depending on how the branch destination process number 12 is selected. This may result in learning not being completed.

[0089] In response to this, by providing a termination condition to the function information storage unit 2, the access sequence 14 can be truncated at a finite point and the learning can be completed.

[0090] 12 is a diagram showing an example of the configuration of a learning device related to the data placement assistance device of this embodiment. As shown in FIG. 12, the learning device includes a source code analysis unit 1, a function information storage unit 2, a termination condition input unit 26, an access sequence generation unit 3, an access sequence storage unit 4, an access sequence learning unit 5, and a learned model storage unit 6.

[0091] The input of the function information storage unit 2 is connected to the output of the source code analysis unit 1 and the output of the termination condition input unit 26. The input of the access sequence generation unit 3 is connected to the output of the function information storage unit 2. The input of the access sequence storage unit 4 is connected to the output of the access sequence generation unit 3. The input of the access sequence learning unit 5 is connected to the output of the access sequence storage unit 4. The input of the learned model storage unit 6 is connected to the output of the access sequence learning unit 5.

[0092] The termination condition 25 input by the termination condition input unit 26 specifies the maximum number of executions of the branch destination process number 12 for each process number 11 with respect to the branch information 8 .

[0093] Fig. 13 is a diagram showing an example of the termination condition 25. In the example shown in Fig. 13, the source code includes a while statement. In this case, if 3 is continuously selected as the branch destination process number 12 in the line where the process number 11 is 2, an infinite loop will occur, and the access sequence 14 will continue infinitely, and learning will not be completed.

[0094] In branch destination process number 12 in Fig. 13, the number in parentheses indicates the termination condition 25. Since branch destination process number 12 with termination condition 25 specified indicates the maximum number of executions, in the example in Fig. 13, the branch with process number 11 of 3 can only be taken a maximum of two times, and from the third time onwards, the branch with process number 11 of 6 is always selected.

[0095] The termination condition input unit 26 specifies a termination condition 25, which is the maximum number of executions, for the branch destination process number 12 in the branch information 8 stored in the function information storage unit 2. The termination condition input unit 26 may specify the termination condition 25 as the maximum number of executions for the corresponding line number of the specified source file, or may directly edit the termination condition 25 in the function information storage unit 2.

[0096] The access sequence generation unit 3 in FIG. 12 generates an access sequence 14 in the manner described in the first embodiment, and also generates a feasible path 13 taking into consideration a termination condition 25, which is the maximum number of executions, and generates an access sequence 14 based on the generated feasible path 13.

[0097] FIG. 14 is a flowchart showing an example of a method for generating an executable path 13 among methods for generating an access sequence 14 by the access sequence generating unit 3 of this embodiment.

[0098] In FIG. 14, different from FIG. 6, in step ST13, an unprocessed branch destination process number 12 is extracted from among the branch destination process numbers 12 acquired in step ST12, and then the process proceeds to step ST51.

[0099] Next, in step ST51, the number of executions for branch destination process number 12 is incremented by one. Next, in step ST52, it is determined whether or not the number of executions incremented in step ST51 exceeds the maximum number of executions defined in termination condition 25. If the number of executions exceeds the maximum number of executions defined in termination condition 25, the process proceeds to step ST15, and if the number of executions does not exceed the maximum number of executions defined in termination condition 25, the process proceeds to step ST14.

[0100] In this way, by specifying the termination condition 25, it is possible to prevent infinite generation of access sequences 14 and complete the learning within a finite time.

[0101] <Third embodiment> A data placement support device and a data placement support method according to the present embodiment will be described. In the following description, components similar to those described in the above embodiment will be illustrated with the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0102] <Learning Phase> In the first embodiment, a function reference sequence is generated based on branch information 8 that can be obtained from the source code analysis unit 1. Therefore, when learning is performed based on an executable path 13 such as an abnormal or quasi-abnormal system, the inferred variable identifier list 24 may not be in the optimal order for the executable path 13 of the normal system.

[0103] In response to this, by reducing the branch information 8 stored in the function information storage unit 2, it is possible to infer the optimal order for the executable path 13 of the normal system.

[0104] 15 is a diagram showing an example of the configuration of a learning device related to the data placement assistance device of this embodiment. As shown in FIG. 15, the learning device includes a source code analysis unit 1, a function information storage unit 2, a prohibited condition input unit 27, an access sequence generation unit 3, an access sequence storage unit 4, an access sequence learning unit 5, and a learned model storage unit 6.

[0105] The input of the function information storage unit 2 is connected to the output of the source code analysis unit 1 and the output of the prohibited condition input unit 27. The input of the access sequence generation unit 3 is connected to the output of the function information storage unit 2. The input of the access sequence storage unit 4 is connected to the output of the access sequence generation unit 3. The input of the access sequence learning unit 5 is connected to the output of the access sequence storage unit 4. The input of the learned model storage unit 6 is connected to the output of the access sequence learning unit 5.

[0106] The prohibition condition input by the prohibition condition input unit 27 specifies the branch destination process number 12 to be deleted with respect to the branch information 8.

[0107] The prohibited condition input unit 27 deletes the branch destination process number 12 specified by the prohibited condition from the branch information 8 stored in the function information storage unit 2. The prohibited condition input unit 27 can specify the process to be deleted in either the format of the line number where the corresponding process is described in the source file or the format of the branch destination process number 12 in the function information storage unit 2.

[0108] In this way, by specifying the prohibited conditions, it is possible to prevent erroneous learning based on feasible paths 13 such as abnormal or quasi-abnormal paths, and to support appropriate data placement for feasible paths 13 in the normal path.

[0109] <Fourth embodiment> A data placement support device and a data placement support method according to the present embodiment will be described. In the following description, components similar to those described in the above embodiment will be illustrated with the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0110] <Inference Phase> In the first embodiment, the variable identifier list 24 is generated based on the branch information 8 that can be obtained from the source code analysis unit 1, so shared variables between threads (between multiple functions, or between multiple access sequences) are not taken into consideration. As a result, variables shared between threads and variables that are not shared are adjacent to each other and placed in the same cache line, which leads to false sharing of the cache and unnecessary cache updates for variables that are not shared between threads. This may result in a decrease in software performance.

[0111] In response to this problem, by separating variables that are shared between threads from variables that are not shared, false sharing of caches can be prevented and degradation of software performance can be suppressed.

[0112] 16 is a diagram showing an example of the configuration of an inference device related to the data placement support device of this embodiment. As shown in FIG. 16, the inference device includes a source code analysis unit 1, a function information storage unit 2, an access sequence generation unit 3, an access sequence storage unit 4, a learned model storage unit 6, a variable order inference unit 21, a variable information storage unit 20, a thread starting point information input unit 29, a shared variable extraction unit 30, a variable order classification unit 31, and a variable order display unit 22.

[0113] An input of the function information storage unit 2 is connected to an output of the source code analysis unit 1. An input of the access sequence generation unit 3 is connected to an output of the function information storage unit 2. An input of the access sequence storage unit 4 is connected to an output of the access sequence generation unit 3. An input of the variable order inference unit 21 is connected to an output of the learned model storage unit 6. An input of the shared variable extraction unit 30 is connected to an output of the access sequence storage unit 4 and an output of the thread starting point information input unit 29. An input of the variable order classification unit 31 is connected to an output of the variable order inference unit 21 and an output of the shared variable extraction unit 30. An input of the variable information storage unit 20 is connected to an output of the source code analysis unit 1. An input of the variable order display unit 22 is connected to an output of the variable order classification unit 31 and an output of the variable information storage unit 20.

[0114] The shared variables extracted by the shared variable extraction unit 30 indicate variables shared between threads.

[0115] 17 is a diagram showing an example of a shared variable. As shown in FIG 17, a threadA function and a threadB function each indicate an independent thread.

[0116] The threadA function uses variables a and c, and the threadB function uses variables c and d. The shared variable between these threads is c.

[0117] 16 specifies the starting point of a thread. That is, the thread starting point information input unit 29 specifies multiple threads as starting points. The thread starting point information input unit 29 may specify the starting point of a thread in the form of a function, or may specify the access sequence 14 stored in the access sequence storage unit 4 as the starting point of a thread. However, the thread starting point information input unit 29 cannot specify multiple starting points of the same thread.

[0118] 16 outputs variable identifiers 9 for shared variables from multiple access sequences 14 specified by the thread starting point information input unit 29. Here, a shared variable is a variable identifier 9 that appears in common between any two threads, and does not refer only to a variable identifier 9 that appears in all threads.

[0119] The variable order classification unit 31 in FIG. 16 receives the shared variables output from the shared variable extraction unit 30, and classifies the variable identifiers 9 of the adjacent series output by the variable order inference unit 21 in FIG. 16 into variable identifiers 9 shared between threads (i.e., variable identifiers 9 corresponding to shared variables) and variable identifiers 9 not shared between threads (i.e., variable identifiers 9 not corresponding to shared variables).

[0120] Then, the variable order classification unit 31 rearranges the variable identifiers 9 in each of the classified sequences in the order in the adjacent sequence output by the variable order inference unit 21. It does not matter which of the sets of variable identifiers 9 shared between threads and the set of variable identifiers 9 not shared between threads comes first, but each set must not contain variable identifiers 9 from another set.

[0121] The variable order display unit 22 in FIG. 16 displays the order of the variable identifiers 9 in the adjacent series rearranged by the variable order classification unit 31 with the corresponding variables.

[0122] By allocating data for shared variables separately from non-shared variables in this way, it is possible to prevent software performance degradation due to false cache sharing.

[0123] <Hardware configuration of the data placement support device> 18 and 19 are diagrams illustrating schematic examples of hardware configurations when the data placement support devices shown in FIGS. 1, 9, 12, 15, and 16 are actually operated.

[0124] Note that the hardware configurations illustrated in Figures 18 and 19 may not match the numbers, etc., of the configurations illustrated in Figures 1, 9, 12, 15, and 16, but this is because the configurations illustrated in Figures 1, 9, 12, 15, and 16 represent conceptual units.

[0125] Therefore, at least the following cases can be envisaged: a configuration illustrated in Figures 1, 9, 12, 15, and 16 is composed of multiple hardware configurations illustrated in Figures 18 and 19; a configuration illustrated in Figures 1, 9, 12, 15, and 16 corresponds to a part of the hardware configuration illustrated in Figures 18 and 19; and further, a case can be envisaged in which multiple configurations illustrated in Figures 1, 9, 12, 15, and 16 are provided in one hardware configuration illustrated in Figures 18 and 19.

[0126] 18 shows a processing circuit 1102A that performs calculations and a storage device 1103 that can store information as a hardware configuration for realizing the source code analysis unit 1, function information storage unit 2, access sequence generation unit 3, access sequence storage unit 4, access sequence learning unit 5, learned model storage unit 6, variable information storage unit 20, variable order inference unit 21, variable order display unit 22, termination condition input unit 26, prohibited condition input unit 27, thread starting point information input unit 29, shared variable extraction unit 30, variable order classification unit 31, etc. in Figures 1, 9, 12, 15, and 16. This configuration is similar in all of the above embodiments.

[0127] 19 shows a processing circuit 1102B that performs calculations as a hardware configuration for realizing the source code analysis unit 1, function information storage unit 2, access sequence generation unit 3, access sequence storage unit 4, access sequence learning unit 5, learned model storage unit 6, variable information storage unit 20, variable order inference unit 21, variable order display unit 22, termination condition input unit 26, prohibited condition input unit 27, thread starting point information input unit 29, shared variable extraction unit 30, variable order classification unit 31, etc. in Figures 1, 9, 12, 15, and 16. This configuration is similar in all of the above embodiments.

[0128] The function information storage unit 2, the access sequence storage unit 4, the trained model storage unit 6, and the variable information storage unit 20 are realized by the storage device 1103 or another storage device (not shown here).

[0129] The storage device 1103 may be, for example, a memory (recording medium) including a hard disk drive (i.e., HDD), random access memory (i.e., RAM), read only memory (i.e., ROM), flash memory, volatile or non-volatile semiconductor memory such as erasable programmable read only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM), a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, or a DVD, or any recording medium to be used in the future.

[0130] The processing circuit 1102A may execute a program stored in the storage device 1103, an external CD-ROM, an external DVD-ROM, or an external flash memory, etc. That is, it may be, for example, a central processing unit (CPU), a microprocessor, a microcomputer, or a digital signal processor (DSP).

[0131] In the case where the processing circuit 1102A executes a program stored in the storage device 1103, an external CD-ROM, an external DVD-ROM, an external flash memory, or the like, the source code analysis unit 1, the access sequence generation unit 3, the access sequence learning unit 5, the variable order inference unit 21, the variable order display unit 22, the termination condition input unit 26, the prohibited condition input unit 27, the thread starting point information input unit 29, the shared variable extraction unit 30, and the variable order classification unit 31 are realized by software, firmware, or a combination of software and firmware, in which the program stored in the storage device 1103 is executed by the processing circuit 1102A. Note that the functions of the source code analysis unit 1, the access sequence generation unit 3, the access sequence learning unit 5, the variable order inference unit 21, the variable order display unit 22, the termination condition input unit 26, the prohibited condition input unit 27, the thread starting point information input unit 29, the shared variable extraction unit 30, and the variable order classification unit 31 may be realized, for example, by a plurality of processing circuits working together.

[0132] The software and firmware may be written as a program and stored in the storage device 1103. In this case, the processing circuit 1102A realizes the above-mentioned functions by reading and executing the program stored in the storage device 1103. In other words, the storage device 1103 may store a program that, when executed by the processing circuit 1102A, results in the above-mentioned functions being realized.

[0133] The processing circuitry 1102B may also be dedicated hardware, i.e., a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a combination thereof, for example.

[0134] When the processing circuit 1102B is a dedicated hardware, the source code analysis unit 1, the access sequence generation unit 3, the access sequence learning unit 5, the variable order inference unit 21, the variable order display unit 22, the termination condition input unit 26, the prohibited condition input unit 27, the thread starting point information input unit 29, the shared variable extraction unit 30, and the variable order classification unit 31 are realized by the operation of the processing circuit 1102B. Note that the functions of the source code analysis unit 1, the access sequence generation unit 3, the access sequence learning unit 5, the variable order inference unit 21, the variable order display unit 22, the termination condition input unit 26, the prohibited condition input unit 27, the thread starting point information input unit 29, the shared variable extraction unit 30, and the variable order classification unit 31 may be realized by separate circuits or by a single circuit.

[0135] The functions of the source code analysis unit 1, access sequence generation unit 3, access sequence learning unit 5, variable order inference unit 21, variable order display unit 22, termination condition input unit 26, prohibited condition input unit 27, thread starting point information input unit 29, shared variable extraction unit 30, and variable order classification unit 31 may be partly realized in a processing circuit 1102A that executes a program stored in a memory device 1103, and partly realized in a processing circuit 1102B that is dedicated hardware.

[0136] <Effects of the above-described embodiments> Next, examples of effects produced by the above-described embodiments are shown. In the following description, the effects are described based on the specific configurations shown as examples in the above-described embodiments, but may be replaced with other specific configurations shown as examples in this specification as long as the same effects are produced. In other words, for convenience, only one of the corresponding specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another corresponding specific configuration.

[0137] Furthermore, the replacement may be made across a number of embodiments, that is, configurations shown as examples in different embodiments may be combined to produce the same effect.

[0138] According to the embodiment described above, the data placement support device includes a source code analysis unit 1, an access sequence generation unit 3, an access sequence learning unit 5, a variable order inference unit 21, and a variable order display unit 22. The source code analysis unit 1 outputs variable read / write 7, branch information 8, and variable definition information 10 from the source code. The variable read / write 7 represents access to a plurality of variables in a function with a unique variable identifier 9. The branch information 8 is information about the branch of the function. The variable definition information 10 is information about the definition of the variable. The access sequence generation unit 3 generates an executable path 13, which is at least one executable processing order of the function, based on the branch information 8. Then, the access sequence generation unit 3 outputs the order of variables referenced in the executable path 13 as an access sequence 14 based on the variable read / write 7 (mainly the variable identifier 9). The access sequence learning unit 5 generates a learned model. The learned model infers the occurrence probability of a variable identifier 9 corresponding to a variable referenced in the order in the access sequence 14. The variable order inference unit 21 infers an adjacent series including variable identifiers 9 arranged in the order of highest probability of concatenation based on the trained model. The variable order display unit 22 displays the order of the variable identifiers 9 in the adjacent series with the corresponding variables based on the variable definition information 10.

[0139] Furthermore, according to the embodiment described above, the data placement support device includes a processing circuit 1102A that executes a program, and a storage device 1103 that stores the program to be executed. The processing circuit 1102A executes the program to realize the following operations.

[0140] That is, based on the source code, variable read / write 7 expressing access to multiple variables in a function with a unique variable identifier 9, branch information 8 which is information on the branching of the function, and variable definition information 10 which is information on the definition of variables are output. Then, based on the variable read / write 7 and the branch information 8, an executable path 13 which is an executable processing order of at least one function is generated, and the order of variables referenced in the executable path 13 is output as an access sequence 14. Then, a trained model is generated for inferring the occurrence probability of variable identifier 9 corresponding to variables referenced in the order in the access sequence 14. Then, based on the trained model, an adjacent sequence including variable identifiers 9 arranged in an order most likely to be connected is inferred. Then, based on the variable definition information 10, the order of variable identifiers 9 in the adjacent sequence is displayed with the corresponding variables.

[0141] Furthermore, according to the embodiment described above, the data placement support apparatus includes the processing circuit 1102B, which is dedicated hardware. The processing circuit 1102B, which is dedicated hardware, performs the following operations.

[0142] That is, the processing circuit 1102B, which is a dedicated hardware, outputs, from the source code, variable read / write 7 expressing access to multiple variables in a function with a unique variable identifier 9, branch information 8 which is information regarding function branching, and variable definition information 10 which is information regarding variable definition. Then, based on the variable read / write 7 and the branch information 8, an executable path 13 which is an executable processing order for at least one function is generated, and the order of variables referenced in the executable path 13 is output as an access sequence 14. Then, a trained model is generated for inferring the occurrence probability of variable identifier 9 corresponding to variables referenced in the order in the access sequence 14. Then, based on the trained model, an adjacent sequence including variable identifiers 9 arranged in an order most likely to be concatenated is inferred.

[0143] Based on the variable definition information 10, the order of the variable identifiers 9 in the adjacent series is displayed with the corresponding variables.

[0144] According to this configuration, by inferring an adjacent sequence in which processes are arranged in the order most likely to be connected for an access sequence that indicates the processing order of the software, and displaying variables in the order in the adjacent sequence, it is possible to improve data locality and cache utilization efficiency and suppress degradation of software performance.

[0145] Furthermore, the same effect can be achieved even if other configurations, examples of which are shown in this specification, are appropriately added to the above configuration, i.e., even if other configurations in this specification that were not mentioned as the above configuration are appropriately added.

[0146] Furthermore, according to the embodiment described above, the data placement assistance device includes a termination condition input unit 26 for specifying the maximum number of executions of a branch of a function in the branch information 8. Then, the access sequence generation unit 3 generates an executable path 13 that is executable within the maximum number of executions, based on the branch information 8. With such a configuration, learning for improving data locality can be completed in a finite time.

[0147] Furthermore, according to the embodiment described above, the data placement assistance device includes a prohibited condition input unit 27 for deleting specific operations of a function in the branch information 8. Then, the access sequence generation unit 3 generates an executable path 13 excluding the operations deleted by the prohibited condition input unit 27, based on the branch information 8. Such a configuration makes it possible to prevent erroneous learning based on an executable path 13 such as an abnormal or quasi-abnormal system, and to assist in appropriate data placement for the executable path 13 of a normal system.

[0148] According to the embodiment described above, the data placement support device includes a thread starting point information input unit 29 for specifying a plurality of threads, a shared variable extraction unit 30, and a variable order classification unit 31. The shared variable extraction unit 30 extracts a variable identifier 9 corresponding to a shared variable that is a variable shared among a plurality of specified threads. The variable order classification unit 31 classifies the variable identifiers 9 in the adjacent series into those corresponding to shared variables and those not corresponding to shared variables. Then, the variable order classification unit 31 rearranges the variable identifiers 9 in the adjacent series in each classification. Then, the variable order display unit 22 displays the order of the variable identifiers 9 in the adjacent series rearranged by the variable order classification unit 31 with the corresponding variables. According to such a configuration, by arranging data by separating the shared variables from the non-shared variables in this way, it is possible to suppress a decrease in software performance due to false sharing of a cache.

[0149] According to the embodiment described above, in the data placement support method, variable read / write 7 expressing access to multiple variables in a function with a unique variable identifier 9, branch information 8 which is information on the branching of the function, and variable definition information 10 which is information on the definition of the variables are output from the source code. Then, based on the variable read / write 7 and the branch information 8, an executable path 13 which is an executable processing order of at least one function is generated, and the order of variables referenced in the executable path 13 is output as an access sequence 14. Then, a trained model is generated for inferring the occurrence probability of variable identifier 9 corresponding to variables referenced in the order in the access sequence 14. Then, based on the trained model, an adjacent sequence including variable identifiers 9 arranged in an order with the highest probability of concatenation is inferred. Then, based on the variable definition information 10, the order of variable identifiers 9 in the adjacent sequence is displayed with the corresponding variables.

[0150] According to this configuration, by inferring an adjacent sequence in which processes are arranged in the order most likely to be connected for an access sequence that indicates the processing order of the software, and displaying variables in the order in the adjacent sequence, it is possible to improve data locality and cache utilization efficiency and suppress degradation of software performance.

[0151] Unless otherwise specified, the order in which the processes are performed may be changed.

[0152] Furthermore, even if other configurations, examples of which are shown in this specification, are appropriately added to the above configuration, i.e., even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be produced.

[0153] <Modifications of the above-described embodiments> In the embodiments described above, the dimensions, shapes, relative positional relationships, and implementation conditions of each component may be described, but these are merely examples in all aspects and are not limiting.

[0154] Therefore, countless modifications and equivalents not shown as examples are assumed within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0155] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may be provided.

[0156] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0157] Furthermore, each of the components described in the above embodiments is envisioned as either software or firmware, or as corresponding hardware, and as software, is referred to as, for example, a "unit," and as hardware, is referred to as, for example, a "processing circuit" (circuitry).

[0158] Furthermore, the technology disclosed in this specification may also be in a form in which each component is distributed across multiple devices, that is, in a form such as a system that is a combination of multiple devices.

[0159] Various aspects of the present disclosure are summarized below as appendices.

[0160] (Appendix 1) a source code analysis unit for outputting, from a source code, variable read / write information representing access to a plurality of variables in a function by a unique variable identifier, branch information which is information regarding a branch of the function, and variable definition information which is information regarding the definition of the variables; an access sequence generation unit for generating an executable path, which is an executable processing sequence of at least one of the functions, based on the branch information, and outputting an order of the variables referenced in the executable path as an access sequence based on the variable reads and writes; an access sequence learning unit for generating a trained model for inferring an occurrence probability of the variable identifier corresponding to the variable referenced in the order in the access sequence; a variable order inference unit for inferring an adjacent sequence including the variable identifiers arranged in an order that is most likely to be connected based on the trained model; a variable order display unit for displaying an order of the variable identifiers in the adjacent series by the corresponding variables based on the variable definition information, Data placement support device.

[0161] (Appendix 2) 2. A data placement support device according to claim 1, a termination condition input unit for specifying a maximum number of times a branch of the function is to be executed in the branch information; the access sequence generation unit generates the feasible path that can be executed within the maximum number of executions based on the branch information. Data placement support device.

[0162] (Appendix 3) 3. The data placement support device according to claim 1, a prohibition condition input unit for deleting a specific process of the function in the branch information, the access sequence generation unit generates the executable path excluding the process deleted by the prohibited condition input unit, based on the branch information. Data placement support device.

[0163] (Appendix 4) A data placement support device according to any one of claims 1 to 3, a thread starting point information input section for specifying a plurality of threads; a shared variable extraction unit for extracting a variable identifier corresponding to a shared variable that is a variable shared among a specified number of threads; a variable order sorting unit for sorting the variable identifiers in the adjacent series into those corresponding to the shared variables and those not corresponding to the shared variables, and for rearranging the variable identifiers in each sorting in the order of the variable identifiers in the adjacent series; the variable order display unit displays the order of the variable identifiers in the adjacent series sorted by the variable order classification unit, by the corresponding variables. Data placement support device.

[0164] (Appendix 5) outputting, from the source code, variable read / write information representing access to a plurality of variables in a function by a unique variable identifier, branch information which is information regarding the branching of the function, and variable definition information which is information regarding the definition of the variables; generating an executable path, which is an executable processing sequence of at least one of the functions, based on the variable reads and writes and the branch information, and outputting an order of the variables referenced in the executable path as an access sequence; generating a trained model for inferring the occurrence probability of the variable identifier corresponding to the variable referenced in the order in the access sequence; Inferring an adjacent sequence including the variable identifiers arranged in an order of most likely concatenation based on the trained model; displaying an order of the variable identifiers in the adjacent series with the corresponding variables based on the variable definition information; A method for supporting data placement. [Explanation of symbols]

[0165] 1 source code analysis unit, 2 function information storage unit, 3 access sequence generation unit, 4 access sequence storage unit, 5 access sequence learning unit, 6 learned model storage unit, 7 variable reading and writing, 8 branch information, 9 variable identifier, 10 variable definition information, 11 processing number, 12 branch destination processing number, 13 executable path, 14 access sequence, 15 reference sequence, 16 reference sequence, 20 variable information storage unit, 21 variable order inference unit, 22 variable order display unit, 24 variable identifier list, 25 termination condition, 26 termination condition input unit, 27 prohibited condition input unit, 29 thread starting point information input unit, 30 shared variable extraction unit, 31 variable order classification unit, 1102A processing circuit, 1102B processing circuit, 1103 storage device.

Claims

1. a source code analysis unit for outputting, from a source code, variable read / write information representing access to a plurality of variables in a function by a unique variable identifier, branch information which is information regarding a branch of the function, and variable definition information which is information regarding the definition of the variables; an access sequence generation unit for generating an executable path, which is an executable processing sequence of at least one of the functions, based on the branch information, and outputting an order of the variables referenced in the executable path as an access sequence based on the variable reads and writes; an access sequence learning unit for generating a trained model for inferring an occurrence probability of the variable identifier corresponding to the variable referenced in the order in the access sequence; a variable order inference unit for inferring an adjacent sequence including the variable identifiers arranged in an order that is most likely to be connected based on the trained model; a variable order display unit for displaying an order of the variable identifiers in the adjacent series by the corresponding variables based on the variable definition information, Data placement support device.

2. 2. The data placement support device according to claim 1, a termination condition input unit for specifying a maximum number of times a branch of the function is to be executed in the branch information; the access sequence generation unit generates the feasible path that can be executed within the maximum number of executions based on the branch information. Data placement support device.

3. 3. The data placement support device according to claim 1, a prohibition condition input unit for deleting a specific process of the function in the branch information, the access sequence generation unit generates the executable path excluding the process deleted by the prohibited condition input unit, based on the branch information. Data placement support device.

4. 3. The data placement support device according to claim 1, a thread starting point information input section for specifying a plurality of threads; a shared variable extraction unit for extracting a variable identifier corresponding to a shared variable that is a variable shared among a specified number of threads; a variable order sorting unit for sorting the variable identifiers in the adjacent series into those corresponding to the shared variables and those not corresponding to the shared variables, and for rearranging the variable identifiers in each sorting in an order according to the variable identifiers in the adjacent series; the variable order display unit displays the order of the variable identifiers in the adjacent series sorted by the variable order classification unit, by the corresponding variables. Data placement support device.

5. outputting, from the source code, variable read / write information representing access to a plurality of variables in a function by a unique variable identifier, branch information which is information regarding the branching of the function, and variable definition information which is information regarding the definition of the variables; generating an executable path, which is an executable processing sequence of at least one of the functions, based on the variable reads and writes and the branch information, and outputting an order of the variables referenced in the executable path as an access sequence; generating a trained model for inferring the occurrence probability of the variable identifier corresponding to the variable referenced in the order in the access sequence; Inferring an adjacent sequence including the variable identifiers arranged in an order of most likely concatenation based on the trained model; displaying an order of the variable identifiers in the adjacent series with the corresponding variables based on the variable definition information; A method for supporting data placement.

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