Semiconductor memory device

Abstract

To provide a semiconductor memory device that suppresses both accumulation of erroneous writes in non-selected sub-blocks and occurrences of SSIs.SOLUTION: In a semiconductor memory device having a memory cell array including a plurality of bit lines, a source line, a plurality of NAND strings connecting the plurality of bit lines and the source line, first and second sub-blocks sharing the plurality of bit lines, the plurality of NAND strings, and the source line as a series current path with each other, a first word line group included in the first sub-block, a second word line group included in the second sub-block, and a dummy word line located between the first sub-block and the second sub-block, and a control circuit capable of applying a predetermined voltage to the first word line group, the second word line group, and the dummy word line, a voltage higher than a voltage applied to the non-selected word lines belonging to the first word line group and the second word line group, is added to the dummy word line, when a specific word line belonging to the first word line group is selected to perform write operations.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices such as 3D-NAND, the number of layers of word lines (groups) that form the gates of memory cell transistors is increasing. Accordingly, the block size of the semiconductor memory device is increasing. This means that the load (e.g., power consumption, system block ratio, etc.) on users of the semiconductor memory device is increasing.

[0003] Therefore, there is an increasing demand for a sub-block mode (SBM) that divides a single block and handles it independently. In the sub-block mode, the sub-block to which the word line that executes the program belongs is called the "selected sub-block (SB_sel)" and the sub-block to which the word line that executes the program does not belong is called the "unselected sub-block (SB_usel)". The selected sub-block and the unselected sub-block can be managed independently.

[0004] In the sub-block mode, when a program is executed on a word line in a selected sub-block, a voltage V PASS_usel It is known that a write error (Disturb) occurs due to the above. In other words, if erasing and writing to a selected sub-block are repeated while retaining data in an unselected sub-block, the voltage V PASS_usel This causes erroneous writing to accumulate (accumulate electric charge). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP2012-252775A [Patent Document 2] Patent No. 5951253 Summary of the Invention [Problem to be solved by the invention]

[0006] By applying a voltage to the word lines belonging to the unselected sub-blocks that is lower than the voltage applied to the word lines belonging to the selected sub-block other than the word lines related to programming, it is possible to suppress erroneous programming to the unselected sub-blocks. On the other hand, if the potential difference between the voltage applied to the word lines related to programming in the selected sub-block and the voltage applied to the word lines belonging to the unselected sub-blocks is large, a phenomenon in which electrons move from the unselected block to the selected block (Source Side Injection: SSI) occurs.

[0007] As described above, in conventional semiconductor memory devices, when programming a selected sub-block while holding data in the unselected sub-block in the sub-block mode, there is a problem that erroneous writing to the unselected sub-block accumulates. Furthermore, when this problem is solved by controlling the voltage applied to the word lines belonging to the unselected sub-block, there is a problem that SSI occurs. The embodiment of the present invention provides a semiconductor memory device that can suppress the accumulation of erroneous writing to the unselected sub-block in the sub-block mode while also suppressing the occurrence of SSI. [Means for solving the problem]

[0008] An embodiment of the present invention is a semiconductor memory device including a memory cell array including a plurality of bit lines, a source line, a plurality of NAND strings each having a plurality of memory cell transistors connected in series and connecting the plurality of bit lines and the source line, a first sub-block and a second sub-block different from the first sub-block, the plurality of bit lines, the plurality of NAND strings, and the source line sharing a series current path with each other, a first word line group included in the first sub-block, a second word line group included in the second sub-block, and a dummy word line located between the first sub-block and the second sub-block, and a control circuit capable of applying a predetermined voltage to the first word line group, the second word line group, and the dummy word line. When a specific word line belonging to the first word line group is selected to perform a write operation, the control circuit applies a voltage to the dummy word line that is higher than the voltage applied to the unselected word lines belonging to the first word line group and the second word line group. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a hardware configuration of a semiconductor memory device according to a first embodiment of the present invention. [Diagram 2] 1 is a circuit diagram showing a configuration of a block in a memory cell array according to a first embodiment of the present invention. [Diagram 3] 5 is a flowchart showing an example of the operation of the semiconductor memory device according to the first embodiment of the present invention. [Figure 4] 5A and 5B are diagrams showing examples of gate potential levels during writing in the semiconductor memory device according to the first embodiment of the present invention. [Diagram 5] 11A and 11B are diagrams illustrating an example of bit count numbers for explaining how erroneous writing occurs in a non-selected sub-block in a semiconductor memory device; [Figure 6] 1A to 1C are diagrams illustrating examples of gate potential levels during writing, illustrating how erroneous writing to unselected sub-blocks is suppressed in the semiconductor memory device according to the first embodiment of the present invention. [Figure 7]1A and 1B are diagrams showing examples of bit count numbers illustrating how erroneous writing to unselected sub-blocks is suppressed in the semiconductor memory device according to the first embodiment of the present invention. [Figure 8] 5A to 5C are diagrams illustrating an example of gate potential levels during writing, illustrating how SSI is suppressed in the semiconductor memory device according to the first embodiment of the present invention. [Figure 9] 5A and 5B are diagrams illustrating an example of a bit count number for explaining how SSI is suppressed in the semiconductor memory device according to the first embodiment of the present invention. [Figure 10] 10 is a flowchart showing an example of an erase operation of the semiconductor memory device according to the second embodiment of the present invention. [Figure 11] 13 is a diagram showing an example of a bit count number for explaining the operation of the semiconductor memory device according to the second embodiment of the present invention. FIG. [Figure 12] 13 is a diagram showing an example of a bit count number for explaining the operation of the semiconductor memory device according to the second embodiment of the present invention. FIG. [Figure 13] 13 is a diagram illustrating an example of the gate potential level during erasure in the semiconductor memory device according to the second embodiment of the present invention. FIG. [Figure 14] FIG. 11 is a diagram showing an example of the bit count number during erasure in the semiconductor memory device according to the second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (First embodiment) Hereinafter, the embodiments will be described in detail with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and duplicated descriptions will be omitted. Each of the embodiments described below is an example of an apparatus or method for embodying the technical idea of ​​the embodiment, and the technical idea of ​​the embodiment does not specify the material, shape, structure, arrangement, etc. of the components as described below. The technical idea of ​​the embodiment may be modified in various ways within the scope of the claims.

[0011] Fig. 1 is a block diagram showing a hardware configuration of a semiconductor memory device according to the first embodiment. Fig. 2 is a circuit diagram showing a configuration of a block in a memory cell array according to the first embodiment. The semiconductor memory device 1 shown in Figs. 1 and 2 is an example of a three-dimensional stacked NAND flash memory in which memory cell transistors are stacked three-dimensionally on a semiconductor substrate.

[0012] As shown in FIG. 1, the semiconductor memory device 1 includes a memory core 10 and a peripheral circuit 20.

[0013] The memory core 10 is a storage medium in the semiconductor memory device 1. The memory core 10 includes a memory cell array 11, a row decoder 12, and a sense amplifier 13.

[0014] The memory cell array 11 is a collection of memory cell transistors and includes a plurality of blocks BLK (BLK0, BLK1, . . . ).

[0015] The block BLK includes a plurality of string units SU (string units SU0 to SU3 in the example of FIG. 1). The string units SU are a set of NAND strings NS in which a plurality of memory cell transistors are connected in series. The block BLK is, for example, a data erasure unit. In other words, data held in the memory cell transistors included in the block BLK can be erased all at once.

[0016] In the semiconductor memory device 1 of this embodiment, a block BLK is divided into a plurality of sub-blocks SBLK. Each of the sub-blocks SBLK can be erased independently. As shown in FIG. 1, each NAND string NS in the block BLK is divided according to the number of sub-blocks SBLK. The divided NAND strings NS are included in different sub-blocks SBLK. In the example shown in FIG. 1, the block BLK includes two sub-blocks SBLK. In the following description, the two sub-blocks SBLK are referred to as an "Upper sub-block USBLK" and a "Lower sub-block LSBLK."

[0017] 1, the block BLK0 includes an upper sub-block USBLK0 and a lower sub-block LSBLK0. The block BLK1 includes an upper sub-block USBLK1 and a lower sub-block LSBLK1. Note that the number of blocks BLK in the memory cell array 11, the number of sub-blocks SBLK, the number of string units SU in the block BLK, and the number of NAND strings NS in the string unit SU are arbitrary.

[0018] The row decoder 12 is a circuit that decodes a row address received from an external controller (not shown). The row decoder 12 has a function of selecting wiring in the row direction of the memory cell array 11 based on the decoded result. More specifically, the row decoder 12 applies voltages to various wirings (word line(s), dummy word line(s) and select gate line(s)) for selecting the row direction.

[0019] The sense amplifier 13 is a circuit that detects data from the memory cell array 11 and applies a predetermined voltage to the memory cell array 11. When reading data, the sense amplifier 13 has a function of sensing data read from any block BLK via a bit line. When writing data, the sense amplifier 13 has a function of applying a voltage according to the write data to the memory cell array 11 via the bit line.

[0020] The peripheral circuit unit 20 includes a sequencer 21 and a voltage generating circuit 22 .

[0021] The sequencer 21 is a control circuit that controls the overall operation of the semiconductor memory device 1. The sequencer 21 has a function of controlling the voltage generation circuit 22, the row decoder 12, the sense amplifier 13, etc. during a write operation, a read operation, and an erase operation.

[0022] The voltage generating circuit 22 generates voltages used in the write operation, read operation, and erase operation, and supplies the generated voltages to the memory cell array 11, the row decoder 12, the sense amplifier 13, etc.

[0023] Next, the configuration of the memory cell array 11 will be described in detail with reference to Fig. 2. Fig. 2 shows an example of a circuit of the string unit SU0 of the block BLK0. The other blocks BLK and string units SU have the same configuration.

[0024] As shown in Fig. 2, the string unit SU0 of the block BLK0 includes a plurality of NAND strings NS. In the example shown in Fig. 2, the NAND string NS includes 160 memory cell transistors MC0 to MC159, 10 dummy memory cell transistors MCDD0 to MCDD3, MCDU, MCDL, and MCDS0 to MCDS3, and 13 select transistors STT1a to STT1c, ST1a to ST1c, ST2a to ST2c, and STB2a to STB2d. In the following description, when there is no limitation on any of the memory cell transistors MC0 to MC159, it is referred to as a memory cell transistor MC.

[0025] Similarly, when any of the dummy memory cell transistors MCDD0 to MCDD3 is not limited, it is written as a dummy memory cell transistor MCDD. When any of the dummy memory cell transistors MCDS0 to MCDS3 is not limited, it is written as a dummy memory cell transistor MCDS. When any of the dummy memory cell transistors MCDD, MCDU, MCDL, and MCDS is not limited, it is written as a dummy memory cell transistor MCD.

[0026] When any of the select transistors STT1a to STT1c is not limited, it is written as STT1. When any of the select transistors ST1a to ST1c is not limited, it is written as ST1. When any of the select transistors ST2a to ST2c is not limited, it is written as ST2. When any of the select transistors STB2a to STB2d is not limited, it is written as STB2.

[0027] The memory cell transistor MC and the dummy memory cell transistor MCD each include a control gate and a charge storage layer. The memory cell transistor MC can retain data in a non-volatile manner. The dummy memory cell transistor MCD has the same configuration as the memory cell transistor MC, but is used as a dummy and is not used to retain data.

[0028] The memory cell transistors MC and the dummy memory cell transistors MCD may be of a MONOS type that uses an insulating film for the charge storage layer, or of an FG type that uses a conductive layer for the charge storage layer. In the following, the present embodiment will be described using the MONOS type as an example. The number of memory cell transistors MC and dummy memory cell transistors MCD in the NAND string NS is arbitrary. The dummy memory cell transistors MCD do not need to be provided.

[0029] The selection transistors ST1 and ST2 are used to select the string unit SU (NAND string NS). The selection transistors STT1 and STB2 are used to select the string unit SU in the same manner as the selection transistors ST1 and ST2 during write and read operations. The selection transistors STT1 and STB2 are used to generate a GIDL (Gate Induced Drain Leakage) current during an erase operation. The number of selection transistors ST1, ST2, STT1, and STB2 is arbitrary, and may be one or more of each.

[0030] 2, in the NAND string NS, the current paths of the memory cell transistors MC, the dummy memory cell transistors MCD, and the selection transistors ST1, ST2, STT1, and STB2 are connected in series. For example, the current paths of the selection transistors STB2a-STB2d and ST2a-ST2c, the dummy memory cell transistors MCDS0-MCDS3, the memory cell transistors MC0-MC79, the dummy memory cell transistors MCDL and MCDU, the memory cell transistors MC80-MC159, the dummy memory cell transistors MCDD3-MCDD0, and the selection transistors ST1c-ST1a and STT1c-STT1a are connected in series in this order.

[0031] In this embodiment, the NAND string NS includes a lower string NSL corresponding to the lower sub-block LBLK and an upper string NSU corresponding to the upper sub-block USBLK. In the example shown in Fig. 2, the lower string NSL includes memory cell transistors MC0 to MC79, dummy memory cell transistors MCDS0 to MCDS3 and MCDL, and selection transistors ST2a to ST2c and STB2a to STB2d. The upper string NSU includes memory cell transistors MC80 to MC159, dummy memory cell transistors MCDD0 to MCDD3 and MCDU, and selection transistors ST1a to ST1c and STT1a to STT1c.

[0032] That is, the erase operation of the Lower sub-block LSBLK makes it possible to erase data from the memory cell transistors MC0 to MC79 in the block BLK, and the erase operation of the Upper sub-block USBLK makes it possible to erase data from the memory cell transistors MC80 to MC159 in the block BLK.

[0033] The control gates of the memory cell transistors MC0 to MC159 in the block BLK are commonly connected to the word lines WL0 to WL159, respectively. The memory cell transistors MC0 of the multiple NAND strings NS included in the string units SU0 to SU3 in the block BLK0 are commonly connected to the word line WL0. The same is true for the other memory cell transistors MC.

[0034] Furthermore, the control gates of the dummy memory cell transistors MCDD0-MCDD3, MCDU, MCDL, and MCDS0-MCDS3 in the block BLK are commonly connected to dummy word lines WLDD0-WLDD3, WLDU, WLDL, and WLDS0-WLDS3, respectively. In the following description, when any of the word lines WL0-WL159 is not specified, it is referred to as a word line WL. When any of the dummy word lines WLDD0-WLDD3, WLDU, WLDL, and WLDS0-WLDS3 is not specified, it is referred to as a dummy word line WLD.

[0035] The word lines WL0 to WL159 and the dummy word lines WLDD0 to WLDD3, WLDU, WLDL, and WLDS0 to WLDS3 are connected to a row decoder 12 and are each controlled independently.

[0036] The gates of the multiple selection transistors STT1a-STT1c and ST1a-ST1c in the string unit SU are each commonly connected to one selection gate line corresponding to the string unit SU. That is, the gates of the multiple selection transistors STT1a-STT1c in the string unit SU0 are each commonly connected to the selection gate lines SGDT0a-SGDT0c. The gates of the multiple selection transistors ST1a-ST1c in the string unit SU0 are each commonly connected to the selection gate lines SGD0a-SGD0c. And, the selection gate lines SGDT0a-SGDT0c are commonly connected to the selection gate line SGDT0. The selection gate lines SGD0a-SGD0c are commonly connected to the selection gate line SGD0.

[0037] Similarly, the gates of the multiple selection transistors STT1a-STT1c in the string unit SU1 (not shown) are commonly connected to the selection gate lines SGDT1a-SGDT1c, respectively. The gates of the multiple selection transistors ST1a-ST1c in the string unit SU1 are commonly connected to the selection gate lines SGD1a-SGD1c, respectively. The selection gate lines SGDT1a-SGDT1c are commonly connected to the selection gate line SGDT1. The selection gate lines SGD1a-SGD1c are commonly connected to the selection gate line SGD1. Hereinafter, when the wiring equivalent to the selection gate lines SGDT0 and SGD0 of the string unit SU0 is not limited to the string unit SU, it will be referred to as the selection gate lines SGDT and SGD, respectively.

[0038] The select gate lines SGDT0 and SGD0 are connected to the row decoder 12 and are each controlled independently. The same applies to the other string units SU1 to SU3. Therefore, the row decoder 12 can apply different voltages to the select gate lines SGDT and SGD of each string unit SU. Note that, for example, the select gate lines SGDT0a to SGDT0c and SGD0a to SGD0c of the string unit SU0 may each be controlled independently by the row decoder 12. The same applies to the other string units SU.

[0039] The gates of the multiple selection transistors STB2a to STB2d in the block BLK are commonly connected to one selection gate line SGSB. Similarly, the gates of the multiple selection transistors ST2a to ST2c in the block BLK are commonly connected to one selection gate line SGS. That is, the gates of the multiple selection transistors STB2a to STB2d in the string unit SU0 are commonly connected to the selection gate lines SGSB0a to SGSB0d, respectively. The gates of the multiple selection transistors ST2a to ST2c in the string unit SU0 are commonly connected to the selection gate lines SGS0a to SGS0c, respectively. Then, the selection gate lines SGSB0a to SGSB0d are commonly connected to the selection gate line SGSB. The selection gate lines SGS0a to SGS0c are commonly connected to the selection gate line SGS. The same applies to the other string units SU. Note that different selection gate lines SGSB and SGS may be provided for each string unit SU.

[0040] The select gate lines SGSB and SGS are connected to the row decoder 12 and are controlled independently. Therefore, the row decoder 12 can apply different voltages to the select gate lines SGSB and SGS. For example, the select gate lines SGSB0a-SGSB0d and SGS0a-SGS0c of the string unit SU0 may be controlled independently by the row decoder 12. The same applies to the other string units SU.

[0041] The drains of the select transistors STT1a of the multiple NAND strings NS in the string unit SU are connected to different bit lines BL0 to BLn (n is an integer equal to or greater than 1). Hereinafter, the bit lines BL0 to BLn will be referred to as bit lines BL unless otherwise specified. Each bit line BL is connected to a sense amplifier 13 and can be controlled independently.

[0042] The sources of the multiple selection transistors STB2a in the block BLK are commonly connected to a source line SL. That is, the NAND string NS connects the bit line BL and the source line SL.

[0043] That is, a string unit SU is a collection of NAND strings NS connected to different bit lines BL and the same select gate lines SGDT and SGD. A block BLK is a collection of multiple string units SU that share a word line WL. The memory cell array 11 is a collection of multiple blocks BLK that share a bit line BL.

[0044] In the semiconductor memory device of this embodiment, the sub-blocks share a plurality of bit lines BL, a plurality of NAND strings NS, and a source line SL as a series current path. That is, the Lower sub-block LBLK and the Upper sub-block USBLK share the bit lines BL, the NAND strings NS, and the source line SL.

[0045] A write operation and a read operation are performed collectively on a plurality of memory cell transistors MC connected to any word line WL in any string unit SU. Hereinafter, a group of memory cell transistors MC selected collectively during a write operation and a read operation is called a "cell unit CU." A collection of 1 bit of data written to or read from one cell unit CU is called a "page."

[0046] (Operation of the first embodiment) Next, the operation of the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 3 to 9. FIG. 3 is a flowchart showing an example of the operation of the semiconductor memory device according to the first embodiment. FIG. 4 is a diagram showing an example of the gate potential level at the time of writing in the semiconductor memory device according to the first embodiment. FIG. 5 is a diagram showing an example of the bit count number explaining the state of erroneous writing to the unselected subblock in the semiconductor memory device according to the first embodiment of the present invention. FIG. 6 is a diagram showing an example of the gate potential level at the time of writing explaining the state of suppressing erroneous writing to the unselected subblock in the semiconductor memory device according to the first embodiment of the present invention. FIG. 7 is a diagram showing an example of the bit count number explaining the state of suppressing erroneous writing to the unselected subblock in the semiconductor memory device according to the first embodiment of the present invention. FIG. 8 is a diagram showing an example of the gate potential level at the time of writing explaining the state of suppressing SSI in the semiconductor memory device according to the first embodiment of the present invention. FIG. 9 is a diagram showing an example of the bit count number explaining the state of suppressing SSI in the semiconductor memory device according to the first embodiment of the present invention.

[0047] When the sequencer 21 receives a program command, it instructs the row decoder 12 and the voltage generating circuit 22 to program a predetermined address (S100).

[0048] The voltage generating circuit 22 generates a program voltage V PGM , the selected subblock voltage V PASS_sel , non-selected sub-block voltage V PASS_usel , dummy word line voltage V PASS_DMY is generated (S110).

[0049] Program voltage V PGM is the voltage applied to the word line WL corresponding to the program command. Program voltage V PGM is exemplified as 20V.

[0050] Selected subblock voltage V PASS_sel is the voltage applied to the word lines WL in the selected sub-block that are not related to the program command.PASS_sel A voltage (for example, about 10 V) is selected that turns on the memory cell transistor and does not increase the threshold voltage.

[0051] Non-selected sub-block voltage V PASS_usel is the voltage applied to the word lines WL in the unselected sub-block. Unselected sub-block voltage V PASS_usel A voltage that does not increase the threshold voltage is selected.

[0052] Dummy word line voltage V PASS_DMY is a voltage applied to the dummy word line WLD (dummy word line WLDU, dummy word line WLDL in the example shown in FIG. 2) located between the selected sub-block SB_sel and the unselected sub-block SB_usel. The dummy word line voltage V PASS_DMY is usually the selected sub-block voltage V PASS_sel A voltage lower than

[0053] Here, as shown in FIG. 4, the unselected subblock voltage V PASS_usel is the selected subblock voltage V PASS_sel As shown in FIG. 5, when erasing and writing are repeated on the selected sub-block SB_sel while holding the data of the unselected sub-block SB_usel ("WE_cycle" in FIG. 5), the unselected sub-block voltage V PASS_usel This causes erroneous writing and accumulation of electric charges. Figure 5 shows how the gate voltage rises during reading in the unselected sub-block SB_usel ("(a)" in Figure 5). This reduces the read reliability of the data stored in the unselected sub-block SB_usel.

[0054] Therefore, the voltage generating circuit 22 generates the unselected sub-block voltage V PASS_usel Select the sub-block voltage V PASS_sel As a result, the unselected sub-block voltage V PASS_uselIt is possible to suppress erroneous writing due to the above-mentioned problem. Fig. 7 shows how the rise in gate voltage during reading in the unselected sub-block SB_usel is suppressed ("(c)" in Fig. 7).

[0055] On the other hand, as shown in FIG. 6, the unselected subblock voltage V PASS_usel Select the sub-block voltage V PASS_sel If you set it to a voltage lower than the program voltage V PGM and the unselected subblock voltage V PASS_usel This potential difference may cause a phenomenon in which electrons in the unselected sub-block SB_usel rush into the selected sub-block SB_sel (Source Side Injection: SSI), as shown in FIG. 6(d), causing excess electrons to be unintentionally injected into the selected sub-block SB_sel.

[0056] When electrons in the unselected sub-block SB_usel are injected into the selected sub-block SB_sel by SSI, the gate voltage in the selected sub-block SB_sel during reading increases, as shown in (e) of Fig. 7. In other words, the overlapping of peaks in the distribution of bit counts in the selected sub-block SB_sel increases, causing a deterioration in the distribution of writes to the selected sub-block SB_sel.

[0057] Therefore, the voltage generating circuit 22 generates the dummy word line voltage V PASS_DMY , the selected sub-block voltage V PASS_sel Higher than program voltage V PGM By setting the voltage configuration in this way, electrons in the unselected sub-blocks SB_usel are captured by the dummy word lines WLD, making it possible to suppress SSI ("(g)" in FIG. 8).

[0058] As a result, as shown in (h) of Fig. 9, the gate voltage of the dummy word line WLD rises during a read, but the rise in the gate voltage in the selected sub-block SB_sel during a read is suppressed as shown in (i) of Fig. 9. That is, the overlapping of the peaks of the bit count distribution in the selected sub-block SB_sel is suppressed, and the deterioration of the write distribution in the selected sub-block SB_sel can be suppressed.

[0059] The row decoder 12 receives the program voltage V PGM , the selected subblock voltage V PASS_sel , non-selected sub-block voltage V PASS_usel , dummy word line voltage V PASS_DMY is applied to the memory cell array 11 (S120).

[0060] In this way, in the semiconductor memory device according to the first embodiment, the unselected sub-block voltage V PASS_usel In addition, according to the semiconductor memory device according to the first embodiment, the dummy word line voltage V PASS_DMY is set higher than the voltage applied to the surrounding word lines WL, it is possible to suppress SSI to the selected sub-block SB_sel and prevent deterioration of the write distribution.

[0061] Second embodiment Next, the semiconductor memory device according to the second embodiment will be described in detail. This embodiment relates to an erase operation of the dummy word line WLD in the semiconductor memory device according to the first embodiment. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and duplicated descriptions are omitted. FIG. 10 is a flowchart showing an example of an erase operation of the semiconductor memory device according to the second embodiment. FIG. 11 is a diagram showing an example of a bit count number explaining the operation of the semiconductor memory device according to the second embodiment. FIG. 12 is a diagram showing an example of a bit count number explaining the operation of the semiconductor memory device according to the second embodiment. FIG. 13 is a diagram showing an example of the gate potential level during erase in the semiconductor memory device according to the second embodiment. FIG. 14 is a diagram showing an example of a bit count number during erase in the semiconductor memory device according to the second embodiment.

[0062] In the semiconductor memory device according to the first embodiment, a dummy word line voltage V PASS_DMY By setting the voltage applied to the dummy word line WL higher than that applied to the surrounding word lines WL, the SSI to the selected sub-block SB_sel is suppressed. However, as a result of the dummy word line WLD absorbing electrons from the unselected sub-block SB_usel, the gate voltage of the dummy word line WLD during read increases, and the effect of preventing the deterioration of the write distribution is reduced.

[0063] Therefore, in the semiconductor memory device of this embodiment, when erasing the selected sub-block SB_sel, the dummy word line WLD is also erased. More specifically, when erasing the selected sub-block SB_sel, the threshold value of the dummy word line WLD is read, and when the count number of error bits (Fail Bit Count) becomes equal to or greater than a certain value, the dummy word line WLD is erased.

[0064] The sequencer 21 executes a read process for the dummy word line WLD (in the example shown in FIG. 2, the dummy word line WLDU and the dummy word line WLDL) (S200). The sense amplifier 13 reads data corresponding to the dummy word line WLDU and the dummy word line WLDL based on an instruction signal from the sequencer 21.

[0065] The sequencer 21 determines whether the count number of error bits in the dummy word line WLD exceeds a predetermined threshold value (S210). Figure 11 shows an example of the bit count number of the dummy word line WLD. When electrons are accumulated in the dummy word line WLD, the distribution of the bit count number shifts to the high potential side. As a result, the count number of error bits increases, and the bit count number includes a certain number of error bits or more (shaded area in Figure 11).

[0066] If the number of error bits in the dummy word line WLD does not exceed the predetermined threshold value (No in S210), the sequencer 21 executes erasing of the selected sub-block SB_sel (S220).

[0067] If the number of error bits in the dummy word line WLD exceeds a predetermined threshold (Yes in S210), the sequencer 21 executes an erase process for the selected sub-block SB_sel (S230). Furthermore, the sequencer 21 executes an erase process for the dummy word line WLDU and the dummy word line WLDL (S240). Fig. 12 shows a state where the erase process for the dummy word line WLD (the dummy word line WLDU and the dummy word line WLDL) is performed. When the erase process for the dummy word line WLD is performed, the distribution of the bit count number shifts to the low potential side.

[0068] 13 shows the gate potential after the erase process of the selected sub-block SB_sel is executed. The gate potential of the selected sub-block SB_sel is V ERASE The gate potential of the dummy word line WLD is also reduced to V ERASE_DMYOn the other hand, the gate potential V ERASE_usel is maintained at a high potential.

[0069] The sequencer 21 continues the execution of the selected sub-block SB_sel based on the received program command (S250).

[0070] By the above process, the erase process of the dummy word line WLD is also executed at the same time as the erase process of the selected sub-block SB_sel is executed ("(k)" in FIG. 14). As a result, the damaged dummy word line WLD, which is a sacrificial layer, can be restored.

[0071] The embodiments are illustrative and the scope of the invention is not limited thereto. [Explanation of symbols]

[0072] 1...Semiconductor memory device 10…Memory core 11...Memory cell array 12...Row decoder 13...Sense amplifier 20...Peripheral circuit 21...Sequencer 22...Voltage generation circuit BLK, BLK0, BLK1...block SU, SU0~SU3...String unit NS...NAND string NSU…Upper string NSL…Lower string SBLK...Sub-block SB_sel...Selection sub-block SB_usel: Unselected sub-block USBLK…Upper sub-block LSBLK...Lower subblock MC, MC0 to MC159...Memory cell transistors MCD, MCDD, MCDD0 to MCDD3, MCDU, MCDL, MCDS, MCDS0 to MCDS3... Dummy memory cell transistors STT1, STT1a to STT1c, ST1, ST1a to ST1c, ST2, ST2a to ST2c, STB, STB2a to STB2d...selection transistor WL, WL0~WL159...Word lines WLD, WLDD0 to WLDD3, WLDU, WLDL, and WLDS0 to WLDS3... dummy word lines

Claims

1. A plurality of bit lines; A source line; a plurality of NAND strings each having a plurality of memory cell transistors connected in series and connecting the plurality of bit lines and the source line; a first sub-block and a second sub-block different from the first sub-block, the first sub-block and the second sub-block sharing the bit lines, the NAND strings, and the source line as a series current path; a first word line group included in the first sub-block; a second word line group included in the second sub-block; a memory cell array including a dummy word line located between the first sub-block and the second sub-block; a control circuit capable of applying a predetermined voltage to the first word line group, the second word line group, and the dummy word line; A semiconductor memory device comprising: when a specific word line belonging to the first word line group is selected and a write operation is performed, the control circuit applies to the dummy word line a voltage higher than a voltage applied to an unselected word line belonging to the first word line group and to the second word line group; Semiconductor memory device.

2. 2. The semiconductor memory device according to claim 1, wherein the first word line group is a word line group adjacent to the second word line group.

3. 2. The semiconductor memory device according to claim 1, wherein, when the control circuit selects a particular word line belonging to the first word line group to perform a write operation, the control circuit applies to the second word line group a voltage that is lower than a voltage applied to unselected word lines belonging to the first word line group.

4. 2. The semiconductor memory device according to claim 1, wherein said control circuit performs an erase operation on said dummy word lines when executing an erase operation on said first sub-block.

5. 5. The semiconductor memory device according to claim 4, wherein the control circuit executes a read process of the dummy word line at a predetermined timing, and performs an erase operation on the dummy word line when executing an erase operation on the first sub-block based on a result of reading the dummy word line.

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