Wiring board and manufacturing method of the same

Abstract

To provide a wiring board in which a risk that both of adjacent wiring layers short-circuit is reduced.SOLUTION: A wiring board includes: a first wiring layer; an insulation layer that contains a filler formed onto the first wiring layer; a via hole that penetrates the insulation layer, and exposes an upper surface of the first wiring layer; and a second wiring layer that is electrically connected to the first wiring layer so as to fill the via hole, and is extended to the upper surface of the insulation layer from the via hole. The insulation layer contains: a first insulation layer that coats the first wiring layer; and a second insulation layer that is laminated onto the first insulation layer. The second insulation layer is thinner than the first insulation layer, and an amount of the filler contained in the second insulation layer is smaller than the amount of the filler contained in the first insulation layer. In a cross-sectional view, an inner surface of the via hole is inclined to the upper surface of the first wiring layer. In the cross-sectional view, an inclination angle to the upper surface of the first wiring layer of the inner surface of the via hole positioned in the first insulation layer is larger than the inclination angle to the upper surface of the first wiring layer in the inner surface of the via hole positioned in the second insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board and a manufacturing method thereof. [Background technology]

[0002] There is known a wiring board having a multilayer build-up structure in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated. In such a wiring board, an insulating layer consisting of a lower insulating layer and an upper insulating layer provided on the lower insulating layer may be used. For example, the upper insulating layer and the lower insulating layer contain an inorganic material in a resin insulating material, and the upper insulating layer is formed thinner than the lower insulating layer. Also, the volume ratio of the inorganic material in the upper insulating layer is smaller than the volume ratio of the inorganic material in the lower insulating layer (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-122545 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the volume ratio of the inorganic material in the upper insulating layer is small, when via holes are formed in the insulating layer, the opening diameter of the via holes on the upper surface of the upper insulating layer tends to be large, which narrows the distance between adjacent via holes and may cause a short circuit between adjacent wiring layers formed on the upper insulating layer.

[0005] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a wiring board in which the risk of short-circuiting between adjacent wiring layers is reduced. [Means for solving the problem]

[0006] This wiring board has a first wiring layer, an insulating layer containing a filler formed on the first wiring layer, a via hole penetrating the insulating layer and exposing an upper surface of the first wiring layer, and a second wiring layer filling the via hole and electrically connecting to the first wiring layer, and extending from within the via hole to an upper surface of the insulating layer, wherein the insulating layer includes a first insulating layer covering the first wiring layer and a second insulating layer stacked on the first insulating layer, the second insulating layer is thinner than the first insulating layer, the amount of filler contained in the second insulating layer is less than the amount of filler contained in the first insulating layer, the inner side of the via hole is inclined with respect to the upper surface of the first wiring layer in a cross-sectional view, and the inclination angle of the inner side of the via hole located in the first insulating layer with respect to the upper surface of the first wiring layer is greater than the inclination angle of the inner side of the via hole located in the second insulating layer with respect to the upper surface of the first wiring layer in a cross-sectional view. Effect of the Invention

[0007] According to the disclosed technique, it is possible to provide a wiring board in which the risk of short-circuiting between adjacent wiring layers is reduced. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of the wiring board according to the first embodiment; [Diagram 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4] 5A to 5C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted.

[0010] First Embodiment [Wiring board structure] 1A and 1B are cross-sectional views illustrating a wiring board according to a first embodiment, where FIG. 1A is an overall view and FIG. 1B is a partially enlarged view of part A in FIG. 1A.

[0011] Referring to FIG. 1, wiring board 1 is a wiring board in which wiring layers and insulating layers are laminated on both sides of core layer 10.

[0012] Specifically, in the wiring board 1, a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, and a solder resist layer 17 are laminated in this order on one surface 10a of the core layer 10. Also, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27 are laminated in this order on the other surface 10b of the core layer 10.

[0013] In the first embodiment, for convenience, the solder resist layer 17 side of the wiring board 1 is referred to as the upper side or one side, and the solder resist layer 27 side is referred to as the lower side or the other side. Also, the surface of each part on the solder resist layer 17 side is referred to as one side or upper side, and the surface on the solder resist layer 27 side is referred to as the other side or lower side. However, the wiring board 1 can be used upside down or placed at any angle. Also, the planar view refers to viewing the object from the normal direction of one surface 10a of the core layer 10, and the planar shape refers to the shape of the object viewed from the normal direction of one surface 10a of the core layer 10.

[0014] The core layer 10 may be, for example, a so-called glass epoxy substrate in which a glass cloth is impregnated with an insulating resin such as an epoxy resin. The core layer 10 may be a substrate in which a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber is impregnated with an epoxy resin. The thickness of the core layer 10 is, for example, about 60 to 1000 μm. The core layer 10 is provided with a through hole 10x that penetrates the core layer 10 in the thickness direction. The planar shape of the through hole 10x is, for example, a circle.

[0015] The wiring layer 12 is formed on one surface 10a of the core layer 10. The wiring layer 22 is formed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by the through wiring 11 formed in the through hole 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. The wiring layers 12 and 22 and the through wiring 11 may be made of, for example, copper (Cu). The thickness of the wiring layers 12 and 22 is, for example, about 10 to 40 μm. The wiring layer 12, the wiring layer 22, and the through wiring 11 may be integrally formed.

[0016] The insulating layer 13 is an interlayer insulating layer formed on the wiring layer 12 on one surface 10a of the core layer 10. The insulating layer 13 includes a first insulating layer 13a that covers the upper surface and side surface of the wiring layer 12, and a second insulating layer 13b that is laminated on the first insulating layer 13a. The second insulating layer 13b is thinner than the first insulating layer 13a. The thickness of the first insulating layer 13a is, for example, 10 μm or more and 40 μm or less. The thickness of the second insulating layer 13b is, for example, 1 μm or more and 2 μm or less. The roughness of the upper surface 13u of the second insulating layer 13b is, for example, 250 nm or more and 300 nm or less in terms of arithmetic mean roughness Ra. When the arithmetic mean roughness Ra is in such a range, wiring lifting and the like is less likely to occur, and the wiring layer 14 can be stably formed on the second insulating layer 13b. In addition, the adhesion between the second insulating layer 13b and the wiring layer 14 can be improved by the anchor effect.

[0017] Each of the first insulating layer 13a and the second insulating layer 13b contains a filler 131. The filler 131 is, for example, silicon dioxide (SiO2). The filler contained in each of the first insulating layer 13a and the second insulating layer 13b is, for example, kaolin (Al2Si2O5(OH4)), talc (Mg3Si4O 10 (OH2), alumina (Al2O3), etc.

[0018] The types of filler 131 contained in each of first insulating layer 13a and second insulating layer 13b may be the same or different. The average particle size of filler 131 contained in each of first insulating layer 13a and second insulating layer 13b may be the same or different. The particle size of filler 131 may be, for example, a minimum particle size of 0.1 μm, a maximum particle size of 5 μm, and an average particle size of about 0.5 to 2 μm. Some or all of fillers 131 may be hollow.

[0019] The amount of filler 131 contained in first insulating layer 13a can be, for example, 70% by weight or more and 80% by weight or less. By making the amount of filler 131 contained in first insulating layer 13a 70% by weight or more, it is possible to reduce the dielectric tangent of first insulating layer 13a, and an insulating layer with small electrical loss can be realized. In addition, by making the amount of filler 131 contained in first insulating layer 13a 70% by weight or more, it is possible to make the thermal expansion coefficient of first insulating layer 13a close to the thermal expansion coefficient (about 17 ppm / °C) of copper (Cu) constituting wiring layer 12 and wiring layer 14, and warping generated in wiring board 1 can be reduced.

[0020] The amount of filler 131 contained in the second insulating layer 13b is less than the amount of filler 131 contained in the first insulating layer 13a. The amount of filler 131 contained in the second insulating layer 13b can be, for example, more than 0% by weight and less than 70% by weight. If the amount of filler 131 contained in the second insulating layer 13b is 70% by weight or more, the upper surface 13u of the second insulating layer 13b is etched in the desmear process described later, and the upper surface 13u of the second insulating layer 13b becomes filler-rich. If the upper surface 13u of the second insulating layer 13b becomes filler-rich, the adhesion with the wiring layer 14 becomes weak, and problems such as floating of wiring occur. If floating of wiring occurs, disconnection failure occurs, and the yield of the wiring board deteriorates. If the amount of filler 131 contained in the second insulating layer 13b is less than 70% by weight, the risk of such problems occurring can be reduced. The amount of filler contained in second insulating layer 13b is preferably less than 60% by weight, and more preferably less than 50% by weight, which can further reduce the risk of the above-mentioned problems occurring.

[0021] The insulating resin used for the first insulating layer 13a and the second insulating layer 13b may be, for example, a thermosetting resin. Specifically, the insulating resin used for the first insulating layer 13a and the second insulating layer 13b may be, for example, an epoxy resin, an imide resin, a phenol resin, a cyanate resin, etc. The insulating resin used for the first insulating layer 13a and the second insulating layer 13b may be the same or different. When the insulating resin used for the first insulating layer 13a and the second insulating layer 13b is the same, it is preferable in that the adhesion between the two layers is improved.

[0022] The first insulating layer 13a may or may not have a reinforcing member. If the first insulating layer 13a does not have a reinforcing member, it is preferable in that the via holes 13x described later are easily formed. The second insulating layer 13b does not have a reinforcing member. Here, the reinforcing member is, for example, a woven or nonwoven fabric of glass fiber, carbon fiber, aramid fiber, or the like.

[0023] The insulating layer 13 has a via hole 13x. The via hole 13x penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12. The via hole 13x is, for example, a recess in a substantially inverted truncated cone shape in which the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 12.

[0024] That is, in a cross-sectional view, the inner side surface of the via hole 13x is inclined with respect to the upper surface of the wiring layer 12 in a direction in which the via hole 13x widens as it moves away from the wiring layer 12 in the thickness direction. The inclination angle of the inner side surface of the via hole 13x with respect to the upper surface of the wiring layer 12 is not constant, but changes at the interface between the first insulating layer 13a and the second insulating layer 13b.

[0025] Specifically, in a cross-sectional view, the inclination angle α of the inner surface of the via hole 13x located in the first insulating layer 13a with respect to the upper surface of the wiring layer 12 is larger than the inclination angle β of the inner surface of the via hole 13x located in the second insulating layer 13b with respect to the upper surface of the wiring layer 12. The inclination angle α is, for example, not less than 70 degrees and less than 90 degrees. β is, for example, not less than 30 degrees and less than 60 degrees. In FIG. 1(b), the dashed line L is a virtual line parallel to the upper surface of the wiring layer 12.

[0026] The via hole 13x is, for example, circular in plan view. In this case, the opening diameter of the via hole 13x located in the first insulating layer 13a on the wiring layer 12 side is about 40 μm, and the opening diameter of the via hole 13x located in the second insulating layer 13b is about 50 μm. The opening diameter of the via hole 13x located in the second insulating layer 13b on the first insulating layer 13a side is the same as the opening diameter of the via hole 13x located in the first insulating layer 13a on the second insulating layer 13b side. The opening diameter of the via hole 13x located in the second insulating layer 13b on the insulating layer 15 side is about 25 to 30 μm.

[0027] The wiring layer 14 fills the via holes 13x to be electrically connected to the wiring layer 12, and extends from within the via holes 13x to the upper surface of the insulating layer 13 (upper surface 13u of the second insulating layer 13b). In detail, the wiring layer 14 includes via wiring filled in the via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 through the via wiring. The material of the wiring layer 14 and the thickness of the wiring pattern are, for example, similar to those of the wiring layer 12.

[0028] The insulating layer 15 is an interlayer insulating layer formed on the upper surface of the insulating layer 13 so as to cover the wiring layer 14. The insulating layer 15 includes a first insulating layer 15a covering the upper surface and side surfaces of the wiring layer 14, and a second insulating layer 15b laminated on the first insulating layer 15a. Details of the first insulating layer 15a and the second insulating layer 15b are similar to those of the first insulating layer 13a and the second insulating layer 13b.

[0029] The insulating layer 15 has a via hole 15x. The via hole 15x penetrates the insulating layer 15 and exposes the upper surface of the wiring layer 14. Details of the via hole 15x are similar to those of the via hole 13x.

[0030] The wiring layer 16 fills the via holes 15x to be electrically connected to the wiring layer 14, and extends from within the via holes 15x to the upper surface of the insulating layer 15 (the upper surface of the second insulating layer 15b). In detail, the wiring layer 16 includes via wiring filled in the via holes 15x and a wiring pattern formed on the upper surface of the insulating layer 15. The wiring pattern of the wiring layer 16 is electrically connected to the wiring layer 14 through the via wiring. The material of the wiring layer 16 and the thickness of the wiring pattern are similar to those of the wiring layer 12, for example.

[0031] The solder resist layer 17 is a protective insulating layer located at the outermost side of one side of the wiring board 1, and is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The solder resist layer 17 can be formed from, for example, a photosensitive resin whose main component is an epoxy resin or the like. The thickness of the solder resist layer 17 is, for example, about 15 to 35 μm.

[0032] The solder resist layer 17 has an opening 17x. The opening 17x penetrates the solder resist layer 17 and exposes the upper surface of the wiring layer 16. The wiring layer 16 exposed in the opening 17x can be used as, for example, a pad for electrically connecting to an electronic component such as a semiconductor chip.

[0033] In addition, a metal layer may be formed on the surface of the wiring layer 16 exposed in the opening 17x, or an organic coating may be formed by performing an anti-oxidation treatment such as an OSP (Organic Solderability Preservative) treatment. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), a Ni / Pd / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order), and a Sn layer.

[0034] The insulating layer 23 is an interlayer insulating layer formed on the other surface 10b of the core layer 10 so as to cover the wiring layer 22. The insulating layer 23 includes a first insulating layer 23a covering the lower surface and side surfaces of the wiring layer 22, and a second insulating layer 23b laminated on the first insulating layer 23a. Details of the first insulating layer 23a and the second insulating layer 23b are similar to those of the first insulating layer 13a and the second insulating layer 13b.

[0035] The insulating layer 23 has a via hole 23x. The via hole 23x penetrates the insulating layer 23 and exposes the lower surface of the wiring layer 22. The via hole 23x has a shape that is upside down compared to the via hole 13x. Other details of the via hole 23x are the same as those of the via hole 13x.

[0036] The wiring layer 24 fills the via holes 23x to be electrically connected to the wiring layer 22, and extends from within the via holes 23x to the lower surface of the insulating layer 23 (the lower surface of the second insulating layer 23b). In detail, the wiring layer 24 includes via wirings filled within the via holes 23x, and a wiring pattern formed on the lower surface of the insulating layer 23. The wiring pattern of the wiring layer 24 is electrically connected to the wiring layer 22 through the via wirings. The material of the wiring layer 24 and the thickness of the wiring pattern are similar to those of the wiring layer 12, for example.

[0037] The insulating layer 25 is an interlayer insulating layer formed on the lower surface of the insulating layer 23 so as to cover the wiring layer 24. The insulating layer 25 includes a first insulating layer 25a covering the lower surface and side surfaces of the wiring layer 24, and a second insulating layer 25b laminated on the first insulating layer 25a. Details of the first insulating layer 25a and the second insulating layer 25b are similar to those of the first insulating layer 13a and the second insulating layer 13b.

[0038] The insulating layer 25 has a via hole 25x. The via hole 25x penetrates the insulating layer 25 and exposes the lower surface of the wiring layer 24. The via hole 25x has a shape that is upside down compared to the via hole 13x. Other details of the via hole 25x are the same as those of the via hole 13x.

[0039] The wiring layer 26 fills the via holes 25x to be electrically connected to the wiring layer 26, and extends from within the via holes 25x to the lower surface of the insulating layer 25 (the lower surface of the second insulating layer 25b). In detail, the wiring layer 26 includes via wirings filled in the via holes 25x, and a wiring pattern formed on the lower surface of the insulating layer 25. The wiring pattern of the wiring layer 26 is electrically connected to the wiring layer 24 through the via wirings. The material of the wiring layer 26 and the thickness of the wiring pattern are similar to those of the wiring layer 12, for example.

[0040] The solder resist layer 27 is a protective insulating layer located at the outermost position on the other side of the wiring board 1, and is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The material and thickness of the solder resist layer 27 are the same as those of the solder resist layer 17, for example.

[0041] The solder resist layer 27 has an opening 27x, and a part of the lower surface of the wiring layer 26 is exposed in the opening 27x. The opening 27x has a planar shape of, for example, a circle. The wiring layer 26 exposed in the opening 27x can be used as a pad for electrically connecting to a mounting substrate (not shown) such as a motherboard. If necessary, the above-mentioned metal layer may be formed on the lower surface of the wiring layer 26 exposed in the opening 27x, or an organic coating may be formed by performing an anti-oxidation treatment such as an OSP treatment.

[0042] [Method of manufacturing wiring board] Fig. 2 to Fig. 4 are cross-sectional views illustrating the manufacturing process of the wiring board according to the first embodiment, corresponding to Fig. 1. Fig. 2(d) is an enlarged view of part A in Fig. 2(c), and Figs. 3(b) and 3(c) are enlarged views of part A in Fig. 3(a).

[0043] Since the process is the same for one surface 10a side and the other surface 10b side of the core layer 10, only the one surface 10a side of the core layer 10 is illustrated and described here. Also, an example of the process for producing one wiring board is shown here, but a process may be used in which multiple parts that will become the wiring board are produced and then diced into individual wiring boards.

[0044] 2(a), a core layer 10 is prepared in which a through-wire 11 and a wiring layer 12 are formed. Specifically, a laminate is prepared in which a plain copper foil that is not patterned is formed on one surface 10a of the core layer 10, which is a so-called glass epoxy substrate, for example. Then, in the prepared laminate, the copper foil is thinned as necessary, and then a through hole 10x that penetrates the core layer 10 and the copper foil is formed by a laser processing method using a CO2 laser or the like.

[0045] Next, a desmear process is performed as necessary to remove the resin residue contained in the core layer 10 that is attached to the inner side surface of the through hole 10x. Then, a seed layer (copper, etc.) that covers the copper foil and the inner side surface of the through hole 10x is formed by, for example, electroless plating or sputtering, and an electrolytic plating layer (copper, etc.) is formed on the seed layer by electrolytic plating using the seed layer as a power supply layer. As a result, the through hole 10x is filled with the electrolytic plating layer formed on the seed layer, and a wiring layer 12 in which the copper foil, the seed layer, and the electrolytic plating layer are laminated is formed on one surface 10a of the core layer 10. Next, the wiring layer 12 is patterned into a predetermined planar shape by a subtractive method or the like.

[0046] Next, in the step shown in FIG. 2(b), an insulating layer 13 is formed on the wiring layer 12 on one surface 10a of the core layer 10. The insulating layer 13 includes a first insulating layer 13a containing a filler, and a second insulating layer 13b laminated on the first insulating layer 13a, which is thinner than the first insulating layer 13a and contains less filler than the first insulating layer 13a. The amount of filler contained in the first insulating layer 13a can be, for example, 70% by weight or more and 80% by weight or less. The amount of filler contained in the second insulating layer 13b can be, for example, more than 0% by weight and less than 70% by weight.

[0047] Specifically, for example, a laminate in which the second insulating layer 13b and the resin film 100 are sequentially laminated on the first insulating layer 13a is prepared, and the laminate is arranged so that the first insulating layer 13a faces the wiring layer 12. The first insulating layer 13a and the second insulating layer 13b are formed of, for example, a thermosetting resin in a B-stage state. Examples of the resin film 100 include a polyethylene terephthalate film and a polyethylene naphthalate film. The thickness of the resin film 100 can be, for example, 25 μm or more and 50 μm or less. Next, the first insulating layer 13a and the second insulating layer 13b are cured by heating to a predetermined temperature and applying pressure as necessary. At this point, the thickness of the second insulating layer 13b is, for example, 3 μm or more and 5 μm or less. Note that a peelable release layer is provided between the upper surface 13u of the second insulating layer 13b and the resin film 100.

[0048] Next, in the steps shown in Figures 2(c) and 2(d), via holes 13x are formed in the insulating layer 13, penetrating the insulating layer 13 and exposing the upper surface of the wiring layer 12. The via holes 13x can be formed, for example, by irradiating a laser beam such as a CO2 laser from the resin film 100 side. The resin film 100 containing no filler and the second insulating layer 13b containing a small amount of filler are easily processed by a laser, and therefore have a relatively large opening diameter. In contrast, the first insulating layer 13a containing a large amount of filler is difficult to process by a laser, and therefore have a relatively small opening diameter.

[0049] That is, in a cross-sectional view, the inner side surface of the via hole 13x is inclined with respect to the upper surface of the wiring layer 12 in a direction in which the via hole 13x widens as it moves away from the wiring layer 12 in the thickness direction. The inclination angle of the inner side surface of the via hole 13x with respect to the upper surface of the wiring layer 12 is not constant, but changes at the interface between the first insulating layer 13a and the second insulating layer 13b. Specifically, in a cross-sectional view, the inclination angle α of the inner side surface of the via hole 13x located on the first insulating layer 13a with respect to the upper surface of the wiring layer 12 is larger than the inclination angle β of the inner side surface of the via hole 13x located on the second insulating layer 13b and the resin film 100 with respect to the upper surface of the wiring layer 12. The inclination angle α is, for example, 70 degrees or more and less than 90 degrees. β is, for example, 30 degrees or more and less than 60 degrees.

[0050] 2(b), it is not essential to use the resin film 100. However, when the resin film 100 is disposed on the upper surface 13u of the second insulating layer 13b, the power of the irradiated laser can be increased. Therefore, the inclination angles α and β can be increased compared to when the resin film 100 is not disposed. Furthermore, when the resin film 100 is disposed on the upper surface 13u of the second insulating layer 13b, it is possible to prevent foreign matter from adhering to the upper surface 13u of the second insulating layer 13b.

[0051] Next, in the process shown in FIG. 3(a) and FIG. 3(b), after removing the resin film 100, the entire insulating layer 13 is subjected to a plasma treatment to thin the second insulating layer 13b. For example, a gas mixture of oxygen (O2) and tetrafluoromethane (CF4) can be used for the plasma treatment. By using a gas containing O2 in the plasma treatment, the resin can be easily decomposed. In addition, by using a gas containing O2 in the plasma treatment, the surface of the filler is oxidized and the hydrophilicity can be increased. Therefore, the etching solution used in the desmear treatment described later can be uniformly spread on the upper surface 13u of the second insulating layer 13b, and the upper surface 13u of the second insulating layer 13b can be uniformly roughened. Note that Ar gas may be used for the plasma treatment. By the plasma treatment, the second insulating layer 13b is etched by about 1 to 3 μm, and the thickness of the second insulating layer 13b after the plasma treatment is, for example, 1 μm or more and 2 μm or less.

[0052] 3(c), a desmear process is performed on the entire insulating layer 13. This makes it possible to remove the resin residue of the insulating layer 13 attached to the upper surface of the wiring layer 12 exposed at the bottom of the via hole 13x, and to roughen the upper surface 13u of the second insulating layer 13b constituting the insulating layer 13. The roughness of the upper surface 13u of the second insulating layer 13b after the desmear process is, for example, 250 nm or more and 300 nm or less in terms of arithmetic mean roughness Ra. Since the second insulating layer 13b has a small filler content, the upper surface 13u of the second insulating layer 13b does not become filler-rich even after the desmear process is performed.

[0053] The desmear process may include a wet etching process. The desmear process may include a swelling process before the wet etching process. In the swelling process, the insulating layer 13 including the via holes 13x is immersed in a swelling liquid for a predetermined time. This makes it easier to remove the resin residue in the etching process. In addition, by swelling the insulating layer 13, it is possible to improve the adhesion between the insulating layer 13 obtained through the etching process and the wiring layer 14 formed thereafter. The wet etching process may be performed after the swelling process. In the wet etching process, an etching solution such as sodium permanganate or potassium permanganate may be used. After the wet etching process, it is preferable to perform a post-treatment (neutralization treatment) using a reducing agent solution.

[0054] 3(d), the via holes 13x are filled to form a wiring layer 14 that is electrically connected to the wiring layer 12 and extends from the inside of the via holes 13x to the upper surface of the insulating layer 13. The wiring layer 14 includes via wiring filled in the via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via holes 13x. The wiring layer 14 can be formed by using various wiring formation methods, such as a semi-additive method or a subtractive method.

[0055] For example, when the wiring layer 14 is formed by a semi-additive method, a seed layer is formed by electroless plating of copper, for example, on the upper surface of the insulating layer 13 (upper surface 13u of the second insulating layer 13b), the inner side surface of the via hole 13x, and the upper surface of the wiring layer 12 exposed in the via hole 13x. Next, a plating resist pattern having an opening corresponding to the shape of the wiring pattern of the wiring layer 14 is formed on the seed layer, and then an electrolytic plating layer is deposited on the seed layer exposed in the opening of the plating resist pattern by electrolytic plating of copper or the like supplied with power from the seed layer. Next, the plating resist pattern is removed, and then etching is performed using the electrolytic plating layer as a mask to remove the seed layer exposed from the electrolytic plating layer, thereby obtaining the wiring layer 14 having the via wiring and the wiring pattern. In this case, the wiring layer 14 has a structure in which an electrolytic plating layer is laminated on a seed layer.

[0056] As described above, the upper surface 13u of the second insulating layer 13b is not filler-rich, and the roughness of the upper surface 13u of the second insulating layer 13b is, for example, 250 nm or more and 300 nm or less in terms of arithmetic mean roughness Ra. This provides good adhesion between the upper surface 13u of the second insulating layer 13b and the seed layer constituting the wiring layer 14. As a result, the risk of wire floating occurring in the wiring layer 14 is reduced.

[0057] Next, in a step shown in FIG. 4(a), the same steps as those shown in FIGS. 2(b) to 3(d) are repeated to form an insulating layer 15 and a wiring layer 16.

[0058] 4(b), a solder resist layer 17 is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin to the upper surface of the insulating layer 15 by a screen printing method, a roll coating method, a spin coating method, or the like so as to cover the wiring layer 16. Alternatively, for example, the solder resist layer 17 may be formed by laminating a film-like photosensitive epoxy insulating resin on the upper surface of the insulating layer 15 so as to cover the wiring layer 16.

[0059] Next, in the step shown in FIG. 4(c), the solder resist layer 17 is exposed and developed to form an opening 17x in the solder resist layer 17 that exposes a part of the upper surface of the wiring layer 16 (photolithography method). The planar shape of the opening 17x is, for example, circular. The diameter of the opening 17x can be designed arbitrarily according to the connection target (semiconductor chip, etc.). If necessary, the above-mentioned metal layer may be formed on the surface of the wiring layer 16 exposed in the opening 17x, or an organic coating may be formed by performing an anti-oxidation treatment such as OSP treatment. Through the above steps, the wiring board 1 is completed.

[0060] In this manner, the manufacturing process of the wiring board 1 includes a step of thinning the second insulating layer 13b by performing a plasma treatment between the step of forming the via holes 13x that penetrate the first insulating layer 13a and the second insulating layer 13b and expose the upper surface of the wiring layer 12 and the step of performing a desmear treatment.

[0061] As described with reference to FIG. 2(c) and FIG. 2(d), in a cross-sectional view, the inclination angle α of the inner surface of the via hole 13x located in the first insulating layer 13a with respect to the upper surface of the wiring layer 12 is larger than the inclination angle β of the inner surface of the via hole 13x located in the second insulating layer 13b and the resin film 100 with respect to the upper surface of the wiring layer 12. In other words, the inclination angle β is smaller than the inclination angle α. Therefore, if the second insulating layer 13b is thick, the opening diameter of the via hole 13x on the upper surface 13u of the second insulating layer 13b becomes large, and the interval between adjacent via holes 13x becomes narrow. This causes a risk of short-circuiting between adjacent wiring layers 14. On the other hand, if the interval between adjacent via holes 13x is widened to avoid short-circuiting between the wiring layers 14, the wiring density of the wiring layer 14 decreases. However, in the wiring board 1, since the second insulating layer 13b is thinned by plasma processing, the interval between adjacent via holes 13x becomes wider than when the second insulating layer 13b is not thinned. As a result, even if a high-density wiring layer 14 is formed, it is possible to reduce the risk of short-circuiting between adjacent wiring layers 14. The same applies to the other wiring layers.

[0062] Also, since the second insulating layer 13b contains less filler than the first insulating layer 13a, the thicker it is, the more disadvantageous it is in terms of dielectric properties. However, since the second insulating layer 13b is thinned in the wiring board 1, the effect on the dielectric properties can be reduced. That is, the dielectric properties of the insulating layer 13 are dominated by the effect of the first insulating layer 13a, which is thicker than the second insulating layer 13b and contains more filler than the second insulating layer 13b. Therefore, it is possible to realize a wiring board 1 with less loss of electrical signals and excellent electrical properties.

[0063] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0064] For example, in the step shown in FIG. 2(b), the resin film 100 may not be used. In this case, for example, a thermosetting resin mainly composed of a film-like epoxy resin in a semi-cured state is laminated and cured on one surface 10a of the core layer 10 so as to cover the wiring layer 12, to form the first insulating layer 13a. Furthermore, a thermosetting resin mainly composed of a film-like epoxy resin in a semi-cured state can be laminated on the first insulating layer 13a and cured to form the second insulating layer 13b. The first insulating layer 13a and the second insulating layer 13b may be cured at the same time. Also, instead of laminating a film-like epoxy resin, a liquid or paste-like epoxy resin may be applied as the first insulating layer 13a and the second insulating layer 13b, and then cured.

[0065] In the above embodiment, the present invention is applied to a wiring board having a core layer manufactured by a build-up method, but the present invention may be applied to a coreless wiring board manufactured by a build-up method. The present invention is not limited to these, and can be applied to various wiring boards. [Explanation of symbols]

[0066] 1. Wiring board 10 Core Layer 10a One side 10b The other side 10x through holes 11 Through Wiring 12, 14, 16, 22, 24, 26 wiring layer 13, 15, 23, 25 Insulating layer 13a, 15a, 23a, 25a First insulating layer 13b, 15b, 23b, 25b Second insulating layer 13x, 15x, 23x, 25x via holes 13u top 17, 27 Solder resist layer 17x, 27x opening 131 Filler

Claims

1. A first wiring layer; an insulating layer containing a filler formed on the first wiring layer; a via hole penetrating the insulating layer and exposing an upper surface of the first wiring layer; a second wiring layer filling the via hole, electrically connected to the first wiring layer, and extending from within the via hole to an upper surface of the insulating layer; the insulating layer includes a first insulating layer covering the first wiring layer and a second insulating layer stacked on the first insulating layer; The second insulating layer is thinner than the first insulating layer, the amount of the filler contained in the second insulating layer is less than the amount of the filler contained in the first insulating layer; In a cross-sectional view, an inner side surface of the via hole is inclined with respect to an upper surface of the first wiring layer; A wiring board, wherein, in a cross-sectional view, an inclination angle of an inner surface of the via hole located in the first insulating layer relative to an upper surface of the first wiring layer is greater than an inclination angle of an inner surface of the via hole located in the second insulating layer relative to the upper surface of the first wiring layer.

2. The wiring board according to claim 1 , wherein the second insulating layer has a thickness of not less than 1 μm and not more than 2 μm.

3. 3. The wiring board according to claim 1, wherein the roughness of the upper surface of the second insulating layer is in the range of 250 nm to 300 nm in terms of arithmetic mean roughness Ra.

4. 3. The wiring board according to claim 1, wherein the amount of the filler contained in the first insulating layer is 70% by weight or more.

5. forming an insulating layer on a first wiring layer, the insulating layer including a first insulating layer containing a filler, and a second insulating layer laminated on the first insulating layer, the second insulating layer being thinner than the first insulating layer and having a lower filler content than the first insulating layer; forming a via hole penetrating the insulating layer and exposing an upper surface of the first wiring layer; a step of thinning the second insulating layer by performing a plasma treatment after the step of forming the via hole; a step of performing a desmear treatment after the thinning step; and forming, after the desmearing step, a second wiring layer that is electrically connected to the first wiring layer by filling the via hole and extends from within the via hole to an upper surface of the insulating layer.

6. In the step of forming the insulating layer, a laminate in which the second insulating layer and a resin film are sequentially laminated on the first insulating layer is prepared, and the laminate is arranged so that the first insulating layer faces the first wiring layer side; The method for manufacturing a wiring board according to claim 5 , wherein in the step of forming the via holes, the via holes are formed by irradiating the resin film with laser light.

7. 7. The method for manufacturing a wiring board according to claim 5 or 6, wherein in the step of forming the via hole, in a cross-sectional view, the inner side of the via hole is inclined relative to the upper surface of the first wiring layer, and the inclination angle of the inner side of the via hole located in the first insulating layer relative to the upper surface of the first wiring layer is greater than the inclination angle of the inner side of the via hole located in the second insulating layer relative to the upper surface of the first wiring layer.

8. 7. The method for manufacturing a wiring board according to claim 5, wherein the second insulating layer has a thickness of 1 [mu]m or more and 2 [mu]m or less after the plasma treatment.

9. The method for manufacturing a wiring board according to claim 5 , wherein the roughness of the upper surface of the second insulating layer after the desmear treatment is in a range of 250 nm to 300 nm in terms of arithmetic mean roughness Ra.

10. The method for manufacturing a wiring board according to claim 5 , wherein the amount of the filler contained in the first insulating layer is 70% by weight or more.

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