Josephson junction-based charge sensing in quantum systems

Abstract

To provide a method of charge sensing in a quantum system.SOLUTION: The method includes supplying a bias current through a Josephson junction. The bias current is less than a first value of a critical current of the Josephson junction. The method further includes measuring an output voltage of the Josephson junction. In response to a change in charge of one or more charge islands coupled to the Josephson junction, the critical current is reduced to a second value less than the bias current, causing a voltage drop across the Josephson junction.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] Aspects of the present disclosure relate to techniques for local charge sensing in quantum systems. [Background technology]

[0002]

[0002] It is difficult to obtain the local charge state of a quantum system quickly and accurately. Existing solutions for measuring local charge include capacitively coupling a tunnel dot (or "measurement island") or operating it as a conventional field effect transistor (FET). The amount of current flowing through the source and drain terminals of the FET changes as the charge occupancy at the bias of the measurement island changes. However, to accurately measure the charge occupancy of the coupled island, multiple samples of the measurement island current response are required. This method is relatively time consuming, typically requiring on the order of microseconds to perform the integration function. It also requires a sensitive amplifier at the output, as well as a resistor near the measurement island that tends to cause local heating and noise generation. Summary of the Invention

[0003]

[0003] The present disclosure provides a method of charge sensing in a quantum system. In one aspect, the method includes providing a bias current through a Josephson junction, the bias current being less than a first value of a critical current of the Josephson junction. The method further includes measuring an output voltage of the Josephson junction. In response to a change in charge of one or more charge islands coupled to the Josephson junction, the critical current decreases to a second value less than the bias current, causing a voltage drop across the Josephson junction.

[0004]

[0004] In one aspect, in combination with any exemplary method described above or below, each of the one or more charge islands comprises a respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more microscopic surface features.

[0005]

[0005] In one aspect, in combination with any exemplary method above or below, the one or more charge islands include a plurality of charge islands, each charge island coupled to a Josephson junction via a respective capacitor.

[0006]

[0006] In one aspect, in combination with any of the exemplary methods described above or below, some or all of the capacitors corresponding to the multiple charge islands have different capacitance values.

[0007]

[0007] In one aspect, in combination with any exemplary method above or below, the method further includes updating the critical current of the Josephson junction to a second value in response to a change in charge of one or more charge islands using a shunt resistor coupled across and in parallel with the Josephson junction.

[0008]

[0008] In one aspect, in combination with any of the exemplary methods described above or below, a Josephson junction is included within a Josephson junction field effect transistor (JJFET), one or more charge islands are capacitively coupled to the gate of the JJFET, and a bias current is supplied by a current source coupled to the source or drain of the JJFET.

[0009]

[0009] In one aspect, in combination with any of the exemplary methods described above or below, the Josephson junction is included within a pair of series-connected Josephson junctions, one or more charge islands are capacitively coupled between the pair of Josephson junctions, and a bias current is supplied by a current source coupled to one of the pair of Josephson junctions.

[0010]

[0010] The present disclosure provides an apparatus. In one aspect, the apparatus includes a Josephson junction field effect transistor (JJFET), one or more charge islands capacitively coupled to a gate of the JJFET, and a current source coupled to one of the source or drain of the JJFET. The current source provides a bias current that is less than a first value of a critical current of the JJFET, and a predefined change in charge on the one or more charge islands reduces the critical current to a second value less than the bias current.

[0011]

[0011] In one aspect, in combination with any of the exemplary devices described above or below, each of the one or more charge islands comprises a respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more microscopic surface features.

[0012]

[0012] In one aspect, in combination with any of the exemplary devices described above or below, the one or more charge islands include a plurality of charge islands, each charge island coupled to a gate via a respective capacitor.

[0013] In one aspect, in combination with any of the exemplary devices described above or below, some or all of the capacitors corresponding to the multiple charge islands have different capacitance values.

[0014] In one aspect, in combination with any of the above or below exemplary devices, the device further includes a shunt resistor coupled across and in parallel with the source and drain of the JJFET.

[0015] In one aspect, in combination with any of the above or below described exemplary apparatus, the apparatus further comprises a measurement circuit coupled to the other of the source or drain of the JJFET.

[0016] In one aspect, in combination with any of the above or below described exemplary apparatus, the measurement circuit includes an amplifier circuit for amplifying the output voltage of the JJFET.

[0017]

[0017] The present disclosure provides an apparatus, in one aspect, that includes a pair of series-connected Josephson junctions, one or more charge islands capacitively coupled to a node between the pair of Josephson junctions, and a current source coupled to a first Josephson junction of the pair, the current source providing a bias current less than a first value of an effective critical current of the Josephson junction, such that a predefined change in charge on the one or more charge islands reduces the effective critical current to a second value less than the bias current.

[0018]

[0018] In one aspect, in combination with any of the exemplary devices described above or below, each of the one or more charge islands comprises a respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more microscopic surface features.

[0019]

[0019] In one aspect, in combination with any of the exemplary devices described above or below, the one or more charge islands include a plurality of charge islands, each charge island coupled between a pair of Josephson junctions via a respective capacitor.

[0020] In one aspect, in combination with any of the exemplary devices described above or below, some or all of the capacitors corresponding to the multiple charge islands have different capacitance values.

[0021]

[0021] In one aspect, in combination with any exemplary apparatus described above or below, the apparatus further includes a shunt resistor coupled across and in parallel with the pair of Josephson junctions.

[0022] In one aspect, in combination with any of the above or below described exemplary apparatus, the apparatus further comprising a measurement circuit coupled to a second Josephson junction of the pair.

[0023]

[0023] So that the above-mentioned features of the present disclosure can be understood in detail, a more detailed description of the present disclosure than that briefly summarized above can be made by reference to several exemplary aspects, some of which are illustrated in the accompanying drawings. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 illustrates a perspective view of an exemplary Josephson junction according to one or more aspects. [Diagram 2]

[0025] 1 illustrates a cross-sectional view of an exemplary Josephson Junction Field Effect Transistor (JJFET) in accordance with one or more embodiments. [Diagram 3]

[0026] 1 illustrates a system having one or more charge sensors in a quantum scale device or system according to one or more embodiments. [Figure 4]

[0027] 1 illustrates an exemplary device having one or more charge islands capacitively coupled to a JJFET according to one or more embodiments. [Diagram 5]

[0028] 1 illustrates an exemplary device having one or more charge islands capacitively coupled to a node between a pair of series-connected Josephson junctions according to one or more embodiments. [Figure 6]

[0029] 1 illustrates plots of current-voltage (IV) characteristics of Josephson junctions for different charge states according to one or more embodiments. [Figure 7]

[0030] 1 is a method of charge sensing in a quantum system according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025]

[0031] In the present disclosure, various embodiments are referenced. However, it should be understood that the disclosure is not limited to the specific described embodiments. Instead, any combination of the following features and elements, whether related to various embodiments or not, is contemplated for implementing and practicing the teachings provided herein. Furthermore, when an element of an embodiment is described in the form of "at least one of A and B," it should be understood that an embodiment including element A only, element B only, and elements A and B are each contemplated. Furthermore, while some embodiments may realize other potential solutions and / or advantages over the prior art, whether or not a particular advantage is realized by a given embodiment does not limit the disclosure. Thus, the embodiments, features, and advantages disclosed herein are merely exemplary and should not be considered elements of or limiting the scope of the appended claims unless expressly recited in the claim(s). Similarly, references to "the present invention" should not be construed as a generalization of all inventive subject matter disclosed herein, and should not be considered an element of or as limiting the scope of any accompanying claim(s) unless expressly recited in the claim(s).

[0026]

[0032] 1 illustrates a perspective view of an exemplary Josephson junction (JJ) 100 in accordance with one or more embodiments. The JJ 100 may be used in conjunction with any of the other embodiments described herein. Additionally, in some embodiments, the JJ 100 may be incorporated into a charge sensor and integrated into a quantum system.

[0027]

[0033] The JJ 100 comprises a first superconducting section 105 spaced from a second superconducting section 110 by a weak link section 115. The first superconducting section 105 and the second superconducting section 110 may be formed of any suitable superconducting material(s). In some embodiments, the weak link section 115 comprises an insulating material, whereby the JJ 100 is implemented as a superconductor-insulator-superconductor (SIS) junction. In other embodiments, the weak link section 115 comprises a non-superconducting metallic material, whereby the JJ 100 is implemented as a superconductor-non-superconducting metal-superconductor (SNS) junction. In still other embodiments, the weak link section 115 comprises a physical constraint providing an area of ​​reduced superconductivity, whereby the JJ 100 is implemented as a superconductor-constraint-superconductor (ScS) junction.

[0028]

[0034] Weak link section 115 has dimensions suitable to support quantum tunneling of electrons therethrough. Typically, the thickness of weak link section 115 may be on the order of 30 angstroms (Å) or less for a SIS junction, or on the order of a few microns for an SNS junction. The components of JJ 100 are shown in a linear arrangement for simplicity, although other configurations and shapes of JJ 100 are contemplated.

[0029]

[0035] When cooled to cryogenic temperatures, the first superconductor section 105 and the second superconductor section 110 can pass electrons without offering any electrical resistance. The flow of supercurrent 125 conducted through the JJ 100 across the weak link section 115 is governed by quantum tunneling of Cooper pairs 120 (i.e., pairs of electrons with opposite spins bound together at cryogenic temperatures).

[0030]

[0036] According to various aspects, and as will be described in more detail below, the properties of the JJ 100 can be dynamically controlled to support fast, single-shot charge sensing by the JJ 100. For example, applying different values ​​of electrostatic potentials in the vicinity of the JJ 100 changes its quantum tunneling properties and therefore the amount of supercurrent 125. The "critical current" of the JJ 100 represents the maximum value of the supercurrent 125 that can flow through the JJ 100. When the current through the JJ 100 exceeds the critical current, the JJ 100 transitions from its superconducting state to a "normal" conducting state (i.e., has resistive losses through the JJ 100). As a result, the voltage drop across the JJ 100 increases. In some aspects, the critical current of the JJ 100 is modulated using an electrostatic potential (one or more) (e.g., changing the number of Cooper pairs 120 available for transport). Thereby, a predefined change in charge "sensed" by the JJ 100 causes the JJ 100 to transition between a superconducting and a normal conducting state. The resulting pulse in the output voltage of the JJ 100 can then be measured and / or adjusted to provide a signal indicative of the change in charge.

[0031]

[0037] 2 illustrates a cross-sectional view of an exemplary Josephson Junction Field Effect Transistor (JJFET) 200 in accordance with one or more embodiments. The JJFET 200 may be used in conjunction with any of the other embodiments described herein. Additionally, in some embodiments, the JJFET 200 may be incorporated into a charge sensor and integrated into a quantum system.

[0032]

[0038] The JJFET 200 comprises a source 205 and a drain 210 formed of any suitable superconducting material(s). The JJFET 200 further comprises a gate 215 disposed on an oxide layer 220. In some embodiments, the gate 215 is formed of a metallic material. The oxide layer 220 is disposed between the source 205 and the drain 210, and the gate 215 is disposed partially between the source 205 and the drain 210 (as shown, the gate 215 extends through the plane of the top surfaces of the source 205 and the drain 210). The source 205, the drain 210, and the oxide layer 220 are disposed on a channel layer 225 formed of a semiconductor material. The channel layer 225 is disposed on a substrate 230 formed of an insulating material. The source 205, the drain 210, the gate 215, and the channel layer 225 support a channel length that is short enough to allow coherent transport of Cooper pairs through the channel. In this manner, JJFET 200 defines a first JJ with channel layer 225 as its weak link section. JJFET 200 may further define a second JJ (e.g., an SNS junction) with gate 215 as its weak link section, and / or a third JJ (e.g., an SIS junction) with oxide layer 220 as its weak link section. Although the components of JJFET 200 are shown in a particular arrangement in FIG. 2 for simplicity, other configurations and shapes of JJFET 200 are contemplated. For example, a more complex shape of JJFET 200 may be effective to minimize or eliminate the second JJ and / or the third JJ.

[0033]

[0039] In a conventional FET, the flow of current between the source 205 and the drain 210 (i.e., through a channel formed in the channel layer 225) is controlled by the amount of voltage applied to the gate 215. The electric field defined by the applied voltage modulates the conductivity of the channel layer 225. In the JJFET 200, the applied voltage changes the quantum tunneling properties of one or more JJs of the JJFET 200. In some aspects, the critical current of the JJFET 200 is modulated (e.g., by changing the number of Cooper pairs 120 available for transport in supercurrent) using the applied voltage to the gate 215. In this manner, a predefined change in the charge "sensed" by the JJFET 200 at the gate 215 can change the critical current and transition the JJFET 200 between the superconducting and normal states. The resulting voltage pulse output from the JJFET 200 can then be measured.

[0034]

[0040] 3 illustrates a system 300 having one or more charge sensors 330 in a quantum scale device or system 315 according to one or more embodiments. The JJFET 300 may be used in conjunction with any other embodiments described herein. For example, the one or more charge sensors 330 of the system 300 may include one or more JJFETs 100 (FIG. 1) and / or one or more JJFETs 200 (FIG. 2).

[0035]

[0041] The system 300 includes a cryogenic cooling system 305 in fluid communication with a cryogenic environment 310 for the quantum system 315. Typically, the cryogenic environment 310 is defined as having a temperature at or below 120K (-153°C). In some aspects, the cryogenic environment 310 has a temperature very close to absolute zero (0K, -273.15°C) since superconductivity and its associated quantum properties are most pronounced at these temperatures. However, the cryogenic environment 310 may have any suitable temperature (e.g., based on the critical temperature of the semiconductor material(s)) to ensure superconductivity. The cryogenic cooling system 305 may have any suitable implementation as known to those skilled in the art. In some aspects, the cryogenic cooling system 305 uses a liquefied gas, such as liquid nitrogen, liquid hydrogen, or liquid helium, to achieve the desired temperature within the cryogenic environment 310.

[0036]

[0042] Cryogenic system 315 includes quantum memory 325, which may have any suitable implementation as known to one of skill in the art. In some aspects, quantum memory 325 includes Josephson junctions operating as superconducting qubits. In some aspects, quantum information in the qubits can be stored, changed, and / or read by transmitting microwave photons to the qubits. Other implementations of quantum memory 325 are also contemplated.

[0037]

[0043] In some aspects, quantum memory 325 stores quantum information in multiple qubits. Each qubit is in a superposition of states (representing all possible combinations of configurations). Some or all of the multiple qubits may further exhibit quantum entanglement, in which case a change occurring to one qubit also affects one or more entangled qubits. Thus, multiple qubits can be used to represent complex multi-dimensional computational spaces.

[0038]

[0044] Alternative implementations of quantum system 315 are also contemplated. For example, quantum system 315 may include one or more quantum processes, one or more quantum networks, one or more quantum sensors, or one or more classical (i.e., non-quantum) cryogenic sensors.

[0039]

[0045] In some aspects, the quantum system 315 is communicatively coupled to one or more processors 335 that are separate from the quantum system 315. The one or more processors 335 may be located inside or outside the cryogenic environment 310. The one or more processors 335 may comprise any suitable implementation of a classical (i.e., non-quantum) processor(s). In some aspects, the one or more processors 335 comprise control circuitry that communicates control signals and / or data to the one or more quantum processors 320. For example, the control signals may be used to control characteristics of microwave photons used to interact with qubits of the quantum memory 325. The one or more processors 335 may receive measurement data from the one or more quantum processors 320. In some aspects, the one or more processors 335 are communicatively coupled to the cryogenic cooling system 305 and further communicate control signals and / or data to the cryogenic cooling system 305 to maintain the cryogenic environment 310. In some aspects, one or more processors 335 are communicatively coupled to one or more external networks and act as gateways for communicating with public and / or private networks (e.g., the cloud). In one non-limiting example, the quantum system 315 may be included in a quantum repeater that spans substantial distances.

[0040]

[0046] The quantum system 315 further comprises one or more charge sensors 330 operable to detect a change in charge of one or more charge islands of the quantum system 315. In some aspects, each of the one or more charge islands includes a respective one or more quantum dots. Each quantum dot is a semiconductor structure (e.g., Si or GaAs) of a size small enough to exhibit quantum mechanical properties, e.g., the semiconductor structure can trap individual electrons. In other words, each quantum dot operates as an "artificial atom." Although described with respect to quantum dot(s), other implementations of the one or more charge islands are contemplated. For example, the one or more charge islands may alternatively include one or more material defects, one or more grain boundaries, one or more microscopic surface features, or the like.

[0041]

[0047] In some aspects, each of the one or more charge sensors 330 includes one or more JJs 100 (FIG. 1) and / or one or more JJFETs 200 (FIG. 2). As described above, applying different values ​​of electrostatic potentials in the vicinity of a JJ changes its quantum tunneling properties. In some aspects, a JJ (whether implemented as a JJ 100 or a JJFET 200) included in the one or more charge sensors 330 is capacitively coupled to one or more charge islands according to a selected configuration, some examples of which are shown in FIGS. 4 and 5.

[0042]

[0048] By capacitively coupling one or more charge islands to the JJ in any of the selected configurations, a change in electron occupancy occurring in the one or more charge islands changes the critical current of the JJ. In some aspects, a bias current (e.g., a DC current) less than a first value of the critical current is supplied to the JJ. The first value of the critical current corresponds to a first charge state of the one or more charge islands. When a predefined change in charge occurs in the one or more charge islands (e.g., the electron occupancy of the one or more charge islands meets a predefined count), the change in charge reduces the critical current to a second value less than the bias current. Thus, the JJ transitions between a superconducting state and a normal state, presenting a resistance that causes a pulse in the output voltage of the JJ. The pulse in the output voltage may then be measured, allowing for a single-shot readout of the quantum system 315.

[0043]

[0049] Beneficially, the use of JJs enables a rapid, single-shot readout method for measuring charge occupancy within the quantum system 315. As the size of devices and systems shrinks to the atomic scale, the ability to rapidly measure the charge state within these systems frees up resources and accelerates operations utilizing these systems. Additionally, the JJs used in one or more charge sensors 330 (whether implemented as JJs 100 or JJFETs 200) operate natively in the cryogenic environment 310 that hosts the quantum system 315, providing more efficient utilization of the infrastructure required for the cryogenic environment 310.

[0044]

[0050] 4 illustrates an example device 400 having one or more charge islands 405-1, ..., 405-N capacitively coupled to a JJFET 410 in accordance with one or more aspects. Device 400 may be used in conjunction with any other aspects described herein. For example, device 400 may represent one example implementation of charge sensor 330 of FIG.

[0045]

[0051] The device 400 comprises a JJFET 410, which represents one embodiment of the JJFET 200. The device 400 further comprises one or more charge islands 405-1, ..., 405-N capacitively coupled to a gate (G) of the JJFET 410. In some aspects, each of the one or more charge islands 405-1, ..., 405-N includes a respective one or more quantum dots. In some aspects, as shown, each of the one or more charge islands 405-1, ..., 405-N includes a respective capacitor C1, ..., C2, which is connected to a respective capacitor C3, ..., C4, which is connected to a respective capacitor C5, ..., C6, which is connected to a respective capacitor C7, ..., C8, which is connected to a respective capacitor C9, ..., C10, which is connected to a respective capacitor C11, ..., C12, which is connected to a respective capacitor C13, ..., C14, which is connected to a respective capacitor C15, ..., C16, which is connected to a respective capacitor C17, ..., C18, which is connected to a respective capacitor C19, ..., C20, which is connected to a respective capacitor C21, ..., C22, which is connected to a respective capacitor C18, ..., C19, which is connected to a respective capacitor C21, ..., C22, which is connected to a respective capacitor C19, ..., C20, which is connected to a respective capacitor C21, ..., C22, which is connected to a respective capacitor C19, ..., C22, which is connected to a respective capacitor C19, ..., C22, which is connected to a respective capacitor C21 ... N The gate includes a plurality of charge islands coupled to the gate via a gate electrode. Although two charge islands are shown, any other number of charge islands (e.g., one, three, four, five or more) are contemplated.

[0046]

[0052] Capacitors C1,…,C N Capacitors C1, ..., C2 may be implemented as discrete elements within device 400, or may represent capacitances that exist between one or more charge islands 405-1, ..., 405-N that extend across a dielectric region and the gate of JJFET 410 (e.g., due to the manufacturing process or relative proximity). N may have any capacitance value suitable for detecting changes in charge occurring in one or more charge islands 405-1, ..., 405-N. In some aspects, C1, ..., C N have the same capacitance value (e.g., the effect of each charge island 405-1, ..., 405-N is weighted similarly). N Some or all of the charge islands C1, . . . , C2, . . . have different capacitance values. By weighting the effect of each charge island 405-1, . . . , 405-N differently, further information can be communicated to the measurement circuitry 425. In one non-limiting example, the capacitors C1, . . . , C3, . . . N have capacitance values ​​that increase in powers of 2, C1,…,C N The sum of the currents flowing through may effectively identify which (or more) of the charge islands 405-1, ..., 405-N have experienced a change in charge. Other encoding schemes are contemplated, which may include implementing charge islands 405-1, ..., 405-N with different characteristics.

[0047]

[0053] The apparatus 400 further includes a current source 415 coupled to one of the source (S) or drain (D) of the JJFET 410. As shown, the current source 415 is coupled to the drain of the JJFET 410. The current source 415 may have any suitable implementation, such as a MOSFET constant current source. The current source 415 provides a bias current (e.g., a DC current) through the JJFET 410 that is less than a first value of a critical current of the JJFET 410. The first value of the critical current corresponds to a first charge state of the one or more charge islands 405-1, ..., 405-N.

[0048]

[0054] Critical current I of JJFET410 c is related to the carrier density and carrier velocity according to the following equation: TIFF2025069068000002.tif21170Where, W is the device width, C g is the gate capacitance per unit area, V t is the threshold voltage, V g is the voltage applied to the gate.

[0049]

[0055] According to the equation for the resistive-capacitive shunt junction (RCSJ) model of the JJFET410, TIFF2025069068000003.tif23170This means that the sustained current through JJFET 410 (e.g., the bias current provided by current source 415) exceeds the critical current I c , a pulse occurs in the output voltage when the input voltage is greater than

[0050]

[0056] Thus, in some aspects, a predefined change in charge (e.g., resulting in a second charge state) on one or more of the charge islands 405-1,...,405-N reduces the critical current of the JJFET 410 to a second value less than the bias current. In this manner, the JJFET 410 transitions between a superconducting state and a normal conducting state.

[0051]

[0057] Measurement circuit 425 is coupled to the other of the source and drain of JJFET 410. In other words, current source 415 and measurement circuit 425 are located on opposite sides of JJFET 410. As shown, measurement circuit 425 is connected to the source of JJFET 410 and measures the output voltage of JJFET 410. When the critical current decreases below the bias current, JJFET 410 transitions to a normal conducting state, causing resistive losses in JJFET 410 and a pulse in the output voltage.

[0052]

[0058] The measurement circuit 425 may have any suitable implementation as known to one of ordinary skill in the art. In some aspects, the measurement circuit 425 includes an amplifier circuit for amplifying the output voltage of the JJFET 410. In some aspects, the measurement circuit 425 communicates signals to one or more processors 335 of FIG.

[0053]

[0059] The apparatus 400 further comprises a shunt resistor 420 coupled across and in parallel with the source and drain of the JJFET 410. The shunt resistor 420 operates to update a critical current of the JJFET 410 in response to a change in the charge state of the one or more charge islands 405-1, ..., 405-N. In some aspects, the shunt resistor 420 has a smaller resistance than the JJFET 410 exhibits while in a normal conducting phase, as this tends to provide a non-hysteretic overdamped voltage response. In some aspects, the current source 415 is controlled to vary a bias current based on the updated critical current. For example, the one or more processors 335 may communicate a control signal that sets the bias current based on the determined charge state of the one or more charge islands 405-1, ..., 405-N. In some aspects, the device 400 resets the charge state of one or more charge islands 405-1, . . . , 405-N, and the device 400 uses the shunt resistor 420 to restore the critical current to a first value.

[0054]

[0060] Thus, JJFET 410 may be used in conjunction with one or more charge islands 405-1, ..., 405-N in device 400 to provide fast and accurate measurements of the local charge state of quantum system 315. In some aspects, device 400 may obtain single shot measurements on the order of nanoseconds.

[0055]

[0061] 5 illustrates an example device 500 having one or more charge islands 405-1,...,405-N capacitively coupled to a node 510 between a pair of series-connected Josephson junctions 505-1, 505-2 in accordance with one or more aspects. The device 500 may be used in conjunction with any other aspects described herein. For example, the device 500 may represent one example implementation of the charge sensor 330 of FIG.

[0056]

[0062] The device 500 includes series-connected Josephson junctions 505-1, 505-2, each of which represents a multiple embodiment of the Josephson junction 100. The device 500 includes respective capacitors C1, . . . , C N , C1, ..., C2, .... The capacitors C1, ..., C3, .... The capacitors C2, ..., C4, .... The capacitors C1, ..., C5, .... The capacitors C2, ..., C6, .... The capacitors C3, ..., C7, .... The capacitors C4, ..., C8, .... The capacitors C5, ..., C9, .... N may be implemented as a discrete element within device 400, or may represent a capacitance that exists between one or more charge islands 405-1, ..., 405-N that extend across a dielectric region and node 510 (e.g., due to the manufacturing process or relative proximity).

[0057]

[0063] The apparatus 500 further comprises a current source 415 coupled to the JJ 505-2 opposite the node 510. The current source 415 provides a bias current (e.g., a DC current) through the JJs 505-1, 505-2 that is less than a first value of a critical current of the JJs 505-1, 505-2. The first value of the critical current corresponds to a first charge state of the one or more charge islands 405-1, ..., 405-N.

[0058]

[0064] The device 500 further comprises a measurement circuit 425 coupled to the JJ 505-1 on the other side of the node 510. In some aspects, a predefined change in charge (e.g., resulting in a second charge state) on one or more of the charge islands 405-1,...,405-N reduces the critical current of the JJs 505-1,505-2 to a second value less than the bias current. In this manner, the JJs 505-1,505-2 transition between a superconducting state and a normal conducting state. When the critical current decreases below the bias current, the JJs 505-1,505-2 transition to a normal conducting state, resulting in resistive losses in the JJs 505-1,505-2 and a pulse in the output voltage of the device 500. The apparatus 500 further includes a shunt resistor 420 coupled across and in parallel with the pair of JJs 505-1, 505-2, the shunt resistor 420 restoring the critical current of the JJs 505-1, 505-2 to a first value after a pulse occurs in the output voltage.

[0059]

[0065] Thus, JJs 505-1, 505-2 may be used in conjunction with one or more charge islands 405-1, ..., 405-N in device 500 to provide fast and accurate measurements of local charge states of quantum system 315. In some aspects, device 500 may obtain single shot measurements on the order of nanoseconds. Furthermore, the use of JJs 505-1, 505-2 with one or more charge islands 405-1, ..., 405-N significantly reduces manufacturing challenges for charge sensing.

[0060]

[0066] 6 illustrates a plot of current-voltage (IV) characteristics of a Josephson junction for different charge states according to one or more embodiments. The features of FIG. 6 may be used in conjunction with any other embodiments described herein. For example, the plot may illustrate an example operation of the device 400 of FIG. 4 or the device 500 of FIG. 5.

[0061]

[0067] More specifically, graph 600 includes plot 605 representing a bias current provided by current source 415. In some aspects, the bias current is less than a first value of a critical current of the JJFET or JJ. As shown, the bias current is approximately 45 microamps (μA). Graph 600 further includes plot 610 representing the IV characteristics of the JJFET or JJ at a first charge state and plot 615 representing the IV characteristics of the JJFET or JJ at a second charge state.

[0062]

[0068] In plot 610, the JJFET or JJ is operated in the superconducting state at the bias current, and voltage point 620 shows an output voltage of approximately 0. In plot 615, the JJFET or JJ is operated in the normal state at the bias current (in other words, the bias current is above the critical current), and voltage point 625 shows an output voltage of approximately 20 millivolts (mV).

[0063]

[0069] 7 is a method 700 of charge sensing in a quantum system according to one or more aspects. Method 700 may be used in conjunction with other embodiments, such as performed using apparatus 400 of FIG. 4 or apparatus 500 of FIG. 5.

[0064]

[0070] Method 700 begins at block 705, where the apparatus provides a bias current through a Josephson junction, the bias current being less than a first value of a critical current of the Josephson junction. In some aspects, the JJ is implemented as a two-terminal device, such as JJ 100 of FIG. 1. In other aspects, the JJ is implemented as a three-terminal device, such as JJFET 200 of FIG.

[0065]

[0071] At block 715, the apparatus measures an output voltage of the Josephson junction. The measurement of the output voltage is responsive to a change in charge of one or more charge islands coupled to the Josephson junction. In some embodiments, the change in charge is determined at a node between the series connected JJs. In other embodiments, the change in charge is determined at the gate of the JJFET. The change in charge reduces the critical current to a second value less than the bias current.

[0066]

[0072] At block 725, the device updates the critical current to a second value in response to a change in charge of one or more charge islands using a shunt resistor coupled across and in parallel with the Josephson junction. In some aspects, method 700 proceeds along branch 730 back to block 705, where the device provides a bias current less than the (updated) critical current. In this manner, in response to a change in charge, the critical current settles to the updated value (due to the shunt resistor) and the device updates the bias current to be less than the updated value.

[0067]

[0073] In some aspects, the method 700 proceeds to block 735, where the apparatus resets the charge state of one or more charge islands. In block 745, the apparatus restores the critical current to the first value using a shunt resistor. The method 700 ends after completing block 745.

[0068]

[0074] As will be appreciated by one of ordinary skill in the art, aspects described herein may be embodied as a system, method, and / or computer program product. Accordingly, aspects may take the form of entirely hardware aspects, entirely software aspects (including firmware, resident software, microcode, etc.), or aspects combining software and hardware aspects, all of which may be broadly referred to herein as "circuits," "modules," or "systems." Additionally, aspects described herein may take the form of a computer program product embodied in one or more computer-readable storage medium(s) having computer-readable program code embodied therein.

[0069]

[0075] The program code embodied in the computer readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, etc., or any suitable combination thereof.

[0070]

[0076] Computer program code for carrying out operations of aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as the "C" programming language or similar. The program code may run entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider).

[0071]

[0077] Aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to aspects of the present disclosure. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose or special purpose computer, or other programmable data processing device, to produce a machine. These instructions, executed via the processor of the computer or other programmable data processing device, thereby create means for performing the function / acts identified in the block(s) of the flowcharts and / or block diagrams.

[0072]

[0078] The computer program instructions may also be stored on a computer-readable medium that may direct a computer, other programmable data processing apparatus, or other device to function in a particular manner, whereby the instructions stored in the computer-readable medium produce an article of manufacture. The instructions include instructions that implement the function / act identified in the flowchart and / or block diagram block(s).

[0073]

[0079] The computer program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be executed on the computer, other programmable data processing apparatus, or other device to generate a computer-implemented process, whereby the instructions executing on the computer, other programmable data processing apparatus, or other device provide a process for implementing the functions / acts identified in the flowchart and / or block diagram block(s).

[0074]

[0080] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various aspects of the disclosure. As such, each block in the flowcharts and block diagrams may represent a module, a segment, or a portion of code, including one or more executable instructions for implementing a particular logical function(s). In some alternative implementations, the functions shown in the blocks may not be performed in the order described in the figures. For example, in practice, two blocks shown in succession may be executed substantially simultaneously, or the blocks may be executed in reverse or out of order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a special-purpose hardware-based system that performs a particular function or function, or by a combination of special-purpose hardware and computer instructions.

[0075]

[0081] While the foregoing is directed to aspects of the disclosure, other and further aspects of the disclosure may be devised without departing from the basic scope thereof, the scope of which is defined by the following claims.

Claims

1. A method (700) of charge sensing in a quantum system (315), comprising: providing (705) a bias current (605) through a Josephson junction (100, 200, 410, 505-1, 505-2), the bias current being less than a first value of a critical current of the Josephson junction; and measuring (715) an output voltage of the Josephson junction; In response to a change in charge of one or more charge islands (405-1, ..., 405-N) coupled to the Josephson junction, the critical current decreases to a second value less than the bias current, causing a voltage drop across the Josephson junction.

2. 10. The method of claim 1, wherein each of the one or more charge islands comprises a respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more microscopic surface features.

3. The one or more charge islands include a plurality of charge islands (405-1, ..., 405-N), each of which has a respective capacitor (C １ ,…,C Ｎ 2. The method of claim 1 , wherein the Josephson junction is coupled to the first junction via a first insulating layer.

4. The method of claim 3 , wherein some or all of the capacitors corresponding to the plurality of charge islands have different capacitance values.

5. 2. The method of claim 1, further comprising updating (725) the critical current of the Josephson junction to a second value in response to a change in the charge of the one or more charge islands using a shunt resistor (420) coupled across and in parallel with the Josephson junction.

6. the Josephson junction is contained within a Josephson junction field effect transistor (JJFET) (200, 410); the one or more charge islands are capacitively coupled to a gate (G) of the JJFET; 2. The method of claim 1, wherein the bias current is provided by a current source (415) coupled to a source (S) or a drain (D) of the JJFET.

7. the Josephson junctions are contained within a pair of series-connected Josephson junctions (100, 505-1, 505-2); the one or more charge islands are capacitively coupled between the pair of Josephson junctions (510); The method of claim 1 , wherein the bias current is provided by a current source (415) coupled to one of the pair of the Josephson junctions.

8. An apparatus (400), comprising: Josephson junction field effect transistor (JJFET) (200, 410), one or more charge islands (405-1, ..., 405-N) capacitively coupled to the gate (G) of the JJFET; and a current source (415) coupled to one of the source (S) or drain (D) of the JJFET for providing a bias current (605) less than a first value of a critical current of the JJFET; The apparatus, wherein a predetermined change in charge on the one or more charge islands reduces the critical current to a second value less than the bias current.

9. 10. The device of claim 8, wherein each of the one or more charge islands comprises a respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more microscopic surface features.

10. The one or more charge islands include a plurality of charge islands (405-1, ..., 405-N), each of which has a respective capacitor (C １ ,…,C Ｎ 9. The apparatus of claim 8, wherein said gate is coupled to said transistor via a first transistor.

11. The apparatus of claim 10 , wherein some or all of the capacitors corresponding to the plurality of charge islands have different capacitance values.

12. 9. The apparatus of claim 8, further comprising a shunt resistor (420) coupled across and in parallel with the source and the drain of the JJFET.

13. 9. The apparatus of claim 8, further comprising a measurement circuit coupled to the other of the source or the drain of the JJFET.

14. 14. The apparatus of claim 13, wherein the measurement circuitry includes an amplifier circuit for amplifying an output voltage of the JJFET.

15. An apparatus (500), comprising: A pair of series-connected Josephson junctions (100, 505-1, 505-2), one or more charge islands (405-1, ..., 405-N) capacitively coupled to a node (510) between the pair of Josephson junctions; and a current source (415) coupled to a first Josephson junction of the pair for providing a bias current (605) less than a first value of an effective critical current of the Josephson junction; The apparatus, wherein a predetermined change in charge on the one or more charge islands reduces the effective critical current to a second value less than the bias current.

16. 16. The device of claim 15, wherein each of the one or more charge islands comprises a respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more microscopic surface features.

17. The one or more charge islands include a plurality of charge islands (405-1, ..., 405-N), each of which has a respective capacitor (C １ ,…,C Ｎ 16. The device of claim 15, wherein the pair of said Josephson junctions are coupled between each other via a first insulating layer.

18. 20. The apparatus of claim 17, wherein some or all of the capacitors corresponding to the plurality of charge islands have different capacitance values.

19. 16. The apparatus of claim 15, further comprising a shunt resistor (420) coupled across and in parallel with the pair of Josephson junctions.

20. 16. The apparatus of claim 15, further comprising a measurement circuit coupled to a second Josephson junction of the pair.

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