Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes a memory module. The memory module includes a first memory cell, a first wire, a second wire including metal oxide, and a third wire. The first memory cell includes a readout transistor and a rewriting transistor. The first wire includes a region functioning as a back gate of the readout transistor and a region where the second wire functions as a conductor. The second wire includes a region functioning as a channel formation region of the readout transistor, a region functioning as a back gate of the rewriting transistor, and a region where the third wire functions as a conductor. The third wire includes a region functioning as the channel formation region of the rewriting transistor and a region functioning as a conductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in the present specification and the like relates to an object, a driving method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like that can function by utilizing semiconductor characteristics. As one example, a semiconductor element such as a transistor or a diode is a semiconductor device. As another example, a circuit having a semiconductor element is a semiconductor device. As yet another example, a device including a circuit having a semiconductor element is a semiconductor device. [Background technology]

[0004] Electronic devices having semiconductor devices, such as mobile devices such as smartphones, tablets, and e-books, personal computers, and servers, are required to handle large amounts of data. Therefore, the semiconductor devices are required to have large memory capacities, low power consumption, and high processing speeds.

[0005] In particular, in recent years, the amount of data handled by the electronic devices described above has increased as applications that handle high-definition images, videos, sounds, and the like have increased. Therefore, semiconductor devices with large storage capacities are in demand. Patent Document 1 discloses a semiconductor device in which memory cells are stacked three-dimensionally. In addition, in order to realize a semiconductor device having a large storage capacity without changing the size of the semiconductor device chip, a technology for miniaturizing the circuits of the semiconductor device is required. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2008-258458 A Summary of the Invention [Problem to be solved by the invention]

[0007] Applications running on electronic devices are required to comfortably handle large amounts of data such as images and audio by connecting to the Internet or a network. In addition, for portable electronic devices such as mobile devices, reducing power consumption is an issue in order to enable long-term use. In electronic devices, power reduction techniques such as power gating can be used to reduce power consumption. However, using power reduction techniques such as power gating poses a problem in that data in use must be evacuated.

[0008] For example, in a NAND type flash memory, which is known as a semiconductor device, data other than the address specified for rewriting data must be updated. Therefore, in a NAND type flash memory, a long processing time is required to write a large amount of data, and power consumption increases according to the amount of data. In addition, a high potential is required to write data, which results in high power consumption.

[0009] In view of the above problems, an object of one embodiment of the present invention is to provide a storage device with a novel structure. Alternatively, an object of one embodiment of the present invention is to provide a storage device with reduced power consumption. Alternatively, an object of one embodiment of the present invention is to provide a storage device with a reduced rewrite time.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device having a memory module. The memory module has a first memory cell, a first wiring, a second wiring, and a third wiring. Note that the second wiring and the third wiring contain metal oxide. The first memory cell has a first read transistor and a first rewrite transistor. The first wiring has a region that functions as a back gate of the first read transistor and a region that causes the second wiring to function as a conductor. The second wiring has a region that functions as a channel formation region of the first read transistor, a region that functions as a back gate of the first rewrite transistor, and a region that causes the third wiring to function as a conductor. The third wiring has a region that functions as a channel formation region of the first rewrite transistor and a region that functions as a conductor.

[0012] In the above configuration, it is preferable that the first rewrite transistor is formed in the same opening as the first read transistor, and the second wiring including the channel formation region of the first read transistor is formed inside the third wiring including the channel formation region of the first rewrite transistor with an insulating layer interposed therebetween.

[0013] An electronic device having the above-described semiconductor device and a housing is preferable. Effect of the Invention

[0014] According to one embodiment of the present invention, it is possible to provide a storage device with a novel structure, a storage device with reduced power consumption, or a storage device with reduced rewrite time.

[0015] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. The effects not mentioned in this section can be derived by a person skilled in the art from the description of the specification or drawings, etc., and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0016] [Figure 1] 1A to 1C are circuit diagrams showing configuration examples of a semiconductor device. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration example of the semiconductor device. [Diagram 3] FIG. 3 is an equivalent circuit diagram of a memory string. [Figure 4] FIG. 4 is an equivalent circuit diagram of a memory string. [Diagram 5] FIG. 5 is an equivalent circuit diagram of a memory string. [Figure 6] FIG. 6 is an equivalent circuit diagram of a memory string. [Figure 7] FIG. 7 is a timing chart showing an example of the operation of the semiconductor device. [Figure 8] FIG. 8 is a timing chart showing an example of the operation of the semiconductor device. [Figure 9] FIG. 9 is a timing chart showing an example of the operation of the semiconductor device. [Figure 10] FIG. 10 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 11] FIG. 11 is a timing chart showing an example of the operation of the semiconductor device. [Figure 12] FIG. 12 is a timing chart showing an example of the operation of the semiconductor device. [Figure 13] 13A and 13B are block diagrams illustrating an example of a storage device. [Figure 14] FIG. 14 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 16] FIG. 16 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 17] 17A and 17B are a top view and a cross-sectional view for explaining a configuration example of a semiconductor device. [Figure 18] 18A and 18B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Figure 19] 19A and 19B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Figure 20] 20A and 20B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Figure 21] 21A and 21B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Figure 22] 22A and 22B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Diagram 23] 23A and 23B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Figure 24] 24A and 24B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Diagram 25] 25A and 25B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Figure 26] 26A and 26B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Figure 27]27A and 27B are cross-sectional views for explaining a manufacturing example of a semiconductor device. [Figure 28] FIG. 28 is a cross-sectional view for explaining a manufacturing example of a semiconductor device. [Figure 29] FIG. 29 is a cross-sectional view for explaining a manufacturing example of a semiconductor device. [Diagram 30] FIG. 30 is a cross-sectional view for explaining a manufacturing example of a semiconductor device. [Diagram 31] FIG. 31 is a cross-sectional view for explaining a semiconductor device. [Diagram 32] 32A and 32B are cross-sectional views for explaining a semiconductor device. [Diagram 33] 33A and 33B are cross-sectional views for explaining a semiconductor device. [Diagram 34] FIG. 34 is a diagram illustrating a semiconductor device. [Diagram 35] FIG. 35 is a diagram illustrating an example of the operation of the semiconductor device. [Diagram 36] FIG. 36 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 37] FIG. 37 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 38] FIG. 38 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 39] FIG. 39 is a diagram illustrating an example of the operation of the semiconductor device. [Diagram 40] FIG. 40 is a diagram illustrating an example of the operation of the semiconductor device. [Diagram 41] FIG. 41 is a block diagram illustrating the CPU. [Diagram 42] 42A to 42E are perspective views showing examples of electronic devices. [Diagram 43] 43A to 43F are perspective views showing examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] (Embodiment 1) In this embodiment mode, a semiconductor device in which the time required for rewriting a memory cell is reduced will be described with reference to FIGS.

[0018] First, the circuit configuration of the semiconductor device will be described with reference to FIG. 1A. The semiconductor device shown in FIG. 1A is a memory module 10 having n memory cells. The memory module 10 has memory cells MC[1] to MC[n], a selection transistor DTr1, a selection transistor DTr2, a selection transistor DTr3, a wiring WWL_D, a wiring RWL_D1, a wiring RWL_D2, a wiring WWL[1] to WWL[n], a wiring RWL[1] to RWL[n], a wiring WBL1, a wiring RBL1, and a wiring RBL2. Note that the wiring WWL (wirings WWL[1] to WWL[n]) functions as a rewrite word line, the wiring RWL (wirings RWL[1] to RWL[n]) functions as a read word line, the wiring WBL1 functions as a rewrite bit line, and the wirings RBL1 and RBL2 function as read bit lines. n is an integer of 2 or more.

[0019] Each of the memory cells MC[1] to MC[n] includes a transistor WTr and a transistor RTr. Note that the transistors WTr (transistors WTr[1] to WTr[n]) and the transistors RTr (transistors RTr[1] to RTr[n]) illustrated in FIG. 1A are preferably transistors with small off-currents. By using transistors with small off-currents for the transistors WTr and RTr, the independence of data held in adjacent memory nodes can be ensured. Furthermore, the transistors WTr and RTr are preferably transistors with backgates. The thresholds of the transistors WTr and RTr can be controlled by applying a potential to the backgate.

[0020] FIG. 1A shows an example in which memory cells MC[1] to MC[n] are connected in series. It is preferable that a selection transistor DTr1 for rewriting data stored in the memory cells is connected to one end of the memory cells MC[1] to MC[n] connected in series. It is also preferable that a selection transistor DTr2 for reading data stored in the memory cells is connected to one end of the memory cells MC[1] to MC[n] connected in series, and a selection transistor DTr3 for reading data stored in the memory cells is connected to the other end. FIG. 1A shows an example in which the selection transistor DTr1 and the selection transistor DTr2 are connected to the memory cell MC[1].

[0021] Each memory cell has a capacitance CS and a memory node in addition to a transistor WTr and a transistor RTr. The transistor WTr functions as a write transistor, and the transistor RTr functions as a read transistor.

[0022] The memory node is formed by electrically connecting one of the source or drain of the transistor WTr, the gate of the transistor RTr, and one of the electrodes of the capacitance CS. The gate of the transistor WTr is electrically connected to the wiring WWL, and the other electrode of the capacitance CS is electrically connected to the wiring RWL. For example, the other of the source or drain of the transistor WTr[1] of the memory cell MC[1] is electrically connected to the memory node of the memory cell MC[2] that is connected in series with the memory cell MC[1].

[0023] One of the source or drain of the selection transistor DTr1 is electrically connected to the wiring WBL1, the other of the source or drain of the selection transistor DTr1 is electrically connected to the memory node of the memory cell MC[1], and the gate of the selection transistor DTr1 is electrically connected to the wiring WWL_D.

[0024] The other of the source and drain of the transistor WTr[n] of the memory cell MC[n] is electrically connected to the wiring WBL1. That is, one end of the series of memory cells connected in series is electrically connected to the other end of the series of memory cells via the selection transistor DTr1 and the wiring WBL1.

[0025] One of the source or drain of the selection transistor DTr2 is electrically connected to the wiring RBL2, the other of the source or drain of the selection transistor DTr2 is electrically connected to one of the source or drain of the transistor RTr[1] of the memory cell MC[1], and the gate of the selection transistor DTr2 is electrically connected to the wiring RWL_D1.

[0026] The other of the source or the drain of the transistor RTr[1] in the memory cell MC[1] is electrically connected to one of the source or the drain of the transistor RTr[2] in the memory cell MC[2] connected in series.

[0027] The other of the source or drain of the transistor RTr[n] in the memory cell MC[n] is electrically connected to the source or drain of the selection transistor DTr3. The other of the source or drain of the selection transistor DTr3 is electrically connected to the wiring RBL1. The gate of the selection transistor DTr3 is electrically connected to the wiring RWL_D2. That is, the wiring RBL1 is electrically connected to the transistor RTr in the memory cell connected in series via the selection transistor DTr2, and the transistor RTr[n] in the memory cell MC[n] is electrically connected to the wiring RBL2 via the selection transistor DTr2.

[0028] As an example, the backgate of the transistor WTr[1] in the memory cell MC[1] is electrically connected to a node where the other of the source or drain of the transistor RTr[1] in the memory cell MC[1] is connected to one of the source or drain of the transistor RTr[2] in the memory cell MC[2]. The backgate of the selection transistor DTr1 is electrically connected to a node where the other of the source or drain of the selection transistor DTr2 is connected to one of the source or drain of the transistor RTr[1] in the memory cell MC[1].

[0029] 1A is electrically connected to the back gates of the transistors RTr[1] to RTr[n] of the memory cells MC[1] to MC[n]. The selection transistors DTr2 and DTr3 preferably have back gates similar to the transistor WTr[n], and as shown in FIG. 1A, the back gates of the selection transistors DTr2 and DTr3 are preferably electrically connected to the wiring BGL.

[0030] In the configuration of the memory module 10 described above, data in any one of the memory cells MC[1] to MC[n] can be rewritten via the transistor WTr connected in series and the memory node. However, to rewrite data in the memory cell MC[j] (j is an integer between 1 and n) close to the memory cell MC[1], it is preferable that data is provided from the wiring WBL1 via the selection transistor DTr1, and to rewrite data in the memory cell MC[j] close to the memory cell MC[n], it is preferable that data is provided from the wiring WBL1 connected to the memory cell MC[n].

[0031] In the configuration of the memory module 10 described above, data of any one of the memory cells MC[1] to MC[n] can be read via the transistor RTr connected in series. However, to read data of the memory cell MC[j] close to the memory cell MC[1], it is preferable that the read data is provided to the wiring RBL1 via the selection transistor DTr2, and to read data of the memory cell MC[j] close to the memory cell MC[n], it is preferable that the read data is provided to the wiring RBL2 via the selection transistor DTr3 connected to the memory cell MC[n].

[0032] The channel formation portion of the selection transistor DTr1, the memory node, and the channel formation region of the transistor WTr are semiconductor layers containing the same metal oxide. However, the semiconductor layer containing the metal oxide can be made to function as wiring by adding impurities including hydrogen or the like to lower the resistance value. The semiconductor layer containing the metal oxide can be made to function as wiring by applying a positive electric field to lower the resistance value. Therefore, the semiconductor layer containing the metal oxide can be called wiring in other words.

[0033] The channel formation regions of the select transistors DTr2 and DTr3, the channel formation region of the read transistor RTr, and the connection nodes between the transistors RTr are semiconductor layers containing metal oxide. Therefore, the semiconductor layers containing metal oxide can be referred to as wiring.

[0034] The channel formation regions of the transistors WTr and RTr preferably contain, for example, a metal oxide selected from one or more of indium, an element M (the element M is, for example, aluminum, gallium, yttrium, tin, etc.), and zinc. In this case, the metal oxide functions as a wide-gap semiconductor, and therefore a transistor in which the metal oxide is contained in the channel formation region has a characteristic of having a very low off-current. By applying a transistor with a low off-current characteristic to the transistor WTr that controls data retention, data can be retained in the memory cell MC for a long time. This can reduce the number of times the retained data is refreshed, thereby reducing the power consumption of the semiconductor device. Note that a transistor containing a metal oxide in its channel formation region can be called an OS transistor.

[0035] In addition, it is preferable to use a material with high field effect mobility for the channel formation region of the transistor RTr. By using such a transistor, the semiconductor device can operate faster. For example, the material contained in the channel formation region of the transistor RTr can include a semiconductor material such as a metal oxide selected from one or more of indium, element M (element M is, for example, aluminum, gallium, yttrium, tin, etc.), and zinc, or silicon.

[0036] A memory module 10 having a circuit configuration different from that of FIG. 1A will be described with reference to FIG. 1B. The wiring BGL shown in FIG. 1B is electrically connected to the back gates of the transistors WTr and RTr of the memory cells MC[1] to MC[n]. The thresholds of the transistors WTr and RTr can be controlled by applying a potential to the back gates.

[0037] Unlike the example shown in FIG. 1B, the memory module 10 may be configured such that the wiring BGL is independently electrically connected to the back gates of the transistors WTr and RTr included in the memory cells MC[1] to MC[n], and each of the wirings supplies a different potential.

[0038] A memory module 10 having a circuit configuration different from that of Fig. 1B will be described with reference to Fig. 1C. In Fig. 1C, the transistor WTr or the transistor RTr is a transistor that is not provided with a back gate.

[0039] For example, by using metal oxide for the channel formation regions of the transistors WTr and RTr, the transistors WTr can be formed in the same opening as the transistor RTr. The wiring including the channel formation region of the transistor RTr is preferably formed inside the wiring including the channel formation region of the transistor WTr with an insulating layer interposed therebetween. Note that it is preferable that a plurality of transistors WTr and transistors RTr are formed so as to alternately overlap in one opening. Note that this structure will be described in detail with reference to FIGS. 14 to 29.

[0040] The transistors WTr and RTr can be formed on a silicon substrate. By using metal oxide for the channel forming regions of the transistors WTr and RTr, the memory module 10 can be formed above the transistors formed on the silicon substrate. Therefore, when providing a semiconductor device with a high information density per unit area, it is easy to realize it by forming a plurality of transistors WTr and RTr alternately overlapping in one opening.

[0041] Furthermore, when it is desired to reduce production costs by simplifying the manufacturing process, a plurality of transistors WTr and transistors RTr are formed in a planar manner. Note that the manufacturing process can be simplified by simultaneously forming the transistors WTr and the transistors RTr on a silicon substrate, and circuits having different functions can be mounted on the silicon substrate. Since a memory module including the transistors WTr and the transistors RTr can be formed on the circuit, it is suitable for mounting embedded memories, etc. Furthermore, by configuring a memory module on the circuit, the mounting space can be reduced.

[0042] The semiconductor device shown in FIG. 2 is configured by arranging m columns of memory modules 10 shown in FIG. 1A as one column, and electrically connecting the wiring RWL and the wiring WWL to share the memory cells MC in the same row. That is, the semiconductor device shown in FIG. 2 is a semiconductor device that can be expressed two-dimensionally with n rows and m columns, and has memory cells MC[1,1] to MC[m,n]. Although not shown in FIG. 2 for the sake of simplicity, the semiconductor device can have three-dimensional memory cells MC[1,1,1] to MC[m,n,d] by considering the depth direction. In the second embodiment, a detailed description will be given of an example in which the semiconductor device has three-dimensional memory cells MC[1,1,1] to MC[m,n,d]. m, n, or d is an integer of 2 or more.

[0043] The semiconductor device shown in Figure 2 has wiring WWL_D, wiring RWL_D1, wiring RWL_D2, wiring RWL[1] to wiring RWL[n], wiring WWL[1] to wiring WWL[n], wiring RBL1[1] to wiring RBL1[m], wiring RBL2[1] to wiring RBL2[m], wiring WBL1[1] to wiring WBL1[m], and wiring BGL[1] to wiring BGL[m].

[0044] Specifically, the other electrode of the capacitance CS of the memory cell MC[i,j] (not shown) is electrically connected to the wiring RWL[j], and the gate of the transistor WTr[i,j] of the memory cell MC[i,j] is electrically connected to the wiring WWL[j]. The wiring WBL1[i] is electrically connected to one of the source or drain of the selection transistor DTr1[i] and the other of the source or drain of the transistor WTr[i,n] of the memory cell MC[i,n]. The wiring RBL1[i] is electrically connected to the other of the source or drain of the transistor RTr[i,n] of the memory cell MC[i,n]. The wiring RBL2[i] is electrically connected to one of the source or drain of the transistor RTr of the memory cell MC[i,1]. i is an integer between 1 and m, and j is an integer between 1 and n.

[0045] 3, the transistor WTr, the transistor RTr, and the capacitance element CS of the memory cell MC[1] are shown as the transistor WTr[1], the transistor RTr[1], and the capacitance element CS[1], respectively. The transistors WTr, the transistors RTr, and the capacitance elements CS of the memory cells MC[2] to MC[4] are also shown in the same manner.

[0046] The number of memory cells MC included in the memory module 10 is not limited to 4. If the number of memory cells MC included in the memory module 10 is n, n may be an integer of 2 or more.

[0047] In addition, "a configuration in which multiple memory cells MC are connected in series" refers to a configuration in which the drain (or source) of transistor WTr[k] included in memory cell MC[k] (k is an integer greater than or equal to 1 and less than or equal to n-1) is electrically connected to the source (or drain) of transistor WTr[k+1] included in memory cell MC[k+1], and the drain (or source) of transistor RTr[k] included in memory cell MC[k] is electrically connected to the source (or drain) of transistor RTr[k+1] included in memory cell MC[k+1].

[0048] The semiconductor in which the channels of the transistors WTr and RTr are formed may be a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either alone or in combination. Examples of the semiconductor material include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0049] Note that the semiconductor used in the transistor may be a stack of semiconductors. When semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used.

[0050] In particular, the transistor WTr is preferably an OS transistor using an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed. An oxide semiconductor has a band gap of 2 eV or more, and therefore has an extremely small off-state current. When an OS transistor is used for the transistor WTr, charge written to the node ND (also referred to as a "storage node") can be held for a long period of time. When an OS transistor is used for the transistor WTr, the memory cell MC can be called an "OS memory." In addition, a memory module 10 including the memory cell MC can also be called an "OS memory."

[0051] A NAND type storage device that includes an OS memory is also called an "OS NAND type" or "OS NAND type storage device." Additionally, an OS NAND type storage device that has multiple OS memories stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0052] The transistor RTr may be a transistor using silicon in a semiconductor layer in which a channel is formed (also referred to as a "Si transistor"). The transistor RTr may be a Si transistor, and the transistor WTr may be an OS transistor. FIG. 4 shows an equivalent circuit diagram of the memory module 10 in which the transistor WTr is an OS transistor and the transistor RTr is a Si transistor.

[0053] The OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered as a non-volatile memory.

[0054] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0055] In addition, since OS memory writes charge to a node via an OS transistor, it does not require the high voltage required for conventional flash memory, and can achieve high-speed write operations. In addition, OS memory does not require the erase operation before rewriting data, which is performed in flash memory. In addition, since no charge is injected or extracted from the floating gate or charge trapping layer, OS memory can write and read data an unlimited number of times. OS memory is less susceptible to deterioration and is highly reliable compared to conventional flash memory.

[0056] In addition, the OS memory does not involve structural changes at the atomic level, as in magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), etc. Therefore, the OS memory has better rewrite endurance than the magnetoresistive random access memory and the resistive random access memory.

[0057] Moreover, the off-current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. Moreover, the on-current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory is stable in operation even in a high-temperature environment, and is highly reliable. Moreover, the OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that is stable in operation even in a high-temperature environment and has good reliability can be realized.

[0058] Note that, depending on the purpose or application, a Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr as shown in Fig. 5. Also, depending on the purpose or application, a Si transistor may be used as both the transistor WTr and the transistor RTr as shown in Fig. 6.

[0059] By providing a plurality of memory cells MC consecutively in the Z direction, as in the memory module 10, the storage capacity per unit area can be increased.

[0060] The structure of data stored in the memory module of the semiconductor device shown in Fig. 2 is preferably expressed in bits, which are the minimum unit of data width. As an example, the operation of rewriting data in the first, second, n-1th, and nth rows will be described with reference to the timing chart of Fig. 7.

[0061] At time T11, the wiring WWL_D is supplied with "H", so that the selection transistors DTr1[1] to DTr1[m] are turned on. Furthermore, the wiring WWL[1] is supplied with "H", so that the transistors WTr in the memory cells MC[1,1] to MC[m,1] are turned on. The wirings WBL1[1] to WBL1[m] can supply data D[2] to the memory nodes of the memory cells MC[1,2] to MC[m,2] via the selection transistors DTr1[1] to DTr1[m]. At this time, the data D[2] is also supplied to the memory nodes of the memory cells MC[1,1] to MC[m,1]. The data D is preferably digital data having a data width of m bits. Alternatively, the data D may be analog data. Note that the analog data is preferably controlled by a potential. The amount of data that can be stored in a semiconductor device can be dramatically improved by handling analog data with different bits.

[0062] At time T12, the wiring WWL[1] is supplied with "L", turning off the transistors WTr of the memory cells MC[1,1] to MC[m,1]. Thus, data D[2] is held in the memory nodes of the memory cells MC[1,2] to MC[m,2]. Furthermore, the data D[1] supplied to the wirings WBL1[1] to WBL1[m] can rewrite the data in the memory nodes of the memory cells MC[1,1] to MC[m,1] via the selection transistors DTr1[1] to DTr1[m].

[0063] At time T13, the wiring WWL_D is applied with “L”, turning off the selection transistors DTr1[1] to DTr1[m]. Thus, data D[1] is held in the memory nodes of the memory cells MC[1,1] to MC[m,1].

[0064] At time T14, the wiring WWL[n-1] is supplied with "H" to turn on the transistors WTr in the memory cells MC[1,n-1] to MC[m,n-1]. The wiring WWL[n] is supplied with "H" to turn on the transistors WTr in the memory cells MC[1,n] to MC[m,n]. The data D[n-1] supplied to the wirings WBL1[1] to WBL1[m] can rewrite the data in the memory nodes of the memory cells MC[1,n-1] to MC[m,n-1] via the memory nodes of the memory cells MC[1,n] to MC[m,n].

[0065] At time T15, the wiring WWL[n-1] is supplied with "L," turning off the transistors WTr in the memory cells MC[1,n-1] to MC[m,n-1]. Thus, data D[n-1] is held in the memory nodes of the memory cells MC[1,n-1] to MC[m,n-1]. Furthermore, the wirings WBL1[1] to WBL1[m] can supply data D[n] to the memory nodes of the memory cells MC[1,n] to MC[m,n].

[0066] At time T16, the wiring WWL[n] is applied with "L", turning off the transistors WTr in the memory cells MC[1,n] to MC[m,n]. Thus, the data D[n] is held in the memory nodes of the memory cells MC[1,n] to MC[m,n].

[0067] During the period from time T10 to time T17, when "L" is applied to the wiring WWL_D and the wiring WWL[n], as an example, the section sandwiched between the selection transistor DTr1[1,n] and the transistor WTr[1,n] can be put into a floating state.

[0068] In the period from time T10 to time T17, "L" is applied to the wirings RWL_D1 and RWL_D2. As an example, the section between the selection transistor DTr2[1] and the selection transistor DTr3[1] can be set to a floating state. Since the potential applied to the wirings RBL1 and RBL2 does not affect the memory module, the wirings RBL1 and RBL2 can be set to a floating state. Therefore, the power applied to the wirings RBL1 and RBL2 can be reduced. Alternatively, any potential may be applied to the wirings RBL1 and RBL2.

[0069] In a NAND flash memory, in order to update any one memory cell of a memory module in which memory cells are connected in series, it is necessary to update the data in all rows of the memory module. However, in the configuration shown in this embodiment, data can be rewritten from any row of the memory module, so data can be rewritten at high speed.

[0070] Next, an example will be described in which a semiconductor device has a plurality of memory modules connected by wirings WWL, RWL, and WWL_D, and the structure of stored data has a data width of m bits. As an example, the operation of rewriting data in the first, second, third, n-1th, and nth rows will be described with reference to the timing chart of FIG.

[0071] The basic operation is the same as that described in FIG. 7, so the description will be omitted, and in FIG. 8, the difference from FIG. 7 will be described. As an example, in FIG. 8, the rewrite of data in the third row will be described. In FIG. 8, data D[3] is held in memory cells MC[1,3] to MC[m,3] as data in the third row during the period from time T21 to time T22. In a memory module having multiple rows, it is preferable to access an arbitrary rewrite target row from the closer side of either the memory cell MC in the first row to which the selection transistor DTr1 is connected or the memory cell MC in the nth row. The rewrite time of the memory cell corresponds to the number of rows up to the arbitrary rewrite target row. Therefore, the rewrite time can be shortened by accessing the arbitrary rewrite target row from the closer side.

[0072] 8, a plurality of memory cells are arranged in m columns. Therefore, data to be rewritten is simultaneously rewritten by data provided to the wirings WBL1[1] to WBL1[m]. That is, in the configuration shown in this embodiment, the semiconductor device can be said to be a memory device having a data width of m bits (m bit / width) for any address.

[0073] In the period from time T20 to time T28, "L" is applied to the wirings RWL_D1 and RWL_D2. As an example, the section between the selection transistor DTr2[1] and the selection transistor DTr3[1] can be set to a floating state. Since the potential applied to the wirings RBL1 and RBL2 does not affect the memory module, the wirings RBL1 and RBL2 can be set to a floating state. Therefore, the power applied to the wirings RBL1 and RBL2 can be reduced. Alternatively, any potential may be applied to the wirings RBL1 and RBL2.

[0074] Next, the operation of reading the data written in FIG. 7 will be described with reference to the timing chart of FIG.

[0075] At time T30, the wirings RBL1[1] to RBL1[m] can be initialized with an arbitrary potential. A reference potential is applied to the wirings RBL2[1] to RBL2[m] to confirm that arbitrary data is stored in the memory cell. The arbitrary potential to be initialized is preferably the same as the data "L" or a potential lower than the data "L". During the period in which the reference potential is applied to the wirings RBL2[1] to RBL2[m], "H" is applied to the wirings RWL_D1 and RWL_D2, and the selection transistors DTr2 and DTr3 are turned on.

[0076] At time T31, the data stored in the memory cells MC[1,1] to MC[m,1] connected to the wiring RWL[1] can be read. An "L" is applied to the wiring RWL[1], and an "H" is applied to the other wirings RWL[2] to RWL[n]. Since the transistors RTr are connected in series, if any of the memory cells MC[1,1] to MC[m,1] holds data of "H", a reference potential signal is output to the wiring RBL1 of the target column of the memory cell MC holding data of "H".

[0077] In each of the memory cells MC connected to the wirings RWL[2] to RWL[n], the capacitance CS can be set to a state in which "H" is applied to the gate of the transistor RTr according to the law of conservation of charge by applying "H" to the wirings RWL[2] to RWL[n]. Therefore, in the transistors RTr connected in series, all the transistors RTr other than the one to be read are turned on. Therefore, when the data of the memory cell to be read is "L", the reference potential applied to the wiring RBL2 cannot be output to the wiring RBL1. Also, when the data of the memory cell to be read is "H", the reference potential applied to the wiring RBL2 is output to the wiring RBL1. Therefore, the data stored in each of the memory cells MC[1,1] to MC[m,1] is output to the wirings RBL1[1] to RBL1[m].

[0078] At time T32, "L" is applied to the wirings RWL[1] to RWL[n], and the wirings RBL1[1] to RBL1[m] are initialized to an arbitrary potential. At this time, it is preferable that "H" is applied to the wirings RBL2[1] to RBL2[m], but "L" may be applied.

[0079] At time T33, the data stored in the memory cells MC[1,2] to MC[m,2] connected to the wiring RWL[2] can be read. An "L" is applied to the wiring RWL[2], and an "H" is applied to the other wirings RWL[1], RWL[3] to RWL[n]. The following operations are the same as those for reading data from the wiring RWL[1], so the explanation will be omitted.

[0080] The operation at time T34 is the same as that at time T32, and therefore the description thereof will be omitted. After time T34 (the period from time T35 to time T39), similar to the operations at time T31 and time T33, the read operation is performed row by row, so that the data stored in the memory cells MC connected to the wirings RWL[3] to RWL[n] can be read. Therefore, data can be read from the memory cells MC sequentially in the row direction of the memory cells.

[0081] A semiconductor device different from that shown in Fig. 2 will be described with reference to Fig. 10. The semiconductor device shown in Fig. 10 differs from that shown in Fig. 2 in that one of the source or drain of the selection transistor DTr1 is electrically connected to the wiring WBL2. For ease of explanation, a memory module 10 will be used as an example.

[0082] Since the wiring WBL2 is electrically connected to either the source or the drain of the selection transistor DTr1, the memory module 10 can rewrite data in the memory cell MC from either or both of the wiring WBL1 and the wiring WBL2.

[0083] That is, by applying "H" to the wiring WWL_D, the wiring WBL2[1] can rewrite the data of the memory node of the memory cell MC[1,1] via the selection transistor DTr1[1]. Also, by applying "H" to the wiring WWL[n], the wiring WBL1[1] can rewrite the data of the memory node of the memory cell MC[1,n]. Also, by applying "H" to the wiring WWL[1] and the wiring WWL[n] simultaneously, the data of the memory nodes of the memory cells MC[1,1] and MC[1,n] can be rewritten simultaneously.

[0084] An operation of rewriting data in the 1st, 2nd, (n-1)th, and (n)th rows using a method different from that shown in FIG. 7 will be described with reference to the timing chart of FIG.

[0085] At time T40, "L" is applied to the wiring WWL_D, the wiring WWL[1] to the wiring WWL[n], the wiring RWL_D1, the wiring RWL_D2, the wiring RWL[1] to the wiring RWL[n], the wiring RBL1[1], and the wiring RBL2[2]. In addition, no data is input to the wiring WBL1[1] and the wiring WBL2[1].

[0086] At time T41, the wiring WWL_D is given "H", so that the selection transistors DTr1[1] to DTr1[m] are turned on. The wiring WWL[1] is given "H", so that the transistors WTr in the memory cells MC[1,1] to MC[m,1] are turned on. Therefore, the data D[2] given to the wirings WBL2[1] to WBL2[m] can rewrite the data in the memory cells MC[1,2] to MC[m,2] via the selection transistors DTr1[1] to DTr1[m]. At this time, the data D[2] is also given to the memory cells MC[1,1] to MC[m,1].

[0087] Furthermore, when "H" is applied to the wiring WWL[n], the transistors WTr in the memory cells MC[1,n] to MC[m,n] are turned on. When "H" is applied to the wiring WWL[n-1], the transistors WTr in the memory cells MC[1,n-1] to MC[m,n-1] are turned on. Therefore, the data D[n-1] applied to the wirings WBL1[1] to WBL1[m] can rewrite the data in the memory nodes of the memory cells MC[1,n-1] to MC[m,n-1]. At this time, the data D[n-1] is also applied to the memory cells MC[1,n] to MC[m,n].

[0088] Therefore, data is simultaneously rewritten in the memory nodes of the memory cells MC[1,2] to MC[m,2] and the memory cells MC[1,n-1] to MC[m,n-1].

[0089] At time T42, the wiring WWL[1] is applied with "L" to turn off the transistors WTr in the memory cells MC[1,1] to MC[m,1], and the wiring WWL[n-1] is applied with "L" to turn off the transistors WTr in the memory cells MC[1,n-1] to MC[m,n-1]. Thus, the memory nodes in the memory cells MC[1,2] to MC[m,2] hold data D[2], and the memory nodes in the memory cells MC[1,n-1] to MC[m,n-1] hold data D[n-1].

[0090] Furthermore, data D[1] provided to the wirings WBL2[1] to WBL2[m] can rewrite data in the memory cells MC[1,1] to MC[m,1] via the selection transistors DTr1[1] to DTr1[m]. Data D[n] provided to the wirings WBL2[1] to WBL2[m] can rewrite data in the memory cells MC[1,n] to MC[m,n] via the selection transistors DTr1[1] to DTr1[m].

[0091] In FIG. 11, after the data is rewritten, “L” is applied to each of the wiring WWL_D and the wiring WWL[n] from time T43 onward (between time T43 and time T45).

[0092] 12, an example will be described in which a plurality of memory modules included in a semiconductor device are connected by wirings WWL, RWL, and WWL_D, and the structure of stored data has a data width of m bits. As an example, an operation of rewriting data in the 1st, 2nd, 3rd, n-1th, and nth rows will be described with reference to the timing chart of FIG.

[0093] The basic operation is the same as that described in Fig. 11, so the explanation will be omitted, and in Fig. 12, the difference from Fig. 11 will be explained. As an example, at time T51, the data in the 2nd row and the n-1th row are rewritten simultaneously. Also, at time T52, the data in the 1st row and the nth row are rewritten simultaneously.

[0094] In a memory module having n rows, for example, when two different rows are to be rewritten, it is preferable to simultaneously access each row from the closer side of either the memory cell MC in the first row connected to the selection transistor DTr1 or the memory cell MC in the nth row. Since two different rows can be rewritten simultaneously, the rewrite time to the memory cells can be further reduced. Therefore, by accessing the row to be rewritten from the closer side, the rewrite time can be reduced.

[0095] 12, a plurality of memory cells are arranged in m columns. Therefore, data to be rewritten is simultaneously rewritten by data provided to the wirings WBL1[1] to WBL1[m] and data provided to the wirings WBL2[1] to WBL2[m]. That is, in the configuration shown in this embodiment, the semiconductor device can be said to be a memory device having a data width of m bits for any address.

[0096] 10 to 12, data can be rewritten simultaneously in any row of the memory module from different directions, so data can be rewritten at higher speed than in the circuit configuration described in FIG.

[0097] The structures and methods described in this embodiment mode can be used in appropriate combination with structures and methods described in other embodiment modes.

[0098] (Embodiment 2) In this embodiment mode, a memory device including the semiconductor device described in the above embodiment mode will be described.

[0099] 13A shows an example of the configuration of a memory device. The memory device 2600 has a peripheral circuit 2601 and a memory cell array 2610. The peripheral circuit 2601 has a row decoder 2621, a word line driver circuit 2622, a bit line driver circuit 2630, an output circuit 2640, and a control logic circuit 2660.

[0100] The semiconductor device illustrated in FIG. 1A, FIG. 1B, or FIG. 1C described in the first embodiment can be applied to the memory cell array 2610.

[0101] The bit line driver circuit 2630 includes a column decoder 2631, a precharge circuit 2632, a sense amplifier 2633, and a write circuit 2634. The precharge circuit 2632 has a function of precharging the wiring RBL2 described in the first embodiment to a predetermined potential. The sense amplifier 2633 has a function of acquiring a potential output from the memory cell MC to the wiring RBL1 as a data signal and amplifying the data signal. The amplified data signal is output to the outside of the memory device 2600 via the output circuit 2640 as a digital data signal RDATA.

[0102] Further, the memory device 2600 is supplied with a low power supply potential (VSS), a high power supply potential (VDD) for the peripheral circuit 2601, and a high power supply potential (VIL) for the memory cell array 2610 as power supply potentials from the outside.

[0103] In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 2600. The address signal ADDR is input to a row decoder 2621 and a column decoder 2631, and the data signal WDATA is input to a write circuit 2634.

[0104] The control logic circuit 2660 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 2621 and column decoder 2631. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 2660 are not limited to these, and other control signals may be input as necessary.

[0105] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as necessary.

[0106] 13B shows an example in which the memory device 2600 is configured using a p-channel Si transistor and a transistor including an oxide semiconductor (preferably an oxide including In, Ga, and Zn) in a channel formation region. For example, the memory device 2600 shown in FIG. 13B has a logic layer 1000 and a memory layer 2000 in which peripheral circuits are configured using Si transistors. That is, the memory layer 2000 formed of transistors including an oxide semiconductor in a channel formation region is formed above the logic layer 1000.

[0107] Therefore, by disposing the sense amplifier 2633 under the memory layer 2000, the length of the wiring RBL1 connecting the sense amplifier 2633 and the memory cell MC can be shortened. Therefore, the wiring RBL1 reduces the influence of the time constant of the wiring, and the speed of the operation of reading data from the memory cell MC can be improved. In addition, by using a transistor having an oxide semiconductor for the memory cell MC, the off-current of the memory cell MC can be reduced. Since data leakage between adjacent memory cells MC can be suppressed, data can be stored for a long period of time. In addition, since the refresh interval of the memory cell can be extended, the power consumption of the memory device 2600 can be reduced. Furthermore, by using only p-channel type Si transistors, the manufacturing cost can be kept low. Alternatively, only n-channel type Si transistors may be used.

[0108] Figures 14 to 16 show the configuration of the memory cell array 2610 of Figure 13. In Figures 14 to 16, some elements are omitted for clarity of the drawings.

[0109] In Fig. 14, the memory cell MC[m,n,d] is connected to the wiring RBL1[m], the wiring WBL1[m], the wiring WWL[n,d], and the wiring RWL[n,d]. Therefore, the semiconductor device shown in Fig. 14 has memory cells MC[1,1,1] to MC[m,n,d] arranged three-dimensionally having a depth direction.

[0110] 14 also includes a selection transistor DTr1, a selection transistor DTr2, a selection transistor DTr3, a wiring WWL_D, a wiring RWL_D1, and a wiring RWL_D2. The wiring WBL1 is connected to one end and the other end of the memory module 10 via the selection transistor DTr1, the wiring RBL2 is connected to one end of the memory module 10 via the selection transistor DTr2, and the wiring RBL1 is connected to the other end of the memory module 10 via the selection transistor DTr3. The wiring WWL_D is electrically connected to the gate of the selection transistor DTr1, the wiring RWL_D1 is electrically connected to the gate of the selection transistor DTr2, and the wiring RWL_D2 is electrically connected to the gate of the selection transistor DTr3.

[0111] The selection transistor DTr2 can precharge each memory module 10 with a predetermined potential used for reading data. The wiring RBL2 may be fixed at an arbitrary high potential. The selection transistor DTr3 can select the memory module 10 from which data is to be read. The wiring RWL_D2 from which data is to be read can individually turn off the selection transistors DTr3 connected to the memory modules 10 that are not selected.

[0112] Therefore, since the unselected memory modules 10 can be separated, the signal quality of the data read from the selected memory cell to the wiring RBL1 can be improved. In particular, when the data held by the memory module 10 is analog data, it is preferable to have the selection transistor DTr3. As a different example, when data is read from the wiring RBL2, the selection transistor DTr2 can be controlled. Note that the selection transistor DTr2 or the selection transistor DTr3 can be provided as necessary.

[0113] It is preferable that the wiring RBL1 and the wiring WBL1 are connected to the bit line driver circuit 2630A in units of columns and in the depth direction d. Similarly, it is preferable that the wiring RBL2 is electrically connected to the bit line driver circuit 2630B in units of columns and in the depth direction d. Therefore, the memory cells MC[1,1] to MC[m,n] are processed as data access units. In other words, it is indicated that the data width has m bits. The semiconductor device of this embodiment can be easily applied not only to general-purpose memories but also to frame memories of display devices.

[0114] In each memory module 10, by shortening the length of the wiring WBL1, the variation due to the wiring resistance can be reduced, and therefore the data rewrite time can be shortened.

[0115] FIG. 15 shows a configuration of the memory cell array 2610 different from that shown in FIG. 14. In FIG. 15, the memory cell array 2610 further includes a wiring WBL1a, which is electrically connected to the memory module 10 via the selection transistor DTr1. In FIG. 14, the wiring WBL1 is electrically connected in the vicinity of the memory module 10, and the memory module 10 shares the wiring WBL1 and is electrically connected to the bit line driver circuit 2630A. FIG. 15 shows an example in which the memory module 10 is electrically connected to the bit line driver circuit 2630A via the wiring WBL1 and is electrically connected to the bit line driver circuit 2630B via the wiring WBL1a. The wiring WBL1 or the wiring WBL1a shown in FIG. 15 is preferably electrically connected to the bit line driver circuit 2630A and the bit line driver circuit 2630B outside the memory cell array 2610. Note that the bit line driver circuit 2630A and the bit line driver circuit 2630B preferably function as one bit line driver circuit 2630. Therefore, the memory cell array 2610 shown in FIG. 15 does not require the wiring WBL1 to be connected near the memory module 10, and therefore the data density of the semiconductor device can be improved.

[0116] FIG. 15 shows a configuration of the memory cell array 2610 different from that of FIG. 14. In FIG. 15, the memory cell array 2610 further includes a wiring WBL1a, which is electrically connected to the memory module 10 via the selection transistor DTr1. In FIG. 14, the wiring WBL1 is connected in the vicinity of the memory module 10, and the memory module 10 is connected to the bit line driver circuit 2630A by sharing the wiring WBL1. FIG. 15 shows an example in which the memory module 10 is connected to the bit line driver circuit 2630A via the wiring WBL1 or the wiring WBL2. The wiring WBL1 or the wiring WBL2 shown in FIG. 15 is preferably connected to the bit line driver circuit 2630A outside the memory cell array 2610. Therefore, the memory cell array 2610 can improve the data density of the semiconductor device compared to the configuration shown in FIG. 14.

[0117] 16, one side of the memory module 10 is connected to the wiring WBL2 via the selection transistor DTr1. The wiring WBL1 and the wiring RBL1 are connected to the bit line driver circuit 2630A, and the wiring WBL2 and the wiring RBL2 are connected to the bit line driver circuit 2630B. Therefore, the memory module 10 can rewrite data by a signal provided from the bit line driver circuit 2630A to the wiring WBL1 and a signal provided from the bit line driver circuit 2630B to the wiring WBL2. Also, as described in FIG. 12, the bit line driver circuit 2630A and the bit line driver circuit 2630B can simultaneously perform rewrite or read processing on the same memory module 10.

[0118] <Structure examples and manufacturing method examples> In order to facilitate understanding of the structure of the semiconductor device of this embodiment mode, a manufacturing method thereof will be described below.

[0119] Figures 17A and 17B are schematic diagrams showing the semiconductor device shown in Figures 1A to 1C. Figure 17A shows a top view of the semiconductor device, and Figure 17B shows a cross-sectional view corresponding to the dashed dotted line A1-A2 in Figure 17A.

[0120] The semiconductor device has a structure in which a wiring RWL, a wiring WWL, and an insulator (area not shown with hatching in FIGS. 17A and 17B) are stacked, an opening is provided in the structure, and a conductor PG is formed so as to fill the opening. A wiring ER is formed on the conductor PG, and this electrically connects the wiring ER to the wiring WWL_D, the wiring RWL_D1, the wiring RWL_D2, the wiring RWL, or the wiring WWL.

[0121] In addition, an opening is formed in the structure so as to penetrate the wiring RWL and the wiring WWL together. In the opening, the selection transistor DTr1 and the selection transistor DTr2 can be provided in the region DM1 penetrated by the wiring WWL_D, the wiring RWL, and the wiring WWL, the transistor WTr and the transistor RTr of the memory cell MC can be provided in the region AR, and the selection transistor DTr3 can be provided in the region DM2. Therefore, an insulator, a conductor, and a semiconductor for forming the above transistors are formed in the opening. The conductor functions as the wiring WBL and the wiring RBL, and the semiconductor functions as a channel formation region for the selection transistor DTr1, the selection transistor DTr2, the selection transistor DTr3, the transistor WTr, and the transistor RTr.

[0122] 17, a region in which an insulator, a conductor, and a semiconductor are formed in the opening is illustrated as a region HL. When the transistor has a back gate, the conductor in the region HL functions as the back gate. Therefore, the back gate can be referred to as a wiring BGL.

[0123] In other words, FIG. 17 shows that the semiconductor device shown in either FIG. 1A or FIG. 1B is configured in region SD1, and the semiconductor device shown in FIG. 2 or FIG. 10 is configured in region SD2.

[0124] In the following manufacturing method example 1 and manufacturing method example 2, a method for forming a transistor included in a memory cell MC formed in the region AR will be described.

[0125] <<Production method example 1>> 18 to 22 are cross-sectional views for explaining a manufacturing example of the semiconductor device shown in FIG. 1A, and in particular, cross-sectional views in the channel length direction of the transistors WTr and RTr are shown. In addition, in the cross-sectional views of FIG. 18 to 22, some elements are omitted for clarity.

[0126] As shown in Fig. 18A, the semiconductor device in Fig. 1A has an insulator 101A arranged above a substrate (not shown), a conductor 131A arranged on the insulator 101A, an insulator 101B arranged on the conductor 131A, a conductor 132A arranged on the insulator 101B, an insulator 101C arranged on the conductor 132A, a conductor 131B arranged on the insulator 101C, an insulator 101D arranged on the conductor 131B, a conductor 132B arranged on the insulator 101D, and an insulator 101E arranged on the conductor 132B. Hereinafter, a stack having these multiple conductors and multiple insulators will be referred to as a stack 100.

[0127] The substrate may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon, germanium, and the like, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides and substrates having metal oxides. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor, a resistor, a transistor, a switch element, a light-emitting element, a memory element, and the like.

[0128] A flexible substrate may be used as the substrate. As an example, a method of providing a transistor on a flexible substrate may include a method of forming a transistor on a non-flexible substrate, peeling the transistor, and transferring the transistor to a flexible substrate. In that case, a peeling layer may be provided between the non-flexible substrate and the transistor. Note that a sheet, film, or foil having woven fibers may be used as the substrate. The substrate may also have elasticity. The substrate may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. The substrate has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. By making the substrate thin, the weight of a semiconductor device having a transistor can be reduced. In addition, by making the substrate thin, even when glass or the like is used, the substrate may have elasticity or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, it is possible to reduce the impact applied to the semiconductor device on the substrate due to a drop or the like. That is, a robust semiconductor device can be provided.

[0129] The flexible substrate may be made of, for example, a metal, an alloy, a resin, or glass, or a fiber thereof. The lower the linear expansion coefficient of the flexible substrate, the more preferable it is, since deformation due to the environment is suppressed. For example, the linear expansion coefficient of the flexible substrate may be 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. Aramid, in particular, is suitable for a flexible substrate because of its low linear expansion coefficient.

[0130] In the manufacturing example described in this embodiment mode, since a heat treatment is included in the process, it is preferable to use a material having high heat resistance and a low thermal expansion coefficient as the substrate.

[0131] The conductor 131A (conductor 131B) functions as the wiring WWL shown in FIG. 1A, and the conductor 132A (conductor 132B) functions as the wiring RWL shown in FIG. 1A.

[0132] The conductors 131A, 131B, 132A, and 132B may be made of a material containing one or more metal elements selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0133] Moreover, as the conductor, particularly the conductor 131A and the conductor 131B, a conductive material containing a metal element and oxygen contained in a metal oxide applicable to the semiconductor 1, the semiconductor 152, the semiconductor 153a, and the semiconductor 153b described later may be used. Also, a conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Also, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used. Also, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen mixed in from a surrounding insulator or the like.

[0134] Moreover, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen as the conductors, particularly the conductors 132A and 132B. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like, which may be formed as a single layer or a multilayer structure.

[0135] In addition, a plurality of conductors formed of the above-mentioned materials may be laminated. For example, a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. In addition, a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. In addition, a laminate structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen. In addition, by applying an insulator having an excess oxygen region as an insulator in contact with a conductor, oxygen may diffuse in a region of the conductor in contact with the insulator. This makes it possible to form a laminate structure in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, similarly, by applying an insulator having an excess nitrogen region as an insulator in contact with a conductor, nitrogen may diffuse in a region of the conductor in contact with the insulator. This makes it possible to form a laminate structure in which a material containing a metal element and a conductive material containing nitrogen are combined.

[0136] Note that the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B may be made of the same material or different materials. In other words, materials used for the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B constituting the semiconductor device of one embodiment of the present invention can be appropriately selected and used.

[0137] The insulators 101A to 101E are preferably made of materials with reduced concentrations of impurities such as water or hydrogen. For example, the amount of desorption of hydrogen from the insulators 101A to 101E is calculated as 2×10 per area of ​​any one of the insulators 101A to 101E when the surface temperature of the film is in the range of 50° C. to 500° C. and converted into hydrogen molecules, as determined by thermal desorption spectroscopy (TDS). 15 molecules / cm 2 Less than or equal to 1×10 15 molecules / cm 2 Less than or equal to 5×10 14molecules / cm 2 The following may be used. The insulators 101A to 101E may be formed using an insulator that releases oxygen when heated. As a result, as described above, the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B can have a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined.

[0138] The insulators 101A to 101E can be, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum, in a single layer or a stacked layer. Also, for example, a material containing silicon oxide or silicon oxynitride can be used.

[0139] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0140] In the next step, as shown in FIG. 18B, an opening 191 is formed in the laminate 100 shown in FIG. 18A by forming a resist mask and performing an etching process or the like.

[0141] The resist mask can be formed by appropriately using a lithography method, a printing method, an inkjet method, etc. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced. In addition, the etching process may be a dry etching method or a wet etching method, or both may be used.

[0142] 19A, the conductor 132A (conductor 132B) on the side surface of the opening 191 is removed by etching or the like to form a recess 192A (recess 192B) in the side surface. Here, it is assumed that a material (a material having a higher etching rate than the insulators 101A to 101E and the conductor 131A (conductor 131B)) is used as the conductor 132A (conductor 132B) from which the conductor 132A (conductor 132B) is selectively removed out of the laminate 100.

[0143] 18A, a sacrificial layer may be provided in a region where opening 191 and recess 192A (recess 192B) are to be formed, and recess 192A (recess 192B) may be formed together with opening 191 in the manufacturing process of the semiconductor device shown in Fig. 18B. In some cases, recess 192A (recess 192B) can be automatically formed when opening 191 is formed without providing a sacrificial layer.

[0144] In the next step, as shown in FIG. 19B, an insulator 102 is formed on the side surface of the opening 191 shown in FIG. 19A and in the recessed portion described above.

[0145] An insulating material having a function of suppressing oxygen permeation is preferably used as the insulator 102. For example, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like is preferably used as the insulator 102. By forming such an insulator 102, a decrease in the conductivity of the conductor 133, which would be caused by oxygen entering through the insulator 102 and oxidizing the conductor 133 described later, can be prevented.

[0146] 20A, in the next step, a conductor 133 is formed on the side surface of the opening 191 shown in FIG.

[0147] The materials applicable to the above-mentioned conductors 131A, 131B, 132A, and 132B can be used as the conductor 133. In particular, it is preferable to use a material having high conductivity for the conductor 133 among the above materials.

[0148] 20B, in the next step, the conductor 133 included in the opening 191 is removed by forming a resist mask and performing an etching process, etc., so that the conductor 133 remains only in the recessed portion described above. This results in the formation of conductors 133a and 133b. Note that at this time, a portion of the insulator 102 may be removed as long as the insulators 101A to 101E, the conductor 131A, and the conductor 131B are not exposed in the opening 191.

[0149] For details about the formation of the resist mask and the etching process, please refer to the explanation of FIG. 18B.

[0150] The conductor 133a (conductor 133b) functions as the other electrode of the capacitance CS shown in Fig. 1A. That is, the capacitance CS is formed in the region 181A (region 181B) shown in Fig. 20B.

[0151] In the next step, as shown in FIG. 21A, a semiconductor 151 is formed on the insulator 102, the conductor 133a, and the conductor 133b located on the side portions of the opening 191.

[0152] As the semiconductor 151, it is preferable to use a material containing an oxide of one or more metals selected from indium, element M (element M is, for example, aluminum, gallium, yttrium, tin, etc.), and zinc.

[0153] Incidentally, when the semiconductor 151 contains a metal oxide, the insulator 102 in contact with the semiconductor 151 is preferably made of an insulating material having a function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen. By forming such an insulator 102, it is possible to prevent impurities such as water or hydrogen from penetrating the insulator 102 and reacting with oxygen contained in the semiconductor 151 to become water. When water is generated in the semiconductor 151, oxygen vacancies may be formed in the semiconductor 151. When impurities such as hydrogen enter the oxygen vacancies, electrons that serve as carriers may be generated. Therefore, when a region containing a large amount of hydrogen exists in the semiconductor 151, a transistor in which the region is included in the channel formation region is likely to have normally-on characteristics. To prevent this, it is preferable to use an insulating material having a function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen as the insulator 102.

[0154] When the semiconductor 151 contains a metal oxide, the semiconductor 151 may have different conductivity depending on the region where it is formed. In FIG. 21A, among the regions where the semiconductor 151 is formed, regions in contact with the insulator 102 are illustrated as regions 151a and 151b, and a region in contact with the conductor 133a (conductor 133b) is illustrated as a region 151c. In particular, the region 151a overlaps with a side surface of the conductor 131A (conductor 131B), and the region 151b overlaps with a side surface of the insulator 101A (insulators 101B to 101E). Since the region 151c is in contact with the conductor 133a (conductor 133b), impurities such as hydrogen or water contained in the conductor 133a (conductor 133b) may diffuse to the region 151c. As described above, when impurities such as water or hydrogen diffuse into the semiconductor 151, electrons that become carriers may be generated, and the resistance of the region 151c may be reduced. Therefore, the region 151c becomes a region with higher conductivity than the regions 151a and 151b.

[0155] The region 151a is a region that becomes a channel formation region of the transistor, and therefore, when the transistor is in an on state, the region 151a has a low resistance and is therefore more conductive than the region 151b.

[0156] In the next step, as shown in FIG. 21B, an insulator 103 and a semiconductor 152 are formed in this order on the semiconductor 151 located on the side of the opening 191.

[0157] The insulator 103 can be any of the above-mentioned materials applicable to the insulator 102. In particular, when the semiconductor 151 contains a metal oxide, the insulator 103 is preferably an insulating material that has a function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen.

[0158] 1A is configured in the region 182A (region 182B) shown in Fig. 21B. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as a channel formation region of the transistor WTr, the two regions 151b of the semiconductor 151 function as a source electrode and a drain electrode of the transistor WTr, and the conductor 132A functions as a gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, the transistor WTr constitutes an oxide semiconductor (OS) transistor.

[0159] As the semiconductor 152, a material containing an oxide of one or more metals selected from indium, an element M (for example, the element M is aluminum, gallium, yttrium, tin, or the like), and zinc can be used, similarly to the semiconductor 151. Alternatively, a semiconductor material such as polycrystalline silicon or amorphous silicon can be used instead of the semiconductor 152.

[0160] In the next step, as shown in FIG. 22A, an insulator 104 is deposited on the semiconductor 152, and a conductor 134 is deposited so as to fill the remaining openings 191.

[0161] As the insulator 104, the materials applicable to the insulators 102 and 103 described above can be used.

[0162] The conductor 134 can be made of a material that can be used for the conductor 131A, the conductor 131B, the conductor 132A, the conductor 132B, the conductor 133a, and the conductor 133b described above.

[0163] 1A is configured in the region 183A (region 183B) shown in Fig. 22A. Specifically, in the region 183A (region 183B), the region 151c, the two regions 151b, and the conductor 133a (conductor 133b) of the semiconductor 151 function as the gate electrode of the transistor RTr, the semiconductor 152 functions as the channel formation region of the transistor RTr, and the conductor 134 functions as the backgate electrode of the transistor RTr. In particular, when a material containing a metal oxide is used as the semiconductor 152, the transistor RTr constitutes an OS transistor.

[0164] By carrying out the steps shown in FIG. 18A to FIG. 22A, the semiconductor device shown in FIG. 1A can be manufactured.

[0165] One embodiment of the present invention is not limited to the example of the configuration of the semiconductor device illustrated in Fig. 22A. One embodiment of the present invention can have a configuration in which the semiconductor device illustrated in Fig. 22A is modified as appropriate depending on the case, situation, or need.

[0166] For example, as described above, one embodiment of the present invention can be a semiconductor device in which the transistors WTr and RTr do not have back gates as shown in FIG. 1C. When manufacturing the semiconductor device shown in FIG. 1C, the process of manufacturing the semiconductor device shown in FIG. 1A may be performed by performing the process shown in FIG. 22B instead of the process shown in FIG. 22A. Specifically, for example, FIG. 22B shows a process of depositing an insulator 105 to fill the opening 191 instead of the conductor 134 in FIG. 22A. Note that the insulator 105 can be formed using a material that can be used as the insulator 104, for example.

[0167] Furthermore, for example, in one embodiment of the present invention, the structure of the gate electrode of the transistor WTr may be changed from that shown in FIG. 22A in order to improve the switching characteristics of the transistor WTr. FIGS. 23A, 23B, 24A, and 24B illustrate an example of a manufacturing method of the semiconductor device. FIG. 23A illustrates a step in which the conductor 131A (conductor 131B) on the side surface of the opening 191 in FIG. 18B is removed to form the recess 193A (recess 193B). Here, it is assumed that the conductor 131A (conductor 131B) is made of a material (a material having a higher etching rate than the conductor 132A (conductor 132B) and the insulators 101A to 101E) from which the conductor 131A (conductor 131B) in the stack 100 is selectively removed.

[0168] 18A, a sacrificial layer may be provided in the region where opening 191 and recess 193A (recess 193B) are to be formed, and recess 193A (recess 193B) may be formed together with opening 191 in the manufacturing process of the semiconductor device shown in Fig. 18B. In some cases, recess 193A (recess 193B) can be automatically formed when opening 191 is formed without providing a sacrificial layer.

[0169] In the next step, as shown in FIG. 23B, a semiconductor 153 is formed on the side surface of the opening 191 and in the recess 193A (recess 193B) shown in FIG. 23A.

[0170] The semiconductor 153 is made of a material containing an oxide of one or more metals selected from indium, element M (eg, element M is aluminum, gallium, yttrium, tin, etc.), and zinc.

[0171] 24A, in the next step, the semiconductor 153 included in the opening 191 is removed by forming a resist mask and etching so that the semiconductor 153 remains only in the above-mentioned recess 193A (recess 193B), forming the semiconductor 153a (semiconductor 153b). Simultaneously with or after this process, an etching process is performed to remove the conductor 132A (conductor 132B) and form the recess 192A (recess 192B).

[0172] Next, similarly to the process of FIG. 20B, the insulator 102 is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). When a material containing a metal oxide is applied as the semiconductor 153a (semiconductor 153b), the semiconductor 153a (semiconductor 153b) comes into contact with the insulator 102, so that impurities such as hydrogen and water contained in the insulator 102 diffuse into the semiconductor 153a (semiconductor 153b). Furthermore, the semiconductor 153a (semiconductor 153b) comes into contact with the conductor 133a (conductor 133b), so that impurities such as hydrogen and water contained in the conductor 133a (conductor 133b) diffuse into the semiconductor 153a (semiconductor 153b). That is, the semiconductor 153a (semiconductor 153b) has a role of collecting impurities such as hydrogen and water. As a result, the semiconductor 153a (semiconductor 153b) has a low resistance and can function as a gate electrode of the transistor WTr. Thereafter, by carrying out the same steps as those in FIGS. 21A to 22A, the semiconductor device shown in FIG. 24B can be fabricated.

[0173] In addition, for example, in one embodiment of the present invention, in order to reduce electrical resistance between the first terminal or the second terminal of the transistor WTr shown in FIG. 1A and the gate of the transistor RTr, the structure of the gate electrode of the transistor RTr may be changed from that shown in FIG. 22A. FIGS. 25A and 25B show an example of a manufacturing method of the semiconductor device. FIG. 25A shows a step in which not only the conductor 132A (conductor 132B) on the side surface of the opening 191 in FIG. 19A is removed, but the insulators 101A to 101E are also removed to form a recess 194B (recess 194A, recess 194C). Here, the conductor 132A (conductor 132B) and the insulators 101A to 101E are made of a material (a material having an etching rate higher than that of the conductor 131A (conductor 131B)) that allows the conductor 132A (conductor 132B) and the insulators 101A to 101E to be selectively removed from the laminate 100.

[0174] 18A, a sacrificial layer may be provided in a region where opening 191 and recess 194B (recess 194A, recess 194C) are to be formed, and recess 194B (recess 194A, recess 194C) may be formed together with opening 191 in the manufacturing process of the semiconductor device shown in Fig. 18B. In some cases, recess 194B (recess 194A, recess 194C) can be automatically formed when opening 191 is formed without providing a sacrificial layer.

[0175] 25A, in recess 194B (recess 194A, recess 194C), a larger amount of conductor 132A (conductor 132B) is removed than insulator 101B and insulator 101C (insulator 101A, insulator 101D, insulator 101E), but a larger amount of insulator 101B and insulator 101C (insulator 101A, insulator 101D, insulator 101E) may be removed than conductor 132A (conductor 132B). In addition, insulator 101B and insulator 101C (insulator 101A, insulator 101D, insulator 101E) and conductor 132A (conductor 132B) may be formed to the same depth.

[0176] FIG. 25B shows a configuration example of a semiconductor device through the process of FIG. 25A. After the process of FIG. 25A, the conductor 133 is formed so as to fill the recess 194B (recess 194A, recess 194C), and the gate electrode of the transistor RTr is formed. FIG. 25B shows the conductor 133a, the conductor 133b, and the conductor 133c that function as the gate electrode of the transistor RTr. After this, the semiconductor device shown in FIG. 25B can be formed by performing the same processes from FIG. 21A to FIG. 22A. This semiconductor device has a configuration in which the contact area between the semiconductor 151 and the conductor 133a (conductor 133b) is larger than that of the semiconductor device shown in FIG. 22A. When a material having a metal oxide is applied to the semiconductor 151, the semiconductor device shown in FIG. 25B does not have the region 151b shown in FIG. 22A, and therefore the electrical resistance between the first terminal or the second terminal of the transistor WTr and the gate of the transistor RTr can be reduced.

[0177] <<Production method example 2>> Here, as a semiconductor device of this embodiment mode, an example of a structure different from that of Manufacturing Method Example 1 will be described with reference to FIGS.

[0178] 26 to 28 are cross-sectional views for explaining a manufacturing example of the semiconductor device shown in Fig. 1A, and in particular, show cross-sectional views in the channel length direction of the transistors WTr and RTr, similar to Fig. 18 to 22. In addition, in the cross-sectional views of Fig. 26 to 28, some elements are omitted for clarity, similar to Fig. 18 to 22.

[0179] For the initial step, please refer to the description of FIG. 18A to FIG. 19B in the example 1 of the manufacturing method.

[0180] The process shown in Fig. 26A is a continuation of the process shown in Fig. 19B. In Fig. 26A, a semiconductor 151 is formed on the side surface of the opening 191 shown in Fig. 19B and in the formed recess. That is, the semiconductor 151 is formed on the insulator 102.

[0181] As the semiconductor 151, it is preferable to use one or more semiconductors selected from indium, element M (element M is, for example, aluminum, gallium, yttrium, tin, etc.), and zinc.

[0182] In the next step, as shown in FIG. 26B, a conductor 133 is formed on the side surface of the opening 191 shown in FIG. 26A and in the formed recess.

[0183] For the conductor 133, the description of the conductor 133 in the manufacturing method example 1 can be referred to.

[0184] 27A, in the next step, the conductor 133 included in the opening 191 is removed by forming a resist mask and performing an etching process, etc., so that the conductor 133 remains only in the recessed portion described above. This forms the conductors 133a and 133b. At this time, a part of the semiconductor 151 may be removed as long as the insulator 102 is not exposed in the opening 191.

[0185] For details about the formation of the resist mask and the etching process, please refer to the explanation of FIG. 18B.

[0186] The conductor 133a (conductor 133b) functions as the other electrode of the capacitance CS shown in Fig. 1A. That is, the capacitance CS is formed in the region 181A (region 181B) shown in Fig. 27A.

[0187] The description of the semiconductor 151 in Manufacturing Method Example 1 can be referred to for the semiconductor 151. When the semiconductor 151 contains a metal oxide, the semiconductor 151 can be divided into regions 151a, 151b, and 151c. The descriptions of the regions 151a, 151b, and 151c in Manufacturing Method Example 1 can be referred to for the regions 151a, 151b, and 151c.

[0188] In the next step, as shown in FIG. 27B, an insulator 103 is deposited on the conductor 133a, the conductor 133b, and the semiconductor 151 located on the side portions of the opening 191, and then a semiconductor 152 is deposited on the insulator 103.

[0189] For the insulator 103, the description of the insulator 103 in the manufacturing method example 1 can be referred to.

[0190] For the semiconductor 152, the description of the semiconductor 152 in the Manufacturing Method Example 1 can be referred to.

[0191] 1A is configured in the region 182A (region 182B) shown in Fig. 27B. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as a channel formation region of the transistor WTr, the two regions 151b of the semiconductor 151 function as a source electrode and a drain electrode of the transistor WTr, and the conductor 132A functions as a gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, the transistor WTr configures an OS transistor.

[0192] In the next step, as shown in FIG. 28, an insulator 104 is deposited on the semiconductor 152, and a conductor 134 is deposited so as to fill the remaining openings 191.

[0193] For the insulator 104, the description of the insulator 104 in the manufacturing method example 1 can be referred to.

[0194] For the conductor 134, the description of the conductor 134 in the manufacturing method example 1 can be referred to.

[0195] 28, the transistor RTr shown in FIG. 1A is configured. Specifically, in the region 183A (region 183B), the region 151c, the two regions 151b, and the conductor 133a (conductor 133b) of the semiconductor 151 function as the gate electrode of the transistor RTr, the semiconductor 152 functions as the channel formation region of the transistor RTr, and the conductor 134 functions as the backgate electrode of the transistor RTr. In particular, when a material containing a metal oxide is used as the semiconductor 152, the transistor RTr constitutes an OS transistor.

[0196] By carrying out the steps shown in FIGS. 18A to 19B and 26A to 28, the semiconductor device shown in FIG. 1A can be manufactured.

[0197] One embodiment of the present invention is not limited to the example of the configuration of the semiconductor device illustrated in Fig. 28. One embodiment of the present invention can have a configuration in which the semiconductor device illustrated in Fig. 28 is modified as appropriate depending on the case, situation, or need.

[0198] For example, as described above, one embodiment of the present invention can be a semiconductor device in which the transistors WTr and RTr do not have back gates as shown in FIG. 1C. When manufacturing the semiconductor device shown in FIG. 1C, instead of the step shown in FIG. 28, in the process of manufacturing the semiconductor device shown in FIG. 1A, an insulator 105 may be formed to fill the opening 191 (not shown) in the same manner as in the step shown in FIG. 22B. Note that the insulator 105 can be formed using, for example, a material that can be used as the insulator 104.

[0199] For example, in one embodiment of the present invention, the configuration of the gate electrode of the transistor WTr may be changed from that shown in FIG. 28 in order to improve the switching characteristics of the transistor WTr. FIG. 29 illustrates an example of the configuration of the semiconductor device. When manufacturing the semiconductor device illustrated in FIG. 29, the semiconductor 153a (semiconductor 153b) is formed so as to fill the recess 193A (recess 193B) as in the example of the configuration illustrated in FIG. 24B described in the manufacturing method example 1. Next, the insulator 102 is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). After that, the same steps as those in FIG. 26A to FIG. 28 are performed to thereby configure the semiconductor device illustrated in FIG. 29. Note that for the effect of configuring the semiconductor device illustrated in FIG. 29, refer to the descriptions of FIG. 23A, FIG. 23B, FIG. 24A, and FIG. 24B described in the manufacturing method example 1.

[0200] For example, in one embodiment of the present invention, in order to reduce electrical resistance between the first terminal or the second terminal of the transistor WTr shown in FIG. 1A and the gate of the transistor RTr, the configuration of the gate electrode of the transistor RTr may be changed from that shown in FIG. 28. FIG. 30 illustrates an example of the configuration of the semiconductor device. When manufacturing the semiconductor device illustrated in FIG. 30, the example of the configuration illustrated in FIG. 25A described in Manufacturing Method Example 1 is manufactured. Thereafter, the semiconductor device illustrated in FIG. 30 can be manufactured by performing the same steps as those from FIG. 26A to FIG. 28. Note that for the effect of the configuration of FIG. 30, refer to the description of FIG. 25B described in Manufacturing Method Example 1.

[0201] By the above-described Manufacturing Method Example 1 or Manufacturing Method Example 2, a semiconductor device capable of holding a lot of data can be manufactured.

[0202] Here, FIG. 31 shows a structure in which the cross-sectional view of the semiconductor device shown in FIG. 22A (circuit configuration of FIG. 1A) is applied to region SD2 of the semiconductor device shown in FIG. 17B. Region SD1 corresponds to memory cell MC. As shown in FIG. 31, openings are provided all at once in a structure in which conductors and insulators, which are wirings RWL and WWL, are stacked, and the circuit configuration of FIG. 1A can be realized by performing the manufacturing process according to the above-described manufacturing method example 1 or manufacturing method example 2.

[0203] <Example of connection to peripheral circuits> The semiconductor device shown in the manufacturing method example 1 or the manufacturing method example 2 may have peripheral circuits of a memory cell array, such as a read circuit and a precharge circuit, formed thereunder. In this case, the peripheral circuits may be formed by forming Si transistors on a silicon substrate or the like, and then the semiconductor device of one embodiment of the present invention may be formed on the peripheral circuits by the manufacturing method example 1 or the manufacturing method example 2. FIG. 32A is a cross-sectional view in which the peripheral circuits are formed of planar Si transistors and the semiconductor device of one embodiment of the present invention is formed thereon. FIG. 33A is a cross-sectional view in which the peripheral circuits are formed of FIN Si transistors and the semiconductor device of one embodiment of the present invention is formed thereon. Note that the semiconductor devices shown in FIG. 32A and FIG. 33A are, for example, configured as shown in FIG. 22A.

[0204] 32A and 33A, Si transistors constituting the peripheral circuit are formed on a substrate 1700. An element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the sources and drains of the Si transistors. Conductors 1730 are formed to extend in the channel width direction, and are connected to other Si transistors or the conductors 1712 (not shown).

[0205] The substrate 1700 can be a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like.

[0206] In addition, the substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminate film, paper containing a fibrous material, or a base film. A semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. In Fig. 32A and Fig. 33A, a single crystal silicon wafer is used as the substrate 1700 as an example.

[0207] Here, the details of the Si transistor will be described. The planar type Si transistor shown in FIG. 32A shows a cross-sectional view in the channel length direction, and the planar type Si transistor shown in FIG. 32B shows a cross-sectional view in the channel width direction. The Si transistor has a channel formation region 1793 provided in a well 1792, a low concentration impurity region 1794 and a high concentration impurity region 1795 (collectively simply referred to as impurity regions), a conductive region 1796 provided in contact with the impurity regions, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and sidewall insulating layers 1798 and 1799 provided on the side surfaces of the gate electrode 1790. Note that the conductive region 1796 may be made of metal silicide or the like.

[0208] The FIN type Si transistor shown in FIG. 33A is a cross-sectional view in the channel length direction, and the FIN type Si transistor shown in FIG. 33B is a cross-sectional view in the channel width direction. In the Si transistor shown in FIG. 33A and FIG. 33B, the channel formation region 1793 has a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along the side and upper surface of the channel formation region 1793. In this embodiment, a case where a convex portion is formed by processing a part of a semiconductor substrate is shown, but a semiconductor layer having a convex shape may be formed by processing an SOI substrate. The reference characters shown in FIG. 33A and FIG. 33B are the same as those shown in FIG. 32A and FIG. 32B.

[0209] The insulators, conductors, semiconductors, and the like disclosed in this specification can be formed by a PVD (Physical Vapor Deposition) method or a CVD (Chemical Vapor Deposition) method. Examples of the PVD method include a sputtering method, a resistance heating deposition method, an electron beam deposition method, and a PLD (Pulsed Laser Deposition) method. Examples of the CVD method include a plasma CVD method and a thermal CVD method. In particular, examples of the thermal CVD method include a MOCVD (Metal Organic Chemical Vapor Deposition) method and an ALD (Atomic Layer Deposition) method.

[0210] The thermal CVD method is a film formation method that does not use plasma, and therefore has the advantage that defects caused by plasma damage are not generated.

[0211] In the thermal CVD method, a source gas and an oxidant are fed simultaneously into a chamber, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the materials are reacted near or on a substrate to deposit the materials on the substrate, thereby forming a film.

[0212] In addition, in the ALD method, the chamber may be under atmospheric pressure or reduced pressure, raw material gases for the reaction may be sequentially introduced into the chamber, and the order of gas introduction may be repeated to form a film. For example, two or more types of raw material gases may be sequentially supplied to the chamber by switching each switching valve (also called a high-speed valve), and an inert gas (argon, nitrogen, etc.) may be introduced simultaneously with or after the first raw material gas so that the multiple raw material gases are not mixed, and then the second raw material gas is introduced. When the inert gas is introduced simultaneously, the inert gas serves as a carrier gas, and the inert gas may be introduced simultaneously with the introduction of the second raw material gas. Alternatively, instead of introducing the inert gas, the first raw material gas may be exhausted by vacuum evacuation, and then the second raw material gas may be introduced. The first raw material gas is adsorbed on the surface of the substrate to form a first thin layer, and reacts with the second raw material gas introduced later, and the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction order multiple times until a desired thickness is obtained while controlling the gas introduction order, a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing precise adjustment of the film thickness, making this method suitable for fabricating fine FETs.

[0213] Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. In addition, the combination is not limited to these, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0214] For example, when forming a hafnium oxide film using a film formation device that uses ALD, two types of gas are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamido)hafnium.

[0215] For example, when forming an aluminum oxide film using a film formation device that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0216] For example, when forming a silicon oxide film using a film formation apparatus that uses ALD, hexachlorodisilane is adsorbed onto the surface to be formed, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed material.

[0217] For example, when forming a tungsten film using a film forming apparatus that uses ALD, WF6 gas and B2H6 gas are repeatedly introduced in sequence to form an initial tungsten film, and then WF6 gas and H2 gas are repeatedly introduced in sequence to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0218] For example, when an oxide semiconductor film, such as an In-Ga-Zn-O film, is formed by a film forming apparatus using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. Also, mixed oxide layers such as an In-Ga-O layer, an In-Zn-O layer, and a Ga-Zn-O layer may be formed using these gases. Note that, instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0219] Note that the respective structural examples of the semiconductor device described in this embodiment mode can be combined with each other as appropriate.

[0220] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0221] (Embodiment 3) In this embodiment, a detailed method for driving the semiconductor device of the above embodiment will be described with reference to Figs. 34 to 40. Figs. 34 to 40 show the semiconductor device described in embodiment 2 (part of the cross-sectional view of Fig. 22A), and a method for driving the semiconductor device will be described with reference to these drawings. In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated description will be omitted. Moreover, the method for driving the semiconductor device can be described with reference to embodiment 1. In this embodiment, the semiconductor device will be described as a memory module.

[0222] FIG. 34 is a diagram for explaining a memory module. As an example, the memory module has a first memory cell, a second memory cell, a wiring BG, a wiring WL, a wiring RL, a wiring WWL[1], a wiring WWL[2], a wiring RWL[1], and a wiring RWL[2]. The wiring WL and the wiring RL are semiconductor layers containing metal oxide. The wiring WL has regions WL1 to WL9, and the wiring RL has regions RL1 to RL9. Note that, although FIG. 34 shows an example in which the memory module has a first memory cell and a second memory cell, the number of memory cells that the memory module can have is not limited.

[0223] The first memory cell has a read transistor RTr[1], a write transistor WTr[1], and a capacitance CS[1]. The second memory cell has a read transistor RTr[2], a write transistor WTr[2], and a capacitance CS[2].

[0224] The gate electrode RTrG[1] of the transistor RTr[1] is located in a position overlapping with the regions WL2 and RL2. The wiring WWL[1] that functions as the gate electrode of the transistor WTr[1] is located in a position overlapping with the regions WL4 and RL4. Similarly, the gate electrode RTrG[2] of the transistor RTr[2] is located in a position overlapping with the regions WL6 and RL6. The wiring WWL[2] that functions as the gate electrode of the transistor WTr[2] is located in a position overlapping with the regions WL8 and RL8.

[0225] The capacitance CS[1] is formed by arranging the gate electrode RTrG[1] of the transistor RTr[1] at a position where it overlaps with the wiring RWL[1] via the insulator 102. Therefore, the gate electrode RTrG[1] can be said to be the first memory node of the first memory cell. Note that data stored in the first memory node is stored in the capacitance CS[1].

[0226] The capacitance CS[2] is formed by arranging the gate electrode RTrG[2] of the transistor RTr[2] at a position where it overlaps with the wiring RWL[2] via the insulator 102. Therefore, the gate electrode RTrG[2] can be said to be the second memory node of the second memory cell. The data held in the second memory node is held in the capacitance CS[2].

[0227] The wiring BG has a region that overlaps with the wiring RL via the insulator 104, and the wiring RL has a region that overlaps with the wiring WL via the insulator 103. The wiring BG is disposed inside the wiring RL via the insulator 104, and the wiring RL is disposed inside the wiring WL via the insulator 103.

[0228] As an example, the wiring BG has a region that functions as a back gate of the transistor RTr[1]. The wiring BG can also cause the regions RL1, RL3, RL4, RL5, RL7, RL8, and RL9 of the wiring RL to function as conductors.

[0229] The region RL2 functions as a channel formation region of the transistor RTr[1], the region RL6 functions as a channel formation region of the transistor RTr[2], the region RL4 functions as a back gate of the transistor WTr[1], and the region RL8 functions as a back gate of the transistor WTr[2].

[0230] Note that regions RL1, RL3, RL5, RL7, and RL9 can be made to function as conductors by applying a potential to regions WL1, WL3, WL5, WL7, and WL9. As a different method, regions RL1, RL3, RL5, RL7, and RL9 can be made to function as conductors by lowering the resistance value with impurities such as hydrogen diffusing from insulating layer 101 (insulators 101A to 101E).

[0231] Next, the electrical connection of the memory module will be described. Note that FIG. 1A can be used for the wiring WBL1, wiring RBL1, wiring RBL2, wiring WWL_D, wiring RWL_D1, wiring RWL_D2, selection transistor DTr1, selection transistor DTr2, and selection transistor DTr3, which are components of the memory module not shown in FIG.

[0232] First, the wiring WL will be described. Either the source or the drain of the selection transistor DTr1 is electrically connected to the wiring WBL1. The gate of the selection transistor DTr1 is electrically connected to the wiring WWL_D.

[0233] The other of the source or drain of the selection transistor DTr1 is electrically connected to the gate electrode RTrG[1] functioning as the first memory node through the region WL1. The region WL1 is preferably electrically connected to the gate electrode RTrG[1] through the region WL2. The gate electrode RTrG[1] is electrically connected to the region WL4 functioning as the channel formation region of the transistor WTr[1] through the region WL3. The gate electrode RTrG[1] is preferably electrically connected to the region WL3 through the region WL2.

[0234] The region WL4 is electrically connected to the gate electrode RTrG[2] functioning as the second memory node through the region WL5. The region WL5 is preferably electrically connected to the gate electrode RTrG[1] through the region WL6. The gate electrode RTrG[2] is electrically connected to the region WL8 functioning as the channel formation region of the transistor WTr[2] through the region WL7. The gate electrode RTrG[2] is preferably electrically connected to the region WL7 through the region WL6. The region WL8 is electrically connected to the wiring WBL1 through the region WL9 (not shown in FIG. 34).

[0235] Next, the wiring RL will be described. Either the source or the drain of the selection transistor DTr2 is electrically connected to the wiring RBL2. The gate of the selection transistor DTr2 is electrically connected to the wiring RWL_D1.

[0236] The other of the source or drain of the selection transistor DTr2 is electrically connected to a region RL2 that functions as a channel formation region of the transistor RTr[1] through a region RL1. The region RL2 is electrically connected to a region RL4 through a region RL3. The region RL4 functions as a back gate of the transistor WTr[1].

[0237] Region RL4 is electrically connected to region RL6, which functions as a channel formation region of transistor RTr[2], via region RL5. Region RL6 is electrically connected to region RL8 via region RL7. Region RL8 functions as a back gate of transistor WTr[2].

[0238] The region RL8 is electrically connected to one of the source or drain of the selection transistor DTr3 via a region RL9 (not shown in FIG. 34). The gate of the selection transistor DTr3 is electrically connected to the wiring RWL_D2.

[0239] The regions WL1 to WL9 can be put into a floating state using the selection transistor DTr1 and the transistor WTr[2], and the regions RL1 to RL9 can be put into a floating state using the selection transistor DTr2 and the selection transistor DTr3.

[0240] 35 to 40 are diagrams for explaining an example of the operation of the memory module.

[0241] FIG. 35 explains, as an example, the operation of a memory cell in a memory module during a data retention period. As an example, the potentials applied to each wiring during the retention period are shown in the figure. Note that the potentials are merely examples and are not limited to the above. Also, when "F-4V" is written, it means that the wiring is put into a floating state after -4V is applied to the wiring. As a different example, when "F0V" is written, the wiring is put into a floating state after 0V is applied to the wiring.

[0242] As an example, a potential of 0V to 3V is applied to the capacitance CS[1] or capacitance CS[2] as data. In addition, -2V is applied to the wiring BG. In the region RL1 of the wiring RL, -4V is applied from the wiring RBL2 through the selection transistor DTr2. In addition, in the region RL9 of the wiring RL, -4V is applied from the wiring RBL1 through the selection transistor DTr3. Then, the selection transistor DTr2 and the selection transistor DTr3 are turned off, and the wiring RL is in a floating state. In addition, 0V is applied to the wiring WL from the wiring WBL1 through the selection transistor DTr1. Then, the selection transistor DTr1 and the transistor WTr[2] are turned off, and the wiring WL is in a floating state. In addition, 0V is applied to the wiring WWL[1], the wiring RWL[1], the wiring WWL[2], and the wiring RWL[2], and then they are in a floating state.

[0243] As a different example, to put the wiring RL in a floating state, the wirings RBL1 and RBL2 may be put in a floating state, and to put the wiring WL in a floating state, the wiring WBL1 may be put in a floating state.

[0244] By making the potential of the wiring BG higher than the potential of the wiring RL, the resistance value of the wiring RL formed in the semiconductor layer is reduced. Therefore, the potential of -4V applied to the wiring RL is applied to the regions RL1, RL3, RL4, RL5, RL7, RL8, and RL9. At this time, a parasitic capacitance is formed between the wiring BG and the wiring RL via the insulator 104. In other words, the parasitic capacitance can hold the potential difference applied to the wiring BG and the wiring RL by putting the wiring RL in a floating state.

[0245] The regions RL4 and RL8 function as the back gates of the transistors WTr[1] and WTr[2], thereby reducing the off-current of the transistors WTr[1] and WTr[2]. Note that it is preferable to apply a lower potential to the back gates of the selection transistors DTr1, DTr2, and DTr3 than the potential applied to the wiring RL.

[0246] As another example, a potential lower than the potential applied to the wiring BG may be applied to the wiring RL. When a potential lower than the potential applied to the wiring BG is applied to the wiring RL, the off-state current of the transistor RTr[1] or the transistor RTr[2] can be reduced.

[0247] In addition, the region RL4 functioning as the back gate of the transistor WTr[1] is supplied with a potential that is capacitively coupled to the potential applied to the wiring BG via the parasitic capacitance described above. Therefore, a smaller potential is applied to the back gate of the transistor WTr[1]. The same is true for the region RL8 functioning as the back gate of the transistor WTr[2].

[0248] Therefore, the off-state current of the transistor WTr[1] or the transistor WTr[2] can be reduced, and the retention period of the data stored in each memory node can be extended.

[0249] 36 illustrates an example of the operation of a memory cell in a memory module during a data rewrite period. As an example, the potentials applied to the respective wirings during the rewrite period are shown in the figure. Note that the potentials are merely examples and are not intended to be limiting.

[0250] A voltage of 0V is applied from the wiring RBL2 to the region RL1 of the wiring RL via the selection transistor DTr2. A voltage of 0V is applied from the wiring RBL1 to the region RL9 of the wiring RL via the selection transistor DTr3. In the case of a memory module that performs data rewriting, a voltage of 3V is applied from the wiring WBL1 to the region WL1 or region WL9 of the wiring WL via the selection transistor DTr1. In the case of a memory module that does not perform data rewriting, a voltage of 0V is applied from the wiring WBL1 to the region WL1 or region WL9 of the wiring WL via the selection transistor DTr1. A voltage of -2V is applied to the wiring BG.

[0251] As an example, a case where the data of the capacitance CS[2] is rewritten via the region WL9 will be described. -5V is applied to the wiring WWL[1], 0V is applied to the wiring RWL[1], 3V is applied to the wiring WWL[2], and 0V is applied to the wiring RWL[2]. By applying -5V to the wiring WWL[1], the transistor WTr[1] is turned off, and by applying 3V to the wiring WWL[2], the transistor WTr[2] is turned on. Thus, the data of the capacitance CS[2] can be rewritten.

[0252] Although not shown, as a different example, a case will be described in which data in the capacitor CS[1] is rewritten via the area WLR9 and then data in the capacitor CS[2] is rewritten.

[0253] First, 3V is applied to the wire WWL[1], 0V is applied to the wire RWL[1], 3V is applied to the wire WWL[2], and 0V is applied to the wire RWL[2]. By applying 3V to the wire WWL[1], the transistor WTr[1] is turned on, and by applying 3V to the wire WWL[1], the transistor WTr[2] is turned on. Therefore, the data of the capacitance CS[1] can be rewritten.

[0254] Next, a case where the data of the capacitance CS[2] is rewritten via the region WLR9 will be described. -5V is applied to the wiring WWL[1], 0V is applied to the wiring RWL[1], 3V is applied to the wiring WWL[2], and 0V is applied to the wiring RWL[2]. By applying -5V to the wiring WWL[1], the transistor WTr[1] is turned off, and by applying 3V to the wiring WWL[2], the transistor WTr[2] is turned on. Thus, the data of the capacitance CS[2] can be rewritten.

[0255] Although not described in detail, data in the memory cells of the memory module may be rewritten via the area WL1.

[0256] 37 illustrates an example of the operation during a data read period (non-selection) from a memory cell in a memory module. As an example, the potentials applied to each wiring during the read period are shown in the figure. Note that the potentials are just an example and are not limited to the above.

[0257] Regions WL1 and WL9 of the wiring WL are given 0V via the wiring WBL1, and then are put into a floating state. It is also preferable that region RL1 of the wiring RL is given 3V via the wiring RBL2, and region RL9 of the wiring RL is given 0V via the wiring RBL1, and then is put into a floating state. Note that -2V is given to the wiring BG.

[0258] Next, −5V is applied to the wiring WWL[1] and the wiring WWL[2]. By applying −5V to the wiring WWL[1], the transistor WTr[1] is turned off. Also, by applying −5V to the wiring WWL[2], the transistor WTr[2] is turned off. Therefore, the data of the capacitances CS[1] and CS[2] is held.

[0259] 37, as an example, a case will be described in which 0 V is held in the capacitance CS[1] and 3 V is held in the capacitance CS[2]. 3 V is applied to the wiring RWL[1] and the wiring RWL[2].

[0260] The potential held by the capacitor CS[1] changes from 0V to 3V due to the capacitive coupling of the capacitor CS[1]. The potential held by the capacitor CS[1] is applied to the gate of the transistor RTr[1]. As a result, the transistor RTr[1] is turned on.

[0261] The potential held by the capacitor CS[2] changes from 3 V to 6 V due to the capacitive coupling of the capacitor CS[2]. The potential held by the capacitor CS[2] is applied to the gate of the transistor RTr[2]. As a result, the transistor RTr[2] is turned on.

[0262] Therefore, when 3V is applied to the wiring RWL[1] and the wiring RWL[2], the transistors RTr[1] and RTr[2] are turned on regardless of the amount of data stored in the capacitance CS. Therefore, when the memory cell in the memory module is not selected, the potential applied to the wiring RBL2 is output to the region RL9 of the wiring RL.

[0263] FIG. 38 explains, as an example, the operation during a data read period (selection) from a memory cell in a memory module. As an example, the potentials applied to each wiring during the read period are shown in the figure. Note that the potentials are merely an example and are not limited to the above. Note that FIG. 38 differs from FIG. 37 in that the potential applied to the wiring RWL[1] is 0V. Note that 0V is held in the capacitance CS[1] and 3V is held in the capacitance CS[2].

[0264] The wiring RWL[1] is supplied with 0V as the memory cell to be read. When the wiring RWL[1] is 0V, capacitive coupling via the capacitance CS[1] does not occur. Therefore, the potential held in the capacitance CS[1] is supplied to the gate of the transistor RTr[1]. Since the transistor RTr[1] maintains the off state, the potential applied to the wiring RBL2 is not output to the region RL9 of the wiring RL, so 0V is maintained.

[0265] Also, 3V is applied to the wiring RWL[2]. The potential held by the capacitor CS[2] changes from 3V to 6V due to the capacitive coupling of the capacitor CS[2]. The potential held by the capacitor CS[2] is applied to the gate of the transistor RTr[2]. Therefore, the transistor RTr[2] is turned on.

[0266] When the data held in the selected memory cell is 3 V, the potential applied to the wiring RBL2 is output to the region RL9 of the wiring RL. As a different example, when the data held in the selected memory cell is 0 V, the potential applied to the wiring RBL2 in the region RL9 of the wiring RL does not change from 0 V.

[0267] FIG. 39 explains, as an example, the transition operation from the data read period to the data retention period from the memory cell of the memory module. As an example, the potentials applied to each wiring during the read period and the change in potential when transitioning are shown in the figure. Note that the potentials are only an example and are not limited to the above. Note that -2V is applied to the wiring BG. 0V is applied to the wiring RWL[1] and the wiring RWL[2]. Note that 0V is held in the capacitance CS[1] and 3V is held in the capacitance CS[2].

[0268] First, the potential given to the region RL1 and the region RL9 of the wiring RL is changed from 3V to -3V. Next, the wiring WWL[1] and the wiring WWL[2] are changed from -5V to 0V. Next, the wiring RWL[1] and the wiring RWL[2] are changed from 3V to 0V. Next, the wiring RL, the wiring RWL[1], the wiring RWL[2], the wiring WWL[1], and the wiring WWL[2] are put into a floating state. The transistors RTr and WTr are OS transistors, and therefore have a small off-current. Therefore, when the memory module is power-gated, even if the wiring RL, the wiring RWL[1], the wiring RWL[2], the wiring WWL[1], and the wiring WWL[2] are put into a floating state, the data held in the capacitances CS[1] and CS[2] can be suppressed from deteriorating.

[0269] FIG. 40 explains, as an example, the transition operation from the data rewrite period to the data retention period from the memory cell of the memory module. As an example, the potentials applied to each wiring during the rewrite period and the change in potential when transitioning are shown in the figure. Note that the potentials are only an example and are not limited to the above. Note that -2V is applied to the wiring BG. 0V is applied to the wiring RWL[1] and the wiring RWL[2]. Note that 0V is held in the capacitance CS[1] and 3V is held in the capacitance CS[2].

[0270] First, the potentials applied to the regions WL1 and WL9 of the wiring WL are changed from 0V to -3V. Next, the wiring WWL[1] is changed from -5V to 0V, and the wiring WWL[2] is changed from 3V to 0V. Next, the wiring WL, the wiring WWL[1], the wiring WWL[2], the wiring RWL[1], and the wiring RWL[2] are put into a floating state. The transistors RTr and WTr are OS transistors, and therefore have a small off-current. Therefore, when the memory module is power-gated, even if the wiring WL, the wiring WWL[1], the wiring WWL[2], the wiring RWL[1], and the wiring RWL[2] are put into a floating state, the data held in the capacitances CS[1] and CS[2] can be suppressed from deteriorating.

[0271] The structures and methods described in this embodiment mode can be used in appropriate combination with structures and methods described in other embodiment modes.

[0272] (Embodiment 4) In this embodiment, a CPU that can include the semiconductor device of the above embodiment will be described.

[0273] FIG. 41 is a block diagram showing a configuration of an example of a CPU that partially uses the semiconductor device described in the first embodiment.

[0274] The CPU shown in FIG. 41 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F) on a substrate 1190. The substrate 1190 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 41 is merely an example of a simplified configuration, and an actual CPU has a wide variety of configurations depending on its application. For example, a configuration including the CPU or arithmetic circuit shown in FIG. 41 may be one core, and a configuration including a plurality of such cores, each of which operates in parallel, that is, a configuration like a GPU, may be used. In addition, the number of bits that the CPU can handle in its internal arithmetic circuitry and data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0275] An instruction input to the CPU via the bus interface 1198 is input to an instruction decoder 1193 , decoded, and then input to an ALU controller 1192 , an interrupt controller 1194 , a register controller 1197 , and a timing controller 1195 .

[0276] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits based on their priority and mask state while the CPU is executing a program. The register controller 1197 generates an address for the register 1196, and reads and writes data from and to the register 1196 depending on the state of the CPU.

[0277] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0278] 41, a memory cell is provided in a register 1196. The transistor described in the above embodiment can be used as the memory cell of the register 1196.

[0279] In the CPU shown in FIG. 41, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, it selects whether the memory cells in the register 1196 will hold data by flip-flops or by capacitance. If holding data by flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 1196. If holding data in capacitance is selected, the data is rewritten to the capacitance, and the supply of the power supply voltage to the memory cells in the register 1196 can be stopped.

[0280] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0281] (Embodiment 5) The storage device of the above embodiment can be applied to various removable storage devices such as a memory card (e.g., an SD card), a USB (Universal Serial Bus) memory, an SSD (Solid State Drive), etc. In this embodiment, some configuration examples of removable storage devices will be described with reference to FIG.

[0282] FIG. 42A is a schematic diagram of a USB memory. The USB memory 5100 has a housing 5101, a cap 5102, a USB connector 5103, and a board 5104. The board 5104 is housed in the housing 5101. A storage device and a circuit for driving the storage device are provided on the board 5104. For example, a memory chip 5105 and a controller chip 5106 are attached to the board 5104. The memory chip 5105 incorporates the memory cell array 2610, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, the column decoder 2631, and the like described in the second embodiment. The controller chip 5106 specifically incorporates a processor, a work memory, an ECC circuit, and the like. The circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to those described above, and may be changed as appropriate depending on the situation or circumstances. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, and column decoder 2631 may be incorporated in the controller chip 5106 instead of the memory chip 5105. The USB connector 5103 functions as an interface for connecting to an external device.

[0283] FIG. 42B is a schematic diagram of the appearance of an SD card, and FIG. 42C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a memory device and a circuit for driving the memory device. For example, a memory chip 5114 and a controller chip 5115 are attached to the substrate 5113. The memory chip 5114 incorporates the memory cell array 2610, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, the column decoder 2631, and the like described in the second embodiment. The controller chip 5115 incorporates a processor, a work memory, an ECC circuit, and the like. The circuit configurations of the memory chip 5114 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation or circumstances. For example, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, and the column decoder 2631 may be incorporated in the controller chip 5115 instead of the memory chip 5114.

[0284] The capacity of the SD card 5110 can be increased by providing a memory chip 5114 on the back side of the substrate 5113. A wireless chip having a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the memory chip 5114.

[0285] FIG. 42D is a schematic diagram of the appearance of an SSD, and FIG. 42E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a memory device and a circuit for driving the memory device. For example, the substrate 5153 is provided with a memory chip 5154, a memory chip 5155, and a controller chip 5156. The memory chip 5154 incorporates the memory cell array 2610, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, the column decoder 2631, and the like, which are described in the second embodiment. The capacity of the SSD 5150 can be increased by providing a memory chip 5154 on the back side of the substrate 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. A processor, an ECC circuit, and the like are built into the controller chip 5156. The circuit configurations of the memory chip 5154, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation or circumstances. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0286] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0287] (Embodiment 6) In this embodiment, an example of an electronic device to which the memory device in the above embodiment can be applied will be described.

[0288] <Notebook type personal computer> 43A shows a laptop personal computer including a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like. The storage device of one embodiment of the present invention can be provided in the laptop personal computer.

[0289] <Smart Watch (registered trademark)> FIG. 43B shows a smartwatch, which is a kind of wearable terminal, and includes a housing 5901, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, and the like. The storage device of one embodiment of the present invention can be provided in the smartwatch. A display device to which a function as a position input device is added may be used for the display unit 5902. The function as the position input device can be added by providing a touch panel in the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element also called a photosensor in a pixel portion of the display device. The operation buttons 5903 can include any of a power switch for starting the smartwatch, a button for operating an application of the smartwatch, a volume control button, and a switch for turning on or off the display unit 5902. Although the number of operation buttons 5903 is two in the smartwatch shown in FIG. 43B, the number of operation buttons of the smartwatch is not limited to this. The operator 5904 functions as a crown for setting the time of the smartwatch. In addition, the operation element 5904 may be used as an input interface for operating a smart watch application other than for setting the time. Note that, although the smart watch shown in FIG. 43B has the operation element 5904, the present invention is not limited to this, and may have a configuration without the operation element 5904.

[0290] <Video camera> 43C shows a video camera, which includes a first housing 5801, a second housing 5802, a display unit 5803, an operation key 5804, a lens 5805, a connection unit 5806, and the like. The storage device according to one embodiment of the present invention can be provided in the video camera. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display unit 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection unit 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection unit 5806. The video on the display unit 5803 may be switched according to the angle between the first housing 5801 and the second housing 5802 at the connection unit 5806.

[0291] <Mobile phone> FIG. 43D shows a mobile phone having a function of an information terminal, and includes a housing 5501, a display unit 5502, a microphone 5503, a speaker 5504, and an operation button 5505. The storage device of one embodiment of the present invention can be provided in the mobile phone. A display device to which a function as a position input device is added may be used as the display unit 5502. The function as the position input device can be added by providing a touch panel in the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element also called a photosensor in a pixel portion of the display device. The operation button 5505 can include any one of a power switch for starting the mobile phone, a button for operating an application of the mobile phone, a volume control button, a switch for turning on or off the display unit 5502, and the like.

[0292] In addition, the mobile phone shown in Fig. 43D has two operation buttons 5505, but the number of operation buttons of the mobile phone is not limited to this. Although not shown, the mobile phone shown in Fig. 43D may have a light-emitting device for use as a flashlight or illumination.

[0293] <Television equipment> 43E is a perspective view showing a television device. The television device includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared ray), and the like. The storage device of one embodiment of the present invention can be provided in the television device. The television device can incorporate a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

[0294] <Mobile object> The above-mentioned storage device can also be applied to the vicinity of the driver's seat of an automobile, which is a moving body.

[0295] For example, Fig. 43F is a diagram showing the periphery of the windshield in the interior of a car. Fig. 43F shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0296] The display panels 5701 to 5703 can provide various information by displaying navigation information, a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioner settings, etc. In addition, the display items and layouts displayed on the display panels can be changed as appropriate according to the user's preferences, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

[0297] The display panel 5704 can complement the field of view (blind spot) blocked by the pillar by displaying an image from an imaging means provided on the vehicle body. That is, by displaying an image from an imaging means provided on the outside of the vehicle, blind spots can be complemented and safety can be improved. In addition, by displaying an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0298] The storage device of one embodiment of the present invention can be provided in a mobile object. For example, the storage device of one embodiment of the present invention can be used as a frame memory for temporarily storing image data used when displaying images on the display panels 5701 to 5704, or a storage device for storing a program for driving a system included in the mobile object.

[0299] Although not shown, the electronic devices shown in Figures 43A to 43C, 43E, and 43F may have a microphone and a speaker. With this configuration, for example, the electronic devices described above can be provided with a voice input function.

[0300] Although not shown, the electronic devices shown in FIGS. 43A, 43B, and 43D to 43F may be configured to include a camera.

[0301] 43A to 43F may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared ray, etc.) inside the housing, although this is not shown. In particular, by providing a detection device having a sensor for detecting gradient such as a gyro or acceleration sensor to the mobile phone shown in Fig. 43D, the orientation of the mobile phone (the orientation of the mobile phone relative to the vertical direction) can be determined, and the screen display of the display unit 5502 can be automatically switched according to the orientation of the mobile phone.

[0302] 43A to 43F may have a device for acquiring biometric information such as a fingerprint, vein, iris, or voiceprint, although this is not shown in the drawings. By applying this configuration, an electronic device having a biometric authentication function can be realized.

[0303] A flexible substrate may be used as the display unit of the electronic device shown in Figures 43A to 43F. Specifically, the display unit may have a configuration in which transistors, capacitors, display elements, and the like are provided on a flexible substrate. By applying this configuration, electronic devices having a housing with a curved surface as well as a housing with a flat surface like the electronic device shown in Figures 43A to 43F can be realized.

[0304] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0305] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the description of each component in the above embodiment.

[0306] <Additional Notes on One Aspect of the Invention Described in the Embodiments> The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0307] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0308] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0309] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0310] <Note on ordinal numbers> In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0311] <Notes regarding the description of the drawings> The embodiments are described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the forms and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations thereof will be omitted.

[0312] In addition, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in order to explain the positional relationship between components with reference to the drawings. The positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, terms indicating arrangement are not limited to the descriptions explained in the specification, and can be rephrased appropriately depending on the situation.

[0313] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0314] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0315] In addition, in the drawings, such as perspective views, some components may be omitted in order to ensure clarity of the drawings.

[0316] In addition, in the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0317] <Notes on possible alternative descriptions> In this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or the operating conditions of the transistor. The source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation. In this specification, the two terminals other than the gate may be referred to as the first terminal, the second terminal, the third terminal, and the fourth terminal. In this specification, the channel formation region refers to a region where a channel is formed by applying a potential to the gate, and the formation of this region allows a current to flow between the source and the drain.

[0318] In addition, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0319] In addition, when a transistor described in this specification has two or more gates (this configuration may be referred to as a dual gate structure), the gates may be referred to as a first gate, a second gate, a front gate, and a back gate. In particular, the term "front gate" may be simply replaced with the term "gate". In addition, the term "back gate" may be simply replaced with the term "gate". Note that a bottom gate refers to a terminal that is formed before a channel formation region during the manufacture of a transistor, and a "top gate" refers to a terminal that is formed after a channel formation region during the manufacture of a transistor.

[0320] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0321] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground potential (earth potential), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0322] In this specification, terms such as "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the circumstances, terms such as "film" and "layer" may not be used and may be replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0323] In this specification, terms such as "wiring", "signal line", and "power line" can be interchanged depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0324] <Notes on definitions of terms> The following provides definitions of terms used in the above embodiments.

[0325] <<About impurities in semiconductors>> An impurity in a semiconductor refers to, for example, anything other than the main component constituting a semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The inclusion of an impurity may cause, for example, the formation of DOS (Density of States) in the semiconductor, the reduction in carrier mobility, or the reduction in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, and in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, oxygen vacancies may be formed by the inclusion of an impurity such as hydrogen. In addition, when the semiconductor is a silicon layer, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements other than oxygen and hydrogen.

[0326] <<About switches>> In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0327] As an example, an electrical switch or a mechanical switch can be used. In other words, the switch is not limited to a specific one as long as it can control the current.

[0328] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits that combine these.

[0329] When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0330] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0331] <<About connection>> In this specification, when it is stated that X and Y are connected, this includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, this is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, but also includes connection relationships other than those shown in a figure or text.

[0332] X, Y, etc. used here are objects (eg, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0333] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitor, an inductor, a resistive element, a diode, a display element, a light-emitting element, a load, etc.) that enable an electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0334] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0335] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the cases where X and Y are electrically connected (i.e., when they are connected with another element or circuit between them), where X and Y are functionally connected (i.e., when they are functionally connected with another circuit between them), and where X and Y are directly connected (i.e., when they are connected without another element or circuit between them). In other words, when it is explicitly stated that X and Y are electrically connected, this is the same as when it is explicitly stated that they are simply connected.

[0336] For example, the case where the source (or the first terminal, etc.) of the transistor is electrically connected to X via (or without) Z1 and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or the case where the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, can be expressed as follows.

[0337] For example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these expressions. Here, X, Y, Z1, and Z2 are objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0338] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0339] <<About parallel and perpendicular>> In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Explanation of symbols]

[0340] DM1: area, DM2: area, DTr1: selection transistor, DTr2: selection transistor, DTr3: selection transistor, RBL1: wiring, RBL2: wiring, RL1: area, RL2: area, RL3: area, RL4: area, RL5: area, RL6: area, RL7: area, RL8: area, RL9: area, RW2: area, RW4: area, RW6: area, RW8: area, RWL_D1: wiring, RWL_D2: wiring, WWL_D: wiring, SD1: area, SD2: area, WBL1: wiring, WBL1a: wiring, WBL2: wiring, WL1: area, WL2: area, WL3: area region, WL4: region, WL5: region, WL6: region, WL7: region, WL8: region, WL9: region, WLR9: region, WWL4: region, 10: memory module, 100: laminate, 101: insulating layer, 101A: insulator, 101B: insulator, 101C: insulator, 101D: insulator, 101E: insulator, 102: insulator, 103: insulator, 104: insulator, 105: insulator, 131A: conductor, 131B: conductor, 132A: conductor, 132B: conductor, 133: conductor, 133a: conductor, 133b: conductor, 133c: conductor, 134: conductor, 151: semiconductor body, 151a: region, 151b: region, 151c: region, 152: semiconductor, 153: semiconductor, 153a: semiconductor, 153b: semiconductor, 181A: region, 181B: region, 182A: region, 182B: region, 183A: region, 183B: region, 191: opening, 192A: recess, 192B: recess, 193A: recess, 193B: recess, 194A: recess, 194B: recess, 194C: recess, 1000: logic layer, 1189: ROM interface, 1190: substrate, 1191: ALU, 1192: ALU controller, 1193: instruction decoder , 1194: interrupt controller, 1195: timing controller, 1196: register, 1197: register controller, 1198: bus interface, 1199: ROM, 1700: substrate, 1701: element isolation layer, 1712: conductor, 1730: conductor, 1790: gate electrode, 1792: well, 1793: channel formation region, 1794: low concentration impurity region, 1795: high concentration impurity region, 1796: conductive region, 1797: gate insulating film, 1798: side wall insulating layer, 1799: side wall insulating layer, 2000: memory layer, 2600: storage device,2601: peripheral circuit, 2610: memory cell array, 2621: row decoder, 2622: word line driver circuit, 2630: bit line driver circuit, 2630A: bit line driver circuit, 2630B: bit line driver circuit, 2631: column decoder, 2632: precharge circuit, 2633: sense amplifier, 2634: circuit, 2640: output circuit, 2660: control logic circuit, 5100: USB memory, 5101: housing, 5102: cap, 5103: USB connector, 5104: board, 5105: memory chip, 5106: controller chip, 5110: SD card, 5111: housing, 5112: connector, 5113: board, 5114: memory chip, 5115: controller chip, 5150: SSD, 5151: housing, 5152: connector, 5153: board, 5154: memory chip, 5155: memory chip, 5156: controller chip, 5401: housing, 5402: display unit, 5403: keyboard, 5404: pointing device, 5501: housing, 5502: display unit, 5503: microphone, 5504: speaker, 5505: operation button, 5701: display panel, 5702: display panel, 5703: table display panel, 5704: display panel, 5801: housing, 5802: housing, 5803: display unit, 5804: operation keys, 5805: lens, 5806: connection unit, 5901: housing, 5902: display unit, 5903: operation button, 5904: operation element, 5905: band, 9000: housing, 9001: display unit, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor,

Claims

[Claim 1] A semiconductor device having a memory module, the memory module includes a first memory cell, a second memory cell, a first selection transistor, a second selection transistor, a write bit line, a read bit line, and a wiring; the first memory cell includes a first write transistor, a first read transistor, and a first capacitance element; the second memory cell includes a second write transistor, a second read transistor, and a second capacitance element; One of the source and the drain of the first selection transistor is always electrically connected to the write bit line, the other of the source and the drain of the first selection transistor is always electrically connected to the gate of the first read transistor; a back gate of the first selection transistor is always electrically connected to one of the source and the drain of the first read transistor; one of the source and the drain of the second selection transistor is always electrically connected to the read bit line; the other of the source and the drain of the second selection transistor is always electrically connected to one of the source and the drain of the first readout transistor; a back gate of the second selection transistor is always electrically connected to the wiring; one of the source and the drain of the first write transistor is always electrically connected to the gate of the first read transistor; the other of the source and the drain of the first write transistor is always electrically connected to the gate of the second read transistor; a back gate of the first write transistor is always electrically connected to the other of the source and the drain of the first read transistor; a gate of the first write transistor is always electrically connected to a first write word line; the other of the source and the drain of the first readout transistor is always electrically connected to one of the source and the drain of the second readout transistor; a back gate of the first read transistor is always electrically connected to the wiring; a first electrode of the first capacitance element is always electrically connected to a gate of the first read transistor; a second electrode of the first capacitance element is always electrically connected to a first read word line; one of the source and the drain of the second write transistor is always electrically connected to the gate of the second read transistor; a back gate of the second write transistor is always electrically connected to the other of the source and the drain of the second read transistor; a gate of the second write transistor is always electrically connected to a second write word line; a back gate of the second read transistor is always electrically connected to the wiring; a first electrode of the second capacitance element is always electrically connected to a gate of the second read transistor; a second electrode of the second capacitance element is always electrically connected to a second read word line; a channel formation region of the first read transistor, a channel formation region of the second read transistor, a back gate of the first write transistor, and a back gate of the second write transistor are provided in one continuous metal oxide film. Semiconductor device.

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