Imaging apparatus and data structure

Abstract

To improve frame rate while widening the dynamic range.SOLUTION: An imaging apparatus includes: pixels; a determination circuit configured to compare levels of analog signals read from the pixels with at least one threshold; an amplifying circuit which amplifies the analog signals with one of a plurality of amplification factors determined in accordance with comparison results of the determination circuit, and outputs the signals; an AD conversion circuit which converts the signals output from the amplification circuit into digital signals; and an output data generation circuit which adds additional information corresponding to the one amplification factor to the digital signals to generate output data related to the pixels.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to imaging devices and data structures. [Background technology]

[0002] In recent years, proposals have been made to realize a wide dynamic range in imaging devices such as charge coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors.

[0003] Patent document 1 describes an imaging device having a control unit that controls the gain applied to an analog signal output from a pixel to at least a first gain and a second gain higher than the first gain depending on the signal value of the analog signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-208291 A Summary of the Invention [Problem to be solved by the invention]

[0005] In an image capture device, it is desirable to increase the frame rate while expanding the dynamic range. [Means for solving the problem]

[0006] In one non-limiting exemplary embodiment, the imaging device of the present disclosure includes a pixel, a determination circuit that compares a level of an analog signal read from the pixel with at least one threshold value, an amplification circuit that amplifies and outputs the analog signal with one of a plurality of amplification factors determined in accordance with a comparison result of the determination circuit, an AD conversion circuit that converts the output signal from the amplification circuit into a digital signal, and an output data generation circuit that adds additional information corresponding to the one amplification factor to the digital signal to generate output data related to the pixel.

[0007] In another non-limiting exemplary embodiment, the imaging device of the present disclosure includes a pixel, a determination circuit that compares a level of an analog signal read from the pixel with at least one threshold value, a signal generation circuit that generates a ramp signal, an amplification circuit that amplifies and outputs the ramp signal with one of a plurality of amplification factors determined according to a comparison result of the determination circuit, an AD conversion circuit that converts the analog signal into a digital signal by referring to an output from the amplification circuit, and an output data generation circuit that adds additional information corresponding to the one amplification factor to the digital signal to generate output data related to the pixel.

[0008] In one non-limiting exemplary embodiment, the data structure of the present disclosure is a data structure of image data transferred from an imaging device having a plurality of pixels to an image processing circuit, the image data including pixel data associated with pixel signals read out from each of the plurality of pixels, the pixel data including a plurality of data bits indicating a level of the pixel signal and at least one flag bit encoding compression information of the pixel signal, the image processing circuit decodes the at least one flag bit to obtain the compression information, decodes the pixel signal based on the compression information to generate decoded image data, and performs image processing using the decoded image data. Effect of the Invention

[0009] According to one aspect of the present disclosure, there is provided an imaging device capable of improving a frame rate while expanding a dynamic range. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of a configuration of an imaging device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating a schematic configuration example of a pixel. [Diagram 3] FIG. 3 is a circuit diagram showing an example of a circuit configuration of a pixel. [Figure 4] FIG. 4 is a circuit diagram showing another example of the circuit configuration of a pixel. [Diagram 5] FIG. 5 is a block diagram illustrating a schematic configuration of a conversion circuit according to the first embodiment of the present disclosure. [Figure 6A] FIG. 6A is a circuit diagram showing an example of the configuration of a comparator at the functional block level. [Figure 6B] FIG. 6B is a circuit diagram showing an example of the configuration of the comparator at the symbol level. [Figure 6C] FIG. 6C is a circuit diagram showing an example of the configuration of the comparator at the transistor level. [Figure 6D] FIG. 6D is a diagram showing the relationship between the pixel signal VSIG, which is an input signal to the comparator, and the output signal DOUT1. [Figure 7] FIG. 7 is a circuit diagram showing an example of the configuration of the attenuator. [Figure 8A] FIG. 8A is a diagram illustrating a schematic configuration example of a holding circuit. [Figure 8B] FIG. 8B is a diagram showing a truth table of the latch circuit. [Figure 9] FIG. 9 is a block diagram illustrating a schematic configuration example of the conversion circuit according to the first embodiment of the present disclosure. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of the attenuator. [Figure 11] FIG. 11 is a schematic diagram showing the relationship between the range, threshold value, and attenuation rate of a pixel signal of an imaging device. [Figure 12] FIG. 12 is a schematic diagram showing another relationship between the range, threshold value, and attenuation rate of a pixel signal in an imaging device. [Figure 13] FIG. 13 is a schematic diagram showing an example of a data structure of image data output from an imaging device. [Figure 14] FIG. 14 is a table showing an example of the correspondence between flag bits and amplification factors when two flag bits are used. [Figure 15] FIG. 15 is a table showing the results obtained by shifting a bit string when a 12-bit string is used as a reference. [Figure 16] FIG. 16 is a table showing other results obtained by shifting operations on bit strings when a 12-bit string is used as a reference. [Figure 17] FIG. 17 is a timing chart showing an example of the procedure of the operation of an imaging device including the conversion circuit shown in FIG. [Figure 18] FIG. 18 is another timing chart showing an example of the procedure of the operation of the imaging device including the conversion circuit shown in FIG. [Figure 19] FIG. 19 is a block diagram illustrating a schematic configuration example of an imaging device according to the second embodiment of the present disclosure and an image processing circuit connected to the imaging device. [Figure 20] FIG. 20 is a block diagram illustrating a schematic configuration of a conversion circuit according to a second embodiment of the present disclosure. [Figure 21] FIG. 21 is a block diagram illustrating a schematic configuration of a conversion circuit according to a third embodiment of the present disclosure. [Figure 22A] FIG. 22A is a circuit diagram illustrating a configuration example of an attenuator according to a third embodiment of the present disclosure. [Figure 22B] FIG. 22B is a circuit diagram showing another configuration example of the attenuator according to the third embodiment of the present disclosure. [Diagram 23] FIG. 23 is a diagram illustrating a second configuration example of the holding circuit. [Figure 24] FIG. 24 is a timing chart showing an example of the procedure of the operation of the imaging device according to the third embodiment of the present disclosure. [Diagram 25] FIG. 25 is another timing chart showing an example of the procedure of the operation of the imaging device according to the third embodiment of the present disclosure. [Figure 26] FIG. 26 is a schematic diagram showing the relationship between the range, threshold value, and AD conversion gain of a pixel signal of an imaging device. [Figure 27] FIG. 27 is a diagram illustrating a schematic configuration example of a camera system according to the fourth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] <Knowledge that formed the basis of this disclosure> There is a known technique for expanding the dynamic range by changing the gain of an amplifier circuit for each pixel. For example, Patent Document 1 discloses such a technique.

[0012] A correlated double sampling (CDS) circuit is used to process pixel signals output from pixels. The CDS finds the difference between the levels of the pixel signal and the reset signal, resulting in a pixel signal with suppressed reset (kTC) noise. The CDS circuit may be provided in a signal processing circuit externally connected to the imaging device, or may be provided inside the imaging device. When the CDS circuit is externally connected to the imaging device, the imaging device needs to output two types of data, a reset signal and a pixel signal, to the outside in order to generate one frame of image. This has the disadvantage of reducing the frame rate by half or less compared to when the CDS circuit is provided inside the imaging device. Therefore, when the CDS circuit is externally connected to the imaging device, some ingenuity is required to avoid reducing the frame rate. It is also desirable to improve the frame rate of image data output from an imaging device equipped with a CDS circuit inside.

[0013] In order to solve the above problems, the inventors of the present application have focused on data compression of a digital signal output from an AD (Analog-to-Digital) converter, and have arrived at a novel imaging device that generates image data by adding additional information corresponding to the amplification factor of an amplifier circuit to a compressed digital signal. According to one aspect of the present disclosure, in an imaging device that can set a plurality of amplification factors (or attenuation factors) in an amplifier circuit (or attenuator), it is possible to improve the frame rate while realizing a wide dynamic range.

[0014] An outline of one aspect of the present disclosure is as follows.

[0015] [Item 1] Pixels and a determination circuit that compares a level of an analog signal read from the pixel with at least one threshold; an amplifier circuit that amplifies the analog signal at one of a plurality of amplification factors determined in accordance with a comparison result of the determination circuit, and outputs the amplified signal; an AD conversion circuit for converting an output signal from the amplifier circuit into a digital signal; an output data generating circuit that generates output data related to the pixel by adding additional information corresponding to the one amplification factor to the digital signal; An imaging device comprising:

[0016] [Item 2] Pixels and a determination circuit that compares a level of an analog signal read from the pixel with at least one threshold; a signal generating circuit for generating a ramp signal; an amplifier circuit that amplifies the ramp signal by one of a plurality of amplification factors determined according to a comparison result of the determination circuit, and outputs the amplified ramp signal; an AD conversion circuit that converts the analog signal into a digital signal by referring to an output from the amplifier circuit; an output data generating circuit that generates output data related to the pixel by adding additional information corresponding to the one amplification factor to the digital signal; An imaging device comprising:

[0017] [Item 3] 3. The imaging device according to claim 1, wherein the output data includes a plurality of data bits representing the digital signal and at least one flag bit representing the additional information.

[0018] [Item 4] 4. The imaging device of item 3, wherein the at least one flag bit includes two or more bits.

[0019] [Item 5] 3. The imaging device according to item 1 or 2, wherein the one amplification factor is smaller than 1 / 2 or larger than 2.

[0020] [Item 6] the analog signal includes a pixel signal representing an image of a subject and a reset signal indicating a reset level; The determination circuit compares a level of the pixel signal with the at least one threshold value; the amplifier circuit amplifies the pixel signal and the reset signal by the one amplification factor determined in response to a comparison result of the determination circuit; 2. The imaging device according to item 1, wherein the output data generation circuit generates the output data by adding the additional information to a difference between a digital signal corresponding to the pixel signal and a digital signal corresponding to the reset signal.

[0021] [Item 7] the analog signal includes a pixel signal representing an image of a subject and a reset signal indicating a reset level; The determination circuit compares a level of the pixel signal with the at least one threshold value; during a period in which the AD conversion circuit converts the pixel signal and the reset signal into a digital signal, the amplifier circuit amplifies the ramp signal by the one amplification factor determined in response to a comparison result of the determination circuit; 3. The imaging device according to item 2, wherein the output data generation circuit generates the output data by adding the additional information to a difference between a digital signal corresponding to the pixel signal and a digital signal corresponding to the reset signal.

[0022] [Item 8] the analog signal includes a pixel signal representing an image of a subject and a reset signal indicating a reset level; The determination circuit compares a level of the pixel signal with the at least one threshold value; the amplifier circuit amplifies the pixel signal by the one amplification factor determined in response to a comparison result of the determination circuit; 2. The imaging device according to item 1, wherein the output data generation circuit generates the output data by adding the additional information to the digital signal corresponding to the pixel signal.

[0023] [Item 9] the analog signal includes a pixel signal representing an image of a subject and a reset signal indicating a reset level; The determination circuit compares a level of the pixel signal with the at least one threshold value; during a period in which the AD conversion circuit converts the pixel signal and the reset signal into a digital signal, the amplifier circuit amplifies the ramp signal by the one amplification factor determined in response to a comparison result of the determination circuit; 3. The imaging device according to item 2, wherein the output data generation circuit generates the output data by adding the additional information to the digital signal corresponding to the pixel signal.

[0024] [Item 10] the additional information includes compression information of the digital signal; 3. The imaging device according to item 1 or 2, wherein a bit width of the output data is smaller than a bit width of data when the output data is restored based on the additional information.

[0025] [Item 11] A data structure of image data transferred from an imaging device having a plurality of pixels to an image processing circuit, the image data includes pixel data associated with pixel signals read out from each of the plurality of pixels; the pixel data includes a plurality of data bits indicating a level of the pixel signal and at least one flag bit that encodes compression information of the pixel signal; The image processing circuit includes: Decoding the at least one flag bit to obtain the compressed information; A data structure for decoding the pixel signal based on the compression information to generate decoded image data, and performing image processing using the decoded image data.

[0026] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection forms of components, processing contents, processing order, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as there is no contradiction. In addition, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components. In the following description, components having substantially the same functions are indicated by common reference symbols, and descriptions may be omitted.

[0027] <Overall configuration of the imaging device> First, the overall configuration of an imaging device according to an embodiment of the present disclosure will be described with reference to FIG. 1. FIG. 1 is a block diagram that illustrates an example of the configuration of an imaging device according to an embodiment of the present disclosure. The imaging device 200 illustrated in FIG. 1 is, for example, a solid-state imaging device having a so-called stacked type configuration described later. However, the imaging device 200 may be a solid-state imaging device such as a CMOS image sensor. The imaging device 200 includes a pixel unit 201, a vertical scanning circuit 202, a horizontal transfer scanning circuit 203, a signal generating circuit 204, a drive control circuit 205, a column processing unit 206, a plurality of vertical signal lines 212, a horizontal signal line 213, and an amplifier circuit 214.

[0028] The pixel unit 201 includes a plurality of pixels 10 arranged in a matrix. Each pixel 10 generates a signal charge having a magnitude according to the intensity of the incident light by photoelectrically converting incident light, and generates pixel signals VSIG0 to VSIGp (p is an integer equal to or greater than 1) that are electrical signals based on the signal charge. The pixel signals are an example of signals handled in the embodiment of the present disclosure. Details of the pixels 10 will be described later.

[0029] The vertical scanning circuit 202 is configured to control row addresses and row scanning. The vertical scanning circuit 202 generates pixel control signals such as VSEL or VRST, which will be described later, and outputs them to the pixel unit 201.

[0030] Each of the multiple vertical signal lines 212 is provided for each column, and is connected to pixels arranged in the corresponding column among the multiple pixels 10. More specifically, each vertical signal line 212 transmits pixel signals VSIG0 to VSIGp output from pixels 10 arranged in the corresponding column among columns 0 to p of the multiple pixels 10 to the column processing unit 206.

[0031] The column processing unit 206 includes a plurality of column circuits 207. Each column circuit 207 is provided for each column of a plurality of pixels 10. The column processing unit 206 generates image data based on a digital signal corresponding to a pixel signal output from each pixel 10. Each column circuit 207 includes a load current circuit 215 and a conversion circuit 220. Each column circuit 207 is connected to a vertical signal line 212 of a corresponding column. When a pixel signal is transmitted to the vertical signal line 212 of the corresponding column, the load current circuit 215 supplies a load current to the vertical signal line 212. The load current circuit 215 forms a source follower circuit together with the vertical signal line 212 and an amplifying transistor of the pixel described later. Each column circuit 207 in the embodiment of the present disclosure further includes a counter 209 and a memory 211 described later.

[0032] The signal generating circuit 204 generates a reference signal Vramp and supplies the generated reference signal Vramp to each of the multiple conversion circuits 220. The reference signal Vramp in the embodiment of the present disclosure is a ramp signal that at least monotonically increases or decreases. The ramp signal indicates a time change in a voltage value that changes at a predetermined rate of change (slope). The conversion circuit 220 compares the reference signal Vramp with the pixel signal transmitted from the pixel 10 to the vertical signal line 212. The configuration and operation of the conversion circuit 220 will be described in detail later.

[0033] The horizontal transfer scanning circuit 203 is configured to control column addresses and column scanning. The horizontal signal line 213 sequentially transmits a plurality of digital signals generated in the column processing unit 206 for each column. The amplifier circuit 214 is connected to the column processing unit 206 via the horizontal signal line 213. The digital signals of each column are amplified by the amplifier circuit 214 via the horizontal signal line 213 in order from the digital signal corresponding to the pixel signal output from the pixel of the column selected by the horizontal transfer scanning circuit 203, and output to the outside of the imaging device.

[0034] The imaging device 200 according to the embodiment of the present disclosure further includes a signal processing circuit 208 to which the digital signal output from the conversion circuit 220 is input. However, the signal processing circuit 208 is not essential. The signal processing circuit 208 may be realized by a microcontroller including one or more processors and memories. The signal processing circuit 208 may include a dedicated logic circuit that performs the processing described below.

[0035] The drive control circuit 205 generates signals for driving each circuit inside the imaging device 200. The drive control circuit 205 collectively generates various internal clocks based on a master clock signal input from an MCLK terminal and data signals for various settings input from a DATA terminal, and supplies the generated internal clocks to each circuit inside the imaging device 200. For example, the drive control circuit 205 supplies a control signal CN to the vertical scanning circuit 202. The vertical scanning circuit 202 operates according to this control signal CN.

[0036] <Pixel and conversion circuit configuration> An example of the configuration of the pixel 10 will be described with reference to FIGS.

[0037] FIG. 2 is a diagram showing a schematic configuration example of a pixel 10. FIG. 3 is a circuit diagram showing an example of a circuit configuration of the pixel 10. The pixel 10 shown in FIG. 2 includes a pixel electrode 12, a counter electrode 13 facing the pixel electrode 12, and a photoelectric conversion unit 18 including a photoelectric conversion layer 11 located between the pixel electrode 12 and the counter electrode 13. The photoelectric conversion unit 18 performs photoelectric conversion of incident light. The pixel electrode 12 and the counter electrode 13 are a pair of electrodes stacked on the photoelectric conversion layer 11 so as to sandwich the photoelectric conversion layer 11. Thus, the pixel 10 shown in FIG. 2 is a stacked photoelectric conversion element. However, the pixel in the embodiment of the present disclosure is not limited to a stacked photoelectric conversion element. The photoelectric conversion layer 11 generates excitons, for example, pairs of holes and electrons, upon receiving incident light. The pixel electrode 12 collects one of the generated pairs of holes and electrons as a signal charge. For example, a voltage is supplied to the counter electrode 13 so that a potential difference occurs between the pixel electrode 12 and the counter electrode 13, and one of the pairs of holes and electrons is collected by the pixel electrode 12 based on the potential difference.

[0038] The pixel 10 includes a charge storage section (hereinafter referred to as a "floating diffusion: FD") that stores the signal charge converted by the photoelectric conversion section 18. The FD is provided in a semiconductor substrate 15. The pixel electrode 12 and the FD are electrically connected via a contact plug 14. The signal charge collected by the pixel electrode 12 is stored in the FD.

[0039] The pixel 10 includes a readout circuit provided on the semiconductor substrate 15. The readout circuit of the pixel 10 shown in FIG. 3 includes an amplifier transistor M1, a selection transistor M2, and a reset transistor M3. The amplifier transistor M1 amplifies a pixel signal according to the magnitude of the charge accumulated in the FD. The selection transistor M2 selects whether or not to output the pixel signal amplified by the amplifier transistor M1 to the vertical signal line 212. In this way, a pixel signal according to the potential of the FD is output to the vertical signal line 212. The reset transistor M3 resets the FD to a desired reset voltage V1.

[0040] Fig. 4 is a circuit diagram showing another example of the circuit configuration of the pixel 10. The pixel 10 shown in Fig. 4 includes a photodiode PD as a photoelectric conversion unit, and further includes a transfer transistor M4 for transferring a signal charge generated in the photodiode PD to the FD. In this manner, the photoelectric conversion unit may be configured using a photoelectric conversion film or a photodiode. When the pixel 10 includes the photodiode PD, the pixel 10 may further include a transistor for discharging a signal charge generated in the photodiode PD. By using the transistor, multiple exposure is possible.

[0041] The exposure of the pixels 10 in the pixel unit 201 may be performed by global shutter driving or rolling shutter driving. In the embodiment of the present disclosure, the pixel 10 outputs a pixel signal VSIG and then outputs a reset signal in one frame period. The pixel signal VSIG read out by the readout circuit of the pixel 10 is transmitted to the conversion circuit 220 via the vertical signal line 212.

[0042] First Embodiment A conversion circuit according to a first embodiment of the present disclosure will be described with reference to FIGS.

[0043] [1. Configuration of conversion circuit] 5 is a block diagram illustrating a configuration of a conversion circuit 220a according to the first embodiment of the present disclosure. The conversion circuit 220a illustrated in FIG. 5 includes a comparator 240, an attenuator 250, a comparator 260, a holding circuit 270, a capacitance C1, and a capacitance Cramp.

[0044] The comparator 240 and the attenuator 250 are electrically connected to the pixel 10 via the vertical signal line 212, and the pixel signal VSIG from the pixel 10 is input. The input terminal of the holding circuit 270 is connected to the output terminal of the comparator 240. The output terminal of the holding circuit 270 is connected to the signal line 222. The output signal DOUT2 from the holding circuit 270 is output to the outside of the conversion circuit 220 via the signal line 222. Furthermore, the output terminal of the holding circuit 270 is also connected to the attenuator 250. One end of the capacitance C1 is connected to the output terminal of the attenuator 250, and the other end of the capacitance C1 is connected to the input terminal of the comparator 260. One end of the capacitance Cramp is connected to the signal generation circuit 204, and the other end of the capacitance Cramp is connected to another input terminal of the comparator 260. The output terminal of the holding circuit 270 may be connected to the input terminal of the comparator 240. In other words, the holding circuit 270 may be connected to the previous stage of the comparator 310.

[0045] In this embodiment, the counter 209 functions as an AD conversion circuit together with the conversion circuit 220. The counter 209 and the conversion circuit 220 include a CDS circuit that performs CDS processing. The counter 209 is an example of an output data generation circuit. Furthermore, the counter 209 (or the output data generation circuit) is configured to generate output data 210 related to pixels by adding additional information corresponding to one amplification factor determined according to a comparison result of a determination circuit described later to the digital signal.

[0046] An output terminal of the holding circuit 270 is connected to the counter 209 (see FIG. 1) via a signal line 222, and an output terminal of the comparator 260 is connected to the counter 209 via a signal line 221. Note that the output terminal of the comparator 260 may be connected to the memory 211 instead of the counter 209 via the signal line 221, or may be connected to both the counter 209 and the memory 211. Also, although the holding circuit 270 is disposed inside the conversion circuit 220a in the example shown in FIG. 5, it may be disposed inside the counter 209 or the memory 211.

[0047] [2. Comparator (judgment circuit)] The comparator 240 is electrically connected to the pixel 10 and configured to compare the level of the pixel signal VSIG, which is an analog signal, with at least one threshold value. The comparator 240 exemplifies a determination circuit. As described later, the comparator 240 may include an inverter circuit. The comparator 240 sets the gain of the attenuator 250 to one of a plurality of gains based on a comparison result of the level of the pixel signal VSIG with at least one threshold value.

[0048] FIG. 6A is a circuit diagram showing an example of the configuration of the comparator 240a at a functional block level. FIG. 6B is a circuit diagram showing an example of the configuration of the comparator 240a at a symbol level. FIG. 6C is a circuit diagram showing an example of the configuration of the comparator 240a at a transistor level. As shown in FIG. 6A to FIG. 6C, the comparator 240a is an inverter type comparator. However, the inverter type comparator is just one example, and there is no particular limitation as long as it is configured to compare the pixel signal VSIG with a predetermined threshold value. The comparator 240a is composed of two inverters 242 and 243. Hereinafter, the inverter circuit will be simply referred to as an "inverter".

[0049] The comparator 240a includes an inverter 242 and an inverter 243 connected in series. The pixel signal VSIG is input to the inverter 242, and an output signal from the inverter 242 is input to the inverter 243. The inverter 243 outputs an output signal DOUT1. The number of inverters connected in series is not limited to two as illustrated, and may be one or three or more. As the number of inverters increases, the driving capability can be improved.

[0050] 6C, the inverter 242 includes a P-type MOS transistor 242a and an N-type MOS transistor 242b. The inverter 243, like the inverter 242, includes a P-type MOS transistor 243a and an N-type MOS transistor 243b.

[0051] Fig. 6D is a diagram showing the relationship between the pixel signal VSIG, which is an input signal to the comparator 240a, and the output signal DOUT1. The upper part (a) of Fig. 6D shows the relationship between the pixel signal VSIG and the number of accumulated charges in FD, and the lower part (b) of Fig. 6D shows the relationship between the pixel signal VSIG and the output signal DOUT1.

[0052] In this specification, a logical change in the level of a digital signal from low to high may be expressed simply as "the signal level changes to high." Also, a logical change in the level of a digital signal from high to low may be expressed simply as "the signal level changes to low."

[0053] As shown in the upper part (a) of FIG. 6D, when a signal charge is generated by the incidence of light and is accumulated in the FD, the number of accumulated charges in the FD increases, and the pixel signal VSIG also increases. Also, as shown in the lower part (b) of FIG. 6D, when the pixel signal VSIG increases and exceeds the threshold voltage VTH0, the level of the output signal DOUT1 changes logically from Low to High. For example, the output signal DOUT1 changes from a digital value of zero to a digital value of one. Therefore, when the number of accumulated charges in the FD gradually increases and the pixel signal VSIG exceeds the threshold voltage VTH0, the level of the output signal DOUT1 from the comparator 240a changes logically from Low to High. In this way, when the voltage level of the pixel signal VSIG input to the comparator 240a is equal to or higher than the threshold voltage VTH0, the output signal DOUT1 becomes High, and conversely, when the voltage level of the pixel signal VSIG is lower than the threshold voltage VTH0, the output signal DOUT1 becomes Low. The threshold voltage VTH0 is the threshold voltage of the inverter 242, and is determined by the characteristics of the P-type MOS transistor 242a and the N-type MOS transistor 242b. Specifically, the threshold voltage VTH0 is determined by the following formula (1). VTH0 = (Vhigh - |Vtp| + Vtn·(β_n / β_p) 1 / 2 ) / (1 + (β_n / β_p) 1 / 2 ) (1) Here, Vhigh is the voltage applied to the source of the P-type MOS transistor 242a, Vtp is the threshold voltage of the P-type MOS transistor 242a, and Vtn is the threshold voltage of the N-type MOS transistor 242b. Also, β_p and β_n are constants defined by the following equations (2) and (3). β_p = (W_p / L_p)·μ_p·C_ox (2) β_n = (W_n / L_n)·μ_n·C_ox (3) Here, W_p is the gate width of the P-type MOS transistor 242a, L_p is the gate length of the P-type MOS transistor 242a, and μ_p is the carrier mobility of the P-type MOS transistor 242a. W_n is the gate width of the N-type MOS transistor 242b, L_n is the gate length of the N-type MOS transistor 242b, and μ_n is the carrier mobility of the N-type MOS transistor 242b. C_ox is the capacitance per unit volume of the gate oxide film of each of the P-type MOS transistor 242a and the N-type MOS transistor 242b.

[0054] The inverter 243 is designed, for example, based on the formulas (1) to (3) so that the threshold voltage of the inverter 243 becomes a desired threshold voltage VTH0. For example, the gate width and gate length of each of the P-type MOS transistor 243a and the N-type MOS transistor 243b are optimally designed to obtain the desired threshold voltage VTH0. In addition, taking the inverter 242 as an example, the substantial gate width or gate length can be adjusted by providing at least one of the P-type MOS transistor 242a and the N-type MOS transistor 242b in parallel or in series. The gate width or gate length of the inverter 243 can also be adjusted in the same manner as the inverter 242.

[0055] The inverter type comparator 240a according to the above-described configuration example can be configured with a small number of transistors, and is therefore characterized by its area-saving and power-saving features.

[0056] [3. Attenuator (amplifier circuit)] The attenuator 250 in this embodiment is electrically connected to the pixel 10. The attenuator 250 is configured to amplify and output an analog signal including a pixel signal and a reset signal at one of a plurality of amplification factors determined according to the comparison result of the judgment circuit. The attenuator 250 configured in this manner exemplifies an amplifier circuit. The one amplification factor set in the attenuator 250 is, for example, smaller than 1 / 2 (-6 dB) or larger than 2 (6 dB). The attenuator 250 in this embodiment amplifies each of the pixel signal and the reset signal at a single amplification factor set by the comparator 240. However, the attenuator 250 may amplify each of the pixel signal and the reset signal at different amplification factors. When the pixel signal and the reset signal are amplified at different amplification factors, the holding circuit 270 may not be provided, and the conversion circuit may have a circuit configuration as shown in FIG. 20, for example.

[0057] 7 is a circuit diagram showing a configuration example of the attenuator 250a. The attenuator 250a includes capacitances Ca and Cb, switches S1 and S2, and an inverter 224. The switch S1 is connected to an output terminal of the inverter 224 via a signal line 223. The switch S2 is connected to a signal line 222. The on / off of the switch S1 is controlled by an output signal from the inverter 224, and the on / off of the switch S2 is controlled by an output signal DOUT2 from a holding circuit 270. With such connections, the on / off of the two switches S1 and S2 is selectively controlled. When the switch S1 is on and the switch S2 is off, the voltage value of the pixel signal VSIG is output as it is to the signal line 251 as the output signal AOUT. When switch S1 is off and switch S2 is on, a voltage value calculated from the voltage division ratio (capacitance value of Cb) / (capacitance value of Ca+capacitance value of Cb) based on the voltage value of the pixel signal VSIG is output from signal line 222 as output signal DOUT2.

[0058] The attenuator is not particularly limited as long as it can attenuate the pixel signal VSIG. For example, the capacitances Ca and Cb in the example configuration shown in FIG.

[0059] In the embodiments of the present disclosure, either an attenuator having an attenuation factor less than 1 or an amplifier having an amplification factor greater than 1 can be used as the amplification circuit.

[0060] [4. Comparator] The comparator 260 in this embodiment is electrically connected to the attenuator 250. The analog signal output from the attenuator 250 is converted into a digital signal by the comparator 260 and the counter 209 at the rear stage. In other words, the comparator 260 and the counter 209 function as an AD conversion circuit. The AD conversion circuit converts the output signal from the attenuator 250 into a digital signal. The comparator 260 compares the pixel signal VSIG of the corresponding column input via either the switch S1 or S2 of the attenuator 250 and the capacitance C1 with the reference signal Vramp input via the capacitance Cramp, and outputs the comparison result. The output terminal of the comparator 260 is connected to the counter 209 at the rear stage via a signal line 221.

[0061] [5.Holding circuit] 5 is connected to the rear stage of the comparator 240. The holding circuit 270 holds the comparison result or pixel signal VSIG output from the comparator 240.

[0062] FIG. 8A is a diagram showing a schematic configuration example of a holding circuit. The holding circuit 270 according to the configuration example of FIG. 8A is a D-type latch circuit. However, the configuration of the holding circuit is not particularly limited as long as it is configured to hold the comparison result of the comparator 240 or the pixel signal VSIG. In the D-type latch circuit 271, as shown in the truth table shown in FIG. 8B, for example, when the control signal CNT supplied from the drive control circuit 205 is High, the output Q is determined based on the input of the D terminal, and when the control signal CNT is Low, the output Q is not considered with respect to the input of the D terminal, and the output Q before the control signal CNT becomes Low is held. In this configuration example, since it is desirable that the input to the D terminal is a voltage of High or Low level, the holding circuit 270 is connected to the rear stage of the comparator 240 as shown in FIG. 5. The holding circuit 270 in the example of FIG. 5 includes a latch circuit 271 electrically connected to the rear stage of the comparator 240 including an inverter circuit.

[0063] 8A or 8B, a signal line 225 connected to an output terminal Q# of the holding circuit 270 may be connected to the switch S1 instead of the signal line 223. In this case, the output signal from the output terminal Q# is used as a control signal for the switch S1.

[0064] The decision circuit of the conversion circuit 220a described above compares the level of the analog signal read from the pixel with one threshold value. However, the decision circuit may compare the level of the analog signal read from the pixel with two or more threshold values. In this case, the attenuator may amplify the analog signal with one of three or more gains determined according to the comparison result of the decision circuit.

[0065] FIG. 9 is a block diagram showing a schematic diagram of another example of the configuration of the conversion circuit according to the present embodiment. The conversion circuit 220b shown in FIG. 9 is different from the conversion circuit 220a shown in FIG. 5 in that it includes a first and a second comparator. The first comparator 240a is electrically connected to the pixel 10 and configured to compare the level of the pixel signal VSIG with at least one threshold value. The second comparator 240b is electrically connected to the pixel 10 and configured to compare the level of the pixel signal VSIG with at least one threshold value different from the at least one threshold value of the first comparator 240a. The conversion circuit 220b further includes a first holding circuit 270a electrically connected to the first comparator 240a and the attenuator 250 and holding the comparison result of the first comparator 240a, and a second holding circuit 270b electrically connected to the second comparator 240b and the attenuator 250 and holding the comparison result of the second comparator 240b. Two paths exist in parallel: a first comparator 240a and a first holding circuit 270a connected in series, and a second comparator 240b and a second holding circuit 270b connected in series.

[0066] In this configuration example, the threshold of the first comparator 240a is different from the threshold of the second comparator 240b. Therefore, the level of the output signal DOUT1a from the first comparator 240a is different from the level of the output signal DOUT1b from the second comparator 240b. In other words, the output signals DOUT1a and DOUT1b from the first and second comparators 240a and 240b change at different signal levels.

[0067] Fig. 10 is a circuit diagram showing a configuration example of an attenuator. The attenuator 250b shown in Fig. 10 has a configuration in which a capacitance Cc, a switch S3, an inverter 224b, and an AND circuit 252 are added to the attenuator 250a shown in Fig. 7. In the configuration shown in Fig. 10, each of the capacitances Ca, Cb, and Cc can be replaced with a resistor. However, the configuration of the attenuator is not limited to this. Any configuration can be adopted as long as it can make the voltage level of the input pixel signal VSIG 1 time, X times, or Y times (X ≠ Y, X < 1, Y < 1).

[0068] FIG. 11 is a schematic diagram showing the relationship between the range, threshold value VTH, and attenuation rate of the pixel signal VSIG of the imaging device 200 including the conversion circuit 220a. In this embodiment, as shown in FIG. 11, the threshold value VTH is set to 1 / 2 of the saturation signal level of the pixel. The attenuation rate of the attenuator 250 is 1 / 2. However, by setting the attenuation rate to less than 1 / 2, a greater noise reduction effect can be obtained. In addition, the level of the threshold value VTH is not limited to 1 / 2 of the saturation signal level, and can be made variable by either the circuit design, the control signal, or the control voltage.

[0069] 12 is a schematic diagram showing the relationship between the range, threshold VTH, and attenuation rate of the pixel signal VSIG of the imaging device 200 equipped with the conversion circuit 220b. The first comparator 240a has a threshold VTH1, and the second comparator 240b has a threshold VTH2. As shown in FIG. 12, the threshold VTH1 is set to 1 / 4 of the saturation signal level of the pixel, and the threshold VTH2 is set to 1 / 2 of the saturation signal level of the pixel.

[0070] The attenuator 250b illustrated in FIG. 10 has three types of attenuation rates, 1 (0 dB), 1 / 2 (-6 dB), and 1 / 4 (-12 dB), according to the level of the pixel signal VSIG. The attenuator 250b does not apply an attenuation process to a pixel signal VSIG whose signal level is less than a threshold VTH1. In this case, the attenuator 250b maintains the level of the pixel signal VSIG, that is, attenuates it to 1. The attenuator 250b applies an attenuation process to a pixel signal VSIG whose signal level is equal to or greater than the threshold VTH1 and less than the threshold VTH2. In this case, the attenuator 250b attenuates the pixel signal VSIG by 1 / 2. The attenuator 250b applies an attenuation process to a pixel signal VSIG whose signal level is equal to or greater than the threshold VTH2. In this case, the attenuator 250b attenuates the pixel signal VSIG by 1 / 4. With this method, even if the range of the AD conversion is, for example, 1 / 4 of the saturation level of the pixel, it is possible to appropriately place the level of the pixel signal VSIG within the range of the AD conversion according to the level of the pixel signal. The number of thresholds or attenuation rates is not limited to two or three, but may be four or more.

[0071] In this embodiment, a single-slope AD conversion circuit is exemplified as the AD conversion circuit, but the present invention is not limited to this. For example, a successive approximation type AD conversion circuit, a delta-sigma AD conversion circuit, or a cyclic type AD conversion circuit may also be used.

[0072] In an embodiment of the present disclosure, an analog signal read from the pixel 10 includes a pixel signal VSIG that represents an image of a subject, and a reset signal that indicates a reset level. The decision circuit compares the level of the pixel signal VSIG with at least one threshold. The attenuator 250 amplifies the pixel signal VSIG and the reset signal with one amplification factor that is determined according to the comparison result of the decision circuit. The AD conversion circuit converts each of the pixel signal VSIG and the reset signal into a digital signal. In this way, by amplifying the pixel signal VSIG and the reset signal with the same amplification factor, errors in CDS are less likely to occur. Furthermore, it is possible to improve the frame rate of output data output from an imaging device equipped with a CDS circuit inside.

[0073] The output data generation circuit generates output data 210 (see FIG. 1) by adding additional information to the difference between the digital signal corresponding to the pixel signal VSIG and the digital signal corresponding to the reset signal. More specifically, the output data generation circuit applies CDS processing to the output from the conversion circuit 220 to obtain differential data between the digital signal corresponding to the pixel signal VSIG and the digital signal corresponding to the reset signal. The CDS processing can be performed by the counter 209 switching the up-count and down-count operations between the pixel signal VSIG and the reset signal. The output data generation circuit generates the additional information based on, for example, the output signal DOUT2 (see FIG. 5). The output data generation circuit compresses the pixel signal after the CDS processing based on the additional information, and then adds the additional information to the compressed pixel signal to generate output data 210.

[0074] The output data 210 includes a plurality of data bits representing a digital signal obtained by compressing the difference between a digital signal corresponding to the pixel signal VSIG and a digital signal corresponding to the reset signal, and at least one flag bit representing additional information. The additional information corresponds to one amplification factor set in the attenuator 250 according to the comparison result of the decision circuit, and can be added by at least one flag bit that encodes compression information of the pixel signal VSIG after the CDS process. By generating such output data, it is possible to improve the frame rate.

[0075] [6. Image data compression] FIG. 13 is a schematic diagram showing an example of the data structure of image data output from an imaging device. FIG. 13 shows the structure of the minimum required image data for one frame. A frame start code (SOF), a line start code (SOL), an end of line (EOL) and an end of frame (EOF) are added to the image data shown in the figure. SOF indicates the start of one frame's worth of pixel data, and EOF indicates the end of one frame's worth of pixel data. SOL indicates the start of one line's worth of pixel data of a group of pixels located in the horizontal direction among the group of pixels arranged in a matrix, and EOL indicates the end of one line's worth of pixel data. There may be a header including SOF / SOL at the beginning of the image data. The header may include data or information related to the image data.

[0076] The pixel data X of one pixel corresponds to the output data output from the output data generating circuit for each pixel. In the embodiment of the present disclosure, the at least one flag bit may be 1, 2, or 3 or more bits. When one flag bit is used, the flag bit can be assigned to the most significant bit (MSB) of the pixel data X. Of course, it is also possible to assign the flag bit to the least significant bit (LSB) of the pixel data X. Consider a case where the amplification factors that can be set in the attenuator 250 are, for example, 0 dB and 12 dB. In other words, the multiple amplification factors include amplification factors 0 dB and 12 dB. In this case, for example, the flag bit "0" of the MSB indicates an amplification factor of 0 dB, and the flag bit "1" of the MSB indicates an amplification factor of 12 dB. In the subsequent processing, the flag bit is referred to, and if the flag bit is set to "1", the image data is multiplied by 4.

[0077] As described above, the output data for each pixel includes information on the amplification factor encoded by the flag bit, which can facilitate subsequent processing.

[0078] According to a conventional sensor, image data per pixel output from the sensor is expressed by, for example, 16 bits. If the digital value of pixel data X after CDS processing is, for example, (5533), 10 In this case, the pixel data X is represented by 16 bits (0001_0101_1001_1101)2. On the other hand, according to the imaging device of the present disclosure, the pixel data X can be represented by 14 bits including the flag bit. For example, (5533) 10 The pixel data X is represented by 14 bits (11_0101_1001_1101)2. In this example, the image data can be compressed from 16 bits to 14 bits, resulting in a compression effect of 2 bits. In the later processing, the MSB flag bit "1" is decoded and the pixel data X is multiplied by 4. That is, in the later processing, (11_0101_1001_1101)2 is expressed as (22132:5533×4) 10 The image data is treated as:

[0079] If flag bits are used, the transfer speed of image data will improve. For example, consider image data consisting of 2000 pixels x 4000 pixels, with 12 bits per pixel. If there are no flag bits, 96 Mbits of image data must be transferred per frame. On the other hand, if a 1-bit flag bit is used, the image data for one pixel can be expressed by 11 bits including the flag bit. If there are 88 Mbits of image data, the transfer of 88 Mbits of image data is equivalent to the transfer of 96 Mbits of image data without using flag bits. If the frame rate without flag bits is assumed to be 30 fps (frames per second), the frame rate with flag bits is 30*96 / 88 ≒ 32.7 fps. In this way, a speed increase of about 9% is expected. In this example, image data can be compressed from 12 bits to 11 bits, and a compression effect of 1 bit is obtained.

[0080] As described above, by setting a flag bit that encodes the amplification factor to be set in the attenuator 250 for each pixel, the effect of compressing pixel data is obtained, thereby making it possible to improve the frame rate.

[0081] At least one flag bit may include two or more bits. FIG. 14 is a table showing an example of the correspondence between flag bits and amplification factors when two flag bits are used. In this example, image data for one pixel is represented by 15 bits. The flag bits are assigned to the upper two bits on the MSB side of the 15 bits. The flag bits "00", "01", "10" and "11" indicate amplification factors of 0 dB, 12 dB, -24 dB and -12 dB, respectively. One of the amplification factors -24 dB, -12 dB, 0 dB and 12 dB is set in the attenuator 250 according to the comparison result of the decision circuit.

[0082] For reference, Fig. 14 shows the values ​​of 16-bit image data output from a conventional sensor. By using two flag bits, the image data can be compressed from 16 bits to 15 bits, resulting in a reduction of 1 bit. Even if overflow occurs in the data after post-processing, data compression can prevent the overflow from occurring, and as a result, a further expansion of the dynamic range can be expected.

[0083] In this embodiment, the output data generation circuit compresses the image data according to the amplification factor of the attenuator 250, that is, the additional information. As a result, the bit width of the output data (or image data) which is a digital signal is smaller than the bit width of the data when the output data is restored based on the additional information.

[0084] FIG. 15 is a table showing the results obtained by shifting a bit string when a 12-bit bit string is used as a reference. In FIG. 15, (3202) represented by 12 bits is 10 For example, when the pixel signal of a certain pixel is amplified with an amplification factor of 12 dB, the pixel signal level becomes (3202). 10 In this case, the conventional sensor outputs 12-bit output data (1100_1000_0010)2. In contrast, the imaging device of the present disclosure compresses the 12-bit image data into 11-bit image data, for example, by adding a 1-bit flag bit to the image data. When the flag bit "1" indicates an amplification factor of 12 dB, the output data generation circuit applies a shift operation to the 12-bit data (1100_1000_0010)2 and shifts it right by 2 bits to generate 10-bit data (11_0010_0000)2. The output data generation circuit adds a 1-bit flag bit to the MSB side of the 10-bit data (11_0010_0000)2 to generate 11-bit output data (111_0010_0000)2. The 11-bit output data (111_0010_0000)2 is a pixel signal level (3202) 10 Equivalent level (3200 = 4 × 800) 10In this way, data compression to 1 bit is possible, which enables faster data transfer and a wider dynamic range.

[0085] FIG. 16 is a table showing other results obtained by shifting bit strings when a 12-bit bit string is used as a reference. FIG. 16 shows the result of shifting bit strings of (4092) represented by 12 bits. 10 For example, if the pixel signal of a certain pixel is amplified by an amplification factor of 12 dB, the pixel signal level becomes (4092). 10 In this case, the conventional sensor outputs 12-bit output data (1111_1111_1100)2. In contrast, according to the imaging device of the present disclosure, when the flag bit "1" indicates an amplification factor of 12 dB, the output data generation circuit applies a shift operation to the 12-bit data (1111_1111_1100)2 and shifts it right by two bits to generate 10-bit data (11_1111_1111)2. The output data generation circuit adds one flag bit to the MSB side of the 10-bit data (11_1111_1111)2 to generate 11-bit output data (111_1111_1111)2. The 11-bit output data (111_1111_1111)2 corresponds to the pixel signal level (4092) 10 In this way, data compression to 1 bit is possible, which enables faster data transfer and a wider dynamic range.

[0086] An image processing circuit may be connected to the imaging device 200. The image processing circuit will be described later. The image processing circuit may decode at least one flag bit to obtain additional information indicating an amplification factor, and may decode pixel data based on the additional information to generate decoded image data. The image processing circuit may perform image processing using the decoded image data.

[0087] [7. AD conversion operation] 1 again, an operation of AD conversion by the conversion circuit 220 included in the imaging device 200 according to an embodiment of the present disclosure will be described. The imaging device 200 according to an embodiment of the present disclosure is an image sensor using a column-parallel AD conversion method. When capturing an image with the imaging device 200, light incident on the imaging device 200 is converted into a pixel signal, which is an electrical signal, in the pixel unit 201.

[0088] Operations such as exposure and readout of each of the multiple pixels 10 in the pixel unit 201 are controlled row by row by the vertical scanning circuit 202. Pixel signals VSIG0 to VSIGp generated in the multiple pixels 10 belonging to a row selected by the vertical scanning circuit 202 are simultaneously output to multiple vertical signal lines 212. At this time, each of the multiple load current circuits 215 (or source follower circuits) supplies a load current to the corresponding vertical signal line 212 among the multiple vertical signal lines 212.

[0089] The operation of the conversion circuit 220 performing AD conversion on the pixel signal VSIG will be described in detail with reference to FIG.

[0090] The comparator 260 compares the reference signal Vramp output by the signal generating circuit 204 with the pixel signal VSIG of the column corresponding to the comparator 260. The counter 209 counts the time from when it starts counting at a timing corresponding to the start timing of the ramp signal until the magnitude relationship between the level of the pixel signal VSIG and the level of the reference signal Vramp is inverted. This converts the pixel signal VSIG, which is an analog signal, into a digital signal corresponding to the count value of the counter 209. The comparator 260 and the counter 209 function as an AD conversion circuit. The pixel signal VSIG of each column is converted from an analog signal to a digital signal by the AD conversion circuit of each column.

[0091] The digital signals output from the AD conversion circuit are stored in the memory 211 included in the column circuit 207 of each column. The digital signals stored in the memory 211 of each column are output via the amplifier circuit 214 in order from the column selected by the horizontal transfer scanning circuit 203.

[0092] The comparator 240 compares the level of the pixel signal VSIG of the corresponding column with a predetermined threshold voltage. The comparator 240 outputs a high or low voltage signal indicating whether the level of the pixel signal VSIG is equal to or greater than the predetermined threshold to the signal line 222. For example, the comparator 240 outputs a logically high level signal when the level of the pixel signal VSIG is equal to or greater than the predetermined threshold, and outputs a logically low level signal when the magnitude of the pixel signal VSIG is less than the predetermined threshold. Naturally, it goes without saying that the logic may be reversed.

[0093] When the level of the pixel signal VSIG is equal to or higher than a predetermined threshold, the attenuator 250 attenuates the input pixel signal VSIG by 1 / N (N is 1 or more) and outputs the attenuated signal to the subsequent stage. The operation of the attenuator 250 will be described in detail later.

[0094] [8. Overall operation of the imaging device] Generally, when the AD conversion range is smaller than the maximum range (or full range) of the pixel signal output from the pixel, the pixel signal must be attenuated so that it falls within the AD conversion range. On the other hand, when the pixel signal is attenuated, the noise in the processing after AD conversion becomes larger relative to the pixel signal. Therefore, using an attenuator can reduce the S / N ratio in dark situations or when the subject is in low light. Here, the ratio of the noise level to the voltage level of the pixel signal is generally called the "S / N ratio" or simply "S / N".

[0095] In this embodiment, when the level of a pixel signal exceeds a threshold, AD conversion is performed after applying an attenuation process to the pixel signal, and when the level of the pixel signal falls below the threshold, AD conversion can be performed without attenuating the pixel signal and maintaining the pixel signal at its original level. The imaging device according to this embodiment makes it possible to AD convert the pixel signal in the maximum range of the pixel signal while avoiding S / N degradation in low illuminance. This can improve the dynamic range. Furthermore, the time required for AD conversion is shortened, so the imaging device according to this embodiment also contributes to high speed.

[0096] The operation of the imaging device 200 according to this embodiment will be described with reference to the timing chart of FIG.

[0097] Each of Fig. 17 and Fig. 18 is a timing chart showing an example of the operation procedure of the imaging device 200 including the conversion circuit 220a shown in Fig. 5. Fig. 17 shows an example of each signal waveform when the level of the pixel signal VSIGp exceeds the threshold value of the comparator 240. In the explanation of the operation procedure of the imaging device 200, each of the multiple pixels 10 is a stacked photoelectric conversion element. The comparator 240 of the conversion circuit 220a has the configuration shown in Fig. 6A, the attenuator 250 has the configuration shown in Fig. 7, and the holding circuit 270 has the configuration shown in Fig. 8A.

[0098] A horizontal synchronization signal HD, which is a pulse signal, is input from the vertical scanning circuit 202 to the pixel unit 201. Imaging of the nth row of the pixel unit 201 starts at the rising edge of the horizontal synchronization signal HD. A selection signal VSELn is input to the gate of a selection transistor M2 (see FIG. 3) included in each of the multiple pixels 10 in the nth row. When the selection signal VSELn is HIgh, the selection transistor M2 is turned on, and a pixel signal according to the potential of FD is output to the vertical signal line 212.

[0099] When the selection transistor M2 is turned on, the pixel signal VSIG is read out to the vertical signal line 212, which causes the potential of the vertical signal line 212 to start changing. The threshold value VTH of the comparator 240 is shown together with the pixel signal VSIG in the timing chart of Fig. 17. The threshold value VTH in this embodiment is set to, for example, 1 / 2 the saturation signal voltage of the pixel 10.

[0100] A reset control signal VRSTn is input to the gate of the reset transistor M3 (see FIG. 3) included in each of the multiple pixels 10 in the nth row. During a period when the reset control signal VRSTn is High, the reset transistor M3 is turned on and the potential of FD is reset to the reset voltage V1.

[0101] 8A, a control signal CNT that controls the latch operation is input to the latch circuit 271. When the level of the control signal CNT is High, the output Q is determined based on the input to the D terminal, and when the level of the control signal CNT is Low, the output Q is not affected by the input to the D terminal, and the output Q before the level of the control signal CNT became Low is held.

[0102] 17 shows the time change of the output signal AOUT from the attenuator 250 (the potential change of the signal line 251), the time change of the output signal DOUT1 from the comparator 240, and the time change of the output signal DOUT2 from the holding circuit 270 (the potential change of the signal line 222). The output signal DOUT2 is input to the attenuator 250 and controls the on / off of the switch S2 shown in FIG. 7. Also shown is the time change of the inverted signal of the output signal DOUT2 output from the inverter 224 of the attenuator 250 (the potential change of the signal line 223). The inverted signal of the output signal DOUT2 controls the on / off of the switch S1.

[0103] First, at time t0, the level of the horizontal synchronization signal HD changes from low to high, starting imaging of the pixels in the nth row of the pixel section 201. At time t1, the level of the horizontal synchronization signal HD changes from high to low.

[0104] Next, at time t2, the selection signal VSELn goes High, the selection transistor M2 turns on, and the pixel signal VSIG of the nth row is output to the vertical signal line 212. In addition, the control signal CNT goes High, and the holding circuit 270 operates in an operation mode in which it outputs an output value based on the pixel signal VSIG.

[0105] Next, at time t3 when the level of the pixel signal VSIG exceeds the threshold VTH of the comparator 240, the output signal DOUT1 from the comparator 240 becomes High. As a result, the inverted signal of the output signal DOUT2 output from the inverter 224 of the attenuator 250, which was High when the level of the pixel signal VSIG was below the threshold VTH, becomes Low, and the state of the switch S1 of the attenuator 250 changes from ON to OFF. Then, the output signal DOUT2, which was Low when the level of the pixel signal VSIG was below the threshold VTH, becomes High, and the state of the switch S2 of the attenuator 250 changes from OFF to ON. In this state, the pixel signal VSIG input to the attenuator 250 is subjected to an attenuation process, and as a result, the voltage level of the output signal AOUT from the attenuator 250 becomes capacitance Cb / (capacitance Ca+capacitance Cb) times the voltage level of the pixel signal VSIG.

[0106] In this embodiment, the capacitance Ca is the same as the capacitance Cb. In this case, the attenuation rate of the attenuator 250 is 1 / 2. By applying an attenuation process to the pixel signal VSIG according to the level of the pixel signal VSIG, the pixel signal VSIG can be placed within the voltage range of the AD conversion circuit.

[0107] Next, at time t4, the signal generating circuit 204 starts generating the reference signal Vramp. During the period from time t4 to time t5, the comparator 260 compares the voltage according to the reference signal Vramp with the output signal AOUT from the attenuator 250, and the counter 209 continues counting until the output levels of the two match. Also, at time t4, the control signal CNT goes low, and the holding circuit 270 holds the current output value. The holding circuit 270 holds the output value until the control signal CNT next goes high. As a result, the output signal DOUT2 does not change and remains high.

[0108] Next, at time t5, the reset control signal VRSTn applied to the pixels 10 in the nth row goes High, and the reset transistor M3 starts the reset operation of the pixels 10 in the nth row. Thereafter, at time t6 when the potential level of the vertical signal line 212 corresponding to the level of the reset signal falls below the threshold VTH of the comparator 240, the level of the output signal DOUT1 changes from High to Low. At this time, the level of the control signal CNT remains Low, so that the output signal DOUT2 from the holding circuit 270 does not change.

[0109] Next, at time t7, the reset control signal RSTn changes from High to Low, completing the reset operation. Also, at time t7, the signal generating circuit 204 starts generating the reference signal Vramp. During the period from time t7 to time t9, the comparator 260 compares the voltage corresponding to the reference signal Vramp with the reset signal, and the counter 209 continues counting until the output levels of the two match.

[0110] Next, at time t10, the horizontal synchronization signal HD goes high, and the imaging device 200 transitions to a readout operation of the pixels 10 in the (n+1)th row.

[0111] In this way, during the period when the selection signal VSELn is high, a first comparison is made by the comparator 260 between the level of the pixel signal VSIG and the level of the reference signal Vramp, and then, after the reset operation is completed, a second comparison is made by the comparator 260 between the reset signal and the reference signal Vramp.

[0112] 18 shows an example of each signal waveform when the level of the pixel signal VSIG falls below the threshold of the comparator 240. Below, differences from the case where the pixel signal VSIG exceeds the threshold of the comparator 240 described above will be mainly described.

[0113] 18, because the level of the pixel signal VSIG read out from the pixel 10 is lower than the threshold VTH of the comparator 240, the output signal DOUT1 from the comparator 240 does not change from Low, and as a result, the output signal DOUT2 from the holding circuit 270 and the output signal from the inverter 224 of the attenuator 250 (the inverted signal of the output signal DOUT2) maintain their Low and High states, respectively. Therefore, the switch S1 of the attenuator 250 is turned on, and the switch S2 is turned off. Therefore, the pixel signal VSIG is not attenuated by the attenuator 250, and an output signal AOUT corresponding to the voltage level of the pixel signal VSIG is output from the attenuator 250.

[0114] As described above, when the level of the pixel signal VSIG exceeds the threshold value VTH of the comparator 240, the pixel signal VSIG is attenuated by the attenuator 250, and when the pixel signal Vsig is below the threshold value VTH of the comparator 240, the pixel signal VSIG is not attenuated by the attenuator 250. By operating the conversion circuit 220 in accordance with the above-mentioned operation sequence, it is possible to perform AD conversion of the pixel signal VSIG in the maximum range of the pixel signal while avoiding S / N degradation at low illuminance, and thus the dynamic range can be improved.

[0115] In an embodiment of the present disclosure, the comparison result between the level of the pixel signal VSIG and the threshold value of the comparator 240 is provided to a downstream output data generation circuit. The comparison result may also be provided to the memory 211. For example, the signal processing circuit 208 inside the imaging device 200 or a camera signal processing unit, which will be described later and is externally connected to the imaging device, may correct the AD conversion value by shifting the AD conversion value in accordance with the attenuation rate of each pixel so that the level of the pixel signal VSIG of each pixel 10 matches the magnitude of the AD conversion value.

[0116] According to the pixel configuration and operation sequence of this embodiment, after a pixel signal corresponding to the intensity of incident light is read out, the pixel is reset and a reset signal is read out. In this way, the pixel signal is first read out, and the attenuation factor of the attenuator is determined based on the magnitude relationship between the level of the pixel signal and the threshold value of the comparator, so that the subsequent reset signal can also be read out at the same attenuation factor. By using the same attenuation factor for reading out the pixel signal and the reset signal, it is possible to improve the SNR without generating unnecessary offsets in the processing after AD conversion.

[0117] <Second embodiment> The configuration of an imaging device according to a second embodiment of the present disclosure will be described with reference to Fig. 19 and Fig. 20. The imaging device according to the second embodiment differs from the imaging device according to the first embodiment in that it does not include a CDS circuit and is externally connected to a CDS circuit. The following mainly describes the differences.

[0118] FIG. 19 is a block diagram illustrating a schematic configuration example of an imaging device 200a according to the second embodiment of the present disclosure and an image processing circuit 800 connected to the imaging device 200a.

[0119] The imaging device 200a includes a plurality of pixels 10, a plurality of column circuits 207, and an output data generation circuit 290. Each column circuit 207 may have a load current circuit, a conversion circuit, and a counter, similar to the imaging device 200 according to the first embodiment. In the block diagram of FIG. 19, only the symbols of the attenuator 250 and the AD conversion circuit included in the conversion circuit are shown within the dotted line frame indicating each column circuit 207.

[0120] 20 is a block diagram showing a schematic configuration of a conversion circuit 220c according to a second embodiment of the present disclosure. Unlike the conversion circuit 220a according to the first embodiment, the conversion circuit 220c according to the second embodiment does not have a holding circuit. The output signal DOUT1 from the comparator 240 is output to the outside of the conversion circuit 220c via a signal line 222.

[0121] In this embodiment, the decision circuit compares the level of the pixel signal with at least one threshold value. The attenuator 250 amplifies the pixel signal VSIG by an amplification factor determined according to the comparison result of the decision circuit.

[0122] The output data generation circuit 290 compresses the digital signal corresponding to the pixel signal VSIG based on the additional information. The output data generation circuit 290 adds the additional information to the compressed digital signal to generate output data. In contrast, the output data generation circuit 290 does not compress the digital signal corresponding to the reset signal, and outputs the digital signal as is as output data without adding any additional information to the digital signal. In this way, the digital signal added with the additional information and the digital signal corresponding to the reset signal are output from the output data generation circuit 290 to the outside.

[0123] With this configuration, it is possible to improve the frame rate when the CDS circuit is externally connected to the imaging device.

[0124] 20 includes an input I / F 810, frame memories 820 and 830, a decoding processing unit 840, a subtraction processing unit 850, and an image processing unit 860. The functions of the decoding processing unit 840, the subtraction processing unit 850, and the image processing unit 860 may be implemented in, for example, a microcontroller including one or more processors and memories. The frame memories 820 and 830, the decoding processing unit 840, and the subtraction processing unit 850 function as a CDS circuit.

[0125] The digital signal to which the additional information has been added and the digital signal corresponding to the reset signal, which are output from the output data generation circuit 290 of the imaging device 200a, are input to the input I / F 810. Uncompressed data of the digital signal corresponding to the reset signal is held in the frame memory 820, and compressed data of the digital signal to which the additional information has been added is held in the frame memory 830.

[0126] The decoding processor 840 reads out a digital signal corresponding to the pixel signal VSIG from the frame memory 830, and decodes the flag bit added to the digital signal. The decoding processor 840 decodes the digital signal compressed with an amplification factor corresponding to the flag bit, and generates decoded data. For example, if the 2-bit flag bit indicates an amplification factor of 12 dB, the decoding processor 840 multiplies the 14-bit compressed data (11_0101_1001_1101)2 by 4 to generate 16-bit decoded data (1101_0110_0111_0100)2.

[0127] The subtraction processing unit 850 reads out the uncompressed data from the frame memory 820. The subtraction processing unit 850 calculates the difference between the decoded data decoded by the decoding processing unit 840 and the uncompressed data to generate decoded image data. This makes it possible to suppress reset (kTC) noise or manufacturing variations in the transistors that constitute the pixels 10.

[0128] The image processor 860 performs image processing using the decoded image data. The image processor 860 applies processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance to the decoded image data.

[0129] A display device 900 may be connected to the image processing circuit 800. Examples of the display device 900 are a liquid crystal display or an organic EL display. Image data output from the image processing unit 860 is input to the display device 900, and an image represented by the image data is displayed on the display device 900.

[0130] <Third embodiment> A conversion circuit according to a third embodiment of the present disclosure will be described with reference to Fig. 21 to Fig. 25. The conversion circuit according to the third embodiment differs from the conversion circuit according to the first or second embodiment in that it includes an attenuator electrically connected to a comparator and a signal generating circuit. The following mainly describes the difference.

[0131] Fig. 21 is a block diagram showing a schematic configuration of a conversion circuit according to a third embodiment of the present disclosure. The conversion circuit 220d shown in Fig. 21 includes a comparator 260 electrically connected to the pixel 10, which converts the pixel signal VSIG and the reset signal, each of which is an analog signal and is read out from the pixel 10, into a digital signal, a signal generating circuit 204 which generates and outputs a ramp signal which is a reference signal Vramp, an attenuator 255 electrically connected to the comparator 260 and the signal generating circuit 204, which amplifies the ramp signal by one of a plurality of amplification factors, and outputs the ramp signal to the comparator 260, and a comparator 240 electrically connected to the pixel 10 and which compares the level of the pixel signal VSIG with at least one threshold value.

[0132] The attenuator 255 in this embodiment is configured to amplify the ramp signal by the amplification factor set by the comparator 240 during the period in which the pixel signal VSIG and the reset signal are converted into digital signals.

[0133] 22A and 22B are circuit diagrams showing an example of the configuration of an attenuator according to a third embodiment of the present disclosure. The configuration of the attenuator 255 shown in FIG. 22A or 22B differs from the configuration of 250a shown in FIG. 7 in that the polarities of the control signals of the switches S1 and S2 are inverted. The reason for inverting the polarities of the control signals is that, in the first embodiment, the attenuator 250 attenuates the signal when the level of the pixel signal VSIG is relatively large, whereas in the third embodiment, the attenuator 255 attenuates the reference signal Vramp when the level of the pixel signal VSIG is relatively small.

[0134] The comparator 240 sets the amplification factor of the attenuator 255 to one of a plurality of amplification factors based on a result of comparing the level of the pixel signal VSIG with at least one threshold value. In this embodiment, the signal generating circuit 204 is connected to the attenuator 255, so that the slope of the reference signal Vramp, i.e., the amount of change in voltage per unit time, changes depending on the attenuation factor set in the attenuator 255. The comparator 260 compares the levels of the pixel signal VSIG and the reset signal with the amplified ramp signal output from the attenuator 255, i.e., the reference signal Vramp with a changed slope. The comparator 260 in this embodiment is an example of a comparison circuit.

[0135] When the AD conversion gain is low, a large signal can be converted into an AD signal, but the resolution is reduced. As a result, the quantization noise increases. In contrast, when the AD conversion gain is high, the quantization noise can be suppressed. However, the signal range that can be handled becomes smaller.

[0136] According to this embodiment, when the level of the pixel signal is greater than the threshold, AD conversion is performed with a relatively low AD conversion gain, and when the level of the pixel signal is less than the threshold, AD conversion is performed with a relatively high AD conversion gain. As a result, it is possible to perform AD conversion of the pixel signal in the maximum range while suppressing quantization noise and avoiding S / N degradation in low illuminance, thereby improving the dynamic range.

[0137] The imaging device according to this embodiment includes a pixel 10, a determination circuit, a signal generation circuit 204 that generates a ramp signal, an attenuator 255 that amplifies and outputs the ramp signal at one of a plurality of amplification factors determined according to a comparison result of the determination circuit, an AD conversion circuit that converts an analog signal into a digital signal by referring to the output from the attenuator 255, and an output data generation circuit that adds additional information corresponding to the one amplification factor to the digital signal, and generates and outputs output data related to the pixel.

[0138] In this embodiment, the determination circuit compares the level of the pixel signal VSIG with at least one threshold value. During the period in which the AD conversion circuit converts the pixel signal VSIG and the reset signal into digital signals, the attenuator 255 amplifies the ramp signal by one amplification factor determined according to the comparison result of the determination circuit. As in the first embodiment, the output data generation circuit generates output data by adding additional information to the difference between the digital signal corresponding to the pixel signal VSIG and the digital signal corresponding to the reset signal. The data structure of the output data, that is, the image data, is as described in the first embodiment.

[0139] In this embodiment, as in the first embodiment, the pixel signal VSIG and the reset signal are amplified by the same amplification factor, so that errors in the CDS are less likely to occur. Furthermore, it is possible to improve the frame rate of the output data output from an imaging device equipped with a CDS circuit inside.

[0140] The operation of the imaging device 200 according to this embodiment will be described with reference to FIGS.

[0141] Each of Fig. 24 and Fig. 25 is a timing chart showing an example of the operation procedure of the imaging device 200. Fig. 24 shows an example of each signal waveform when the level of the pixel signal VSIG is below the threshold value of the comparator 240. In the explanation of the operation procedure of the imaging device 200, each of the multiple pixels 10 is a stacked photoelectric conversion element. The comparator 240 of the conversion circuit 220d has the configuration shown in Fig. 6A, the attenuator 255 has the configuration shown in Fig. 22B, and the holding circuit 270 has the configuration shown in Fig. 23.

[0142] 23 is a diagram showing a second example of the holding circuit. The holding circuit 270 according to the second example of the configuration includes a switch S4 and a capacitance Cd. When the level of the control signal CNT is High, the switch S4 is turned on and the voltage of the pixel signal VSIG is charged in the capacitance Cd, and when the level of the control signal CNT is Low, the switch S4 is turned off and the voltage of the pixel signal VSIG is held in the capacitance Cd (the input node of the comparator 240). When the second example of the configuration is adopted, it is preferable that the impedance of the rear stage of the holding circuit 270 is large, so the holding circuit 270 is connected to the front stage of the comparator 240. In this example, the holding circuit 270 includes a switch S4 electrically connected between the pixel 10 and the comparator 240.

[0143] First, at time t0, the level of the horizontal synchronization signal HD changes from low to high, starting imaging of the pixels in the nth row of the pixel section 201. At time t1, the level of the horizontal synchronization signal HD changes from high to low.

[0144] Next, at time t2, the selection signal VSELn goes High, the selection transistor M2 turns on, and the pixel signal VSIG of the nth row is output to the vertical signal line 212. In addition, the control signal CNT goes High, and the switch S4 of the holding circuit 270 (see FIG. 23) turns on.

[0145] Next, at time t4, the switch S4 of the holding circuit 270 is turned off, and a voltage based on the level of the pixel signal VSIG is held in the capacitor Cd.

[0146] In this embodiment, since the output signal SHOUT does not exceed the threshold value VTH during the period from time t2 to time t4 when the control signal CNT is High, the output signal DOUT1 is fixed to Low after time t4, and the inverted signal of the output signal DOUT1 (the output signal of the inverter 224) is fixed to High. As a result, the reference signal Vramp is attenuated to Vramp×Rb / (Ra+Rb) by the attenuator 250, and is output from the attenuator 250 as the output signal AOUT. In other words, the reference signal Vramp whose slope is multiplied by Rb / (Ra+Rb) is output.

[0147] In this embodiment, the resistors Ra and Rb are the same. In this case, the attenuation rate of the attenuator 255 is 1 / 2. By applying the attenuation process of the attenuator 255 to the reference signal Vramp according to the level of the pixel signal VSIG, the slope of the reference signal Vramp becomes 1 / 2, and therefore, the quantization noise during AD conversion can be reduced.

[0148] Next, at time t4, the signal generating circuit 204 starts generating the reference signal Vramp. During the period from time t4 to time t5, the comparator 260 compares the voltage corresponding to the attenuated reference signal Vramp with the level of the pixel signal VSIG, and the counter 209 continues counting until the output levels of the two match.

[0149] Next, at time t5, the reset control signal VRSTn applied to the pixels 10 in the nth row goes High, and the reset transistor M3 starts the reset operation of the pixels in the nth row. After that, the potential level of the vertical signal line 212 according to the level of the reset signal does not exceed the threshold VTH of the comparator 240, so the level of the output signal DOUT1 is maintained at Low.

[0150] Next, at time t7, the reset control signal RSTn changes from High to Low, completing the reset operation. Also, at time t7, the signal generating circuit 204 starts generating the reference signal Vramp. During the period from time t7 to time t9, the comparator 260 compares the voltage corresponding to the reference signal Vramp with the reset signal, and the counter 209 continues counting until the output levels of the two match.

[0151] Next, at time t10, the horizontal synchronization signal HD goes high, and the imaging device 200 starts reading out pixels in the (n+1)th row.

[0152] In this way, during the period when the selection signal VSELn is high, a first comparison of the pixel signal VSIG with the reference signal Vramp is performed by the comparator 260, and then, after the reset operation is completed, a second comparison of the reset signal with the reference signal Vramp is performed by the comparator 260.

[0153] 25 shows an example of each signal waveform when the level of the pixel signal VSIG exceeds the threshold of the comparator 240. Below, the differences from the above-mentioned case where the pixel signal VSIG falls below the threshold of the comparator 240 will be described.

[0154] 25, the level of the pixel signal VSIG read out from the pixel 10 is held in the holding circuit 270, and the output signal SHOUT is higher than the threshold VTH of the comparator 240, so that the output signal DOUT1 of the comparator 240 changes from low to high. This turns on the switch S1 of the attenuator 255 and turns off the switch S2. Therefore, the reference signal Vramp is not attenuated by the attenuator 250b, and is output as the output signal AOUT with the slope of the reference signal Vramp unchanged.

[0155] As described above, when the level of the pixel signal VSIG is below the threshold VTH of the comparator 240, the reference signal Vramp is attenuated by the attenuator 255, and when the level of the pixel signal VSIG is above the threshold VTH of the comparator 240, the reference signal Vramp is not attenuated by the attenuator 255. By operating the conversion circuit 220d in accordance with the above-mentioned operation sequence, it is possible to suppress quantization noise and perform AD conversion of the pixel signal in the maximum range of the pixel signal while avoiding S / N degradation at low illuminance, thereby improving the dynamic range.

[0156] According to the pixel configuration and operation sequence of this embodiment, after a pixel signal corresponding to the intensity of incident light is read out, the pixel is reset and a reset signal is read out. In this way, the pixel signal is first read out, and the attenuation rate of the attenuator is determined based on the magnitude relationship between the level of the pixel signal and the threshold value of the comparator, so that the subsequent reset signal can also be AD converted with the slope of the reference signal Vramp. By using the same waveform of the reference signal Vramp in reading out the pixel signal and the reset signal, it is possible to improve the SN without causing unnecessary offsets, etc. On the other hand, when using a pixel configuration and operation sequence that reads out the level of the reset signal first, it is difficult to use the same waveform of the reference signal Vramp in reading out the pixel signal and the reset signal because the level of the pixel signal is unknown at the time when the reset signal is read out.

[0157] Fig. 26 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold VTH, and the AD conversion gain of the imaging device 200 according to this embodiment. In this embodiment, as shown in Fig. 26, the threshold VTH is set to 1 / 2 the saturation signal level of the pixel, and the AD conversion gain is 6 dB. However, by making the AD conversion gain smaller than 6 dB, a greater noise reduction effect can be obtained.

[0158] <Modifications of this embodiment> In the embodiment in which the CDS circuit is externally connected to the imaging device described with reference to FIG. 19, the conversion circuit included in the imaging device can be replaced with a conversion circuit including an attenuator electrically connected to a comparator and a signal generation circuit as shown in FIG. 21. In this modification, during a period in which the AD conversion circuit converts the pixel signal VSIG and the reset signal into digital signals, the attenuator amplifies the ramp signal with one amplification factor determined according to the comparison result of the determination circuit. As in the second embodiment, the output data generation circuit generates output data by adding additional information to a digital signal corresponding to the pixel signal VSIG. On the other hand, the output data generation circuit does not compress the digital signal corresponding to the reset signal, and outputs the digital signal as it is as output data without adding additional information to the digital signal. With this configuration, it is possible to improve the frame rate when the CDS circuit is externally connected to the imaging device.

[0159] <Fourth embodiment> A camera system according to a fourth embodiment of the present disclosure will be described with reference to FIG.

[0160] 27 is a schematic diagram showing a configuration example of a camera system 400 according to a fourth embodiment of the present disclosure. The camera system 400 includes a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing unit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0161] The lens optical system 601 includes a lens group including, for example, an autofocus lens and a zoom lens. The lens optical system 601 may include a diaphragm. The lens optical system 601 focuses light on the imaging surface of the imaging device 200. As the imaging device 602, the imaging devices according to the first to third embodiments described above can be widely used.

[0162] The system controller 603 controls the entire camera system 400. The system controller 603 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0163] The camera signal processing unit 604 has a function of processing an output signal from the imaging device 602. The image processing circuit 800 described above is an example of the camera signal processing unit 604. The camera signal processing unit 604 is, for example, a DSP (Digital Signal Processor). The camera signal processing unit 604 receives output data from the imaging device 602 and performs processes such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance. The imaging device 602 and the camera signal processing unit 604 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, an electronic device including the imaging device 602 as a part thereof can be made smaller.

[0164] The imaging device according to the embodiment of the present disclosure may not include all of the components described in the first to third embodiments, and may be configured with only components for performing a desired operation. In addition, in the above operation examples, there may be some operations that are not performed by the imaging device.

[0165] In the above embodiment, the processing performed by a specific processing unit such as a signal processing circuit may be executed by another processing unit. In addition, the order of multiple processes may be changed, or multiple processes may be executed in parallel.

[0166] The general or specific aspects of the present disclosure may be realized in a system, an apparatus, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or may be realized in any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium.

[0167] For example, the present disclosure may be realized as an imaging device of the above-described embodiments, as a processing circuit for an imaging device having the functions of the signal processing circuit of the above-described embodiments, as a signal processing method for an imaging device performed by the signal processing circuit of the above-described embodiments, as a program for causing a computer to execute such a signal processing method, or as a computer-readable non-transitory recording medium on which such a program is recorded.

[0168] In addition, as long as they do not deviate from the spirit of this disclosure, various modifications that would occur to those skilled in the art to the embodiments and examples, as well as other forms constructed by combining some of the components in the embodiments and examples, are also included in the scope of this disclosure. [Industrial Applicability]

[0169] The imaging device of the present disclosure is useful as various imaging devices, and can also be used in applications such as digital cameras, digital video cameras, camera-equipped mobile phones, medical cameras such as electronic endoscopes, vehicle-mounted cameras, and cameras for robots. [Explanation of symbols]

[0170] 10 pixel, 11 photoelectric conversion layer, 12 pixel electrode, 13 counter electrode, 14 contact plug, 15 semiconductor substrate, 18 photoelectric conversion section, 200, 602 imaging device, 201 pixel section, 202 vertical scanning circuit, 203 horizontal transfer scanning circuit, 204 signal generation circuit, 205 drive control circuit, 206 column processing section, 207 column circuit, 212 vertical signal line, 213 horizontal signal line, 214 amplifier circuit, 21 5···load current circuit, 220···conversion circuit, 240, 260···comparator, 250···attenuator, 270···hold circuit, 290···output data generation circuit, 400···camera system, 601···optical system, 603···system controller, 604···camera signal processing unit, 800···image processing circuit, 810···input I / F, 820, 830···frame memory, 840···decoding processing unit, 850···arithmetic processing unit, 860···image processing unit, 900···display device

Claims

1. Pixels and a determination circuit for comparing a level of an analog signal read from the pixel with at least one threshold; an amplifier circuit that amplifies the analog signal at one of a plurality of amplification factors determined in accordance with a comparison result of the determination circuit, and outputs the amplified signal; an AD conversion circuit for converting an output signal from the amplifier circuit into a digital signal; an output data generating circuit that generates output data related to the pixel by adding additional information corresponding to the one amplification factor to the digital signal; An imaging device comprising:

2. Pixels and a determination circuit for comparing a level of an analog signal read from the pixel with at least one threshold; a signal generating circuit for generating a ramp signal; an amplifier circuit that amplifies the ramp signal by one of a plurality of amplification factors that is determined in response to a comparison result of the determination circuit, and outputs the amplified ramp signal; an AD conversion circuit that converts the analog signal into a digital signal by referring to an output from the amplifier circuit; an output data generating circuit that generates output data related to the pixel by adding additional information corresponding to the one amplification factor to the digital signal; An imaging device comprising:

3. 3. The imaging device according to claim 1, wherein the output data includes a plurality of data bits representing the digital signal and at least one flag bit representing the additional information.

4. The imaging device of claim 3 , wherein the at least one flag bit includes two or more bits.

5. The imaging device according to claim 1 , wherein the one amplification factor is smaller than ½ or larger than 2.

6. the analog signal includes a pixel signal representing an image of a subject and a reset signal indicating a reset level; the determination circuit compares a level of the pixel signal with the at least one threshold value; the amplifier circuit amplifies the pixel signal and the reset signal by the one amplification factor determined in response to a comparison result of the determination circuit; The imaging device according to claim 1 , wherein the output data generation circuit generates the output data by adding the additional information to a difference between a digital signal corresponding to the pixel signal and a digital signal corresponding to the reset signal.

7. the analog signal includes a pixel signal representing an image of a subject and a reset signal indicating a reset level; the determination circuit compares a level of the pixel signal with the at least one threshold value; during a period in which the AD conversion circuit converts the pixel signal and the reset signal into a digital signal, the amplifier circuit amplifies the ramp signal by the one amplification factor determined in response to a comparison result of the determination circuit; The imaging device according to claim 2 , wherein the output data generation circuit generates the output data by adding the additional information to a difference between a digital signal corresponding to the pixel signal and a digital signal corresponding to the reset signal.

8. the analog signal includes a pixel signal representing an image of a subject and a reset signal indicating a reset level; the determination circuit compares a level of the pixel signal with the at least one threshold value; the amplifier circuit amplifies the pixel signal by the one amplification factor determined in response to a comparison result of the determination circuit; The imaging device according to claim 1 , wherein the output data generating circuit generates the output data by adding the additional information to the digital signal corresponding to the pixel signal.

9. the analog signal includes a pixel signal representing an image of a subject and a reset signal indicating a reset level; the determination circuit compares a level of the pixel signal with the at least one threshold value; during a period in which the AD conversion circuit converts the pixel signal and the reset signal into a digital signal, the amplifier circuit amplifies the ramp signal by the one amplification factor determined in response to a comparison result of the determination circuit; The imaging device according to claim 2 , wherein the output data generating circuit generates the output data by adding the additional information to the digital signal corresponding to the pixel signal.

10. the additional information includes compression information of the digital signal; 3. The imaging device according to claim 1, wherein a bit width of the output data is smaller than a bit width of data obtained when the output data is restored based on the additional information.

11. A data structure of image data transferred from an imaging device having a plurality of pixels to an image processing circuit, the image data includes pixel data associated with pixel signals read out from each of the plurality of pixels; the pixel data includes a plurality of data bits indicating a level of the pixel signal and at least one flag bit that encodes compression information of the pixel signal; The image processing circuit includes: Decoding the at least one flag bit to obtain the compressed information; A data structure for decoding the pixel signal based on the compression information to generate decoded image data, and performing image processing using the decoded image data.

Images