Information processor and control method

Abstract

To provide an information processor that easily updates data in a memory using external communication.SOLUTION: An information processor includes: a memory that stores a program for executing system processing; a first processor that executes system processing on the basis of the program stored in the memory; a second processor that is connected to the memory and controls start and stop operations of the first processor; a connection unit for external communication; and a switching unit that switches a connection destination of the external communication via the connection unit between the first processor and the second processor. The second processor controls the switching unit so that, when operation of the first processor is stopped, the second processor becomes the connection destination of the external communication via the connection unit, and executes a write process to write a part or all of the program acquired via the external communication through the connection unit into the memory.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an information processing device and a control method. [Background technology]

[0002] An information processing device such as a PC (Personal Computer) has a non-volatile memory (e.g., a flash ROM (Read Only Memory)) stored therein that executes a program for executing a system such as a BIOS (Basic Input Output System). The PC starts up the system and executes various processes by executing this program (e.g., Patent Document 1).

[0003] If the program data written in this memory becomes corrupted, or if an incorrect program is written to the memory, the system will not be able to start up properly. Conventional methods for recovering data in memory include clamping the memory's terminals (leads) with a special clip and rewriting the data with a ROM writer, or replacing the memory itself. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-10492 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in modern PCs, electrode pads are now being used instead of leads as memory terminals, so the method using a ROM writer cannot actually be used, and the only way to repair the program is to replace the memory itself. Replacing the memory raises concerns that it may damage the circuit board and that replacing parts will be expensive.

[0006] The present invention has been made in consideration of the above circumstances, and has as its object to provide an information processing device and a control method that can easily update data in a memory using external communication. [Means for solving the problem]

[0007] The present invention has been made to solve the above-mentioned problems, and an information processing device according to a first aspect of the present invention comprises a memory for storing a program for executing system processing, a first processor for executing system processing based on the program stored in the memory, a second processor connected to the memory and controlling the start and stop of operation of the first processor, a connection unit for external communication, and a switching unit for switching the connection destination of external communication via the connection unit to the first processor or the second processor, wherein when operation of the first processor is stopped, the second processor controls the switching unit so that the connection destination of external communication via the connection unit becomes the second processor, and executes a write process for writing part or all of the program acquired by external communication via the connection unit to the memory.

[0008] In the above information processing device, the second processor may control the switching unit such that, when the first processor is operating, a connection destination for external communication via the connection unit becomes the first processor.

[0009] In the above information processing device, the second processor may cause the operation of the first processor to continue to be stopped while the write process is being performed, even if a trigger to start operation of the first processor is received.

[0010] In the above-mentioned information processing device, when operation of the first processor is stopped, the second processor may control each unit within the second processor to a low power mode, and may enable a return function for returning an external communication unit among the units from the low power mode, and may return the external communication unit from the low power mode in response to receiving an external communication via the connection unit.

[0011] In the above information processing device, the second processor may start the write process after returning the external communication unit from a low power mode, and when the write process is completed, return the external communication unit to the low power mode.

[0012] In the above information processing device, when the second processor starts operation of the first processor after the write process is completed, the second processor may disable the return function and return each of the units from the low power mode.

[0013] In addition, according to a second aspect of the present invention, a control method in an information processing device having a memory storing a program for executing system processing, a first processor that executes system processing based on the program stored in the memory, a second processor connected to the memory and controlling the start and stop of operation of the first processor, a connection unit for external communication, and a switching unit that switches the connection destination of external communication via the connection unit between the first processor and the second processor includes the steps of: when operation of the first processor is stopped, the second processor controls the switching unit so that the connection destination of external communication via the connection unit becomes the second processor; and, after controlling the switching unit, executing a write process to write part or all of the program acquired by external communication via the connection unit into the memory. Effect of the Invention

[0014] According to the above aspects of the present invention, data in memory can be easily updated using external communications. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is an explanatory diagram of an overview of an information processing apparatus according to an embodiment. [Diagram 2] 6 is a flowchart showing an example of a procedure for writing to a ROM according to the embodiment. [Diagram 3]FIG. 1 is a block diagram showing an example of a hardware configuration of an information processing apparatus according to an embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of a configuration for performing ROM writing processing of the information processing device according to the embodiment. [Diagram 5] 11 is a flowchart showing an example of a ROM write process according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1 is an explanatory diagram of an overview of an information processing device according to this embodiment. The illustrated information processing device 1 is a clamshell-type notebook PC (Personal Computer). The information processing device 1 includes an internal non-volatile memory (e.g., a flash ROM (Read Only Memory)) that stores programs for executing a system such as a BIOS (Basic Input Output System). This non-volatile memory will be referred to as "ROM" below.

[0017] If the data of a program such as a BIOS (Basic Input Output System) stored in the ROM is corrupted, or if an incorrect program is written to the memory, the system will not be able to start up normally. In this embodiment, the data in the ROM is restored by a communication connection from another information processing device.

[0018] 1 is a target PC that needs to repair data in its ROM. Meanwhile, information processing device 1B is a host PC that writes data to the ROM of information processing device 1A to repair it. By communicatively connecting information processing device 1A and information processing device 1B via cable 5, information processing device 1A can access the ROM of information processing device 1B and write data thereto.

[0019] For example, the cable 5 is a Universal Serial Bus (USB) cable (for example, a USB 2.0 cable). By connecting the USB Type-C connectors of the information processing device 1A and the information processing device 1B using the cable 5, the host-side information processing device 1B accesses the ROM of the target-side information processing device 1A.

[0020] Here, the target information processing device 1A needs to establish a communication connection with the host information processing device 1B even when the system cannot be started normally. Therefore, in the information processing device 1A, the EC (Embedded Controller) enables the communication function and performs a write process to the ROM while the power is off (CPU is off). The system configuration of the CPU, EC, etc. will be described later.

[0021] Next, a procedure that a user follows when writing data from information processing device 1B to the ROM of information processing device 1A will be described with reference to FIG. 2 is a flowchart showing an example of a procedure for writing data to a ROM according to the present embodiment. First, the user turns off the power of the information processing device 1A. At this time, it is assumed that an AC power source (AC power adapter) is inserted into the information processing device 1A and power is being supplied thereto (step S11).

[0022] Next, the user connects the target side information processing device 1A and the host side information processing device 1B with a cable 5 (step S13). Then, the user starts a dedicated application (hereinafter, referred to as a "dedicated application") on the host side information processing device 1B (step S15). This dedicated application has a function of writing data to the ROM of the target side information processing device 1A.

[0023] The user selects data to be written to the ROM of the information processing device 1A using a dedicated application started on the information processing device 1B. For example, the user selects BIOS program data to be written to the ROM of the information processing device 1A from the data stored in the information processing device 1B using the dedicated application. The information processing device 1B transmits the data selected by the user to the information processing device 1A via communication connected by cable 5, and starts writing the data to the ROM of the information processing device 1A.

[0024] The configuration of the information processing device 1 will be described in detail below. Note that here, an example of the configuration of the information processing device 1 having the function of the target side information processing device 1A will be described. Note that the configuration of the host side information processing device 1B may be the same as the configuration of the target side information processing device 1A, or may be the configuration of a general PC that does not have the target side functions (part of the configuration).

[0025] [Hardware configuration of information processing device] 3 is a block diagram showing an example of a main hardware configuration of an information processing device according to this embodiment, in which the same reference numerals are used to designate components corresponding to those in FIG.

[0026] As shown in FIG. 3, the information processing device 1 includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a storage 15, an audio system 16, a communication unit 17, a USB connector 18, a switching unit 21, an EC (Embedded Controller) 31, a ROM 32, a keyboard 33, a power button 34, a power circuit 35, and a battery 36.

[0027] The CPU 11 is an example of a processor (first processor) that executes programs of a BIOS and an OS (Operating System). The CPU 11 executes various arithmetic processes under program control, and controls the information processing device 1 as a whole.

[0028] The CPU 11 is connected to a plurality of devices using a USB, a serial ATA (AT Attachment), a Serial Peripheral Interface (SPI) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express bus, an eSPI bus, etc. In the example shown in Fig. 3, as examples of devices, a main memory 12, a video subsystem 13, a storage 15, an audio system 16, a communication unit 17, a USB connector 18 via a switching unit 21, etc. are connected to the CPU 11.

[0029] For example, the CPU 11 reads a BIOS program stored in the ROM 32 via the EC 31, develops it in the main memory 12, and executes BIOS processing (such as POST processing) based on the program. The CPU 11 also reads an OS, various drivers, various services / utilities, application programs, etc. from the storage 15 into the main memory 12 and executes the respective processes. The CPU 11 also controls the video subsystem 13 and the audio system 16, and processes USB communication with external devices and equipment via the USB connector 18.

[0030] The CPU 11 may be configured in combination with a chipset that handles interfacing and processing with multiple devices connected via a bus, etc. The CPU 11 may also be configured as a SoC (System on a Chip) together with the chipset and peripheral devices.

[0031] The main memory 12 is a writable memory used as a read area for the programs executed by the CPU 11 or as a work area for writing processing data for the programs executed. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. The programs executed by the CPU 11 include the BIOS, the OS, various drivers for operating the hardware of peripheral devices, various services / utilities, application programs, etc.

[0032] Video subsystem 13 is a subsystem for implementing functions related to image display, and includes a video controller. This video controller processes drawing commands from CPU 11, writes the processed drawing information to a video memory, and also reads the drawing information from the video memory and outputs it to display unit 14 as drawing data (display data).

[0033] The display unit 14 includes, for example, a liquid crystal display, an organic EL display, etc. The display unit 14 displays a display screen based on drawing data (display data) output from the video subsystem 13.

[0034] The storage 15 includes a non-volatile storage device such as a hard disk drive (HDD) or a solid state drive (SSD), etc. For example, the storage 15 stores an OS, various drivers, various services / utilities, application programs, various data, and the like.

[0035] The audio system 16 records, plays back, and outputs audio data. The communication unit 17 connects to a communication network via a wireless LAN (Local Area Network) or a wired LAN, and performs data communication.

[0036] The USB connector 18 is an example of a connection section for external communication for communicating with an external device or equipment using USB. For example, the USB connector 18 is a connector compatible with USB Type-C. By connecting one end of a cable 5 for USB 2.0 (see FIG. 1) to the USB connector 18, external communication with an external device or equipment to which the other end of the cable 5 is connected is possible. The USB connector 18 may include multiple connectors so that it can be connected to multiple external devices or equipment.

[0037] The switching unit 21 is provided to use an existing built-in port for external communication, for example, to use an existing USB signal for UART (Universal Asynchronous Receiver / Transmitter) communication. The switching unit 21 switches the connection destination of the external communication via the USB connector 18 to either the CPU 11 (USB communication side) or the EC 31 (UART communication side). For example, the switching unit 21 switches the connection destination of the USB connector 18 to either the main CPU 11 or the EC 31 under the control of the EC 31.

[0038] The EC31 (an example of a second processor) is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the operating state of the system of the information processing device 1. The EC31 is composed of a CPU and memory (ROM, RAM, etc.) not shown, and also includes various buses, A / D input terminals for multiple channels, D / A output terminals, a timer, and digital input / output terminals. The EC31 is connected to, for example, the CPU11, the switching unit 21, the ROM32, the keyboard 33, the power button 34, and the power circuit 35, and controls the operations of these. For example, the EC31 controls the start and stop of the operation of the CPU11.

[0039] The ROM 32 is, for example, an electrically rewritable non-volatile memory such as an SPI flash memory. The ROM 32 stores system firmware such as a BIOS program and a program for controlling the EC 31. The ROM 32 may be an EEPROM (Electrically Erasable Programmable Read Only Memory).

[0040] The keyboard 33 is, for example, a physical keyboard. When the user operates (types), the keyboard 33 transmits an operation signal indicating the operated key to the EC 31. Based on the operation signal transmitted from the keyboard 33, the EC 31 executes a process corresponding to the key operated by the user.

[0041] The power button 34 is an operator that allows the user to instruct power on or power off. When the power button 34 is operated by the user, it transmits an operation signal to the EC 31 in response to the operation.

[0042] The power supply circuit 35 includes, for example, a DC / DC converter, a charge / discharge unit, a battery unit, an AC / DC adapter, and the like, and converts a DC voltage supplied from an AC adapter (AC / DC adapter) or a battery 36 (battery unit) into a plurality of voltages required to operate the information processing device 1. The power supply circuit 35 also controls the supply of power to each part of the information processing device 1 based on the power-on or power-off control from the EC 31.

[0043] [Explanation of the configuration for performing ROM writing via external communication] Next, a detailed description will be given of a configuration for performing a ROM write process for writing data into the ROM 32 of the information processing device 1 through external communication.

[0044] Fig. 4 is a block diagram showing an example of a configuration for performing ROM write processing in the information processing device according to this embodiment. The configuration shown in Fig. 4 is a configuration required in the target side information processing device 1A shown in Fig. 1. In this figure, the same reference numerals are used to designate components corresponding to those in Fig. 3.

[0045] (External communication switching control) First, the switching control of external communication by the switching unit 21 will be described. As described above, the switching unit 21 is provided to use an existing built-in port for external communication, for example, to use an existing USB signal for UART (Universal Asynchronous Receiver / Transmitter) communication. In the example shown in FIG. 4, the switching unit 21 is provided in the middle of the path of USB communication between the CPU 11 and the USB connector 18. When performing ROM write processing, the switching unit 21 cuts off the connection between the CPU 11 and the USB connector 18 and connects the EC 31 to the USB connector 18. For example, the EC 31 uses a UART (Universal Asynchronous Receiver / Transmitter) to communicate with an external device or equipment connected via the USB connector 18. By making the USB D+ / D- signal lines correspond to the UART TX / RX signal lines, the EC 31 uses the USB communication path as a data communication (UART communication) path during ROM write processing to communicate with the external device or equipment connected via the USB connector 18.

[0046] That is, when the connection destination of the USB connector 18 is the CPU 11, the CPU 11 performs USB communication with the external device connected via the USB connector 18. On the other hand, when the connection destination of the USB connector 18 is switched to the EC 31 in order to perform ROM write processing, the EC 31 uses UART to communicate with the external device connected via the USB connector 18. Here, the external device connected via the USB connector 18 when performing ROM write processing will be described as the host-side information processing device 1B shown in FIG.

[0047] 3, the switching unit 21 switches the connection destination of the external communication via the USB connector 18 to either the CPU 11 or the EC 31. The switching of the external communication by the switching unit 21 is controlled by the EC 31.

[0048] The EC 31 outputs a switching control signal to the switching unit 21, which controls switching of the external communication by the switching unit 21. For example, by setting the switching control signal to "Low", the switching unit 21 switches the connection destination of the external communication to the EC 31. By setting the switching control signal to "High", the switching unit 21 switches the connection destination of the external communication to the CPU 11.

[0049] When the operation of the CPU 11 is stopped (CPU off), the EC 31 sets the switching control signal to "Low" to control the switching unit 21 so that the connection destination of external communication via the USB connector 18 is EC 31. That is, when the operation of the CPU 11 is stopped (CPU off), the EC 31 opens communication of UART signals in the switching unit 21. Here, when the operation of the CPU 11 is stopped (CPU off) refers to, for example, before the power button 34 is pressed, or when the system is shut down from an operating state. Note that the condition when the operation of the CPU 11 is stopped (CPU off) may include the connection of an AC adapter.

[0050] Furthermore, when the CPU 11 is operating (CPU on), the EC 31 sets the switching control signal to "High" to control the switching unit 21 so that the connection destination of external communication via the USB connector 18 is the CPU 11. That is, when the CPU 11 is operating (CPU on), the EC 31 opens communication of USB signals in the switching unit 21. Here, when the CPU 11 is operating (CPU on), it refers to, for example, the state after the power button 34 is pressed.

[0051] In this way, EC31 opens UART signal communication in switching unit 21 only when CPU 11 is stopped (CPU off), so that CPU 11 and EC31 do not access each other at the same time, and UART communication can be performed using USB signals.

[0052] (Control of writing data to ROM) Next, a description will be given of the control of writing data to the ROM 32. The EC 31 starts a writing process when the operation of the CPU 11 is stopped (when the CPU is off). The EC 31 acquires data (for example, BIOS program data) transmitted by external communication from the host-side information processing device 1B connected via the USB connector 18, and executes a ROM writing process for writing a part or all of the acquired program to the ROM 32.

[0053] Here, since it is necessary to prevent a collision occurring when EC 31 and CPU 11 access ROM 32 at the same time, EC 31 restricts the operation of CPU 11 while ROM write processing is being executed. In the example shown in FIG. 4, a start control signal is output from EC 31 to CPU 11. The start control signal is a control signal that controls the start of CPU 11. For example, by setting the start control signal to "Low", a start restriction is set so that CPU 11 is not started. Also, by setting the start control signal to "High", the start restriction is released so that CPU 11 is operable.

[0054] When starting the ROM write process, the EC31 sets the start restriction by setting the start control signal to "Low," and when the ROM write process ends, the start restriction is released by setting the start control signal to "High." As a result, even if the EC31 receives a trigger (e.g., pressing the power button 34) to start the operation of the CPU 11 (turn the CPU on) while the ROM write process is being executed, the operation of the CPU 11 can continue to be stopped, so that no collision occurs when the EC31 and the CPU 11 access the ROM 32 at the same time, and the ROM write process can be executed normally.

[0055] (Power control for EC's UART communication unit) Next, power control in the EC 31 will be described. When the operation of the CPU 11 is stopped (CPU off), the EC 31 controls the EC 31 itself (core portion) and each section (each functional unit) in the EC 31 to be in a low power mode, so that in order to perform communication using the UART, it is necessary to control the power supply of the UART communication section 311 that performs UART communication and the EC 31 itself. For example, the EC 31 performs power supply control using a wake-up function of a GPIO (General Purpose Input / Output). The GPIO wake-up function has a return function that can detect a voltage change in a signal line connected to the EC 31 even when the EC 31 is in a low power mode, and can return the EC 31 from the low power mode, and can generate an interrupt process.

[0056] Specifically, when the operation of the CPU 11 is stopped (CPU off), the EC 31 enables the GPIO wake-up function, which is a return function, in order to return the UART communication unit 311, which is one of the units controlled to be in the low power mode, from the low power mode. Then, the EC 31 detects, by the GPIO, that an external communication has been received via the USB connector 18 (a voltage change on the signal line), and generates an interrupt process by the GPIO wake-up function to return the UART communication unit 311 from the low power mode.

[0057] After returning the UART communication unit 311 from the low power mode, the EC 31 starts writing data to the ROM 32 based on the command and data acquired from the host-side information processing device 1B through external communication. Then, when the EC 31 finishes writing data to the ROM 32, it returns the UART communication unit 311 to the low power mode.

[0058] On the other hand, when the CPU 11 is operating (CPU on), the EC 31 disables (Disables) the GPIO wake-up function, which is a return function for returning the UART communication unit 311 from the low power mode. For example, when the EC 31 starts the operation of the CPU 11 after the ROM write process ends, the EC 31 disables (Disables) the GPIO wake-up function, which is a return function for returning the UART communication unit 311 from the low power mode. In addition, the EC 31 causes each unit in the EC 31 to return from the low power mode.

[0059] [ROM writing process via external communication] Next, the operation of the ROM writing process via external communication will be described. 5 is a flowchart showing an example of a ROM write process according to the present embodiment. This process is started when the information processing device 1A is powered off.

[0060] (Step S101) The EC 31 controls the CPU 11 to a stopped state (CPU off), and proceeds to the process of step S103.

[0061] (Step S103) The EC 31 enables a return function (GPIO wake-up function) for returning the UART communication unit 311 from the low power mode among the units controlled to the low power mode, and then proceeds to the process of step S105.

[0062] (Step S105) EC31 controls the switching unit 21 by setting the switching control signal to "Low" so that the connection destination of external communication (USB connector 18) is changed from the CPU 11 to EC31. In response to this control by EC31, the switching unit 21 switches the connection destination of external communication (USB connector 18) from the CPU 11 to EC31.

[0063] (Step S107) The EC 31 controls each unit in the EC 31 to a low power mode and waits for an interrupt process by the GPIO wakeup function.

[0064] (Step S109) When the EC 31 receives the interrupt, it determines whether or not it has received external communication via the USB connector 18. If it determines that it has received external communication (YES), it proceeds to processing of step S111. On the other hand, if it determines that it has not received external communication (NO), it proceeds to processing of step S121.

[0065] (Step S111) The EC 31 causes the UART communication unit 311 to return from the low power mode, and proceeds to the process of step S113.

[0066] (Step S113) The EC 31 sets the start control signal to "Low" to restrict the start-up of the CPU 11, and proceeds to the process of step S115.

[0067] (Step S115) The EC 31 uses external communication to write data to the ROM 32. For example, the EC 31 starts writing data to the ROM 32 based on a command and data acquired from the host-side information processing device 1B through external communication. When the EC 31 finishes writing data to the ROM 32, the process proceeds to step S117.

[0068] (Step S117) The EC 31 sets the start control signal to "High" to release the start restriction so that the CPU 11 becomes operable, and proceeds to the process of step S119.

[0069] (Step S119) The EC 31 returns the UART communication unit 311 to the low power mode, and returns to waiting for an interrupt.

[0070] (Step S121) EC31 determines whether or not there is a trigger (e.g., pressing of the power button 34) to start the operation of the CPU 11 (CPU on). If EC31 determines that there is no trigger to start the operation of the CPU 11 (CPU on) (NO), it returns to waiting for an interrupt. On the other hand, if EC31 determines that there is a trigger to start the operation of the CPU 11 (CPU on) (YES), it proceeds to the process of step S123.

[0071] (Step S123) The EC 31 disables the return function (GPIO wake-up function) for returning the UART communication unit 311 from the low power mode, and proceeds to the process of step S125.

[0072] (Step S125) The EC 31 restores each unit in the EC 31 from the low power mode, and proceeds to the process of step S127.

[0073] (Step S127) The EC 31 starts the operation (CPU ON) of the CPU 11. If the program data in the RON 32 is normal or has been restored, the system starts up normally.

[0074] As described above, the information processing device 1 according to the present embodiment includes the ROM 32 (an example of a memory), the CPU 11 (an example of a first processor), the EC 31 (an example of a second processor), the USB connector 18 for external communication (an example of a connection unit), and the switching unit 21. The ROM 32 stores a program for executing a system (e.g., BIOS) process. The CPU 11 executes a system process (e.g., BIOS process) based on the program stored in the ROM 32. The EC 31 is connected to the ROM 32 and controls the start and stop of the operation of the CPU 11. The switching unit 21 switches the connection destination of the external communication via the USB connector 18 between the CPU 11 and the EC 31. Then, when the operation of the CPU 11 is stopped, the EC 31 controls the switching unit 21 so that the connection destination of the external communication via the USB connector 18 becomes the EC 31, and executes a ROM write process for writing a part or all of the program acquired by the external communication via the USB connector 18 to the ROM 32.

[0075] This allows the information processing device 1 to easily update the data of the ROM 32 from another information processing device using external communication. For example, even if the system cannot be started normally due to the data of a program written in the ROM 32 being corrupted or an incorrect program being written in the ROM 32, the information processing device 1 can restore the data of the ROM 32 from another information processing device using external communication in a power-off (CPU-off) state in which the operation of the CPU 11 is stopped. Furthermore, even if the method using a ROM writer cannot be used because the information processing device 1 uses electrode pads for its terminals, there is no need to peel off and replace the ROM 32 mounted on the circuit board, so there is no concern that the circuit board will be damaged or that the cost of replacing parts will be high.

[0076] Furthermore, the EC 31 controls the switching unit 21 so that the connection destination for external communication via the USB connector 18 becomes the CPU 11 when the CPU 11 is operating (when the CPU is on).

[0077] This allows the information processing device 1 to perform USB communication with external devices and equipment when the CPU is on.

[0078] Furthermore, during the execution of the ROM write process, even if a trigger for starting the operation of the CPU 11 is received, the EC 31 causes the operation of the CPU 11 to continue in a stopped state (CPU off state).

[0079] This allows the information processing device 1 to use an existing built-in port for external communication of EC31 when EC31 is writing data transmitted by external communication to ROM32, thereby preventing a collision between access to ROM32 from EC31 and access to ROM32 from CPU 11.

[0080] Furthermore, when the operation of the CPU 11 is stopped (CPU off), the EC 31 controls each unit in the EC 31 to a low power mode, and sets a return function for returning the UART communication unit 311 (one example of an external communication unit) from the low power mode to Enable. Furthermore, the EC 31 returns the UART communication unit 311 from the low power mode in response to receiving an external communication via the USB connector 18.

[0081] As a result, when the information processing device 1 is in a power-off (CPU-off) state, the EC 31 is in low-power mode to reduce power consumption, but when an external communication is received, the UART communication unit 311 is returned from the low-power mode, making it possible to obtain communication data via external communication even in a power-off (CPU-off) state.

[0082] Furthermore, the EC 31 starts the ROM write process after returning the UART communication unit 311 from the low power mode, and when the ROM write process ends, returns the UART communication unit 311 to the low power mode.

[0083] As a result, the information processing device 1 causes the UART communication unit 311 to return from the low power mode only during the execution of the ROM write process, making it possible to suppress an increase in power consumption due to the ROM write process.

[0084] In addition, when EC31 starts operation of CPU 11 after the ROM write process is completed, it disables the return function for returning UART communication unit 311 (an example of an external communication unit) from low power mode, and causes each unit within EC31 to return from low power mode.

[0085] As a result, after the information processing device 1 has restored the data in the ROM 32 by the ROM write process, it can return the return function that was set to enabled (Enable) to disabled when the CPU 11 starts operating (CPU on) and return each unit in the EC 31 from the low power mode. That is, after the information processing device 1 has restored the data in the ROM 32 by the ROM write process, it can return the contents that were controlled when the power was off (CPU off) to the original state when the CPU 11 starts operating (CPU on).

[0086] In addition, in this embodiment, a control method in an information processing device 1 including a ROM 32 (an example of a memory) that stores a program for executing system (e.g., BIOS) processing, a CPU 11 (an example of a first processor) that executes system processing (e.g., BIOS processing) based on the program stored in the ROM 32, an EC 31 (an example of a second processor) that is connected to the ROM 32 and controls the start and stop of operation of the CPU 11, a USB connector 18 (an example of a connection unit) for external communication, and a switching unit 21 that switches the connection destination of external communication via the USB connector 18 to the CPU 11 or EC 31 includes a step in which the EC 31 controls the switching unit 21 when the operation of the CPU 11 is stopped so that the connection destination of external communication via the USB connector 18 is EC 31, and a step in which, after controlling the switching unit 21, a ROM write process is executed to write a part or all of the program acquired by external communication via the USB connector 18 to the ROM 32.

[0087] As a result, the control method in the information processing device 1 can easily update the data of the ROM 32 from another information processing device using external communication. For example, even if the system cannot be started normally because the data of the program written in the ROM 32 is corrupted or an incorrect program is written in the ROM 32, the control method in the information processing device 1 can restore the data of the ROM 32 from another information processing device using external communication in a power-off (CPU-off) state in which the operation of the CPU 11 is stopped. Furthermore, even if the method using a ROM writer cannot be used because the information processing device 1 uses electrode pads for the terminals, there is no need to peel off and replace the ROM 32 mounted on the circuit board, so there is no concern that the circuit board will be damaged or that the cost of replacing parts will be high.

[0088] Although each embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to the above-mentioned embodiment, and the present invention also includes designs within the scope of the gist of the present invention. For example, the configurations described in the above-mentioned embodiments can be arbitrarily combined.

[0089] In the above embodiment, the USB connector 18 corresponding to the USB Type-C of the target side information processing device 1A and the host side information processing device 1B is connected by the cable 5, but the present invention is not limited to this. For example, the USB connector 18 may be a USB connector corresponding to a standard other than USB Type-C (for example, USB Type-A, etc.). In addition, instead of the USB connector 18, a connector corresponding to a communication standard other than USB, such as HDMI (registered trademark), may be used. In addition, the cable 5 may be any cable that is compatible with the specifications of the connectors of the target side information processing device 1A and the host side information processing device 1B. In other words, any communication standard may be applied to the communication connection between the target side information processing device 1A and the host side information processing device 1B.

[0090] In the above embodiment, when the EC 31 and the USB connector 18 are connected via the switching unit 21 during the ROM write process, the EC 31 performs communication using UART, but this is not limiting. For example, the EC 31 may use any communication function that the EC 31 has, and when the EC 31 has a USB communication function, the EC 31 may perform USB communication with the host-side information processing device 1B connected via the USB connector 18.

[0091] The information processing device 1 described above has a computer system inside. A program for implementing the functions of each component of the information processing device 1 described above may be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read into a computer system and executed to perform processing in each component of the information processing device 1 described above. Here, "reading a program recorded on a recording medium into a computer system and executing it" includes installing the program into a computer system. The "computer system" here includes hardware such as an OS and peripheral devices. The "computer system" may also include multiple computer devices connected via a network including a communication line such as the Internet, a WAN, a LAN, or a dedicated line. The "computer-readable recording medium" refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM, or a CD-ROM, and a storage device such as a hard disk built into a computer system. In this way, the recording medium storing the program may be a non-transient recording medium such as a CD-ROM.

[0092] The recording medium also includes a recording medium installed inside or outside and accessible from a distribution server to distribute the program. The program may be divided into a plurality of parts, downloaded at different times, and then combined by each component of the information processing device 1, or each divided program may be distributed by a different distribution server. Furthermore, the "computer-readable recording medium" includes a recording medium that holds a program for a certain period of time, such as a volatile memory (RAM) in a computer system that becomes a server or a client when a program is transmitted via a network. The program may be a recording medium for implementing part of the above-mentioned functions. Furthermore, the program may be a so-called difference file (difference program) that can realize the above-mentioned functions in combination with a program already recorded in the computer system.

[0093] In addition, some or all of the functions of the information processing device 1 in the above-mentioned embodiment may be realized as an integrated circuit such as an LSI (Large Scale Integration). Each function may be individually processed, or some or all of the functions may be integrated into a processor. The integrated circuit method is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. In addition, when an integrated circuit technology that replaces LSI appears due to the progress of semiconductor technology, an integrated circuit based on that technology may be used.

[0094] Moreover, the information processing device 1 of the above embodiment is not limited to a notebook PC, but may be a desktop PC, a tablet PC, etc. Moreover, the information processing device 1 is not limited to a PC (Personal Computer), but may be a game device, a multimedia terminal, a smartphone, etc. [Explanation of symbols]

[0095] 1 Information processing device, 11 CPU, 12 main memory, 13 video subsystem, 14 display unit, 15 storage, 16 audio system, 17 communication unit, 18 USB connector, 21 switching unit, 31 EC, 32 ROM, 33 keyboard, 34 power button, 35 power circuit, 36 battery, 311 UART communication unit

Claims

1. A memory for storing a program for executing the processing of the system; a first processor that executes system processing based on a program stored in the memory; a second processor connected to the memory and controlling starting and stopping of the operation of the first processor; A connection for external communication; a switching unit that switches a connection destination of external communication via the connection unit to the first processor or the second processor; Equipped with The second processor, controlling the switching unit so that a connection destination of external communication via the connection unit is the second processor when the operation of the first processor is stopped, and executing a write process for writing a part or all of a program acquired through the external communication via the connection unit into the memory; Information processing device.

2. The second processor, controlling the switching unit so that, when the first processor is operating, a connection destination of external communication via the connection unit becomes the first processor; The information processing device according to claim 1 .

3. The second processor, During the execution of the write process, even if a trigger for starting the operation of the first processor is received, the operation of the first processor is continued in a stopped state. The information processing device according to claim 1 .

4. The second processor, When the operation of the first processor is stopped, each unit in the second processor is controlled to a low power mode, and a return function for returning an external communication unit among the units from the low power mode is enabled, and the external communication unit is returned from the low power mode in response to receiving an external communication via the connection unit. The information processing device according to claim 1 .

5. The second processor, starting the write process after returning the external communication unit from the low power mode, and returning the external communication unit to the low power mode when the write process is completed; The information processing device according to claim 4.

6. The second processor, when the operation of the first processor is started after the writing process is completed, the return function is set to be invalid and each of the units is returned from the low power mode. The information processing device according to claim 5 .

7. A control method for an information processing device including a memory that stores a program for executing a system process, a first processor that executes the system process based on the program stored in the memory, a second processor that is connected to the memory and controls starting and stopping of an operation of the first processor, a connection unit for external communication, and a switching unit that switches a connection destination of the external communication via the connection unit between the first processor and the second processor, comprising: The second processor: controlling the switching unit so that a connection destination of external communication via the connection unit is the second processor when the operation of the first processor is stopped; executing a write process of writing a part or all of a program acquired by external communication via the connection unit into the memory after controlling the switching unit; A control method comprising:

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