Multilayer image sensor and manufacturing method for the same

Abstract

To provide a multilayer image sensor to secure a conversion gain, and a manufacturing method for the same.SOLUTION: A first pixel array 10a of an image sensor includes: a first semiconductor chip including a first photoelectric conversion layer, a first floating diffusion region 12a_1, a first transfer transistor electrically connecting the first photoelectric conversion layer and the first floating diffusion region, a second photoelectric conversion layer, a second floating diffusion region 12a_2, a second transfer transistor electrically connecting the second photoelectric conversion layer and the second floating diffusion region; and a second semiconductor chip including at least one transistor and outputting a pixel signal. The first semiconductor chip includes a first contact 13a_1 extending in a Z-axis direction, a second contact 13a_2 extending in the Z-axis direction, and a plurality of third contacts 13a_3.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] The present invention relates to a stacked image sensor and a manufacturing method thereof. [Background technology]

[0002] An image sensor is a device that converts an optical image into an electrical signal, and may be used in cameras of portable electronic devices such as smartphones or tablets. In order to reduce the size of the portable electronic devices and improve the performance of the cameras, stacked image sensors have been developed. The stacked image sensor can achieve a reduction in the area of ​​the image sensor, an improvement in the resolution of the image sensor, and an improvement in the signal processing speed of the image sensor. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide an image sensor with improved performance.

[0004] An object of the present invention is to provide an image sensor having improved conversion gain (CG). [Means for solving the problem]

[0005] In order to achieve the above technical objective, a stacked image sensor according to the technical idea of ​​the present disclosure is disclosed.

[0006] The image sensor includes a first semiconductor chip including a first photoelectric conversion layer, a first floating diffusion region, and a first transfer transistor electrically connecting the first photoelectric conversion layer and the first floating diffusion region, and a second photoelectric conversion layer, a second floating diffusion region, and a second transfer transistor electrically connecting the second photoelectric conversion layer and the second floating diffusion region; and a second semiconductor chip including at least one transistor and outputting a pixel signal based on the first photoelectric conversion layer and the second photoelectric conversion layer; wherein the first semiconductor chip includes the first transfer transistor. a first contact electrically connected to the second transfer transistor and extending in a Z-axis direction; a second contact electrically connected to the second transfer transistor and extending in a Z-axis direction; a plurality of third contacts electrically connected to the first floating diffusion region and the second floating diffusion region, respectively, and extending in a Z-axis direction; and a first metal region electrically connecting the plurality of third contacts and extending in an X-axis direction; the first contact, the second contact, and the first metal region may be in contact with a first surface of a first interlayer insulating layer on which the first contact, the second contact, and the first metal region are formed.

[0007] In order to achieve the above technical objective, a stacked image sensor according to the technical idea of ​​the present disclosure is disclosed.

[0008] The image sensor includes a first semiconductor chip including a first photoelectric conversion layer, a first floating diffusion region, and a first transfer transistor electrically connecting the first photoelectric conversion layer and the first floating diffusion region, and a second photoelectric conversion layer, a second floating diffusion region, and a second transfer transistor electrically connecting the second photoelectric conversion layer and the second floating diffusion region; a second semiconductor chip including at least one transistor and outputting a pixel signal based on the first photoelectric conversion layer and the second photoelectric conversion layer; and a third semiconductor chip including a circuit for processing the pixel signal, a first contact electrically connected to the first transfer transistor and extending in a Z-axis direction; a second contact electrically connected to the second transfer transistor and extending in the Z-axis direction; a plurality of third contacts electrically connected to the first floating diffusion region and the second floating diffusion region, respectively, and extending in the Z-axis direction; and a first metal region electrically connecting the plurality of third contacts and extending in an X-axis direction; and the first contact, the second contact, and the first metal region may be in contact with a first surface of a first interlayer insulating layer on which the first contact, the second contact, and the first metal region are formed.

[0009] In order to achieve the above technical objective, a stacked image sensor according to the technical idea of ​​the present disclosure is disclosed.

[0010] the image sensor includes a pixel array in which a plurality of pixels are arranged; a row driver that provides a control signal to the pixel array; and a readout circuit that reads out a pixel signal output from a pixel of a row line selected by the row driver; each of the plurality of pixels includes a first photodiode; a first transfer transistor connected to the first photodiode; a second photodiode; a second transfer transistor connected to the second photodiode; a plurality of floating diffusion regions that accumulate charges generated in the first photodiode and the second photodiode; and a source follower transistor having a gate connected to the floating diffusion region; and a height of a first contact and a second contact that are electrically connected to the first transfer transistor and the second transfer transistor, respectively, and extend in a Z-axis direction is equal to a height of a first metal region that is electrically connected to each of the plurality of floating diffusion regions and electrically connects a plurality of third contacts that extend in the Z-axis direction and extend in the X-axis direction.

[0011] In order to achieve the above technical objective, a method for manufacturing a stacked image sensor according to the technical idea of ​​the present disclosure is disclosed.

[0012] The manufacturing method also includes forming a transfer transistor and a plurality of floating diffusion regions in a first substrate, forming a first interlayer insulating layer on the first substrate, etching a first metal region and a contact region of the first interlayer insulating layer to form a first recess region, a second recess region, and a third recess region, depositing a first material in the first recess region, the second recess region, and the third recess region, performing a first CMP process, forming a second interlayer insulating layer, etching the second interlayer insulating layer to form a fourth recess region, depositing a second material in the fourth recess region, and performing a second CMP process. Effect of the Invention

[0013] According to the image sensor according to the technical idea of ​​the present disclosure, a stacked image sensor capable of ensuring conversion gain is disclosed.

[0014] The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other effects not mentioned can be clearly derived and understood by a person having ordinary skill in the art to which the exemplary embodiments of the present disclosure belong from the following description of the exemplary embodiments of the present disclosure. In other words, unintended effects by implementing the exemplary embodiments of the present disclosure can also be derived from the exemplary embodiments of the present disclosure by a person having ordinary skill in the art. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram of an image sensor according to an exemplary embodiment of the present disclosure. [Diagram 2] 2 is a block diagram for explaining a first pixel array, a second pixel array, a logic circuit, and an ADC (analog-to-digital converter) in FIG. 1. FIG. [Diagram 3] 2 is a circuit diagram for explaining unit pixels of a first pixel array and a second pixel array in FIG. 1. FIG. [Figure 4] 2 is a perspective view for three-dimensionally explaining a first pixel array, a logic circuit, and an ADC of the image sensor of FIG. 1. [Figure 5A] 2 is an exemplary cross-sectional view corresponding to a first pixel array of an image sensor according to the present disclosure. [Figure 5B] 5B is a diagram for explaining a relationship related to contacts included in the first pixel array according to FIG. 5A. FIG. [Figure 6] 2 is an exemplary cross-sectional view corresponding to a first pixel array of an image sensor according to the present disclosure. [Figure 7]2 is a diagram illustrating a connection relationship between components included in a first pixel array and a second pixel array of an image sensor according to the present disclosure. [Figure 8A] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 8B] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 8C] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 8D] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 8E] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 8F] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 8G] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 8H] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 9] 4 is a flowchart illustrating a method for manufacturing an image sensor according to the present disclosure. [Figure 10] 1 illustrates an example of a pixel circuit of an image sensor according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Various embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0017] FIG. 1 is a block diagram of an image sensor according to an exemplary embodiment of the present disclosure.

[0018] 1, the image sensor may include a first semiconductor chip 100, a second semiconductor chip 200, and a third semiconductor chip 300. The first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may be arranged to overlap each other in terms of planar area. The first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may be stacked in a vertical direction in sequence. The first semiconductor chip 100 may be referred to as an upper plate, the second semiconductor chip 200 may be referred to as a middle plate, and the third semiconductor chip 300 may be referred to as a lower plate.

[0019] The first semiconductor chip 100 also includes a first pixel array 10. The second semiconductor chip 200 also includes a second pixel array 20. The third semiconductor chip 300 also includes a logic circuit 30 and an analog-to-digital converter (ADC) 35. The first pixel array 10 may generate an electric charge in proportion to the amount of light entering the first pixel array 10. The second pixel array 20 may convert an optical signal into an electrical signal, i.e., an analog signal, under the control of the logic circuit 30. The second pixel array 20 may output the analog signal to the ADC 35. The ADC 35 may convert the analog signal into a digital signal. The ADC 35 may provide data based on the digital signal.

[0020] Although not shown, the image sensor according to some embodiments may also include a memory cell array, which may store data based on the digital signals.

[0021] The data may be image data generated in units of frames. The number of bits of the data may be determined based on the resolution of the ADC 35. The number of bits of the data may be determined based on a high dynamic range (HDR) supported by the image sensor. The bits of the data may further include at least one extension bit indicating a data generation position, data information, etc.

[0022] The image sensor according to the present disclosure includes a first pixel array 10 and a second pixel array 20, and is described as a 3-stack image sensor in which the first pixel array 10 and the second pixel array 20 are formed on different chips and stacked. The image sensor according to the present disclosure may secure a conversion gain (CG) through a connection structure of a contact region of the first pixel array 10 included in the first semiconductor chip 100. This will be described in detail below with reference to FIG. 5A and subsequent drawings.

[0023] FIG. 2 is a block diagram for explaining the first pixel array 10, the second pixel array 20, the logic circuit 30, and the ADC 35 of FIG.

[0024] 2, the first pixel array 10 may be implemented in a first semiconductor chip 100. The second pixel array 20 may be implemented in a second semiconductor chip 200. The logic circuit 30 (FIG. 1) may be implemented in a third semiconductor chip 300.

[0025] The first pixel array 10 may convert incident light and generate an electrical signal. The second pixel array 20 may include unit pixels arranged in a matrix form along row and column directions. The second pixel array 20 may be driven under the control of a logic circuit 30. Specifically, the logic circuit 30 may control a plurality of transistors included in the second pixel array 20. The plurality of transistors included in the second pixel array 20 may control the electrical signal transmitted from the first pixel array 10.

[0026] The logic circuit 30 may efficiently receive data from the second pixel array 20 and generate an image frame. For example, the logic circuit 30 may use a global shutter scheme in which all unit pixels are sensed simultaneously, a flutter shutter scheme in which an exposure time is adjusted in which all unit pixels are sensed simultaneously, a rolling shutter scheme or a coded rolling shutter scheme in which unit pixels are controlled by row, etc. The logic circuit 30 may also include a row driver 31 and a timing controller 32, and may be connected to an ADC 35.

[0027] The row driver 31 may control the second pixel array 20 on a row-by-row basis under the control of the timing controller 32. The row driver 31 may select at least one row of the rows of the second pixel array 20 according to a row address. The row driver 31 may decode the row address and be connected to a selection transistor SEL, a reset transistor RG, and a source follower transistor SF included in the second pixel array 20. The second pixel array 20 may be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, received from the row driver 31.

[0028] The ADC 35 may be connected to the second pixel array 20 via the column lines COL. The ADC 35 may convert an analog signal received from the second pixel array 20 via the column lines COL into a digital signal. The number of ADCs 35 may be determined based on the number of unit pixels arranged along one row and the number of column lines COL. The number of ADCs 35 may be at least one.

[0029] For example, the ADC 35 may include a reference signal generator REF, a comparator CMP, a counter CNT, and a buffer BUF. The reference signal generator REF may generate a ramp signal having a specific slope and provide the ramp signal as a reference signal for the comparator. The comparator CMP may compare an analog signal with the ramp signal of the reference signal generator REF and output a comparison signal having transition time points according to valid signal components. The counter CNT may perform a counting operation, generate a counting signal, and provide the counting signal to the buffer BUF. The buffer BUF may include latch circuits respectively connected to the column lines COL, and may latch the counting signals output from the counter CNT for each column in response to a transition of the comparison signal, and output the latched counting signals as data.

[0030] In some embodiments, the ADC 35 may further include a correlated double sampling circuit that obtains a difference between a reference voltage indicating a reset state of the unit pixel and an output voltage indicating a signal component corresponding to the incident light, performs correlated double sampling (CDS), and outputs an analog sampling signal corresponding to the effective signal component. The correlated double sampling circuit may be connected to the column line COL.

[0031] The timing controller 32 may control the operation timing of the row driver 31 and the ADC 35. The timing controller 32 may provide timing signals and control signals to the row driver 31 and the ADC 35. More specifically, the timing controller 32 controls the ADC 35, and the ADC 35 may provide data to the logic circuit 30 under the control of the timing controller 32. The timing controller 32 may also include a circuit that provides a request, command, or address to the logic circuit 30 so that data of the ADC 35 is stored in the memory cell array.

[0032] Fig. 3 is a circuit diagram for explaining unit pixels of the first pixel array and the second pixel array in Fig. 1. For reference, Fig. 3 also shows a 4T structure of the unit pixels constituting the first pixel array and the second pixel array.

[0033] 3, the first pixel array 10 also includes a photoelectric conversion layer PD, a transfer transistor TG, and a floating diffusion region (FD), and the second pixel array 20 also includes a reset transistor RG, a source follower transistor SF, and a selection transistor SEL.

[0034] The photoelectric conversion layer PD may generate charges in proportion to the amount of light incident from the outside. The photoelectric conversion layer PD may be coupled to a transmission transistor TG that transmits the generated and accumulated charges to a floating diffusion region FD. The floating diffusion region FD is a region that converts charges into voltages and has a parasitic capacitance, so that charges may be stored cumulatively. The charges accumulated in the floating diffusion region FD may be converted into a voltage. At this time, a ratio at which the charges accumulated in the floating diffusion region FD are converted into a voltage may be referred to as a conversion gain (CD). The conversion gain may vary depending on the capacitance of the floating diffusion region FD. If the capacitance of the floating diffusion region FD increases, the conversion gain may be reduced, and if the capacitance of the floating diffusion region FD is reduced, the conversion gain may be increased. According to the present disclosure, a connection structure between the floating diffusion region FD and the transmission transistor TG that can increase the conversion gain is proposed.

[0035] One end of the transfer transistor TG may be connected to the photoelectric conversion layer PD, and the other end of the transfer transistor TG may be connected to the floating diffusion region FD. The transfer transistor TG may be formed of a transistor driven by a predetermined bias (e.g., a transfer signal TX). That is, the transfer transistor TG may transfer charges generated from the photoelectric conversion layer PD to the floating diffusion region FD by the transfer signal TX. According to one example, the transfer transistor TG may also have a vertical transfer gate (VTG) structure that can improve the transfer efficiency of photocharges.

[0036] The source follower transistor SF amplifies the change in the electric potential of the floating diffusion region FD to which the charge is transferred from the photoelectric conversion layer PD, and outputs it to the output line V OUT When the source follower transistor SF is turned on, a predetermined electrical potential, for example, a power supply voltage V DD can be transferred to the drain region of the select transistor SEL.

[0037] The selection transistor SEL can select a unit pixel to be read on a row-by-row basis, and may be a transistor driven by a selection line that applies a predetermined bias (for example, a row selection signal SX).

[0038] The reset transistor RG can periodically reset the floating diffusion region FD. The reset transistor RG is also a transistor driven by a reset line that applies a predetermined bias (e.g., a reset signal (RX)). When the reset transistor RG is turned on by the reset signal RX, a predetermined electric potential, e.g., a power supply voltage V DD can be transmitted to the floating diffusion region FD.

[0039] According to an example, as the area of ​​a unit pixel becomes smaller, the photoelectric conversion layer PD and the transfer transistor TG may be formed in a first semiconductor chip 100 (FIG. 1), and the reset transistor RG, the source follower transistor SF, and the selection transistor SEL may be formed in a second semiconductor chip 200 (FIG. 1). The first semiconductor chip 100 and the second semiconductor chip 200 may be aligned to form a unit pixel.

[0040] FIG. 4 is a perspective view for three-dimensionally explaining the first pixel array 10, the second pixel array 20, the logic circuit 30, and the ADC 35 of the image sensor of FIG.

[0041] Referring to FIG. 4, in an image sensor according to some embodiments, a first semiconductor chip 100, a second semiconductor chip 200, and a third semiconductor chip 300 may be sequentially stacked. In FIG. 4, the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 are illustrated as having the same size, but this is for convenience of explanation only and is not intended to be limiting. The first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may also have different sizes. As described above, the first pixel array 10 may be disposed in the first semiconductor chip 100, and the second pixel array 20 may be disposed in the second semiconductor chip 200. The logic circuit 30 and the ADC 35 may be disposed in the third semiconductor chip 300.

[0042] In the first semiconductor chip 100, a plurality of unit pixels may be arranged in a two-dimensional array structure on a two-dimensional plane. Although not shown, the first pixel array 10 also includes a sensor array region and a pad region. The sensor array region may be disposed, for example, in a central portion of the first semiconductor chip 100, and the pad region may be disposed, for example, on an edge of the first semiconductor chip 100, but is not limited thereto.

[0043] The sensor array region may be provided with light and may include an array of active pixels that generate active signals. The second pixel array 20 may transmit control signals to the sensor array region of the first pixel array 10. The second pixel array 20 may transmit output signals of the unit pixels to the logic circuit 30 of the third semiconductor chip 300. The pad region may be configured to transmit and receive electrical signals between the image sensor according to some embodiments and an external device.

[0044] The logic circuit 30 also includes a circuit for processing a pixel signal received from a unit pixel. The logic circuit 30 can receive an image signal from the ADC 35 and process the image signal.

[0045] FIG. 5A is an exemplary cross-sectional view corresponding to a first pixel array of an image sensor according to the present disclosure.

[0046] 5A illustrates an example of a transfer transistor, a floating diffusion region, and a contact connection structure for connecting them, which are included in a first pixel array 10a of an image sensor according to the present disclosure. The cross-sectional view of FIG. 5A is also a cross-sectional view corresponding to a portion of a first semiconductor chip in which the first pixel array 10a is disposed.

[0047] 5A, the first pixel array 10a may include a first substrate 110a, a first interlayer insulating layer 120a, and a second interlayer insulating layer 130a. Referring to FIG 5A, the first substrate 110a, the first interlayer insulating layer 120a, and the second interlayer insulating layer 130a may be sequentially stacked in the Z-axis direction.

[0048] The first substrate 110a may include a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. The group IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or silicon (Si)-germanium (Ge). The group III-V semiconductor material may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). The group II-VI semiconductor material may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS).

[0049] Although not shown in FIG. 5A, a color filter and a microlens may be formed on the lower side of the first substrate 110a. A structure in which the color filter and the microlens are formed in the opposite direction to the first interlayer insulating layer 120a based on the first substrate 110a on which the pixels are formed is called a BSI (back side illumination) structure. Conversely, a structure in which the color filter and the microlens are formed in the same direction as the first interlayer insulating layer 120a based on the first substrate 110a, that is, a structure in which the color filter and the microlens are formed on the first interlayer insulating layer 120a, is called an FSI (front side illumination) structure. In the present disclosure, an image sensor having a BSI structure is assumed for description, but it should be noted that the present disclosure is not limited thereto.

[0050] The first interlayer insulating layer 120a may cover the vertical transmission gate 11a_1 of the first substrate 110a. The first interlayer insulating layer 120a may include a multi-layer structure. The first interlayer insulating layer 120a may include, for example, silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the first interlayer insulating layer 120a may include a low-k material having a dielectric constant less than that of silicon oxide.

[0051] The second interlayer insulating layer 130a may be disposed on the first interlayer insulating layer 120a. The second interlayer insulating layer 130a may include, for example, silicon oxide, silicon nitride, or a combination thereof. According to an example, the first interlayer insulating layer 120a and the second interlayer insulating layer 130a may be made of different materials.

[0052] The first substrate 110a may also include a plurality of floating diffusion regions 12a_1 and 12a_2. The plurality of floating diffusion regions 12a_1 and 12a_2 may be disposed in the first substrate 110a so as to be adjacent to a first surface 120a_2 of the first substrate 110a. Each of the plurality of floating diffusion regions 12a_1 and 12a_2 may also be an impurity region in the first substrate 110a.

[0053] The first substrate 110a further includes a plurality of vertical transmission gates 11a_1 and 11a_2. In some embodiments, the vertical transmission gates 11a_1 and 11a_2 may be recessed into the first substrate 110a from the first surface 120a_2 of the first substrate 110a. In other embodiments, unlike the embodiment illustrated in FIG. 5A, the vertical transmission gates 11a_1 and 11a_2 are not recessed into the first substrate 110a. According to an example, the vertical transmission gates 11a_1 and 11a_2 may be included in the transmission transistor TG of FIG. 3. The source / drain regions 11a_d and 11a_s may be disposed on both sides of the vertical transmission gates 11a_1 and 11a_2. The first substrate 110a may also include shallow trench isolation (STI) regions 150a_1, 150a_2, and 150a_3. The STI regions 150a_1, 150a_2, and 150a_3 may be made of an insulating material. The STI regions 150a_1, 150a_2, and 150a_3 may be, for example, an oxide, a nitride, or a combination thereof. The bottom arrangement of the STI regions 150a_1, 150a_2, and 150a_3 is not limited to that shown in FIG. 5A and may be variously changed according to an embodiment. An oxide film 140a may be disposed between the first substrate 110a and the first interlayer insulating layer 120a. According to the example shown in FIG. 5A, two vertical transmission gates 11a_1 and 11a_2 may be provided, and two floating diffusion regions 12a_1 and 12a_2 may be provided. They may be vertical transmission gates and floating diffusion regions included in different unit pixels, or may be vertical transmission gates and floating diffusion regions included in one unit pixel.

[0054] The first interlayer insulating layer 120a also includes a first contact 13a_1 electrically connected to the first vertical transmission gate 11a_1 and extending in the Z-axis direction, a second contact 13a_2 electrically connected to the second vertical transmission gate 11a_2 and extending in the Z-axis direction, a plurality of third contacts 13a_3 and 13a_4 electrically connected to the floating diffusion regions 12a_1 and 12a_2, respectively, and extending in the Z-axis direction, and a first metal region 14a electrically connecting the plurality of third contacts 13a_3 and 13a_4 and extending in the X-axis direction.

[0055] 5A, the floating diffusion regions 12a_1 and 12a_2 may be electrically connected to each other by a first metal region 14a extending in the X-axis direction. The first metal region 14a may be disposed such that one side of the first metal region 14a contacts a first surface 120a_1 of the first interlayer insulating layer 120a. Referring to FIG. 5A, the first metal region 14a, the first contact 13a_1, and the second contact 13a_2 may each extend in the Z-axis direction to contact the first surface 120a_1 of the first interlayer insulating layer 120a.

[0056] 5A, the third contacts 13a_3 and 13a_4 and the first metal region 14a are connected to one another. The third contacts 13a_3 and 13a_4 extend from the floating diffusion regions 12a_1 and 12a_2 in the Z-axis direction and are not in contact with the first interlayer insulating layer 120a. The first metal region 14a is a region disposed between the upper surfaces of the third contacts 13a_3 and 13a_4 and the first surface 120a_1 of the first interlayer insulating layer 120a.

[0057] According to an example, the first contact 13a_1, the second contact 13a_2, the plurality of third contacts 13a_3 and 13a_4, and the first metal region 14a may include a metal material. According to an example, the first contact 13a_1, the second contact 13a_2, the plurality of third contacts 13a_3 and 13a_4, and the first metal region 14a may include a conductive material. According to an example, the first contact 13a_1, the second contact 13a_2, the plurality of third contacts 13a_3 and 13a_4, and the first metal region 14a may be formed of the same material. A specific relationship between the first contact 13a_1, the second contact 13a_2, the plurality of third contacts 13a_3 and 13a_4, and the first metal region 14a will be described in detail later with reference to FIG. 5B.

[0058] The second interlayer insulating layer 130a also includes a plurality of first vias 15a_1 and 15a_3, a second via 15a_2, a plurality of second metal regions 16a_1 and 16a_3, and a third metal region 16a_2. The first via 15a_1 may electrically connect the second metal region 16a_1 to the first contact 13a_1. The second via 15a_2 may electrically connect the third metal region 16a_2 to the first metal region 14a. The first via 15a_3 may electrically connect the second metal region 16a_3 to the second contact 13a_2. According to one example, the first vias 15a_1 and 15a_3, the second vias 15a_2, the second metal regions 16a_1 and 16a_3, and the third metal region 16a_2 may include a different material from the first contacts 13a_1, the second contacts 13a_2, the third contacts 13a_3 and 13a_4, and the first metal region 14a. According to one example, the first contacts 13a_1, the second contacts 13a_2, the third contacts 13a_3 and 13a_4, and the first metal region 14a may include tungsten (W), and the first vias 15a_1 and 15a_3, the second vias 15a_2, the second metal regions 16a_1 and 16a_3, and the third metal region 16a_2 may include copper (Cu). According to one example, the second metal regions 16a_1 and 16a_3 and the third metal region 16a_2 are also metal layers located in the same layer.

[0059] Fig. 5B is a diagram for explaining a relationship related to contacts included in the first pixel array according to Fig. 5A. Fig. 5B is a diagram for explaining a relationship between a plurality of third contacts 13a_3, 13a_4 and a first metal region 14a connected to a plurality of floating diffusion regions 12a_1, 12a_2, and a first contact 13a_1 and a second contact 13a_2 connected to vertical transmission gates 11a_1, 11a_2, respectively, shown in Fig. 5A. In this disclosure, thickness may refer to the width of a corresponding component in the Z-axis direction, and height may refer to the value at the highest position of the corresponding component in the Z-axis direction.

[0060] According to one example, the thickness of the first interlayer insulating layer 120a in which the first contact 13a_1, the second contact 13a_2, the third contacts 13a_3 and 13a_4, and the first metal region 14a are formed is also d4. The thickness of the first metal region 14a is also d2. The thickness of the first contact 13a_1 is also d1. The thickness of the second contact 13a_2 is also d1. The thickness of the third contacts 13a_3 and 13a_4 is also d3. According to one example, the sum of the thickness of the third contacts 13a_3 and 13a_4 and the thickness of the first metal region 14a is also the same as the thickness of the first interlayer insulating layer 120a.

[0061] Referring to FIG 5B, the height of vertical transmission gates 11a_1 and 11a_2 is also h1. Referring to FIG 5B, the height of the plurality of third contacts 13a_3 and 13a_4 is also h2. According to one example, the height of first metal region 14a is also h3. According to one example, the height of first contact 13a_1 and second contact 13a_2 is also h3.

[0062] According to one example, the thicknesses of the first contact 13a_1, the second contact 13a_2, and the plurality of third contacts 13a_3 and 13a_4 may be the same or different.

[0063] 5B, the height of the first metal region 14a may be the same as the height of the first contact 13a_1 and the second contact 13a_2. According to one example, one side of the first metal region 14a may contact upper surfaces of the third contacts 13a_3 and 13a_4, and the other side of the first metal region 14a may contact a first surface of the first interlayer insulating layer 120a.

[0064] 5B, the distance between the floating diffusion regions 12a_1 and 12a_2 is also P1. According to one example, P2, which is the length of the first metal region 14a in the X-axis direction, may be greater than the distance between the floating diffusion regions 12a_1 and 12a_2.

[0065] That is, according to the present disclosure, by setting the heights of the first metal region 14a connecting the third contacts 13a_3 and 13a_4 in the X-axis direction and the first contacts 13a_1 and the second contacts 13a_2 connected to the vertical transmission gates 11a_1 and 11a_2, respectively, to be the same, connection with the source follower transistors formed in the second semiconductor chip can be easily performed. Also, by introducing the first metal region 14a, the distance between the floating diffusion regions 12a_1 and 12a_2 and the metal layer to which the source follower transistors are connected can be increased, and the capacitance can be reduced, thereby ensuring the conversion gain.

[0066] 6 is an exemplary cross-sectional view corresponding to a first pixel array of an image sensor according to the present disclosure. In the description of FIG. 6, the description of the parts overlapping with FIG. 5A and FIG. 5B will be omitted.

[0067] Referring to FIG. 6, a first pixel array 10b is formed on a first semiconductor chip and includes a first substrate 110b, a first interlayer insulating layer 120b and a second interlayer insulating layer 130b.

[0068] The first substrate 110b also includes a plurality of floating diffusion regions 12b_1, 12b_2, vertical transmission gates 11b_1, 11b_2, source / drain regions 11b_s, 11b_d, and STI regions 150b_1, 150b_2, and 150b_3.

[0069] The first interlayer insulating layer 120b also includes a first contact 13b_1, a second contact 13b_2, a plurality of third contacts 13b_3 and 13b_4, and a first metal region 14b.

[0070] The second interlayer insulating layer 130b also includes first vias 15b_1 and 15b_2 and second metal regions 16b_1 and 16b_2. The second interlayer insulating layer 130b also includes a first via 15b_1 that connects the first contact 13b_1 to the second metal region 16b_1 and a first via 15b_2 that connects the second contact 13b_2 to the second metal region 16b_2.

[0071] Compared to the first pixel array 10a of FIG. 5A, the second interlayer insulating layer 130b included in the first pixel array 10b of FIG. 6 does not include a second via connecting the first metal region 14b and the third metal region.

[0072] FIG. 7 is a diagram illustrating a connection relationship between components included in a first pixel array and a second pixel array of an image sensor according to the present disclosure.

[0073] Referring to FIG. 7, a cross-sectional view corresponding to a first pixel array 10c and a cross-sectional view corresponding to a second pixel array 20c of an image sensor according to the present disclosure are respectively disclosed.

[0074] Referring to the cross-sectional view of the first pixel array 10c, a floating diffusion region FD and a vertical transmission gate VTG formed on a first substrate 110c are disclosed. Referring again to the cross-sectional view of the first pixel array 10c, a third contact CA_3 extending in the Z-axis direction and a first metal region M0 extending in the X-axis direction are disclosed in the floating diffusion region FD, and a first contact CA_1 extending in the Z-axis direction from the vertical transmission gate VTG to a height corresponding to the first metal region M0 is disclosed. The height of the first contact CA_1 connected to the vertical transmission gate VTG is the same as the height of the third contact CA_3 and the first metal region M0 connected to the floating diffusion region FD. A first via VO and a second metal region M1 may be connected to the first contact CA_1 and the first metal region M0 at the same height, respectively.

[0075] Referring to FIG. 7, the conversion gain of the stacked image sensor may be improved by using the first metal region M0 included in the first pixel array 10c. According to the present disclosure, the floating diffusion region FD may be electrically connected through the third contact CA_3 and the first metal region M0 formed by the same process. The same process may be a dual damascene process. According to the present disclosure, in order to reduce the capacitance of the floating diffusion region FD in the upper plate, the first metal region M0 may be added and the distance between the floating diffusion region FD and the second metal region M1 may be increased. According to an example, the plurality of floating diffusion regions may be electrically connected through the first metal region M0, and the plurality of floating diffusion regions may be connected to the source follower transistor of the second semiconductor chip through the first metal region M0, the first via V0, and the second metal region M1. That is, a step may be formed through the first metal region M0.

[0076] According to the present disclosure, easy connection to subsequent layers is possible via the first contact CA_1 and the first metal region M0, which are at the same height.

[0077] Referring to the cross-sectional view of the second pixel array 20c, the second substrate 220c also includes source / drain regions corresponding to the source follower transistor SF and the selection transistor SEL, respectively. A gate of the source follower transistor SF and a gate of the selection transistor SEL may be disposed on the upper portion of the second substrate 220c.

[0078] The gate of the source follower transistor SF also includes a contact CA_4 formed to extend in the Z-axis direction, and a plurality of metal regions M3.

[0079] According to the present disclosure, when the first metal region M0 is formed in the first pixel array 10c, it has the same height as the first contact CA_1 and can be manufactured using a dual damascene process, thereby simplifying the process. In addition, a step is formed with the second metal region M2 through the first via V0, and the source follower transistor SF of the second pixel array 20c can be easily connected through the first via V0 and the second metal region M1. The first pixel array 10c and the second pixel array 20c can be connected using C2C, deep contact, a method of connecting multiple metal layers to each other, etc.

[0080] 8A through 8H are cross-sectional views illustrating a method for manufacturing an image sensor according to the present disclosure.

[0081] 8A, components corresponding to a transfer transistor may be formed on a first substrate 110d. Vertical transfer gates 11d_1 and 11d_2, source / drain regions 11d_s and 11d_d, floating diffusion regions FD, and STI regions 150d may be formed on the first substrate 110d. An oxide film 140d may be formed to cover the formed vertical transfer gates 11d_1 and 11d_2, and a first interlayer insulating layer 120d may be formed thereon. This may be formed by a deposition process.

[0082] 8B, the first recess region Recess_1 may be formed by a mask pattern for forming the first metal region. According to one example, the first recess region Recess_1 may be formed by anisotropically etching the first interlayer insulating layer 120d to form the first metal region. The first recess region Recess_1 may be formed by a wet etching process or a dry etching process. According to one example, the thickness of the first recess region Recess_1 may be formed as thin as possible.

[0083] 8C, the first interlayer insulating layer 120d may be anisotropically etched to form the first and second contacts, forming a second recess region Recess_2, and the first interlayer insulating layer 120d may be anisotropically etched to form a plurality of third contacts, forming a third recess region Recess_3. The second recess region Recess_2 and the third recess region Recess_3 may be formed by a wet etching process or a dry etching process. The second recess region Recess_2 may be connected to the vertical transmission gates 11d_1 and 11d_2, and the third recess region Recess_3 may be connected to the floating diffusion region FD. According to an example, the order of the steps of FIG. 8B and FIG. 8C may be changed.

[0084] 8D, the first recess region, the second recess region, and the third recess region may be deposited simultaneously, which may be a dual damascene process. Thus, the first contact, the second contact, the plurality of third contacts, and the first metal region may be formed simultaneously. In one embodiment, the deposited material may be tungsten (W).

[0085] 8E, a CMP process may be performed to a height corresponding to the first metal region, so that the first contact CA_1, the second contact CA_2, the plurality of third contacts CA_3, and the first metal region M0 may have the same height.

[0086] 8F, a second interlayer insulating layer 130d may be formed. At this time, the material deposited to form the second interlayer insulating layer 130d may be different from the material deposited to form the first interlayer insulating layer 120d.

[0087] 8G, a fourth recess region Recess_4 may be formed in the second interlayer insulating layer 130d. The fourth recess region Recess_4 may be formed by anisotropically etching the second interlayer insulating layer 130d to form the first via and the second metal region. The fourth recess region Recess_4 may be connected to the first contact and the second contact.

[0088] Referring to FIG. 8H, a deposition process may be performed to fill the fourth recess region Recess_4. This may be a dual damascene process. Thus, the first via and the second metal region may be formed simultaneously. In one example, the deposited material may be copper (Cu). In one example, the deposited materials may be different between the dual damascene process of FIG. 8D and the dual damascene process of FIG. 8H.

[0089] Thereby, a first pixel array corresponding to FIG. 6 can be formed.

[0090] By expanding the fourth recess region Recess_4 of FIG. 8H, a first pixel array corresponding to FIG. 5A can be formed.

[0091] 8A to 8H, a manufacturing method for a region corresponding to a first pixel array of an image sensor has been described. According to the present disclosure, in a process for manufacturing an image sensor in which three chips are stacked, the distance between the floating diffusion region and the second metal region can be increased to reduce the capacitance of the floating diffusion region. To this end, a first metal region can be used to connect a plurality of floating regions to each other, and the height of the first metal region and the first contact connected to the vertical transmission gate can be made the same, and a connection to a source follower transistor present in another chip can be easily made by connecting the first via to the second metal region.

[0092] FIG. 9 is a flow chart illustrating a method for manufacturing an image sensor according to the present disclosure.

[0093] Referring to step S100, a transfer transistor and a floating diffusion region may be formed on a first substrate, which corresponds to FIG. 8A.

[0094] Referring to step S200, a first interlayer insulating layer may be formed on a first substrate, which corresponds to the step of FIG. 8A.

[0095] Referring to step S300, a first interlayer insulating layer may be etched to form a first recess region corresponding to a first metal region, a second recess region corresponding to a contact region, and a third recess region, which corresponds to Fig. 8B and Fig. 8C. The second recess region may be a recess region for forming a contact connected to a vertical transmission gate, and the third recess region may be a recess region for forming a contact connected to a floating diffusion region. According to an example, the first recess region may have a length longer than a distance between the floating diffusion regions.

[0096] Referring to step S400, deposition may be performed on the first through third recessed regions using a first material, which corresponds to FIG.

[0097] Referring to step S500, a first CMP process may be performed, which also corresponds to Fig. 8E. Through steps S400 and S500, the first contact, the second contact, and a plurality of third contacts having the same height as each other and the first metal region connected thereto are formed through a dual damascene process, and since they are formed simultaneously, a process simplification effect can be obtained.

[0098] Referring to step S600, a second interlayer insulating layer may be deposited, which corresponds to Fig. 8F. According to one embodiment, the first interlayer insulating layer and the second interlayer insulating layer may not each contain the same material.

[0099] Referring to step S700, the second interlayer insulating layer may be etched to form a fourth recessed region corresponding to the first via and the second metal region, which also corresponds to FIG.

[0100] Referring to step S800, a second material may be deposited in the fourth recessed region.

[0101] Referring to step S900, a second CMP process may be performed. Steps S800 and S900 also correspond to FIG.

[0102] Through steps S700 to S900, the first via and the second metal region can be simultaneously formed, resulting in a simplified process. The first via and the second metal region can also be formed by a dual damascene process. The conductive material included in the first via and the second metal region is also different from the conductive material included in the first contact, the second contact, the plurality of third contacts, and the first metal region.

[0103] According to the present disclosure, a connection structure for increasing a conversion gain when a floating diffusion region located in a first semiconductor chip is connected to a source follower transistor located in a second semiconductor chip is proposed. In order to increase the conversion gain, a reduction in capacitance of the floating diffusion region is required. According to the present disclosure, in order to increase the distance between the floating diffusion region and a metal layer for connection with other components, a first metal region for connection between the floating diffusion regions is added, and the source follower transistor can be connected via a first via and a second metal region that can be connected to the first metal region.

[0104] FIG. 10 is an example of a pixel circuit of an image sensor according to the present disclosure.

[0105] 10, the unit pixels PX included in the image sensor according to the embodiment of the present disclosure also include pixel circuits PXC corresponding to each of the unit pixels PX. The pixel circuits PXC also include a plurality of semiconductor elements for processing charges generated in the photodiodes PD1, PD2, PD3, and PD4 included in each of the unit pixels PX. As an example, the pixel circuit PXC also includes a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, and a fourth photodiode PD4. The pixel circuit PXC also includes a first transfer transistor TX1, a second transfer transistor TX2, a third transfer transistor TX3, and a fourth transfer transistor TX4, a reset transistor RX, a selection transistor SX, and a driving transistor DX corresponding to each of the photodiodes PD1, PD2, PD3, and PD4. The photodiodes PD1, PD2, PD3, and PD4 included in the pixel circuit PXC may share a floating diffusion region FD, a reset transistor RX, a selection transistor SX, and a driving transistor DX.

[0106] In addition, the gate electrodes of the transistors TX1, TX2, TX3, TX4, RX, SX, and DX included in the pixel circuit PXC may be connected to the driving signal line. For example, the first transmission transistor TX1, the second transmission transistor TX2, the third transmission transistor TX3, and the fourth transmission transistor TX4 may receive transmission control signals TG1, TG2, TG3, and TG4 from a transmission control signal line, the reset transistor RX may receive a reset control signal RG from a reset control signal line, and the selection transistor SX may receive a selection control signal SG. However, these are merely exemplary embodiments and are not limited to those shown in FIG. 10. The pixel circuit PXC may be designed in various ways. For example, the pixel circuit PXC may include a semiconductor element for processing charges generated in a photodiode in a unit larger or smaller than the unit pixel PX.

[0107] The first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 may be connected to the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4, respectively. The first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 may share a floating diffusion region FD. The first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 may generate charges in proportion to the amount of light incident from the outside and accumulate them in the photodiodes.

[0108] The first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 may sequentially transfer charges stored in the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 to the floating diffusion region FD. Different transfer control signals TG1, TG2, TG3, and TG4 may be applied to the gate electrodes of the first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 to transfer charges generated in any one of the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 to the floating diffusion region FD. Thus, the floating diffusion region FD may accumulate charges generated in at least one of the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4.

[0109] According to one embodiment of the present disclosure, charges from four photodiodes may be accumulated in a floating diffusion region FD. The floating diffusion region FD connected to the four photodiodes may be formed as a plurality of floating diffusion regions, for example, four floating diffusion regions, each corresponding to four transfer transistors, and the plurality of floating diffusion regions may be electrically connected through a first metal region. Referring to FIG. 10, four floating diffusion regions may be electrically connected through the first metal region, and according to another embodiment, eight floating diffusion regions may be electrically connected through the first metal region. In this case, gates of the plurality of transfer transistors may be connected to the first vias through separate contacts.

[0110] The reset transistor RX may periodically reset the charge stored in the floating diffusion region FD. As an example, the electrode of the reset transistor RX may be connected to the floating diffusion region FD and the power supply voltage V DD When the reset transistor RX is turned on, the power supply voltage V DD Due to the potential difference with the power supply voltage V, the charge stored in the floating diffusion region FD is discharged, the floating diffusion region FD is reset, and the voltage of the floating diffusion region FD becomes the power supply voltage V. DD It also becomes the same as.

[0111] The operation of the driving transistor DX can be controlled by the amount of charge accumulated in the floating diffusion region FD. The driving transistor DX can function as a source follower buffer amplifier in combination with a current source disposed outside the unit pixel PX. For example, the driving transistor DX can amplify the potential change caused by the charge accumulation in the floating diffusion region FD and output it to the output line V. out The output can be

[0112] The selection transistor SX may select a unit pixel PX to be read in a row unit. When the selection transistor SX is turned on, an electrical signal output from the driving transistor DX may be transferred to the selection transistor SX.

[0113] As above, exemplary embodiments have been disclosed with the drawings and the specification. In this specification, the embodiments have been described using specific terms, but these terms are merely used for the purpose of describing the technical idea of ​​the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and other equivalent embodiments are possible. Therefore, the true technical scope of protection of the present disclosure is defined by the technical idea of ​​the claims. [Explanation of symbols]

[0114] 10,10a First Pixel Array 20 Second Pixel Array 30 Third Pixel Array 31 Row Driver 32 Timing Controller 35 ADC 100 First semiconductor chip 110a First Board 120a First interlayer insulation layer 130a Second interlayer insulation layer 200 Second semiconductor chip 300 The third semiconductor chip

Claims

1. a first semiconductor chip including a first photoelectric conversion layer, a first floating diffusion region, a first transfer transistor electrically connecting the first photoelectric conversion layer and the first floating diffusion region, a second photoelectric conversion layer, a second floating diffusion region, and a second transfer transistor electrically connecting the second photoelectric conversion layer and the second floating diffusion region; a second semiconductor chip including at least one transistor and outputting a pixel signal based on the first photoelectric conversion layer and the second photoelectric conversion layer; The first semiconductor chip is a first contact electrically connected to the first transfer transistor and extending in a Z-axis direction; a second contact electrically connected to the second transfer transistor and extending in a Z-axis direction; a plurality of third contacts electrically connected to the first floating diffusion region and the second floating diffusion region, respectively, and extending in a Z-axis direction; a first metal region electrically connecting the third contacts and extending in an X-axis direction; a first contact, a second contact, and a first metal region in contact with a first surface of a first interlayer insulating layer on which the first contact, the second contact, and the first metal region are formed.

2. 2. The stacked image sensor of claim 1, wherein the first contact, the second contact, the first metal region, and the third contact comprise the same conductive material.

3. 3. The stacked image sensor of claim 2, wherein the first contact, the second contact, the first metal region, and the third contact include tungsten (W).

4. The first semiconductor chip is a second interlayer insulating layer disposed on the first surface of the first interlayer insulating layer; The second interlayer insulating layer is a first via and a second metal region connected to the first contact and the second contact, respectively; 2. The stacked image sensor of claim 1, further comprising: a second via connected to the first metal region and a third metal region.

5. 5. The stacked type image sensor according to claim 4, wherein the second metal region and the third metal region are a same metal layer.

6. The first via, the second metal region, the second via, and the third metal region are 5. The stacked image sensor of claim 4, wherein the first contact, the second contact, the first metal region, and the third contacts include different conductive materials.

7. 2. The stacked image sensor of claim 1, wherein the second semiconductor chip further comprises a source follower transistor connected to the first floating diffusion region and the second floating diffusion region.

8. a first semiconductor chip including a first photoelectric conversion layer, a first floating diffusion region, a first transfer transistor electrically connecting the first photoelectric conversion layer and the first floating diffusion region, a second photoelectric conversion layer, a second floating diffusion region, and a second transfer transistor electrically connecting the second photoelectric conversion layer and the second floating diffusion region; a second semiconductor chip including at least one transistor and outputting a pixel signal based on the first photoelectric conversion layer and the second photoelectric conversion layer; a third semiconductor chip including a circuit for processing the pixel signal; The first semiconductor chip is a first contact electrically connected to the first transfer transistor and extending in a Z-axis direction; a second contact electrically connected to the second transfer transistor and extending in a Z-axis direction; a plurality of third contacts electrically connected to the first floating diffusion region and the second floating diffusion region, respectively, and extending in a Z-axis direction; a first metal region electrically connecting the third contacts and extending in an X-axis direction; a first contact, a second contact, and a first metal region in contact with a first surface of a first interlayer insulating layer on which the first contact, the second contact, and the first metal region are formed.

9. 9. The stacked image sensor of claim 8, wherein the first contact, the second contact, the first metal region, and the third contact include the same conductive material.

10. The first semiconductor chip is a second interlayer insulating layer disposed on the first surface of the first interlayer insulating layer; The second interlayer insulating layer is a first via and a second metal region connected to the first contact and the second contact, respectively; 9. The stacked image sensor of claim 8, further comprising: a second via connected to the first metal region and a third metal region.

11. The first via, the second metal region, the second via, and the third metal region are 11. The stacked image sensor of claim 10, wherein the first contact, the second contact, the first metal region, and the third contacts include different conductive materials.

12. the second semiconductor chip further includes a source follower transistor connected to the first floating diffusion region and the second floating diffusion region, 9. The stacked image sensor according to claim 8, wherein the third semiconductor chip includes a plurality of logic circuits for controlling the source follower transistors.

13. The second semiconductor chip is disposed on an upper portion of the third semiconductor chip, 13. The stacked type image sensor according to claim 12, wherein the first semiconductor chip is disposed on an upper portion of the second semiconductor chip.

14. 9. The stacked image sensor of claim 8, wherein the first contact, the second contact, the first metal region, and the third contacts include tungsten.

15. the first contact, the second contact, the first metal region, and the third contacts include tungsten; 12. The stacked image sensor of claim 11, wherein the first via, the second metal region, the second via, and the third metal region contain copper.

16. A pixel array in which a plurality of pixels are arranged; a row driver for providing control signals to the pixel array; a readout circuit for reading out pixel signals output from pixels of a row line selected by the row driver; Each of the plurality of pixels comprises: A first photodiode; a first transfer transistor coupled to the first photodiode; A second photodiode; a second transfer transistor coupled to the second photodiode; a plurality of floating diffusion regions for storing charges generated by the first photodiode and the second photodiode; a source follower transistor having a gate coupled to the floating diffusion region; The heights of the first and second contacts, which are electrically connected to the first and second transfer transistors, respectively, and extend in the Z-axis direction, are a plurality of third contacts electrically connected to the plurality of floating diffusion regions, each of the third contacts extending in a Z-axis direction, and having a height equal to that of a first metal region extending in an X-axis direction.

17. 17. The stacked image sensor of claim 16, wherein the first contact, the second contact, the third contact, and the first metal region include the same conductive material.

18. 18. The stacked image sensor of claim 17, wherein the first contact, the second contact, the third contact, and the first metal region include tungsten (W).

19. 17. The stacked image sensor according to claim 16, wherein a height of the third contacts is a value obtained by subtracting a thickness of the first metal region from a height of the first metal region.

20. 17. The stacked image sensor of claim 16, wherein the first metal region is formed on the third contacts.

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