All-algorithm-compatible program

Abstract

To provide an all-algorithm-compatible program capable of implementing any algorithm in one program without changing a structure of the program or adding or deleting the program itself.SOLUTION: An algorithm is divided into a plurality of pieces of processing, and each processing is solved by continuously constructing a variable data structure by executing one structured program per processing, line by line, based on each processing data, and by adding a first address of a line to be executed as data for each processing data.SELECTED DRAWING: Figure 55

Description

Technical Field

[0001] The present invention relates to a system that writes a program and uses a programmable logic controller (PLC) that can handle various algorithms, a personal computer (PC) that writes a program and can handle various algorithms, and the like.

Background Art

[0002] Conventionally, in a production factory, equipment and devices for automating the production process have been used. As a control device for electrically controlling such equipment and devices, a programmable logic controller (PLC) has been used. In recent years, a programmable logic controller (PLC) system has been constructed by connecting a programmable logic controller (PLC), a touch panel (TP) as an interface, external link I / O (I / O), various network devices, a personal computer (PC), etc. with various cables and making them complement each other, and it has been used.

[0003] Among them, for example, Patent Document 1 (Patent No. 5335128) has been devised, which aims to easily change the control program when changing the order of processes or the set values in the facilities constituting a plant. Also, Patent Document 2 (Patent No. 5155228), which aims to facilitate and shorten engineering work, Patent Document 3 (Patent No. 6023266), which aims to provide a programmable logic controller (PLC) program management device that diversely configures the size of memory blocks assigned to each user program and improves the usability of unused space to enable flexible program modification and addition, Patent Document 4 (Japanese Patent Application No. 7-78376), which aims to enable the rapid creation and necessary modification of a program suitable for an application in a robot control system, Patent Document 5 (Japanese Patent Application No. 14-41125), which aims to keep the design cost and creation cost of an operation scheduler that executes a unit sequence low, etc. have also been devised. Furthermore, in relation to data structures, Patent Document 6 (Patent No. 4770694), which aims to efficiently search within data having a data structure composed of identification information consisting of a plurality of components and an information body associated with the identification information, and Patent Document 7 (Patent No. 4884438), which aims to efficiently compress an XML (Extensible Markup Language)-based document, etc. in a data structure representing a hierarchical tree, where the data structure is content of a content type associated with a compression coding technique, have been devised.

[0004] In the invention of Patent Document 1 (Patent No. 5335128), it is divided into an operation control circuit, a process control circuit, a main control circuit, and a process control circuit. However, the operation circuit is a general automatic circuit, the process control circuit is a recipe selection circuit or a setup change circuit, the main control circuit is an initial setting circuit, and the process control circuit is a data setting screen control circuit, and there is not much difference from the old design method. That is, it is only a plant version of recipe control performed in the manufacture of liquid crystals and semiconductors. In other words, it is only a setup change of an automatic process and does not support the dispersion and convergence of free processes.

[0005] In the invention of Patent Document 2 (Patent No. 5155228), a template is created by prescribing the form in advance. However, for forms that are not prescribed, it is necessary to create a template in the conventional manner. It only attempts to shorten the work by this difference. It is merely the same as a subroutine or a function block just by naming it a template. This invention also does not support the dispersion and convergence of free processes.

[0006] In the invention of Patent Document 3 (Patent No. 6023266), although waste is reduced by making continuous memory into block sizes such as N, 2N, 4N of the size to be stored, between N and 2N, between 2N and 4N, etc., it is still the same as the conventional case. When a large amount of additional data occurs, it straddles them, and it was necessary to define new N, 2N, 4N. Also, it does not support cases where the continuous rows themselves are variable.

[0007] The invention of Patent Document 4 (Japanese Patent Application No. 7-78366) is a robot control system that uses a hierarchical structure instead of plant control. Even if a program can be selected in a hierarchical structure, for robot control, it takes time for fine-tuning corresponding to the actual movement, and since this fine-tuning is important, it has only partial advantages. Also, like Patent Document 1 and Patent Document 2, this invention does not support the dispersion and convergence of free processes.

[0008] The invention of Patent Document 5 (Japanese Patent Application No. 14-41125) is almost plant control. However, it attempts to realize that the program is divided into a unit sequence part with the current programmable logic controller (PLC) unit as a unit, the current stepping circuit and sequential circuit as an operation scheduler part, and a parameter buffer that describes the form of the unit and the operation scheduler, so that the creation cost can be kept low. However, it has drawbacks such as the processing of constantly monitoring in units and the complexity of processing when multiple units are involved at one point.

[0009] In the invention of Patent Document 6 (Patent No. 4770694), efficient search is achieved by collating identification information and indexes at the component unit level, etc. The main focus is on the speed of searching for the data structure, and it is not a data structure for the extensibility of the program itself.

[0010] In the invention of Patent Document 7 (Patent No. 4884438), it compensates for the drawbacks of the prior art, provides an efficient compression technique for XML-based documents, document skipping ability, and a progressive structure, and it is not a data structure for the extensibility of the program itself.

[0011] Conventionally, even in the control of plants and robots, except for complete replication devices, it is common practice to make the control dedicated to that device, that is, to manufacture it as a one-of-a-kind product. Therefore, in Patent Documents 1 to 5, attention is paid to that field of control, and the inventions are made in consideration of the versatility in that field rather than algorithms in general. Note that in Patent Documents 6 and 7, they are inventions for efficient searching and efficient compression in terms of data structure.

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0013] The problem to be solved is that each processing program can support all algorithms without changing the program just by changing each piece of processing data, but a contradiction occurs in setting the storage area for each piece of processing data for each process. That is, if the area is set, an increase in a certain piece of processing data may cause it to span into another processing area, making it impossible to support all algorithms. Also, taking a large area will result in wasted memory areas.

[0014] Furthermore, another problem to be solved is that for processing data consisting of arbitrary numbers of rows and columns, when the processing data is executed by a processing program row by row and the processing content to be executed requires repetition or branching, the maximum number of repetitions needs to be incorporated in advance to create the rows of the processing data. That is, when the algorithm is determined, the maximum value of the number of repetitions can be determined, but it cannot be determined to support all algorithms. Similarly, for processes where the number of processing data changes row by row, the maximum value of the maximum number cannot be determined. Also, the memory for the part less than the maximum value becomes a wasted memory area.

[0015] Furthermore, the problem to be solved is that the programmable logic controller (PLC) for writing programs to handle various algorithms and the engineering tool for writing and controlling programs in the programmable logic controller (PLC) are separate. Moreover, even the connection cable for connecting the programmable logic controller (PLC) and the engineering tool is different for each manufacturer of the programmable logic controller (PLC), so it was impossible to respond promptly on-site. However, in recent years, although the engineering tool has become a software on a personal computer (PC) or an attempt has been made to standardize the connection cable, conversely, problems such as inability to respond due to different versions have also occurred. Additionally, depending on the external touch panel (TP), functions such as adding a memory later have been added so that programs can be added, modified, or deleted, but this is only an auxiliary function after all.

[0016] Furthermore, the problem to be solved is that in order to handle various algorithms, a program tailored to individual algorithms needs to be created, and if necessary, data and constants must be written into the programmable logic controller (PLC) to make the created program executable. Therefore, program files, data files, comment files, etc. are also required, and each time a program is created for individual algorithms, all of them must be managed.

[0017] Furthermore, even when the algorithms are the same, the instruction words and description methods are different for each manufacturer of the programmable logic controller (PLC). Therefore, it is necessary to understand the differences in instruction words and description methods for each manufacturer.

[0018] Furthermore, the problem to be solved is that when adding or deleting a program during program execution, if the program is converted into a format directly executable by a microprocessor (MPU, Micro Processing Unit), the program may automatically become larger or smaller. As a result, depending on where the current execution program is being executed, the program may not be executed reliably. Even when executed by watching the monitor, there is a time lag in the monitor itself, and the program may not be executed reliably. That is, the problem lies in the fact that the size of the program is being changed.

[0019] Furthermore, the problem to be solved is that the number of characters in the comments managed in the comment file is generally fixed, and it is not easy to increase the number of characters in the comments. Although comments can be written to the microprocessor (MPU) of a programmable logic controller (PLC), there are limitations, and since they have to be written each time, there is a risk of forgetting, which is troublesome.

[0020] Furthermore, the problem to be solved is that for different programs for each manufacturer of programmable logic controllers (PLCs), the instruction words of the program are designed based on the assembly language of the microprocessor (MPU), which is a low-level (lower) language that is closest to machine language among the programming languages that humans can practically use. Therefore, numerical values such as addresses and instruction words are generally difficult to understand. For this reason, various notes and comments are set at the expense of the form of a separate file or program capacity, but there is no common writing method and they are free, which conversely hinders understanding.

[0021] Furthermore, the problem to be solved is that because the freedom of the program creator is too great, it is difficult to easily understand whether the coils and contacts are physically determined, whether they are replaced coils and contacts, or whether the contacts and coils are only necessary for the connections within the program. Also, since all devices can be freely selected, using replaced coils and contacts or the program creator using them appropriately according to the application further complicates understanding. In addition, when constructing a program hierarchically, if the definition of the hierarchy becomes ambiguous, it further makes understanding difficult. For example, the interlock processing may not be placed in the same hierarchy, or conversely, the same interlock processing is performed in all hierarchies, making the program complex and difficult to understand. That is, because information can be freely entered into the program according to the mood and way of thinking of the program creator, it is also one of the factors for the program to be different for each program creator. In a more developed form of this problem, it also hinders complete modification and change when a person other than the program creator modifies or changes the program. Moreover, because complete modification and change cannot be done, forced addition is carried out, further complicating the program.

[0022] Furthermore, the problem to be solved is that in recent years, as technological innovation has advanced and the role of electrical control has become more significant, along with the program becoming large and complex, machine designers and plant designers must convey the design intent, key points, and ideas to the program designer, and it takes a lot of time to make them understood.

[0023] Furthermore, the problem to be solved is that in recent years, because the program has become large and complex, program designers often design with multiple people, taking a lot of time to convey the design intent, key points, and ideas, and the probability of leakage of the secrets included in the intent, key points, and ideas has been increasing.

[0024] Furthermore, the problem to be solved is that as display devices such as touch panels (TPs) and displays controlled by personal computers (PCs) as interfaces, the screen size, resolution, specifications, and character size also vary. Therefore, depending on what kind of display is used, what character size is set, and the data control specifications, when creating a large amount of data, a large number of screens must be created.

[0025] Furthermore, the problem to be solved is the nature of the digital structure, which is that programs can be easily replicated. In recent years, there are many programs that distribute programs into multiple files for each role. Although increasing the opportunity to use files by only changing the address adds the advantage of improving the reliability of the program with the file structure of that function, from the perspective of machine designers and plant designers, the design man-hours of the program are different from the actual design man-hours of the program. Therefore, depending on whether the manual of the controlled device was read to construct the program or it was a program created once, the man-hours are significantly different and it becomes expensive. Also, from the perspective of the manufacturer of programmable logic controllers (PLCs), even if the reference program is modified or changed, it is difficult for the modification or change to be reflected. That is, the accurate design cost cannot be defined. Also, it is difficult to easily modify or change the reference program.

[0026] Furthermore, the problem to be solved is that manufacturing devices that control connected devices and apparatuses have a high level of confidentiality. In general factories, outsiders are prohibited from entering and the manufacturing devices are not shown. Therefore, when using a manufacturing device manufacturer different from the first unit, there may be cases where the design intent, key points, and contrived parts are replicated inexpensively. Therefore, although a process to prohibit replication is performed using passwords, in general factories, since outsiders are prohibited from entering, the analysis process is carried out over time and illegal replication is taking place.

Means for Solving the Problem

[0027] The first aspect of the present invention is that there are a plurality of pieces of processing data consisting of an arbitrary number of rows and an arbitrary number of columns. Based on a plurality of pieces of processing data, and further based on one piece of processing data among the plurality of pieces of processing data, and further based on one row among that one piece of processing data, the microprocessor (MPU) or CPU executes processing according to the purpose, then moves to the next row and executes processing. When the rows are exhausted, it returns to the first row and continues to execute processing. The processing data of the program is In addition to the processing data of that row, the start address of the next row and the start address of the previous row are added to the processing data of that row. Furthermore, when the number of data in the processing data of one row is variable, the variable number of data is added to the processing data of that row. Furthermore, when the processing content to be executed in one row is repeated or requires branching, the repetition data and the processing data for the processing data to be repeated or branched are added to the processing data of that row. It is a data structure characterized by this.

[0028] The first aspect of the present invention is illustrated by showing the relationship of the data structure with processing data, transfer data, repetition data, and number data in FIGS. 4, 8 to 13, 16 to 20, 38 to 47, 57, and 58.

[0029] The second aspect of the present invention is a program for causing a microprocessor (MPU) or CPU to execute processing according to the purpose based on the data structure described in the first aspect of the present invention. The plurality of said processing data are For each row, the processing data of the input device data processing that compares the device data and changes the result to the ON / OFF state of the general-purpose bit for execution, and For each row, the processing data of the input processing that takes in the physically arranged input bits and changes the ON / OFF state of the general-purpose bit for execution, and For each row, when the logical product or logical sum of a plurality of general-purpose bits output from other processing becomes true, the processing data of the logical processing that replaces it with the ON / OFF of the general-purpose bit for execution, and For each line, based on the general-purpose bits output from other processes, shift the ON state of the general-purpose bits to transfer, transmit, and execute the execution state of the process to other lines or lines of other processes. The processing data of the sequential step-by-step process, and For each line, the processing data of the device data arithmetic processing that operates the arithmetic function provided in the microprocessor (MPU) or CPU with device data or device bits as specified, and For each line, the processing data of the output processing that changes the ON / OFF state of the physically arranged output bits based on the general-purpose bits output from other processes, and Among the processing data of the timing processing that changes the ON / OFF state of the general-purpose bits over time for each line, including at least one piece of processing data, and To execute the above processing, replace the selections required for the processing with numerical values of the processing data, use the address of the general-purpose bit as the processing data, write the processing data to a plurality of modification registers and use it to execute the processing of that line, and then move to the next line to execute the processing. When the lines are exhausted, return to the first line and continue executing the processing. A program characterized by this.

[0030] The second aspect of the present invention is illustrated as a ladder program in FIGS. 23 to 34 and FIGS. 48 to 54, as an overall configuration in FIGS. 55 and 56, and as all flowcharts in FIGS. 64 to 84.

[0031] The third aspect of the present invention is an interface processing program that uses a touch panel (TP) or a PC as an interface for operating each processing data of the program described in the second aspect of the present invention. When a display memory area for the display part corresponding to each processing data described in the second aspect of the present invention is secured in a microprocessor (MPU) or CPU, the display memory area is used to create, delete, add, and change the processing data. It is an interface processing program characterized by being included in the program on the touch panel (TP) or PC side, or further included in the program described in the second aspect of the present invention.

[0032] The third of the present invention is illustrated in FIG. 59.

[0033] The fourth of the present invention is an identification and initial processing program that performs identification processing when the power supply is turned on or reset, and controls and stabilizes the processing state to the initial state. Before the identification and initial processing program is written into a microprocessor (MPU) or CPU, unique physical unique data is written into the identification and initial processing program. During the identification process, the written data is compared with the unique physical unique data of the read microprocessor (MPU) or CPU. If they do not match, the ON / OFF state of the general-purpose bits is changed, and the identification and initial processing program further includes transmitting a prohibition instruction to the programs of each process described in the second of the present invention. Based on the prohibition instruction of the identification and initial processing program, a program that does not execute each process described in the second of the present invention is incorporated into the program of each process, which is characterized by the program described in the second of the present invention.

[0034] The fourth of the present invention is illustrated in FIG. 60.

Effect of the Invention

[0035] The effect of the present invention is that each process is performed with processing data in units of execution of the process. With a plurality of processing data consisting of arbitrary rows and columns, each process adds or deletes processing data in row units. In addition to the processing data of that row, the start address of the next row and the start address of the previous row are added to the processing data of that row. Therefore, a plurality of processing data can be mixed in row units, and even if processing data is added, it does not span other processes. That is, the algorithm can be easily added or deleted without worrying about the area where it can be added.

[0036] Furthermore, in order to execute processing in units of rows using row unit processing data and perform addition or deletion of processing data in units of rows, in addition to the processing data for that row, by adding the start address of the next row and the start address of the previous row to the processing data for that row, and further adding a count in addition to the processing data, it becomes unnecessary to fix the size of the row in the processing unit, and it is possible to incorporate a variable number of data. Similarly, by adding repetitive data and its repetitive processing data in addition to the processing data, a repetitive structure can be incorporated within a row. That is, it is possible to handle further changes to the algorithm.

[0037] Furthermore, when constructing a program that reflects an algorithm, which is a procedure or calculation method for solving problems, in a programmable logic controller (PLC), without converting it into a form directly executable by the microprocessor (MPU) of the programmable logic controller (PLC), by changing the processing data, the program can be constructed or changed. Therefore, when the programmable logic controller (PLC) is connected by a connection cable to an input / output device such as an external touch panel (TP) or a personal computer (PC) equipped with a standard input screen, by simply changing the data of the standard input screen, it is possible to handle the construction and change of the program without the need for engineering tools. Also, even if it does not have a standard input screen, depending on the manufacturer, since there is a function to change device data from the touch panel (TP) side, it can also be changed without the need for engineering tools.

[0038] Furthermore, as a method of constructing or changing a program, since only the processing data is added, deleted, or changed, the program file becomes unnecessary and file management becomes easier. However, depending on the manufacturer, some touch panels (TPs) that are connected to input / output devices such as external touch panels (TPs) or personal computers (PCs) via connection cables rather than engineering tools have the function of reading and writing programs. However, since there are limitations such as the need for an external memory, new problems also arise.

[0039] Furthermore, since the instruction words and the formats of numerical values used differ among the manufacturers of programmable logic controllers (PLCs) that create programs, it is possible to absorb the differences among the companies. That is, in the same factory, even if the devices are made by different manufacturers, when they are connected via connection cables to input / output devices such as external touch panels (TPs) or personal computers (PCs), since the screens are tables with the same structure, the differences among the companies are reduced.

[0040] Furthermore, even when changing, adding, or deleting during program execution, since the program is not converted into a format directly executable by the microprocessor (MPU) of the programmable logic controller (PLC) and written, mistakes may be made in deleting the initial settings of loop structures (For~Next statements), etc., or mistakes may be made in the addresses or labels of jump structures (such as subroutine calls, unconditional jumps, and conditional jumps), resulting in the program not stopping. That is, because the program structure is not changed. However, depending on the manufacturer, syntax checks are also performed, for example, when the program is converted into a format directly executable by the microprocessor (MPU) of the programmable logic controller (PLC). However, since it is possible to slip through even that process and, depending on the usage method, it is necessary to bypass the check of that process, rarely, the program may stop.

[0041] Furthermore, since comments are not managed in units of the maximum number, the memory capacity of comments is not wasted. However, currently, since the comment file is separate from the program file in many manufacturers, it is necessary to change the structure of comments on the manufacturer side. Additionally, depending on the touch panel (TP) manufacturer, it is best to use the comments on the touch panel (TP) side. However, since comments on the touch panel (TP) side cannot be written from the screen, a change in its structure is also necessary.

[0042] Furthermore, by making comments into device data, the biggest drawback of this invention alone is that it consumes a large amount of data memory. However, although comments can be written to the microprocessor (MPU) of the programmable logic controller (PLC), there are limitations, and since it is no longer necessary to write each time, the annoyance is eliminated.

[0043] Furthermore, as a method of constructing or changing a program, when only using processing data and connected by a connection cable to an input display device such as an external touch panel (TP) or a personal computer (PC), since a table is used on the screen, it is visually easy to understand.

[0044] Furthermore, as a method of constructing a program, by performing it only with processing data, generally, when designing a program for a large device, in order to construct a hierarchical structure, the hierarchical structure can be divided according to the judgment of the program designer, preventing differences in the hierarchical structure depending on the person. Also, even when someone other than the program designer changes the program, since the screen is represented as a table, the changed location can be seen at a glance.

[0045] Furthermore, in recent years, with the progress of technological innovation and the increasing role of electrical control, the programs have become larger, making it impossible for mechanical designers or plant designers to design them single-handedly. They have to convey the design intent, key points, and ideas to program designers with program knowledge. However, if new employees within the organization who have no program knowledge, to whom mechanical designers or plant designers belong, are asked to input based on the design flowchart, time can be saved, new employees can understand the equipment and devices, and confidentiality can be maintained.

[0046] Furthermore, by creating a display memory, the display devices controlled by a touch panel (TP) or a personal computer (PC) have various screen sizes, resolutions, specifications, and character sizes. They vary depending on the type of display used, the character size selected, and the specifications of the device or factory, so they can have versatility.

[0047] Furthermore, by storing the unique physical data of a programmable logic controller (PLC) and controlling whether to execute it or not from the program side using that programmable logic controller (PLC), it can be made executable only by changing the program. Therefore, combined with the ability to control the program through data input, security permissions such as passwords can regain their true meaning, and the rights of the program can be protected even in a space where manufacturing equipment vulnerable to unauthorized entry by outsiders is placed.

[0048] That is to say, although it is a programmable logic controller (PLC), algorithms can be constructed or changed simply by changing the data without changing the program. In short, it can be said to be a data table logic controller (DLC), or a data table controller (DC).

[0049] (Description of drawing classification) Before the brief description of the drawings, since the drawings cover from Figure 1 to Figure 115 and some span multiple drawings, the classification will be described. Figures 1 to 3 are the basic drawings of a general embodiment according to the present invention. Figure 4 is a memory tree diagram of an embodiment according to the present invention. Figures 5 to 54 are related drawings for driving two motors in an embodiment according to the present invention. The detailed classification will be further described with two blank characters inserted below. Figures 5 to 6 are the basic drawings for driving two motors in an embodiment according to the present invention. Figures 7 to 13 are data diagrams related to initial settings in an embodiment according to the present invention. Figures 14 to 20 are data diagrams related to each process for driving two motors in an embodiment according to the present invention. Figures 21 to 23 are ladder program circuit diagrams of input processing in a general embodiment according to the present invention. Figures 24 to 27 are ladder program circuit diagrams of logical processing in a general embodiment according to the present invention. Figures 28 to 30 are ladder program circuit diagrams of output processing in a general embodiment according to the present invention. Figures 31 to 34 are ladder program circuit diagrams of timing processing in a general embodiment according to the present invention. Figure 35 is a ladder program circuit diagram with specification changes for driving two motors in a general embodiment according to the present invention. Figures 36 to 47 are data diagrams related to each process with specification changes for driving two motors in an embodiment according to the present invention. Figures 48 to 54 are ladder program circuit diagrams of sequential step operation / processing in a general embodiment according to the present invention. Figures 55 to 62 are basic conceptual drawings of an embodiment according to the present invention. From Figure 63 to Figure 84 are program flowcharts of each process and the like of one embodiment according to the present invention. The following further describes the detailed classification with two blank characters inserted at the beginning. From Figure 63 to Figure 66 are program flowcharts of the initial setting, the minute reset of the time measurement process, the start of each process with the same structure, and the minute reset of each process with the same structure of one embodiment according to the present invention. From Figure 67 to Figure 69 are program flowcharts of starting the execution of the process for each number of the first half of three processes of one embodiment according to the present invention. From Figure 70 to Figure 73 are program flowcharts related to the interface process of one embodiment. From Figure 74 to Figure 76 are program flowcharts related to the logical process of one embodiment. From Figure 77 to Figure 79 are program flowcharts related to the sequential step - by - step process of one embodiment. Figure 80 is a program flowchart of the output process of one embodiment. From Figure 81 to Figure 84 are program flowcharts related to the time measurement process of one embodiment. From Figure 85 to Figure 115 are data setting diagrams of all processes set as a specific servo - press device of one embodiment according to the present invention. The following further describes the detailed classification with two blank characters inserted at the beginning. Figure 85 and Figure 86 are data setting diagrams of the input device data process and the device data calculation process (input standard) of one embodiment. Figure 87 and Figure 88 are data setting diagrams of the input process of one embodiment. From Figure 89 to Figure 100 are data setting diagrams of the logical process of one embodiment. Figure 101 is a data setting diagram of the sequential step - by - step operation of one embodiment. From Figure 102 to Figure 105 are data setting diagrams of the sequential step - by - step process in the origin return operation of one embodiment. Figure 106 and Figure 107 are data setting diagrams of the sequential step - by - step process in the press operation of one embodiment. From Figure 108 to Figure 113 are data setting diagrams of device data arithmetic processing (output standard) in one embodiment. Figure 115 and Figure 116 are data setting diagrams of output processing and timing processing in one embodiment.

Brief Description of the Drawings

[0050]

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Embodiments for Carrying Out the Invention

[0051] (Summary Supplement 1) Generally, when a program is created according to an algorithm, it is executed. If the execution result is NG, the program is corrected. If the execution result is OK, there is no need for correction, and finally, a program that continuously repeats execution is completed. The present invention is completed by setting data conforming to an algorithm in an already created program, which is then executed. If the execution result is NG, the data is changed. If the execution result is OK, the data is not changed, and finally, data that continuously repeats execution is completed, thereby realizing the algorithm. There are various complex algorithms for the algorithm itself, such as parallel algorithms, sequential algorithms, parallel and sequential, sequential and parallel. A data structure corresponding to all of them was required, but it is realized by the first aspect of the present invention. The first aspect of the present invention is data composed of rows and columns. Based on the data in one row, one program is executed. When the last row is executed, it returns to the beginning and repeats the execution of the program. In order to mix data with different execution purposes in units of rows, the starting address of the next execution row and the starting address of the previously executed row (in order to delete the next row) are added to the data, so that data with the same execution purpose can be searched and executed in the order arranged in rows. Also, when the number of data in one row is variable or when iterative processing is performed within one row, it is realized by adding the starting address of the next execution row and the starting address of the previously executed row (in order to delete the next row) to the data. However, when changing, if the number of data in that row becomes smaller, a simple change is sufficient. But if the number of data becomes larger, a new area is required, and it is necessary to rewrite the starting address of the previous row that designates that row. Note that the address rewriting may be performed automatically by a program or manually. Furthermore, inevitably, useless areas that are not used will occur, but it can be dealt with by adding a memory cleaning program. Based on the experience of constructing programmable logic controller (PLC) program software for many years, as long as there is no complicated rewriting, there should be no significant waste.In this way, it can be said that new extensibility has been obtained by performing each of the multiple processes on a line-by-line basis, regardless of which process is being extended. That is, this data structure is a structure that can accommodate all algorithms.

[0052] (Summary Supplement 2) Also, in the production of a program, usually, an initial setting program is written from the beginning of the program area, followed by a processing program according to the algorithm, and finally, an output processing program is written (excluding subroutine processing) to declare the end of the program. The processing program according to the algorithm is realized by the second aspect of the present invention. Generally, the program is divided by work item (manual, automatic, home return, etc.), and within each program, while creating bits, devices, etc. with connections and meanings for each process (step, step, etc.), it is comparable to the structured sequential step processing of the second aspect of the present invention. The general reason for not structuring is that it is difficult to recognize the situation at a glance, making debugging difficult, and because the program is not frequently changed. In the second aspect of the present invention, furthermore, input device data processing, input processing, logical processing, device data arithmetic processing, output processing, and timing processing are provided. Generally, it is often not structured, and even when partially structured, the results are not replaced with unified bits but are directly described at the necessary positions. Since the results are not replaced with unified bits, it may seem that there is no waste, but because it is not a simple replacement, it is also the biggest factor causing the program to become complex. In addition, for a programmer, although it is an important element that can assign the creator's own meaning to the address, such as making it odd or even, a multiple of the sequence, or a multiple of 10, and play a supplementary role for comments with limitations, usually, since the numerical value itself has no meaning, when dealing with it through an interface, it is also possible to promote the understanding of whether it conforms to the algorithm by displaying comments without limitations for the numerical value.

[0053] (Summary Supplement 3) In recent years, in systems that use a programmable logic controller (PLC), as an interface for a person to interact with equipment, a touch panel (TP) or a personal computer (PC) (including engineering tools here) is used, and communication is utilized to perform settings such as various data, and a system has been constructed that can change the actual address of the programmable logic controller (PLC). Usually, since a programmable logic controller (PLC), a touch panel (TP), or a personal computer (PC) (including engineering tools here) is also assumed to be a dedicated machine, there is no need to have a display memory area. However, as in the present invention, in order to support various algorithms or because there are various sizes for the touch panel (TP) or the personal computer (PC) as well, as a buffer function of the memory, and also by changing only a part of a row and making the row into complete processing data, it is realized by the third aspect of the present invention. Furthermore, for the touch panel (TP), a basic screen corresponding to the size of the screen can be provided in combination with the program of the present invention, and for the personal computer (PC), the program itself can be provided in combination with the program of the present invention, which can further promote its popularity.

[0054] (Summary Supplement 4) If this all-algorithm-compatible program is obtained, there is no longer a need to create a program. Therefore, if it is copied and transplanted to a different CPU, due to the nature of the factory, it is not known whether the CPU is running with a copy. The fourth aspect of the present invention is a device for preventing the program from starting. For this, it is a major premise that a general password system that cannot change the program at least is incorporated into the system of the programmable logic controller (PLC) in advance, and the fourth aspect of the present invention can function reliably.

[0055] Hereinafter, embodiments of the present invention will be described together with the accompanying drawings. (Pre-concept) Figure 1 is an electrical control equipment diagram of a general embodiment. It can be said that all equipment or devices except those using classical wind power or hydraulic power are electrically controlled. Among them, control using a rewritable computer has become widespread. Such computers include microcontrollers, personal computers (PCs), programmable logic controllers (PLCs), etc., and the equipment is controlled by taking advantage of their features. However, with the remarkable technological progress these days, factors such as the emergence of optical fibers, the speeding up of CPUs, microprocessors (MPUs), or GPUs (Graphics Processing Units), the exponential increase in the capacity of memory elements, the miniaturization of each electronic component, the multi-layerization of substrates, and the fine processing technology of line widths have made their features flat, and the boundaries are becoming unclear. Based on the above, Figure 1 is an electrical control equipment diagram of a general embodiment. The part surrounded by a dashed line is equipment or a device. A is the equipment or device of Company A, B is the equipment or device of Company B, C is the equipment or device of Company C, D is the equipment or device of Company D, and E is the equipment or device of Company E. Each company is connected by a thick-line network 5. In a large factory, an optical fiber is used for the backbone network to support high-speed and large-capacity communication. However, there are also networks closed within the equipment or device, and the communication cable is not an optical fiber, and coaxial cables, multi-core cables, etc. are still used. 1 is a programmable logic controller (PLC), 2 is a touch panel (TP), 3 is a personal computer (PC), and 4 is an engineering tool. It is easier to manage if the programmable logic controller (PLC) of 1 and the touch panel (TP) of 2 have the same manufacturer and model, but there are also many cases where this is not so. Note that the personal computer (PC) of 3, the engineering tool of 4, and the touch panel (TP) of 2 are also man-machine interfaces.

[0056] (Pre-concept) Figure 2 is a flowchart diagram including each program of a programmable logic controller (PLC) according to a general embodiment of the present invention and processes associated with the programs. The programmable logic controllers (PLCs) of each company do not have much difference and have almost the same specifications and operations. The flowchart diagrams including each program and processes associated with the programs are also almost the same. At 20 in Figure 2, when the power is turned from OFF to ON, or from STOP to RUN, the programmable logic controller (PLC) starts up. First, the program check process at 21 is performed. Subsequently I / O refresh at 22 is performed, and the process proceeds to END process 1 at 23. Then, the group of initial execution type programs at 25 created by the user is executed in the specified order, and the process proceeds to END process 2 at 24. Subsequently, I / O refresh at 22 is performed, the process proceeds to END process 1 at 23, the group of scan execution type programs at 26 created by the user is executed in the specified order, the process proceeds to END process 2 at 24, returns before I / O refresh at 22, and is repeated until the power is turned from ON to OFF, or from RUN to STOP. The reason why END process is divided into END process 1 at 23 and END process 2 at 24 is that depending on the instructions described in the program, there are some instructions that require processing to be performed before the program to be described. Without that instruction, only END process 2 at 24 would be sufficient. The group of fixed - cycle execution type programs at 27 and the group of standby type programs at 28 are independent programs and are not executed in order. The fixed - cycle execution type program executes the program at a fixed cycle. The standby program is executed each time it is called from each program. Note that depending on the model, there are also event execution type programs with a width in the trigger element, which are similar programs to the standby program. The dashed lines indicate that interrupts are inserted or calls are made within the normal repetition.

[0057] (Pre - concept) Figure 3 is a relational diagram of each program of a general programmable logic controller (PLC) according to an embodiment of the present invention. Although the 30 initial execution type program group and the 31 scan execution type program group in Figure 3 are separated by [END / FEND], they are continuous and can be regarded as one program. Depending on the model of the programmable logic controller (PLC), there are even cases where there is only one program without being divided into the 30 initial execution type program, the 31 scan execution type program, the 32 fixed cycle execution type program, and the 33 standby program. In the early programmable logic controllers (PLCs), there were only a few types of fixed cycle execution type programs, which were handled with fixed cycle interrupt pointers. Specifically, an interrupt pointer was created, and the circuit of that pointer was activated periodically, and the [IRET] (interrupt return instruction) was used to return to normal processing. Also, the method of using the standby program as a subroutine with the pointer as the destination is equivalent. Furthermore, when the power is turned from OFF to ON or from STOP to RUN, the initial execution type program that is executed only once can achieve an equivalent function by using a conditional jump combined with a system flag that is ON only for the first scan and a system flag that is OFF only for the first scan, and a pointer that is the destination of an unconditional jump. So, why? The reason for grouping programs is nothing but to use the programs as assets many times, improve reliability, reduce design man-hours, and make it easier for program creators, maintenance personnel, and others to understand. Even in the present invention, although the programs are classified in units of processing, it has little meaning for users of the programs other than program creators, maintenance personnel, and evaluators.

[0058] Figure 4 is a memory tree diagram according to an embodiment of the present invention. It is a memory tree diagram that is subdivided from left to right. The name of the memory changes depending on the position from which the memory is viewed. Figure 4 shows the memory names as seen from a programmable logic controller (PLC) incorporating the program of the present invention. The memory is divided into the memory inside the PLC and the memory outside the PLC (external memory). One of the memories inside the PLC is further divided into the memory inside the CPU and the memory outside the CPU (buffer memory of each unit). Both are further divided into ROM (Read Only Memory) and RAM (Random Access Memory). The memory outside the CPU varies depending on the specifications of each unit, but both the ROM and the RAM serve as the buffer memory for each unit. The ROM inside the CPU is divided into a program memory for storing programs and a data memory. The RAM inside the CPU is divided into seven types: program cache memory, device memory, label memory, function memory, refresh memory, CPU buffer memory, and signal flow memory. This is the general configuration so far. In Figure 4, the device memory is divided into 12 (device file memory, device link relation memory, device system relation memory, device timer / counter memory, device general-purpose memory, device latch bit memory, device link relation bit memory, device system relation bit memory, device timer / counter bit memory, device input bit memory, device output bit memory, device general-purpose bit memory), but it varies depending on the specifications of each company. Note that a part of the general-purpose device memory is allocated to the processing data, transfer data, repetitive data, and count data of the present invention. Note that the memories that can be addressed by the program are generally the buffer memory of each unit, the CPU buffer memory, and the device memory, and the other memories cannot be accessed from the program side.

[0059] Figure 5 is a ladder program circuit diagram for driving two motors according to a general embodiment of the present invention. The input bits and output bits are in the device input bit memory and device output bit memory of Figure 4, and the addresses are hard - determined. Also, the system bits are in the device system - related bit memory, which is assigned by the manufacturer. Furthermore, the timer bits are in the device timer / counter bit memory, and the user can freely select the addresses. Note that the device timer / counter memory corresponds to the device timer / counter bit memory and stores the set values. It is for understanding the program of the programmable logic controller (PLC) itself and the gist of the present invention, and it is a program for driving two star - delta starting motors. Star - delta starting means that for a three - phase motor with a large capacity, since the starting current is large, first, the motor is slowly driven in star connection, and after a certain time, it is switched to delta connection with a low current. Here, since the two motors cannot be driven in star connection simultaneously, while one is in star starting, the starting switch of the other non - running motor is disabled so that it cannot start in star. Also, there is a starting lamp for each motor. When starting in star connection, it blinks at intervals of 0.5 seconds, and when switched to delta connection, it lights up. For such small - scale control, instead of using a programmable logic controller (PLC) that can successively build input / output units, etc., it is common to create a relay - sequence circuit for one motor, which consists of three relays and two time - delay relays (timer - relays), or to use a small programmable logic controller (PLC) with an integrated input / output circuit. However, assuming that another device is added later and a general programmable logic controller (PLC) is used for controlling that device, this configuration is adopted. In the ladder program circuit diagram of Fig. 5, it consists only of A contacts, B contacts, and coils. The signal from the input unit is used as the input bit, the coil output by the output unit is used as the output bit, the timer built into the programmable logic controller (PLC) is used as the timer bit, and the 1-second clock built into the programmable logic controller (PLC) is used as the 1-second clock system bit. Note that the PB1 input bit is the start switch of motor 1, the PB2 input bit is the stop switch of motor 1, the TH1 input bit is the thermal trip signal of motor 1, the PB3 input bit is the start switch of motor 2, the PB4 input bit is the stop switch of motor 2, the TH2 input bit is the thermal trip signal of motor 2, the EMS input bit is the emergency stop switch, the MC1 output bit coil is the coil that drives the star start of motor 1, the MC2 output bit coil is the coil that drives the delta start of motor 1, the PL1 output bit drives the start indicator lamp of motor 1, the MC3 output bit coil is the coil that drives the star start of motor 2, the MC4 output bit coil is the coil that drives the delta start of motor 2, and the PL2 output bit drives the start indicator lamp of motor 2.

[0060] The following is a detailed description of each block. For 50, the MC1 output bit coil is self-held when the start switch is pressed and remains self-held and activated when the stop switch is pressed, a thermal trip signal is input, the emergency stop is pressed, the switching time is being measured, or motor 2 is not in star start. For 51, when the TM1 timer bit coil is continuously driven during star start, the measurement of the TM1 timer bit coil starts, and when the set time of 100 seconds is reached, it is self-held and remains self-held and activated if the stop switch is not pressed, a thermal trip signal is not input, or the emergency stop switch is not pressed. For 52, the MC1 output bit coil is activated by delta start in accordance with the activation of the TM1 timer. For the PL1 output bit coil of 53, during star startup, it repeatedly activates and deactivates every second, and during delta startup, it remains activated. For the MC3 output bit coil of 54, self - holding is applied when the start switch is pressed, and self - holding continues and it remains activated when the stop switch is pressed, a thermal trip signal is input, an emergency stop is pressed, during switching time measurement, or when not in star startup of motor 1. For the TM2 timer coil of 55, when continuously driven during star startup, the measurement of the TM2 timer starts. When it reaches the set time of 150 seconds, self - holding is applied, and self - holding continues and it remains activated if the stop switch is not pressed, a thermal trip signal is not input, and the emergency stop switch is not pressed. For the MC4 output bit coil of 56, it is activated during delta startup in accordance with the activation of the TM2 timer bit coil. For the PL2 output bit coil of 57, during star startup, it repeatedly activates and deactivates every second, and during delta startup, it remains activated. With the structure instruction END, the program file is terminated.

[0061] For the ladder program circuit diagram of FIG. 5 to drive two motors, in order to exactly match it using the present invention, the data is required. From FIG. 6 to FIG. 20, a general - purpose device memory map, an image data diagram of initial settings, a detailed data diagram of initial settings, an image data diagram of each process, and a detailed data diagram of each process for driving two motors are described. Since it can support all algorithms, it is not limited to only driving two motors. However, the ladder program circuit diagrams of input processing, logical processing, output processing, and timing processing used for driving two motors are described in FIGS. 21 to 34.

[0062] FIG. 6 is a general - purpose device memory map for driving two motors according to an embodiment of the present invention. Using the device general-purpose memory and the device general-purpose bit memory in FIG. 4, the area of the device general-purpose memory has the initial settings for screen processing from 1800 to 1819, the initial settings for input device data processing from 1820 to 1839, the initial settings for device data arithmetic processing from 1840 to 1859, the initial settings for input processing from 1860 to 1879, the initial settings for logical processing from 1880 to 1899, the initial settings for sequential step operation / processing from 1900 to 1939, the initial settings for output processing from 1940 to 1959, the initial settings for timing processing from 1960 to 1999, and the program data area from 2000 onwards. The area of the device general-purpose bit memory has the general-purpose bits generated by the program starting from 0. Note that the numerical values are addresses, which are provisional and arbitrarily set.

[0063] FIG. 7 is an image data diagram displayed on the interface of the initial settings of one embodiment according to the present invention. Since touch panels (TP), engineering tools, and personal computers (PC) come in various sizes, the initial settings of input processing, logical processing, output processing, and timing processing, as well as the initial settings of the modified sequential step operation and sequential step processing required to drive two motors, are shown in the image data diagram displayed on the interface. The numerical values are variables and can be changed, but are substantially fixed in content. 70 is the initial setting (input processing) data, 71 is the initial setting (logical processing) data, 72 is the initial setting (output processing) data, 73 is the initial setting (timing processing) data, 74 is the initial setting (sequential step operation) data, and 75 is the initial setting (sequential step processing) data.

[0064] FIG. 8 is a detailed data diagram of the initial settings of the input processing of one embodiment according to the present invention. On the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Similarly, below the horizontal double line, the items of TP / PC display, value, address, and memory type are described. Although it is the 70 initial setting (input process) data in Fig. 7, the first one on the right side of the double vertical line, the number of input processes, is not in the 70 initial setting (input process) data in Fig. 7. After the change, it is described at the beginning of the 360 input process data in Fig. 36 and at the beginning of the 140 input process data in Fig. 14. The lower side of the double horizontal line is the data of each item, which is sequentially assigned from the address 1860 described in Fig. 6. The reason why there is no TP / PC display in the second item on the right side of the double vertical line is that it is automatically assigned by the program. Although the memory type shows external, process, and transition, external refers to the memory outside the PLC described in Fig. 4, process refers to the process data (memory) of the device general-purpose memory described in Fig. 4, and transition refers to the transition data (memory) of the device general-purpose memory described in Fig. 4. The first interval refers to the size of the device selection in Fig. 14, 140 and the size of the device selection in Fig. 15. The subsequent ones in each figure also correspond sequentially.

[0065] Fig. 9 is a detailed data diagram of the initial setting of the logical process in an embodiment according to the present invention. On the left side of the double vertical line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Similarly, on the lower side of the double horizontal line, the items of TP / PC display, value, address, and memory type are described. It is the 71 initial setting (logical processing) data in Fig. 7. However, for the first one on the right side of the vertical double line, the number of logical processings is not in the 71 initial setting (logical processing) data in Fig. 7. After the change, it is described at the beginning of the 361 logical processing data in Fig. 36, instead of at the beginning of the 141 logical processing data in Fig. 14. Below the horizontal double line are the data of each item, which are sequentially assigned starting from the address 1880 described in Fig. 6. The reason why there is no TP / PC display in the second item on the right side of the vertical double line is that it is automatically assigned by the program. Note that although the memory types of external, processing, transition, and repetition are displayed, "external" refers to the memory outside the PLC described in Fig. 4, "processing" refers to the processing data (memory) in the device general-purpose memory described in Fig. 4, "transition" refers to the transition data (memory) in the device general-purpose memory described in Fig. 4, and "repetition" refers to the repetition data (memory) in the device general-purpose memory described in Fig. 4. Note that the first interval refers to the sizes of the general-purpose bit addresses in Figs. 14 and 141 and the size of the general-purpose bit address in Fig. 16. The subsequent parts in each figure also correspond sequentially.

[0066] Fig. 10 is a detailed data diagram of the initial setting of the output processing according to an embodiment of the present invention. On the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Similarly, below the horizontal double line, the items of TP / PC display, value, address, and memory type are described. It is the 72 initial setting (output process) data in FIG. 7. However, for the first one on the right side of the double vertical line, the number of output processes is not in the 72 initial setting (output process) data in FIG. 7, but at the beginning of the 142 output process data in FIG. 14. After the change, it is described at the beginning of the 371 output process data in FIG. 37. Below the double horizontal line are the data of each item, which are sequentially assigned starting from the address 1940 described in FIG. 6. The reason why there is no TP / PC display in the second item on the right side of the double vertical line is that it is automatically assigned by the program. Note that although the memory type shows external, process, and transition, external refers to the memory outside the PLC described in FIG. 4, process refers to the process data (memory) in the device general-purpose memory described in FIG. 4, and transition refers to the transition data (memory) in the device general-purpose memory described in FIG. 4. Note that the first interval refers to the size of the ON bit address in FIGS. 14 and 142 and the size of the ON bit address in FIG. 18. The subsequent ones in each figure also correspond sequentially.

[0067] FIG. 11 is a detailed data diagram of the initial setting of the timing process according to an embodiment of the present invention. On the left side of the double vertical line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Similarly, below the double horizontal line, the items of TP / PC display, value, address, and memory type are described. It is the 73 initial setting (timing process) data in Figure 7. However, the first one on the right side of the double vertical line, the number of timing processes, is not in the 73 initial setting (timing process) data in Figure 7, but at the beginning of the 143 timing process data in Figure 14. After the change, it is described at the beginning of the 372 timing process data in Figure 37. Below the double horizontal line are the data for each item, which are sequentially assigned starting from the address 1960 described in Figure 6. The reason why there is no TP / PC display in the second item on the right side of the double vertical line is that it is automatically assigned by the program. Note that the memory types shown are external, process, and transition. External refers to the memory outside the PLC described in Figure 4, process refers to the process data (memory) in the device general-purpose memory described in Figure 4, and transition refers to the transition data (memory) in the device general-purpose memory described in Figure 4. Note that the first interval refers to the magnitudes of the control selections in Figures 14 and 143 and the magnitude of the control selection in Figure 19. The subsequent ones in each figure also correspond sequentially.

[0068] Figure 12 is a detailed data diagram of the initial setting of the sequential step operation in one embodiment according to the present invention. On the left side of the double vertical line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Similarly, below the double horizontal line, the items of TP / PC display, value, address, and memory type are described. It is the 74 initial setting (sequential step operation) data in Figure 7. However, the first one on the right side of the double vertical line, the number of sequential step operations, is not in the 74 initial setting (sequential step operation) data in Figure 7, but at the beginning of the 362 sequential step operation data in Figure 36. Below the double horizontal line are the data for each item, which are sequentially assigned starting from the address 1900 described in Figure 6. The reason why there is no TP / PC display in the second item on the right side of the double vertical line is that it is automatically assigned by the program. Note that the memory types shown are external, process, and transition. External refers to the memory outside the PLC described in Figure 4, process refers to the process data (memory) in the device general-purpose memory described in Figure 4, and transition refers to the transition data (memory) in the device general-purpose memory described in Figure 4. Note that the first interval refers to the magnitudes of the number of processes in Figures 36 and 362 and the magnitude of the number of processes in Figure 40.

[0069] Figure 13 is a detailed data diagram of the initial setting of the sequential step processing according to an embodiment of the present invention. On the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Similarly, on the lower side of the horizontal double line, the items of TP / PC display, value, address, and memory type are described. It is the 75 initial setting (sequential step processing) data in FIG. 7. However, the first item on the right side of the vertical double line, the number of sequential step operations, does not exist in the 74 initial setting (sequential step operation) data in FIG. 7. It becomes an item for each row of the 362 sequential step operations in FIG. 36 and is described at the beginning of the 363 sequential step processing data of the motor 1 operation in FIG. 36 or at the beginning of the 370 sequential step processing data of the motor 2 operation in FIG. 37. Therefore, the value is arbitrary. The lower side of the horizontal double line is the data for each item and is sequentially assigned from the address 1911 described in FIG. 6. The reason why there is no TP / PC display in the second item on the right side of the vertical double line is that it is automatically assigned by the program. Note that for the memory type, external, processing, transition, and repetition are displayed. External refers to the memory outside the PLC described in FIG. 4, processing refers to the processing data (memory) in the device general-purpose memory described in FIG. 4, transition refers to the transition data (memory) in the device general-purpose memory described in FIG. 4, and repetition refers to the repetition data (memory) in the device general-purpose memory described in FIG. 4. Note that the first interval refers to the magnitude of the absolute condition bit address between FIG. 36, 363 and FIG. 37, 370, and the magnitude of the absolute condition bit address between FIG. 41 and FIG. 43. The second and subsequent figures also correspond sequentially.

[0070] Figure 14 is an image general device data diagram displayed at the interface of each process for driving two motors according to an embodiment of the present invention. Since the touch panel (TP), engineering tools, and personal computer (PC) come in various sizes, the input processing, logical processing, output processing, and timing processing necessary for driving two motors are displayed in the image data diagram displayed at the interface. The numerical values are variables and can be changed. 140 is the input processing data, 141 is the logical processing data, 142 is the output processing data, and 143 is the timing processing data. This device data is created for the programmable logic controller (PLC) in which the program of the present invention is written in order to exactly match the ladder program circuit diagram for driving two motors in FIG. 5. However, in FIG. 5, the contacts are composed of input / output devices, but all of these are replaced with general-purpose bits for matching. Normally, to implement an algorithm, a program like that in FIG. 5 is written into a programmable logic controller (PLC) for implementation. However, in the present invention, instead of creating a program according to the algorithm, device data is created to cope with the changing algorithm. To correspond to the ladder program circuit diagram for driving two motors in FIG. 5, an equivalent circuit can be created by setting data for input processing, logical processing, output processing, and timing processing. Since the device names, etc. are different for each company, this device data in FIG. 5 is assumed to be using a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation. Here, in order to be the same as the ladder program in FIG. 5, the input bit is X, the system bit is SM, and the output bit is Y.

[0071] Hereinafter, a detailed description of FIG. 14 will be given with reference to FIG. 5. Regarding the intention to create input processing data for 140, since the input processing replaces the bits of various devices one-to-one with general-purpose bits and outputs them, it only defines this. The input bits in Figure 5 are 7, and there is 1 system bit. However, in other processes, only general-purpose bits can be used at all times, so it is set to 9 by adding the always-ON system bit. Here, the general-purpose bits replaced and output by the input processing are from 0 to 8 (in the programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, the general-purpose device bits are designated as M), but these numbers have no meaning, and any value may be used as long as there is no duplication. This is because it is set from 0 in the general-purpose device memory map in Figure 6. Also, the order of No. is in the order of creation, and this also has no great meaning. The intention of creating the logical processing data of 141 is only to define it because the logical processing outputs general-purpose bits based on whether it is activated by multiple consecutive logical products or only consecutive logical sums. Specifically explained in the circuit block of the 50 MC1 output bit coils in Figure 5, this circuit block includes a part where the start switch (A contact) and the contact of the start coil of MC1 (A contact) are continuously configured in a logical product, a part where the stop switch (B contact), the thermal trip signal (B contact), and the emergency stop switch (B contact) are continuously configured in a logical sum, and a part where the contact of the motor 1 star-delta switching time coil (B contact) and the contact of the start coil of MC3 (B contact) are continuously configured in a logical sum. The divided parts are further continuously configured in a logical sum, and the output of the general-purpose bit is the start coil of MC1. In this logical processing data, it is defined from No. 1 to 4, and the general-purpose bits to be output are 9 to 12 (in a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, the device is designated as M). However, since it is a block aggregation, this order doesn't matter. As long as there is no duplication, any value from 9 to 12 is acceptable. Note that No. 1 to 4 of this logical processing data construct 50 in Figure 5, No. 5 and 6 construct 51 in Figure 5, No. 7 constructs 52 in Figure 5, No. 8 constructs 53 in Figure 5, No. 9 to 12 construct 54 in Figure 5, No. 13 and 14 construct 55 in Figure 5, No. 15 constructs 56 in Figure 5, and No. 16 constructs 57 in Figure 5. The intention of creating the output processing data of 142 is only to define it because the output processing replaces general-purpose bits one-to-one with the bits of various devices and outputs them. It corresponds to the 50 MC1 output bit coils, 52 MC2 output bit coils, 53 PL1 output bit coils, 54 MC3 output bit coils, 56 MC4 output bit coils, and 57 PL2 output bit coils in Figure 5. Note that the order doesn't matter. The intention of creating the timing process data for 143 is just to define it because the timing process delays general-purpose bits and outputs them with other general-purpose bits, or blinks them and outputs them with other general-purpose bits. It corresponds to the TM1 timer coil with a setting of 100 seconds at 51 and the TM1 timer coil with a setting of 150 seconds at 55 in Figure 5. Here, the general-purpose bits replaced and output by the timing process are 25 and 26 (in a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, the device is designated as M), but these numbers have no meaning and any value may be used as long as there is no duplication. Also, the order of No is in the order of creation, and this also has no great significance. However, since only two are used here, it is just reversed.

[0072] Figure 15 is a detailed data diagram of the output process for driving two motors according to an embodiment of the present invention. On the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together, sandwiched by the horizontal double line, and are composed of five groups except for the omitted parts. On the right side of the vertical double line in the topmost group, it consists of two items, the number of input processes and its numerical value. On the right side of the vertical double line in the remaining four groups, it consists of 10 items, No, blank, name, blank, blank, device selection, actual address (10 / Hex), logic, general-purpose bit address (10 / Hex), and differentiation. Since it is omitted and to make the address structure easier to understand, under each of the five groupings, a table of the starting address by No, the number of words, and the creation order is attached with four items, No, starting address, number of words, and creation order, on one line. To explain in detail, for the input processing data of No1, the starting address starts from 2000, the number of words is 15, and the creation order is the first. The reason why the starting address is 2000 is that the program data area in Figure 6 starts from 2000 and it was created first. The number of words varies depending on the name. Since 6 words are required for a 1-second clock, it is 15 words. The next created input processing data of No2 starts from the starting address of 2015, the number of words is 13, and the creation order is the second. The same applies to No3 to No9 which are omitted. This is the same as the 140 input processing data in Figure 14 and Figure 15. However, in Figure 15, No3 to No8 are omitted and only three blanks are added to the items for description. The absence of TP / PC display is because it is automatically assigned by the program. Regarding the memory type, external, processing, quantity, and transfer are displayed. External refers to the memory outside the PLC described in Figure 4, processing refers to the processing data (memory) in the device general-purpose memory described in Figure 4, quantity refers to the quantity data (memory) in the device general-purpose memory described in Figure 4, and transfer refers to the transfer data (memory) in the device general-purpose memory described in Figure 4.

[0073] Figure 16 is the detailed data diagram 1 / 2 of the logical processing for driving two motors in one embodiment according to the present invention. Figure 17 is the detailed data diagram 2 / 2 of the logical processing for driving two motors in one embodiment according to the present invention. In Fig. 16, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Excluding the parts sandwiched by the horizontal double lines and the omitted parts, it is composed of five groups. In Fig. 17, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Excluding the parts sandwiched by the horizontal double lines and the omitted parts, it is composed of four groups. On the right side of the vertical double line in the topmost group of Fig. 16, it consists of two items, the number of input processes and its numerical value. On the right side of the vertical double line in the remaining four groups of Fig. 16, it spans across Fig. 17 and consists of 15 items, namely No, blank, name, blank, blank, general-purpose bit address (10 / Hex), differentiation, logical selection, number of elements, element 1 bit address (10 / Hex), logic, element 2 bit address (10 / Hex), logic, element 3 bit address (10 / Hex), logic. Since the parts in Fig. 16 are omitted and to make the address structure easier to understand, below the five groups, a table of the starting address, number of words, and creation order by No is attached with four items, No, starting address, number of words, and creation order, in one line. To explain in detail, the logical processing data of No1 starts from the starting address of 2175, has 20 words, and the creation order is the 10th. The reason why the starting address is 2175 is that the next address after the last address 2174 with the 9th creation order in Fig. 15 is 2175, and it was created as the 10th. The number of words varies depending on the name. Since the self-holding of MC1 requires 8 words, it is 20 words. The next created output processing data of No2 starts from the starting address of 2195, has 24 words, and the creation order is the 11th. The omitted No3 to No9 are created in the same way. FIG. 17, which straddles FIG. 16, is the same as the logical processing data of 141 in FIG. 14. However, in FIG. 17 that straddles FIG. 16, from No3 to No15 are omitted, and only three blanks are added to the items for description. The absence of the TP / PC display is because it is automatically assigned by the program. Regarding the memory type, external, quantity, processing, and transfer are displayed. Here, "external" refers to the memory outside the PLC described in FIG. 4, "processing" refers to the processing data (memory) of the device general-purpose memory described in FIG. 4, "quantity" refers to the quantity data (memory) of the device general-purpose memory described in FIG. 4, and "transfer" refers to the transfer data (memory) of the device general-purpose memory described in FIG. 4.

[0074] FIG. 18 is a detailed data diagram of the output processing for driving two motors according to an embodiment of the present invention. On the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. It is sandwiched by horizontal double lines and is composed of five groups except for the omitted parts. On the right side of the vertical double line in the topmost group, it consists of two items, namely the output processing number and its numerical value. On the right side of the vertical double line in the remaining four groups, it consists of 11 items: No, blank, name, blank, blank, ON bit address (10 / Hex), logic, OFF bit address (10 / Hex), logic, device selection, and actual address (10 / Hex). Since it is omitted and to make the address structure easier to understand, under each of the five groupings, there is an address table by No. with four items, namely No., start address, number of words, and creation order, with each line containing these four items. To explain in detail, for the output processing data of No. 1, the start address starts from 2597, the number of words is 23, and the creation order is the 28th. The reason why the start address is 2597 is that in FIGS. 19 and 20 which are related, the address after the last address 2596 of the 27th creation order is 2597, and it was created as the 28th. The number of words varies depending on the name. Since the motor 1 star start (MC1) requires 13 words, it is 23 words. The next created output processing data of No. 2 starts from the start address of 2620, the number of words is 23, and the creation order is the 29th. The same applies to No. 3 to No. 9 which are omitted. This is the same as the output processing data of 142 in FIG. 18 and FIG. 14. However, in FIG. 15, No. 3 to No. 5 are omitted, and only three blanks are added to the items for description. The absence of TP / PC display is because it is automatically assigned by the program. Note that the memory type shows external, processing, quantity, and transfer. External refers to the memory outside the PLC described in FIG. 4, processing refers to the processing data (memory) of the device general-purpose memory described in FIG. 4, quantity refers to the quantity data (memory) of the device general-purpose memory described in FIG. 4, and transfer refers to the transfer data (memory) of the device general-purpose memory described in FIG. 4.

[0075] FIG. 19 is the detailed data diagram 1 / 2 of the timing process for driving two motors according to an embodiment of the present invention. FIG. 20 is the detailed data diagram 2 / 2 of the timing process for driving two motors according to an embodiment of the present invention. In Fig. 19, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Excluding the parts sandwiched by the horizontal double lines and the omitted parts, it is composed of four groups. In Fig. 20, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Excluding the parts sandwiched by the horizontal double lines and the omitted parts, it is composed of three groups. On the right side of the vertical double line in the topmost group of Fig. 19, it consists of two items, the number of timing processes and its numerical value. On the right side of the vertical double line in the remaining three groups of Fig. 19, it spans across Fig. 20 and consists of 16 items, namely No, blank, name, blank, blank, control selection, start bit address (10 / Hex), logic, count stop bit address (10 / Hex), logic, blink ON time, blink interval time, elapsed time, general-purpose bit address (10 / Hex), and differentiation. To make the address structure in Fig. 19 easier to understand, below the four groups, a table of the starting address, number of words, and creation order for each No is attached, with four items, No, starting address, number of words, and creation order, in one line. To explain in detail, for the timing process data of No1, the starting address starts from 2539, the number of words is 29, and the creation order is the 26th. The reason why the starting address is 2539 is that in Fig. 17, the next address after the last address 2538 with the 25th creation order is 2539, and it was created as the 26th. Since the number of words varies depending on the name, and 14 words are required for the motor 1 star-delta switching time, it is 29 words. The next created timing process data of No2 has a starting address starting from 2568, the number of words is 29, and the creation order is the 27th. Figure 20, which spans with this Figure 19, is the same as the timing processing data of 142 in Figure 14. However, only three blanks are added to the items for description. The reason there is no TP / PC display is that it is automatically assigned by the program. Regarding the memory type, external, quantity, processing, and transfer are displayed. Here, "external" refers to the memory outside the PLC described in Figure 4, "processing" refers to the processing data (memory) of the device general-purpose memory described in Figure 4, "quantity" refers to the quantity data (memory) of the device general-purpose memory described in Figure 4, and "transfer" refers to the transfer data (memory) of the device general-purpose memory described in Figure 4.

[0076] (Basic Concept) Before explaining the programs from Figure 21 to Figure 34 and from Figure 48 to Figure 54, the indispensable modification register (denoted as modified R in each figure) and the repeat instruction will be explained. The modification register is a function that can modify each device data and each device bit to make its address variable. To explain with a specific example, assume there is an A contact of X0 with a modification register (in a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, the input device is denoted as X). When the value of the modification register is set to 0, it becomes the A contact of X0, and when the value is set to 8, it becomes the A contact of X8. This function of the modification register, regardless of the number that can be used simultaneously, is a basic function incorporated by the programmable logic controller (PLC) manufacturer. The repeat instruction is a function that repeats a group of instructions from the repeat instruction to the repeat completion instruction for a specified number of times. When combined with the modification register, many programs do not need to be described, so the description capacity of the program is reduced. However, since it changes constantly, it has the drawback that it cannot be easily debugged. This repeat instruction, as well as the repeat structure with another repeat within the repeat, regardless of the number, is a basic function incorporated by the programmable logic controller (PLC) manufacturer.

[0077] Figure 21 is the ladder program circuit diagram 1 / 3 of the input processing of one embodiment according to the present invention. Figure 22 is the ladder program circuit diagram 2 / 3 of the input processing according to an embodiment of the present invention. Figure 23 is the ladder program circuit diagram 3 / 3 of the input processing according to an embodiment of the present invention. That is, FIGS. 21 to 23 are a series of ladder program circuit diagrams of input processing. This ladder program circuit diagram uses the program instructions of a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, and processes one by one while changing the address with a modification register, and has a structure that repeats the processing for the number of processes with a repeat instruction. From block 210 to 212 are pre-processings before the processing, and from block 214 to 233 are performing the processing. From 235 to 238, from 239 to 23B, and from 23C to 23F are three subroutine programs. Details will be described below for each block. The transfer instruction GOEND of 210 transfers to the END of this input processing program without performing this input processing when the execution permission contact determined in the identification and initial processing program is not activated, or when the number of input processes determined by the user in use is 0. The call instruction CALL of 211 calls and executes the differentiation reset processing. Here, since all differentiations are set to "none", it is not executed. The transfer instruction MOV of 212 transfers the start address of the input processing data determined in the identification and initial processing program to the general-purpose device 1. The repeat instruction (1) FOR of 213 is paired with the repeat instruction (1) NEXT of 233, and here, it repeats for the number of input processes. The call instruction CALL of 214 calls and executes the addition processing of the number. With the arithmetic instruction + (addition) of 215, the interval up to the next number address of the input processing described in the identification and initial processing program is added to the general-purpose device 1 defined in 212 and stored in the modification register 20. With the transfer instruction MOV of 216, the general-purpose device modified by the modification register 20 is transferred to the general-purpose device 2. With the arithmetic instruction + (addition) of 217, the interval up to the device selection address of the input process, which is described in the identification and initial processing program, is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 218, the general-purpose device modified by the modification register 20 is transferred to the modification register 4. With the arithmetic instruction + (addition) of 219, the interval up to the actual address of the input process, which is described in the identification and initial processing program, is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 21A, the general-purpose device modified by the modification register 20 is transferred to the modification register 1. With the arithmetic instruction + (addition) of 21B, the interval up to the logical selection at the time of activation of the input process, which is described in the identification and initial processing program, is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 21C, the general-purpose device modified by the modification register 20 is transferred to the modification register 5. With the arithmetic instruction + (addition) of 21D, the interval up to the general-purpose bit address of the input process, which is described in the identification and initial processing program, is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 21E, the general-purpose device modified by the modification register 20 is transferred to the modification register 2. With the arithmetic instruction + (addition) of 21F, the interval up to the differentiation of the input process, which is described in the identification and initial processing program, is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 21G, the general-purpose device modified by the modification register 20 is transferred to the modification register 3. 220's input-only auxiliary general-purpose bit 1 coil outputs the activation and deactivation of input bits, general-purpose bits, link bits, latch bits, and system bits at the level for device selection. Although the data is described in words, 1 is the input bit, 2 is the general-purpose bit, 3 is the link bit, 4 is the latch bit, and 5 is the system bit. Also, although the logic of the bits is described in words, 1 is the positive logic and 2 is the negative logic. For 221, in the CALL instruction, a subroutine is called to output at the level the bit-decomposed device and the bit-decomposed each unit memory. Although not used here, the input-only auxiliary general-purpose bit 2 is activated or deactivated and returns. For 222, in the SET operation instruction, if the input-only auxiliary general-purpose bit 1 or the input-only auxiliary general-purpose bit 2 is activated, the general-purpose bit modified by the modification register 2 is (activated). This is the final output of this input process. For 223, in the SET operation instruction, when differentiation is "yes", the input differentiation prohibition general-purpose bit is set simultaneously with the final output. Although the differentiation is also described in words, 1 is "no" and 2 is "yes". For 224, in the FIFW operation instruction, when differentiation is "yes", following the SET operation instruction of 72, the modification register 2 is written to the output differentiation table. For 230, in the RST operation instruction, when the input-only auxiliary general-purpose bit 1 and the input-only auxiliary general-purpose bit 2 are deactivated and the input differentiation prohibition general-purpose bit is activated or when differentiation is "no", the input differentiation prohibition general-purpose bit is reset (deactivated). This is the final output of this input process. For 231, in the RST operation instruction, only when the input-only auxiliary general-purpose bit 1 and the input-only auxiliary general-purpose bit 2 are deactivated, the general-purpose bit modified by the modification register is reset. This and 71 are the final output of this input process. For 232, in the MOV transfer instruction, for the preparation of repetition, the general-purpose device 2 is transferred to the general-purpose device 1. As a result, when repeating, the values of the respective modification registers for the next No. are changed. The loop instruction (1) NEXT of 233 is paired with the loop instruction (1) FOR and returns to the loop instruction (1) FOR until the number of loops is exceeded, and then repeats the subsequent instructions. The structural instruction FEND of 234 ends the program for this output process. The addition process pointer of 235 is the call destination for the call instruction CALL of 214. With the arithmetic instruction + (addition) of 236, 1 is added to the general-purpose device 1 and stored in the modified register 20. With the arithmetic instruction + (addition) of 237, the modified register 20 is added to the general-purpose device with the modified register 20 and stored in the general-purpose device 1. With the return instruction RET of 238, the call is completed and the program proceeds to the next instruction after the call instruction of 214. The differentiation reset process pointer of 239 is the call destination for the call instruction CALL of 211. For all Nos. in the subroutine program group of the differentiation reset process of 23A, since the differentiation is "none", it is not described, but only the arithmetic instruction FIFR needs to be used to put the read data into the modified register and reset the general-purpose bits modified by the modified register. With the return instruction RET of 23B, the call is completed and the program proceeds to the next instruction after the call instruction of 211. The device decomposition bit process pointer of 23C is for the call instruction CALL of 221. For the subroutine program group of the device decomposition bit process of 23D, since the device decomposition bit is not used, it is omitted, but a large number of move instructions can be used to create the input-only auxiliary general-purpose bit 2 with many classifications. With the return instruction RET of 23E, the call is completed and the program proceeds to the next instruction after the call instruction of 221. The structural instruction END of 23F ends the program file.

[0078] Figure 24 is the ladder program circuit diagram 1 / 4 of the logical processing of one embodiment according to the present invention. Figure 25 is the ladder program circuit diagram 2 / 4 of the logical processing according to an embodiment of the present invention. Figure 26 is the ladder program circuit diagram 3 / 4 of the logical processing according to an embodiment of the present invention. Figure 27 is the ladder program circuit diagram 4 / 4 of the logical processing according to an embodiment of the present invention. That is, FIGS. 24 to 27 are a series of ladder program circuit diagrams of logical processing. Note that this ladder program circuit diagram uses the program instructions of a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, and processes each element of one No. while changing the address with a modified register, and repeats the number of elements with a repeat instruction. Further, when the repetition of the number of elements is completed, it has a structure that repeats the number of processes. Note that for the logical product, all are repeated to make an output determination, but for the logical sum, if even one is established, the repetition is exited and the output is performed. Blocks 240 to 242 are preprocessing for performing processing, and blocks 244 to 265 are performing processing. 267 to 26N, 270 to 273, and 274 to 277 are three subroutine programs. Details will be described below for each block. In the transfer instruction GOEND of 240, when the contact of execution permission determined in the program of identification and initial processing is not activated, or when the number of logical processes determined by the user in use is 0, this logical process is not performed, and the process moves to the END of this logical process program. In the call instruction CALL of 241, the differentiation reset process is called and executed. Here, since all differentiations are set to "none", it is not executed. In the transfer instruction MOV of 242, the start address of the logical processing data determined in the program of identification and initial processing is transferred to the general-purpose device 1. The repeat instruction (1) FOR of 243 is paired with the repeat instruction (1) NEXT of 265, and here, the repetition is performed for the number of logical processes. In the call instruction CALL of 244, the addition process of the number is called and executed. With the arithmetic instruction + (addition) of 245, the interval up to the next numbered address of the logical processing described in the identification and initial processing program is added to the general-purpose device 1 defined in 242 and stored in the modified register 20. With the transfer instruction MOV of 246, the general-purpose device modified by the modified register 20 is transferred to the general-purpose device 2. With the arithmetic instruction + (addition) of 247, the interval up to the general-purpose bit address of the logical processing described in the identification and initial processing program is added to the modified register 20 and stored in the modified register 20. With the transfer instruction MOV of 248, the general-purpose device modified by the modified register 20 is transferred to the modified register 1. With the arithmetic instruction + (addition) of 249, the interval up to the differentiation of the logical processing described in the identification and initial processing program is added to the modified register 20 and stored in the modified register 20. With the transfer instruction MOV of 24A, the general-purpose device modified by the modified register 20 is transferred to the modified register 2. With the arithmetic instruction + (addition) of 24B, the interval up to the logical selection of the logical processing described in the identification and initial processing program is added to the modified register 20 and stored in the modified register 20. With the transfer instruction MOV of 24C, the general-purpose device modified by the modified register 20 is transferred to the modified register 4. With the arithmetic instruction + (addition) of 24D, the interval up to the number of elements of the logical processing described in the identification and initial processing program is added to the modified register 20 and stored in the modified register 20. With the transfer instruction MOV of 24E, the general-purpose device modified by the modified register 20 is transferred to the modified register 5. With the arithmetic instruction + (addition) of 24F, the interval up to the element 1 bit address of the logical processing described in the identification and initial processing program is added and stored in the general-purpose device 7 in the modified register 20. With the arithmetic instruction + (addition) of 24G, the interval up to the logic of element 1 of the logical processing described in the identification and initial processing program is added to the general-purpose device 7 and stored in the general-purpose device 8. With the arithmetic instruction + (addition) for 24H, the interval between the element 1-bit addresses and the logical interval of the logical processing described in the identification and initial processing program are added and stored in the general-purpose device 3. With the transfer instruction MOV for 24J, 0 is transferred to the general-purpose device 4. With the transfer instruction MOV for 24K, 0 is transferred to the general-purpose device 5. The loop instruction (2) FOR for 250 pairs with the loop instruction (2) NEXT for 262. Here, a loop is performed for the value of the general-purpose device modified by the modification register 5. With the arithmetic instruction * (multiplication) for 251, the general-purpose device 4 is multiplied by the general-purpose device 3 calculated with 24H and stored in the general-purpose device 6. With the arithmetic instruction + (addition) for 252, the general-purpose device 6 calculated with 251 is added to the general-purpose device 7 calculated with 24F and stored in the modification register 20. With the transfer instruction MOV for 253, the general-purpose device modified by the modification register 20 is transferred to the modification register 3. With the arithmetic instruction + (addition) for 254, the general-purpose device 6 calculated with 251 is added to the general-purpose device 8 calculated with 24G and stored in the modification register 20. With the transfer instruction MOV for 255, the general-purpose device modified by the modification register 20 is transferred to the modification register 6. The arithmetic instruction INC for 256 selects the logical product. In the element logic, when the element is activated, 1 is added to the general-purpose device 5. The call instruction CALL for 257 selects the logical product. For all the number of elements, in the element logic, when the element is activated, the subroutine of the output process is called. The move instruction CJ for 258 selects the logical product. In the element logic, when the element is activated, it shifts to the loop position pointer for 260. The transfer instruction MOV for 259 selects the logical product. In the element logic, when the element is deactivated, 0 is transferred to the general-purpose device 5. The CALL instruction of 25A selects the logical product. In the logic of the element, when the element is deactivated, it calls the subroutine for non-output processing. The BREAK instruction of 25B selects the logical product. In the logic of the element, when the element is deactivated, it abandons the loop and transfers to the loop completion position pointer. The CALL instruction of 25C selects the logical sum. In the logic of the element, when the element is activated, it calls the subroutine for output processing. The BREAK instruction of 25D selects the logical sum. In the logic of the element, when the element is activated, it abandons the loop and transfers to the loop completion pointer. The CALL instruction of 25E selects the logical sum. In the logic of the element, when the element is deactivated, it calls the subroutine for non-output processing. The loop position pointer of 260 is the destination of the CJ instruction of 258. In the INC instruction of 261, 1 is added to the general-purpose device 4 for loop preparation. Thereby, when looping, the value of each modification register of the next element is changed. The NEXT instruction (2) of 262 pairs with the FOR instruction (2). Until exceeding the number of loop iterations, it returns to the FOR instruction (2) and repeats the subsequent instructions. The loop completion position pointer of 263 is the destination of the BREAK instruction of 25B and 25D. In the MOV instruction of 264, for loop preparation, the general-purpose device 2 is transferred to the general-purpose device 1. Thereby, when looping, the value of each modification register of the next No. is changed. The NEXT instruction (1) of 265 pairs with the FOR instruction (1). Until exceeding the number of loop iterations, it returns to the FOR instruction (1) and repeats the subsequent instructions. The FEND instruction of 266 ends this logical processing program. The output processing pointer of 267 is the call destination for the CALL instructions of 257 and 25C. For the operation instruction SET of 268, when the differentiation is "none", it sets (activates) the logical auxiliary general-purpose bit. For the transfer instruction CJ of 269, when the differentiation is "none", it transfers to the level output pointer. For the operation instruction SET of 26A, when the differentiation is "yes" and the logical differentiation prohibition general-purpose bit is not activated, it sets (activates) the general-purpose bit modified by modification register 1. This is the final output of this logical processing. For the operation instruction SET of 26B, when the differentiation is "yes" and the logical differentiation prohibition general-purpose bit is not activated, following the operation instruction SET of 26A, it sets (activates) the logical differentiation prohibition general-purpose bit. For the operation instruction FIFW of 26C, when the differentiation is "yes" and the logical differentiation prohibition general-purpose bit is not activated, following the operation instruction SET of 26B, it writes modification register 2 to the logical differentiation table. For the transfer instruction CJ of 26D, when the differentiation is "yes", it transfers to the call completion pointer. The non-output processing pointer of 26E is the call destination for the call instructions CALL of 25A and 25E. For the operation instruction RST of 26F, when the differentiation is "none", it resets (deactivates) the logical auxiliary general-purpose bit. For the transfer instruction CJ of 26G, when the differentiation is "none", it transfers to the level output pointer. For the operation instruction RST of 26H, when the differentiation is "yes", it resets (deactivates) the logical differentiation prohibition general-purpose bit. For the transfer instruction CJ of 26J, following the operation instruction RST, it transfers to the call completion pointer of 26M. The level output processing pointer of 26K is the transfer destination for the transfer instructions CJ of 269 and 26G. The general-purpose bit coil modified by modification register 1 outputs at the level according to the logical auxiliary general-purpose bit. This is the final output at the level of this logical processing. The call completion pointer of 26M is the transfer destination for the transfer instructions CJ of 25D and 26J. With the return instruction RET of 26N, the call is completed and the process proceeds to the next call instruction corresponding to 257, 25C, 25A, and 25E. The count addition processing pointer of 270 is the call destination for the call instruction CALL of 244. With the arithmetic instruction + (addition) of 271, 1 is added to the general-purpose device 1 and stored in the modified register 20. With the arithmetic instruction + (addition) of 272, the modified register 20 is added to the general-purpose device with the modified register 20 and stored in the general-purpose device 1. With the return instruction RET of 273, the call is completed and the process proceeds to the next instruction after the call instruction of 244. 274, the differentiation reset processing pointer, is the call destination for the call instruction CALL of 241. The subroutine program group for the differentiation reset processing of 275 is not described for all Nos because the differentiation is "none". It only needs to use the arithmetic instruction FIFR, put the read data into the modified register, and reset the general-purpose bits modified by the modified register. With the return instruction RET of 276, the call is completed and the process proceeds to the next instruction after the call instruction of 241. With the structure instruction END of 277, the program file is terminated.

[0079] Figure 28 is the ladder program circuit diagram 1 / 3 of the output processing according to an embodiment of the present invention. Figure 29 is the ladder program circuit diagram 2 / 3 of the output processing according to an embodiment of the present invention. Figure 30 is the ladder program circuit diagram 3 / 3 of the output processing according to an embodiment of the present invention. That is, FIGS. 28 to 30 are a series of ladder program circuit diagrams for output processing. This ladder program circuit diagram uses the program instructions of a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, and processes each No. while changing the address with a modification register, and has a structure that repeats the processing for the number of processes with a repeat instruction. Blocks 280 and 281 are preprocessing before the processing, and blocks 283 to 300 are performing the processing. From 303 to 305 and from 306 to 308 are two subroutine programs. The following will provide a detailed explanation for each block. The transfer instruction GOEND of 280 transfers to the END of this output processing program without performing this output processing when the execution permission contact determined in the identification and initial processing program and the number of output processes determined by the user are 0. The transfer instruction MOV of 281 transfers the start address of the output processing data determined in the identification and initial processing program to the general-purpose device 1. The repeat instruction (1) FOR of 282 pairs with the repeat instruction (1) NEXT of 301, and here, repeats for the number of output processes. The call instruction CALL of 283 calls and executes the addition process of the number. The arithmetic instruction + (addition) of 284 adds the interval up to the next number address to the general-purpose device 1 defined in 281 and stores it in the modification register 20. The transfer instruction MOV of 285 transfers the general-purpose device modified by the modification register 20 to the general-purpose device 2. The arithmetic instruction + (addition) of 286 adds the interval up to the ON bit address to the modification register 20 and stores it in the modification register 20. The transfer instruction MOV of 287 transfers the general-purpose device modified by the modification register 20 to the modification register 1. The arithmetic instruction + (addition) of 288 adds the interval up to the logic of the ON bit to the modification register 20 and stores it in the modification register 20. With the transfer instruction MOV of 289, the general-purpose device modified by the modification register 20 is transferred to the modification register 4. With the arithmetic instruction + (addition) of 28A, the interval up to the logic of the OFF bit is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 28B, the general-purpose device modified by the modification register 20 is transferred to the modification register 2. With the arithmetic instruction + (addition) of 28C, the interval up to the logic of the OFF bit is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 28D, the general-purpose device modified by the modification register 20 is transferred to the modification register 5. With the arithmetic instruction + (addition) of 28E, the interval up to the device selection is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 28F, the general-purpose device modified by the modification register 20 is transferred to the modification register 6. With the arithmetic instruction + (addition) of 28G, the interval up to the physical address is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 28H, the general-purpose device modified by the modification register 20 is transferred to the modification register 3. With the arithmetic instruction SET of 290, according to the logic of the ON bit, if the general-purpose bit modified by the modification register 1 is activated, the output bit modified by the modification register 3 selected by the device selection is set (activated). With the arithmetic instruction SET of 291, according to the logic of the ON bit, if the general-purpose bit modified by the modification register 1 is activated, the general-purpose bit modified by the modification register 3 selected by the device selection is set (activated). With the arithmetic instruction SET of 292, according to the logic of the ON bit, if the general-purpose bit modified by the modification register 1 is activated, the link bit modified by the modification register 3 selected by the device selection is set (activated). For 293, the operation instruction SET sets (activates) the latch bits modified by modification register 3 selected by device selection if the general-purpose bits modified by modification register 1 are activated according to the logic of the ON bits. For 294, the operation instruction SET sets (activates) the system bits modified by modification register 3 selected by device selection if the general-purpose bits modified by modification register 1 are activated according to the logic of the ON bits. For 295, in the call instruction CALL, a subroutine is called to set (activate) each decomposed value modified by modification register 3 for the device bit-decomposed or each unit memory bit-decomposed. This is not used here. For 296, the operation instruction RST resets (deactivates) the output bits modified by modification register 3 selected by device selection if the general-purpose bits modified by modification register 2 are activated according to the logic of the OFF bits. For 297, the operation instruction RST resets (deactivates) the general-purpose bits modified by modification register 3 selected by device selection if the general-purpose bits modified by modification register 2 are activated according to the logic of the OFF bits. For 298, the operation instruction RST resets (deactivates) the link bits modified by modification register 3 selected by device selection if the general-purpose bits modified by modification register 2 are activated according to the logic of the OFF bits. For 299, the operation instruction RST resets (deactivates) the latch bits modified by modification register 3 selected by device selection if the general-purpose bits modified by modification register 2 are activated according to the logic of the OFF bits. For 29A, the operation instruction RST resets (deactivates) the system bits modified by modification register 3 selected by device selection if the general-purpose bits modified by modification register 2 are activated according to the logic of the OFF bits. A subroutine is called by the CALL instruction of 29B to reset (deactivate) each decomposed value obtained by bit-decomposing the device or each unit memory with the modification register 3. This is not used here. With the MOV transfer instruction of 300, the general-purpose device 2 is transferred to the general-purpose device 1. 301 is paired with the NEXT loop instruction (1) and the FOR loop instruction (1), and it loops until the loop count is exceeded, starting from the FOR loop instruction (1). With the FEND structure instruction of 302, the program for this output process is terminated. The count addition processing pointer of 303 is the call destination for the CALL instruction of 283. With the + (addition) arithmetic instruction of 304, 1 is added to the general-purpose device 1 and stored in the modification register 20. With the + (addition) arithmetic instruction of 305, the modification register 20 is added to the general-purpose device with the modification register 20 and stored in the general-purpose device 1. With the RET return instruction of 306, the call is completed and the program proceeds to the next instruction after the CALL instruction of 283. The device decomposition bit set processing pointer of 307 is for the CALL instruction of 295. The subroutine program group for the device decomposition bit set processing of 308 does not use the device decomposition bits, so it is omitted. However, by using many MOV instructions, the bits of each device can be set with many classifications. With the RET return instruction of 309, the call is completed and the program proceeds to the next instruction after the CALL instruction of 295. The device decomposition bit reset processing pointer of 30A is for the CALL instruction of 29B. The subroutine program group for the device decomposition bit reset processing of 30B does not use the device decomposition bits, so it is omitted. However, by using many MOV instructions, the bits of each device can be reset with many classifications. With the RET return instruction of 30C, the call is completed and the program proceeds to the next instruction after the CALL instruction of 29B. The 30D, with the structure command END, ends the program file.

[0080] Figure 31 is the 1 / 4 of the ladder program circuit diagram for the counting process according to one embodiment of the present invention. Figure 32 is the 2 / 4 of the ladder program circuit diagram for the counting process according to one embodiment of the present invention. Figure 33 is the 3 / 4 of the ladder program circuit diagram for the counting process according to one embodiment of the present invention. Figure 34 is the 4 / 4 of the ladder program circuit diagram for the counting process according to one embodiment of the present invention. That is, from Figure 31 to Figure 34 are a series of ladder program circuit diagrams for the counting process. Note that this ladder program circuit diagram uses the program instructions of a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, and processes one by one while changing the address with a modification register, and has a structure that repeats the processing for the number of processes with a repeat instruction. Blocks 310 and 311 are pre-processing before the processing, and blocks 313 to 332 are performing the processing. From 334 to 337, from 338 to 33B, and from 340 to 348 are three subroutine programs. The following is a detailed explanation for each block. Note that this program is not a scan execution type program, but a fixed cycle program. Usually, in a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, a timer is used, but since it does not fit well with the repeat instruction, a fixed cycle program of 100 mmsec (0.1 second) is used to measure time. However, although there are timers with a measurement of 1 mmsec (0.001 second), here, the fixed cycle of 0.001 second, which is rarely used, has little meaning and is not created deliberately. The following gives a detailed explanation for each block. The transfer instruction GOEND of 310, when the contact for execution permission determined in the program of identification and initial processing and the number of counting processes determined by the user are 0, does not perform this counting process and transfers to the END of this counting process program. In 311, with the transfer instruction MOV, the starting address of the timing processing data determined by the identification and initialization processing program is transferred to the general-purpose device 1. The loop instruction (1) FOR in 312 pairs with the loop instruction (1) NEXT in 332 and here performs loops for the number of times of timing processing. In 313, with the call instruction CALL, the addition processing of the quantity is called and executed. In 314, with the arithmetic instruction + (addition), the interval up to the next number address is added to the general-purpose device 1 defined in 311 and stored in the modified register 20. In 315, with the transfer instruction MOV, the general-purpose device modified by the modified register 20 is transferred to the general-purpose device 2. In 316, with the arithmetic instruction + (addition), the interval up to the control selection is added to the modified register 20 and stored in the modified register 20. In 317, with the transfer instruction MOV, the general-purpose device modified by the modified register 20 is transferred to the modified register 9. In 318, with the arithmetic instruction + (addition), the interval up to the start bit address is added to the modified register 20 and stored in the modified register 20. In 319, with the transfer instruction MOV, the general-purpose device modified by the modified register 20 is transferred to the modified register 1. In 31A, with the arithmetic instruction + (addition), the interval up to the logic of the start bit is added to the modified register 20 and stored in the modified register 20. In 31B, with the transfer instruction MOV, the general-purpose device modified by the modified register 20 is transferred to the modified register 10. In 31C, with the arithmetic instruction + (addition), the interval up to the count stop bit address is added to the modified register 20 and stored in the modified register 20. In 31D, with the transfer instruction MOV, the general-purpose device modified by the modified register 20 is transferred to the modified register 2. In 31E, with the arithmetic instruction + (addition), the interval up to the logic of the count stop bit is added to the modified register 20 and stored in the modified register 20. In 31F, with the transfer instruction MOV, the general-purpose device modified by the modification register 20 is transferred to the modification register 11. In 31G, with the arithmetic instruction + (addition), the interval from the modification register 20 to the start address of the blink ON time is added and stored in the modification register 20. In 31H, with the transfer instruction MOV, the general-purpose device modified by the modification register 20 is transferred to the modification register 3. In 31J, with the arithmetic instruction + (addition), the interval from the modification register 20 to the address of the blink interval time is added and stored in the modification register 20. In 31K, with the transfer instruction MOV, the general-purpose device modified by the modification register 20 is transferred to the modification register 4. In 320, with the arithmetic instruction + (addition), the interval from the modification register 20 to the address of the delay time is added and stored in the modification register 20. In 321, with the transfer instruction MOV, the general-purpose device modified by the modification register 20 is transferred to the modification register 5. In 322, with the arithmetic instruction + (addition), the interval from the modification register 20 to the address of the elapsed time is added and stored in the modification register 20. In 323, with the transfer instruction MOV, the general-purpose device modified by the modification register 20 is transferred to the modification register 6. In 324, with the arithmetic instruction + (addition), the interval from the modification register 20 to the general-purpose bit address is added and stored in the modification register 20. In 325, with the transfer instruction MOV, the general-purpose device modified by the modification register 20 is transferred to the modification register 7. In 326, with the arithmetic instruction + (addition), the interval from the modification register 20 to the differentiation is added and stored in the modification register 20. In 327, with the transfer instruction MOV, the general-purpose device modified by the modification register 20 is transferred to the modification register 12. In 328, with the arithmetic instruction + (addition), the interval from the modification register 20 to the address of the differentiation inhibition bit is added and stored in the modification register 20. In 329, with the transfer instruction MOV, the general-purpose device modified by the modification register 20 is transferred to the modification register 8. For the operation instruction RST of 32A, according to the logic of the start bit, if the general-purpose bit modified by modification register 1 is deactivated and the differentiation prohibition bit is activated, it resets (deactivates) the general-purpose bit modified by modification register 8. For the operation instruction RST of 32B, according to the logic of the start bit, if the general-purpose bit modified by modification register 1 is deactivated and the general-purpose bit is activated, it resets (deactivates) the general-purpose bit modified by modification register 7. For the transfer instruction MOV of 32C, according to the logic of the start bit, if the general-purpose bit modified by modification register 1 is deactivated and the elapsed time is not 0, it transfers 0 to the general-purpose device modified by modification register 7. For the move instruction CJ of 32D, according to the logic of the start bit, when the general-purpose bit modified by modification register 1 is deactivated, it transfers to the repeat completion pointer. For the operation instruction INC of 32E, according to the logic of the start bit, if the general-purpose bit modified by modification register 1 is activated and according to the logic of the stop bit, if the general-purpose bit modified by modification register 11 is deactivated, it adds 1 to the general-purpose device modified by modification register 6. For the call instruction CALL of 32F, according to the logic of the start bit, if the general-purpose bit modified by modification register 1 is activated and according to the logic of the stop bit, if the general-purpose bit modified by modification register 11 is deactivated, and when the blinking process is selected, it calls the subroutine of the blinking process. For the call instruction CALL of 32G, according to the logic of the start bit, if the general-purpose bit modified by modification register 1 is activated and according to the logic of the stop bit, if the general-purpose bit modified by modification register 11 is deactivated, and when the ON delay process is selected, it calls the subroutine of the ON delay process. The repeat completion position pointer of 330 is the destination of the move instruction CJ of 32D. For the transfer instruction MOV of 331, for the preparation of repetition, it transfers the general-purpose device 2 to the general-purpose device 1. Thereby, when repeating, it changes the values of each modification register of the next No. The loop instruction (1) NEXT of 332 pairs with the loop instruction (1) FOR and returns to the loop instruction (1) FOR until the number of loops is exceeded, and then repeats the subsequent instructions. The structural instruction FEND of 333 ends this logical processing program. The addition processing pointer of 334 is the call destination for the call instruction CALL of 313. The arithmetic instruction + (addition) of 335 adds 1 to the general-purpose device 1 and stores it in the modified register 20. The arithmetic instruction + (addition) of 336 adds the modified register 20 to the general-purpose device with the modified register 20 and stores it in the general-purpose device 1. The return call instruction RET of 337 completes the call and transfers to the next instruction after the call instruction of 313. The blink processing pointer of 338 is the call destination for the call instruction CALL of 32F. The general-purpose bit coil modified by the modified register 7 of 339 is activated if the elapsed time is less than the blink interval time and the elapsed time is less than the blink ON time. This is the final output by blink selection. The transfer instruction MOV of 33A transfers 0 to the general-purpose device modified by the modified register 6 if the elapsed time exceeds the blink interval time. The return call instruction RET of 33B completes the call and transfers to the next instruction after the call instruction of 32F. The ON delay processing pointer of 340 is the call destination for the call instruction CALL of 32G. The general-purpose bit coil modified by the modified register 7 of 341 is activated if the elapsed time exceeds the delay time and no differentiation is performed. This is the final output by blink selection. The arithmetic instruction SET of 342 sets (activates) the general-purpose bit modified by the modified register 7 if the elapsed time exceeds the delay time, differentiation is "enabled", and the logic differentiation prohibition general-purpose bit is not activated. This is the final output by blink selection. When the elapsed time of the arithmetic instruction FIFW of 343 exceeds the delay time, differentiation is "enabled", and the general-purpose bit for logical differentiation prohibition is not activated, following the arithmetic instruction SET of 342, it writes the modification register 7 to the timing differentiation table. When the elapsed time of the arithmetic instruction FIFW of 344 exceeds the delay time, differentiation is "enabled", and the general-purpose bit for logical differentiation prohibition is not activated, following the arithmetic instruction FIFW of 343, it further writes the constant 2 to the timing differentiation table. When the elapsed time of the arithmetic instruction SET of 345 exceeds the delay time, differentiation is "enabled", and the general-purpose bit for logical differentiation prohibition is not activated, following the arithmetic instruction FIFW of 33C, it sets (activates) the general-purpose bit modified by the modification register 12. When the elapsed time of the transfer instruction MOV of 346 reaches the upper limit value, it transfers the general-purpose device modified by the modification register 5 to the general-purpose device modified by the modification register 6. With the return call instruction RET of 347, the call is completed and it proceeds to the next of the call instruction of 32G. With the structure instruction END of 348, the program file is terminated.

[0081] Note that in order to be equivalent to the ladder program of Fig. 5, only the input processing ladder program, logical processing ladder program, output processing ladder program, and timing processing ladder program of the program of the present invention are used, and it is realized by setting the corresponding data. Here, the input device data processing ladder program and device data arithmetic processing ladder program required to support all algorithms, and the corresponding data for each, can also be created in the same structure as the input processing ladder program from Fig. 21 to Fig. 23, the logical processing ladder program from Fig. 24 to Fig. 27, the output processing ladder program from Fig. 28 to Fig. 30, and the timing processing ladder program from Fig. 31 to Fig. 34. Both programs are structured to process each No. and repeat the process number of times with a repeat command. The input device data processing program compares data and activates the result bit. If the bit is activated, the device data calculation processing program executes the command set selected by the PLC manufacturer and changes the device data and bit to perform processing. The bits and device data are processed by the modification register with the address data set.

[0082] (Concept) Here, we will further explain the common structure and definition of each process while comparing it with a general program. General programs start from the form of CPU machine language, and essentially start from an assembly language that corresponds one-to-one to the machine language that the computer can directly interpret, and gradually change to a high-level language to meet the convenience of programmers and users. The current programmable logic controller (PLC) programs are high-level languages ​​that have a language form that combines a relay sequence circuit with a powerful monitor function and an assembly language. In other words, the reason why programs can be structured, interrupt programs can be used frequently, and multiple programs can be managed is to meet the convenience of programmers and users, and from the CPU's perspective, it can be said that everything is one program. The program of this invention is also formed of nine core processing programs and three derived programs, but it can also be created in one program, and conversely, it can even be subdivided. In addition, programmable logic controllers (PLCs) often meet the needs of programmers rather than users, and assets such as faster CPUs and cheaper memories are diverted to structuring for programmers, and unification and consolidation are limited to programmers, further increasing the freedom of programmers. The present invention is not for programmers, but aims at unifying and aggregating the program itself. By replacing the definitions and allocations of programmable logic controllers (PLCs), or the specifications from flowcharts, with multiple data, unification and aggregation are achieved. The definitions and allocations of programmable logic controllers (PLCs) refer to the physical arrangement order of I / O, the counting rules, or the symbol names of device bits, etc., which are determined for each company. Also, the specifications from flowcharts refer to whether the activation bits described above are positive logic or negative logic. Moreover, since multiple data can use modified registers to identify bits, unification and aggregation are achieved by replacing them with bit address data, or by replacing the selection of symbol names of device data and device bits, positive / negative logic selection, operation selection, etc. with numerical values because case differentiation can be done numerically. The above replacement with numerical values is performed for each processing order. The processing for each processing order means that when the input part is activated, it is activated or an operation is performed to output. The input part has three forms: bits, device bits defined and allocated, and judgment by comparison of device data, all of which can be modified by modified registers. The form of the output part is bits that can be modified by modified registers and operations for case differentiation replaced with numerical values. Although operations often require many case differentiations, they are mostly unused operations, so a more ideal program can be obtained by selecting and discarding current operation instructions.

[0083] Figure 35 is a ladder program circuit diagram with specification changes for driving two motors in a general embodiment according to the present invention. Figure 35 is a ladder program circuit diagram obtained by modifying the ladder program circuit diagram of Figure 5. The modification specifications are as follows: when starting Motor 1 and then starting Motor 2, or when starting Motor 2 and then starting Motor 1, once either motor starts, the other motor cannot be started until the flashing ends. Since the operator needs to be present until the flashing ends, this is a modification due to poor efficiency. Also, as an additional modification point, the star-delta switching time for both motors is increased by another 10 seconds. The ladder program circuit diagram of Figure 35 consists only of contact A, contact B, and a coil. The signal from the input unit is used as the input bit, the coil output by the output unit is used as the output bit, the general-purpose bit built into the programmable logic controller (PLC), and a timer is used, with the built-in 1-second clock used as the 1-second clock system bit. Except for using the general-purpose bit, each component (such as PB and MC) is the same as in Figure 5. Note that since 2 seconds does not exist as a system bit, the general-purpose bit is used as a 2-second clock in a self-holding procedure.

[0084] The following provides a detailed description for each block. The set 1-second TM1 timer coil at 350 starts measurement when the TM2 timer is not activated and is activated when the set time of 1 second is reached. The set 1-second TM2 timer coil at 351 starts measurement when the TM1 timer is activated and is activated when the set time of 1 second is reached. The M1 general-purpose bit coil at 352 is activated when the TM1 timer is not activated. That is, it creates a 2-second clock. The M2 general-purpose bit coil at 353 is self-held when the start switch is pressed when Motor 1 is neither in star start nor in delta start, and remains self-held and activated unless the stop switch is pressed, a thermal trip signal is input, or an emergency stop is pressed. The general-purpose bit coil of M3 at 354 is self-held, continues, and is activated when the general-purpose bit of M2 is activated and the motor 2 is not in star start-up. The timer coil of TM3 set at 355 is self-held, starts measurement when the general-purpose bit of M2 is activated and the motor 2 is not in star start-up, and is activated when the set time of 110 seconds is reached. The general-purpose bit coil of M4 at 356 is self-held when the start switch is pressed when the motor 2 is neither in star start-up nor in delta start-up, and continues to be self-held and is activated unless the stop switch is pressed, a thermal trip signal is input, or an emergency stop is pressed. The general-purpose bit coil of M5 at 357 is self-held, continues, and is activated when the general-purpose bit of M4 is activated and the motor 1 is not in star start-up. The timer coil of TM4 set at 358 is self-held, starts measurement when the general-purpose bit of M5 is activated and the motor 1 is not in star start-up, and is activated when the set time of 160 seconds is reached. The output bit coil of MC1 at 359 is activated when the general-purpose bit of M3 is activated and the general-purpose timer of TM3 is inactive. The output bit coil of MC2 at 35A is activated when the timer of TM3 is activated. The output bit coil of PL1 at 35B repeats activation and inactivation every 2 seconds when the general-purpose bit of M2 is activated and the output bits of MC1 and MC2 are inactivated, repeats activation and inactivation every 1 second when the output bit of MC1 is activated, or is activated when the output bit of MC2 is activated. The output bit coil of MC3 at 35C is activated when the general-purpose bit of M5 is activated and the general-purpose timer of TM4 is inactive. The output bit coil of MC4 at 35D is activated when the timer of TM4 is activated. When the PL2 output bit coil and the M4 general-purpose bit of 35E are activated and the MC3 output bit and the MC4 output bit are deactivated, activation and deactivation are repeated every 2 seconds. When the MC3 output bit is activated, activation and deactivation are repeated every 1 second. Or when the TM4 timer is activated, it is activated. Note that 35E should have a structure where the motor has only changed from 1 to 2 compared to 35B. Here, for the sake of having the same movement, instead of using the output of the MC, a timer that activates the MC is used. That is, the creator's choice is also an example that affects the structure.

[0085] Figure 36 is the image data diagram 1 / 2 displayed on the interface of each process with specification changes for driving two motors according to an embodiment of the present invention. Figure 37 is the image data diagram 2 / 2 displayed on the interface of each process with specification changes for driving two motors according to an embodiment of the present invention. That is, Figures 36 and 37 are image data diagrams displayed on the interface for driving two motors with procedures added. However, instead of the image data displayed on the interface of Figure 14 equivalent to the program of Figure 5, in order to make the part where the procedure is added understandable in sequential step processing, although it is of course possible to create it equivalently, the image data displayed on the interface realized by sequential step processing is deliberately used. Since it is not created equivalently to Figure 6, while specifying the procedure for creating new data for realizing the specifications including the specifications added in Figure 35, and also comparing with the new design of the program of a normal programmable logic controller (PLC), a detailed description will be given. In the design of a program for a new programmable logic controller (PLC), since program design is carried out after the hard circuit (electrical connection circuit diagram) is determined, first, comments are created for each input / output address bit. In this invention as well, it starts with creating a part of the input processing and output processing. The reason for stating a part of the output processing is that when newly creating data, the ON bit address and OFF bit address of the output processing cannot be known until the design is completed, so it is described as the input part. The input processing data of 360 in Fig. 36 is exactly the same data as the input processing data of 140 in Fig. 14. Note that for No1 and No2 of the input processing data, it is assumed that a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation is used. Therefore, for system bits (SM in device selection), from No3 to No9 are input bits (X in device selection). The general-purpose bits of 360 can be determined at this point. As also described in the detailed explanation of Fig. 14, in a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, general-purpose device bits are designated as M, and here they are set from 0 to 8. These numbers have no meaning, and any value can be used as long as there is no duplication. Also, the order of No is in the creation order, and this also has no great significance. Therefore, the determination of these numbers can be carried out by the data creation system (engineering tool, touch panel (TP), personal computer (PC)), so it can be determined manually, but basically the data creation system can automatically determine the available addresses. Similarly, the output processing data of 371 in Fig. 37 is exactly the same data as the device selection and actual address of the output part of the output processing data of 142 in Fig. 14. At this stage, all settings of the input processing data of 360 are completed, and the data of the output part of the output processing data of 371 is completed, while no other data has been set at all. In the case of a device that is not a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, depending on the device selection, it may not be possible to determine whether it is an input bit, an output bit, or a system bit. Furthermore, there are even cases where all data is treated as 16-bit data (to be used after being decomposed into bits). In this case, it is necessary to pay attention to the fact that the "name" associated with No should also include its function to indicate the role of that bit. Next, we enter the design of the core specification. Generally, after analyzing the specification and completing the analysis, comments for general-purpose device bits are created. Referring to these comments, while further devising the specification, the program is constructed. Here, the analysis of the specification is the same, but next, the setting of 362 sequential step operation data is performed. Since the basic requirement is to move two motors according to the analysis of the specification, the number of sequential step operations is set to 2, and the names associated with No are set to "Motor 1 Operation" and "Motor 2 Operation". Next, the setting of the sequential step processing data for Motor 1 Operation in 363 is performed. According to the specification, it consists of three processes: accepting startup by pressing the startup switch, initial startup in star connection, and switching to delta connection for startup. Also, since each process only moves to the next No, the total number of branches associated with No is 1. The names are set to "Motor 1 Startup Acceptance", "Motor 1 Initial Startup", and "Motor 1 Switching". Next, the general-purpose bit address for Branch 1 and the reset bit address for Branch 1 are set. Here, the general-purpose bit address for Branch 1 is set to 9, 10, and 11, which are the subsequent numbers of the input process. The reset bit address for Branch 1, except for No1, is set according to the previous No. There is no meaning to this number, and any value can be used as long as there is no duplication. However, the reset bit address for Branch 1 must be the address before the transition. At this stage, the setting of the input process data in 360 is completed, the setting of the sequential step operation data in 362 is completed, the data for the output part of the output process data in 371 is completed, and the data for the output part of the sequential step processing data for Motor 1 Operation in 363 is completed. Next, construct trigger bits such as the absolute condition bit, start bit, start condition bit, branch condition bit, and branch permission bit for each No. of the sequential step processing data of the motor 1 operation of 363. Since there is no branching, the branch condition bit and branch permission bit for each No. are set to all 1s to be always ON without doing anything. Next, when analyzing the absolute condition bits of this process, since there are three elements: the stop switch is not pressed, the thermal is not tripped, and the emergency stop switch is not pressed, 361 logical processing data will be used. At this stage, since the general-purpose bit address of the 361 logical processing data can be determined, the next number in the sequential step-by-step processing of the motor 1 operation in 362 is set to 12. This number has no meaning and can be any value as long as there is no duplication. Next, when analyzing the start bits for each No, the start bit for No1 is 2 because it is the start switch from the input processing. The start bit for No2 is set as the motor 2 not starting in star connection, and it cannot be determined at present. The start bit for No3 is specified in the specification to start 110 seconds after the star connection start of motor 1, so 372 timing processing data will be used. At this stage, since the general-purpose bit address of the 372 timing processing data can be determined, the next number in the logical processing is set to 13. This number has no meaning and can be any value as long as there is no duplication. Also, the start bit of the 372 timing processing data is set to 10 for the initial start of motor 1 in the sequential step-by-step processing of the motor 1 operation in 363, and since the measurement is not stopped, the count stop bit is set to be always ON in negative logic. Note that the control selection for No1 is ON delay. Here, also, return to the continuation of the construction of the trigger bit in the sequential step-by-step processing data of the motor 1 operation in 363 and analyze the start condition bits for each No. Then, the start condition bit for No1 has two elements because motor 1 is not starting in star connection and not starting in delta connection either, so 361 logical processing data will be used. At this stage, since the general-purpose bit address of the 361 logical processing data can be determined, the next number in the timing processing is set to 14. This number has no meaning and can be any value as long as there is no duplication. Note that with the above settings, for the input part on hold in the 371 output processing data, 10 and 11 in the sequential step-by-step processing data of the motor 1 operation in 363 can be set for the ON bit address and OFF bit address of No1 and No2. Summarizing up to this stage, the input processing data of 360 is completed, the sequential step-by-step operation data of 362 is completed, the No. 1 and No. 2 data of the logical processing data of 361 is completed, the data of the output part of the output processing data of 371 and the No. 1 and No. 2 data of the input part are completed, and the data other than No. 2 that is the activation condition for not starting with the star connection of the motor 2 in the sequential step-by-step processing data of 373 is completed. Next, in order to complete the control specification of motor 1, lamp control must be constructed. Since there is one lamp, its lighting and blinking time express the difference. Blinking in 2 seconds means accepting the switch, blinking in 1 second means driving the motor in star connection, and lighting means driving the motor in delta connection. Therefore, it is decided to construct and handle the logical processing data of 361. Also, although there is a 2-second clock system bit, it is decided to perform the blinking control in the timing process. Since there are three ways to light the lamp, it is decided to set from No. 3 to No. 5 in the logical processing data of 361. No. 3 is the startup display of MC1, and the general-purpose bit address is set to 15 following. Note that the number of elements is 2, and 10 and 0 of the motor 1 initial startup and 1-second clock are set. No. 4 is the motor 1 startup acceptance display, and the general-purpose bit address is set to 16 following. Note that the number of elements is 2, and 9 and the new 18 of the motor 1 startup acceptance and newly created 2-second clock are set. The newly created 2-second clock is set to No. 2 in the timing processing data of 372. The startup bit is set to always ON with positive logic, and the count stop bit is set to always ON with negative logic to perform blinking control, and the blinking ON time and blinking interval time are set. At this stage, the input processing data of 360 is completed, the logical processing data of 361 is completed from No. 1 to No. 5, the sequential step-by-step operation data of 362 is completed, the sequential step-by-step processing data of the motor 1 operation of 363 is completed except for the startup bit address of No. 2, the output processing data of 371 is completed except for the input part settings of No. 4 to No. 6, and the timing processing data of 372 is completed for No. 1 and No. 2. Finally, set the motor 2 with the same specification as the motor 1. That is, the sequential step processing data for the operation of the motor 2 at 370 is set. According to the specifications, it consists of three processes: startup reception by pressing the startup switch, initial startup in star connection, and switching to delta connection for startup. Also, since each process only transfers to the next No, the total number of branches associated with each No is 1, and they are set as "Motor 2 Startup Reception", "Motor 2 Initial Startup", and "Motor 2 Switching" in the name. Next, the general-purpose bit address of branch 1 and the reset bit address of branch 1 associated with the No are set. Here, the general-purpose bit address of branch 1 is set as 19, 20, 21, which are the subsequent numbers of the timing process, and the reset bit address of branch 1, except for No1, is set according to the previous No. There is no meaning to these numbers, and any value can be used as long as there is no duplication, but the reset bit address of branch 1 must be the address before the transfer. Here, the startup condition of No2 in the sequential step processing data for the operation of the motor 1 at 363 is set to 20. At this stage, the setting of the input processing data at 360 is completed, the setting of the sequential step operation data at 362 is also completed, the sequential step processing data for the operation of the motor 1 at 363 is completed, the output processing data from No1 to No3 at 371 is completed, the data of the output part from No4 to No6 is completed, and the No1 and No2 of the timing processing data at 372 are in a completed state. Next, the construction of trigger bits such as the absolute condition bit, startup bit, startup condition bit, branch condition bit, and branch permission bit for each No in the sequential step processing data for the operation of the motor 2 at 370 is performed. Since there is no branching, the branch condition bit and branch permission bit for each No are set to 1 all the time, which means they do nothing. Next, when analyzing the absolute condition bits of this process, since there are three elements: the stop switch is not pressed, the thermal is not tripped, and the emergency stop switch is not pressed, 361 logical processing data will be used. At this stage, since the general-purpose bit address of the 361 logical processing data can be determined, the next number in the sequential step-by-step processing of the motor 2 operation in 370 is set to 22. This number has no meaning and can be any value as long as there is no duplication. Next, when analyzing the start bits for each No, the start bit of No1 is the start switch from the input process, so it is set to 6. The start bit of No2 is set to 10 because the motor 1 is not starting in star connection. The start bit of No3 is set to use the timing processing data in 372 because, according to the specification, it starts 160 seconds after the star connection start of the motor 2. At this stage, since the general-purpose bit address of the 372 timing processing data can be determined, the next number in the logical processing is set to 23. This number has no meaning and can be any value as long as there is no duplication. Also, the start bit of the 372 timing processing data is set to 20 for the initial start of the motor 2 in the sequential step-by-step processing of the motor 2 operation in 370. Since the measurement is not stopped, the count stop bit is set to negative logic with always ON. Note that the control selection of No3 is ON delay. Here, also, return to the continuation of the construction of the trigger bit in the sequential step-by-step processing data of the motor 2 operation in 370 and analyze the start condition bits for each No. Then, the start condition bit of No1 has two elements because the motor 2 is not starting in star connection and not starting in delta connection either, so 361 logical processing data will be used. At this stage, since the general-purpose bit address of the 361 logical processing data can be determined, the next number in the timing processing is set to 24. This number has no meaning and can be any value as long as there is no duplication. Note that with the above settings, 20 and 21 in the sequential step-by-step processing data of the motor 2 operation in 370 can be set to the ON bit address and OFF bit address of the input part on hold in the output processing data in 371 for No4 and No5. To summarize up to this stage, the input processing data of 360 is completed, the logical processing data from No. 1 to No. 7 of 361 is completed, the sequential step operation data of 362 is completed, the sequential step processing data of the motor 1 operation of 363 is completed, and for the sequential step processing data of the motor 2 operation of 370, the data other than No. 2, where the starting condition is that the star connection of motor 2 is not started, is completed. For the output processing data of 371, the data of the output part and the data from No. 1 to No. 5 of the input part are completed, and the timing processing data of 372 is in a completed state. Next, in order to complete the control specification of motor 2, it is necessary to construct lamp control. Since there is one lamp, its lighting and blinking time represent the difference. When it blinks in 2 seconds, it accepts the switch. When it blinks in 1 second, the motor is driven in star connection. When it is lit, it represents that the motor is driven in delta connection. Therefore, it is decided to construct and handle the logical processing data of 361. Since there are three ways to light the lamp, it is decided to set them in No. 8 to No. 10 of the logical processing data of 361. No. 8 is the startup display of MC3, and the general-purpose bit address is set to the following 25. Note that the number of elements is 2, and 20 and 0 of the motor 2 initial startup and 1-second clock are set. No. 9 is the motor 2 startup acceptance display, and the general-purpose bit address is set to the following 26. Note that the number of elements is 2, and 19 and 18 of the motor 2 startup acceptance and 2-second clock are set. Thus, the setting of all processing data is completed. Note that the above setting of the processing data is carried out with the address value. However, since the numerical value is difficult for people to intuitively understand, when creating, it can be replaced with the name as a symbol.

[0086] Figure 38 is the detailed data diagram 1 / 2 of the logical processing with specification changes for driving two motors according to an embodiment of the present invention. Figure 39 is the detailed data diagram 2 / 2 of the logical processing with specification changes for driving two motors according to an embodiment of the present invention. In FIG. 38, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Excluding the parts sandwiched by the horizontal double lines and omitted, it is composed of five groups. In FIG. 39, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Excluding the parts sandwiched by the horizontal double lines and omitted, it is composed of four groups. On the right side of the vertical double line in the topmost group of FIG. 38, it consists of two items, the number of input processes and its numerical value. On the right side of the vertical double line in the remaining four groups of FIG. 38, it spans across FIG. 39 and consists of 15 items, namely No, blank, name, blank, blank, general-purpose bit address (10 / Hex), differentiation, logical selection, number of elements, element 1 bit address (10 / Hex), logic, element 2 bit address (10 / Hex), logic, element 3 bit address (10 / Hex), logic. Since the parts of FIG. 38 are omitted and to make the address structure easier to understand, a table of No-based starting addresses and change orders with four items, namely No, starting address, number of words, and change order, in one line is attached below the five groups. To explain in detail, for the logical processing data of No1, the starting address starts from 2759, the number of words is 22, and the change order is the 3rd. The reason why the starting address is 2759 is that the next address after the last address 2758 with the 2nd change order in FIG. 40 is 2759, and it is the 3rd change. The number of words varies depending on the name. Since the motor 1 absolute condition requires 8 words, it is 22 words. The next created motor 1 start condition of No2 has a starting address starting from 2195, the number of words is 24, and the change order is the 7th. The reason why the starting address is 2195 is that since the number of words in the previously created row does not increase, a new area was not required. The 20 words from 2175 used previously are set as unused areas. The same applies to No3 to No9 which are omitted. Figure 39, which spans with this Figure 38, is the same as the logical processing data of 361 in Figure 36. However, in Figure 39 that spans with Figure 38, from No3 to No9 are omitted, and only three blanks are added to the items for description. The reason there is no TP / PC display is that it is automatically assigned by the program. Regarding the memory type, external, quantity, processing, and transition are displayed. Here, "external" refers to the memory outside the PLC described in Figure 4, "processing" refers to the processing data (memory) of the device general-purpose memory described in Figure 4, "quantity" refers to the quantity data (memory) of the device general-purpose memory described in Figure 4, and "transition" refers to the transition data (memory) of the device general-purpose memory described in Figure 4.

[0087] Figure 40 is a detailed data diagram of the sequential step operation with specification changes for driving two motors according to an embodiment of the present invention. On the left side of the vertical double line, from top to bottom, TP / PC display, value, address, and memory type are grouped together, sandwiched by horizontal double lines, and composed of four groups. On the right side of the vertical double line in the topmost group, there are two items, namely the sequential step operation number and its value. On the right side of the vertical double line in the remaining three groups, there are ten items, namely No, blank, name, blank, blank, number of processes, blank. To make the address structure easier to understand, below the four groups, a table of the starting address by No and the change order with four items of No, starting address, number of words, and change order in one line is attached. To explain in detail, the sequential step operation data of No1 starts from the starting address of 2735, has 11 words, and the creation order is the first. The reason the starting address is 2735 is that in Figure 18, the last line created previously is No6 of the output processing data, and the next address after the last address 2734 is 2735, and it was created first. The number of words varies depending on the name. Since the motor 1 operation requires 6 words, it is 11 words. The sequential step operation data of No2 created next starts from the starting address of 2747, has 11 words, and the change order is the second. This is the same as the sequential step operation data of 362 in Fig. 36 and Fig. 40. In Fig. 15, only four blanks are added to the items for description. The reason for the absence of TP / PC display is that it is automatically assigned by the program. Regarding the memory type, although external, processing, quantity, and transfer are displayed, "external" refers to the memory outside the PLC described in Fig. 4, "processing" refers to the processing data (memory) of the device general-purpose memory described in Fig. 4, "quantity" refers to the quantity data (memory) of the device general-purpose memory described in Fig. 4, and "transfer" refers to the transfer data (memory) of the device general-purpose memory described in Fig. 4.

[0088] Fig. 41 is the detailed data diagram 1 / 2 of the motor 1 operation of the sequential step processing with specification changes for driving two motors according to an embodiment of the present invention. Fig. 42 is the detailed data diagram 2 / 2 of the motor 1 operation of the sequential step processing with specification changes for driving two motors according to an embodiment of the present invention. In Fig. 41, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Except for the parts sandwiched by the horizontal double line and omitted, it is composed of five groups. In Fig. 42, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Except for the parts sandwiched by the horizontal double line and omitted, it is composed of four groups. On the right side of the vertical double line of the topmost group in Fig. 41, it consists of two items, namely the sequential step processing number and its numerical value. On the right side of the vertical double line of the remaining four groups in Fig. 41, it spans across Fig. 42 and consists of 18 items, namely No, blank, name, blank, blank, absolute condition bit address (10 / Hex), logic, start bit address (10 / Hex), logic, start condition bit address (10 / Hex), logic, branch number, branch 1 condition bit address (10 / Hex), logic, branch 1 permission bit address (10 / Hex), logic, branch 1 general-purpose bit address (10 / Hex), branch 1 reset bit address (10 / Hex). For the address structure in Figure 41 to be easier to understand, below the five groupings, there is an attached table of the No, starting address, number of words, and change order, with four items per line as the starting address and change order by No. To explain in detail, the sequential stepping process data for No1 starts with a starting address of 2781, has 25 words, and a change order of the 5th. The reason the starting address is 2781 is that in Figures 38 and 39, the address after the last address 2780 with a change order of the 3rd is 2781, and for the 4th change order, in Figure 41 for No1, since it was a change with the same address, it became the 5th. The number of words varies by name. Since 8 words are required for the motor 1 start acceptance, it is 25 words. Next, the motor 1 initial start for No2 created starts with a starting address of 2806, has 25 words, and a change order of the 6th. The reason the starting address is 2781 is because it is a continuation from No1. Next, the motor 1 switching for No3 created starts with a starting address of 2831, has 23 words, and a change order of the 8th. The reason the starting address is 2831 is that in Figures 38 and 39, for No2, since the 7th change order was a change with the same address, it became the 8th. Figure 42 that straddles this Figure 41 is the same as the sequential stepping process data of 363 in Figure 36. Note that in Figure 42 that straddles Figure 41, only three blanks are added to the items for description. The absence of the TP / PC display is because it is automatically assigned by the program. Note that for the memory type, external, quantity, process, and transfer are displayed. External refers to the memory outside the PLC described in Figure 4, process refers to the process data (memory) of the device general-purpose memory described in Figure 4, quantity refers to the quantity data (memory) of the device general-purpose memory described in Figure 4, and transfer refers to the transfer data (memory) of the device general-purpose memory described in Figure 4.

[0089] Figure 43 is the detailed data diagram 1 / 2 of the sequential stepping process with specification changes for operating two motors in one embodiment according to the present invention for the motor 2 operation. Figure 44 is the detailed data diagram 2 / 2 of the motor 2 operation of the sequential step processing with specification changes for driving two motors according to an embodiment of the present invention. In Figure 43, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Except for the parts sandwiched by the horizontal double line and omitted, it is composed of five groups. In Figure 44, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Except for the parts sandwiched by the horizontal double line and omitted, it is composed of four groups. On the right side of the vertical double line of the topmost group in Figure 43, it consists of two items, the sequential step processing number and its numerical value. On the right side of the vertical double line of the remaining four groups in Figure 43, it spans across Figure 44 and consists of 18 items, No, blank, name, blank, blank, absolute condition bit address (10 / Hex), logic, start bit address (10 / Hex), logic, start condition bit address (10 / Hex), logic, branch number, branch 1 condition bit address (10 / Hex), logic, branch 1 permission bit address (10 / Hex), logic, branch 1 general-purpose bit address (10 / Hex), branch 1 reset bit address (10 / Hex). To make the address structure in Fig. 43 easier to understand, a table of the starting address, number of words, and change order for each No. is attached below the five grouped parts, with four items, namely No., starting address, number of words, and change order, in one line. To explain in detail, the sequential step processing data for No. 1 starts from the starting address 2876, has 25 words, and the change order is the 11th. The reason why the starting address is 2876 is that in Figs. 38 and 39, the address after the last address 2875 with the 9th change order is 2876, and for the 10th change order, in Fig. 46, for No. 2, since the change at the 10th change order is a change with the same address, it is the 11th. The number of words varies depending on the name. Since 8 words are required for the motor 2 start acceptance, it is 25 words. Next, the motor 2 initial start for No. 2 created starts from the starting address 2901, has 25 words, and the change order is the 12th. The reason why the starting address is 2901 is because it is a continuation from No. 1. Next, the motor 2 switching for No. 3 created starts from the starting address 2926, has 23 words, and the change order is the 14th. The reason why the starting address is 2926 is that in Figs. 38 and 39, for No. 7, since the change at the 13th change order is a change with the same address, it is the 14th. Fig. 44 that straddles this Fig. 43 is the same as the sequential step processing data of 370 in Fig. 37. Note that in Fig. 44 that straddles Fig. 43, only three blanks are added to the items for description. The absence of the TP / PC display is because it is automatically assigned by the program. Note that for the memory type, external, quantity, processing, and transfer are displayed. External refers to the memory outside the PLC described in Fig. 4, processing refers to the processing data (memory) of the device general-purpose memory described in Fig. 4, quantity refers to the quantity data (memory) of the device general-purpose memory described in Fig. 4, and transfer refers to the transfer data (memory) of the device general-purpose memory described in Fig. 4.

[0090] Fig. 45 is a detailed data diagram of the output processing with specification changes for driving two motors according to an embodiment of the present invention. On the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. They are sandwiched by horizontal double lines and, except for the omitted parts, are composed of five groups. On the right side of the vertical double line in the topmost group, there are two items, namely the number of output processes and its value. On the right side of the vertical double line in the remaining four groups, there are eleven items, namely No, blank, name, blank, blank, ON bit address (10 / Hex), logic, OFF bit address (10 / Hex), logic, device selection, and actual address (10 / Hex). Since it is omitted and to make the address structure easier to understand, under the five groups, there is an address table by No with four items, namely No, start address, number of words, and creation order, presented in one line. To explain in detail, the output process data of No1 starts with a start address of 2597, has 23 words, and is the 22nd in the change order. The reason why the start address is 2597 is that it is the same as all the addresses and names in Figure 18, including the following. This Figure 45 is the same as the 371 output process data in Figure 37. However, in Figure 45, from No3 to No5 are omitted, and only three blanks are added to the items for description. The absence of the TP / PC display is because it is automatically assigned by the program. Regarding the memory type, external, process, quantity, and transfer are shown. External refers to the memory outside the PLC described in Figure 4, process refers to the process data (memory) in the device general-purpose memory described in Figure 4, quantity refers to the quantity data (memory) in the device general-purpose memory described in Figure 4, and transfer refers to the transfer data (memory) in the device general-purpose memory described in Figure 4.

[0091] Figure 46 is the detailed data diagram 1 / 2 of the timing process with specification changes for driving two motors according to an embodiment of the present invention. Figure 47 is the detailed data diagram 2 / 2 of the timing process with specification changes for driving two motors according to an embodiment of the present invention. In Fig. 46, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Except for the parts sandwiched by the horizontal double lines and omitted, it is composed of four groups. In Fig. 47, on the left side of the vertical double line, from top to bottom, the TP / PC display, value, address, and memory type are grouped together. Except for the parts sandwiched by the horizontal double lines and omitted, it is composed of three groups. On the right side of the vertical double line in the topmost group of Fig. 46, it consists of two items, the number of timing processes and its numerical value. On the right side of the vertical double line in the remaining three groups of Fig. 46, it spans across Fig. 47 and consists of 16 items, namely No, blank, name, blank, blank, control selection, start bit address (10 / Hex), logic, count stop bit address (10 / Hex), logic, blink ON time, blink interval time, elapsed time, general-purpose bit address (10 / Hex), and differentiation. To make the address structure in Fig. 46 easier to understand, below the four groups, a table of the starting address, number of words, and order of change for each No is attached, with four items, No, starting address, number of words, and order of change, in one line. To explain in detail, for the timing process data of No1, the starting address starts from 2539, the number of words is 29, and the order of change is the 4th. The reason why the starting address is 2539 is that the same address as when it was created is being used. The same is true for No2 with the order of change being the 10th. For the timing process data of No3, the starting address starts from 2949, the number of words is 21, and the order of creation is the 16th. The reason why the starting address is 2949 is that the last address with the order of change being the 14th in Figs. 43 and 44 is 2948, and the next is 2949. Additionally, the address with the order of change being the 15th in Fig. 38 is using the address at the time of creation. Figure 47, which spans with this Figure 46, is the same as the timing processing data of 372 in Figure 37. However, it is only described with three blanks added to the items. The reason there is no TP / PC display is that it is automatically assigned by the program. Regarding the memory type, external, quantity, processing, and transition are displayed. Here, "external" refers to the memory outside the PLC described in Figure 4, "processing" refers to the processing data (memory) of the device general-purpose memory described in Figure 4, "quantity" refers to the quantity data (memory) of the device general-purpose memory described in Figure 4, and "transition" refers to the transition data (memory) of the device general-purpose memory described in Figure 4.

[0092] Figure 48 is the ladder program circuit diagram 1 / 7 of the sequential step operation and processing according to an embodiment of the present invention. Figure 49 is the ladder program circuit diagram 2 / 7 of the sequential step operation and processing according to an embodiment of the present invention. Figure 50 is the ladder program circuit diagram 3 / 7 of the sequential step operation and processing according to an embodiment of the present invention. Figure 51 is the ladder program circuit diagram 4 / 7 of the sequential step operation and processing according to an embodiment of the present invention. Figure 52 is the ladder program circuit diagram 5 / 7 of the sequential step operation and processing according to an embodiment of the present invention. Figure 53 is the ladder program circuit diagram 6 / 7 of the sequential step operation and processing according to an embodiment of the present invention. Figure 54 is the ladder program circuit diagram 7 / 7 of the sequential step operation and processing according to an embodiment of the present invention. That is, FIGS. 48 to 49 are a series of ladder program circuit diagrams for sequential step processing. This ladder program circuit diagram uses the program instructions of a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation. While changing the address with a modification register, processing is performed for each one processing number, one branch, and one work number. With a repeat instruction, the number of branches is repeated. Further, when the repetition of the number of branches is completed, the number of processes is repeated. Further, when the repetition of the number of processes is completed, the number of operations is repeated. Blocks 480 and 481 are preprocessing before performing the process, and blocks 483 to 51B are performing the process. From 520 to 53F, from 540 to 543, from 544 to 547, and from 548 to 54C are four subroutine programs. The following is a detailed explanation for each block. The transfer instruction GOEND of 480 transfers to the END of this sequential step processing program without performing this sequential step processing when the contact for execution permission determined in the identification and initial processing program and the number of sequential step operations determined by the user is 0. With the transfer instruction MOV of 481, the starting address of the sequential step operation data determined in the identification and initial processing program is transferred to the general-purpose device 1. The repeat instruction (1) FOR of 482 is paired with the repeat instruction (1) NEXT of 51B, and here, the repetition is performed for the number of sequential step operations. With the call instruction CALL of 483, the addition process 1 of the number is called and executed. With the arithmetic instruction + (addition) of 484, the interval up to the next work number address is added to the general-purpose device 1 and stored in the modification register 20. With the transfer instruction MOV of 485, the general-purpose device modified by the modification register 20 is transferred to the general-purpose device 2. With the arithmetic instruction + (addition) of 486, the interval up to the number of processes is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 487, the general-purpose device modified by the modification register 20 is transferred to the general-purpose device 3. In 488, with the arithmetic instruction + (addition), the interval from the processing number start address is added to the modified register 20 and stored in the modified register 20. In 489, with the transfer instruction MOV, the general-purpose device modified by the modified register 20 is transferred to the general-purpose device 4. In 48A, with the transfer instruction MOV, the general-purpose device 4 is transferred to the general-purpose device 6. In 48B, the loop instruction (2) FOR in 517 pairs with the loop instruction (2) NEXT, and here, the loop is performed for the number of sequential step processes. In 48C, with the call instruction CALL, the addition process 2 of the quantity is called and executed. In 48D, with the arithmetic instruction +, the interval to the next processing number address is added to the general-purpose device 4 and stored in the modified register 20. In 48E, with the transfer instruction MOV, the general-purpose device with the modified register 20 is transferred to the general-purpose device 5. In 48F, with the arithmetic instruction +, the interval to the absolute condition bit address is added to the modified register 20 and stored in the modified register 20. In 48G, with the transfer instruction MOV, the general-purpose device with the modified register 20 is transferred to the modified register 1. In 48H, with the arithmetic instruction +, the interval to the logic of the absolute condition is added to the modified register 20 and stored in the modified register 20. In 48J, with the transfer instruction MOV, the general-purpose device with the modified register 20 is transferred to the modified register 9. In 490, with the arithmetic instruction +, the interval to the start bit address is added to the modified register 20 and stored in the modified register 20. In 491, with the transfer instruction MOV, the general-purpose device with the modified register 20 is transferred to the modified register 2. In 492, with the arithmetic instruction +, the interval to the logic of the start bit is added to the modified register 20 and stored in the modified register 20. In 493, with the transfer instruction MOV, the general-purpose device with the modified register 20 is transferred to the modified register 10. With the arithmetic instruction + of 494, the interval up to the activation condition bit address is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 495, the general-purpose device with the modification register 20 is transferred to the modification register 3. With the arithmetic instruction + of 496, the interval up to the logic of the activation condition bit is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 497, the general-purpose device with the modification register 20 is transferred to the modification register 11. With the arithmetic instruction + of 498, the interval up to the branch number is added to the modification register 20 and stored in the modification register 20. With the transfer instruction MOV of 499, the general-purpose device with the modification register 20 is transferred to the modification register 4. With the arithmetic instruction + of 49A, the interval of the branch 1 condition bit address is added to the modification register 20 and stored in the general-purpose device 10. With the arithmetic instruction + of 49B, the interval of the logic of the branch 1 condition bit is added to the general-purpose device 10 and stored in the general-purpose device 11. With the arithmetic instruction + of 49C, the interval of the branch 1 permission bit address is added to the general-purpose device 11 and stored in the general-purpose device 12. With the arithmetic instruction + of 49D, the interval of the logic of the branch 1 permission bit is added to the general-purpose device 12 and stored in the general-purpose device 13. With the arithmetic instruction + of 49E, the interval of the branch 1 general-purpose bit address is added to the general-purpose device 13 and stored in the general-purpose device 14. With the arithmetic instruction + of 49F, the interval of the branch 1 reset bit address is added to the general-purpose device 14 and stored in the general-purpose device 15. With the arithmetic instruction + of 49G, the intervals of both the branch 1 condition bit address and the logic are added and stored in the general-purpose device 7. With the arithmetic instruction + of 49H, the interval of the branch 1 permission bit address is added to the general-purpose device 7 and stored in the general-purpose device 7. With the arithmetic instruction + of 49J, the interval of the logic of the branch 1 permission bit is added to the general-purpose device 7 and stored in the general-purpose device 7. For 49K, with the arithmetic instruction +, the interval of the general-purpose device 7 for the general-purpose bit address 1 is added and stored in the general-purpose device 7. For 49L, with the arithmetic instruction +, the interval of the general-purpose device 7 for the reset bit address 1 is added and stored in the general-purpose device 7. For 49M, with the transfer instruction MOV, 0 is transferred to the general-purpose device 8. For 500, the loop instruction (3) FOR pairs with the loop instruction (3) NEXT of 513. Here, the loop is performed for the number of general-purpose devices with the modification register 4. For 501, with the arithmetic instruction *, the general-purpose device 8 is multiplied by the general-purpose device 7 and stored in the general-purpose device 7. For 502, with the arithmetic instruction +, the general-purpose device 9 is added to the general-purpose device 10 and stored in the modification register 20. For 503, with the transfer instruction MOV, the general-purpose device with the modification register 20 is transferred to the modification register 5. For 504, with the arithmetic instruction +, the general-purpose device 7 is added to the general-purpose device 9 and stored in the modification register 20. For 505, with the transfer instruction MOV, the general-purpose device with the modification register 20 is transferred to the modification register 12. For 506, with the arithmetic instruction +, the general-purpose device 7 is added to the general-purpose device 10 and stored in the modification register 20. For 507, with the transfer instruction MOV, the general-purpose device with the modification register 20 is transferred to the modification register 6. For 508, with the arithmetic instruction +, the general-purpose device 7 is added to the general-purpose device 11 and stored in the modification register 20. For 509, with the transfer instruction MOV, the general-purpose device with the modification register 20 is transferred to the modification register 13. For 50A, with the arithmetic instruction +, the general-purpose device 7 is added to the general-purpose device 12 and stored in the modification register 20. For 50B, with the transfer instruction MOV, the general-purpose device with the modification register 20 is transferred to the modification register 7. For 50C, with the arithmetic instruction +, the general-purpose device 7 is added to the general-purpose device 13 and stored in the modification register 20. With the transfer instruction MOV of 50D, a general-purpose device with a modification register 20 is transferred to the modification register 8. With the call instruction CALL of 50E, according to the logic of the absolute condition bit, if the general-purpose bit modified by the modification register 1 is deactivated, the subroutine of the all-general-purpose bit reset process of 520 is called. With the arithmetic instruction SET of 50F, according to the logic of the absolute condition bit, if the general-purpose bit modified by the modification register 1 is deactivated, the general-purpose bit during order discard is set (activated). With the loop instruction BREAK of 50G, according to the logic of the absolute condition bit, if the general-purpose bit modified by the modification register 1 is deactivated, the loop instruction (3) is discarded and the process moves to the loop completion position 1 pointer. With the arithmetic instruction RST of 510, according to the logic of the absolute condition bit, if the general-purpose bit modified by the modification register 1 is activated, and according to the logic of the start bit, if the general-purpose bit modified by the modification register 2 is activated, and according to the logic of the start condition bit, if the general-purpose bit modified by the modification register 3 is activated, and According to the logic of the branch condition bit, if the general-purpose bit modified by the modification register 5 is activated, and according to the logic of the branch permission bit, if the general-purpose bit modified by the modification register 6 is activated, the general-purpose bit with the modification R8 is reset. With the arithmetic instruction SET of 511, according to the logic of the absolute condition bit, if the general-purpose bit modified by the modification register 1 is activated, and according to the logic of the start bit, if the general-purpose bit modified by the modification register 2 is activated, and according to the logic of the start condition bit, if the general-purpose bit modified by the modification register 3 is activated, and According to the logic of the branch condition bit, if the general-purpose bit modified by the modification register 5 is activated, and according to the logic of the branch permission bit, if the general-purpose bit modified by the modification register 6 is activated, the general-purpose bit with the modification register 7 is set. With the arithmetic instruction INC of 512, 1 is added to the general-purpose device 6. As a result, when repeating, the values of each modification register for the next branch are changed. The NEXT of the repetitive instruction (3), which pairs with the FOR of the repetitive instruction (3), returns to the FOR of the repetitive instruction (3) until the number of repetitions is exceeded, and repeats the subsequent instructions. The repetitive completion position 1 pointer of 514 is the destination of the BREAK of the repetitive instruction of 50G. If the general-purpose bit during order discard is activated, the BREAK of the repetitive instruction of 515 discards the repetitive instruction (2) and transfers to the repetitive completion position 2 pointer. In the MOV transfer instruction of 516, the general-purpose device 4 is transferred to the general-purpose device 3. The NEXT of the repetitive instruction (2), which pairs with the FOR of the repetitive instruction (2), returns to the FOR of the repetitive instruction (2) until the number of repetitions is exceeded, and repeats the subsequent instructions. The repetitive completion position 2 pointer of 518 is the destination of the BREAK of the repetitive instruction of 515. If the general-purpose bit during order discard is activated, the RST operation instruction of 519 resets (deactivates) the general-purpose bit during order discard. In the MOV transfer instruction of 51A, the general-purpose device 2 is transferred to the general-purpose device 1. The NEXT of the repetitive instruction (1), which pairs with the FOR of the repetitive instruction (1), returns to the FOR of the repetitive instruction (1) until the number of repetitions is exceeded, and repeats the subsequent instructions. The FEND structural instruction of 51C ends this sequential step processing program. The all general-purpose bit reset processing pointer of 520 is the call destination for the CALL instruction of 50E. In the MOV transfer instruction of 521, the general-purpose device 1 is transferred to the general-purpose device 20. In the MOV transfer instruction of 522, the general-purpose device with modifier register 20 is transferred to the general-purpose device 14. The FOR of the repetitive instruction (4) of 523 pairs with the NEXT of the repetitive instruction (4) of 53E, and here, it repeats for the number of sequential step processes. The CALL instruction of 524 calls and executes the addition process 3 of the quantity. With the arithmetic instruction + of 525, the interval up to the next processing number address is added to the general-purpose device 16 and stored in the modified register 20. With the transfer instruction MOV of 526, the general-purpose device with the modified register 20 is transferred to the general-purpose device 17. With the arithmetic instruction + of 527, the interval up to the absolute condition bit address is added to the modified register 20 and stored in the modified register 20. With the arithmetic instruction + of 528, the interval up to the logic of the absolute condition is added to the modified register 20 and stored in the modified register 20. With the arithmetic instruction + of 529, the interval up to the start bit address is added to the modified register 20 and stored in the modified register 20. With the arithmetic instruction + of 52A, the interval up to the logic of the start bit is added to the modified register 20 and stored in the modified register 20. With the arithmetic instruction + of 52B, the interval up to the start condition bit address is added to the modified register 20 and stored in the modified register 20. With the arithmetic instruction + of 52C, the interval up to the logic of the start condition bit is added to the modified register 20 and stored in the modified register 20. With the arithmetic instruction + of 52D, the interval up to the branch number is added to the modified register 20 and stored in the modified register 20. With the transfer instruction MOV of 52E, the general-purpose device with the modified register 20 is transferred to the modified register 4. With the arithmetic instruction + of 52F, the interval of the branch 1 condition bit address is added to the modified register 20 and stored in the general-purpose device 10. With the arithmetic instruction + of 52G, the interval of the logic of the branch 1 condition bit is added to the general-purpose device 10 and stored in the general-purpose device 11. With the arithmetic instruction + of 52H, the interval of the branch 1 permission bit address is added to the general-purpose device 11 and stored in the general-purpose device 12. With the arithmetic instruction + of 52J, the interval of the logic of the branch 1 permission bit is added to the general-purpose device 12 and stored in the general-purpose device 13. For 52K, with the arithmetic instruction +, the interval of the general-purpose bit address of branch 1 is added to the general-purpose device 13 and stored in the general-purpose device 14. For 52L, with the arithmetic instruction +, the interval of the reset bit address of branch 1 is added to the general-purpose device 14 and stored in the general-purpose device 15. For 530, with the arithmetic instruction +, the intervals of both the conditional bit address of branch 1 and the logic are added and stored in the general-purpose device 7. For 531, with the arithmetic instruction +, the interval of the permission bit address of branch 1 is added to the general-purpose device 7 and stored in the general-purpose device 7. For 532, with the arithmetic instruction +, the interval of the logic of the permission bit of branch 1 is added to the general-purpose device 7 and stored in the general-purpose device 7. For 533, with the arithmetic instruction +, the interval of the general-purpose bit address of branch 1 is added to the general-purpose device 7 and stored in the general-purpose device 7. For 534, with the arithmetic instruction +, the interval of the reset bit address of branch 1 is added to the general-purpose device 7 and stored in the general-purpose device 7. For 535, with the transfer instruction MOV, 0 is transferred to the general-purpose device 8. For 536, the loop instruction (5) FOR pairs with the loop instruction (5) NEXT of 53E. Here, the loop is performed for the number of general-purpose devices with modification register 4. For 537, with the arithmetic instruction *, the general-purpose device 8 is multiplied by the general-purpose device 7 and stored in the general-purpose device 9. For 538, with the arithmetic instruction +, the general-purpose device 9 is added to the general-purpose device 10 and stored in the modification register 20. For 539, with the transfer instruction MOV, the general-purpose device with modification register 20 is transferred to the modification register 7. For 53A, with the arithmetic instruction RST, the general-purpose bit with modification register 7 is reset (deactivated). For 53B, with the arithmetic instruction INC, 1 is added to the general-purpose device 8 for loop preparation. This changes the value of the next branch number when looping. The NEXT of 53C, the loop instruction (5), pairs with the FOR of the loop instruction (5) and returns to the FOR of the loop instruction until the loop count is exceeded, and repeats the subsequent instructions. In 53D, with the transfer instruction MOV, for loop preparation, the general-purpose device 17 is transferred to the general-purpose device 16. Thereby, when repeating, the values of each modification register for the next No. are changed. The NEXT of 53E, the loop instruction (4), pairs with the FOR of the loop instruction (4) and returns to the FOR of the loop instruction until the loop count is exceeded, and repeats the subsequent instructions. In 53F, with the return call instruction RET, the call is completed and the process moves to the next of the call instruction of 50E. The count addition process 1 pointer of 540 is the call destination for the call instruction CALL of 483. In 541, with the arithmetic instruction + (addition), 1 is added to the general-purpose device 1 and stored in the modification register 20. In 542, with the arithmetic instruction + (addition), the modification register 20 is added to the general-purpose device with the modification register 20 and stored in the general-purpose device 1. In 543, with the return call instruction RET, the call is completed and the process moves to the next of the call instruction of 483. The count addition process 2 pointer of 544 is the call destination for the call instruction CALL of 48C. In 545, with the arithmetic instruction + (addition), 1 is added to the general-purpose device 4 and stored in the modification register 20. In 546, with the arithmetic instruction + (addition), the modification register 20 is added to the general-purpose device with the modification register 20 and stored in the general-purpose device 4. In 547, with the return call instruction RET, the call is completed and the process moves to the next of the call instruction of 48C. The count addition process 3 pointer of 548 is the call destination for the call instruction CALL of 524. In 549, with the arithmetic instruction + (addition), 1 is added to the general-purpose device 16 and stored in the modification register 20. In 54A, with the arithmetic instruction + (addition), the modification register 20 is added to the general-purpose device with the modification register 20 and stored in the general-purpose device 16. In 54B, upon the return instruction RET, the call is completed and the process proceeds to the next instruction of the call at 524. In 54C, upon the structure instruction END, the program file ends.

[0093] (Concept) In this sequential step-by-step process, since data can be freely set, the process greatly depends on the discretion of the data creator. Here, a flowchart and descriptions of operations and processes will be provided. A flowchart created to control equipment or devices represents each step of a process, which is a characteristic of a dynamic system, or each means, procedure, or operation for obtaining an answer to a problem, in boxes describing their content. The flow is represented by lines and arrows between those boxes, or by dispersing those lines and arrows, or by being composed of multiple flowcharts, thereby expressing simple to complex processes and algorithms. Each step of a process that is a characteristic of a dynamic system refers to each process in process control. Furthermore, a dynamic system is considered to be one that takes time to return a certain result or does not reach a certain result. Each means, procedure, or operation for obtaining an answer to a problem refers to performing a function that converts some input into an output. Specifically, it could be when a sensor turns ON, when a set speed is reached, or when the temperature reaches the set temperature. In this invention, a plurality of flowcharts created to control equipment or devices are replaced with a structure (operation) that places the processes under control. That is, to control equipment or devices, there may be multiple independent flowcharts or flowcharts that affect other flowcharts, so multiple processes are managed under the name of operations. Specifically, in the sequential step-by-step operation data of 362 in Figure 36, the operation of Motor 1 No. 1 and the operation of Motor 2 No. 2 are each independent and have a relationship where they affect each other. In addition, each step of the process, each means, procedure, and operation in the flowchart created to control a device or apparatus is replaced with a series of multiple data associated with the order of processing in sequential step processing. That is, the data in sequential step processing takes a series of multiple data associated with the order of processing as one unit, and by repeating the processing with a series of multiple data associated with the order of processing as one unit, it corresponds to an increase or decrease in the number of steps of each process, means, procedure, and operation count in the flowchart. In addition, the branched or distributed flow in the flowchart created to control a device or apparatus is replaced by providing items corresponding to the number of branches and the number of branches. In the flowchart created to control a device or apparatus, the destination may be different depending on judgments or conditions, and in some cases, the number of destinations may increase depending on judgments or conditions, and furthermore, it may even migrate to an external flowchart. Considering the above cases, it is not possible to migrate only with its own flowchart, and since the situation of the other flowchart must be considered, a branch permission bit is provided for each item for each number of branches. Specifically, this is because when transfer devices of the same structure are arranged continuously, or when the previous device is not at the receiving position, etc., it is necessary to stop the subsequent device. Basically, in one flowchart, only one step or procedure is executed, but it is not completely prohibited and is left to the discretion of the creator. In addition, the content of the boxes in the flowchart is all considered to be derived from bit address data and selection data. This also holds true for bits created in external processing. Selection data is, for example, data on whether the bit is activated in positive logic or negative logic, and is determined by a pre-determined numerical value. Also, when a series of trigger bits, namely absolute condition bits, startup bits, startup condition bits, branch condition bits, and branch permission bits, which are modified by a modified register with bit address data set based on selection data, are activated, the bits modified by the modified register with bit address data set are activated, and the No that causes the No for monitoring the activation of the bits to be inactivated. That is, it is possible to know up to which step of each process or procedure has been completed by the activation of the bits, and the bits continue to be activated until the currently monitored series of trigger bits are activated. With the above replacements and the like, every algorithm is replaced by a change in data.

[0094] Figure 55 is a flowchart diagram of a programmable logic controller (PLC) according to an embodiment of the present invention. At 550 in Figure 55, when the power is turned from OFF to ON, or from STOP to RUN, the programmable logic controller (PLC) starts up. First, the program check process at 551 is performed. Subsequently, the I / O refresh at 552 is performed, and the process proceeds to END process 1 at 553. The identification and initial processing program at 555 are performed in the specified order, and the process proceeds to END process 2 at 554. Subsequently, the I / O refresh at 552 is performed, the process proceeds to END process 1 at 553, and the differential reset processing program for the timing process at 556, the input device data processing program at 557, the device data arithmetic processing (input reference) program at 558, the input processing program at 559, the interface processing program at 55A, the logic processing program at 55B, the sequential step processing program at 55C, the device data arithmetic processing (output reference) program at 55D, and the output processing program at 55E are performed in the specified order, the process proceeds to END process 2 at 554, and it returns before the I / O refresh at 552 and is repeated until the power is turned from ON to OFF, or from RUN to STOP. That is, the 25 initial execution type program groups in the flowchart of FIG. 2 are identified and processed as one program of the 555 initial execution type programs, the 26 scan execution type program groups are processed as 10 programs including the 556 timing processing differential reset processing program, the 557 input device data processing program, the 558 device data arithmetic processing (input standard) program, the 559 input processing program, the 55A interface processing program, the 55B logic processing program, the 55C sequential step processing program, the 55D device data arithmetic processing (output standard) program, and the 55E output processing program. The 27 fixed cycle execution type program groups are processed as one program of the 55F timing processing program. Also, without using the 28 standby type program groups, an algorithm function equivalent to the flowchart of FIG. 2 is obtained. With the above alone, all algorithms can be constructed. However, if you want to apply program assets that have been created and have a track record, or to handle complex arithmetic calculations, etc., programs can be added. However, the insertion position is important. When adding an initial execution type program, it can be inserted either between the END process 1 of 553 and the identification of 555 and the initial processing program before repeating, or between the identification of 555 and the initial processing program and the I / O refresh of 552. It also depends on whether it affects or is affected by the identification and initial processing program of 555 in the present invention. Also, when adding a scan execution type program, it will be inserted between the END process 1 of 553 and the END process 2 of 554 within the loop. However, it can be inserted anywhere from the micro-differentiated reset processing program of the timing process of 556 to the output processing program of 55E. Therefore, it is necessary to pay attention to how it affects or is affected by the present invention. In particular, from the micro-differentiated reset processing program of the timing process of 556 to the interface processing program of 55A, it is for the processing of the incoming items, and from the logical processing program of 55B to the output processing program of 55E, it is for the processing of the outgoing items, so extreme care is required. Note that once a program is inserted, it will no longer be a general-purpose program but a custom-made program, so sufficient attention is necessary. Here, because the differential reset processing program for the timing process of 556 is at the beginning of the scan execution type program of the present invention, first, it is necessary to explain differential processing. Differential processing is one of the methods of commands and outputs. Usually, when a condition is satisfied, the command continues to be executed or the output continues to be output. It is also said to output at a level, and when the condition is no longer satisfied, the command being executed stops or the output stops. When this is differentiated, even if it is repeated, it is changed to an operation where the command is executed only for one scan or the output is output only for one scan. Further, even if the condition continues to be satisfied, once the command is executed or the output is output, the command will not be executed or the output will not be output until the condition is no longer satisfied. Such a method of commands and outputs is called differential processing and is widely used. In the present invention, in order to simplify or because the conditions can be replaced by differential processing, the differential processing of commands is not deliberately performed. Furthermore, it must also be explained that only the timing processing program that controls the output by time measurement is a fixed-cycle execution type program. Although there are existing timers in a programmable logic controller (PLC), many of those existing timers do not operate normally in the repetitive structure of the program with numbers as units, and they use a fixed-cycle execution type program by counting with a fixed cycle as a unit. If it outputs at a level, there is no problem, but when it is differentiated, in a scan execution type program, depending on the time of one scan and the interval of the fixed cycle, there is a risk of missing it, so as a scan execution type program outside the fixed-cycle execution program, the pulse width is differentiated not as one scan but as more than one scan and less than two scans. There is no particular reason why the differential reset processing program for the timing process is at the beginning of the scan execution type program of the present invention. It is just in the same position because the differential processing occurring in other scan execution type programs is processed at the beginning after one scan. There is no major problem as long as the input device data processing program that compares device data in the first half sandwiching the scan execution type program, the device data arithmetic processing (input standard) program that executes arithmetic instructions, and the input processing program do not exceed the logical processing program, sequential step processing program, device data arithmetic processing (output standard) program, and output processing program in the second half that determine the output. However, since the program position in the first half is likely to use the results of the previous program, the input device data processing program, device data arithmetic processing (input standard) program, and input processing program are in this order. But if you are prepared for a one-scan delay, it will not be a major problem. The same applies to the programs in the second half. Note that in the present invention, it is a program for supporting all algorithms by simply changing device data through the construction of a conventional program without changing an existing programmable logic controller (PLC). However, when a manufacturer that manufactures a programmable logic controller (PLC) constructs the present invention, in order to eliminate the risk of change, the program may be lowered to the same level as the I / O refresh process and END process that cannot be touched by the person creating the program. Furthermore, the concept of a program may be eliminated altogether, and it may be made into a data table logic controller (DLC).

[0095] FIG. 56 is a relational diagram of main programs according to an embodiment of the present invention. The main program is a program essential for implementing various algorithms. It consists of eight programs: a 561 input processing program that is subject to constraints from 560 input processing device data set on the touch panel (TP) screen, a 563 logical processing program that is subject to constraints from 562 logical processing device data set on the touch panel (TP) screen, a 565 sequential step processing program that is subject to constraints from 564 sequential step processing device data set on the touch panel (TP) screen, a 567 output processing program that is subject to constraints from 566 output processing device data set on the touch panel (TP) screen, a 569 input device data processing program that is subject to constraints from 568 input device data processing device data set on the touch panel (TP) screen, a 56B timing processing program that is subject to constraints from 56A timing processing device data set on the touch panel (TP) screen, a 56D device data arithmetic processing (input standard) program that is subject to constraints from 56C device data arithmetic processing (input standard) device data set on the touch panel (TP) screen, and a 56F device data arithmetic processing (output standard) program that is subject to constraints from 56E device data arithmetic processing (output standard) device data set on the touch panel (TP) screen. The dashed line and its arrow indicate the direction in which the general-purpose device bits (general-purpose bits) are generated and consumed. Also, the thick dashed line and its arrow indicate the direction in which the general-purpose device data is generated and consumed, while shifting the timing and so on. Finally, it releases the output device bits and output device data of the square protruding to the left to complete various algorithms. Note that the touch panel (TP) screen is controlled by interface processing.

[0096] Figure 57 is a device memory layout diagram used in each program according to an embodiment of the present invention. 570 is a representative device memory area of the physical memory area. Device memory contains different types of devices for each manufacturer, but representative devices are considered. From the beginning of the physical device memory area up to the first starting address of the device data used in Process 572, it is regarded as the initial constant area 571 and the touch panel display area. After this, from the first starting address of the device data used in Process 572 to the first starting address of the device data used in Process 573, there are the first and second data groups of the device data used in Process 572; from the first starting address of the device data used in Process 573 to the first starting address of the device data used in Process 574, there are the first and second data groups of the device data used in Process 573; from the first starting address of the device data used in Process 574 to the first starting address of the device data used in Process 575, there are the first and second data groups of the device data used in Process 574; from the first starting address of the device data used in Process 575 to the first starting address of the device data used in Process 576, there are the first and second data groups of the device data used in Process 575; from the first starting address of the device data used in Process 576 to the first starting address of the device data used in Process 577, there are the first and second data groups of the device data used in Process 576; from the first starting address of the device data used in Process 577 to the first starting address of the device data used in Process 578 (processing...), there is the first data group of the device data used in Process 577; from the first starting address of the device data used in Process 578 (processing...) to the first starting address of the device data used in Process 579 (processing n), there is the first data group of the device data used in the processing...; from the first starting address of the device data used in Process 579 (processing n) to the third starting address of the device data used in Process 57A (processing 1), there is the first data group of the device data used in Process 579 (processing n); from the third starting address of the device data used in Process 57A (processing 1) to the third starting address of the device data used in Process 57B (processing 2), there is the third data group of the device data used in Process 571.The third data group of the device data used in Process 2 from the third starting address of the device data used in Process 2 of 57B to the third starting address of the device data used in Process 3 of 57C, the third data group of the device data used in Process 3 from the third starting address of the device data used in Process 3 of 57C to the second starting address of the device data used in Process 6 of 57D, the second data group of the device data used in Process 6 from the second starting address of the device data used in Process 6 of 57D to the third starting address of the device data used in Process 4 of 57E, the third data group of the device data used in Process 4 from the third starting address of the device data used in Process 4 of 57E to the second starting address of the device data used in Process... of 57F, the second data group of the device data used in Process... from the second starting address of the device data used in Process... of 57F to the third starting address of the device data used in Process 5 of 57G, the third data group of the device data used in Process 5 from the third starting address of the device data used in Process 5 of 57G to the second starting address of the device data used in Process n of 57H, the second data group of the device data used in Process n from the second starting address of the device data used in Process n of 57H to the third starting address of the device data used in Process... of 57J, the third data group of the device data used in Process... from the third starting address of the device data used in Process... of 57J to the third starting address of the device data used in Process 6 of 57K, the third data group of the device data used in Process 6 from the third starting address of the device data used in Process 6 of 57K to the third starting address of the device data used in Process n of 57L, the third data group of the device data used in Process n from the third starting address of the device data used in Process n of 57L to the...th starting address of the device data used in Process 6 of 57M and the third and...th data groups of the device data used in Process n, the...th data group of the device data used in Process 6 from the...th starting address of the device data used in Process 6 of 57M to the...th starting address of the device data used in Process 4 of 57N,The...th data group of the device data used in process 4 from the...th starting address of the device data used in process 4 of 57N to the...th starting address of the device data used in process 2 of 57P, the...th data group of the device data used in process 2 from the...th starting address of the device data used in process 2 of 57P to the...th starting address of the device data used in process 3 of 57Q, the...th data group of the device data used in process 3 from the...th starting address of the device data used in process 3 of 57Q to the...th starting address of the device data used in process... of 57R, the...th data group of the device data used in process... from the...th starting address of the device data used in process... of 57R to the...th starting address of the device data used in process 1 of 57S, the...th data group of the device data used in process 1 from the...th starting address of the device data used in process 1 of 57S to the...th starting address of the device data used in process 5 of 57T, the...th data group of the device data used in process 5 from the...th starting address of the device data used in process 5 of 57T to the nth starting address of the device data used in process n of 57U, the nth data group of the device data used in process n from the nth starting address of the device data used in process n of 57U to the nth starting address of the device data used in process... of 57V, the nth data group of the device data used in process... from the nth starting address of the device data used in process... of 57V to the nth starting address of the device data used in process 6 of 57W, the nth data group of the device data used in process 6 from the nth starting address of the device data used in process 6 of 57W to the nth starting address of the device data used in process 5 of 57X, the nth data group of the device data used in process 5 from the nth starting address of the device data used in process 5 of 57X to the nth starting address of the device data used in process 4 of 57Y, the nth data group of the device data used in process 4 from the nth starting address of the device data used in process 4 of 57Y to the nth starting address of the device data used in process 3 of 57Z,The nth data group of the device data used in process 3 from the nth starting address of the device data used in process 3 of 57Z to the nth starting address of the device data used in process 2 of 57a, the nth data group of the device data used in process 2 from the nth starting address of the device data used in process 2 of 57a to the nth starting address of the device data used in process 1 of 57b, and the nth data group of the device data used in process 1 from the nth starting address of the device data used in process 1 of 57b to the starting address of the unused area of the device memory of 57c are used. This order is in the creation order, meaning it was created in this order. That is, even with exactly the same device, if the creation order changes, it will not be the same order, so this order also has no meaning. However, even if the size for each process number is not constant, the device memory can be densely packed, but for each process number, it is necessary to have as elements the return address value of the previous number and the destination address value of the next number.,

[0097] Note that there is no problem if the device memory area for that number becomes smaller, but if the device memory area for that number becomes larger, it must be newly created, so large holes will occur. Therefore, when the facilities and devices are stopped, it is necessary to have a countermeasure of constructing a program to fill the holes.,

[0098] FIG. 58 is a device memory layout diagram in which the device memory is rearranged for each process according to an embodiment of the present invention., This Figure 58 is a rearrangement of the device memory layout diagrams used in each program of Figure 57 for each process. This arrangement is an important arrangement for executing each processing program for each operation. 580 is Process 1, 581 is the element group of Process 1, 582 is the order of Process 1, 583 is the device data group of Process 1, 584 is Process 2, 585 is the element group of Process 2, 586 is the order of Process 2, 587 is the device data group of Process 2, 588 is Process 3, 589 is the element group of Process 3, 58A is the element group of Process 3, 58B is the device data group of Process 3, 58C is Process 4, 58D is the element group of Process 4, 58E is the order of Process 4, 58F is the device data group of Process 4, 58G is Process 5, 58H is the element group of Process 5, 58J is the order of Process 5, 58K is the device data group of Process 5, 58L is Process 6, 58M is the element group of Process 6, 58N is the order of Process 6, 58P is the device data group of Process 6, 58Q is Process..., 58R is the element group of Process..., 58S is the order of Process..., 58T is the device data group of Process..., 58U is Process n, 58V is the element group of Process n, 58W is the order of Process n, 58X is the device data group of Process n. To rearrange the device memory for each process, the first address value is stored in the initial setting data for each process, and the return address value of the previous number and the destination address value of the next number are stored for each process number. Programmatically speaking, it is not about rearrangement but about being able to easily reach the target element. Also, the arrangement and regulations of the elements are important, and as a rule, it is necessary to store the initial setting data and comments. For elements with variable sizes, such as character strings, for example, the number of words used for the element is provided as another single element. Furthermore, for elements with variable numbers of elements, such as the number of elements in a logical OR or logical AND (continuous numbers), for example, the number of words used for the element is provided as another single element. In the case of the logical OR and logical AND explicitly given as examples, the address and the logic (positive logic or negative logic) increase by two elements each. As another example, the same applies to the number of branches in sequential step processing, etc., where the branch condition bit address and its logic (positive logic or negative logic), the branch permission bit address and its logic (positive logic or negative logic), the branch general-purpose bit address, and the branch reset bit address increase by six elements each.

[0099] (Concept) Based on the detailed descriptions of FIGS. 57 and 58, further explanations are added. Generally, a memory is for storing, and there are those with and without power-off retention functions. Also, it is classified by function and area, such as program memory and each device memory. The memory of the present invention is a device memory that can retain power-off and store data, in which processing data is stored. The processing data is for realizing steps and algorithms. When processing is executed based on the processing data having a plurality of items, the processing data having the next plurality of items is replaced with a modification register, and further processing is executed until the processing data is exhausted. When it is exhausted, it returns to the beginning and the processing is repeated. If there are a plurality of processing data for different processes in this series of processing data, the number of processing data to be processed is different for each process, and the processing data of different processes cannot be arranged in the next empty area of the memory. Generally, it is performed by a method of providing an area in the memory for each process and arranging a plurality of processing data at equal intervals. There are many unused areas, not only a lot of waste, but also it cannot exceed the area determined by prediction. Therefore, as data other than the processing data having a plurality of items, the start address of the processing data having the next plurality of items to be executed and the start address of the processing data having the plurality of items executed last are added as transfer data to the processing data having a plurality of items for each process. By correcting the transfer data when adding, changing, or deleting the processing data beyond the area, not only can the processing data having a plurality of items with different processes mixed therein be continuously arranged in the memory, but also only the plurality of data having a plurality of items for the same process among the mixed processing data can be sequentially extracted based on the start address of the transfer data. Furthermore, when repeating a process for processing data having a plurality of items and data other than transition data, by adding the number of repetitions as repetition data, not only can the data be continuously arranged in memory even if the number of data between processes is different, but also it is possible to sequentially extract data based on the start address of the transition data. Incidentally, generally, data is arranged by providing a memory area with the maximum number of repetitions for each process.

[0100] FIG. 59 is a relationship diagram between the device memory and the display device memory of a certain process when using a touch panel (TP) according to an embodiment of the present invention and having a function for changing the device memory for each process with the touch panel (TP). In recent factories, physical switches, physical lamps, and physical digital switches are being replaced by touch panels (TP) as interfaces, except for parts related to safety, due to reasons such as reduction of wiring man-hours and physical size. The touch panel (TP), which began to spread under such circumstances, was sometimes considered a large input / output device in the early days, and the programmer of the programmable logic controller (PLC) program had to handle the touch panel (TP). These days, there are also touch panels (TP) that not only have the function of creating and changing the program of the programmable logic controller (PLC), but also have the function of creating and changing the program of the programmable logic controller (PLC). However, since the size and resolution of the touch panel (TP) also vary, and in some factories, the logo of the manufacturer may be displayed, or a screen unique to the device may be created, there is a tendency to create unique screen data. Since the gist of the present invention is the opposite, this is the presentation of that method. 590 in FIG. 59 is a device memory group in which the device memory of a certain process is rearranged. 591 is a group of numbers that can be displayed on the touch panel (TP). Here, although it is provisional, it is assumed to be 15 lines. That is, the maximum number of lines of that model is 15 lines. 592 is a display device data group on the device data group side of a certain process, 593 is a number variable group for the touch panel (TP), 594 is a display device data group on the touch panel (TP) side, 595 is a number as an element on the touch panel (TP) side, and 596 is a group of elements that can be displayed on the touch panel (TP). Here, although it is provisional, it is assumed to be 2 elements. That is, the maximum number of elements of that model is 2 elements. Assuming that the largest possible model is selected, in Fig. 59, the number variable group for the touch panel (TP) currently displayed on the display touch panel (TP) shows values from 7 to 21, that is, the value of D01-00 is 7, the value of D02-00 is 8, the value of D03-00 is 9, the value of D04-00 is 10, the value of D05-00 is 11, the value of D06-00 is 12, the value of D07-00 is 13, the value of D08-00 is 14, the value of D09-00 is 15, the value of D10-00 is 16, the value of D11-00 is 17, the value of D12-00 is 18, the value of D13-00 is 19, the value of D14-00 is 20, and the value of D15-00 is 21, and they are being displayed.Furthermore, among the element groups that can be displayed on the touch panel (TP) of 86, the values of 1 - 72 corresponding to D01 - 02 for 1 - 72, the values of 1 - 73 corresponding to D01 - 03 for 1 - 73, the values of 1 - 82 corresponding to D02 - 02 for 1 - 82, the values of 1 - 83 corresponding to D02 - 03 for 1 - 83, the values of 1 - 92 corresponding to D03 - 02 for 1 - 92, the values of 1 - 93 corresponding to D03 - 03 for 1 - 93, the values of 1 - 102 corresponding to D04 - 02 for 1 - 102, the values of 1 - 103 corresponding to D04 - 03 for 1 - 103, the values of 1 - 112 corresponding to D05 - 02 for 1 - 112, the values of 1 - 113 corresponding to D05 - 03 for 1 - 113, the values of 1 - 122 corresponding to D06 - 02 for 1 - 122, the values of 1 - 123 corresponding to D06 - 03 for 1 - 123, the values of 1 - 132 corresponding to D07 - 02 for 1 - 132, the values of 1 - 133 corresponding to D07 - 03 for 1 - 133, the values of 1 - 142 corresponding to D08 - 02 for 1 - 142, the values of 1 - 143 corresponding to D08 - 03 for 1 - 143, the values of 1 - 152 corresponding to D09 - 02 for 1 - 152, the values of 1 - 153 corresponding to D09 - 03 for 1 - 153, the values of 1 - 162 corresponding to D10 - 02 for 1 - 162, the values of 1 - 163 corresponding to D10 - 03 for 1 - 163, the values of 1 - 172 corresponding to D11 - 02 for 1 - 172, the values of 1 - 173 corresponding to D11 - 03 for 1 - 173, the values of 1 - 182 corresponding to D12 - 02 for 1 - 182, the values of 1 - 183 corresponding to D12 - 03 for 1 - 183, the values of 1 - 192 corresponding to D13 - 02 for 1 - 192, the values of 1 - 193 corresponding to D13 - 03 for 1 - 193, the values of 1 - 202 corresponding to D14 - 02 for 1 - 202, the values of 1 - 203 corresponding to D14 - 03 for 1 - 203, the values of 1 - 212 corresponding to D15 - 02 for 1 - 212, and the values of 1 - 213 corresponding to D15 - 03 for 1 - 213 are being displayed. When shifting in the direction of the up arrow or down arrow using the up shift switch and the down shift switch, the device data of the display device data group on the device data group side of a certain process of 592 changes. Therefore, for the corresponding device data, the device data of the number variable group for the touch panel (TP) of 593, the display device data group on the touch panel (TP) side of 594, and the element group that can be displayed on the touch panel (TP) of 596 are refreshed. When shifting in the direction of the right arrow or left arrow using the right shift switch and the left shift switch, the device data of the element group that can be displayed on the touch panel (TP) of 596 in the corresponding device data is refreshed. In models that do not reach the maximum number of lines or the maximum number of elements, separately from the number variable group for the touch panel (TP) of 593 and the element group that can be displayed on the touch panel (TP) of 596, a real number variable group for the touch panel (TP) and a real element group that can be displayed on the touch panel (TP) are provided, and they can be moved within the number variable group for the touch panel (TP) of 593 and the element group that can be displayed on the touch panel (TP) of 596. When reaching the upper limit or the lower limit, the device data of each necessary group is refreshed. The touch panel (TP) mentioned here is used as an interface.

[0101] Since the present invention changes data with one program, it must be compatible with various devices and facilities. As one of its features, a display memory is provided for each process. This is because when creating a screen, all addresses must be described for numerical display and comment display. It is also because the memory is managed with transition data and repetitive data as features of the present invention. That is, it is because the amount of data is unknown. As a mechanism, it is simple and is carried out by a method in which when the display memory is rewritten, the corresponding data is also rewritten. By using this method, the number of screen sheets can be aggregated.

[0102] FIG. 60 is a system relationship diagram of a programmable logic controller (PLC) and an engineering tool according to an embodiment of the present invention, which identifies the programmable logic controller (PLC) that can be executed and makes it executable only by the programmable logic controller (PLC). In FIG. 60, 600 is an engineering tool, 601 is a network, 602 is a programmable logic controller (PLC) A, 603 is a programmable logic controller (PLC) B, 604 is a programmable logic controller (PLC) C, 605 is a programmable logic controller (PLC) D, 606 is a programmable logic controller (PLC) n, 607 is a project file for the programmable logic controller (PLC) A, 608 is a project file for the programmable logic controller (PLC) B, 609 is a project file for the programmable logic controller (PLC) C, 60A is a project file for the programmable logic controller (PLC) D, and 60B is a project file for the programmable logic controller (PLC) n. In Figure 60, the engineering tool 600 contains a project file for programmable logic controller (PLC) A at 607, a project file for programmable logic controller (PLC) B at 608, a project file for programmable logic controller (PLC) C at 609, a project file for programmable logic controller (PLC) D at 60A, and a project file for programmable logic controller (PLC) n at 60B. Note that a project file is a data group consisting of a plurality of programs and parameters that describe the content for controlling the algorithm for operating a programmable logic controller (PLC). Further, it is unclear whether it was initially included via the network 601 or was there from the start, but the project file for programmable logic controller (PLC) A at 607 is written into programmable logic controller (PLC) A at 602, the project file for programmable logic controller (PLC) B at 608 is written into programmable logic controller (PLC) B at 603, the project file for programmable logic controller (PLC) C at 609 is written into programmable logic controller (PLC) C at 604, the project file for programmable logic controller (PLC) D at 60A is written into programmable logic controller (PLC) D at 605, and the project file for programmable logic controller (PLC) n at 60B is written into programmable logic controller (PLC) n at 606. The project file for the programmable logic controller (PLC) A of 607 contains the identification program described as A of the present invention, programs 1 to n of the present invention, and user programs 1 and 2 to nA created by the user. The project file for the programmable logic controller (PLC) B of 608 contains the identification program described as B of the present invention, programs 1 to n of the present invention, and user programs 3 and 4 to nB created by the user. The project file for the programmable logic controller (PLC) C of 609 contains user programs 5 and 6 to nC created by the user. The project file for the programmable logic controller (PLC) D of 60A contains the identification program described as D of the present invention and programs 1 to n of the present invention. The project file for the programmable logic controller (PLC) n of 60B contains the identification program described as D of the present invention, programs 1 to n of the present invention, and user programs 1 and 2 to nA created by the user. In the state as described above, since the unique data read by the programmable logic controller (PLC) A of 602 matches the data described in the identification program, both the program group of the present invention and the user program group operate. Since the unique data read by the programmable logic controller (PLC) B of 603 does not match the data described in the identification program, the program group of the present invention does not operate, and only the user program group operates. Since the programmable logic controller (PLC) C of 604 does not have the program group of the present invention, only the user program group operates. Since the unique data read by the programmable logic controller (PLC) D of 605 matches the data described in the identification program, the program group of the present invention operates, and since the user program group does not exist, it does not operate. Since the unique data read by the programmable logic controller (PLC) n of 603 does not match the data described in the identification program, the program group of the present invention does not operate, and only the user program group operates. In such a situation, it is presumed that those who use the 600 engineering tools can read and write the program group of the present invention, but at least they do not have the editing authority to view and modify the read program group. This is because to operate all programmable logic controllers (PLCs), it is easy to operate by rewriting the identification content described in the identification program of the project file of each programmable logic controller (PLC) with the 600 engineering tools. Depending on the difference in positions, the interests may be different, so it cannot be asserted, but for the present invention, authority and identification processing are important factors.

[0103] As a mechanism, it is simple. At the beginning of the program, the unique physical unique data of the microprocessor (MPU) is read from the program side and compared with the data in the program. If they do not match, the program jumps to the END of the program and the program ends. The unique physical unique data of the microprocessor (MPU) generally means the serial number, but when using a LAN (Local Area Network), it may also be the MAC address (Media Access Control address), or it may be arbitrarily set. When creating the program of the present invention, it is necessary to determine whether to write the unique data of the program as a constant or as initial data. Although this is only this operation, it becomes indistinguishable from a general program created individually. It is important to determine who will create the final version of the program of the present invention, who will sell the program of the present invention, who will create the data of the program of the present invention, who will verify whether the devices and apparatuses operating with the program of the present invention operate as specified, and who will use the devices and apparatuses operating with the program of the present invention. At production sites such as factories, access is prohibited, so for those with malicious intent, once the present invention is disclosed in this specification, it can be easily imitated. However, if the program is not analyzed, it can be prevented simply by mixing the legitimate program and the imitation program based on the purchase history and the like.

[0104] FIG. 61 is a device data setting diagram showing the common initial settings of one embodiment according to the present invention. 610 in FIG. 61 is a common initial data group. In FIG. 61, with respect to the two items of the number of programs and the start address of the initial device data, as described in FIG. 3, the number of programs may be affected by the model, and also varies depending on who creates the present invention and for what purpose. In this common initial setting, it is necessary to incorporate an empty area in advance so that items can be added in consideration of unforeseen situations.

[0105] FIG. 62 is a device data setting diagram showing the initial settings for each program of one embodiment according to the present invention. 620 in FIG. 62 is an initial data group for each process. It corresponds to the number of programs set in FIG. 61. In FIG. 57, 571 is set as the initial constant area or the touch panel display area, but it has the same structure as that incorporated into the device memory for each number of each process in FIG. 57. That is, instead of numbers, by adding the destination and return addresses for each order of the program to the initial settings for each processing program, it is possible to easily respond to changes.

[0106] Figure 63 is a program flowchart diagram of the identification of the initial execution type and the start of initial processing according to an embodiment of the present invention. When proceeding to "Identification and Initial Processing" at 555 in Figure 55, it transfers to "Identification of Initial Execution Type and Start of Initial Processing" at 630 in Figure 63, and the identification and initial processing are started. First, perform "Reset (turn off) the execution permission flag" at 631, perform "Read the identification data described in the CPU" at 632, and select "Compare the read identification data with the described identification data" at 633. If the selection result is "Match", transfer to "Set (turn on) the execution permission flag" at 634. If the comparison result is "Mismatch", transfer to "End of Identification of Initial Execution Type and Initial Processing" at 637, and the identification and initial processing end. Select "Compare the read identification data with the described identification data" at 633. When the selection result is "Match", perform "Set (turn on) the execution permission flag" at 634, perform "Reset (turn off) the input display device connection flag" at 635, perform "Read the initial values of each program" at 636, and transfer to "End of Identification of Initial Execution Type and Initial Processing" at 637, and the identification and initial processing end.

[0107] Based on the above program flowchart, further explanation is provided. This "Identification of Initial Execution Type and Initial Processing" is executed only once when the power is turned on from off or from STOP to RUN. It is doing two things. One is the identification process from "Reset (turn off) the execution permission flag" at 631 to "Set (turn on) the execution permission flag" at 634. The other is performing the initial processing of all processes, which is a general preliminary preparation. The identification process is a process for ensuring that a program is executed only on the CPU from the program side. Since programs can be easily replicated, they can be executed in the same way on different CPUs. That is, by simply replicating and using this program, which can handle all algorithm constructions just by changing data, there is no need to create a program corresponding to the algorithms for each device or equipment, which is widely practiced. Here, a bit called "execution permission flag" is created to realize the identification process. However, making a judgment based only on whether the execution permission flag is ON or OFF is too vulnerable because it can be easily imagined by monitoring. To strengthen it, instead of using the execution permission flag, it is sufficient to compare the identification data read for each process with the described identification data. However, since it is several words, there is also a problem that it takes a little time. Even more complex processes such as applying a prime number table can be added. At 635, "reset (turn off) the input display device connection flag" is performed. This is to deliberately reset (turn off) the bit set from the touch panel (TP) and monitor whether the touch panel (TP) is set (turned on). The reading of the initial values of each program at 636 is a general reading. It is also possible to perform it at the beginning of each process.

[0108] Figure 64 is a program flowchart diagram of the start of the reset (turn off) process of the refinement of the timing process of the scan execution type according to an embodiment of the present invention. When proceeding to "reset process of the refinement of the timing process" at 556 in Figure 55, it shifts to "start of the reset (turn off) process of the refinement of the timing process of the scan execution type" at 640 in Figure 64, and the reset (turn off) process of the refinement of the timing process is started. First, the selection of "presence or absence of the number of data in the table data" at 641 is performed. If the selection result is "Yes", it proceeds to "Prohibition of Interrupt of Fixed-Cycle Program" at 642. If the selection result is "No", it proceeds to "End of Reset (Turning OFF) Processing of Fine Differentiation of Timing Processing for Scan Execution Type" at 64D, and the reset (turning OFF) processing of the fine differentiation of the timing processing ends. Select "Existence / NON-existence of the Number of Data in Table Data" at 641. When the selection result is "Yes", perform "Interrupt Prohibition of Fixed-Cycle Program" at 642, perform "Calculation of Number of Checks from the Number of Data in Table Data" at 643, perform "Initialization of the Number of Checks Currently Being Executed" at 644, and select "Comparison between the Number of Checks and the Number of Checks Currently Being Executed" at 645. If the selection result is "Less than", it proceeds to "Reading from Modified Register from Table Data" and "Reading of Scan Counter Value from Table Data" at 646. If the selection result is "Greater than or equal to", it proceeds to "Permission of Interrupt of Fixed-Cycle Program" at 64C. Select "Comparison between the Number of Checks and the Number of Checks Currently Being Executed" at 645. When the selection result is "Greater than or equal to", perform "Permission of Interrupt of Fixed-Cycle Program" at 64C, and proceed to "End of Reset (Turning OFF) Processing of Fine Differentiation of Timing Processing for Scan Execution Type" at 64D, and the reset (turning OFF) processing of the fine differentiation of the timing processing ends. Select "Comparison between the Number of Checks and the Number of Checks Currently Being Executed" at 645. When the comparison result is "Less than", perform "Reading from Modified Register from Table Data" and "Reading of Scan Counter Value from Table Data" at 646, and select "Scan Counter Value is" at 647. If the selection result is "1 or less", it proceeds to "Reset (Turning OFF) of General-Purpose Device Bits Modified by Modified Register" at 648. If the selection result is "2 or more", it proceeds to "Changing the Scan Counter Value to 1" at 649. Select "Scan Counter Value is" of 647. When the selection result is "2 or more", perform "Change Scan Counter Value to 1" of 649, "Write Modified Register to Table Data" of 64A, and "Write Scan Counter Value to Table Data", then merge and repeat, and thus transfer to "Change Scan Counter Value to 1" of 649. Select "Scan Counter Value is" of 647. When the selection result is "1 or less", perform "Reset (turn off) General-Purpose Device Bits Modified by Modified Register" of 648, "Increment the Number of Checks Currently Being Executed by 1" of 64B, then merge and repeat, and thus transfer to "Compare Number of Checks and Number of Checks Currently Being Executed" of 645.

[0109] Based on the above program flowchart, further explanations will be provided. This "Reset (turn off) Processing for Fine Differentiation of Timing Processing of Scan Execution Type" is a program for corresponding to what has been finely differentiated in the "Timing Processing" of the program of the fixed-cycle execution type. Differentiating bits, capturing contacts differentially, or differentiating instructions can be replaced by the output method, the capture method, or the instruction execution method, and this is one of their forms. Specifically described, the execution of a group of scan execution type programs is a repetition of a group of scan execution type programs, and one execution of it is called one scan. That is, differentiation is a form of executing only one scan. Differentiating bits means outputting bits for only one scan, capturing contacts differentially means capturing contacts for only one scan, and differentiating instructions means executing instructions for only one scan. However, since one scan of a fixed-cycle execution type program is for the next cycle, unlike a scan execution type program, if the fixed-cycle time of a fixed-cycle execution type program is shorter than one scan of a scan execution type program, it will be interrupted many times within one scan of the scan execution type program. Since differentiating with a fixed-cycle execution type program cannot guarantee one scan of a scan execution type program, there may be omissions in the scan execution type program, and a reset (turning off) process for differentiation is performed in the scan execution type program. In this program, it is turned on for up to two scans. Incidentally, in a scan execution type program, if a bit is set for differentiation and the bit is reset in the next scan, that is, differentiation can be achieved simply by reversing the order of setting and resetting. To better understand the program flow chart diagram, it is necessary to explain the table data. Table data is a group of data in which certain devices are arranged. At the beginning of it, the number of data in the table data and, starting from the next of the number, the data group in which the data is stored form a structure. There is also an instruction word that adds the number every time data is written and subtracts the number every time data is read. The following are the details of each symbol, etc. The selection of "presence or absence of the number of table data" in 641 examines whether the beginning of the table data is 0 or not 0, and determines whether differentiation has been performed. The "prohibition of interrupt of the fixed-cycle program" of 642 is carried out because, in order to change the table data in the reset process of the refinement of this timing process, when the refinement is created in the timing process of the fixed-cycle program, the table data becomes unstable. The calculation of the number of checks from the number of data in the table data of 643, the initialization of the number of currently executed checks of 644, the comparison of the number of checks and the number of currently executed checks of 645, and the addition of 1 to the number of currently executed checks of 64B are carried out in consideration of the case where refinement occurs simultaneously. The calculation of the number of checks from the number of data in the table data of 643 is because, in the data table, when refinement occurs, two data, an address and a scan counter, and two, an address value and the number of checks, are written, so it increases every even number when refinement occurs. The initialization of the number of currently executed checks of 644 is always carried out before repeating in order to compare the number of checks and the number of currently executed checks. The selection of the comparison of the number of checks and the number of currently executed checks of 645 is the final judgment for exiting this process. The reading from the table data to the modified register and the reading of the scan counter value from the table data of 646 are the transfer of the address value and the number of checks using the table data. The selection of the scan counter value of 647 is to check how many scans have been performed because the refinement and the scan are closely related. The reset (turning off) of the general-purpose device bit modified by the modified register of 648 makes the level output appear to be refined by resetting (turning off) in one scan. The change of the scan counter value to 1 of 649 is set to 1 as a mark that one scan has passed because the scan counter value is set to 2. Since "writing the modified register to the table data" and "writing the scan counter value to the table data" in 64A are not the times for processing, the data table is written again, including the modified scan counter. "Adding 1 to the current number of checks being executed" in 64B is done to establish a comparison between the number of checks and the current number of checks being executed. "Enabling the interrupt of the periodic program" in 64C restores the interrupt of the periodic program because this process does not change the data table.

[0110] Figure 65 is a program flowchart diagram of the start of processing other than interface processing, sequential step processing, and timing processing of the scan execution type according to an embodiment of the present invention. When proceeding from the "input device data processing" of 557, "device data arithmetic processing (input standard)" of 558, "input processing" of 559, "logical processing" of 55B, "device data arithmetic processing (output standard)" of 55D, and "output processing" of 55E in Figure 55 to the "processing other than interface processing, sequential step processing, and timing processing" of 650 in Figure 65, the processing other than interface processing, sequential step processing, and timing processing starts. First, a selection of "whether the execution permission flag is ON or OFF" in 651 is made. If the selection result is "ON", it proceeds to the selection of "the presence or absence of that process" in 652. If the selection result is "OFF", it proceeds to "ending the processing other than interface processing, sequential step processing, and timing processing of the scan execution type" in 658, and ends the processing other than interface processing, sequential step processing, and timing processing of the scan execution type. When selecting "the presence or absence of that process" in 652 and the selection result is "none", it proceeds to "ending the processing other than interface processing, sequential step processing, and timing processing of the scan execution type" in 658, and ends the processing other than interface processing, sequential step processing, and timing processing of the scan execution type. When the selection result is "Yes", initialize the processing number of the currently executing process in 653, perform the "Reset (turn off) processing of the differentiation" in 654, and make a selection in 655 for "Comparison between the number of processing numbers and the currently executing processing number of that process". If the selection result is "Less than", transfer to "Execution of processing for each number" in 656. If the selection result is "Greater than or equal to", transfer to "End of processing other than interface processing, sequential step processing, and timing processing" in 657, and the processing other than interface processing, sequential step processing, and timing processing ends. Note that since the "Reset (turn off) processing of the differentiation" in 654 does not perform differentiation in the output processing, this processing is not performed in the output processing, and it transfers to "Comparison between the number of processing numbers and the currently executing processing number of that process" in 655. Select "Comparison between the number of processing numbers and the currently executing processing number of that process" in 655. When the selection result is "Less than", perform "Execution of processing for each number" in 656, perform "Add 1 to the currently executing processing number" in 657, and then merge and repeat, so it transfers to "Compare the number of processing numbers and the currently executing processing number" in 655.

[0111] Based on the above program flowchart, further explanations are provided. This program flowchart is the processing when proceeding to "Input device data processing" in 557, "Device data arithmetic processing (input standard)" in 558, "Input processing" in 559, "Logical processing" in 55B, "Device data arithmetic processing (output standard)" in 55D, and "Output processing" in 55E of Figure 55. Therefore, they are not performed simultaneously. However, since the processing from 653 to 656 is different for each executing process, six processes with the same structure are created and performed. Although it may be a matter of preference, since the processes are not performed simultaneously, by adding data for identifying each process and identifying the process based on the data for identifying each process, it is also possible to structure them. In this program flowchart, the features of the present invention can be glimpsed. In step 656, where "1 is added to the currently executing process number of that process", while changing the currently executing process number, step 655, "execution of the process for each number of that process", is repeatedly performed, and in step 654, "comparison of the number of process numbers of that process with the currently executing process number", the repetition is terminated. In the program of the present invention, all important processes ("input device data processing", "device data arithmetic processing (input standard)", "input processing", "logical processing", "sequential step processing", "device data arithmetic processing (output standard)", "output processing", "timing processing") are structured to execute the process for that number while changing the number, and when the number reaches the upper limit, the repetition is terminated. That is, not only can it easily cope with the addition and deletion of programs created by changing the number of repetitions, but it also has a structure that can cope with the construction of all algorithms. The following are the details of each symbol, etc. Regarding "whether the execution permission flag is ON or OFF" in step 651, although it is only once when the power is turned from OFF to ON, or from STOP to RUN, this process is enabled depending on whether "reset (turning OFF) of the execution permission flag" in step 351 of FIG. 35 is performed and whether "setting (turning ON) of the execution permission flag" in step 354 is performed. Regarding "presence or absence of the number of data in that process" in step 652, it is being done to shorten the one scan time. The "initialization of the currently executing process number of that process" in step 653 is always performed before repeating because it is used to compare the number of process numbers with the currently executing process number. The "reset (turning OFF) process of differentiation" in step 654 is being processed at the beginning to delay the one scan. The selection of "comparison of the number of process numbers of that process with the currently executing process number" in step 655 is the final judgment for exiting this process. The "execution of the process for each number of that process" in step 656 indicates a transition to the detailed program flowchart of the process for each process and each number. The "add 1 to the currently executing process number of that process" in 657 is performed to establish a comparison between the number of process numbers and the currently executing process number.

[0112] Figure 66 is a program flowchart diagram of the start of the reset (turn-off) process of microdifferentiation other than the timekeeping process in one embodiment according to the present invention (each process has the same structure). When the program flowchart diagram of this Figure 66 proceeds to the "reset (turn-off) process of microdifferentiation" in 654 of Figure 65 for each process, it shifts to the "start of the reset (turn-off) process of microdifferentiation other than the timekeeping process" in 660 of Figure 66 for each process, and the reset (turn-off) process of microdifferentiation other than the timekeeping process is started. First, select "presence or absence of the number of data in the table data of that process" in 661. If the selection result is "present", it shifts to "reading from the table data to the modification register of that process" in 662. If the selection result is "absent", it shifts to "end of the reset (turn-off) process of microdifferentiation other than the timekeeping process" in 664, and the reset (turn-off) process of microdifferentiation other than the timekeeping process ends. When selecting "presence or absence of the number of data in the table data of that process" in 661 and the confirmation result is "present", perform "reading from the table data to the modification register of that process" in 662, perform "reset (turn-off) of the general-purpose device bits modified by the modification register" in 663, and then shift back to the selection of "presence or absence of the number of data in the table data of that process" in 661 to repeat.

[0113] Based on the above program flowchart, further explanation is provided. This process is paired with the "device data processing", "input processing", and "logical processing" that perform microdifferentiation other than the timekeeping process for each number. Since each table data is different, three processes with the same structure are required. Although it may be a matter of preference, since the processes are not performed simultaneously, it is also possible to structure them by adding data for identifying each process and identifying the process based on the data for identifying each process. Also, this process is not a scan execution type program, but a simplified version of "reset process for micro-differentiation of timing process in scan execution type", which is a part of the program. That is, "presence or absence of the number of table data" in 641 of FIG. 64 is the same as "presence or absence of the number of table data in that process" in 661 of FIG. 66, "reading from table data to the modified register" in 646 of FIG. 64 is the same as "reading from table data to the modified register in that process" in 662 of FIG. 66, "resetting (turning off) the general-purpose device bits modified by the modified register" in 648 of FIG. 64 is the same as "resetting (turning off) the general-purpose device bits modified by the modified register" in 663 of FIG. 66. Only the arrows are slightly different, and other processes are deleted. The following are the details of each symbol, etc. The selection of "presence or absence of the number of table data in that process" in 661 examines whether the head of the table data in that process is 0 or non-zero, and determines whether micro-differentiation has been performed. As described in FIG. 64 as well, table data is a group of data in which certain devices are arranged. At the head of it, the number of data in the table data is followed by a data group in which data is stored. There are also instruction words for adding the number each time data is written and subtracting the number each time data is read. "Reading from table data to the modified register in that process" in 662 is the transfer of the address using the table data and the subtraction of the number of table data. "Resetting (turning off) the general-purpose device bits modified by the modified register" in 663 is to make the level output appear as if it has been micro-differentiated by resetting (turning off) in one scan.

[0114] FIG. 67 is a program flowchart diagram for starting the execution of the process for each number in the input device data processing according to an embodiment of the present invention. When proceeding from "Input Device Data Processing" at 558 in FIG. 55 to "Execution of Each Process for Each Number" at 376 in FIG. 37 with the same structure for each process, it shifts to "Start of Execution for Each Number of Input Device Data Processing" at 670 in FIG. 67, and the execution for each number of input device data processing starts. First, perform "Sequential tracking of the current execution process number from the start address of this program for the initial value and extraction of the start address of the number" at 671, perform "Extraction of the address of each element for the number of elements from the start address of the number" at 672, perform "Determination of the type, comparison symbol, devices for comparison source and comparison destination, and presence or absence of differentiation from the element value", perform "Writing the element value of the comparison source address to modification register 1", perform "Writing the element value of the comparison destination address to modification register 2", perform "Writing the element value of the general-purpose bit address to modification register 3", and perform "Writing the address of the differentiation prohibition bit determined from the start address of the number to modification register 4", and then make a selection of "Comparison between the comparison source of the determined device modified by modification register 1 and the comparison destination of the determined device modified by modification register 2" at 674. If the selection result is "established", it shifts to "Presence or absence of differentiation" at 675, and if the selection result is "not established", it shifts to "Not outputting the general-purpose bit modified by modification register 3 at the level" at 679. Select "Comparison between the comparison source of the determined device modified by modification register 1 and the comparison destination of the determined device modified by modification register 2" at 674. When the selection result becomes "not established", perform "Not outputting the general-purpose bit modified by modification register 3 at the level" at 679, and make a selection of "Is the differentiation prohibition bit modified by modification register 4 established?" at 67A. If the selection result is "established", it shifts to "Resetting (turning OFF) the differentiation prohibition bit modified by modification register 4" at 67B, and if the selection result is "not established", it shifts to "Ending the execution of each process for each number of input device data processing" at 67C, and ends the execution of each number of input device data processing. Select "Is the differentiation inhibition bit modified by Modification Register 4 valid?". If the selection result is "invalid", transfer to "End the execution of the processing for each number in the input device data processing" in 67C, and end the execution of the processing for each number in the input device data processing. Select "Comparison between the comparison source of the device determined by modification with Modification Register 1 and the comparison destination of the device determined by modification with Modification Register 2" in 674. If the selection result is "valid", select "Presence or absence of differentiation" in 675. If the selection result is "present", transfer to "Is the differentiation inhibition bit modified by Modification Register 4 not valid?" in 676. If the selection result is "absent", transfer to "Output the general-purpose bit modified by Modification Register 3 at the level" in 678. Select "Presence or absence of differentiation" in 675. If the selection result is "absent", perform "Output the general-purpose bit modified by Modification Register 3 at the level" in 678, transfer to "End the execution of the processing for each number in the input device data processing" in 67C, and end the execution of the processing for each number in the input device data processing. Select "Presence or absence of differentiation" in 675. If the selection result is "present", select "Is the differentiation inhibition bit modified by Modification Register 4 not valid?". If the selection result is "invalid", transfer to "Set (turn on) the general-purpose bit modified by Modification Register 3", "Write Modification Register 3 to the table data", and "Set (turn on) the differentiation inhibition bit modified by Modification Register 4". If the selection result is "valid", transfer to "End the execution of the processing for each number in the input device data processing" in 67C, and end the execution of the processing for each number in the input device data processing. Select "Does the differentiation prohibition bit modified by Modification Register 4 not hold?", and if the selection result is "does not hold", perform "Set (turn on) the general-purpose bit modified by Modification Register 3", "Write Modification Register 3 to the table data", and "Set (turn on) the differentiation prohibition bit modified by Modification Register 4", and then transfer to "End the execution of the processing for each number in the input device data processing" at 67C to end the execution of the processing for each number in the input device data processing.

[0115] Based on the above ...

Claims

1. There are a plurality of pieces of processing data consisting of an arbitrary number of rows and an arbitrary number of columns, and a microprocessor (MPU) or CPU executes processing according to a purpose based on the plurality of pieces of processing data, that is, one row of one of the processing data, and then moves on to the next row and executes processing thereon, and when the rows run out, returns to the first row and continues executing processing. In addition to the processing data of that line, the start address of the next line and the start address of the previous line are added to the processing data of that line, Furthermore, if the number of data items in the processing data for one row is variable, the variable number of data items is added to the processing data for that row, Furthermore, a data structure characterized in that, when the processing content for executing processing of one row requires repetition or branching, repetition data and processing data for the repeated or branched processing data are added to the processing data of that row.

2. A program for making a microprocessor (MPU) or a CPU execute processing according to a purpose based on the data structure according to claim 1, wherein the processing data is Processing data for input device data processing, which compares device data for each row and changes the ON / OFF state of the general-purpose bit based on the results; Processing data for an input process that takes in physically arranged input bits for each row and executes the process by changing the ON / OFF state of the general-purpose bits; Processing data of a logical process that, for each row, replaces a general-purpose bit with ON / OFF when a logical AND or OR of a plurality of general-purpose bits output from other processes becomes true, and executes the logical process; Processing data of a sequential step processing in which, for each row, the execution state of the processing is handed over to another row or a row of another processing by transitioning the ON state of the generic bit based on the generic bit output from another processing, and transmitted and executed; For each row, processing data of a device data calculation process in which a calculation function provided in a microprocessor (MPU) or CPU is calculated and executed on device data or device bits as specified; Processing data of an output process that changes the ON / OFF state of a physically arranged output bit by using a general-purpose bit output from another process for each row; and processing data for a time counting process that is executed by changing the ON / OFF state of a general-purpose bit over time for each row. A program characterized in that, in order to execute the above processing, the selection required for the processing is replaced with a numerical value of processing data, the address of a general-purpose bit is used as the processing data, and the processing data is written to and used in a plurality of modifying registers to execute the processing of that row, then the program moves on to the next row and executes the processing, and when the rows run out, the program returns to the first row and continues executing the processing.

3. An interface processing program which uses a touch panel (TP) or a PC as an interface for manipulating each processing data of the program described in claim 2 and, when a display memory area for a portion corresponding to each processing data of claim 2 is secured in a microprocessor (MPU) or a CPU, creates, deletes, adds, or modifies the processing data using the display memory area, and which is further included in a program on the touch panel (TP) or PC side, or in the program described in claim 2.

4. An identification and initial processing program that performs an identification process when a power source is turned on or reset, and controls and stabilizes a processing state to an initial state, wherein unique physical specific data is written into the identification and initial processing program before the identification and initial processing program is written into a microprocessor (MPU) or CPU, and during the identification process, the written data is compared with the unique physical specific data possessed by the read microprocessor (MPU) or CPU, and if they do not match, the identification and initial processing program changes the ON / OFF state of a general-purpose bit and transmits a prohibition instruction to each processing program described in claim 2; 3. The program according to claim 2, wherein a program for not executing each of the processes according to claim 2 based on an instruction to inhibit the identification and initial process program is incorporated into the program for each process.

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