Display device

Abstract

To provide a display device with suppressed power consumption.SOLUTION: A display device comprises a pixel portion comprising a plurality of pixels each including a first transistor, a second transistor, and a light-emitting element having a pair of electrodes. A gate of the first transistor is electrically connected to a scan line, one of a source and a drain of the first transistor is electrically connected to a signal line, and the other of the source and the drain is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to a power supply line and the other of the source and the drain is electrically connected to one of the pair of electrodes. The first transistor comprises an oxide semiconductor layer where the hydrogen concentration is 5×1019 / cm3 or less. A period during which the display device displays a still image includes a period during which output of a signal to all the scan lines in the pixel portion is stopped.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a display device, or to an electronic device including the display device. [Background technology]

[0002] In recent years, liquid crystal display devices and electroluminescence devices using electroluminescence elements have become popular. Flat panel displays, such as electroluminescent (EL) displays (hereinafter referred to as "EL displays"). Ray is now mass-produced as the mainstream image display device.

[0003] In the case of active matrix type liquid crystal display devices and EL display devices, each pixel in the pixel area is These transistors are made of silicon (Si) The semiconductor layer is used as an active layer.

[0004] In response to this, image display devices using transistors with oxides as active layers have been proposed. (See, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] The off-state current is one of the indicators for determining the electrical characteristics of a transistor. When the transistor is in an off state (also called a non-conducting state), In an n-channel transistor, the current that flows between the gate and the source When the applied voltage is equal to or lower than the threshold voltage (Vth), the current that flows between the source and drain It refers to the flow.

[0007] By using an amorphous oxide semiconductor thin film as the channel layer of a transistor, Current is 10 μA (= 1 × 10 -5 A), preferably less than 0.1 μA (= 1 × 10 -7 A) Un Patent Document 1 discloses that the amorphous acid can be used to obtain a satisfactory result. By using a thin film of a nitride semiconductor, the on-off ratio can be increased to 10 3 It is stated that it can be super However, in a transistor that exhibits electrical characteristics of this order, the off-state current is This means that there is a demand for further reduction in the power consumption of image display devices. In order to meet the needs of today's society, there is a demand to further reduce the off-state current.

[0008] One embodiment of the present invention is a pixel circuit including a plurality of pixels each including a transistor including an oxide semiconductor. The object of the present invention is to provide a display device including a pixel portion, the power consumption of which is suppressed. It shall be one. [Means for solving the problem]

[0009] One embodiment of the present invention is a display device in which an oxide semiconductor is used in each pixel of a display portion. The present invention is characterized by having at least a transistor using an oxide semiconductor. The photodiode has stable electrical characteristics, for example, an extremely low off-state current. In order to realize a transistor with a low resistance, one aspect of the present invention is to provide an intrinsic or substantially intrinsic The concentration of impurities that act as carrier donors is so reduced that the Typically, in one embodiment of the present invention, the hydrogen concentration in the film is 5×10 19 / cm 3 The following transistor uses an oxide semiconductor.

[0010] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a pair of electrodes. The pixel portion includes a plurality of pixels each including a light emitting element. The gate of the transistor is electrically connected to a scanning line, and either the source or the drain is electrically connected to a signal line. the other of the source and the drain is electrically connected to the gate of the second transistor and the second transistor has one of its source and drain electrically connected to a power supply line. and the other of the source and drain is electrically connected to one of the pair of electrodes, The first transistor has a hydrogen concentration of 5×10 19 / cm 3 An oxide semiconductor layer The display device is characterized by having:

[0011] In addition, one aspect of the present invention is a method for manufacturing a display device, comprising: A display device having a period during which the output of signals supplied to all scanning lines included in the display device is stopped. do.

[0012] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a pair of electrodes. A pixel section including a plurality of pixels each including a light-emitting element having the above structure, and a driver circuit for driving the pixel section. a control signal for driving the driving circuit unit and an image signal for supplying to the pixels a signal generating circuit, a storage circuit for storing the image signal for each frame period, Among the image signals stored for each frame period, a difference between image signals in successive frame periods a comparison circuit for detecting a difference between the consecutive frame periods when the comparison circuit detects a difference; a selection circuit for selecting and outputting the image signal of a signal output from the selection circuit and an image signal output from the selection circuit to the drive circuit section; When the comparison circuit does not detect a difference, the control signal is stopped from being supplied to the drive circuit. The first transistor has a gate electrically connected to a scanning line. One of the source and the drain is electrically connected to a signal line, and the source or the drain the other terminal of the first transistor is electrically connected to the gate of the second transistor, In the case of a transistor, either the source or the drain is electrically connected to a power supply line, and the The other is electrically connected to one of the pair of electrodes, and the first transistor is 5×10 19 / cm 3 A display device including an oxide semiconductor layer having the following structure: be.

[0013] In addition, one aspect of the present invention is a method for controlling a power supply voltage Vcc of a power supply circuit, comprising: A display device that is a start pulse signal or a reset signal.

[0014] Another embodiment of the present invention is a display device further including a luminous layer in the pixel.

[0015] In one aspect of the present invention, the carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 It is a display device having a resolution of less than 1000 s.

[0016] In one embodiment of the present invention, the oxide semiconductor layer has a band gap of 2 eV or more. It is a display device.

[0017] In one embodiment of the present invention, the second transistor has a hydrogen concentration of 5×10 19 / cm 3 A display device including an oxide semiconductor layer is described below.

[0018] In one aspect of the present invention, the second transistor is a display having a polycrystalline silicon layer. It is a device.

[0019] Another aspect of the present invention is an electronic device including the display device.

[0020] Due to the structure of a transistor, it is difficult to distinguish between the source and the drain. Depending on the operation of the circuit, the high and low potentials may be reversed. In this specification, the source and drain are not particularly specified, but are referred to as a first electrode (or a first terminal), a second electrode (or For example, if the first electrode is the source, the second electrode is refers to the drain, and conversely, if the first electrode is the drain, the second electrode refers to the source. This refers to.

[0021] In this specification, the term "aperture ratio" refers to the area of ​​a region through which light passes per unit area. The ratio of the area occupied by the light-opaque material to the aperture becomes larger. When the aperture ratio decreases and the area occupied by the light-transmitting member increases, the aperture ratio increases. In a display device, the area occupied by wirings overlapping with pixel electrodes, capacitance lines, and transistor sizes are Reducing the size of the aperture increases the aperture ratio.

[0022] In particular, in a self-luminous display device in which each pixel contains a light-emitting element, the observer The ratio of the light-emitting area of ​​the light-emitting element that can be observed from a position facing the display to the pixel area is called the aperture ratio. He said.

[0023] In addition, in this specification, when it is stated that "A and B are connected," it means that A and B are When A and B are electrically connected (i.e., when A and B are connected with another element or circuit between them), A and B are functionally connected (i.e., A and B are not connected to each other) and B is functionally connected (i.e., A and B are not connected to each other). (When A and B are functionally connected via another circuit) and (When A and B are directly connected) This includes cases where A and B are connected without any other element or circuit between them. This shall be done.

[0024] In addition, the terms "first," "second," "third," "n," "third ... The numbers are added to avoid confusion of the components, and are not intended to limit the number of components. For example, The term "first transistor" used in this specification does not cause confusion with other components. In the present specification, the term "second transistor" may be used interchangeably. Effect of the Invention

[0025] According to one embodiment of the present invention, a transistor including a high-purity oxide semiconductor can be used as a pixel electrode for a display device. By using it in the elemental part, the off-current is reduced to 1×10 -13 This can be reduced to below A. This allows data to be retained for a longer period of time, reducing power consumption when displaying still images, etc. It can be suppressed.

[0026] In addition, the control circuit 100 determines whether a still image or a moving image is displayed, and controls the operation of the drive circuit unit during the period when the still image is displayed. By stopping the above, the power consumption of the display device can be further reduced. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 illustrates an example of a configuration of a display device. [Diagram 2] FIG. 2 is an equivalent circuit diagram showing an example of a pixel configuration. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a transistor. [Figure 4] 4 is a diagram showing the relationship between a writing period and a holding period for a pixel. [Diagram 5] FIG. 2 is a cross-sectional view showing an example of a configuration of a pixel. [Figure 6] 1A and 1B are a plan view and a cross-sectional view showing an example of a light-emitting display panel. [Figure 7] FIG. 1 is a block diagram illustrating an example of a display device. [Figure 8] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 9] FIG. 4 is a timing chart of a driver circuit. [Figure 10] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 11] 5A and 5B are diagrams showing an example of a procedure for supplying and stopping a signal to a driver circuit. [Figure 12] 1A and 1B are a plan view and a cross-sectional view showing an example of a light-emitting display panel. [Figure 13] 1A and 1B are a plan view and a cross-sectional view illustrating an example of a transistor. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 18] FIG. 2 is a cross-sectional view showing an example of a configuration of a pixel. [Figure 19] FIG. [Figure 20] FIG. [Figure 21] FIG. 1 is a diagram showing a band structure between a source and a drain of a MOS transistor using an oxide semiconductor. [Figure 22] FIG. 20 is a diagram showing a state in which a positive voltage is applied to the drain side in FIG. 19. [Diagram 23] 1A and 1B are energy band diagrams of a MOS structure of a MOS transistor using an oxide semiconductor, showing a case where the gate voltage is positive and a case where the gate voltage is negative. [Figure 24] FIG. 1 shows the band structure between the source and drain of a silicon MOS transistor. [Diagram 25] FIG. 13 shows initial characteristics of a fabricated transistor. [Figure 26] FIG. 13 is a top view showing a fabricated transistor. [Figure 27] 13A to 13C show electrical characteristics of the fabricated transistors. [Figure 28] 5A and 5B are diagrams showing an example of a procedure for supplying and stopping a signal to a driver circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] An embodiment according to one aspect of the present invention will be described in detail with reference to the drawings. The disclosure is not limited to the following description, and the embodiments described herein are not to be construed as departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details. The present invention is not limited to the description of the embodiment. In the drawings, reference numerals indicating the same objects are common among different drawings.

[0029] In each of the embodiments and examples described below, unless otherwise specified, The present invention may be implemented in appropriate combination with other embodiments and examples described in this specification. It is Noh.

[0030] (Embodiment 1) In this embodiment, an example of a display device according to one embodiment of the present invention will be described. An example of a pixel configuration provided in a pixel portion of a display device will be described with reference to FIGS. 1 to 6. do.

[0031] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment of the present invention. As shown in FIG. In the display device, a pixel section 202 in which a plurality of pixels 201 are arranged in a matrix is ​​provided on a substrate 2. 00. The display device includes a circuit for driving a plurality of pixels 201. The pixel 201 includes a scanning line driver circuit 203 and a signal line driver circuit 204. A scanning signal is supplied by a first wiring 121 (scanning line) electrically connected to the circuit 203. The scanning signal determines whether each row is selected or not. The selected pixel 201 is connected to the second wiring 1 electrically connected to the signal line driving circuit 204. 22 (signal line), a video voltage (video signal, image signal, video The pixel 201 is supplied with a pair of electrodes. A light-emitting element is provided, and a power supply for supplying a potential is connected to one electrode of the light-emitting element. The wire 123 is electrically connected.

[0032] In FIG. 1, the scanning line driving circuit 203 and the signal line driving circuit 204 are disposed on the substrate 20. 0, the present invention is not limited to this configuration. Either the scanning line driving circuit 203 or the signal line driving circuit 204 is provided on the substrate 200. Alternatively, only the pixel section 202 may be provided on the substrate 200. It may be composed of

[0033] In addition, in FIG. 1, a plurality of pixels 201 are arranged in a matrix (stripe arrangement). However, the present invention is not limited to this configuration. As for the layout configuration, not only stripe layout but also delta layout, Bayer layout, etc. can be adopted. This can be done.

[0034] The display method in the pixel unit 202 may be a progressive method, an interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RG B (R stands for red, G stands for green, B stands for blue). For example, RGBW (W stands for white (representing the color), or RGB plus one or more colors such as yellow, cyan, or magenta The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but may be applied to monochrome display devices. It is also possible.

[0035] In addition, in FIG. 1, the number of first wirings 121 and the number of second wirings 122 are each Although the number of rows and columns corresponds to the number of rows and columns in one-to-one correspondence, the present invention is not limited to this configuration. For example, the first wiring 121 or the second wiring 122 is not shared between adjacent pixels. The pixel 201 may be driven by the pixel shift register 204.

[0036] FIG. 2 is an equivalent circuit diagram showing an example of the configuration of the pixel 201 in FIG. The pixel configuration is not limited to that shown in FIG.

[0037] The pixel 6400 includes a first transistor (hereinafter referred to as a switching transistor). A second transistor (hereinafter, sometimes referred to as a driving transistor) 6401 and a second transistor (hereinafter, sometimes referred to as a driving transistor) A light-emitting element 6402 and a light-emitting element 6404 are provided.

[0038] The first transistor 6401 has a gate electrically connected to a scanning line 6406 and a first The electrode (one of the source electrode and the drain electrode) is electrically connected to the signal line 6405, and the second The other of the source electrode and the drain electrode is connected to the gate of the second transistor 6402. The second transistor 6402 is electrically connected to a first electrode (a source electrode and one of the drain electrodes) is electrically connected to a power supply line 6407, and the second electrode (source The other of the electrode and drain electrode is electrically connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. In FIG. 2, a capacitance is provided between the gate of the second transistor 6402 and the power supply line 6407. Although the present invention is configured to include the element 6410, the present invention is not limited to this configuration. Between the gate of the second transistor 6402 and the second electrode of the second transistor 6402 A capacitive element may be provided.

[0039] The common electrode 6408 is electrically connected to a common potential line so that a low power supply potential is applied. Also, the power supply line 6407 is set to be supplied with a high power supply potential. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. A potential that satisfies the condition that the potential is lower than the high power supply potential. Examples of low power supply potential include GND and 0V. The potential difference between the high power supply potential and the low power supply potential is are set to be at least equal to or higher than the forward threshold voltage of the light emitting element 6404. It is necessary.

[0040] In this embodiment, a transistor including an oxide semiconductor layer is used as a first transistor. The first transistor 6401 is an n-channel The second transistor 6402 is an n-channel transistor. Either a p-channel transistor or a p-channel transistor may be used. The transistor 6402 may have a structure in which an oxide semiconductor layer is used as an active layer. When a silicon layer is used as the active layer, the amorphous silicon Although a silicon layer may be used, it is preferable to use a polycrystalline silicon layer. The second transistor 6402 is an n-channel transistor, and the oxide semiconductor layer The case where the above-mentioned is used as an active layer will be described.

[0041] Next, an example of a cross-sectional view of a first transistor 6401 in a pixel 6400 is shown in FIG. The transistor 106 shown in FIG. 3 corresponds to the first transistor 6401. In addition, the oxide semiconductor layer 103 serving as a channel region has a bottom gate structure. The first wiring 101 serving as a gate electrode is disposed on the lower side of the insulating film 101, and the oxide semiconductor layer 103 is disposed between the insulating film 101 and the insulating film 102. A first electrode (one of a source electrode and a drain electrode) is disposed on the opposite side to the first wiring 101. 102A and a second electrode (the other of the source electrode and the drain electrode) 102B. Therefore, it is also called an inverted staggered transistor.

[0042] A first wiring 101 is provided on a substrate 111 via an undercoat film 112. The wiring 101 functions as a gate of the transistor 106. The scanning line may be the scanning line itself that is electrically connected to the scanning line driving circuit, or may be a line that is electrically connected to the scanning line driving circuit. It may be a wiring that is electrically connected.

[0043] In addition, a gate insulating film 113 is provided so as to cover the first wiring 101. An oxide semiconductor layer 103 is provided on the gate insulating film 113. A first electrode 102A and a second electrode 102B are provided on the body layer 103. The first electrode 102A and the second electrode 102B are electrically connected to the oxide semiconductor layer 103. One functions as a source electrode and the other functions as a drain electrode. The first electrode 102A may be a signal line itself that is electrically connected to the signal line driving circuit. Alternatively, it may be a wiring that is electrically connected to a signal line.

[0044] In addition, on the oxide semiconductor layer 103, the first electrode 102A, and the second electrode 102B, An oxide insulating layer 114 is provided to function as a passivation film. An opening is formed in the layer 114, and the fourth wiring 105 and the second wiring 106 are connected to the opening. The fourth wiring 105 is electrically connected to the second transformer 102B. The transistor is electrically connected to the gate of the transistor.

[0045] Next, the oxide semiconductor layer 103 will be described.

[0046] The oxide semiconductor layer 103 used in this embodiment is a Impurities that adversely affect electrical characteristics are reduced to an extremely low level, A typical example of an impurity that adversely affects electrical properties is hydrogen. Hydrogen is an impurity that can act as an electron donor in oxide semiconductors. When a large amount of hydrogen is contained in an oxide semiconductor, the oxide semiconductor becomes n-type. In this way, a transistor using an oxide semiconductor containing a large amount of hydrogen is a normally-on transistor. As a result, the on / off ratio of the transistor cannot be sufficiently obtained. Therefore, in this specification, the term "high-purity oxide semiconductor" refers to an oxide semiconductor having hydrogen. It refers to a semiconductor that is intrinsic or substantially intrinsic and has as little oxide as possible. An example of a semiconductor containing hydrogen is a semiconductor having a hydrogen concentration of at least 5×10 19 / cm 3 Below Preferably 5×10 18 / cm 3 Less than 5×10, more preferably 17 / cm 3 Below Down, or 1×10 16 / cm 3 The oxide semiconductor has a carrier concentration of less than But 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than, preferably is 1×10 11 / cm 3 Less than or equal to 6.0×10 10 / cm 3 oxide semiconductor The oxide semiconductor layer is formed in a channel formation region of a transistor. Concentration measurement is performed using secondary ion mass spectrometry (SIMS). This can be done using a microscope (spectroscopy).

[0047] The energy gap of the oxide semiconductor layer 103 is 2 eV or more, preferably 2.5 eV or more. eV or more, and more preferably 3 eV or more.

[0048] In this way, the high conductivity can be obtained by thoroughly removing hydrogen from the oxide semiconductor layer. By using a high-purity oxide semiconductor layer for a channel formation region of a transistor, Extremely small transistors can be provided.

[0049] For example, a transistor using a high-purity oxide semiconductor layer has a channel length of 3 μm and a channel width of Even when the width is 10 mm, the gate When the gate voltage is in the range of -5V to -20V (off state), the drain current is 1×10 -1 3 It acts to keep it below A.

[0050] Here, the characteristics of a transistor using a high-purity oxide semiconductor layer will be described with reference to FIGS. In the following explanation, we will assume an ideal situation for ease of understanding. The following explanations are based on the actual situation and may not reflect the actual situation. It should be noted that the above is merely a consideration and does not affect the validity of the invention.

[0051] FIG. 21 shows a gate insulating film between the source and drain of a transistor using a high-purity oxide semiconductor layer. FIG. 1 is a diagram showing a structure of an oxide semiconductor having a highly purified structure. The Fermi level of the highly purified oxide semiconductor is in an ideal state. In the oxide semiconductor with reduced hydrogen concentration, the minority carriers are The amount of a (in this case, holes) is zero or very close to zero.

[0052] In this case, the work function is φ m , the electron affinity of the oxide semiconductor is χ, and the thermal equilibrium state of the oxide semiconductor is The carrier density (electron density) in the N d , the effective density of states in the conduction band of the oxide semiconductor is N c Then, the condition for the band structure to be flat at the metal-oxide semiconductor interface is φ m =χ-V t ln(N d / N c )

[0053] Here, V t =k b T / q, k b : Boltzmann constant, T: temperature, q: elementary charge This equation φ m =χ-V t ln(N d / N c ) is the boundary, and if the right side is large, Here, φ m If =χ, the Fermi level of the electrode metal at the junction surface The conduction band level of the oxide semiconductor is the same as that of the band gap 3. 05 eV, electron affinity 4.3 eV, intrinsic state (carrier density approximately 1×10 -7 / cm 3 )in Assume that titanium (Ti) with a work function of 4.3 eV is used as the source and drain electrodes. When using the ion beam, no barrier is formed for electrons, as shown in FIG.

[0054] FIG. 22 shows the state of a transistor using an oxide semiconductor when a positive voltage is applied to the drain side. Since the oxide semiconductor has a wide band gap, it is possible to highly purify the oxide semiconductor. The intrinsic carrier density of an intrinsic or substantially intrinsic oxide semiconductor is zero or very close to zero. When a positive voltage is applied to the gate and a voltage is applied between the source and drain, If this is the case, it will be understood that carriers (electrons) can be injected from the source side and flow to the drain side. can be.

[0055] FIG. 23(A) is an energy band diagram of a MOS structure when the gate voltage is positive. The figure shows a transistor using an oxide semiconductor. E represents a gate electrode, GI represents a gate insulating film, and OS represents an oxide semiconductor. In this case, since there are almost no thermally excited carriers in the highly purified oxide semiconductor, Carriers are not accumulated near the gate insulating film. However, as shown in Figure 22, The injected carriers can propagate through the

[0056] FIG. 23(B) is an energy band diagram of the MOS structure when the gate voltage is made negative. The minority of the oxide semiconductor is shown in FIG. Since the number of carriers (holes) is essentially zero, the current between the source and drain is close to zero. The value is close to

[0057] FIG. 24 shows a band diagram of a transistor using silicon semiconductor. The intrinsic carrier density of silicon semiconductors is 1.45×10 10 / cm 3 (300K) at room temperature This is because thermally excited carriers exist even at room temperature. In practice, silicon containing impurities such as phosphorus or boron is used. Since a silicon wafer is used, the actual 14 / cm 3 The above carriers are silicon In the semiconductor, the electrons are transported between the source and drain. The band gap of silicon is 1.12 eV, so transistors using silicon semiconductors can be used at high temperatures. The off-current varies greatly depending on the degree of the bias.

[0058] In this way, simply applying a wide band gap oxide semiconductor to a transistor Instead, impurities such as hydrogen that form donors are reduced as much as possible, and the carrier concentration is reduced to 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / c m 3 Less than or equal to 6.0×10 10 / cm 3 By making it less than The carriers excited thermally by temperature are excluded, and only the carriers injected from the source side are generated. This allows the transistor to operate with an off-state current of 1×10 -13 A At the same time, the off-current is extremely stable with almost no change due to temperature changes. A working transistor can be obtained.

[0059] Next, the measured values ​​of the off-state current in the evaluation element (also called TEG) will be described below.

[0060] 200 transistors with L / W=3μm / 50μm are connected in parallel, and L / W=3μm / The initial characteristics of the 10,000 μm transistor are shown in FIG. The range is shown up to +5V. The top view is shown in Figure 26(A), and a part of it is enlarged. The top view is shown in FIG. 26(B). The area surrounded by the dotted line in FIG. 26(B) is L / W=3 μm / 5 The initial characteristics of the transistor are For the measurement, the substrate temperature was set to room temperature, and the source-drain voltage (hereafter referred to as drain voltage) The source-gate voltage (hereafter referred to as gate voltage or Vg) is set to 10V. The source-drain current (hereafter referred to as drain) when the The change characteristics of the current (referred to as Id), i.e., the Vg-Id characteristics, were measured.

[0061] As shown in FIG. 25, a transistor with a channel width W of 10000 μm has a Vd of 1 V and At 10V, the off-state current is 1×10 -13 [A] or less, and the measuring instrument (semiconductor The resolution of the meter analyzer (Agilent 4156C; Agilent) (1 00fA).

[0062] Next, a method for manufacturing the measured transistor will be described.

[0063] First, a silicon nitride layer is formed as a base layer on a glass substrate by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer as a gate electrode by a sputtering method. A tungsten layer was formed. The tungsten layer was then selectively etched to form a gate electrode. poles formed.

[0064] Next, a 100 nm thick silicon oxynitride film was formed on the gate electrode as a gate insulating layer by CVD. A base layer was formed.

[0065] Next, an In-Ga-Zn-O metal oxide tantalum was deposited on the gate insulating layer by sputtering. Get (molar ratio, In 2 O 3 :Ga 2 O 3 ZnO=1:1:2) and a thickness of 5 Then, the oxide semiconductor layer was selectively etched. An island-shaped oxide semiconductor layer was formed.

[0066] Next, the oxide semiconductor layer was subjected to a first heating process in a clean oven under a nitrogen atmosphere at 450° C. for 1 hour. The heat treatment was carried out.

[0067] Next, a titanium layer (thickness 150 nm) was formed on the oxide semiconductor layer as a source electrode and a drain electrode. m) was formed by sputtering. Here, the source electrode and the drain electrode were selectively etched. The channel length L of one transistor is 3 μm and the channel width W is 50 μm. By arranging 200 pieces in parallel, the L / W ratio was set to 3 μm / 10,000 μm.

[0068] Next, a protective insulating layer was formed by reactive sputtering so as to contact the oxide semiconductor layer. A silicon oxide layer was formed to a thickness of 300 nm. The silicon oxide layer, which is a protective insulating layer, was selectively removed. The semiconductor device was then etched to form openings above the gate electrode, source electrode, and drain electrode. Thereafter, a second heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0069] Then, before measuring the Vg-Id characteristics, the device was heated at 150° C. for 10 hours.

[0070] Through the above steps, a bottom-gate transistor was manufactured.

[0071] As shown in Figure 25, the off-state current of the transistor is 1×10 -13 [A] is the level This is because the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced in the above manufacturing process. The hydrogen concentration in the oxide semiconductor layer is 5×10 19 atoms / cm 3 Hereinafter, preferably 5×10 18 atoms / cm 3 Less than 5×10, more preferably 17 / cm3 The following is or 1×10 16 atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer is Secondary ion mass spectrometry (SIMS) This is done using ectroscopy.

[0072] In addition, although an example using an In-Ga-Zn-O oxide semiconductor has been shown, the present invention is not particularly limited. , other oxide semiconductor materials, for example, In-Sn-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, In-Sn-O Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. In addition, as the oxide semiconductor material, AlOx is mixed at 2.5 to 10 wt%. In-Al-Zn-O system containing 2.5 to 10 wt% Si, and In-Zn-O system containing 2.5 to 10 wt% Si can also be used.

[0073] In addition, the carrier concentration of the oxide semiconductor layer measured by a carrier measurement device was 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / c m 3 Less than or equal to 6.0×10 10 / cm 3 That is, the carrier of the oxide semiconductor layer is less than 1000 nm. The carrier concentration can be reduced to as close to zero as possible. For example, a MOS capacitor is manufactured, and the results of CV measurement of the MOS capacitor (CV One method is to determine the characteristics by evaluating them.

[0074] In addition, the channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. In this case, the operating speed of the circuit can be increased, and the off-current value is extremely small, so It is also possible to reduce power consumption.

[0075] Note that when the transistor is off, the oxide semiconductor layer is regarded as an insulator in the circuit design. This can be done.

[0076] Next, the temperature characteristics of the off-state current of the transistor manufactured in this embodiment were evaluated. Temperature characteristics are determined based on the environmental resistance of the final product in which the transistor is used, as well as the maintenance of performance. Naturally, the smaller the change, the better, and this increases the degree of freedom in product design. .

[0077] The temperature characteristics are measured using a thermostatic chamber at -30, 0, 25, 40, 60, 80, 100, and 12 The substrate on which the transistor was formed was kept at a constant temperature of 60°C. The Vg-Id characteristics were obtained by changing the gate voltage from -20V to +20V.

[0078] Figure 27(A) shows the Vg-Id characteristics measured at each of the above temperatures, which are overlaid. The area of ​​the off-current surrounded by the dotted line is shown in enlargement in FIG. The rightmost curve indicated by the arrow is taken at -30℃, and the leftmost curve is taken at 120℃. The obtained curve is somewhere between these two. The on-current has almost no temperature dependence. As is clear from the enlarged view of Figure 27(B), the off-state current is At all temperatures, except for the vicinity, the resolution of the measuring instrument is close to 1×10 -12 [A] or less In other words, even at a high temperature of 120°C, the off-state current is 1× 10 -12 [A] or less is maintained, and the channel width W is 10000 μm. Then, 1×10 -16 [A / μm] or less, which shows that the off-current is extremely small. .

[0079] A transistor using a highly purified oxide semiconductor (purified OS) has This is because the temperature dependence of the current is almost nonexistent, as shown in the band diagram of FIG. By purifying the conductor, the conductivity type approaches the intrinsic type and the Fermi level Since it is located in the center of the forbidden band, it can be said that it does not show temperature dependence. The energy gap of the semiconductor is 3 eV or more, and the number of thermally excited carriers is extremely small. Also, since the source and drain regions are in a degenerate state, the temperature The transistor operates by discharging the oxide from the degenerated source region. Most of the charge transport is due to carriers injected into the nitride semiconductor, and the carrier density is dependent on temperature. This explains the above characteristic (no temperature dependence of off-current).

[0080] As mentioned above, if the channel width W of a transistor is 1×10 4 The channel length is 3 μm. Even with a device with a size of 10 μm, the off-state current is -13 A or less, and the subthreshold swing Excellent electrical properties with a switching value (S value) of 0.1V / dec. (gate insulating film thickness 100nm) In this way, the oxide semiconductor is highly purified so that the amount of impurities contained therein is minimized. This makes it possible to improve the operation of the transistor. The transistor having the nitride semiconductor layer has an off-current of 10 aA per 1 μm of channel width. / μm(1×10 -17 A / μm), and further, 1aA / μm (1×10 - 18 The current value in the off state (off current) can be reduced to 0.1A / μm or less. By using a transistor with an extremely low current value as the first transistor 6401, This allows the retention time of electrical signals such as video signals to be extended. The time is 10 seconds or more, preferably 30 seconds or more, and more preferably 1 minute or more and less than 10 minutes. By lengthening the interval between writes, the effect of suppressing power consumption can be increased.

[0081] On the other hand, for example, in a transistor using low-temperature polysilicon, the off-current is 1×10 -1 2 The design is based on the estimation of the equivalent of A / μm. The transistors having the junctions have a higher retention time than transistors with low-temperature polysilicon. When the capacitance is the same (about 0.1 pF), the voltage retention period is increased by 10 5 Stretch it out to about twice its size. In addition, in the case of a transistor having amorphous silicon, the channel width is 1 The off-state current per μm is 1×10 -13 A / μm or more. Therefore, the retention capacity is When the capacitance is the same (about 0.1 pF), the transistor using a high-purity oxide semiconductor has a higher capacitance. Compared to transistors using amorphous silicon, the voltage retention period is 10 4 More than double It can be stretched out.

[0082] As an example, a pixel with a transistor using low-temperature polysilicon can display 60 fps. This is done at 16msec per frame. Similarly, if the rate is reduced (the writing interval is extended), the voltage on the pixel decreases and the display On the other hand, when a transistor including the above-described oxide semiconductor layer is used, In this case, the off-current is small, so the retention period for one signal write is 10 5 Double 1600 Even with a small number of image signal writes, the static display on the display unit can be displayed in about 100 seconds. Since the retention period can be extended, it is particularly useful when displaying still images. For example, the frequency of writing signals can be reduced when displaying a single still image. The number of times the pixels are written during a period (about 1600 seconds) is When using a transistor, 10 5 On the other hand, the above-mentioned oxide semiconductor layer is required When a transistor having such a function is used, the number of times can be reduced to one.

[0083] Figure 4 shows the relationship between the write period and the hold period (also called one frame period) in the display area. In FIG. 4, periods 251 and 252 correspond to the retention period, and periods 261 and The period 262 corresponds to a period for writing to the display portion. Transistors can provide a long retention period, which is particularly useful when displaying still images. This significantly reduces the number of times that pixels need to be written to. This reduces the number of times the display is switched. When displaying still images or the like, it is possible to reduce power consumption.

[0084] In addition, when displaying a still image, the voltage applied to the gate of the driving transistor during the retention period is Taking into consideration the retention rate of the voltage, the refresh operation may be performed appropriately. A specified level is set for the voltage value (initial value) immediately after a signal is written to the gate of the The refresh operation can be performed when the voltage drops to a predetermined level. It is preferable to set the pressure so that flickering is not noticeable compared to the initial value. If the display object is a video, the value should be 1.0% lower than the initial value, preferably 0.3% lower. It is preferable to perform a refresh operation (rewrite) every time the display object If the value is a character, the reset is performed every time the value is 10% lower than the initial value, preferably every time the value is 3% lower. A fresh operation (rewrite) is preferable.

[0085] Next, as an example of a method for driving the light emitting element 6404, a method for performing analog gray scale driving will be described. The gate of the second transistor 6402 is connected to the forward voltage of the light emitting element 6404+the second transistor A voltage equal to or higher than the Vth of the transistor 6402 is applied. The voltage refers to the voltage required to obtain a desired brightness, and includes at least the forward threshold voltage. For example, a video signal (image signal) that causes the second transistor 6402 to operate in a saturation region By inputting a current, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is set to the second transistor 6402. It is recommended to set the potential higher than the gate potential of the transistor 6402. By making the video signal analog, A current corresponding to a video signal is passed through the light emitting element 6404, and analog gray scale driving can be performed. do.

[0086] In addition, the voltage input voltage driving method allows for area gradation display using multiple pixels and displays with different luminescent colors. Color representation by combining multiple pixels (e.g. R, G, B) (e.g. R+G, G +B, R+B, R+G+B, etc. are possible. In the case of a voltage input voltage driving method, the second The gate of the transistor 6402 is connected to a second transistor 6402. In other words, the second transistor 64 is turned on or off. The second transistor 6402 is operated in the linear region. In order to achieve this, the voltage of the power supply line 6407 is set lower than the gate potential of the second transistor 6402. Specifically, the threshold voltage of the second transistor 6402 is set to the potential of the power supply line. A voltage signal that gives a potential equal to or greater than the sum of the voltages may be input to the signal line 6405 .

[0087] In addition, whether the light emitting element 6404 is driven by analog gradation or by voltage input voltage, The off-current of the switching transistor 6401 is, for example, 1×10 -16 Suppressed to below A Therefore, the gate potential of the second transistor 6402 is held for a long period. Even if the number of times of writing image signals is small, still images can be displayed on the display unit. This reduces the frequency of writing signals, which leads to lower power consumption. The pixel configuration shown in FIG. 2 is not limited to this. For example, Switches, resistive elements, capacitive elements, transistors, logic circuits, etc. may be added.

[0088] In particular, one example of a light-emitting element is a light-emitting element that utilizes electroluminescence. The light-emitting element that utilizes electroluminescence is either made of an organic compound or Generally, the former is an organic EL element, and the latter is an inorganic EL element. It is called the L element.

[0089] An organic EL element consists of a pair of electrodes (anode and cathode) and an organic compound placed between the pair of electrodes. The potential of the anode is made higher than the potential of the cathode, and the layer containing the organic compound is Holes are injected from the cathode and electrons are injected from the cathode. The electrons and holes (carriers) contain organic compounds. When they recombine in the layer, they emit light.

[0090] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. It is a localized emission that is utilized.

[0091] In this embodiment, an organic EL element is used as the light-emitting element. However, the present invention is not limited to this structure. It is also possible to use

[0092] Next, a cross-sectional structure of a display device having a light-emitting element will be described with reference to FIG. 5(A), 5(B), and 5(C) are driving transistors 7001 and 7011. The transistor 7021 may be a transistor using a high-purity oxide semiconductor layer or a silicon In this embodiment, the driving transistor 7 When a high-purity oxide semiconductor layer was used as the active layer of 001, 7011, and 7021, He explains.

[0093] The light-emitting element exemplified in this embodiment has a pair of electrodes (a first electrode and a second electrode) between which The EL layer (electroluminescence layer) is sandwiched between the first electrode and the second electrode. One of the electrodes functions as an anode and the other functions as a cathode.

[0094] The material used for the anode is a metal or alloy with a large work function (specifically, 4.0 eV or more). , a conductive compound, or a mixture thereof. Specifically, indium oxide-oxide Tin oxide (ITO: Indium Tin Oxide), silicon or silicon oxide Indium oxide-tin oxide and indium oxide-zinc oxide (IZO) Zinc Oxide, tungsten oxide and zinc oxide containing indium oxide (I Other examples include gold (Au), platinum (Pt), nickel (Ni), and tungsten (Tb). W, Chromium (Cr), Molybdenum (Mo), Iron (Fe), Cobalt (Co) , copper (Cu), palladium (Pd), or nitrides of metallic materials (e.g., titanium nitride), etc. Examples include:

[0095] The material used for the cathode is a metal or alloy with a small work function (specifically, 3.8 eV or less). , an electrically conductive compound, or a mixture thereof. Elements belonging to groups 1 and 2, i.e., lithium (Li) and cesium (Cs), Potash metal, magnesium (Mg), calcium (Ca), strontium (Sr) and other Alkali metals and alkaline earth metals are also included. For example, MgAg, AlLi) can also be used. Rare earth metals such as terbium (Yb) or alloys containing rare earth metals can also be used. . In addition, when an electron injection layer is provided in contact with the second electrode as a part of the EL layer, the work function is large. Various conductive materials, such as Al, Ag, ITO, etc., can be used as the second electrode, regardless of size. These conductive materials can be applied by sputtering, inkjet printing, spin coating, etc. It is possible to form a film using the above.

[0096] The EL layer can be configured as a single layer structure, but is usually configured as a laminated structure. The laminated structure of the EL layer is not particularly limited, and may be a layer containing a substance with high electron transport properties (electron transport layer) or a layer containing a substance with high hole transport properties (hole transport layer), layer (electron injection layer), layer containing a material with high hole injection properties (hole injection layer), bipolar (electron and a layer containing a material having high hole transporting properties (a material having high hole transporting properties), a layer containing a light emitting material (a light emitting layer), etc. For example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron The charge generating layer may be formed by appropriately combining a charge injection layer, a charge generating layer, etc. A structure in which a plurality of EL layers separated by intermediate layers are provided between a first electrode and a second electrode. Good too.

[0097] In order to extract light from the light emitting element, at least one of the first electrode and the second electrode is The light emitting element formed on the substrate is formed of a conductive film having a light transmitting property. If light emitting devices are classified according to the direction in which they are attached, the light emitting devices are taken out from the surface of the substrate on which they are formed. Surface emission, bottom emission from the surface opposite to the side where the light emitting element is formed on the substrate, There are three typical double-sided injection methods, where light is extracted from both the side on which the element is formed and the opposite side. The present invention can be applied to any light-emitting device with any emission structure. .

[0098] When the EL layer is laminated on the first electrode, the periphery of the first electrode is covered with a partition wall. For example, organic resin films such as polyimide, acrylic resin, polyamide, and epoxy resin; inorganic The insulating film or organic polysiloxane may be used to form the insulating film. For example, a photosensitive resin material may be used. When a photosensitive resin material is used, the opening of the partition wall is preferably The sidewalls of the GaN wafer become inclined surfaces with a continuous curvature, and the process of forming a resist mask can be eliminated. Cut.

[0099] A color filter may be formed between the substrate and the light emitting element. The method is a droplet ejection method such as the inkjet method, a printing method, or an etching method using photolithography technology. They may be formed by a bonding method or the like.

[0100] In addition, when an overcoat layer is formed on the color filter and then a protective insulating layer is formed, By providing an overcoat layer, the unevenness caused by the color filter can be smoothed. By forming a protective insulating film, it is possible to prevent impurities from diffusing from the color filter to the light emitting element. do.

[0101] In addition, a light emitting element is formed on the protective insulating layer, the overcoat layer, and the insulating layer on the transistor. When forming the transistor, the protective insulating layer, the overcoat layer, and the insulating layer are penetrated, and the source of the transistor is formed. A contact hole is formed that reaches the electrode or the drain electrode. If the holes are laid out so as to overlap with the partition walls, the reduction in the aperture ratio can be suppressed. Therefore, it is preferable.

[0102] Next, an example of the configuration of a pixel having a light emitting element with a bottom emission structure will be described. FIG. 5(A) is a cross-sectional view of a cut surface including a driving transistor 7011 and a light-emitting element 7012. ) as shown in

[0103] The driving transistor 7011 includes an insulating layer, an oxide semiconductor layer, a source electrode, and a The gate insulating layer and the gate electrode are connected to the source electrode and the drain electrode, respectively. A wiring layer is provided so as to be electrically connected to the semiconductor device.

[0104] In addition, an insulating layer 7031 is formed to cover the driving transistor 7011, and the insulating layer 703 A color filter 7033 having an opening is provided on the conductive film 1. 7017 is an overcoat layer 7034 formed covering the color filter 7033 and It is formed on a protective insulating layer 7035. The electrode and the conductive film 7017 are formed by an overcoat layer 7034, a protective insulating layer 7035, and an insulating layer The conductive film 7017 is electrically connected to the conductive film 7031 through an opening formed therein. A first electrode 7013 of the light-emitting element 7012 is provided in contact with it.

[0105] The light-emitting element 7012 has an EL layer 7014 between a first electrode 7013 and a second electrode 7015. It is sandwiched between the.

[0106] The light-transmitting conductive film 7017 can be formed using indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, acid Indium tin oxide containing titanium dioxide, indium tin oxide (hereinafter referred to as ITO), A film made of indium zinc oxide, indium tin oxide with added silicon oxide, etc. is used. This can be done.

[0107] Here, the case where the first electrode 7013 of the light-emitting element 7012 is used as a cathode will be described. When the first electrode 7013 is used as a cathode, a metal having a small work function is suitable. In FIG. 5A, the film thickness of the first electrode 7013 is set to a value that allows light to pass through (preferably, 5 For example, an aluminum film or M film having a thickness of 20 nm is used. A g-Ag alloy film is used for the first electrode 7013 .

[0108] After a light-transmitting conductive film and an aluminum film are laminated, the aluminum film is selectively etched. In this case, a light-transmitting conductive film 7017 and a first electrode 7013 may be formed. It is preferable that the same mask be used for etching.

[0109] The second electrode 7015 formed on the EL layer 7014 is made of a material having a large work function. A shielding film 7016, for example, a metal that blocks light, is formed on the second electrode 7015. In this embodiment, the second electrode 7015 is made of an ITO film. and a Ti film is used as the shielding film 7016 .

[0110] The color filter 7033 is covered with an overcoat layer 7034, and a protective insulating layer In FIG. 5A, the overcoat layer 7034 is illustrated as being thin. However, the overcoat layer 7034 flattens the unevenness caused by the color filter 7033. There are.

[0111] Also, a drain electrode is formed on the overcoat layer 7034 and the protective insulating layer 7035. The contact hole reaching the electrode 7030 is disposed at a position overlapping with the partition wall 7019. .

[0112] In the case of the pixel structure shown in FIG. 5A, light emitted from the light emitting element 7012 is reflected by the light emitting element 7013 as shown by the arrow. The light is then emitted toward the first electrode 7013, passes through the color filter 7033, and is emitted to the outside of the display device. do.

[0113] The gate electrode, source electrode, and drain electrode of the driving transistor 7011 are A light-transmitting conductive film is used as a channel formation region of the driving transistor 7011. In this case, it is preferable to use a light-transmitting high-purity oxide semiconductor layer. As shown in FIG. 7, the light emitted from the light emitting element 7012 passes through the color filter 7033. The light is not only emitted through the driving transistor 7011 but also through the driving transistor 7011. In addition, the channel of the driving transistor 7011 can be improved. By using a high-purity oxide semiconductor layer having a light-transmitting property as a formation region, The off-current of the transistor 7011 can be reduced to an extremely low level, so the The area of ​​the electrode for forming the capacitance can be reduced. can be improved.

[0114] Next, the configuration of a pixel having a light emitting element with a dual emission structure will be described. FIG. 5B shows a cross-sectional view of a cut surface including a driving transistor 7021 and a light-emitting element 7022. vinegar.

[0115] The driving transistor 7021 includes an insulating layer, an oxide semiconductor layer, a source electrode, and a The gate insulating layer and the gate electrode are connected to the source electrode and the drain electrode, respectively. A wiring layer is provided so as to be electrically connected to the semiconductor device.

[0116] In addition, an insulating layer 7041 is formed to cover the driving transistor 7021, and an insulating layer 704 A color filter 7043 having an opening is provided on the light-transmitting conductive film 1. 7027 is an overcoat layer 7044 formed covering the color filter 7043 and It is formed on the insulating layer 7045. Note that the drain electrode of the driving transistor 7021 The conductive film 7027 is an overcoat layer 7044, an insulating layer 7045, and an insulating layer 7041. The light-emitting element is electrically connected to the conductive film 7027 through an opening formed in the conductive film 7027. A first electrode 7023 of the second electrode 7022 is provided in contact with the first electrode 7023 .

[0117] The light-emitting element 7022 has an EL layer 7024 between a first electrode 7023 and a second electrode 7025. It is sandwiched between the.

[0118] Here, the case where the first electrode 7023 of the light-emitting element 7022 is used as a cathode will be described. Note that the light-transmitting conductive film 7027 has a structure similar to that of the conductive film 7017 shown in FIG. The first electrode 7023 may be formed in the same manner as the first electrode 7013 shown in FIG. The EL layer 7024 may be formed in the same manner as the EL layer 7014 shown in FIG. Since it is sufficient to form the above-mentioned

[0119] The second electrode 7025 formed on the EL layer 7024 functions as an anode here. In particular, a material having a large work function, for example, a transparent conductive material such as ITO, IZO, or ZnO, is preferred. In this embodiment, the second electrode 7025 is formed of ITO.

[0120] The color filter 7043, the overcoat layer 7044, and the protective insulating layer 7045 are 5A, the color filter 7033 and the overcoat layer 703 4 and the protective insulating layer 7035 may be formed in a similar manner.

[0121] In the case of the element structure shown in FIG. 5B, light emitted from the light-emitting element 7022 is indicated by an arrow. As shown in FIG. 1, the light is emitted toward both the first electrode 7023 side and the second electrode 7025 side. The light on the side 23 passes through the color filter 7043 and exits the display device.

[0122] In FIG. 5B, a light-transmitting electrode is used as a gate electrode, a source electrode, and a drain electrode. In this example, the driving transistor 7021 is formed using a conductive film. A part of the light emitted from the element 7022 is reflected by the color filter 7043 and the driving transistor. It passes through 7021 and is ejected.

[0123] Also, a drain electrode is formed on the overcoat layer 7044 and the protective insulating layer 7045. The contact hole reaching the electrode 7040 is disposed at a position overlapping with the partition wall 7029. The layout is such that the contact hole reaching the drain electrode and the partition wall 7029 overlap each other. This makes the aperture ratio on the second electrode 7025 side and the aperture ratio on the first electrode 7023 side almost the same. It is possible.

[0124] However, when both display surfaces of a light-emitting element having a dual emission structure are used for full color display, Since the light from the electrode 7025 side does not pass through the color filter 7043, a separate color filter is required. It is preferable that a sealing substrate having a filter is provided above the second electrode 7025 .

[0125] Next, the structure of a pixel having a light emitting element with a top emission structure will be described. FIG. 5C shows a cross-sectional view of a cut surface including a driving transistor 7001 and a light-emitting element 7002. vinegar.

[0126] The driving transistor 7001 includes an insulating layer, an oxide semiconductor layer, a source electrode, and a The gate insulating layer and the gate electrode are connected to the source electrode and the drain electrode, respectively. A wiring layer is provided so as to be electrically connected to the semiconductor device.

[0127] In addition, an insulating layer 7051 is formed to cover the driving transistor 7001, and the insulating layer 705 An insulating layer 7053 having an opening is provided on the first electrode 7003. It is formed on an insulating layer 7055 formed to cover the driving transistor 7053. The drain electrode and the first electrode 7003 of the gate electrode 7001 are connected to the insulating layer 7055 and the insulating layer 70 Electrical connection is made through an opening formed in 51.

[0128] The insulating layer 7053 is made of polyimide, acrylic resin, benzocyclobutene resin, or poly Resin materials such as amide and epoxy can be used. In addition to the above resin materials, low dielectric constant materials such as low-k materials, siloxane resins, PSG (phosphorus glass), BPSG (phosphorus In addition, the insulating film formed of these materials can be used in multiple layers. The insulating layer 7053 may be formed by stacking. Depending on the material, sputtering, SOG, spin coating, dip coating, sputtering, etc. Ray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), A roll coater, a curtain coater, a knife coater, etc. can be used. By forming the insulating layer 7053, for example, unevenness caused by a driving transistor can be flattened. In addition, a drain electrode 7051 is formed on the insulating layer 7055 and the insulating layer 7053. The contact hole reaching 050 is disposed at a position overlapping with the partition wall 7009 .

[0129] The light-emitting element 7002 has an EL layer 7004 between a first electrode 7003 and a second electrode 7005. In the light-emitting element 7002 illustrated in FIG. The case where 3 is used as a cathode will be described.

[0130] The first electrode 7003 may be made of the same material as the first electrode 7013 shown in FIG. However, in the light-emitting element having a top emission structure shown in FIG. 5C, the first electrode 7003 is transparent. It is preferable that the electrode does not have optical transparency and has high reflectivity. By using such an electrode, the light extraction efficiency can be improved.

[0131] The first electrode 7003 is, for example, an aluminum film or a film mainly composed of aluminum. A titanium film is preferably laminated on an aluminum film or an alloy film. The first electrode 7003 is a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order. do.

[0132] The EL layer 7004 may be formed in the same manner as the EL layer 7014 shown in FIG. In addition, the second electrode 7005 may be formed in the same manner as the second electrode 7025 shown in FIG. Therefore, a detailed description will be omitted here.

[0133] In the case of the element structure shown in FIG. 5C, light emitted from the light emitting element 7002 is indicated by an arrow. As shown in FIG.

[0134] When full color display is performed using the structure of FIG. 5C, for example, the light emitting element 7002 is One adjacent light-emitting element is a red light-emitting element and the other is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is added to make four types of light-emitting elements. A light-emitting display device capable of full color display may be manufactured.

[0135] In addition, all the light emitting elements arranged in the structure of FIG. 5(C) are white light emitting elements. A sealing substrate having a color filter or the like is disposed above each light-emitting element including the element 7002. A light-emitting display device capable of full-color display may be manufactured by using a structure in which the light-emitting element is arranged in a single color such as white. By forming a material that emits light and combining it with a color filter or color conversion layer, full color can be achieved. -Display can be performed.

[0136] If necessary, an optical film such as a circular polarizing plate may be provided.

[0137] Next, the appearance and The cross section will be described with reference to FIG. 6. FIG. 6(A) shows a transistor formed on a first substrate. FIG. 1 is a plan view of a panel in which a transistor and a light-emitting element are sealed between a second substrate and the transistor and a light-emitting element by a sealant. FIG. 6B corresponds to a cross-sectional view taken along line HI in FIG. 6A.

[0138] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 450 is provided to surround the gate driver circuits 4503a and 4504b, and the scanning line driver circuits 4504a and 4504b. 5. Also, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided over the scanning line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 4 504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. Thus, the pixel portion 4502, the signal line 4503, and the like are sealed together with the filler 4507. The driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are exposed to the outside air. A protective film with high airtightness and low outgassing to prevent exposure to It is preferable to package (enclose) the optical fiber using an ultraviolet-curable resin film or a cover material.

[0139] In addition, a pixel portion 4502 and a signal line driver circuit 4503a are provided over a first substrate 4501. , 4503b, and the scanning line driver circuits 4504a, 4504b each have a plurality of transistors. In FIG. 6B, a transistor 4510 included in a pixel portion 4502 and a signal line driver The transistor 4509 included in the driving circuit 4503a is illustrated. Insulating layers 4542-4545 are provided on the insulating layers 45409 and 4510. The source voltage of the transistor 4510 is connected to the contact hole of the 2-4545. The electrode or drain electrode 4848 and the first electrode layer 4517 of the light emitting element 4511 are electrically connected to each other. This is being continued.

[0140] In this embodiment, the transistor 4509 included in the signal line driver circuit 4503a and a transistor 4510 included in the pixel portion 4502, The transistors have the following structures:

[0141] The oxide semiconductor layer of the transistor 4509 for the driver circuit is formed over the insulating layer 4542. A conductive layer 4540 is provided in a position overlapping with the channel forming region. By placing it at a position overlapping with the channel formation region of the semiconductor layer, Change in threshold voltage of transistor 4509 before and after bias and temperature stress test In this specification, the BT stress test (bias-temperature stress test) The stress test is a test in which a high gate voltage is applied to a transistor in a high-temperature atmosphere. In addition, the conductive layer 4540 may have the same potential as the gate electrode of the transistor 4509. It may be the same or different and may function as a second gate electrode. The potential of the conductive layer 4540 may be GND, 0 V, or may be in a floating state.

[0142] The light-emitting element 4511 includes a first electrode layer 4517, an electroluminescent layer 4512, a second electrode The light-emitting element 4511 has a stacked structure including the layer 4513, but is not limited to the structure shown here. The configuration of the light emitting element 4511 can be changed as appropriate according to the direction of the extracted light, etc.

[0143] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form the side walls of the partitions 4520 with a continuous curvature. It is preferable to form the surface so as to form a flat surface.

[0144] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It does not matter whether the

[0145] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode A protective film may be formed over the layer 4513 and the partition wall 4520. As the protective film, a silicon nitride film A silicon oxynitride film, a DLC film, or the like can be formed.

[0146] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504 b, or various signals and potentials applied to the pixel portion 4502 are Powered by 8b.

[0147] The connection terminal electrode 4515 has the same conductive property as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of a film. The source electrode and the drain electrode are formed from the same conductive film.

[0148] The connection terminal electrode 4515 is a terminal of the FPC 4518a and an anisotropic conductive film 4519. The two are electrically connected via a

[0149] The substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or an acrylic film A light-transmitting material such as film is used.

[0150] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0151] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0152] Note that the present invention is not limited to the configuration shown in FIG. The scanning line driver circuits 4503a and 4504b are separately provided on a substrate. The driving circuit may be implemented using a crystalline semiconductor film or a polycrystalline semiconductor film. In addition, only or a part of the signal line driver circuit, or only or a part of the scanning line driver circuit may be separated. The circuit may be implemented in a manner similar to that described above.

[0153] (Embodiment 2) In this embodiment, a configuration for further reducing the power consumption of the display device will be described. In addition to suppressing power consumption in the pixel section of the display device, A configuration for suppressing power consumption in the above will be described.

[0154] FIG. 7 shows an example of a block diagram of a display device. However, the present invention is not limited to the configuration shown in FIG. However, the present invention is not limited to the above.

[0155] The display device 1000 shown in FIG. 7 includes a display panel 1001, a signal generating circuit 1002, a memory circuit 1003, and a storage circuit 1004. The display control circuit 1006 includes a display circuit 1003, a comparison circuit 1004, a selection circuit 1005, and a display control circuit 1006. The display panel 1001 also includes a driver circuit section 1007 and a pixel section 1008. The circuit portion 1007 includes a gate line driver circuit 1009A and a signal line driver circuit 1009B. In addition, the gate line driver circuit 1009A and the signal line driver circuit 1009B have a plurality of pixels. It has a function of driving the pixel portion 1008 .

[0156] The transistors that form the pixel portion 1008 are the same as those described in Embodiment Mode 1. That is, as a switching transistor, an n-channel transistor having a high-purity oxide semiconductor layer is used. Note that the driving transistor is a transistor having a high purity oxide semiconductor layer. Alternatively, a structure using a silicon layer may be used. In the present invention, the driving transistor is also an n-channel transistor having a high-purity oxide semiconductor layer. The case where a transistor is applied will be described.

[0157] In this embodiment, a switch, which is one of the transistors constituting the pixel portion 1008, As a switching transistor, an n-channel transistor having a high-purity oxide semiconductor layer is By using a memory cell, the retention time of image signals and other data can be extended. Therefore, when displaying a still image or the like, the frequency of writing signals can be reduced. This makes it possible to reduce the power consumption of the display device.

[0158] Furthermore, in this embodiment, when a still image is displayed, all the signals included in the pixel unit are and driving the driving circuit unit to stop output of signals supplied to the scanning line and / or all scanning lines. By operating the pixel circuit in this manner, power consumption in not only the pixel portion but also the driver circuit portion can be reduced. That is, during the period when the display device displays a still image, all the signals included in the pixel unit The output of the signal supplied to the scanning line and / or all scanning lines is stopped during this period. In the embodiment, as a configuration for realizing low power consumption of the drive circuit unit, 1000 includes a signal generating circuit 1002, a memory circuit 1003, a comparison circuit 1004, and a selection circuit 10 05, has a display control circuit 1006.

[0159] The signal generating circuit 1002 includes a gate line driving circuit 1009A and a signal line driving circuit 1009B. It has the function of generating a signal (control signal) necessary to drive B. The circuit 1002 outputs a control signal to the drive circuit unit 1007 via the wiring. An image signal (also called a video voltage, a video signal, or video data) is stored in the memory circuit 100 via the In other words, the signal generating circuit 1002 has a function of outputting the signal to the driving circuit section 1007. and a circuit for generating and outputting an image signal to be supplied to the pixel unit. It is.

[0160] Specifically, the signal generating circuit 1002 outputs a control signal to the gate line driving circuit 1009A. , and the signal line driver circuit 1009B is supplied with a high power supply potential Vdd and a low power supply potential Vss A start pulse SP for the gate line driving circuit is supplied to the gate line driving circuit 1009A. A clock signal CK is supplied to the signal line driver circuit 1009B. The signal generating circuit 1002 also supplies a moving image signal SP and a clock signal CK. Alternatively, the image signal Data for displaying a still image is output to the memory circuit 1003 .

[0161] In addition, moving images are created by switching between multiple images at high speed, which are divided into multiple frames. Specifically, it is an image that is recognized as a moving image by the eye 60 times per second (60 By switching images at least one frame, the human eye perceives the image as a moving image with less flicker. A still image is a continuous image signal that is sent over multiple frames. Although it operates by switching multiple images time-divided at high speed during a period, it is difficult to operate the camera during consecutive frame periods. For example, the image signal does not change between the nth frame and the (n+1)th frame. This means.

[0162] The signal generating circuit 1002 also has the function of generating an image signal, a latch signal, etc. The signal generating circuit 1002 may include a gate line driving circuit 1009A and / or The signal line driver circuit 1009B is provided with a relay for stopping the output of the pulse signal of each driver circuit. The set signal Res may be output. The signal may be composed of multiple signals such as a first clock signal, a second clock signal, and a third clock signal. .

[0163] The high power supply potential Vdd is a potential higher than the reference potential, and the low power supply potential is a potential lower than the reference potential. The term "high power supply potential" refers to a potential that is equal to or lower than the semi-potential. It is desirable that the potential be such that the device can operate.

[0164] Voltage refers to the difference in potential between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage, respectively. It is possible.

[0165] In addition, the image signal output from the signal generating circuit 1002 to the memory circuit 1003 is an analog signal. In the case of a signal, the signal is converted into a digital signal via an A / D converter or the like, and the digital signal is stored in the memory circuit 100. It would be best to configure it so that it outputs to 3.

[0166] The memory circuit 1003 includes a plurality of frame memory circuits for storing image signals relating to a plurality of frames. The frame memory is, for example, a dynamic random access memory (DRAM). Random Access Memory), SRAM (Static Random The memory device may be configured using a memory element such as a memory access memory (RAM).

[0167] Note that the frame memory 1010 can store image signals for each frame period. In general, the number of frame memories is not particularly limited. The image signal of 010 is selectively read out by a comparison circuit 1004 and a selection circuit 1005. This is what we have in mind.

[0168] The comparison circuit 1004 compares the image signals of successive frame periods stored in the memory circuit 1003. This is a circuit for selectively reading out the image signals, comparing them, and detecting the difference. When a difference is detected by the comparison of the image signals in the comparison circuit 1004, the difference is detected. The consecutive frame periods are judged to be moving images. If no difference is detected by comparing the image signals of the two, the difference is not detected. In other words, the difference in the comparator circuit 1004 is By detecting the above, the image signals for successive frame periods are converted into image signals for displaying a moving image. It is judged whether the signal is a video signal for displaying a still image or a still image. The difference obtained by the comparison is detected when it exceeds a certain level. The setting may be such that the user is judged to have issued a

[0169] The selection circuit 1005 includes a plurality of switches, for example, switches formed of transistors. When the image signal for displaying a moving image is judged by detecting the difference in the comparison circuit, The image signal is selected from the frame memory 1010 in which the image signal is stored, and a display control circuit The comparison circuit 1004 outputs the image between the frames to the comparison circuit 1006. If no difference in the image signal is detected, the image displayed between successive frames is a still image. In this case, the display control circuit 100 controls the latter image signal during the consecutive frame periods. It is sufficient to configure it so that it does not output to 6.

[0170] The display control circuit 1006 receives an image signal, a high power supply potential Vdd, a low power supply potential Vss, a start Regarding the control signals of the pulse SP, the clock signal CK, and the reset signal Res, the drive circuit The comparison circuit 1007 is a circuit for switching between supply and stop. When it is determined that the image is a moving image by 04, that is, when the difference between the image signals of consecutive frames is extracted In addition, the image signal is supplied from the selection circuit 1005 to the display control circuit 1006. An image signal is supplied to a driving circuit unit 1007 via a display control circuit 1006. The signal is supplied to a driver circuit 1007 via a display control circuit 1006. The comparator circuit 1004 judges that it is a still image, that is, extracts the difference between the image signals during successive frames. If the image signal is not output, the selection circuit 1005 does not supply the image signal. No image signal is supplied to the driver circuit 1007 from the driver circuit 1006. The display control circuit 1006 stops supplying the signal to 1007 .

[0171] In addition, if a still image is judged to be a still image for a short period of time, the restriction Of the control signals, the high power supply potential Vdd and the low power supply potential Vss may not be stopped. In this case, frequent stopping and restarting of the high power supply potential Vdd and the low power supply potential Vss can This is preferable because it can reduce the increase in power consumption that occurs when the power supply is turned on.

[0172] The image signal and the control signal are stopped when each pixel in the pixel section 1008 is unable to hold an image signal. It is desirable to perform this for a period of time that is equal to or longer than the holding period of each pixel, and to supply an image signal again after the holding period of each pixel. In order to make the display control circuit 1006 supply the image signal and the control signal previously supplied again, The configuration may be such that:

[0173] Note that the supply of a signal means supplying a predetermined potential to a wiring. In this case, the supply of a predetermined potential to the wiring is stopped, and a wiring to which a predetermined fixed potential is supplied, for example, a low voltage wiring, is turned on. It means to electrically connect to the wiring to which the power supply potential Vss is supplied. Or, stopping a signal means The electrical connection with the wiring to which a predetermined potential is supplied is cut off, and the device is put into a floating state. cormorant.

[0174] As described above, the video signal is compared to determine whether it is a moving image or a still image, and the clock signal and start The drive circuit is driven by selectively restarting or stopping the supply of a control signal such as a pulse to the drive circuit. The power consumption in the circuit section 1007 can be reduced.

[0175] Next, the gate line driver circuit 1009A and the signal line driver circuit 1009B of the driver circuit section 1007 are FIG. 8 shows an example of the configuration of the shift register that constitutes the above.

[0176] The shift register shown in FIG. 8A includes first pulse output circuits 10_1 to N-th pulse The shift register shown in FIG. The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the A first clock signal CK1 is output from the first wiring 11, a second clock signal CK2 is output from the second wiring 12, and a third clock signal CK3 is output from the third wiring 13. The third wiring 13 transmits a third clock signal CK3, and the fourth wiring 14 transmits a fourth clock signal C In the first pulse output circuit 10_1, a start signal from the fifth wiring 15 is supplied. The first start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), The signal from the previous stage (called the previous stage signal OUT(n-1)(SR)) is input. Also, the first pulse In the output circuit 10_1, a signal is input from a third pulse output circuit 10_3 which is two stages behind. Similarly, in the n-th pulse output circuit 10_n in the second or subsequent stage, the (n+2)-th pulse output circuit in the second or subsequent stage The signal from the pulse output circuit 10_(n+2) (hereafter referred to as the latter signal OUT(n+2)(SR)) Therefore, the pulse output circuit of each stage outputs the pulse from the next stage and / or the stage before it. The first output signal (OUT(1)(SR) to OUT(N ) (SR)), a second output signal (OUT(1) to OUT(N)) input to another wiring, etc. As shown in FIG. 8(A), the last two stages of the shift register have Since the subsequent signal OUT(n+2)(SR) is not input, for example, a sixth A second start pulse SP2 is sent from the line 17, and a third start pulse SP Alternatively, a signal generated inside a separate shift register may be input. For example, the (N+1)th pulse output signal that does not contribute to the pulse output to the pixel unit may be used. A first pulse output circuit 10_(N+1) and a second pulse output circuit 10_(N+2) are provided (dummy The second start pulse (SP2) and the third start pulse (SP3) are generated from the dummy stage. A configuration may be adopted in which a signal equivalent to the pulse (SP3) is generated.

[0177] The first clock signal (CK1) to the fourth clock signal (CK4) are as shown in FIG. The first clock signal (C The fourth clock signal (CK1) to the fourth clock signal (CK4) are delayed by 1 / 4 period in sequence. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used. The clock signal CK is used to control the driving of the pulse output circuit. Depending on the route, it may be called GCK or SCK, but here we will explain it as CK.

[0178] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input A first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 8(B)). .

[0179] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 8(A) and 8(B), the first wiring 13 is electrically connected to any one of the first wiring 13 to the fourth wiring 14. In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal The terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_ 2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is The third input terminal 23 is electrically connected to the third wiring 13, and the third input terminal 24 is electrically connected to the fourth wiring 14. This is being continued.

[0180] In addition, in FIG. 8(A) and (B), the first pulse output circuit 10_1 has a fourth input terminal A start pulse is input to the fifth input terminal 24, and a subsequent signal OUT(3) (SR) is output to the fifth input terminal 25. is input, and the first output signal OUT(1)(SR) is output from the first output terminal 26, The second output terminal 27 outputs the second output signal OUT(1).

[0181] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0182] In FIG. 8C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39 and a gate electrically connected to a fourth terminal of the ninth transistor 39; The second transistor 32 has a first terminal electrically connected to the input terminal 24 of the power supply. a second terminal electrically connected to the first terminal of the ninth transistor 39; The third transistor 31 is electrically connected to the gate of the fourth transistor 34. The transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal The fourth transistor 34 has a first terminal electrically connected to the output terminal 26 of the power supply. The first terminal is electrically connected to the line 52 and the second terminal is electrically connected to the first output terminal 26 . The fifth transistor 35 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the gate of the first transistor 32 and the gate of the fourth transistor 34; The gate is electrically connected to the fourth input terminal 24. The sixth transistor 36 is One terminal is electrically connected to the power supply line 51, and the second terminal is connected to the gate and and the gate of the fourth transistor 34, the gate of which is electrically connected to the fifth input terminal 25. The seventh transistor 37 has a first terminal electrically connected to the power supply line 51. a second terminal electrically connected to the second terminal of the eighth transistor 38 and a gate The eighth transistor 38 has a first terminal electrically connected to the third input terminal 23. A gate of the second transistor 32 and a gate of the fourth transistor 34 are electrically connected to each other. The ninth transistor 39 is electrically connected to the second input terminal 22. , the first terminal is connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. , and the second terminal is electrically connected to the gate of the third transistor 33 and the gate of the tenth transistor The transistor 41 is electrically connected to the gate of the transistor 40 , and the gate is electrically connected to the power supply line 51 . The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the The second terminal of the ninth transistor 39 is electrically connected to the second output terminal 27 and the gate of the ninth transistor 39 is The eleventh transistor 41 has a first terminal electrically connected to the power supply line 52. The second terminal is electrically connected to the second output terminal 27, and the gate is A gate of the fourth transistor 34 is electrically connected to the gate of the second transistor 32. do.

[0183] In FIG. 8C, the gate of the third transistor 33 and the gate of the tenth transistor 40 A connection point between the gate and the second terminal of the ninth transistor 39 is a node NA. The gate of the second transistor 32, the gate of the fourth transistor 34, the gate of the fifth transistor the second terminal of the sixth transistor 36; the first terminal of the eighth transistor 38; The connection point between the terminal and the gate of the eleventh transistor 41 is referred to as a node NB.

[0184] When the pulse output circuit in FIG. 8C is the first pulse output circuit 10_1, the first input A first clock signal CK1 is input to the input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the third input terminal 24. A start pulse SP1 is input to the fourth input terminal 24, and a The second output terminal 26 receives the next stage signal OUT(3)(SR), and outputs the OUT(1)( SR) is output, and OUT(1) is output from the second output terminal 27.

[0185] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a gate line driving circuit. In FIG. 9, period 61 is a vertical blanking period, and period 62 corresponds to a gate selection period.

[0186] The driving circuit shown in Fig. 8 and Fig. 9 is made of multiple n-channel transistors. In the dynamic circuit, when displaying still images and dynamic images, the supply or stop of the potential of each wiring The procedure will be explained below.

[0187] First, when the operation of the driving circuit unit 1007 is stopped, the display control circuit 1006 The start pulse SP is stopped. Then, after the start pulse SP is stopped, the pulse output is After the final stage of the soft register is reached, each clock signal CK is stopped. The high power supply potential Vdd and the low power supply potential Vss of the drive circuit are stopped (see FIG. 11(A)). When the operation of the driving circuit unit 1007 is to be resumed, the display control circuit 1006 first A high power supply potential Vdd and a low power supply potential Vss are supplied to the driver circuit 1007. The lock signal CK is supplied, and then the supply of the start pulse SP is resumed (see FIG. 11(B)). (see).

[0188] Next, we fabricated a multi-channel transistor using the n-channel transistors shown in Figs. 8 and 9. In the drive circuit, the operation of changing from still image display to moving image display, or the driving transistor The operation of rewriting the voltage applied to the gate of the For details of the procedure for supplying or stopping the potential of each wiring to the drive circuit unit, see Figure 28. FIG. 28 shows a wiring for supplying a high power supply potential (VDD) to the shift register. Wiring that supplies the low power supply potential (VSS), wiring that supplies the start pulse (SP), and Wiring for supplying the first clock signal (CK1) through wiring for supplying the fourth clock signal (CK4) 13 is a diagram showing a change in potential of a wiring before and after a frame period (T1). FIG.

[0189] In the display device of the present embodiment, the driving circuit unit is constantly operated to display moving images and still images. Moreover, the display of still images can be achieved without constantly operating the drive circuit for refresh operations. Therefore, as shown in FIG. 28, a high power supply is connected to the shift register. potential (VDD), the first clock signal (CK1) to the fourth clock signal (CK4), and The period during which control signals such as a start pulse and a start pulse are supplied, and the period during which no control signal is supplied are Note that the period T1 shown in FIG. 28 is a period during which a control signal is supplied, that is, a period during which a moving image is This corresponds to the period during which the image is displayed and the period during which the refresh operation is performed. corresponds to a period during which no control signal is supplied, that is, a period during which a still image is displayed.

[0190] In FIG. 28, the period during which the high power supply potential (VDD) is supplied is not limited to the period T1. In FIG. 28, the first clock During the period in which the fourth clock signal (CK1) to the fourth clock signal (CK4) are supplied, This is provided from after the high power supply potential (VDD) is supplied until before the high power supply potential (VDD) is stopped. is.

[0191] As shown in FIG. 28, the first clock signal (CK1) to the fourth clock signal (C K4) is a high-potential signal before the start of period T1, and then a clock signal with a fixed period. After the period T1 ends, the clock signal starts oscillating as a low potential signal. The above may be configured to terminate the process.

[0192] As described above, in the display device of the present embodiment, a high voltage is applied to the shift register during the period T2. potential (VDD), the first clock signal (CK1) to the fourth clock signal (CK4), and The supply of control signals such as a start pulse and a start pulse is stopped. During this period, the transistors are turned on or off to control the shift register. The output of the pulse signal also stops. Therefore, the power consumed in the shift register, And to reduce the power consumed in a pixel unit driven by the shift register. This makes it possible.

[0193] Please note that the above refresh operation is performed with consideration given to the possibility that degradation of the image quality of the displayed still images may occur. In the display device of the present embodiment, the driving function of each pixel is The high purity GaN-GaN-Gate MOSFET is used as a switching element to control the voltage applied to the gate of the transistor. In this case, a transistor including an oxide semiconductor having a high degree of conductivity is used. Therefore, the voltage applied to the gate of the driving transistor of each pixel can be reduced to It is possible to reduce the voltage fluctuation. In other words, when displaying a still image, the operation of the shift register Even if the period during which the image is stopped is long, deterioration of the image quality can be reduced. , it is possible to maintain the quality of the displayed still image even if the period is 3 minutes. For example, a display that rewrites 60 times per second and refreshes once every 3 minutes. Compared to a display device that operates in the same way, the power consumption can be reduced to about 1 / 10,000. It is possible.

[0194] The above-mentioned high power supply potential (VDD) is stopped when the low power supply (V SS) and the high power supply potential (VDD) is stopped when the high power supply potential The potential of the wiring to be supplied may be set in a floating state.

[0195] In addition, the potential of the wiring to which the high power supply potential (VDD) is supplied is increased, that is, during the period T1 When increasing the power supply potential (VSS) to the high power supply potential (VDD) before It is preferable to control the change in potential so that it is gentle. If the change in potential is steep, it will become noise and an incorrect pulse will be output from the shift register. The shift register may be a shift register included in the gate line driving circuit. If the illegal pulse is a signal that turns on the transistor, then the illegal pulse is The voltage applied to the gate of the driving transistor changes depending on the pulse, producing a still image. In consideration of the above, in FIG. 28, the high power supply potential (V DD) is illustrated in the figure, where the rising edge of the signal is slower than the falling edge. In particular, in the display device of the present embodiment, when a still image is displayed in the pixel portion, The supply of the high power supply potential (VDD) to the shift register is stopped and then re-supplied as appropriate. In other words, the change in the potential of the wiring that supplies the high power supply potential (VDD) is detected as noise. If the noise affects the pixel section, it will directly lead to deterioration of the displayed image. In such a display device, a change in the potential of the wiring (especially an increase in the potential) is detected as noise. It is important to control it so that it does not enter the pixel area.

[0196] In the explanation of FIG. 8 and FIG. 9, the configuration of the drive circuit that does not supply the reset signal Res is described. A configuration for supplying the reset signal Res will be described with reference to FIG.

[0197] The shift register shown in FIG. 10A includes first pulse output circuits 10_1 to N-th pulse The shift register shown in FIG. The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the first path (called the previous stage signal OUT(n-1)(SR)) is input. The pulse output circuit 10_1 receives a signal from a third pulse output circuit 10_3, which is two stages behind. Similarly, in the n-th pulse output circuit 10_n in the second or subsequent stage, the (n+ 2) from the pulse output circuit 10_(n+2) (n+2) (n+2) Therefore, the pulse output circuit of each stage outputs the pulses from the next stage and / or the two previous stages. The first output signal OUT((1)(SR) to OUT(N ) (SR)), a second output signal (OUT(1) to OUT(N)) input to another wiring, etc. Also, a reset signal Res is output from the sixth wiring 16 to the pulse output circuit of each stage. is supplied.

[0198] The difference between the pulse output circuit shown in Fig. 10 and the pulse output circuit shown in Fig. 8 is that the The point is that the sixth wiring 16 for supplying the bit signal Res is provided, and the points regarding the other parts are the same as those described above. The explanation is the same as that of FIG.

[0199] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input Terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input It has a terminal 25, a first output terminal 26, a second output terminal 27, and a sixth input terminal 28. (See Figure 10(B)).

[0200] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 10(A) and (B) are electrically connected to any one of the first through fourth wirings 14. In the first pulse output circuit 10_1, a first input terminal 21 is electrically connected to a first wiring 11. the second input terminal 22 is electrically connected to the second wiring 12, and the third input The terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10 _2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. Connected.

[0201] In addition, in FIG. 10(A) and (B), the first pulse output circuit 10_1 has a fourth input A start pulse is input to the terminal 24, and a subsequent signal OUT(3)(S R) is input, and the first output signal OUT(1) (SR) is output from the first output terminal 26. The second output signal OUT(1) is output from the second output terminal 27, and the sixth input terminal 2 A reset signal Res is input from 8.

[0202] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0203] In FIG. 10C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39 and a gate electrically connected to a first terminal of a ninth transistor 39; The second transistor 32 has a first terminal electrically connected to the input terminal 24 of the a second terminal electrically connected to the power supply line 52 and a first terminal electrically connected to the first terminal of the ninth transistor 39; The third transistor 31 is electrically connected to the gate of the fourth transistor 34. The transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 22. The fourth transistor 34 has a first terminal electrically connected to the output terminal 26 of the first transistor. The power supply line 52 is electrically connected to the first terminal, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the The gate of the second transistor 32 and the gate of the fourth transistor 34 are electrically connected to , and the gate is electrically connected to the fourth input terminal 24. The sixth transistor 36 is The first terminal is electrically connected to the power supply line 51, and the second terminal is connected to the gate of the second transistor 32. and the gate of the fourth transistor 34, the gate of which is connected to the fifth input terminal 25 The seventh transistor 37 has a first terminal electrically connected to the power supply line 51. , and a second terminal electrically connected to the second terminal of the eighth transistor 38, is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate of the second transistor 32 and the gate of the fourth transistor 34. The ninth transistor 39 is electrically connected to the second input terminal 22. The first terminal is connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The second terminal is electrically connected to the gate of the third transistor 33 and the gate of the tenth transistor 34. The gate of the transistor 40 is electrically connected to the power supply line 51. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 22. The second terminal is electrically connected to the second output terminal 27, and the gate is the first terminal of the ninth transistor 39. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 52. , the second terminal is electrically connected to the second output terminal 27, and the gate is The gate of the first transistor 32 and the gate of the fourth transistor 34 are electrically connected to The gate of the second transistor 32, the gate of the fourth transistor 34, the gate of the fifth transistor 35, the second terminal of the transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The first terminal of 38 and the gate of the eleventh transistor 41 supply a reset signal Res. The reset signal Res is electrically connected to a wiring 53 for resetting the second transistor. The gate of the fourth transistor 32, the gate of the fifth transistor 35 2 terminal, a second terminal of the sixth transistor 36, a first terminal of the eighth transistor 38, and By supplying a signal of a high power supply potential level to the gate potential of the eleventh transistor 41, This signal is used to forcibly drop the output from the pulse output circuit to a low power supply potential level. be.

[0204] In FIG. 10C, the gate of the third transistor 33 and the gate of the tenth transistor 40 The connection point of the gate of the ninth transistor 39 and the second terminal of the ninth transistor 39 is a node NA. , the gate of the second transistor 32, the gate of the fourth transistor 34, the second terminal of the sixth transistor 36; the second terminal of the eighth transistor 38; The connection point between the first terminal and the gate of the eleventh transistor 41 is referred to as a node NB.

[0205] When the pulse output circuit in FIG. 10C is the first pulse output circuit 10_1, A first clock signal CK1 is input to the input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. The clock signal CK2 is input to the third input terminal 23, and the third clock signal CK3 is input to the third input terminal 24. A start pulse SP is input to the fourth input terminal 24, and a The second output terminal 26 receives the next stage signal OUT(3)(SR), and outputs the OUT(1)( SR) is output from the second output terminal 27, OUT(1) is output from the sixth input terminal A reset signal Res is input to 28.

[0206] In addition, the timing of the shift register having a plurality of pulse output circuits shown in FIG. The timing chart is the same as that shown in FIG.

[0207] The driving circuit shown in Figure 10 is made of multiple n-channel transistors. In the circuit, when displaying still images and moving images, the supply or stop of the potential of each wiring The procedure will be explained.

[0208] First, when the operation of the driving circuit unit 1007 is stopped, the display control circuit 1006 Then, after the start pulse SP stops, the pulse output shifts. After the clock signal CK reaches the final stage of the reset register, the clock signal CK is stopped. Next, the high power supply potential Vdd and the low power supply potential Vss of the power supply voltage are (See FIG. 11C). When the operation of the driving circuit unit 1007 is to be restarted, First, the display control circuit 1006 drives the high power supply potential Vdd and the low power supply potential Vss of the power supply voltage. Then, a reset signal Res is supplied to the circuit unit 1007. Then, a clock The signal CK is supplied, and then the supply of the start pulse SP is resumed (see FIG. 11(D)).

[0209] As explained in FIG. 10, in addition to the configurations in FIG. 8 and FIG. 9, a reset signal is supplied. This reduces malfunctions caused by signal delays when switching between still and moving images. This is preferable because it is possible to

[0210] In addition, when displaying a still image, a transistor that constitutes a driving circuit is provided The common potential electrode may be separated from the common potential line and put into a floating state. When the drive circuit is to be operated again after the still image mode, the common potential electrode is connected to the common potential line. In this way, it is possible to prevent malfunction of the transistors in the drive circuit section.

[0211] FIG. 12(A) shows an example of such a display panel 1800, and FIG. 12(B) shows a cross-section of it. FIG. 2 is a diagram illustrating a surface structure. The display panel 1800 includes driver circuits 1802 and 1804 and a pixel portion 1806. A common potential electrode 1808 is provided so as to overlap the region in which the driver circuit 1802 is provided. Between the common potential electrode 1808 and the common potential terminal 1812, a control circuit for controlling the connection / disconnection between the two is provided. A switch element 1810 is provided.

[0212] As shown in FIG. 12B, the common potential electrode 1808 is connected to the transistor 1803 of the driver circuit. A common potential electrode 1808 is provided on the transistor 1803. As a result, the transistor 1803 is electrostatically shielded, and the threshold voltage shift and the parasitic channel are prevented. This prevents it from becoming a reality.

[0213] The switch element 1810 may have the same configuration as the transistor 1803. These elements have extremely low leakage current in the off state, which reduces the operating In other words, when displaying a still image, the switching element Even if the common potential electrode is floated by turning off the capacitor 1810, the potential is This has the effect of keeping the temperature constant.

[0214] In this way, transistors made of oxide semiconductors with a wide band gap are used. At the same time, a common potential electrode is provided to block the external electric field, thereby stopping the operation of the drive circuit. In addition, the potential of the common potential electrode can be controlled by the driving circuit. By controlling the display appropriately according to the operation, the operation of the display panel can be stabilized. .

[0215] As described above, each pixel includes a transistor using a high-purity oxide semiconductor. This allows the period during which the voltage can be held by the storage capacitor to be longer than before, It is possible to reduce power consumption when displaying still images. The output of signals supplied to all signal lines and / or all scanning lines included in the pixel portion is stopped. By operating the driver circuit section so as to stop the power consumption of the pixel section as well as the driver circuit section, The force can also be reduced.

[0216] (Embodiment 3) In this embodiment, an example of the structure of the first transistor 6401 described in Embodiment 1 will be described. An example of a manufacturing method thereof will be described. An example of a structure of a transistor and an example of a manufacturing method thereof will be described.

[0217] First, an example of a planar structure and a cross-sectional structure of a transistor are shown in FIG. FIG. 13A is a plan view of a transistor 410 having a top-gate structure, and FIG. 13(A) is a cross-sectional view taken along line C1-C2 of FIG.

[0218] The transistor 410 includes an insulating layer 407, an oxide semiconductor layer 412, a first The first electrode (one of the source electrode and the drain electrode) 415a, the second electrode (one of the source electrode and the drain electrode) The first gate electrode 415b, the gate insulating layer 402, and the gate electrode 411 are provided. The first electrode 415a and the second electrode 415b are connected to the first wiring 414a and the second wiring 414b, respectively. 4b is provided adjacent to and electrically connected.

[0219] Note that the transistor 410 shown in FIG. 13A has a single-gate structure. However, the present invention is not limited to this configuration. A transistor having a multi-gate structure having a plurality of channel forming regions may also be used.

[0220] Next, a process for manufacturing a transistor 410 will be described with reference to FIGS. I will explain it below.

[0221] First, an insulating layer 407 is formed over a substrate 400 to serve as a base film.

[0222] There is no particular restriction on the substrate that can be used as the substrate 400, but it is necessary to use a substrate that is at least resistant to the subsequent heat treatment. If the temperature of the subsequent heat treatment is high, It is preferable to use a substrate having a distortion point of 730° C. or higher. A specific example of the substrate 400 is a glass substrate. Plate, crystallized glass substrate, ceramic substrate, quartz substrate, sapphire substrate, plastic substrate Examples of the glass substrate include aluminosilicate glass. Examples of such glass include glass, aluminoborosilicate glass, and barium borosilicate glass.

[0223] The insulating layer 407 may be a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, Alternatively, an oxide insulating layer such as an aluminum oxynitride layer is preferably used. The method for forming the insulating film may be a plasma CVD method, a sputtering method, or the like. In order to prevent a large amount of hydrogen from being contained in the edge layer 407, an insulating layer is formed by a sputtering method. In this embodiment, the insulating layer 407 is preferably formed by sputtering. Specifically, the substrate 400 is transferred to a processing chamber. After that, a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced, and silicon or A silicon oxide target is used to deposit silicon oxide as an insulating layer 407 on a substrate 400. During the deposition, the substrate 400 may be at room temperature or may be heated.

[0224] As a specific example of the film formation conditions, quartz (preferably synthetic quartz) is used as a target, and the substrate is The plate temperature was 108°C, the distance between the substrate 400 and the target (TS distance) was 60 mm, and the pressure was 0 .4 Pa, high frequency power supply 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon A silicon oxide film was formed by RF sputtering under a 25 sccm (1:1) atmosphere. The film thickness is 100 nm. The target is quartz (preferably synthetic quartz). A silicon target can be used instead of the silicon target. Instead of the argon mixed gas, oxygen gas may be used. The sputtering gas used in this process has a concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides of ppm. High purity gases having been removed to the ppb level, preferably, are used.

[0225] In addition, when the insulating layer 407 is formed, the insulating layer 407 is heated while removing residual moisture in the treatment chamber. By forming the insulating layer 407, hydrogen, a hydroxyl group, or moisture is prevented from being contained in the insulating layer 407. is preferred.

[0226] To remove the residual moisture in the processing chamber, an adsorption type vacuum pump may be used. For example, , cryopumps, ion pumps, and titanium sublimation pumps can be used. As an exhaust means, it is preferable to add a cold trap to the turbo pump. The treatment chamber is evacuated using a lion pump, and hydrogen atoms and water (H 2 O) Since the compounds and the like are exhausted, the insulating layer 407 formed in the processing chamber is free of hydrogen atoms as much as possible. This is preferable as it is less likely to be trapped.

[0227] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power source; DC sputtering method using a DC power source, pulsed DC sputtering method using a pulsed bias The RF sputtering method is mainly used to deposit insulating films, while the DC The sputtering method is mainly used when forming a metal film.

[0228] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The TA equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0229] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. ECR using a plasma generated by microwaves without glow discharge. A sputtering device that uses a sputtering method can be used.

[0230] In addition, as a method of forming a film using a sputtering method, a target material and a sputtering agent are mixed during film formation. Reactive sputtering is a method of chemically reacting with the Tagas components to form a compound thin film. There are also sputtering methods, such as the bias sputtering method, in which a voltage is also applied to the substrate during film formation.

[0231] The insulating layer 407 is not limited to a single-layer structure, and may have a multilayer structure. From the side, a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer A stacked structure of a nitride insulating layer such as nitride and the oxide insulating layer may be used.

[0232] For example, a silicon oxide layer and a substrate are provided with a space between them that contains high-purity nitrogen from which hydrogen and moisture have been removed. A putter gas is introduced and a silicon nitride layer is formed using a silicon target. In the same manner as for the silicon oxide layer, the silicon nitride layer is also formed while removing the residual moisture in the processing chamber. In addition, when forming a silicon nitride layer, it is preferable to heat the substrate during the film formation. May be heated.

[0233] When a silicon nitride layer and a silicon oxide layer are laminated as the insulating layer 407, the silicon nitride The silicon oxide layer and the silicon nitride layer are formed in the same processing chamber using a common silicon target. A nitrogen-containing sputtering gas is first introduced to the silicon wafer mounted in the processing chamber. The target is used to form a silicon nitride layer, and then the sputtering gas is changed to a sputtering gas containing oxygen. The silicon oxide layer is then deposited using the same silicon target. When using a silicon nitride layer, the silicon oxide layer is formed successively without exposure to the atmosphere. This prevents impurities such as hydrogen and moisture from being adsorbed on the surface of the silicon nitride layer. Cut.

[0234] Next, an oxide semiconductor layer is formed over the insulating layer 407 by a sputtering method.

[0235] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor layer as much as possible, As a treatment, the substrate 400 on which the insulating layer 407 is formed is placed in a preheating chamber of a sputtering device. It is preferable to preheat the substrate 400 to remove impurities such as hydrogen and moisture adsorbed on the substrate 400 and evacuate the substrate. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. The heating is preferably performed on the substrate 400 before the gate insulating layer 402 to be formed later is formed. In addition, the substrate on which the first electrode 415a and the second electrode 415b are formed is It is preferable to carry out the same process for 400. However, these pre-heating processes are omitted. This is also fine.

[0236] Before the oxide semiconductor layer was formed by a sputtering method, argon gas was introduced. Then, a reverse sputtering process is performed to generate plasma, and dust adhering to the surface of the insulating layer 407 is removed. In reverse sputtering, no voltage is applied to the target side, and the target is sputtered in an argon atmosphere. A plasma is generated near the substrate by applying a voltage to the substrate side using a high-frequency power source under atmospheric pressure. The argon atmosphere can be replaced by nitrogen, helium, or oxygen. etc. may also be used.

[0237] The target for the oxide semiconductor layer is a metal oxide target mainly composed of zinc oxide. Other examples of metal oxide targets include In, Ga , and a metal oxide target containing Zn (composition ratio: In 2 O 3 :Ga 2 O 3 :Zn O=1:1:1[mol%], In:Ga:Zn=1:1:0.5[atom%]) In addition, as a target of a metal oxide containing In, Ga, and Zn, In:Ga:Zn=1:1:1[atom%], or In:Ga:Zn=1:1:2[a A target having a composition ratio of SiO 2 A2 weight It is also possible to use a target containing from 10% by weight to 10% by weight of metal oxide. The filling rate is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a high-temperature metal oxide target, the oxide semiconductor layer formed can be a dense film. It is possible.

[0238] Note that the oxide semiconductor layer is formed under a rare gas (typically, argon) atmosphere or an oxygen atmosphere. The heating may be performed under an atmosphere of air or under an atmosphere of rare gas (typically argon) and oxygen. The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, a hydride, or the like. High-purity gas in which the concentration of impurities has been removed to the ppm level, preferably to the ppb level. Use.

[0239] The oxide semiconductor layer is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual water in the treatment chamber. A sputtering gas from which hydrogen and moisture have been removed while removing the molybdenum is introduced, and a metal oxide is deposited on the target. In order to remove residual moisture in the processing chamber, an adsorption type vacuum cleaner is used. It is preferable to use an air pump. For example, a cryopump, an ion pump, or a titanium sub-pump. It is preferable to use a ration pump as the exhaust means. A cold trap may be added. A processing chamber evacuated using a cryopump For example, hydrogen atom, water (H 2 Compounds containing hydrogen atoms (preferably carbon atoms) such as Since the exhaust gas contains oxygen (including compounds containing oxygen), the oxide semiconductor layer formed in the treatment chamber is In addition, the concentration of impurities in the oxide semiconductor layer can be reduced by keeping the substrate at room temperature during the formation of the oxide semiconductor layer. Alternatively, it may be heated to a temperature below 400°C.

[0240] An example of the deposition conditions for the oxide semiconductor layer is as follows: the substrate temperature is room temperature; Distance 110 mm, pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, oxygen and argon ( The conditions are as follows: oxygen flow rate 15 sccm; argon flow rate 30 sccm. When a pulsed direct current (DC) power supply is used, the powdery substances (particles, dust, etc.) generated during film formation can be eliminated. The thickness of the oxide semiconductor layer is preferably 100 nm or less because the thickness distribution of the oxide semiconductor layer can be uniform. The thickness of the film may be 2 nm or more and 200 nm or less, and preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the material of the oxide semiconductor to be used. You just need to select the

[0241] Specific examples of the oxide semiconductor layer formed by the above method include quaternary metal oxides. The ternary metal oxides In-Ga-Zn-O and In -Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn- O, Sn-Al-Zn-O, and binary metal oxides In-Zn-O and Sn-Zn-O , Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, S The oxide semiconductor layer may be an oxide semiconductor layer such as ZnO or Zn-O. The layer may contain Si. In addition, these oxide semiconductor layers may be amorphous. Alternatively, it may be non-single crystal or single crystal. In this embodiment, a sputtering method using In-Ga-Zn-O as a target is used. In this way, an amorphous In-Ga-Zn-O film is formed.

[0242] In addition, InMO 3 (ZnO) m A thin film expressed as (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. A plurality of metal elements. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and Co. InMO 3 (ZnO) m Structure represented as (m>0) Among the oxide semiconductor films, the oxide semiconductor having a structure containing Ga as M is referred to as the In-G It can be called a-Zn-O oxide semiconductor.

[0243] Next, the oxide semiconductor layer is formed into an island-shaped oxide semiconductor layer 4 by a first photolithography process. The oxide semiconductor layer 412 is then processed into an island-shaped oxide semiconductor layer 412 (see FIG. 14A). A resist mask for this purpose may be formed by an inkjet method. When the film is formed by the jet method, a photomask is not used, and therefore the manufacturing cost can be reduced.

[0244] Note that the etching of the oxide semiconductor layer may be either dry etching or wet etching. Well, you can use both.

[0245] When dry etching is performed, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) The inductively coupled plasma etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0246] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl 2 ), boron chloride (BCl 3 ), silicon chloride (SiCl 4 ), carbon tetrachloride (C Cl 4 ) is preferred, but gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (C F 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF3 ), trifluoromethane (CHF 3 ), hydrogen bromide (HBr), oxygen (O 2 ), and these gases are mixed with helium (He) and arsenic (Ar). It is also possible to use a gas containing an added rare gas such as argon (Ar).

[0247] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia hydrogen peroxide solution (for example, 31% by weight hydrogen peroxide solution: 28% by weight ammonia solution: In addition, a solution in which ITO is mixed with water in a ratio of 5:2:2 can be used. 7N (manufactured by Kanto Chemical Co., Ltd.) may be used. The conditions (time, temperature, etc.) of the heating process may be appropriately adjusted depending on the material of the oxide semiconductor.

[0248] Also, when wet etching is performed, the etchant is mixed with the etched material. The removed material is removed by cleaning. The waste etching solution containing the removed material is purified and The material contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials (e.g. rare metals such as indium), resources can be effectively utilized. It can be utilized.

[0249] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 412 by a thermal etching method.

[0250] Next, first heat treatment is performed on the oxide semiconductor layer 412. The temperature of the first heat treatment is 40 The temperature is set to 0° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. The substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is heated in a nitrogen atmosphere for 4 After heat treatment at 50°C for 1 hour, the oxide semiconductor was The first heat treatment prevents water and hydrogen from re-entering the oxide semiconductor layer 412. Hydrogen, water, hydroxyl groups, etc. can be removed.

[0251] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. In the case of the above, an inert gas (typically, a rare gas such as argon) or nitrogen gas can be used. do.

[0252] For example, the first heat treatment is performed in an inert gas heated to a high temperature of 650°C to 700°C. The substrate is moved in and heated for a few minutes, then the substrate is moved out and heated to a high temperature inert gas. You can also use GRTA, which is a method of heating the food from the inside. Processing becomes possible.

[0253] It is preferable that the atmosphere during the first heat treatment does not contain water, hydrogen, etc. Alternatively, gases such as nitrogen, helium, neon, and argon introduced into the heat treatment device may be used. The purity of the gas should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more. Therefore, it is preferable to keep the impurity concentration at 1 ppm or less, preferably 0.1 ppm or less. It is.

[0254] Note that the first heat treatment may be performed depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer. In some cases, the island-shaped oxide semiconductor layer 412 is crystallized and becomes microcrystalline or polycrystalline. For example, the oxide semiconductor layer may be a microcrystalline oxide semiconductor layer having a crystallinity of 80% or more. Even when the first heat treatment is performed, the island-shaped oxide semiconductor layer 412 is not crystallized and remains as an amorphous oxide semiconductor layer. In some cases, the oxide semiconductor layer may become a semiconductor layer. and 20 nm or less (typically 2 nm or more and 4 nm or less) are mixed. In some cases.

[0255] The first heat treatment is performed on the oxide semiconductor layer before the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In this case, the substrate may be removed from the heat treatment apparatus after the first heat treatment. The plate is removed and subjected to a photolithography process.

[0256] In the first heat treatment, impurities such as hydrogen, water, and a hydroxyl group are removed from the oxide semiconductor layer. The main purpose of the heat treatment is to remove oxygen vacancies in the oxide semiconductor layer. For this reason, it is recommended to carry out an oxidation treatment after the first heat treatment. As a specific example of the oxidation treatment, the first heat treatment is followed by an oxygen atmosphere. or a method of performing heat treatment in an atmosphere containing nitrogen and oxygen (nitrogen:oxygen volume ratio = 4:1) Alternatively, a method of performing a plasma treatment in an oxygen atmosphere can be used.

[0257] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After the film formation, a source electrode and a drain electrode are laminated on the oxide semiconductor layer, and then the source electrode and This may be performed either after forming a gate insulating layer on the drain electrode or after forming a gate insulating layer on the drain electrode.

[0258] Next, a conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film may be formed by sputtering or vacuum deposition. Metallic materials such as Cr, Ta, Ti, Mo, W, and Y, and alloy materials containing such metallic materials as components; Examples of the conductive metal oxide include oxide iridium oxide. Indium (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), indium oxide Tin oxide alloy (In 2 O 3 - SnO 2 Indium oxide zinc oxide (ITO) Gold 2 O 3 -ZnO) or the metal oxide material with silicon or silicon oxide Also, Si, Ti, Ta, W, Mo, Cr, Nd, A containing elements such as Sc and Y that prevent the occurrence of hillocks and whiskers in Al films. l material may be used, in which case the heat resistance can be improved.

[0259] The conductive film may have a single layer structure or a stacked structure of two or more layers. 2. A single layer structure of aluminum film containing silicon, and a titanium film laminated on an aluminum film. A three-layer structure in which an aluminum film is layered on top of a Ti film, and a Ti film is layered on top of that. In addition, there are layers of metals such as Al and Cu and layers of Cr, Ta, Ti, Mo, W, etc. Any high melting point metal layer may be laminated.

[0260] Next, a resist mask is formed on the conductive film by a second photolithography process. After selectively etching the first electrode 415a and the second electrode 415b, a resist pattern is formed. The mask is removed (see FIG. 14(B)). The first electrode 415a is a source electrode and a drain electrode. The second electrode 415b functions as one of the source and drain electrodes. Here, the ends of the first electrode 415a and the second electrode 415b are tapered. Etching to the desired shape improves the coverage of the gate insulating layer that is layered on top. It is preferable to use a resist mask for forming the first electrode 415a and the second electrode 415b. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0261] In this embodiment, the first electrode 415a and the second electrode 415b are formed by a sputtering method. A titanium film having a thickness of 150 nm is formed.

[0262] In addition, when the conductive film is etched, the oxide semiconductor layer 412 is removed and the insulating film therebelow is removed. It is necessary to appropriately adjust the materials and etching conditions so that the layer 407 is not exposed. In view of this, in this embodiment, an In-Ga-Zn-O based oxide semiconductor layer is used as the oxide semiconductor layer 412. An oxide semiconductor is used, a titanium film is used as a conductive film, and an ammonia hydrogen peroxide solution is used as an etchant. By using a mixture of ammonia, water, and hydrogen peroxide, the oxide semiconductor layer 412 However, the present invention is not limited to this configuration. That is, part of the oxide semiconductor layer 412 is etched by a second photolithography process. Alternatively, the oxide semiconductor layer may have a groove (a recess).

[0263] The exposure to light during the formation of the resist mask in the second photolithography process uses ultraviolet light and KrF Laser light or ArF laser light may be used. The width of the gap between the bottom end of the first electrode and the bottom end of the second electrode determines the width of the transistor to be formed later. The channel length L of the photoresist is determined. Note that when exposure is performed with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of several nanometers to several tens of nanometers. olet) is used to perform exposure when forming a resist mask in the second photolithography process. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less. In this case, the operating speed of the transistor can be increased and the off-current value is extremely small. This allows for reduced power consumption of the transistor.

[0264] Next, the insulating layer 407, the oxide semiconductor layer 412, the first electrode 415a, the second electrode 415 A gate insulating layer 402 is formed on b (see FIG. 14C).

[0265] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The aluminum layer can be formed as a single layer or a multilayer.

[0266] It is preferable that the gate insulating layer 402 not contain hydrogen. Therefore, the sputtering method can be used to minimize hydrogen in the film formation atmosphere. It is preferable to form a silicon oxide film by a sputtering method. When forming a film, a silicon target or a quartz target is used as the target. The etching is carried out using oxygen or a mixed gas of oxygen and argon as the etching gas.

[0267] The gate insulating layer 402 is made of an oxide film in this order from the first electrode 415a to the second electrode 415b. Alternatively, a silicon oxide layer and a silicon nitride layer may be laminated. For example, the first gate A silicon oxide layer (SiO x (x>0) A second gate insulating layer having a thickness of 50 nm or more and 200 nm or more is formed on the first gate insulating layer. A silicon nitride layer (SiN y (y>0)) is laminated to form a gate insulating film with a thickness of 100 nm. In this embodiment, the pressure is 0.4 Pa, the high frequency power source is 1.5 kW, and oxygen and and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere. A silicon oxide layer with a thickness of 100 nm is formed by F sputtering.

[0268] Next, a resist mask is formed by a third photolithography process and selectively etched. The gate insulating layer 402 is partially removed by etching to form the first electrode 415a and the second electrode 415b. Openings 421a and 421b reaching the second electrode 415b are formed (see FIG. 14(D)). When the resist mask is formed by the inkjet method, a photomask is not used. This reduces manufacturing costs.

[0269] Next, a conductive film is formed over the gate insulating layer 402 and the openings 421a and 421b. The gate electrode 411, the first wiring 414a, the second wiring Form 414b.

[0270] The gate electrode 411, the first wiring 414a, and the second wiring 414b are made of molybdenum, Titanium, Chromium, Tantalum, Tungsten, Aluminum, Copper, Neodymium, Scandium The metal material or the alloy material mainly composed of these is used to form a single layer or a laminate. The gate electrode 411, the first wiring 414a, and the second wiring 414b are formed in two layers. Specific examples of the structure include a molybdenum layer laminated on an aluminum layer, a molybdenum layer laminated on a copper layer, and so on. A titanium nitride layer or a tantalum nitride layer is laminated on a copper layer. or a structure in which a molybdenum layer is laminated on a titanium nitride layer. A specific example of the layer structure is a tungsten layer or a tungsten nitride layer, an aluminum layer, and and a layer of an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a layer of titanium nitride or titanium. A gate electrode layer may be formed using a light-transmitting conductive film. A specific example of the light-transmitting conductive film is a light-transmitting conductive film. An example of the film is a film made of an oxide.

[0271] In this embodiment, the gate electrode 411, the first wiring 414a, and the second wiring 414b are A titanium film having a thickness of 150 nm is formed by sputtering.

[0272] Next, a second heat treatment (preferably a second heat treatment) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, the heating is performed at a temperature of 00° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarization insulating layer is formed over the transistor 410.

[0273] In addition, heat treatment was performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by maintaining a constant heating temperature or by heating from room temperature to Then, the temperature was increased to 100°C or more and 200°C or less, and then decreased from the heating temperature to room temperature. This heat treatment may be repeated several times. In addition, this heat treatment is performed under reduced pressure before the formation of the oxide insulating layer. It is preferable to carry out the heat treatment under reduced pressure since the heating time can be shortened. .

[0274] Through the above process, a high-purity acid is obtained with reduced concentrations of hydrogen, water, hydrides, and hydroxides. A transistor 410 having a nitride semiconductor layer 412 can be formed (FIG. 14(E)). The transistor 410 is the same as the first transistor 6401 described in Embodiment 1. etc. can be applied.

[0275] A protective insulating layer or a planarization insulating layer for planarization may be provided over the transistor 410. The protective insulating layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a nitride layer. A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or a stacked layer. The planarizing insulating layer may be made of polyimide, acrylic resin, benzocyclobutene resin, or polyimide. For example, organic materials having heat resistance, such as polyamide and epoxy resins, can be used. In addition to organic materials, low-k materials, siloxane resins, PSG (ringa Glass, BPSG (borophosphorus glass), etc. can also be used. A planarizing insulating layer may be formed by stacking a plurality of insulating films.

[0276] Here, the siloxane-based resin is a Si- It corresponds to a resin containing an O-Si bond. Siloxane-based resins have organic groups (e.g. An alkyl group or an aryl group, or a fluoro group may be used. It's fine to do so.

[0277] The method for forming the flattening insulating layer is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A fukota or the like can be used.

[0278] As described above, when forming an oxide semiconductor layer, residual moisture in the reaction atmosphere is removed. By this, the concentrations of hydrogen and hydride in the oxide semiconductor layer can be reduced.

[0279] The transistor having the oxide semiconductor layer described in this embodiment is used to constitute a display portion of a display device. By using this in a pixel that forms a storage capacitor, the off-current can be reduced. This allows the voltage to be maintained for a longer period, reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. In addition, it is possible to switch between still images and moving images without malfunction. .

[0280] (Embodiment 4) In this embodiment, an example of the structure of the first transistor 6401 described in Embodiment 1 will be described. An example of a manufacturing method thereof will be described. An example of a transistor structure and an example of a manufacturing method thereof will be described with reference to FIG. do.

[0281] 15A to 15E show examples of cross-sectional structures of transistors. The transistor 390 is one of the bottom gate structures and is also called an inverted staggered transistor. The transistor 390 may be the same as the first transistor 6401 described in the first embodiment. The transistor 390 can be used as a single-gate transistor. However, the present invention is not limited to this configuration. A transistor having a multi-gate structure having a plurality of channel formation regions may be used.

[0282] Hereinafter, a transistor 390 is fabricated on a substrate 394 using FIGS. The method will be explained.

[0283] First, a conductive film is formed on a substrate 394, and then a gate is formed by a first photolithography process. The end of the gate electrode 391 is tapered, so that the upper layer This is preferable because it improves the coverage of the gate insulating layer. If the resist mask is formed by the ink-jet method, the photomask Since no additional heat is used, the manufacturing cost can be reduced.

[0284] Here, the material of the substrate 394 is the same as that of the substrate 400 described in the third embodiment. The material and film formation method of the gate electrode 391 may be the same as those in the embodiment. The gate electrode 411 described in 3 can be used.

[0285] Note that an insulating film serving as a base film may be provided between the substrate 394 and the gate electrode 391 . The undercoat film has a function of preventing the diffusion of impurity elements from the substrate 394. A silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. The insulating film 10 may have a single layer structure or a laminate structure of a plurality of films selected from these.

[0286] Next, a gate insulating layer 397 is formed on the gate electrode 391 .

[0287] The gate insulating layer 397 is formed by depositing an oxide film using a plasma CVD method or a sputtering method. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an alumina layer. The gate insulating layer 397 may be formed of a single layer or a stacked layer. To prevent a large amount of hydrogen from being contained, a gate insulating layer 397 is formed by sputtering. When the silicon oxide film is formed by the sputtering method, A silicon or quartz target is used as the target, and oxygen is used as the sputtering gas. The etching is carried out using nitrogen or a mixed gas of oxygen and argon.

[0288] The gate insulating layer 397 is made up of a silicon nitride layer and a silicon oxide layer in this order from the gate electrode 391 side. For example, a sputtered silicon oxide film may be used as the first gate insulating layer. The silicon nitride layer (SiN y (y>0) A second gate insulating layer having a thickness of 5 nm to 300 nm is formed on the first gate insulating layer. Silicon oxide layer (SiO x (x>0)) is laminated to form a gate insulating layer with a thickness of 100 nm. Just do that.

[0289] Next, an oxide semiconductor layer 393 having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 397. (See FIG. 15(A)).

[0290] Here, the material, the deposition method, and the like of the oxide semiconductor layer 393 are the same as those of the oxide semiconductor layer 392 described in Embodiment 3. A semiconductor layer similar to the island-shaped oxide semiconductor layer 412 can be used.

[0291] For example, examples of deposition conditions when the oxide semiconductor layer 393 is formed by a sputtering method are as follows: The distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, and the direct current (DC) is The conditions are 0.5 kW power supply and oxygen (oxygen flow rate 100%). By using a direct current (DC) power supply, the powdery substances (also called particles or dust) generated during film formation can be eliminated. This is preferable because the thickness of the oxide semiconductor layer 393 can be reduced and the thickness distribution can be uniform. The thickness of the film is preferably 2 nm to 200 nm, more preferably 5 nm to 30 nm. Note that the appropriate thickness varies depending on the material of the oxide semiconductor to be used. The thickness can be selected.

[0292] Note that before the oxide semiconductor layer 393 is formed, argon gas is introduced to generate plasma. 3. To remove dust adhering to the surface of the gate insulating layer 397, reverse sputtering is performed. is preferred.

[0293] In addition, hydrogen, a hydroxyl group, and moisture are preferably contained in the gate insulating layer 397 and the oxide semiconductor layer 393. In order to prevent this from being included, the pre-heating chamber of the sputtering equipment is used as a pre-treatment for film formation. A substrate 394 on which a gate electrode 391 is formed, or a gate insulating layer 397 is formed The substrate 394 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 394 are desorbed and exhausted. The preheating temperature is preferably 100° C. or higher and 400° C. or lower, and more preferably 1 The temperature should be between 50 and 300 degrees Celsius. In addition, this pre-heating is preferably performed before the formation of the protective insulating layer 396. The same process may be carried out for the substrate 394 on which the first electrodes 5a and 395b have been formed.

[0294] Next, the oxide semiconductor layer is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 3 The island-shaped oxide semiconductor layer 399 is processed into an oxide semiconductor layer 399 (see FIG. 15B). Regarding the processing method for forming the island-shaped oxide semiconductor layer 412 described in Embodiment 3, The same as the law may be adopted.

[0295] Note that reverse sputtering is performed before forming a conductive film in the next step, and the oxide semiconductor layer 399 and the gate It is preferable to remove resist residues and the like adhering to the surface of the gate insulating layer 397.

[0296] Next, a conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The film may be formed by sputtering, vacuum deposition, or the like. The elements are selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or Alloys containing the elements or alloys combining multiple of these elements can be used. In addition, any of the following may be used: manganese, magnesium, zirconium, beryllium, or thorium. One or more materials may be used. A specific example of the conductive film having a light-transmitting property is a film made of a conductive oxide having a light-transmitting property. Membranes are included.

[0297] The conductive film may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of aluminum film containing silicon, and a two-layer structure of titanium film laminated on aluminum film The structure is a Ti film, an aluminum film is layered on top of the Ti film, and a Ti film is layered on top of that. Examples include a three-layer structure that is formed by depositing a film.

[0298] Next, a resist mask is formed on the conductive film by a third photolithography process. After selectively etching the substrate to form a first electrode 395a and a second electrode 395b, a resist pattern is formed. The mask is then removed (see FIG. 15(C)). Here, when etching the conductive film, an acid is used. The gate insulating layer 397 is not exposed when the nitride semiconductor layer 399 is removed. It is necessary to appropriately adjust the material and etching conditions. The oxide semiconductor layer 399 is an In-Ga-Zn-O oxide semiconductor, and the conductive film is A titanium film was used, and an ammonia hydrogen peroxide mixture (ammonia, water, hydrogen peroxide solution) was used as an etchant. By using the mixture, a part of the oxide semiconductor layer 399 is not etched. However, the present invention is not limited to this configuration. In this step, a part of the oxide semiconductor layer 399 is etched to form an oxide semiconductor layer having a groove (a recess). It may also be a conductive layer.

[0299] The third photolithography process uses ultraviolet light and KrF for exposure when forming the resist mask. Laser light or ArF laser light may be used. The gap width between the lower end of the first electrode 395a and the lower end of the second electrode 395b determines the width of the gap. The channel length L of the transistor to be fabricated is determined. Note that the channel length L is less than 25 nm. When performing exposure, extreme ultraviolet rays with extremely short wavelengths of several nm to several tens of nm are used. The resist mask for the third photolithography step is made using Ultraviolet. Exposure to extreme ultraviolet light provides high resolution and a large depth of focus. The channel length L of the transistor to be formed later is set to 10 nm or more and 1000 nm or less. This allows the circuit to operate at high speed, and the off-current is extremely small, The power consumption of the transistor can be reduced.

[0300] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and the shape is further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of exposure masks can be reduced. This also eliminates the need for a corresponding photolithography process, making it possible to simplify the process.

[0301] Also, N 2 O, N 2 or exposed by plasma treatment using a gas such as Ar. Water adsorbed on the surface of the oxide semiconductor layer 399 may be removed. Alternatively, the plasma treatment may be performed using a mixed gas of argon and argon. Then, a plasma treatment is performed.

[0302] Next, after the plasma treatment, the exposed oxide semiconductor A protective insulating film 396 is formed in contact with the layer 399, the first electrode 395a, and the second electrode 395b. At this time, the oxide semiconductor layer 399 and the protective insulating layer 396 are formed (see FIG. 15D). To prevent hydrogen, hydroxyl or moisture from being contained in the processing chamber, remove any residual moisture in the processing chamber. In order to remove residual moisture in the treatment chamber, a protective insulating layer 396 is preferably formed. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump. It is preferable to use a titanium sublimation pump as the exhaust means. A cryopump with a cold trap may be used. The process chamber is filled with hydrogen atoms, water (H 2 O) and other compounds containing hydrogen atoms are exhausted. Therefore, the concentration of impurities contained in the protective insulating layer 396 formed in the treatment chamber can be reduced. do.

[0303] In this embodiment, an oxide insulating layer is formed as the protective insulating layer 396. As a method for forming the sixth insulating film 6, the island-shaped oxide semiconductor layer 399, the first electrode 395a, and the second electrode 395b are The substrate 394 on which the pole 395b is formed is left at room temperature or heated to a temperature below 100° C. Then, a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced, and a silicon semiconductor is formed. The silicon oxide layer is formed using a target of 10 ... Instead of the silicon layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer may be used. A layer of aluminum or the like can also be used.

[0304] For example, a silicon target with a purity of 6N and doped with boron (resistance value of 0.0 The distance between the substrate and the target (TS distance) was 89 mm and the pressure was 0.4 Pa, DC power supply 6kW, oxygen (oxygen flow rate 100%) atmosphere, pulse DC A silicon oxide layer is formed by sputtering. The thickness of the silicon oxide layer is 300 nm. It is also possible to use quartz (preferably synthetic quartz) instead of the silicon target. The sputtering gas may be oxygen or a mixed gas of oxygen and argon.

[0305] Further, when the protective insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other, The heat treatment is preferably performed at 0° C. The heat treatment can be performed to form a film in the oxide semiconductor layer 399. Impurities such as hydrogen, moisture, hydroxyl groups, or hydrides are diffused into the protective insulating layer 396. In this case, the impurities contained in the oxide semiconductor layer 399 can be further reduced.

[0306] By the above steps, an oxide semiconductor having reduced concentrations of hydrogen, moisture, hydroxyl groups, or hydrides is obtained. A transistor 390 having a dielectric layer 392 can be formed (see FIG. 15(E)). As described in this embodiment, when an oxide semiconductor layer is formed, the residual gas in the reaction atmosphere is The residual water is removed to reduce the concentrations of hydrogen and hydrides in the oxide semiconductor layer. This results in an intrinsic or substantially intrinsic semiconductor.

[0307] Note that an insulating layer may be further provided on the protective insulating layer 396. An insulating layer 398 is formed on the edge layer 396. The insulating layer 398 may be a silicon nitride film, a nitride film, or the like. A silicon oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like may be used. stomach.

[0308] The insulating layer 398 is formed by 10 A sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed by heating at a temperature of 0°C to 400°C A silicon nitride film is formed by introducing a gas into the target and using a silicon semiconductor target. In the same manner as the protective insulating layer 396, the insulating layer 398 is also formed while removing the residual moisture in the processing chamber. During the deposition of the insulating layer 398, the substrate 394 is heated to 100° C. to 400° C. By heating, hydrogen or moisture contained in the oxide semiconductor layer 399 is removed from the insulating layer 398 In this case, heat treatment must be performed immediately after the protective insulating layer 396 is formed. It's okay.

[0309] A silicon oxide layer is formed as a protective insulating layer 396, and a silicon nitride layer is formed as an insulating layer 398. When forming a silicon layer, the silicon oxide layer and the silicon nitride layer are formed in the same processing chamber. A silicon target can be used for deposition. First, an etching gas containing oxygen is introduced. A silicon oxide layer is formed using a silicon target mounted in the processing chamber, and then Next, the etching gas was changed to a nitrogen-containing etching gas and the same silicon target was used. The silicon oxide layer and the silicon nitride layer are formed without being exposed to the atmosphere. Since it can be formed continuously, impurities such as hydrogen and moisture are absorbed on the surface of the silicon oxide layer. In addition, a silicon oxide layer is formed as the protective insulating layer 396, and the insulating After a silicon nitride layer is stacked as the layer 398, hydrogen or Heat treatment (at a temperature of 100° C. to 400° C.) is performed to diffuse moisture into the oxide insulating layer. It is more preferable that:

[0310] After the protective insulating layer 396 is formed, the protective insulating layer 396 is further heated in air at 100° C. to 200° C. for 1 hour or more and 3 hours or more. The heating treatment may be performed for 0 hours or less. This heating treatment is performed by maintaining a constant heating temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then the heating temperature may be increased to 100°C or more and 200°C or less. The heating process may be repeated several times to lower the temperature from the temperature of the oxide insulating layer to room temperature. Before forming the edge layer, the heat treatment may be performed under reduced pressure. By performing the heat treatment under reduced pressure, the heating time can be shortened. It is possible.

[0311] The above process is carried out at temperatures below 400℃, so the thickness is less than 1mm and the length of each side is 1m. It can also be applied to manufacturing processes that use glass substrates with temperatures of 400°C or less. Since all processes can be performed at the processing temperature, the energy required to manufacture the display panel is reduced. Consumption can be reduced.

[0312] The transistor having the oxide semiconductor layer described in this embodiment is used to constitute a display portion of a display device. By using this in a pixel that forms a storage capacitor, the off-current can be reduced. This allows the voltage to be maintained for a longer period, reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. In addition, it is possible to switch between still images and moving images without malfunction. .

[0313] (Embodiment 5) In this embodiment, an example of the structure of the first transistor 6401 described in Embodiment 1 will be described. An example of a manufacturing method thereof will be described. An example of a transistor structure and an example of a method for manufacturing the same will be described with reference to FIG. .

[0314] 16A to 16D show examples of cross-sectional structures of transistors. The transistor 360 shown in FIG. 1 is called a channel protection type (also called a channel stop type). This transistor is one of the bottom gate structures that are used in transistors, and is also called an inverted staggered transistor. The transistor 360 can be used as the first transistor 6401 described in Embodiment 1. Although the transistor 360 is a transistor having a single gate structure, The present invention is not limited to this configuration. Alternatively, a transistor having a multi-gate structure having a plurality of gate electrodes may be used.

[0315] Hereinafter, a transistor 360 is fabricated on a substrate 320 using FIGS. The method will be explained.

[0316] First, a conductive film is formed on a substrate 320, and then a gate is formed by a first photolithography process. The substrate 320 is made of the same material as that of the substrate 3 described in the fourth embodiment. The same material and film formation method of the gate electrode 361 can be used. For the gate electrode 391, the same one as that of the gate electrode 391 described in the fourth embodiment can be used.

[0317] Next, a gate insulating layer 322 is formed on the gate electrode 361. The material to be used is the same as that of the gate insulating layer 397 described in the fourth embodiment. In this embodiment, the gate insulating layer 322 is formed by a plasma CVD method to a thickness of 1 A silicon oxynitride layer having a thickness of 00 nm or less is formed.

[0318] Next, an oxide semiconductor layer having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 322. The oxide semiconductor layer is then processed into an island shape by a second photolithography process. The material, film formation method, processing method, etc. of the oxide semiconductor layer are the same as those of the island-shaped oxide semiconductor layer described in the fourth embodiment. The same material as the conductor layer 399 can be used. In this embodiment, the oxide semiconductor layer The film was formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. do.

[0319] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and an oxide semiconductor is The layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to air. By not applying heat to the oxide semiconductor layer, water or hydrogen can be prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 332 can be obtained. (See FIG. 16(A)).

[0320] Next, N 2 O, N 2 Alternatively, plasma treatment is performed using a gas such as Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0321] Next, an oxide insulating layer was formed over the gate insulating layer 322 and the oxide semiconductor layer 332. After that, a resist mask is formed by a third photolithography process, and selective etching is performed. After forming the oxide insulating layer 366, the resist mask is removed.

[0322] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 366. The substrate temperature during film formation should be between room temperature and 300° C. In the case of the above, the temperature is set at 100°C. The deposition of silicon oxide film by sputtering method is carried out using rare gas (typically Argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen atmosphere. The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. A silicon oxide film can be formed in contact with the oxide semiconductor layer by sputtering under atmospheric pressure. The oxide insulating layer 366 formed of the oxide is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film is used to block these substances from entering from the outside. A silicon oxide nitride film, an aluminum oxide film, an aluminum oxide nitride film, or the like is used. There can be.

[0323] At this time, hydrogen, a hydroxyl group, or moisture is added to the oxide semiconductor layer 332 and the oxide insulating layer 366. In order to prevent the inclusion of moisture in the processing chamber, the oxide insulating layer 366 is formed while removing the remaining moisture in the processing chamber. It is preferable to remove the residual moisture in the processing chamber as described in other embodiments. The method described in can be used.

[0324] Next, a second heat treatment (preferably a second heat treatment) is performed in an inert gas atmosphere or an oxygen gas atmosphere. It is preferable to carry out the heating at a temperature of 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. Then, heating is performed while part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 366. I feel heated.

[0325] In this embodiment, the oxide semiconductor layer 364 is formed in a region that is not covered with the oxide insulating layer 366. The oxide insulating layer 332 is subjected to a heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The oxide semiconductor layer 332 in the region not covered by 66 is etched under a nitrogen or inert gas atmosphere. Alternatively, when heat treatment is performed under reduced pressure, dehydrogenation occurs and oxygen deficiency occurs, resulting in low resistance. For example, it is recommended to perform a heat treatment at 250°C for 1 hour in a nitrogen atmosphere. .

[0326] The oxide semiconductor layer 332 provided with the oxide insulating layer 366 is subjected to heat treatment in a nitrogen atmosphere. Due to this phenomenon, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 16 In FIG. 1B, the oxide semiconductor layer 362 has a portion (indicated by a hatched area and a white area).

[0327] Next, a conductive film is formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the conductive film, a resist mask is formed by a fourth photolithography process, and a selective After selectively etching the first electrode 365a and the second electrode 365b, a resist is The mask is then removed (see FIG. 16(C)).

[0328] The materials of the first electrode 365a and the second electrode 365b include Al, Cr, Cu, Ta, An element selected from Ti, Mo, and W, or an alloy containing the above-mentioned elements, or The metal conductive film may be a single-layer structure or an alloy film made by combining the above elements. Alternatively, it may have a laminated structure of two or more layers.

[0329] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. After the resistance of the oxide semiconductor layer is reduced by performing heat treatment for oxidation, a part of the oxide semiconductor layer is selectively treated with excess oxygen. As a result, the channel forming region 363 overlapping with the gate electrode 361 becomes an I-type. A low resistance source region 364a overlaps the first electrode 365a, and a low resistance source region 364b overlaps the second electrode 365b. The low-resistance drain region 364b is formed in a self-aligned manner. A transistor 360 is formed.

[0330] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100° C. or 200° C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By doing so, the heating time can be shortened.

[0331] Note that in the oxide semiconductor layer overlapping with the second electrode 365b (and the first electrode 365a), By forming a low-resistance drain region 364b (or a low-resistance source region 364a) As a result, the reliability of the transistor can be improved. By forming the region 364b, the low resistance drain region 364b and the channel It is possible to provide a structure in which the conductivity can be changed stepwise over the formation region 363. Therefore, the second electrode 365b is connected to a wiring that supplies a high power supply potential VDD. In this case, even if a high electric field is applied between the gate electrode 361 and the second electrode 365b, a low resistance The drain region acts as a buffer to prevent localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is possible to achieve such a configuration.

[0332] Next, a protective insulating layer is formed on the first electrode 365a, the second electrode 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See FIG. 16(D)).

[0333] The transistor having the oxide semiconductor layer described in this embodiment is used to constitute a display portion of a display device. By using this in a pixel that forms a storage capacitor, the off-current can be reduced. This allows the voltage to be maintained for a longer period, reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. It is also possible to switch between still images and moving images without malfunction. do.

[0334] (Embodiment 6) This embodiment shows another example of a transistor that can be applied to the display device disclosed in this specification. The transistor 350 described in this embodiment is used in each pixel of the pixel portion in Embodiment 1. It can be used for the transistor 6401 and the like.

[0335] The transistor 350 shown in FIG. 17D has a single gate structure. However, the present invention is not limited to this configuration. A transistor having a multi-gate structure having a plurality of formation regions may also be used.

[0336] Hereinafter, a transistor 350 is fabricated on a substrate 340 using FIGS. 17(A) to 17(D). The process will be explained.

[0337] First, a conductive film is formed on a substrate 340, and then a gate is formed by a first photolithography process. In this embodiment, the gate electrode 351 is formed with a thickness of 150 nm. The tungsten film is formed by sputtering.

[0338] Next, a gate insulating layer 342 is formed on the gate electrode 351. A silicon oxynitride film having a thickness of 100 nm or less is formed as the insulating layer 342 by the plasma CVD method. Complete.

[0339] Next, a conductive film is formed on the gate insulating layer 342, and the conductive film is formed by a second photolithography process. A resist mask is formed on the conductive film, and selective etching is performed to form a source electrode 355a and a drain electrode 355b. After the rain electrode 355b is formed, the resist mask is removed (see FIG. 17(A)).

[0340] Next, an oxide semiconductor layer 345 is formed (see FIG. 17B). As the gallium nitride semiconductor layer 345, a metal oxide target of In-Ga-Zn-O system was used. Then, the oxide semiconductor layer 345 is formed by a third photolithography process. In this manner, the oxide semiconductor layer is processed into an island shape.

[0341] In the process of forming the oxide semiconductor layer 345, the oxide semiconductor layer 345 is formed by removing residual moisture in the treatment chamber while oxidizing the oxide semiconductor layer 345. By forming the oxide semiconductor layer 345, hydrogen, a hydroxyl group, or It is preferable to prevent moisture from being contained in the processing chamber. Alternatively, the methods described in the other embodiments can be used.

[0342] Next, a first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer. The temperature of the first heat treatment is 400° C. or more and 750° C. or less, preferably 400° C. or more so as to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor is The conductor layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. By preventing the oxide semiconductor layer 346 from being heated, water or hydrogen can be prevented from being re-mixed into the oxide semiconductor layer 346. (See FIG. 17(C)).

[0343] In the first heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for a few minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. A GRTA may be conducted from the

[0344] Next, the oxide insulating layer 356 is formed in contact with the oxide semiconductor layer 346. The oxide insulating layer 356 has a thickness of at least 1 nm. The oxide insulating layer can be formed by a method that does not mix the oxides (for example, a sputtering method). If hydrogen is contained in the edge layer 356, the hydrogen may penetrate into the oxide semiconductor layer or may be oxidized by the hydrogen. Oxygen is extracted from the oxide semiconductor layer, and the resistance of the back channel of the oxide semiconductor layer is reduced. (N-type) and a parasitic channel may be formed. It is important to use a deposition method that results in layer 356 containing as little hydrogen as possible. .

[0345] Note that the material, the deposition method, and the like of the oxide insulating layer 356 are the same as those in the protective layer of the fourth embodiment. A similar insulating layer as the insulating layer 396 can be used.

[0346] Next, a second heat treatment (preferably a second heat treatment) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. The second heat treatment is performed at 250° C. for 1 hour under atmospheric pressure. The layer is heated while in contact with oxide insulating layer 356 .

[0347] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. After the resistance is reduced by heat treatment for oxidation, the oxide semiconductor layer is made into an oxygen-excess state. As a result, an i-type oxide semiconductor layer 352 is formed. 350 is formed.

[0348] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100° C. or 200° C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By performing the heat treatment, the heating time can be shortened. Hydrogen is taken into the oxide insulating layer, and a normally-off transistor can be obtained. This makes it possible to improve the reliability of the display device.

[0349] Note that an insulating layer may be further provided over the oxide insulating layer 356. An insulating layer 343 is formed on the insulating layer 356 (see FIG. 17(D)). The materials and film-forming methods are the same as those of the protective insulating layer 398 in the fourth embodiment. It is possible.

[0350] In addition, a planarization insulating layer may be provided for the purpose of planarizing the surface on the insulating layer 343.

[0351] The transistor having the oxide semiconductor layer described in this embodiment is used to constitute a display portion of a display device. By using this in a pixel that forms a storage capacitor, the off-current can be reduced. This allows the voltage to be maintained for a longer period, reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. It is also possible to switch between still images and moving images without malfunction. do.

[0352] (Embodiment 7) In this embodiment mode, one mode of a display device in which a luminous layer is provided in a pixel portion will be described.

[0353] FIG. 18 is a cross-sectional view of a pixel portion having a bottom emission structure, and shows a transistor (drive A light-emitting element 7 electrically connected to the transistor 7211 2 is a cross-sectional view of a section including 212.

[0354] The transistor 7211 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer over a substrate. The gate insulating layer and the gate electrode layer are connected to the source electrode layer and the drain electrode layer. A wiring layer is provided so as to be electrically connected to each other.

[0355] In addition, an insulating layer 7231 is formed to cover the transistor 7211. A luminous layer 7233 having an opening is provided. A light-transmitting conductive film 7217 is formed over the overcoat layer 7234 and the insulating layer 7235. The drain electrode 7230 of the transistor 7211 and the conductive film 721 7 is a phosphorescent layer 7233, an overcoat layer 7234, an insulating layer 7235, and an insulating layer 723 The light emitting element is electrically connected to the conductive film 7217 through an opening formed in the conductive film 7217. A first electrode 7213 of the light-emitting element 7212 is provided in contact with the first electrode 7213 of the light-emitting element 7212. The EL layer 7214 is sandwiched between a first electrode 7213 and a second electrode 7215. A shielding film 7216 is provided on the second electrode 7015 .

[0356] Note that the transistor 7211 and the light-emitting element 7212 are described in Embodiments 3 to 6. Since the above-mentioned method can be used to fabricate the semiconductor device, detailed description thereof will be omitted here.

[0357] The light-storing layer 7233 contains a light-storing material and stores the light emitted by the adjacent light-emitting element. Even after the optical element stops emitting light, the phosphorescent material contained in the phosphorescent layer 7233 continues to emit light. In the embodiment, copper activated zinc sulfide (ZnS:Cu) is used as the phosphorescent material. Phosphors that use sulfides such as trontium (SrS) as a base material and an activator added, and phosphors that use rare earth elements Alkaline earth aluminates activated with rare earth elements can also be used. Specific examples of earth aluminates include CaAl 2 O 4 :Eu, CaAl 2 O 4 :Nd,S r 4 Al 14 O 25 :Eu, Sr 4 Al 14 O 25 :Dy, SrAl 2 O 4 :Eu, and SrAl 2 O 4 In addition, when inorganic particles are used as the phosphorescent material, the particle size If the particle size is less than 1 nm, the phosphorescence may be lost. In this case, the flatness of the phosphorescent layer may be impaired, making it difficult to fabricate the light-emitting device. Therefore, the particle size is preferably 1 nm or more and 10 μm or less.

[0358] The time that the phosphorescent layer 7233 continues to emit light can be changed depending on the type of phosphorescent material. In other words, the amount of time the light continues to emit, or what is called the afterglow time, varies depending on the type of phosphorescent material. The material can be selected according to the application. For example, if the display content does not need to be changed frequently, Electronic devices equipped with display devices used in various applications (e.g., electronic paper) have a long afterglow time. It is preferable to select and use a phosphorescent material. In addition, it is necessary to rewrite the display relatively frequently. Electronic equipment with a display device for certain applications (e.g., television receivers) have a decay time It is preferable to select and use a short phosphorescent material.

[0359] The phosphorescent layer 7233 may also contain a binder polymer. In this case, A droplet ejection method such as an inkjet method using a dispersed liquid, a printing method, a spin coating method, The method can be appropriately selected from etching methods using photolithography techniques. do.

[0360] In addition, in order to flatten the unevenness of the surface of the phosphorescent layer 7233, the surface of the phosphorescent layer 7233 is covered with It is preferable to cover the insulating layer 7234 with an overcoat layer 7234. It is preferable to cover the insulating layer with an overcoat layer 7234 and A contact hole formed in the protective insulating layer 7235 and reaching the drain electrode 7230 is disposed at a position overlapping with the partition wall 7219.

[0361] In addition, the position where the phosphorescent layer 7233 is provided is not limited to between the user of the display device and the light emitting element. For example, a light-emitting element having a dual emission structure in which an EL layer is sandwiched between a pair of light-transmitting electrodes is In this way, when the light-emitting element has a light-transmitting property, the phosphorescent layer 7233 is In other words, the phosphorescent layer and the display layer can be arranged on the rear side of the light-emitting layer when viewed from the user of the device. It is also possible to place a light emitting element between the user of the device and the light emitting element. When the light source is disposed between the user and the phosphorescent layer, the phosphorescent layer does not necessarily have to be transparent. This allows for a wider range of material choices. Specifically, phosphorescent materials with particle sizes of 100 μm or less can be used. will be available.

[0362] As described above, the display device described in this embodiment includes a high-purity oxide semiconductor layer. In addition to the transistor having the off-state current, a light-storing layer is included in the pixel portion. In addition to having a transistor with reduced resistance in the pixel, the pixel also has a phosphorescent layer, which makes it possible to emit light. Even if the light emission interval is long, flicker is not noticeable. That is, the display device described in this embodiment reduces power consumption and is capable of displaying still images. It can be made to be of excellent quality.

[0363] (Embodiment 8) In this embodiment, an electronic device having the display device described in the above embodiment is However, the electronic devices to which the present invention can be applied are not limited to the specific examples shown below. It is not something that can be determined.

[0364] The electronic device shown in FIG. 19A is a portable game machine. A speaker 9633, an operation key 9635, a connection terminal 9636, a recording medium reading unit 9672, etc. The portable gaming machine also reads the programs or data recorded on the recording medium. and a function to share information with other portable gaming machines via wireless communication. The functions of the portable gaming machine are not limited to these, and may include various functions. It is possible to have the ability.

[0365] The electronic device shown in FIG. 19B is a digital camera. , speaker 9633, operation keys 9635, connection terminal 9636, shutter button 9676 The digital camera has a function of taking still images and a function of taking videos. The function of automatically or manually correcting the captured image, and storing the captured image information in a memory element It has functions such as storing the captured image, displaying the captured image information on the display unit, and receiving images on a television. However, the functions of the digital camera are not limited to those described above, and the digital camera may have various functions. It is possible.

[0366] The electronic device shown in FIG. 19C is a television receiver. The television receiver includes a speaker 9633, operation keys 9635, and a connection terminal 9636. A function that processes television radio waves and converts them into image signals; a function that processes image signals to produce signals suitable for display and a function for converting the frame frequency of the image signal. However, the functions of the television receiver are not limited to those described above, and the television receiver may have a variety of functions.

[0367] The electronic device shown in FIG. 20A is a computer. Speaker 9633, operation keys 9635, connection terminal 9636, pointing device 96 81, and an external connection port 9680. The computer stores various information (still images, video The function of displaying text images, etc. on the display, and the function of displaying images using various software (programs) a function for controlling processing using wireless or wired communication; Functions for connecting to computer networks, and transmission or use of communication functions for various data However, the functions of a computer are not limited to these. It can have a variety of functions.

[0368] The electronic device shown in FIG. 20B is a mobile phone. The mobile phone has a speaker 9633, operation keys 9635, a microphone 9638, etc. , the ability to display various information (still images, videos, text images, etc.), calendars, dates, or The function to display the time, etc. on the display, the function to operate or edit the information displayed on the display, The device may have a function to control the processing by various software (programs). The functions of the mobile phone are not limited to those described above, and the mobile phone can have a variety of functions.

[0369] The electronic device shown in FIG. 20C is an electronic paper. The electronic paper has operation keys 9635 and the like. Functions for displaying images, calendars, dates, or times on the display unit, and display The ability to manipulate or edit the information displayed on the screen, using various software (programs) The electronic paper may have a function to control the processing. The electronic paper can have various functions. Examples include electronic books (also called e-books), posters, and train rides. Examples include in-car advertising of goods.

[0370] The electronic device shown in FIG. 20D is a digital photo frame. The display unit 9703 is capable of displaying various images. For example, by displaying image data taken with a digital camera, it can be used as a normal photo frame. It can function similarly.

[0371] The digital photo frame is equipped with an operation unit, external connection terminals (USB terminal, USB cable, etc.) The device has a terminal that can be connected to various cables, a recording medium insertion section, etc. Although it may be incorporated on the same surface as the display unit, providing it on the side or back improves the design. For example, it is preferable to insert a digital camera into the recording medium insertion section of a digital photo frame. Insert a memory that stores image data taken with the camera and import the image data. Image data can be displayed on the display portion 9703 .

[0372] The digital photo frame may also have a function for wirelessly transmitting and receiving information. In this case, the desired image data is wirelessly imported into the digital photo frame and displayed. However, the functions of the digital photo frame are not limited to these. , can have a variety of functions.

[0373] By applying the display device according to one embodiment of the present invention to these electronic devices, still images and the like can be displayed. This allows for lower power consumption when displaying still images rather than moving images. This book is for electronic devices such as digital cameras, electronic paper, and digital photo frames, which are often used. When a display device according to one embodiment of the present invention is used, the effect of reducing power consumption is remarkable. Particularly preferred. [Explanation of symbols]

[0374] 1000 display devices 1001 Display Panel 1002 Signal generation circuit 1003 Memory circuit 1004 Comparison circuit 1005 Selection circuit 1006 Display control circuit 1007 Drive circuit section 1008 Pixel section 1009A Gate line driver circuit 1009B Signal line driver circuit 1010 Frame Memory

Claims

1. A pixel portion, a gate line driving circuit, and a conductive film are included. the pixel portion includes a light-emitting element, a first transistor, and a second transistor in a pixel; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, the source or drain of the second transistor is always electrically connected to the gate of the first transistor; a potential corresponding to an image signal is supplied to a gate of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the gate line driver circuit has a function of supplying a signal to a gate of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; the first transistor and the second transistor do not overlap with the conductive film, A power supply potential is applied to the conductive film. Display device.

2. A display device having a function of changing a frequency of writing an image signal to a pixel portion, the display device includes the pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, and a second transistor in a pixel; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, the source or drain of the second transistor is always electrically connected to the gate of the first transistor; a potential corresponding to an image signal is supplied to a gate of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the gate line driver circuit has a function of supplying a signal to a gate of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; the first transistor and the second transistor do not overlap with the conductive film, A power supply potential is applied to the conductive film. Display device.

3. A pixel portion, a gate line driving circuit, and a conductive film are included. the pixel portion includes a light-emitting element, a first transistor, and a second transistor in a pixel; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, the source or drain of the second transistor is always electrically connected to the gate of the first transistor; a potential corresponding to an image signal is supplied to a gate of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the gate line driver circuit has a function of supplying a signal to a gate of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; the first transistor and the second transistor do not overlap with the conductive film, A power supply potential is applied to the conductive film, The power supply potential is applied to a common electrode of the light emitting element. Display device.

4. A display device having a function of changing a frequency of writing an image signal to a pixel portion, the display device includes the pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, and a second transistor in a pixel; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, the source or drain of the second transistor is always electrically connected to the gate of the first transistor; a potential corresponding to an image signal is supplied to a gate of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the gate line driver circuit has a function of supplying a signal to a gate of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; the first transistor and the second transistor do not overlap with the conductive film, A power supply potential is applied to the conductive film. The power supply potential is applied to a common electrode of the light emitting element. Display device.

5. A pixel portion, a gate line driving circuit, and a conductive film are included. the pixel portion includes a light-emitting element, a first transistor, a second transistor, and a capacitor in a pixel; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, the source or drain of the second transistor is always electrically connected to the gate of the first transistor; a potential corresponding to an image signal is supplied to a gate of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the capacitance element has a function of holding a potential of a gate of the first transistor, the gate line driver circuit has a function of supplying a signal to a gate of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; the first transistor and the second transistor do not overlap with the conductive film, A power supply potential is applied to the conductive film. Display device.

6. A display device having a function of changing a frequency of writing an image signal to a pixel portion, the display device includes the pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, a second transistor, and a capacitor in a pixel; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, the source or drain of the second transistor is always electrically connected to the gate of the first transistor; a potential corresponding to an image signal is supplied to a gate of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the capacitance element has a function of holding a potential of a gate of the first transistor, the gate line driver circuit has a function of supplying a signal to a gate of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; the first transistor and the second transistor do not overlap with the conductive film, A power supply potential is applied to the conductive film. Display device.

7. A pixel portion, a gate line driving circuit, and a conductive film are included. the pixel portion includes a light-emitting element, a first transistor, a second transistor, and a capacitor in a pixel; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, the source or drain of the second transistor is always electrically connected to the gate of the first transistor; a potential corresponding to an image signal is supplied to a gate of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the capacitance element has a function of holding a potential of a gate of the first transistor, the gate line driver circuit has a function of supplying a signal to a gate of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; the first transistor and the second transistor do not overlap with the conductive film, A power supply potential is applied to the conductive film, The power supply potential is applied to a common electrode of the light emitting element. Display device.

8. A display device having a function of changing a frequency of writing an image signal to a pixel portion, the display device includes the pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, a second transistor, and a capacitor in a pixel; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, the source or drain of the second transistor is always electrically connected to the gate of the first transistor; a potential corresponding to an image signal is supplied to a gate of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the capacitance element has a function of holding a potential of a gate of the first transistor, the gate line driver circuit has a function of supplying a signal to a gate of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; the first transistor and the second transistor do not overlap with the conductive film, A power supply potential is applied to the conductive film. The power supply potential is applied to a common electrode of the light emitting element. Display device.

9. In any one of claims 5 to 8, one electrode of the capacitance element is always electrically connected to the gate of the first transistor; Display device.

10. In any one of claims 1 to 9, the oxide semiconductor layer is an In-Ga-Zn-O-based, In-Sn-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, In-Sn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based, or In-Al-Zn-O-based oxide semiconductor; Display device.

Images