Display device and method of manufacturing the same

Abstract

To provide a display device capable of preventing or reducing lateral moisture penetration due to the presence of a light-emitting stack.SOLUTION: An embodiment disclosed herein relates to a display device, more specifically a display device comprising: a substrate having a non-display area with a through-hole and a display area adjacent to the non-display area; an insulating layer disposed on the substrate; a light-emitting stack disposed on the insulating layer; a second electrode disposed on the light-emitting stack, the second electrode extending from the display area to the non-display area; and an electrode patterning material layer arranged to be in contact with one end of the second electrode and disposed on the light-emitting stack. One end of the light-emitting stack and one end of the electrode patterning material layer coincide.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device and a method of manufacturing the same.

Background Art

[0002] With the development of technology, the uses of display devices have become diversified. In addition, since the thickness of display devices has become thinner and the weight has become lighter, the range of their use has expanded.

[0003] While the area occupied by the display area for displaying an image in a display device is expanding, various functions that are coordinated with or incorporated into the display device are being added.

[0004] A so-called bezel-less or bezel-free design, in which the display area appears to be filled, is gradually becoming common, and research is required on a display device having an area for adding various functions instead of image display inside the display area.

[0005] Accordingly, a display device called a Hole-in Display (HID) or a Hole-in Active Area (HiAA), in which at least a part of a substrate is removed from the display area of a display panel, has been proposed.

[0006] However, there are problems such as cracks occurring in the process of removing a part of the substrate and moisture or the like infiltrating into the area where the substrate has been removed, resulting in deterioration of display quality, and solutions to these problems are being sought.

Summary of the Invention

Problems to be Solved by the Invention

[0007] There was a problem that moisture or the like penetrated into the area where the substrate in the display area was removed, resulting in deterioration of display quality. Therefore, the inventors of the present specification invented a display device that prevents or reduces side moisture permeation by a light-emitting stack.

[0008] Embodiments of the present disclosure can provide a display device capable of patterning a light-emitting stack and blocking a side moisture permeation path by the light-emitting stack, and a method of manufacturing the same.

[0009] Embodiments of the present disclosure can provide a display device capable of patterning a light-emitting stack, disposing a dam structure to prevent or reduce a side moisture permeation path and microcracks by the light-emitting stack, and a method of manufacturing the same.

[0010] Embodiments of the present disclosure can provide a display device capable of low power by preventing or reducing side moisture permeation and improving lifespan, and a method of manufacturing the same.

Means for Solving the Problem

[0011] Embodiments of the present disclosure include a substrate including a non-display area including a through hole and a display area surrounding the non-display area, an insulating layer disposed on the substrate, a light-emitting stack disposed on the insulating layer, a second electrode extending from the display area to the non-display area and disposed on the light-emitting stack, and an electrode patterning material layer disposed on the light-emitting stack in contact with one end of the second electrode, and can provide a display device in which one end of the light-emitting stack and one end of the electrode patterning material layer are disposed to coincide with each other.

[0012] Embodiments of the present disclosure include a substrate including a non-display area including a through hole and a display area surrounding the non-display area, an insulating layer disposed on the substrate, a plurality of dams positioned between the display area and the through hole and disposed on the insulating layer, a light-emitting stack disposed on the insulating layer and the plurality of dams, a second electrode extending from the display area to the non-display area and disposed on the light-emitting stack, an electrode patterning material layer disposed on the light-emitting stack in contact with one end of the second electrode, and can provide a display device including grooves in which the light-emitting stack and the electrode patterning material layer are each cut off.

[0013] Embodiments of the present disclosure can provide a method for manufacturing a display device including steps of forming a substrate including a display area and a non-display area, forming a sacrificial layer and a dam in the non-display area, forming a light-emitting stack to cover the sacrificial layer and the dam, forming an electrode patterning material layer on the light-emitting stack located in the non-display area, forming a second electrode on the light-emitting stack in contact with the electrode patterning material layer, forming a capping layer on the second electrode and the electrode patterning material layer, and irradiating the sacrificial layer with laser light to form a groove.

Advantages of the Invention

[0014] According to embodiments of the present disclosure, it is possible to provide a display device capable of patterning a light-emitting stack and blocking a side moisture permeation path formed by the light-emitting stack, and a method for manufacturing the same.

[0015] According to embodiments of the present disclosure, it is possible to provide a display device capable of patterning a light-emitting stack and arranging a dam structure to prevent or reduce a side moisture permeation path and microcracks formed by the light-emitting stack, and a method for manufacturing the same.

[0016] According to embodiments of the present disclosure, it is possible to provide a display device capable of achieving low power consumption by preventing or reducing side moisture permeation and improving the lifespan, and a method for manufacturing the same.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12a

Figure 12b

Embodiments for Carrying Out the Invention

[0018] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, the same components can be assigned the same numerals as much as possible even if they are shown on different drawings. In addition, when it is determined that a specific description of a related known configuration or function obscures the gist of the present disclosure in explaining the present disclosure, the detailed description thereof can be omitted. When terms such as "including", "having", and "performed" mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it may include the case where a plurality are included unless otherwise explicitly stated.

[0019] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), B, etc. can be used. These terms are for distinguishing the components from other components, and the essence, order, procedure, number, etc. of the components are not limited by these terms.

[0020] In the description of the positional relationship of components, when it is described that two or more components are "connected", "coupled" or "connected", etc., it should be understood that two or more components can be directly "connected", "coupled" or "connected", but it is also possible that another component is further "interposed" between two or more components and they are "connected", "coupled" or "connected". Here, another component may be included in one or more of the two or more components that are "connected", "coupled" or "connected" to each other.

[0021] In the description of the temporal flow relationship regarding components, operating methods, manufacturing methods, etc., for example, when the temporal front-back relationship or flow front-back relationship is described by "after ~", "subsequent to ~", "after ~", "before ~", etc., it can include cases where it is not continuous unless "immediately" or "directly" is used.

[0022] On the other hand, when referring to a numerical value of a component or its corresponding information (for example, level, etc.), even without separate explicit description, the numerical value or its corresponding information can be interpreted as including an error range that can be caused by various factors (for example, process factors, internal or external impacts, noise, etc.).

[0023] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] FIG. 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure. All components of the display device according to the embodiment of the present disclosure are operatively coupled and configured.

[0025] Referring to FIG. 1, the display device 100 is a component for video display and may include a display panel 110 and a display driving circuit.

[0026] The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 120, a gate driving circuit 130, a display controller 140, and the like.

[0027] The display panel 110 may include a display area AA where an image is displayed and a non-display area NA where an image is not displayed. The non-display area NA may be an outer area of the display area AA and is also called a bezel area. All or part of the non-display area NA may be an area visible from the front of the display device 100, or may be bent and not visible from the front of the display device 100.

[0028] The display panel 110 may include a substrate SUB and a number of sub-pixels SP arranged on the substrate SUB. Also, the display panel 110 may further include several types of signal lines for driving the number of sub-pixels SP.

[0029] The display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the number of sub-pixels SP may include a light-emitting element. However, the embodiments of the present disclosure are not limited thereto.

[0030] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting element is composed of an organic light-emitting diode (OLED: Organic Light Emitting Diode). As another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting element is composed of an inorganic-based light-emitting diode. As yet another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting element is a quantum dot which is a semiconductor crystal that emits light by itself.

[0031] Depending on the type of the display device 100, the structures of the numerous sub-pixels SP may be different from each other. For example, when the display device 100 is a self-emitting display device in which the sub-pixel SP emits light by itself, each sub-pixel SP may include a light-emitting element that emits light by itself, one or more transistors, and one or more capacitors. However, the embodiments of the present disclosure are not limited thereto.

[0032] For example, some types of signal lines may include a number of data lines DL that transmit data signals (which may also be data voltages or video signals) and a number of gate lines GL that transmit gate signals (which may also be scan signals).

[0033] The number of data lines DL and the number of gate lines GL may intersect with each other. Each of the number of data lines DL may be arranged to extend in a first direction. Each of the number of gate lines GL may be arranged to extend in a second direction.

[0034] Here, the first direction may be the column direction, and the second direction may be the row direction. The first direction may be the row direction, and the second direction may be the column direction.

[0035] The data driving circuit 120 is a circuit configured to drive a large number of data lines DL, and can output a data signal to the large number of data lines DL. The gate driving circuit 130 is a circuit configured to drive a large number of gate lines GL, and can output a gate signal to the large number of gate lines GL.

[0036] The display controller 140 may be a device configured to control the data driving circuit 120 and the gate driving circuit 130. The display controller 140 can control the driving timing for the large number of data lines DL and the driving timing for the large number of gate lines GL.

[0037] The display controller 140 can supply a data driving control signal DCS to the data driving circuit 120 in order to control the data driving circuit 120. The display controller 140 can supply a gate driving circuit control signal GCS to the gate driving circuit 130 in order to control the gate driving circuit 130.

[0038] The display controller 140 can receive input video data from the host system 150 and supply video data Data to the data driving circuit 120 based on the input video data.

[0039] The data driving circuit 120 can supply a data signal to the large number of data lines DL under the driving timing control of the display controller 140.

[0040] The data driving circuit 120 can receive digital-form video data Data from the display controller 140, convert the received video data Data into an analog-form data signal, and output it to the large number of data lines DL.

[0041] The gate driving circuit 130 can supply gate signals to a number of gate lines GL under the timing control of the display controller 140. The gate driving circuit 130 is supplied with a first gate voltage corresponding to the turn-on level voltage and a second gate voltage corresponding to the turn-off level voltage together with various gate driving circuit control signals GCS, generates a gate signal, and can supply the generated gate signal to a number of gate lines GL.

[0042] For example, the data driving circuit 120 can be connected to the display panel 110 by a tape automated bonding (TAB) method, or connected to the bonding pads of the display panel 110 by a chip on glass (COG) or chip on panel (COP) method, or configured by a chip on film (COF) method and connected to the display panel 110. However, the embodiments of the present disclosure are not limited thereto.

[0043] The gate driving circuit 130 can be connected to the display panel 110 by a tape automated bonding (TAB) method, or connected to the bonding pads of the display panel 110 by a chip on glass (COG) or chip on panel (COP) method, or connected to the display panel 110 by a chip on film (COF) method. Alternatively, the gate driving circuit 130 can be formed in the non-display area NA of the display panel 110 in a gate in panel (GIP) type. The gate driving circuit 130 can be disposed on the substrate SUB or connected to the substrate SUB. For example, when the gate driving circuit 130 is of the gate in panel (GIP) type, it can be disposed in the non-display area NA of the substrate SUB. When the gate driving circuit 130 is of the chip on glass (COG) type, chip on film (COF) type, etc., it can be connected to the substrate.

[0044] On the one hand, at least one of the driving circuits of the data driving circuit 120 and the gate driving circuit 130 can also be arranged in the display area AA of the display panel 110. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be arranged so as not to overlap with the sub-pixel SP, or may be arranged so as to partially or entirely overlap with the sub-pixel SP. However, the embodiments of the present disclosure are not limited thereto.

[0045] The data driving circuit 120 can also be connected to one side (for example, the upper side or the lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (for example, the upper side and the lower side) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0046] The gate driving circuit 130 can also be connected to one side (for example, the left side or the right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 130 may be connected to both sides (for example, the left side and the right side) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0047] The display controller 140 may be composed of components separate from the data driving circuit 120, or may be integrated with the data driving circuit 120 and composed of an integrated circuit.

[0048] The display controller 140 may be a timing controller used in ordinary display technology, or a control device that includes a timing controller and can further perform other control functions, or a control device different from the timing controller, or a circuit within the control device. The display controller 140 may be composed of various circuits and electronic components such as an IC (Integrated Circuit), an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a processor (Processor).

[0049] The display controller 140 can be electrically connected to the data driving circuit 120 and the gate driving circuit 130 via a printed circuit board (PCB: Printed Circuit Board), a flexible printed circuit board (FPCB: Flexible Printed Circuit Board), etc. However, the embodiments of the present disclosure are not limited thereto.

[0050] The display controller 140 can transmit and receive signals with the data driving circuit 120 according to one or more predetermined interfaces. Here, for example, the interface can include a LVDS (Low Voltage Differential Signaling) interface, an EPI interface, an SPI (Serial Peripheral Interface), etc.

[0051] Referring to FIG. 1, the display device 100 according to the embodiment of the present disclosure can include one or more optical areas (OA: Optical Area) in which at least a part of the substrate SUB is removed.

[0052] One or more components (not shown) for providing various functions may be arranged in a region that at least partially overlaps with the optical region OA. The one or more components may be, for example, an optoelectronic device, a clock hand, etc. However, the embodiments of the present disclosure are not limited thereto.

[0053] The optoelectronic device may include one or more of, for example, a photographing device such as a camera (image sensor), a sensing sensor such as a proximity sensor and an illuminance sensor, etc. However, the embodiments of the present disclosure are not limited thereto.

[0054] For example, a photographing device such as a camera may be located under the first optical region OA1, and a sensing sensor may be located under the second optical region OA2. However, the embodiments of the present disclosure are not limited thereto.

[0055] The component may be located under the substrate SUB, or the component may be located such that at least a part thereof overlaps with the optical region OA.

[0056] The shapes of the first optical region OA1 and the second optical region OA2 can have various shapes such as circular, elliptical, square, hexagonal, or octagonal. The shapes of the first optical region OA1 and the second optical region OA2 may be the same or different. The area of the first optical region OA1 may be the same as or different from the area of the second optical region OA2.

[0057] Hereinafter, for convenience of explanation, it will be described assuming that the shapes of the first optical region OA1 and the second optical region OA2 are circular and their areas are the same, but the present invention is not limited thereto.

[0058] On the other hand, one or more optical regions OA are located in a region where the substrate SUB is removed, and such an optical region OA may be a non-display region NA where sub-pixels SP are not arranged.

[0059] The optical region OA located within the display area AA is also referred to as the "HID (Hole in Display)" or "HiAA (Hole in Active Area)" region.

[0060] Signal lines (e.g., data lines DL, gate lines GL, etc.) arranged on the substrate SUB can be arranged around (or detoured around) the periphery of the optical region OA.

[0061] The display device 100 according to an embodiment of the present disclosure can include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen, or to detect the touch position, in order to provide not only a video display function but also a touch sensing function.

[0062] The touch sensing circuit can include a touch driving circuit 160 that drives and senses the touch sensor to generate and output touch sensing data, and a touch controller 170 that can sense the occurrence of a touch or detect the touch position using the touch sensing data.

[0063] The touch sensor can include a number of touch electrodes. The touch sensor can further include a number of touch lines for electrically connecting the number of touch electrodes and the touch driving circuit 160.

[0064] The touch sensor may exist in the form of a touch panel outside the display panel 110, or may exist inside the display panel 110.

[0065] When the touch sensor exists outside the display panel 110 in the form of a panel, the touch sensor is called an external type. When the touch sensor is of the external type, the touch panel and the display panel 110 are manufactured separately and can be combined during the assembly process. The external touch panel can include a touch panel substrate and a number of touch electrodes on the touch panel substrate.

[0066] When the touch sensor is inside the display panel 110, during the manufacturing process of the display panel 110, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving and the like.

[0067] The touch driving circuit 160 can supply a touch driving signal to at least one of a number of touch electrodes and sense at least one of the number of touch electrodes to generate touch sensing data.

[0068] The touch sensing circuit can perform touch sensing in a self-capacitance sensing method or a mutual-capacitance sensing method.

[0069] When the touch sensing circuit performs touch sensing in the self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on capacitance between each touch electrode and a touch object (for example, a finger, a pen, etc.).

[0070] According to the self-capacitance sensing method, each of a number of touch electrodes can also serve as a driving touch electrode and can also serve as a sensing touch electrode. The touch driving circuit 160 can drive all or part of the number of touch electrodes and sense all or part of the number of touch electrodes.

[0071] When the touch sensing circuit performs touch sensing in the mutual-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between touch electrodes.

[0072] According to the mutual-capacitance sensing method, a number of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 160 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0073] The touch driving circuit 160 and the touch controller 170 included in the touch sensing circuit may be configured by separate devices or may be configured by one device. Further, the touch driving circuit 160 and the data driving circuit 120 may be configured by separate devices or may be configured by one device.

[0074] The display device 100 may further include a power supply circuit that supplies various power supplies to the display driving circuit and / or the touch sensing circuit.

[0075] The display device 100 according to the embodiment of the present disclosure may be a mobile terminal such as a smartphone or a tablet, or may be a monitor or a television (TV) of various sizes, and is not limited thereto, and may be various types and sizes of display devices that can display information or images.

[0076] FIG. 2 is an equivalent circuit of the sub-pixel SP in the display panel 110 according to the embodiment of the present disclosure. Among the following descriptions, the same or similar contents as those described with reference to FIG. 1 will be omitted or briefly described.

[0077] Referring to FIG. 2, each of the sub-pixels SP arranged in the display area AA of the display panel 110 may include a light emitting element ED, a driving transistor DRT for driving the light emitting element ED, a scan transistor SCT for transmitting a data voltage Vdata to the first node N1 of the driving transistor DRT, a storage capacitor Cst for maintaining a constant voltage during one frame, and the like.

[0078] The driving transistor DRT can include a first node N1 to which a data voltage Vdata is applied, a second node N2 electrically connected to the light-emitting element ED, and a third node N3 to which a high-potential common voltage ELVDD is applied from a driving voltage line DVL. In the driving transistor DRT, the first node N1 is a gate node, the second node N2 is either a source node or a drain node, and the third node N3 may be the other of the source node or the drain node.

[0079] The light-emitting element ED can include an anode electrode AE as a first electrode, a light-emitting layer EL, and a cathode electrode CE as a second electrode. The anode electrode AE may be a pixel electrode disposed in each sub-pixel SP and can be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP. The cathode electrode CE may be a common electrode commonly disposed in a number of sub-pixels SP, and a low-potential common voltage ELVSS may be applied.

[0080] For example, the anode electrode AE may be a pixel electrode, and the cathode electrode CE may be a common electrode. Conversely, the anode electrode AE may be a common electrode, and the cathode electrode CE may be a pixel electrode. Hereinafter, for convenience of explanation, it is assumed that the anode electrode AE is a pixel electrode and the cathode electrode CE is a common electrode. However, the embodiments of the present disclosure are not limited thereto.

[0081] For example, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element. In this case, when the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL in the light-emitting element ED can include an organic light-emitting layer containing an organic substance.

[0082] The scan transistor SCT is controlled to turn on and off by a scan signal SCAN which is a gate signal applied through a gate line GL. The scan transistor SCT can switch the electrical connection between the first node N1 of the drive transistor DRT and the data line DL.

[0083] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the drive transistor DRT.

[0084] As shown in FIG. 2, each subpixel SP can have a 2T (Transistor) 1C (Capacitor) structure including two transistors DRT, SCT and one capacitor Cst, and in some cases, can further include one or more transistors or one or more capacitors.

[0085] The storage capacitor Cst is not a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor (Internal Capacitor) that may exist between the first node N1 and the second node N2 of the drive transistor DRT, but may be an external capacitor (External Capacitor) intentionally designed outside the drive transistor DRT.

[0086] Each of the drive transistor DRT and the scan transistor SCT may be an n-type transistor or a p-type transistor.

[0087] Since the circuit elements (especially the light-emitting element ED) in each subpixel SP are vulnerable to external moisture, oxygen, etc., a sealing layer ENCAP may be disposed on the display panel 110 to prevent external moisture and oxygen from penetrating into the circuit elements (especially the light-emitting element ED). The sealing layer ENCAP may be disposed in a form covering the light-emitting element ED.

[0088] FIG. 3 is a plan view showing the structure of the optical region OA of the display panel 110 according to an embodiment of the present disclosure. Among the following descriptions, the same or similar contents described with reference to FIGS. 1 and 2 will be omitted or briefly described.

[0089] Referring to FIG. 3, the optical region OA is disposed within the display region AA. Pixels SP may be disposed around the optical region OA. The optical region OA may be either the aforementioned first optical region OA1 or the second optical region OA2. However, embodiments of the present disclosure are not limited thereto.

[0090] Referring to FIG. 3, the optical region OA can include a through hole TH and a bezel region surrounding the periphery of the through hole TH. Such a bezel region located between the through hole TH and the display region AA is also referred to as a "HiAA bezel region HBA".

[0091] The HiAA bezel region HBA is a region surrounding the outer contour of the through hole TH. The HiAA bezel region HBA can prevent damage to the wiring during laser irradiation for forming the through hole TH. The HiAA bezel region HBA has a minimum width and can keep this constant.

[0092] A dam region 200 in which a dam structure for preventing moisture permeation and microcracks flowing in from the outside through a trimming line is disposed may be located in the HiAA bezel region HBA. At least one dam may be disposed in the dam region 200. Sub-pixels for displaying an image may not be located in such an optical region OA. That is, the optical region OA including the HiAA bezel region HBA may be a non-display region NA where an image is not displayed.

[0093] The through-hole TH can be formed by removing the substrate along the trimming line. As shown in FIG. 3, the shape of the through-hole TH may be circular, but it can have various shapes such as elliptical, square, hexagonal, or octagonal. However, the embodiments of the present disclosure are not limited thereto.

[0094] The dam region 200 can include at least one dam. For example, in the dam region 200, the first dam 230, the second dam 220, and the third dam 210 may be arranged in this order adjacent to the display region AA between the display region AA and the through-hole TH.

[0095] The shapes of the dams 210, 220, and 230 have a closed curve shape surrounding the through-hole TH while corresponding to the shape of the through-hole TH. The dams 210, 220, and 230 and the through-hole TH can have different closed curve shapes from each other, or they can have the same shape but different sizes of closed curve shapes. As an example, the dams 210, 220, and 230 and the through-hole TH can have a concentric shape, can overlap continuously, and can be arranged at a certain interval. However, the embodiments of the present disclosure are not limited thereto.

[0096] On the other hand, the sub-pixel SP arranged in the display region AA can include a light-emitting element. In the display region AA, a light-emitting stack (not shown) including a light-emitting layer may be located. When the light-emitting element is an organic light-emitting element, such a light-emitting stack may be an organic light-emitting stack including an organic substance. However, the embodiments of the present disclosure are not limited thereto.

[0097] The organic light-emitting stack can be arranged up to at least a partial region of the optical region OA.

[0098] On the other hand, when moisture penetrates into the organic light-emitting stack, there may be a reduction in defects such as the sub-pixel becoming a dark spot. From various viewpoints, there is a possibility that moisture may penetrate in the region where the through-hole TH is located.

[0099] An inorganic encapsulation layer may be located on the dam region 200. Although moisture can penetrate through the inorganic encapsulation layer, the dam region 200 has the effect of lengthening the path through which moisture penetrates in the inorganic encapsulation layer. According to this, the dam region 200 can prevent the moisture flowing in from through-holes TH or the like from reaching the light-emitting layer located in the display region AA.

[0100] FIG. 4 is an illustration of a cross-sectional view taken along the line I-I' of FIG. 3. For example, FIG. 4 is an illustrative diagram showing the cross-sectional structure of the sub-pixel SP of FIG. 3. Among the following descriptions, the same or similar contents described with reference to FIGS. 1 to 3 will be omitted or briefly described.

[0101] Referring to FIG. 4, the display device 100 according to an embodiment of the present disclosure may include a substrate 301. The substrate 301 may be a glass substrate or a plastic substrate. As the plastic substrate, for example, it may be made of polyimide (PI), polymethyl methacrylate (PMMA), polyethylene (PE), etc., and may have flexible characteristics. However, the embodiments of the present disclosure are not limited thereto.

[0102] A plurality of insulating layers may be provided on the substrate 301. A buffer layer 302 may be provided on the substrate 301. The buffer layer 302 may include a multi-buffer layer 302a and a lower buffer layer 302b. The first transistor 320 may be disposed on the lower buffer layer 302b. The first semiconductor layer 323 constituting the first transistor 320, the first gate electrode 322, and a lower gate insulating film 304 for insulation may be disposed on the first semiconductor layer 323. The lower interlayer insulating film 305 may be disposed on the first gate electrode 322. The lower interlayer insulating film 305 may include a first lower interlayer insulating film 305a and a second lower interlayer insulating film 305b disposed in sequence. The upper buffer layer 307 may be disposed on the lower interlayer insulating film 305. However, the embodiments of the present disclosure are not limited thereto.

[0103] The multi-buffer layer 302a can delay the diffusion of moisture or oxygen that has penetrated the substrate 301, and may be formed by alternately laminating silicon nitride (SiNx) and silicon oxide (SiOx) at least once. However, the embodiments of the present disclosure are not limited thereto.

[0104] The lower buffer layer 302b protects the first semiconductor layer 323 and can function to block various types of defects flowing in from the substrate. This lower buffer layer 302b can be formed of amorphous silicon (a-Si), silicon nitride (SiNx), silicon oxide (SiOx), or the like. However, the embodiments of the present disclosure are not limited thereto.

[0105] The first semiconductor layer 323 of the first thin film transistor 320 may be formed of a polycrystalline semiconductor layer. However, the embodiments of the present disclosure are not limited thereto. The first semiconductor layer 323 can include a channel region, a source region, and a drain region.

[0106] The polycrystalline semiconductor layer has a higher mobility, lower energy consumption power, and better reliability than the amorphous semiconductor layer and the oxide semiconductor layer. Due to such advantages, a polycrystalline semiconductor layer can be used for the driving transistor. However, the embodiments of the present disclosure are not limited thereto.

[0107] The first gate electrode 322 can be disposed on the lower gate insulating film 304 and can be disposed so as to overlap the first semiconductor layer 323.

[0108] The second transistor 330 may be disposed on the upper buffer layer 307, and the light shielding layer 336 may be disposed below the region corresponding to the second transistor 330.

[0109] Referring to FIG. 4, a light-shielding layer 336 may be disposed on the first lower interlayer insulating film 305a in the region corresponding to the second transistor 330, and may be disposed on the second lower interlayer insulating film 305a and the upper buffer layer 307 such that the second semiconductor layer 333 of the second transistor 330 overlaps with the light-shielding layer 336. An upper gate insulating film 337 for insulating the second gate electrode 332 and the second semiconductor layer 333 may be disposed on the upper portion of the second semiconductor layer 333, and subsequently, an upper interlayer insulating film 308 may be disposed on the second gate electrode 332. The first gate electrode 322 and the second gate electrode 332 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but are not limited thereto.

[0110] The first and second lower interlayer insulating films 305a and 305b can be formed of an inorganic film having a higher hydrogen particle content than the upper interlayer insulating film 308. For example, the first and second lower interlayer insulating films 305a and 305b may be made of silicon nitride (SiNx) formed by a vapor deposition process using NH3 gas, and the upper interlayer insulating film 308 can be formed of silicon oxide (SiOx). However, embodiments of the present disclosure are not limited thereto. The hydrogen particles contained in the first and second lower interlayer insulating films 305a and 305b can diffuse into the polycrystalline semiconductor layer during the hydrogenation process, and the voids in the polycrystalline semiconductor layer can be filled with hydrogen. Thereby, the polycrystalline semiconductor layer can be stabilized, and deterioration of the characteristics of the first transistor 320 can be prevented.

[0111] After the activation and hydrogenation processes of the first semiconductor layer 323 of the first transistor 320, the second semiconductor layer 333 of the second transistor 330 can be formed. At this time, the second semiconductor layer 333 can be formed of an oxide semiconductor. Since the second semiconductor layer 333 is not exposed to the high-temperature atmosphere of the activation and hydrogenation processes of the first semiconductor layer 323, damage to the second semiconductor layer 333 can be prevented, and the reliability can be improved.

[0112] After the upper interlayer insulating film 308 is disposed, a first source contact hole 325S and a first drain contact hole 325D may be formed so as to correspond to the source and drain regions of the first transistor, and a second source contact hole 335S and a second drain contact hole 335D may be respectively formed so as to correspond to the source and drain regions of the second transistor 330.

[0113] Referring to FIG. 4, holes can be continuously formed from the upper interlayer insulating film 308 to the lower gate insulating film 304 for the first source contact hole 325S and the first drain contact hole 325D, and the second source contact hole 335S and the second drain contact hole 335D can also be formed for the second transistor 330. A first source electrode 321, a first drain electrode 324 corresponding to the first transistor 320, a second source electrode 331, and a second drain electrode 334 corresponding to the second transistor 330 can be formed simultaneously, thereby reducing the number of process steps for forming the source and drain electrodes of the first transistor 320 and the second transistor 330 respectively.

[0114] The first source and drain electrodes 321, 324 and the second source and drain electrodes 331, 334 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but the embodiments of the present disclosure are not limited thereto.

[0115] The first source and drain electrodes 321, 324 and the second source and drain electrodes 331, 334 may have a three-layer structure. The first source electrode 321 may be sequentially composed of a first electrode layer 321a, a second electrode layer 321b, and a third electrode layer 321c.

[0116] The first electrode layer 321a, the second electrode layer 321b, and the third electrode layer 321c can contain substances with relatively different etching rates. The second electrode layer 321b contains a substance with a relatively fast etching rate, and the first electrode layer 321a and the third electrode layer 321c can contain substances with relatively slow etching rates. For example, the second electrode layer 321b can contain aluminum (Al) with a relatively fast etching rate, and the first electrode layer 321a and the third electrode layer 321c can contain titanium (Ti) with a relatively slow etching rate. The first source electrode 321 can have a triple-layer structure of Ti / Al / Ti. However, the embodiments of the present disclosure are not limited thereto.

[0117] Other source and drain electrodes can also have the same structure as the first source electrode 321.

[0118] A storage capacitor 340 may be disposed between the first transistor 320 and the second transistor 330. As shown in FIG. 4, the storage capacitor 340 can be formed by overlapping a storage lower electrode 341 and a storage upper electrode 342 with the first interlayer insulating film 305a therebetween.

[0119] The storage lower electrode 341 is located on the lower gate insulating film 304 and can be formed of the same material in the same layer as the first gate electrode 322. The storage upper electrode 342 can be electrically connected to the pixel circuit via the storage supply line 343. The storage upper electrode 342 can be formed of the same material in the same layer as the light shielding layer 336. Such a storage upper electrode 342 is exposed through a storage contact hole 344 that penetrates the second lower interlayer insulating film 305b, the upper buffer layer 307, the upper gate insulating layer 337, and the upper interlayer insulating film 308 and is connected to the storage supply line 343. On the other hand, as shown in FIG. 4, the storage upper electrode 342 is separated from the light shielding layer 336, but can also be formed in an integrated type connected to each other. The storage supply line 343 can be formed of the same material on the same plane as the first source and drain electrodes 321, 324 or the second source and drain electrodes 331, 334. Thereby, the storage supply line 343 can be formed simultaneously with the first source and drain electrodes 321, 324 or the second source and drain electrodes 331, 334 in the same mask process.

[0120] An inorganic insulating substance such as SiNx or SiOx can be deposited over the entire surface of the substrate 301 on which the first source and drain electrodes 321, 324, the second source and drain electrodes 331, 334, and the storage supply line 343 are formed, thereby forming the protective film 309. The first planarization layer 310 can be formed on the substrate 301 on which the protective film 309 is formed. Specifically, the first planarization layer 310 can be disposed by coating an organic insulating substance such as an acrylic resin over the entire surface of the substrate 301 on which the protective film 309 is formed.

[0121] The protective layer 309 and the first planarization layer 310 are disposed, and a contact hole that exposes the first source electrode 321 or the first drain electrode 324 of the first transistor 320 can be formed through a photolithography process. The connection electrode 345 can be disposed in the contact hole region that exposes the first drain electrode 324. However, the embodiments of the present disclosure are not limited thereto.

[0122] The connection electrode 345 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but the embodiments of the present disclosure are not limited thereto.

[0123] The connection electrode 345 may have a three-layer structure. The connection electrode 345 may be sequentially composed of a first connection electrode layer 345a, a second connection electrode layer 345b, and a third connection electrode layer 345c.

[0124] The first connection electrode layer 345a, the second connection electrode layer 345b, and the third connection electrode layer 345c can include substances with relatively different etching rates. The second connection electrode layer 345b can include a substance with a relatively fast etching rate, and the first connection electrode layer 345a and the third connection electrode layer 345c can include substances with relatively slow etching rates. For example, the second connection electrode layer 345b can include aluminum (Al) with a relatively fast etching rate, and the first connection electrode layer 345a and the third connection electrode layer 345c can include titanium (Ti) with a relatively slow etching rate. The connection electrode 345 can have a three-layer structure of Ti / Al / Ti. However, the embodiments of the present disclosure are not limited thereto.

[0125] A second planarization layer 311 may be disposed on the connection electrode 345, and a contact hole exposing the connection electrode 345 may be formed in the second planarization layer 311, and a light-emitting element 350 connected to the first transistor 320 may be disposed.

[0126] The light-emitting element 350 can include a first electrode 351 connected to the first drain electrode 324 of the first transistor 320, at least one light-emitting stack 352 formed on the first electrode 351, and a second electrode 353 formed on the light-emitting stack 352.

[0127] The light-emitting stack 352 can include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. However, the embodiments of the present disclosure are not limited thereto. In a tandem structure in which a plurality of light-emitting layers overlap, a charge generation layer may be further disposed between the light-emitting layers. In the case of the light-emitting layer, it may emit different colors for each sub-pixel. For example, a light-emitting layer for red, a light-emitting layer for green, and a light-emitting layer for blue may be separately formed for each sub-pixel. However, a common light-emitting layer may be formed to emit white light without color distinction for each pixel, and a color filter for distinguishing colors may be separately provided. Such a classification can be divided into an RGB type (Real RGB Type) and a WOLED (White OLED). The light-emitting layers can be formed individually, but the injection layer or the transport layer can be provided as a common layer and arranged in the same manner for each sub-pixel.

[0128] The first electrode 351 can be connected to the connection electrode 345 exposed through a contact hole penetrating the second planarization layer 311. The first electrode 351 can be formed in a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film is made of a material with a relatively large work function value such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film may be formed of a single-layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti, or an alloy thereof. However, the embodiments of the present disclosure are not limited thereto. For example, the first electrode 351 can be formed in a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially laminated, or in a structure in which a transparent conductive film and an opaque conductive film are sequentially laminated. Such a first electrode 351 is disposed on the second planarization layer 311 so as to overlap not only the light-emitting region provided by the bank 354 but also the pixel circuit region where the first and second transistors 320, 330 and the storage capacitor 340 are disposed, whereby the light-emitting area may increase. The first electrode 351 may be an anode electrode. However, the embodiments of the present disclosure are not limited thereto.

[0129] The light-emitting stack 352 can be formed by laminating a hole transport layer, an organic light-emitting layer, and an electron transport layer in this order or in the reverse order on the first electrode 351. Additionally, the light-emitting stack 352 can further include a charge generation layer, and can also include first and second light-emitting stacks facing each other with the charge generation layer interposed therebetween. However, the embodiments of the present disclosure are not limited thereto.

[0130] The bank 354 can be formed so as to expose the first electrode 351. Such a bank 354 can be formed of an organic material such as photoacrylic and may be a translucent material, but the embodiments of the present disclosure are not limited thereto, and it can also be formed of an opaque material to prevent light interference between sub-pixels. A spacer (not shown) may be formed on the bank 354. The spacer (not shown) can include an organic insulator. The spacer (not shown) can include the same material as the bank 354. The bank 354 and the spacer (not shown) can be formed together in a mask process using a halftone mask or the like. As another example, the spacer (not shown) can include a material different from the bank 354.

[0131] The second electrode 353 can be formed on the upper surface of the light-emitting stack 352 so as to face the first electrode 351 with the light-emitting stack 352 interposed therebetween. When applied to a front light-emitting type organic light-emitting display device, the second electrode 353 can be formed as a transparent conductive film by thinly forming indium tin oxide (ITO), indium zinc oxide (IZO), or magnesium-silver (Mg-Ag). However, the embodiments of the present disclosure are not limited thereto.

[0132] A capping layer 355 may be disposed on the second electrode 353.

[0133] The capping layer 355 can play a role in helping the light generated in the light-emitting stack 352 to be efficiently emitted outward while protecting the light-emitting element 350. For example, the capping layer 355 may be made of an inorganic substance or an organic substance in order to prevent the light exiting from the light-emitting stack 352 from being lost due to total internal reflection. The capping layer 355 may be made of an organic substance or an inorganic substance in order to prevent the inflow of moisture, oxygen, etc.

[0134] The capping layer 355 can include a single layer or a plurality of layers. For example, the capping layer 355 can be formed of a single layer of an organic capping layer containing an organic substance or an inorganic capping layer containing an inorganic substance, or can be formed of a plurality of layers by alternately depositing an organic capping layer and an inorganic capping layer on each other. When the capping layer 355 is formed of a plurality of layers, the organic capping layer and the inorganic capping layer may be sequentially formed on the second electrode 353. However, the embodiments of the present disclosure are not limited thereto.

[0135] The organic capping layer can include the substance of any one layer constituting the light-emitting stack 352. For example, it can be formed using a substance selected from the host substance of the light-emitting layer, the substance forming the hole transport layer or the electron transport layer, or can be formed using a separate organic substance.

[0136] The inorganic capping layer can be formed using substances such as LiF, LiO, MgF2, NaF, CaO, KF, Bi2S3, Na5Al3F14, SiO2, etc. in order to increase the light transmittance from the light-emitting stack 352. However, the embodiments of the present disclosure are not limited thereto.

[0137] A sealing layer 360 can be formed on the capping layer 355 to protect the light-emitting element 350. Due to the organic material characteristics of the light-emitting stack 352, the light-emitting element 350 may react with external moisture or oxygen, resulting in dark spots or pixel shrinkage. To prevent this, the sealing layer 360 can be disposed on the capping layer 355.

[0138] The sealing layer 360 can have a single-layer structure or a multi-layer structure. For example, as shown in FIG. 4, the sealing layer 360 can include a first sealing layer 361, a second sealing layer 362, and a third sealing layer 363. However, the embodiments of the present disclosure are not limited thereto.

[0139] The sealing layer 360 can include an inorganic film containing an inorganic insulating material. The sealing layer 360 can include an organic film containing an organic material. The sealing layer 360 can include an inorganic film and an organic film.

[0140] For example, the first sealing layer 361 and the third sealing layer 363 may be inorganic films, and the second sealing layer 362 may be an organic film. Among the first sealing layer 361, the second sealing layer 362, and the third sealing layer 363, the second sealing layer 362 may be the thickest. According to this, the second sealing layer 362 can serve as a planarization layer. The first sealing layer 361 may also be referred to as the first inorganic sealing layer, the second sealing layer 362 may also be referred to as the organic sealing layer, and the third sealing layer 363 may also be referred to as the second inorganic sealing layer. However, the embodiments of the present disclosure are not limited thereto.

[0141] The first encapsulation layer 361 is disposed on the capping layer 355 and can be disposed closest to the light-emitting element 350. The first encapsulation layer 361 can be formed of an inorganic insulating material capable of low-temperature deposition. For example, the first encapsulation layer 361 may be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. However, the embodiments of the present disclosure are not limited thereto. Since the first encapsulation layer 361 is deposited in a low-temperature atmosphere, during the deposition process, the first encapsulation layer 361 can prevent the light-emitting stack 352 including organic substances vulnerable to a high-temperature atmosphere from being damaged.

[0142] The second encapsulation layer 362 can be formed with an area smaller than that of the first encapsulation layer 361. In this case, the second encapsulation layer 362 can be formed to expose both ends of the first encapsulation layer 361. The second encapsulation layer 362 can serve as a buffer to relieve the stress between layers due to the warpage of the display device 100 and can also serve to enhance the planarization performance. Also, the second encapsulation layer 362 can be said to be a foreign matter compensation layer. For example, the second encapsulation layer 362 may be an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or silicon oxycarbide (SiOC), or the like, and can be formed of an organic insulating material. However, the embodiments of the present disclosure are not limited thereto. For example, the second encapsulation layer 362 can be formed by an inkjet method.

[0143] The third encapsulation layer 363 can be formed on the substrate 301 on which the second encapsulation layer 362 is formed so as to cover the upper surfaces and side surfaces of the second encapsulation layer 362 and the first encapsulation layer 361, respectively. The third encapsulation layer 363 can minimize or block the penetration of external moisture and oxygen into the first encapsulation layer 361 and the second encapsulation layer 362. For example, the third encapsulation layer 363 is formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). However, the embodiments of the present disclosure are not limited thereto.

[0144] The materials of the first sealing layer 361 and the third sealing layer 363 may be different from each other. The thicknesses of the first sealing layer 361 and the third sealing layer 363 may be different from each other. The thickness of the first sealing layer 361 may be greater than the thickness of the third sealing layer 363. Or, the thickness of the third sealing layer 363 may be greater than the thickness of the first sealing layer 361, or the thicknesses of the first sealing layer 361 and the third sealing layer 363 may be the same as each other.

[0145] FIG. 5 is an illustration of a cross-sectional view taken along line II-II' of FIG. 3. For example, FIG. 5 is an illustrative view showing the cross-sectional structure of the optical region OA of FIG. 3. Among the following descriptions, the same or similar contents described with reference to FIGS. 1 to 4 are omitted or briefly described.

[0146] Referring to FIGS. 3 and 5, in the display device 100 according to an embodiment of the present disclosure, the optical region OA includes a through hole TH and a HiAA bezel region HBA, and a display region AA may be located on the outer contour of the HiAA bezel region HBA. The HiAA bezel region HBA may be a non-display region NA.

[0147] Looking at the cross-section of the HiAA bezel region HBA, various insulating films existing in the display region AA and the HiAA bezel region HBA may be arranged. For example, a buffer layer 302, a lower interlayer insulating film 305, an upper buffer layer 307, an upper interlayer insulating film 308, etc. may be sequentially laminated on the upper part of the substrate 301. However, the embodiments of the present disclosure are not limited thereto.

[0148] Referring to FIGS. 3 and 5, a dam region 200 including a "dam structure" such as a dam may be located between the display region AA and the through hole TH.

[0149] The dam structure can have a multi-layer structure of two or more layers formed perpendicular to the substrate 301. For example, the dam structure can include a first layer formed of the planarization layer 310 and a second layer formed of the bank 354. Specifically, the dam structure can include a first layer formed of the second planarization layer 311 and a second layer formed of the bank 354. The dam structure can include a first layer formed of the second planarization layer 311, a second layer formed of the bank 354, and a third layer formed of a spacer (not shown). The dam structure can further include the first planarization layer 310 under the second planarization layer 311 or can have a stacked structure further including other layers. However, the embodiments of the present disclosure are not limited thereto.

[0150] The dam region 200 can include at least one dam. For example, in the dam region 200, between the display region AA and the through hole TH, the first dam 230, the second dam 220, and the third dam 210 can be arranged in order adjacent to the display region AA.

[0151] Referring to FIG. 5, in the HiAA bezel region HBA which is a non-display region, the light-emitting stack 352 can be arranged on the upper interlayer insulating layer 308 which is an insulating layer. The light-emitting stack 352 can also be arranged on the dams 210, 220, 230 arranged in the dam region 200. The light-emitting stack 352 may be an organic light-emitting stack. However, the embodiments of the present disclosure are not limited thereto.

[0152] Extending from the display region AA to the HiAA bezel region HBA which is a non-display region, the second electrode 353 may be arranged on the light-emitting stack 352. The second electrode 353 may be a cathode electrode. However, the embodiments of the present disclosure are not limited thereto.

[0153] An electrode patterning material layer 420 that can improve the light transmittance can be disposed in the HiAA bezel region HBA. The electrode patterning material layer 420 can be disposed on the light-emitting stack 352 and extend from one end of the second electrode 353 to the through hole TH. One end of the electrode patterning material layer 420 and one end of the light-emitting stack 352 can be arranged to coincide. However, the embodiments of the present disclosure are not limited thereto.

[0154] The electrode patterning material layer 420 can be formed using an electrode patterning material (EPM, Electrode Patterning Material) containing an organic substance. For example, the electrode patterning material layer 420 can be formed by depositing an electrode patterning material (EPM) so as to cover at least a part of the HiAA bezel region HBA using an FMM (Fine Metal Mask). As an example, an organic substance, Ir(ppy)3 (Tris(2-phenylpyridine)iridium(III)), may be used as the electrode patterning material. However, the embodiments of the present disclosure are not limited thereto.

[0155] The electrode patterning material (EPM) can be used to improve the light transmittance in the optical region OA and effectively pattern the second electrode 353 formed on the entire display area AA and a part of the non-display area NA.

[0156] After forming the electrode patterning material (EPM) in the optical region OA using the FMM, the second electrode 353 is deposited on the entire display area AA and a part of the non-display area NA using an OMM (Open Metal Mask), whereby the second electrode 353 can be effectively formed on the entire display area AA and a part of the non-display area NA excluding the electrode patterning material (EPM). Thereby, the electrode patterning material layer 420 and the second electrode 353 can be located on the same plane.

[0157] The thickness of the second electrode 353 may not be smaller than the thickness of the electrode patterning material layer 420. For example, the thickness of the second electrode 353 may be the same as the thickness of the electrode patterning material layer 420, or may be larger than the thickness of the electrode patterning material layer 420.

[0158] For example, when an electrode patterning material (EPM) is deposited on the light-emitting stack 352 in the optical region OA using an FMM to form the electrode patterning material layer 420 and then a metal material as the second electrode 353 is deposited over the entire surface, the metal material may not be deposited on the electrode patterning material layer 420, and the second electrode 353 may be selectively formed only on the entire surface of the display region AA excluding the electrode patterning material layer 420 and on a part of the light-emitting stack 352 in the non-display region NA. However, embodiments of the present disclosure are not limited thereto.

[0159] Since the electrode patterning material (EPM) has low surface energy of the material itself or low adhesion characteristics with high interfacial energy between the metal and the electrode patterning material layer 420, the desorption probability of the metal from the surface of the electrode patterning material layer 420 becomes significantly high during metal deposition, and metal nucleation does not occur. Therefore, by selectively depositing the metal only in a high adhesion region with relatively small interfacial energy, it is possible to form a self-aligned patterned metal.

[0160] Referring to FIG. 5, the light-emitting stack 352 and the electrode patterning material layer 420 can be sequentially stacked and arranged in the HiAA bezel region HBA. For example, the light-emitting stack 352 and the electrode patterning material layer 420 can be sequentially stacked and arranged on the dams 210, 220, 230 located in the dam region 200. The light-emitting stack 352 and the electrode patterning material layer 420 can be sequentially stacked and arranged between the display region AA and the first dam 230. The light-emitting stack 352 and the electrode patterning material layer 420 can be sequentially stacked and arranged between the dams 210, 220, 230 in the dam region 200. The light-emitting stack 352 and the electrode patterning material layer 420 can be sequentially stacked and arranged between the third dam 210 and the through hole TH.

[0161] At least one groove may be arranged between the display region AA and the through hole TH. The groove can be formed by cutting off the light-emitting stack 352 and the electrode patterning material layer 420 respectively.

[0162] A groove 434 may be located between the display region AA and the dam region 200. For example, the groove 434 may be located between the display region AA and the first dam 230.

[0163] Also, a groove may be located between the dams. For example, a groove 433 may be located between the first dam 230 and the second dam 220, and a groove 432 may be located between the second dam 220 and the third dam 210.

[0164] Also, a groove 431 may be located between the dam region 200 and the through hole TH. For example, the groove 431 may be located between the third dam 210 and the through hole TH.

[0165] In the grooves 431, 432, 433, 434, the light-emitting stack 352 and the electrode patterning material layer 420 can be respectively cut off to form.

[0166] Referring to FIG. 5, when the grooves 431, 432, 433, 434 are not formed, the light-emitting stack 352 may be arranged to extend to the through hole TH. Therefore, the light-emitting stack 352 may serve as a lateral moisture permeation path at the cross-sectional plane of the through hole TH, and film lifting may occur due to moisture permeation.

[0167] Referring to FIG. 5, in the grooves 431, 432, 433, 434, the light-emitting stack 352 can be cut off to block the moisture permeation path by the light-emitting stack 352, and lateral moisture permeation due to film lifting can be prevented or reduced.

[0168] In the grooves 431, 432, 433, 434, one end of the electrode patterning material layer 420 and one end of the light-emitting stack 352 can be arranged to coincide. However, the embodiments of the present disclosure are not limited thereto.

[0169] Referring to FIG. 5, a capping layer 355 can be arranged on the second electrode 353 and the electrode patterning material layer 420. The capping layer 355 can be arranged to be cut off in the grooves 431, 432, 433, 434.

[0170] That is, in the grooves 431, 432, 433, 434, the light-emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 can each be arranged to be cut off. Also, in the grooves 431, 432, 433, 434, one end of the light-emitting stack 352, one end of the electrode patterning material layer 420, and one end of the capping layer 355 can be arranged to coincide.

[0171] A sealing layer 360 can be arranged on the capping layer 355.

[0172] The sealing layer 360 can be in contact with the upper interlayer insulating film 308, which is an insulating layer, without being cut off in the grooves 431, 432, 433, 434.

[0173] The sealing layer 360 may be single-layer or multi-layer.

[0174] For example, the sealing layer 360 can include a first sealing layer, a second sealing layer, and a third sealing layer. The first sealing layer and the third sealing layer may be inorganic films, and the second sealing layer may be an organic film. That is, the first sealing layer may be the first inorganic sealing layer 361, the second sealing layer may be the organic sealing layer 362, and the third sealing layer may be the second inorganic sealing layer 363.

[0175] The first inorganic sealing layer 361 is not interrupted in the grooves 431, 432, 433, 434 and can be in contact with the upper interlayer insulating film 308 which is an insulating layer.

[0176] The organic sealing layer 362 can be disposed between the first inorganic sealing layer 361 and the second inorganic sealing layer 363. The organic sealing layer 362 can be disposed between the display area AA and the first dam 230.

[0177] The first inorganic sealing layer 361 and the second inorganic sealing layer 363 can be in contact with each other and extend to the via hole TH around the first dam 230.

[0178] The first inorganic sealing layer 361 and the second inorganic sealing layer 363 can be disposed so as to be exposed in the via hole TH.

[0179] Referring to FIG. 5, a lower shield metal 410 may be disposed between the substrate 301 and the buffer layer 302 which is an insulating layer.

[0180] One end of the lower shield metal 410 can overlap with the electrode patterning material layer 420, and the other end of the lower shield metal 410 can overlap with the second electrode 353. For example, one end of the lower shield metal 410 can be located between one end of the second electrode 353 and the groove 434.

[0181] FIG. 6 is an illustration of another cross-sectional view taken along line II-II' of FIG. 3. For example, FIG. 6 is another illustrative view showing the cross-sectional structure of the optical region OA of FIG. 3. Among the following descriptions, the same or similar content described with reference to FIGS. 1 to 5 will be omitted or briefly described.

[0182] Referring to FIG. 6, compared with the example of the cross-section shown in FIG. 5, there is only a difference in the arrangement portion of the first inorganic sealing layer 361 and the second inorganic sealing layer 363 in the through-hole TH region, so the description of other configurations will be omitted.

[0183] Referring to FIG. 6, the organic sealing layer 362 can be disposed between the first inorganic sealing layer 361 and the second inorganic sealing layer 363. The organic sealing layer 362 can be disposed between the display region AA and the first dam 230.

[0184] The first inorganic sealing layer 361 and the second inorganic sealing layer 363 can be disposed in contact with each other around the first dam 230 and extend into the through-hole TH. The second inorganic sealing layer 363 can cover one end of the first inorganic sealing layer 361 in the through-hole TH. That is, one end 363a of the second inorganic sealing layer 363 can cover one end of the first inorganic sealing layer 361 in the through-hole TH.

[0185] In various embodiments of the present disclosure, the number, size, arrangement, and shape of the grooves 431, 432, 433, 434 may be various. For example, referring to FIGS. 5 and 6, the number of grooves may be four as shown, but the embodiments of the present disclosure are not limited thereto. For example, the number of grooves may be more than four or less than four. In the embodiments shown in FIGS. 5 and 6, the number of the grooves 431, 432, 433, 434 can be provided in a number one more than the number of the dams 210, 220, 230, but in other embodiments, the number of the grooves may be the same as the number of the dams, more than the number of the dams, or less.

[0186] Also, the sizes of one or more grooves 431, 432, 433, 434 may vary. For example, referring to FIGS. 5 and 6, the sizes of the respective grooves 431, 432, 433, 434 can be illustrated as being smaller than the width of the interval between adjacent dams. For example, the groove 433 can be illustrated as being narrower than the interval between the first dam 230 and the second dam 220 or the groove. In this regard, the other grooves 434, 432, 431 can be illustrated as having the same or similar widths or sizes. However, the embodiments of the present disclosure are not limited thereto. For example, the width or size of one or more of the grooves 431, 432, 433, 434 may be the same as the interval between adjacent dams such as the first dam 230 and the second dam 220 or the groove. In this case, the groove 433 can extend from the planarization layer 310 of the first dam 230 to the planarization layer 310 of the second dam 220. One or more of the other grooves 434, 432, 431 can have the same or similar width or size as the groove 433.

[0187] Also, the arrangements of one or more grooves 431, 432, 433, 434 may vary. Referring to FIGS. 5 and 6, one groove is shown between adjacent dams. For example, there is one groove 433 between the adjacent first dam 230 and the second dam 220. However, the embodiments of the present disclosure are not limited thereto. For example, two or more grooves can be located between the first dam 230 and the second dam 220 and between other dams. In other embodiments, any one of the grooves 431, 432, 433, 434 can be formed as a plurality of grooves, while the rest can be formed as single grooves. In the embodiments of the present disclosure, there may be a plurality of grooves between a pair of dams such as the first dam 230 and the second dam 220, but there may be no groove between the second dam 220 and the third dam 210. In other embodiments of the present disclosure, the grooves 434, 431 may each be a plurality of grooves.

[0188] In addition, the shapes of the grooves 431, 432, 433, and 434 may vary. Referring to FIGS. 3, 5, and 6, on a plane, the grooves 431, 432, 433, and 434 may be circular and may correspond to the shape of the through hole, but the embodiments of the present disclosure are not limited thereto. For example, on a plane, the shape of one or more of the grooves 431, 432, 433, and 434 does not have to be a smooth curve, and may be wavy or have a V shape, square wave shape, semi-circular shape, or other shape on one of the outer wall and inner wall of the grooves 431, 432, 433, and 434, but the embodiments of the present disclosure are not limited thereto.

[0189] Referring to FIGS. 5, 6, and 7, the number, size, arrangement, and shape of the sacrificial layers 440 can correspond to the number, size, arrangement, and shape of the grooves 431, 432, 433, and 434.

[0190] FIGS. 7 to 12b are diagrams showing the process of forming the optical region of the display panel according to the embodiment of the present disclosure.

[0191] Referring to FIG. 7, the sacrificial layers 440 and the dams 210', 220', and 230' can be formed on the substrate 301.

[0192] For example, the lower shield metal 410 can be disposed on the substrate 301.

[0193] A plurality of insulating layers can be disposed on the substrate 301 and the lower shield metal 410. For example, the buffer layer 302, the lower interlayer insulating film 305, the upper buffer layer 307, and the upper interlayer insulating film 308 can be disposed. The planarization layer 310 can be formed by patterning on the upper interlayer insulating film 308.

[0194] A metal material is patterned on the upper interlayer insulating film 308 to form the sacrificial layer 440. The sacrificial layer 440 can be formed of the same material as the first electrode material. However, the embodiments of the present disclosure are not limited thereto.

[0195] The bank 354 can be patterned on the planarization layer 310 to form the dams 210’, 220’, 230’. The light-emitting stack 352 can be formed on the bank 354, the upper interlayer insulating film 308, the sacrificial layer 440, and the dams 210’, 220’, 230’.

[0196] Referring to FIG. 8, an electrode patterning material layer 420 can be formed in the HiAA bezel region HBA, which is a non-display region NA, using an electrode patterning material (EPM). The electrode patterning material (EPM) can be deposited using an FMM so as to cover at least a part of the HiAA bezel region HBA. At this time, the electrode patterning material layer 420 can be formed to overlap with the lower shield metal 410.

[0197] Referring to FIG. 9, a second electrode 353 can be formed by depositing a metal on the entire display region AA and a part of the non-display region NA using an OMM. At this time, the second electrode 353 can be effectively formed on the entire display region AA and a part of the non-display region NA, which is the region excluding the electrode patterning material layer 420. Thereby, the electrode patterning material layer 420 and the second electrode 353 can be located on the same plane.

[0198] Referring to FIG. 10, a capping layer 355 can be formed by depositing it entirely on the second electrode 353 and the electrode patterning material layer 420. However, the embodiments of the present disclosure are not limited thereto.

[0199] Referring to FIG. 11, at the lower part of the substrate 301, grooves 431’, 432’, 433’, 434’ can be formed by irradiating the sacrificial layer 440 with laser light 500. The laser light 500 can travel in the thickness direction of the substrate 301 on the lower surface of the substrate 301 and irradiate the lower surface of the sacrificial layer 440. The laser light 500 can have an infrared wavelength. However, the embodiments of the present disclosure are not limited thereto. When the laser light 500 is infrared, the transmittance with respect to the substrate 301 and the insulating layers 302, 305, 307, 308 is high, and the laser light 500 can reach the sacrificial layer 440 efficiently.

[0200] The sacrificial layer 440 can absorb the laser light 500, thermal expansion of the sacrificial layer 440 occurs, and the sacrificial layer 440 irradiated with the laser light 500 can be lifted off from the insulating layers 302, 305, 307, 308.

[0201] When the sacrificial layer 440 is peeled off, the light-emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 disposed on the upper portion of the peeling sacrificial layer 440 can also be removed together with the sacrificial layer 440. Thereby, the grooves 431’, 432’, 433’, 434’ formed from the openings of the light-emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 can be formed.

[0202] On the other hand, the lower shield metal 410 may be located between one end of the second electrode 353 and one end of the sacrificial layer 440. Since one end of the lower shield metal 410 is located between one end of the second electrode 353 and one end of the sacrificial layer 440, even when the laser light 500 is irradiated on the lower surface of the substrate 301, it is possible to prevent the laser light 500 from being irradiated to the second electrode 353 by the lower shield metal 410. Therefore, the distance between the second electrode 353 and the grooves 431’, 432’, 433’, 434’ can be reduced, and the width of the HiAA bezel region HBA can be reduced.

[0203] Referring to FIG. 12a, after forming the grooves 431’, 432’, 433’, 434’, the first inorganic encapsulation layer 361, the organic encapsulation layer 362, and the second inorganic encapsulation layer 363 are sequentially stacked and formed. In this case, the first inorganic encapsulation layer 361 and the second inorganic encapsulation layer 363 can be formed to extend to the through-hole TH region. Thereafter, the through-hole TH can be formed by laser along the trimming line. At this time, the first inorganic encapsulation layer 361 and the second inorganic encapsulation layer 363 can be arranged to be exposed to the through-hole TH.

[0204] Referring to FIG. 12b, after forming grooves 431’, 432’, 433’, 434’, the first inorganic encapsulation layer 361, the organic encapsulation layer 362, and the second inorganic encapsulation layer 363 are sequentially laminated and formed. In this case, the first inorganic encapsulation layer 361 can be formed so as not to extend to the through-hole TH region, and the second inorganic encapsulation layer 363 can extend to the through-hole TH region to form a region 363a that wraps the first inorganic encapsulation layer 361. Then, the through-hole TH can be formed by laser along the trimming line. One end 363a of the second inorganic encapsulation layer 363 can be formed to cover one end of the first inorganic encapsulation layer 361 in the through-hole TH.

[0205] Referring to FIGS. 5 to 12b, when the sacrificial layer 440 is peeled off and the light-emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 are removed, a part of the upper interlayer insulating film 308 can be exposed to the groups 431, 432, 433, 434. Then, when the first encapsulation layer 361 and the third encapsulation layer 363 are formed in the groups 431, 432, 433, 434, a sealing structure of a plurality of laminated inorganic layers can be formed. The sealing structure can include two or more upper interlayer insulating films 308, the first encapsulation layer 361, and the third encapsulation layer 363 that are in direct contact.

[0206] Two or more of the upper interlayer insulating film 308, the first encapsulation layer 361, and the third encapsulation layer 363 can contain the same material or can be formed of the same material. For example, it may be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), etc., but the embodiments of the present disclosure are not limited thereto.

[0207] In various embodiments of the present disclosure, when two or more of the groups 431, 432, 433, 434 are encapsulated by the first encapsulation layer 361 and the third encapsulation layer 363, respective portions of the light-emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 can be encapsulated between the upper interlayer insulating film 308 and the first encapsulation layer 361.

[0208] Briefly explaining the embodiments of the present disclosure described above, it is as follows.

[0209] According to an embodiment of the present disclosure, a display device can be provided that includes a substrate including a non-display area including a through hole and a display area surrounding the non-display area, an insulating layer disposed on the substrate, a light-emitting stack disposed on the insulating layer, a second electrode extending from the display area to the non-display area and disposed on the light-emitting stack, and an electrode patterning material layer disposed on the light-emitting stack in contact with one end of the second electrode, and one end of the light-emitting stack and one end of the electrode patterning material layer are arranged to coincide with each other.

[0210] In the display device according to an embodiment of the present disclosure, a dam disposed between the display area and the through hole can be included.

[0211] In the display device according to an embodiment of the present disclosure, the light-emitting stack and the electrode patterning material layer may be sequentially disposed on the dam.

[0212] In the display device according to an embodiment of the present disclosure, a groove located between the display area and the dam and in which the light-emitting stack and the electrode patterning material layer are each cut off can be included.

[0213] In the display device according to an embodiment of the present disclosure, a capping layer disposed on the second electrode and the electrode patterning material layer can be included.

[0214] In the display device according to an embodiment of the present disclosure, the capping layer may be cut off in the groove.

[0215] In the display device according to an embodiment of the present disclosure, the dam can include a plurality of dams spaced apart from each other.

[0216] In the display device according to an embodiment of the present disclosure, the plurality of dams include a first dam and a second dam, and a groove located between the first dam and the second dam and in which the light-emitting stack and the electrode patterning material layer are each cut off can be included.

[0217] In the display device according to an embodiment of the present disclosure, a groove may be included that is located between the display region and the first dam and in which the light-emitting stack and the electrode patterning material layer are each cut off.

[0218] In the display device according to an embodiment of the present disclosure, a lower shield metal disposed between the substrate and the insulating layer may be included, one end of the lower shield metal may overlap with the electrode patterning material layer, and the other end of the lower shield metal may overlap with the second electrode.

[0219] In the display device according to an embodiment of the present disclosure, one end of the lower shield metal may be located between one end of the second electrode and one end of the electrode patterning material layer.

[0220] In the display device according to an embodiment of the present disclosure, a sealing layer disposed on the capping layer may be included, and the sealing layer may be in contact with the insulating layer without being cut off in the groove.

[0221] In the display device according to an embodiment of the present disclosure, the sealing layer may include a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer, and the first inorganic sealing layer may be in contact with the insulating layer without being cut off in the groove.

[0222] In the display device according to an embodiment of the present disclosure, the first inorganic sealing layer and the second inorganic sealing layer may be exposed in the through hole.

[0223] In the display device according to an embodiment of the present disclosure, the second inorganic sealing layer may cover one end of the first inorganic sealing layer in the through hole.

[0224] In the display device according to an embodiment of the present disclosure, the thickness of the second electrode may not be smaller than the thickness of the electrode patterning material layer.

[0225] According to an embodiment of the present disclosure, a substrate including a non-display area including a through hole and a display area surrounding the non-display area, an insulating layer disposed on the substrate, a plurality of dams located between the display area and the through hole and disposed on the insulating layer, a light-emitting stack disposed on the insulating layer and the plurality of dams, a second electrode extending from the display area to the non-display area and disposed on the light-emitting stack, an electrode patterning material layer in contact with one end of the second electrode and disposed on the light-emitting stack, and a display device including grooves in which the light-emitting stack and the electrode patterning material layer are respectively cut off can be provided.

[0226] In the display device according to an embodiment of the present disclosure, the groove can be disposed in at least one of an area between the display area and the plurality of dams, an area between the plurality of dams, and an area between the plurality of dams and the through hole.

[0227] In the display device according to an embodiment of the present disclosure, a capping layer disposed on the second electrode and the electrode patterning material layer is included, and the capping layer may be cut off in the groove.

[0228] In the display device according to an embodiment of the present disclosure, a lower shield metal disposed between the substrate and the insulating layer is included, and one end of the lower shield metal can be located between one end of the second electrode and one end of the electrode patterning material layer.

[0229] In the display device according to an embodiment of the present disclosure, a sealing layer is disposed on the capping layer, the sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer, and the first inorganic sealing layer can be in contact with the insulating layer without being cut off in the groove.

[0230] In the display device according to an embodiment of the present disclosure, the thickness of the second electrode may not be smaller than the thickness of the electrode patterning material layer.

[0231] According to an embodiment of the present disclosure, there can be provided a method for manufacturing a display device, including steps of forming a substrate including a display area and a non-display area, forming a sacrificial layer and a dam in the non-display area, forming a light-emitting stack so as to cover the sacrificial layer and the dam, forming an electrode patterning material layer on the light-emitting stack and located in the non-display area, forming a second electrode on the light-emitting stack in contact with the electrode patterning material layer, forming a capping layer on the second electrode and the electrode patterning material layer, and irradiating the sacrificial layer with laser light to form a groove.

[0232] In the method for manufacturing a display device according to an embodiment of the present disclosure, in the step of forming a groove, the light-emitting stack may be cut off by the groove.

[0233] In the method for manufacturing a display device according to an embodiment of the present disclosure, in the step of forming a second electrode, the second electrode may be formed in the same layer as the electrode patterning material layer.

[0234] The method for manufacturing a display device according to an embodiment of the present disclosure may include a step of forming a sealing layer so as to cover the capping layer and the groove.

[0235] In the method for manufacturing a display device according to an embodiment of the present disclosure, the step of forming a sealing layer may be performed such that the sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer, the second inorganic sealing layer covers the organic sealing layer, and the second inorganic sealing layer is formed in contact with the first inorganic sealing layer.

[0236] In the method for manufacturing a display device according to an embodiment of the present disclosure, the second inorganic sealing layer may be formed so as to cover one end of the first inorganic sealing layer.

[0237] The display device and the method for manufacturing the same according to an embodiment of the present disclosure can pattern the light-emitting stack to block a side moisture permeation path by the light-emitting stack.

[0238] The display device and its manufacturing method according to the embodiments of the present disclosure can pattern a light-emitting stack and arrange a dam structure to prevent or reduce side moisture permeation paths and fine cracks caused by the light-emitting stack.

[0239] The display device and its manufacturing method according to the embodiments of the present disclosure can enable low power by preventing or reducing side moisture permeation and improving the lifespan.

[0240] The above description merely exemplarily explains the technical idea of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure pertains can make various modifications and deformations without departing from the essential characteristics of the present disclosure. Also, the embodiments disclosed in the present disclosure are for illustrative purposes rather than limiting the technical idea of the present disclosure. Therefore, the scope of the technical idea of the present disclosure is not limited by such embodiments.

Claims

1. a substrate including a non-display area including a through hole and a display area surrounding the non-display area; an insulating layer disposed on the substrate; a light emitting stack disposed on the insulating layer; an electrode extending from the display area to the non-display area and disposed on the light-emitting stack; an electrode patterning material layer disposed on the light emitting stack and in contact with one end of the electrode; One end of the light-emitting stack and one end of the electrode patterning material layer are aligned to each other.

2. The display device according to claim 1 , further comprising a dam disposed between the display area and the through-hole.

3. The display device of claim 2 , wherein the light-emitting stack and the electrode patterning material layer are disposed sequentially on the dam.

4. The display device of claim 3 , wherein the light-emitting stack and the electrode patterning material layer each include a recessed groove located between the display area and the dam.

5. The display device of claim 4 , further comprising a capping layer disposed on the electrode and the electrode patterning material layer.

6. The display device of claim 5 , wherein the capping layer is interrupted at the groove.

7. The display device according to claim 2 , wherein the dam includes a plurality of dams spaced apart from one another.

8. the plurality of dams further includes a first dam and a second dam; 8. The display device of claim 7, further comprising a first groove located between the first dam and the second dam, the first groove being cut into the light emitting stack and the electrode patterning material layer, respectively.

9. 9. The display device of claim 8, further comprising a second groove located between the display area and the first dam, the second groove being cut off from the light emitting stack and the electrode patterning material layer, respectively.

10. a bottom shield metal disposed between the substrate and the insulating layer; The display device of claim 1 , wherein one end of the lower shield metal overlaps the electrode patterning material layer, and the other end of the lower shield metal overlaps the electrode.

11. The display device of claim 10 , wherein one end of the lower shield metal is located between one end of the electrode and one end of the electrode patterning material layer.

12. a sealing layer disposed on the capping layer; The display device according to claim 5 , wherein the sealing layer is not interrupted at the groove and is in contact with the insulating layer.

13. The sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer, The display device according to claim 12 , wherein the first inorganic sealing layer is not interrupted at the groove and is in contact with the insulating layer.

14. The display device of claim 13 , wherein the first inorganic sealing layer and the second inorganic sealing layer are exposed to the through-hole.

15. The display device according to claim 13 , wherein the second inorganic sealing layer covers one end of the first inorganic sealing layer at the through-hole.

16. The display device of claim 1 , wherein the thickness of the electrode is not less than the thickness of the electrode patterning material layer.

17. a substrate including a non-display area including a through hole and a display area adjacent to the non-display area; an inorganic insulating layer disposed on the substrate; a light emitting stack disposed on the inorganic insulating layer; a common electrode extending from the display area to the non-display area and disposed on the light-emitting stack; an electrode patterning material layer disposed on the light emitting stack and in contact with one end of the common electrode; at least one groove formed in the light emitting stack and surrounding the through hole; an inorganic sealing layer disposed on the common electrode and in the at least one groove.

18. The display device of claim 17 , wherein the inorganic insulating layer and the inorganic sealing layer are in direct contact with each other in the at least one groove.

19. forming a substrate including a display area and a non-display area; forming a sacrificial layer and a dam in the non-display area; forming a light emitting stack over the sacrificial layer and the dam; forming an electrode patterning material layer on the light emitting stack located in the non-display area; forming a second electrode on the light emitting stack in contact with the electrode patterning material layer; forming a capping layer on the second electrode and the electrode patterning material layer; and forming a groove on the sacrificial layer by irradiating the sacrificial layer with laser light.

20. In the step of forming the groove, The method of claim 19 , wherein the light emitting stack is interrupted by the groove.

21. In the step of forming the second electrode, The method of claim 19, wherein the second electrode is formed in the same layer as the electrode patterning material layer.

22. The method of claim 19, further comprising forming a sealing layer to cover the capping layer and the groove.

23. The step of forming the sealing layer includes: the sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer; The method for manufacturing a display device according to claim 22 , wherein the second inorganic sealing layer is formed to cover the organic sealing layer and to be in contact with the first inorganic sealing layer.

24. The method of claim 23 , wherein the second inorganic sealing layer is formed so as to cover one end of the first inorganic sealing layer.

Images