Shift register unit, gate driving circuit, display device, and driving method

Abstract

To provide a shift register unit, gate driving circuit, display device and driving method.SOLUTION: A shift register unit comprises: a blanking input circuit; a display input circuit; an output circuit; and a compensation selection circuit. The blanking input circuit is arranged so as to input a blanking signal to a first node, the display input circuit is arranged so as to input a display signal to the first node, the output circuit is arranged so as to output a compensation output signal to an output terminal, and the compensation selection circuit is electrically connected to the output terminal, and is arranged so as to charge a control node by the composite output signal in response to a compensation selection control signal. The gate driving circuit composed of the shift register unit performs random compensation of a sub-pixel unit of a display panel, and can avoid a display failure occurring due to the successive compensation in a line unit over a long time.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - reference to related applications This application claims the priority of Chinese Patent Application No. 201810552885.4 filed on May 31, 2018 and Chinese Patent Application No. 201810151627.5 filed on February 14, 2018, and incorporates all of their published contents herein by reference as part of this application.

[0002] Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.

Background Art

[0003] In a display area, especially in a display using an OLED (Organic Light - Emitting Diode), currently, all gate driving circuits are integrated in a GATE IC. In the design of an IC, the chip area is a main factor affecting the cost of the chip, and engineers must focus on how to effectively reduce the chip area.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure provides a shift register unit including a blanking input circuit, a display input circuit, an output circuit, and a compensation selection circuit. The blanking input circuit is arranged to input a blanking signal to a first node during the blanking period of one frame. The display input circuit is arranged to input a display signal to the first node during the display period of one frame in response to a display input signal. The output circuit is arranged to output a composite output signal to an output terminal under the control of the level of the first node. The compensation selection circuit is electrically connected to the output terminal and is arranged to charge a control node with the composite output signal in response to a compensation selection control signal.

[0005] For example, in the shift register unit provided by one embodiment of the present disclosure, the composite output signal includes a first output signal and a second output signal. During the display period of one frame, the output circuit is arranged to output the first output signal to the output terminal under the control of the level of the first node. During the blanking period of one frame, the output circuit is arranged to output the second output signal to the output terminal under the control of the level of the first node.

[0006] For example, in the shift register unit provided by one embodiment of the present disclosure, during the display period of one frame, the compensation selection circuit is arranged to charge the control node with the first output signal in response to the compensation selection control signal.

[0007] For example, in the shift register unit provided by one embodiment of the present disclosure, the output terminal includes a shift signal output terminal, the shift signal output terminal outputs the composite output signal, the compensation selection circuit includes a first transistor, the gate of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, the first pole of the first transistor is connected to the shift signal output terminal to receive the composite output signal, and the second pole of the first transistor is connected to the control node.

[0008] For example, in the shift register unit provided by one embodiment of the present disclosure, the blanking input circuit further includes a charging sub-circuit arranged to input the blanking input signal to the control node in response to a second clock signal, and a storage sub-circuit arranged to store the blanking input signal input by the charging sub-circuit.

[0009] For example, in a shift register unit provided by one embodiment of the present disclosure, the charging sub-circuit includes a second transistor. The gate of the second transistor is connected to a second clock signal terminal to receive the second clock signal. The first pole of the second transistor is connected to a blanking input signal terminal to receive the blanking input signal. The second pole of the second transistor is connected to the control node. The storage sub-circuit includes a first capacitor. The first pole of the first capacitor is connected to the control node. The second pole of the first capacitor is connected to a first voltage terminal to receive a first voltage.

[0010] For example, in a shift register unit provided by one embodiment of the present disclosure, the display input circuit includes a fifth transistor. The gate of the fifth transistor is connected to a display input signal terminal to receive the display input signal. The first pole of the fifth transistor is connected to a second voltage terminal to receive a second voltage and use this as the display signal. The second pole of the fifth transistor is connected to the first node.

[0011] For example, in a shift register unit provided by one embodiment of the present disclosure, the output terminal further includes a pixel signal output terminal. The pixel signal output terminal outputs the composite output signal. The output circuit includes a sixth transistor, a seventh transistor, and a second capacitor. The gate of the sixth transistor is connected to the first node. The first pole of the sixth transistor is connected to a fourth clock signal terminal to receive the fourth clock signal and use this as the composite output signal. The second pole of the sixth transistor is connected to the shift signal output terminal. The gate of the seventh transistor is connected to the first node. The first pole of the seventh transistor is connected to the fourth clock signal terminal to receive the fourth clock signal and use this as the composite output signal. The second pole of the seventh transistor is connected to the pixel signal output terminal. The first pole of the second capacitor is connected to the first node. The second pole of the second capacitor is connected to the second pole of the sixth transistor.

[0012] For example, the shift register unit provided by one embodiment of the present disclosure further includes a noise reduction circuit and a first control circuit. The output terminal further includes a pixel signal output terminal, the pixel signal output terminal outputs the composite output signal, and the first control circuit is arranged to control the level of a second node under the control of the level of the first node. The noise reduction circuit is arranged to reduce the noise of the first node, the shift signal output terminal, and the pixel signal output terminal under the control of the level of the second node.

[0013] For example, in the shift register unit provided by one embodiment of the present disclosure, the first control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor. The gate of the eighth transistor is connected to a first pole and is arranged to receive a fourth voltage by being connected to a fourth voltage terminal. The second pole of the eighth transistor is connected to the second node. The gate of the ninth transistor is connected to the first pole and is arranged to receive a fifth voltage by being connected to a fifth voltage terminal. The second pole of the ninth transistor is connected to the second node. The gate of the tenth transistor is connected to the first node. The first pole of the tenth transistor is connected to the second node. The second pole of the tenth transistor is connected to a first voltage terminal and is arranged to receive a first voltage.

[0014] For example, in the shift register unit provided by one embodiment of the present disclosure, the noise reduction circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The gate of the eleventh transistor is connected to the second node, the first pole of the eleventh transistor is connected to the first node, the second pole of the eleventh transistor is connected to a first voltage terminal to receive a first voltage. The gate of the twelfth transistor is connected to the second node, the first pole of the twelfth transistor is connected to the shift signal output terminal, the second pole of the twelfth transistor is connected to the first voltage terminal to receive the first voltage. The gate of the thirteenth transistor is connected to the second node, the first pole of the thirteenth transistor is connected to the pixel signal output terminal, and the second pole of the thirteenth transistor is connected to a third voltage terminal to receive a third voltage.

[0015] For example, the shift register unit provided by one embodiment of the present disclosure further includes a second control circuit. The second control circuit is arranged to control the level of the second node in response to a blanking control signal.

[0016] For example, in the shift register unit provided by one embodiment of the present disclosure, the second control circuit includes a fourteenth transistor. The blanking control signal includes a first clock signal. The gate of the fourteenth transistor is connected to a first clock signal terminal to receive the first clock signal. The first pole of the fourteenth transistor is connected to the second node, and the second pole of the fourteenth transistor is connected to a first voltage terminal to receive a first voltage.

[0017] For example, the shift register unit provided by one embodiment of the present disclosure further includes a third control circuit. The third control circuit is arranged to control the level of the second node in response to a display control signal.

[0018] For example, in the shift register unit provided by one embodiment of the present disclosure, the third control circuit includes a fifteenth transistor, the display control signal includes the display input signal, a gate of the fifteenth transistor is connected to a display input signal terminal to receive the display input signal, a first pole of the fifteenth transistor is connected to the second node, and a second pole of the fifteenth transistor is connected to a first voltage terminal to receive a first voltage.

[0019] For example, the shift register unit provided by one embodiment of the present disclosure further includes a blanking reset circuit, and the blanking reset circuit is arranged to reset the first node in response to a blanking reset signal.

[0020] For example, in the shift register unit provided by one embodiment of the present disclosure, the blanking reset circuit includes a sixteenth transistor, a gate of the sixteenth transistor is connected to a second clock signal terminal to receive a second clock signal and use this as the blanking reset signal, a first pole of the sixteenth transistor is connected to the first node, and a second pole of the sixteenth transistor is connected to a first voltage terminal to receive a first voltage.

[0021] For example, the shift register unit provided by one embodiment of the present disclosure further includes a display reset circuit, and the display reset circuit is arranged to reset the first node in response to a display reset signal.

[0022] For example, in the shift register unit provided by one embodiment of the present disclosure, the display reset circuit includes a seventeenth transistor, a gate of the seventeenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first pole of the seventeenth transistor is connected to the first node, and a second pole of the seventeenth transistor is connected to a first voltage terminal to receive a first voltage.

[0023] For example, in a shift register unit provided by one embodiment of the present disclosure, the shift register unit further includes a 21st transistor and a fourth leakage prevention transistor arranged to prevent leakage at the first node. The blanking input circuit includes a separate sub-circuit arranged to input the blanking signal to the first node under the control of the level of the control node and the first clock signal. The separate sub-circuit includes a third transistor and a fourth transistor. The gate of the third transistor is connected to the control node. The first pole of the third transistor receives the blanking signal. The second pole of the third transistor is connected to the first pole of the fourth transistor. The gate of the fourth transistor is connected to the first clock signal terminal to receive the first clock signal. The second pole of the fourth transistor is connected to the first pole of the fourth leakage prevention transistor. The gate of the fourth leakage prevention transistor is connected to the first clock signal terminal to receive the first clock signal. The second pole of the fourth leakage prevention transistor is connected to the first node. The first pole of the 21st transistor is connected to the second voltage terminal. The gate of the 21st transistor is connected to the first node. The second pole of the 21st transistor is connected to the first pole of the fourth leakage prevention transistor.

[0024] At least one embodiment of the present disclosure further provides a gate driving circuit including a plurality of cascaded shift register units provided by any embodiment of the present disclosure.

[0025] For example, the gate driving circuit provided by one embodiment of the present disclosure includes a first sub-clock signal line, a second sub-clock signal line, a third sub-clock signal line, and a fourth sub-clock signal line. When the shift register unit includes a fourth clock signal terminal, the fourth clock signal terminal of the shift register unit at the (4n - 3)-th stage is connected to the first sub-clock signal line, the fourth clock signal terminal of the shift register unit at the (4n - 2)-th stage is connected to the second sub-clock signal line, the fourth clock signal terminal of the shift register unit at the (4n - 1)-th stage is connected to the third sub-clock signal line, and the fourth clock signal terminal of the shift register unit at the 4n-th stage is connected to the fourth sub-clock signal line, where n is an integer greater than 0.

[0026] For example, the gate driving circuit provided by one embodiment of the present disclosure further includes a fifth sub-clock signal line and a sixth sub-clock signal line. When the shift register unit includes a second clock signal terminal and a third clock signal terminal, the second clock signal terminal of the shift register unit at the (2n - 1)-th stage is connected to the fifth sub-clock signal line, the third clock signal terminal is connected to the sixth sub-clock signal line, the second clock signal terminal of the shift register unit at the 2n-th stage is connected to the sixth sub-clock signal line, and the third clock signal terminal is connected to the fifth sub-clock signal line, where n is an integer greater than 0.

[0027] For example, in the gate driving circuit provided by one embodiment of the present disclosure, when the shift register unit includes a blanking input signal terminal, a display input signal terminal, and a shift signal output terminal, the blanking input signal terminal of the shift register unit at the (n + 1)-th stage is connected to the shift signal output terminal of the shift register unit at the n-th stage, and the display input signal terminal of the shift register unit at the (n + 2)-th stage is connected to the shift signal output terminal of the shift register unit at the n-th stage, where n is an integer greater than 0.

[0028] At least one embodiment of the present disclosure further provides a display device including any gate drive circuit provided by the embodiments of the present disclosure.

[0029] At least one embodiment of the present disclosure comprises: a first input phase in which the display input circuit inputs the display signal to the first node in response to the display input signal, and a first output phase in which the output circuit outputs a first output signal under control of a level of the first node, during a display period of one frame; The present invention further provides a method for driving a shift register unit, the method including, during a blanking period of a frame, a second input phase in which the blanking input circuit inputs the blanking input signal to the control node and inputs the blanking signal to the first node, and a second output phase in which the output circuit outputs a second output signal under control of a level of the first node, wherein the composite output signal includes the first output signal and the second output signal.

[0030] For example, a driving method provided by one embodiment of the present disclosure further includes, during a display period of one frame, the compensation selection circuit responding to the compensation selection control signal and charging the control node with the first output signal.

[0031] At least one embodiment of the present disclosure further provides a driving method for a gate driving circuit, the method including: when the gate driving circuit drives a display panel, during a display period of any one frame, an output terminal of an n-th stage shift register unit outputs a first output signal, a compensation selection circuit in the n-th stage shift register unit responds to the compensation selection control signal and charges a control node in the n-th stage shift register unit with the first output signal; and during a blanking period of the one frame, an output terminal of the n-th stage shift register unit outputs a second output signal, wherein the composite output signal includes the first output signal and the second output signal, and n is an integer greater than 0.

Brief Description of the Drawings

[0032] To more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. It is obvious that the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

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Embodiments for Carrying Out the Invention

[0033] In order to make the above objects, technical solutions and advantages of the present disclosure clearer, hereinafter, the technical solutions of the embodiments of the present disclosure will be clearly and completely described with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts are within the scope of the claims of the present disclosure.

[0034] Technical terms or scientific terms used in the present disclosure have the ordinary meanings understood by those skilled in the art unless otherwise defined. Terms such as "first" and "second" used in the present disclosure do not indicate any order, number or importance, but are only used to distinguish different components. Similarly, similar terms such as "one", "a" or "the" do not limit the number either, but represent that there is at least one. Terms such as "comprising" or "including" mean that the element or item before the term encompasses the element or item described after the term and its equivalents, and do not exclude other elements or items. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, and may include electrical connections directly or indirectly. "Above", "below", "left", "right", etc. are only used to indicate relative positional relationships, and if the absolute position of the described object changes, the corresponding relative positional relationships may also change accordingly.

[0035] In an embodiment of the present disclosure, for example, when each circuit is implemented as an N-type transistor, "pull-up" means to charge one node or one electrode of one transistor, thereby increasing the absolute value of the level of the node or the electrode to realize the operation (for example, turn-on) of the corresponding transistor, and "pull-down" means to discharge one node or one electrode of one transistor, thereby decreasing the absolute value of the level of the node or the electrode to realize the operation (for example, turn-off) of the corresponding transistor.

[0036] Also for example, when each circuit is implemented as a P-type transistor, "pull-up" means to discharge one node or one electrode of one transistor, thereby decreasing the absolute value of the level of the node or the electrode to realize the operation (for example, turn-on) of the corresponding transistor, and "pull-down" means to charge one node or one electrode of one transistor, thereby increasing the absolute value of the level of the node or the electrode to realize the operation (for example, turn-off) of the corresponding transistor.

[0037] Furthermore, the specific meanings of "pull-up" and "pull-down" are adjusted accordingly according to the specific type of transistor used, as long as the transistor can be controlled to realize the corresponding switching function.

[0038] The gate drive circuit currently used in OLED generally needs to be composed of a combination of three sub-circuits: a detection circuit, a display circuit, and a connection circuit (or gate circuit) that outputs a composite pulse of the two. Such a circuit has a very complex structure and cannot meet the requirements of high resolution and narrow bezel.

[0039] When compensating for sub-pixel units in an OLED display panel, in addition to providing a pixel compensation circuit within the sub-pixel unit for internal compensation, a sense transistor can also be provided to perform external compensation. When performing external compensation, the gate driving circuit composed of a shift register unit needs to supply driving signals for scanning the transistor and the sense transistor to the sub-pixel units in the display panel respectively. For example, during the display period (Display) of one frame, a scanning driving signal for scanning the transistor is supplied, and during the blanking period (Blank) of one frame, a sensing driving signal for detecting the transistor is supplied.

[0040] In one external compensation method, the sensing driving signal output by the gate driving circuit performs sequential scanning in row units. For example, during the blanking period of the first frame, a sensing driving signal for the sub-pixel units in the first row of the display panel is output, and during the blanking period of the second frame, a sensing driving signal for the sub-pixel units in the second row of the display panel is output. In this way, for each frame, the frequency of the sensing driving signal corresponding to the sub-pixel units in one row is sequentially output in row units, that is, sequential compensation in row units for the display panel is completed.

[0041] However, when using the above method of sequential compensation in row units, display defects may occur. That is, firstly, in the process of scanning and displaying multiple frames, there is one scanning line moving in row units, and secondly, there are differences in the time points for performing external compensation, so the luminance difference between different regions of the display panel becomes relatively large. For example, when performing external compensation on the sub-pixel units in the 100th row of the display panel, external compensation has already been performed on the sub-pixel units in the 10th row of the display panel. At this time, for example, the emission luminance has decreased, and the emission luminance of the sub-pixel units in the 10th row has already changed, and the luminance of different regions of the display panel may become non-uniform. Such problems are more prominent in large-sized display panels.

[0042] Regarding the above problems, at least one embodiment of the present disclosure provides a shift register unit including a blanking input circuit, a display input circuit, an output circuit, and a compensation selection circuit. The blanking input circuit is arranged to input a blanking input signal to a control node and input a blanking signal to a first node during the blanking period of one frame. The display input circuit is arranged to input a display signal to the first node during the display period of one frame in response to a display input signal. The output circuit is arranged to output a composite output signal to an output terminal under the control of the level of the first node. The compensation selection circuit is electrically connected to the output terminal and arranged to charge the control node with the composite output signal in response to a compensation selection control signal. Embodiments of the present disclosure further provide a gate driving circuit, a display device, and a driving method corresponding to the above shift register unit.

[0043] The shift register unit, gate driving circuit, display device, and driving method provided by the embodiments of the present disclosure can further achieve random compensation on the premise of sequential compensation in row units (for example, it is necessary to perform sequential compensation in row units during shutdown detection, etc.). Thereby, it is possible to avoid problems of display defects such as uneven scanning lines and display brightness caused by performing sequential compensation in row units.

[0044] In addition, in the embodiments of the present disclosure, random compensation refers to an external compensation method that is distinguished from sequential compensation in row units and can randomly output a sensing drive signal corresponding to any one row of sub-pixel units in a display panel during the blanking period of a certain frame. The same applies to the following embodiments and will not be repeatedly described.

[0045] In addition, in the embodiments of the present disclosure, "one frame", "per frame", or "a certain frame" includes a display period and a blanking period that are performed in sequence. For example, in the display period, the gate drive circuit outputs a display output signal, and the display output signal can drive the display panel to complete the scanning display of the entire image from the first row to the last row. In the blanking period, the gate drive circuit outputs a blanking output signal, and the blanking output signal can be used to drive the sense transistor in a sub-pixel unit of a certain row in the display panel, thereby completing the external compensation of the sub-pixel unit of the row.

[0046] Hereinafter, embodiments of the present disclosure and their examples will be described in detail with reference to the drawings.

[0047] At least one embodiment of the present disclosure provides a shift register unit 10. As shown in FIG. 1, the shift register unit 10 includes a blanking input circuit 100, a display input circuit 200, an output circuit 300, and a compensation selection circuit 400. The blanking input circuit 100, the display input circuit 200, and the output circuit 300 are connected via a first node Q.

[0048] The blanking input circuit 100 inputs a blanking input signal to a control node H (not shown in FIG. 1. Refer to FIG. 2) and inputs a blanking signal to the first node Q during the blanking period of one frame.

[0049] In some embodiments, the blanking input circuit 100 may be connected to the blanking input signal terminal STU1 and the second clock signal terminal CLKB, and thereby, under the control of the second clock signal input to the second clock signal terminal CLKB, the blanking input signal input by the blanking input signal terminal STU1 may be input to the control node H. The blanking input circuit 100 may be further connected to the third clock signal terminal CLKC, and in the blanking period of one frame, the third clock signal input by the third clock signal terminal CLKC may be input to the first node Q as a blanking signal, thereby pulling up the potential of the first node Q to the operating potential.

[0050] For example, the blanking input circuit 100 may receive and store the blanking input signal during the display period of one frame, and output a blanking signal to the first node Q based on the blanking input signal during the blanking period of this frame, thereby pulling up the potential of the first node Q to the operating potential. Also, for example, the blanking input circuit 100 may receive and store the blanking input signal during the blanking period of one frame, and output a blanking signal to the first node Q based on the blanking input signal during the blanking period of the next frame, thereby pulling up the potential of the first node Q to the operating potential. The embodiments of the present disclosure do not limit this.

[0051] The display input circuit 200 is arranged to input a display signal to the first node Q during the display period of one frame in response to a display input signal. For example, in some embodiments, the display input circuit 200 may be connected to the display input signal terminal STU2 to receive the display input signal, and further connected to the second voltage terminal VDD to receive the second voltage and use this as the display signal. For example, during the display period of one frame, the display input circuit 200 may input the display signal to the first node Q under the control of the display input signal, thereby pulling up the potential of the first node Q to the operating potential.

[0052] In the embodiments of the present disclosure, the second voltage terminal VDD is arranged to input a DC high-level signal, that is, the second voltage is at a high level, which is the same in the following embodiments and will not be repeatedly described.

[0053] The output circuit 300 is arranged to output a composite output signal to the output terminal OUTPUT under the control of the level of the first node Q. For example, in some embodiments, the output circuit 300 may be connected to the fourth clock signal terminal CLKD to receive the fourth clock signal and use this as the composite output signal.

[0054] For example, in some embodiments, the composite output signal includes a first output signal and a second output signal. For example, the first output signal is a display output signal, and the second output signal is a blanking output signal. For example, during the display period of one frame, the output circuit 300 outputs a display output signal to the output terminal OUTPUT under the control of the level of the first node Q. For example, in some embodiments, the output terminal OUTPUT may include a shift signal output terminal CR and a pixel signal output terminal OUT. The display output signal output from the shift signal output terminal CR can be used for the scanning shift of the previous-stage shift register unit, and the display output signal output from the pixel signal output terminal OUT can also be used to drive the sub-pixel units in the display panel for scanning display. During the blanking period of one frame, the output circuit 300 outputs a blanking output signal to the output terminal OUTPUT under the control of the level of the first node Q, and the blanking output signal may be used to drive the sense transistor.

[0055] The compensation selection circuit 400 is electrically connected to the output terminal OUTPUT and is arranged to charge the control node H with the composite output signal in response to a compensation selection control signal.

[0056] For example, in some embodiments, during the display period of one frame, the compensation selection circuit 400 is arranged to charge the control node H with a first output signal (e.g., a display output signal) in response to a compensation selection control signal.

[0057] For example, when the output terminal OUTPUT includes a shift signal output terminal CR and a pixel signal output terminal OUT, in one example, the compensation selection circuit 400 may be electrically connected to the shift signal output terminal CR. In some embodiments, the compensation selection circuit 400 may further be connected to a compensation selection control terminal OE to receive a compensation selection control signal.

[0058] For example, when performing sequential compensation row by row, a signal for turning off the compensation selection circuit 400 may be input via the compensation selection control terminal OE so that the compensation selection circuit 400 does not operate. Also, for example, when performing random compensation, if it is necessary to compensate the sub-pixel unit of the nth row in the display panel in a certain frame, during the display period of that frame, when outputting a display output signal (composite output signal) for driving the sub-pixel unit of the nth row, a compensation selection control signal for turning on the compensation selection circuit 400 may be input via the compensation selection control terminal OE, and the compensation selection control signal may be arranged so that its timing is the same as that of the display output signal for driving the sub-pixel unit of the nth row described above. At the same time, since the compensation selection circuit 400 and the output terminal OUTPUT are electrically connected, when the compensation selection circuit 400 is on, the control node H in the blanking input circuit 100 is charged with the composite output signal, and the control node H is charged to a high level, whereby during the blanking period of that frame, the output circuit 300 may output a blanking output signal for driving the sense transistor in the sub-pixel unit of the nth row.

[0059] In some embodiments, the compensation selection control terminal OE may be arranged to be electrically connected to a control circuit, and the control circuit may supply an electrical signal for turning on or off the compensation selection circuit 400 to the compensation selection control terminal OE. For example, in one illustration, the control circuit may be implemented as an FPGA (Field Programmable Gate Array) device or other signal generation circuit.

[0060] The shift register unit 10 provided by the embodiments of the present disclosure may implement random compensation on the premise of considering providing the compensation selection circuit 400 to perform sequential compensation in row units, thereby avoiding problems of display defects such as uneven scanning lines and display brightness due to sequential compensation in row units.

[0061] In one illustration of an embodiment of the present disclosure, as shown in FIG. 2, the blanking input circuit 100 includes a charging sub-circuit 110, a memory sub-circuit 120, and a separation sub-circuit 130.

[0062] The charging sub-circuit 110 is arranged to input a blanking input signal to the control node H in response to a second clock signal. For example, the charging sub-circuit 110 is connected to the blanking input signal terminal STU1 to receive the blanking input signal, and the charging sub-circuit 110 is connected to the second clock signal terminal CLKB to receive the second clock signal. For example, the charging sub-circuit 110 is turned on under the control of the second clock signal, whereby the blanking input signal can be input to the control node H.

[0063] The memory sub-circuit 120 is arranged to store the blanking input signal input by the charging sub-circuit 110. For example, during the display period of one frame, the blanking input signal input to the control node H is charged to a high level, and the memory sub-circuit 120 stores the blanking input signal, whereby the high level of the control node H may be maintained throughout until the blanking period of the frame.

[0064] The separation sub-circuit 130 is arranged to input a blanking signal to the first node Q under the control of the level of the control node H and the first clock signal. For example, in some embodiments, the output circuit 130 is connected to the first clock signal terminal CLKA to receive the first clock signal, and the separation sub-circuit 130 is connected to the third clock signal terminal CLKC to receive the third clock signal and uses this as the blanking signal.

[0065] For example, during the blanking period of one frame, the separation sub-circuit 130 is turned on under the control of the level of the control node H and the first clock signal, whereby the blanking signal can be input to the first node Q. Also for example, in some embodiments, the separation sub-circuit 130 is provided between the first node Q and the control node H and is used to prevent the first node Q and the control node H from affecting each other. For example, when there is no need to output the blanking signal, the separation sub-circuit 130 may disconnect the connection between the first node Q and the control node H.

[0066] In the shift register unit 10 provided by the embodiments of the present disclosure, during different periods, the blanking input circuit 100 and the display input circuit 200 may respectively control the level of the first node Q, so that the blanking input circuit 100 and the display input circuit 200 share the same output circuit 300 to realize the output of the composite output signal.

[0067] In some embodiments, as shown in FIG. 3, the shift register unit 10 may further include a first control circuit 600, and the first control circuit 600 is arranged to control the level of the second node QB under the control of the level of the first node Q. For example, in one example, the first control circuit 600, the first voltage terminal VGL1, and the fourth voltage terminal VDD_A are connected. In the embodiments of the present disclosure, the first voltage terminal VGL1 may be arranged to input, for example, a DC high-level signal, and the same applies to the following embodiments and will not be repeatedly described.

[0068] For example, when the first node Q is at a high level, the first control circuit 600 may pull down the potential of the second node QB to a low level via the first voltage terminal VGL1. Also, for example, when the potential of the first node Q is at a low level, the first control circuit 600 may charge the second node QB with the fourth voltage (e.g., high level) input by the fourth voltage terminal VDD_A, and pull up the second node QB to a high level.

[0069] In another exemplary case, the first control circuit 600 may further be connected to a fifth voltage terminal VDD_B to receive a fifth voltage (e.g., high level). For example, the fourth voltage terminal VDD_A and the fifth voltage terminal VDD_B may be arranged to alternately input high levels, that is, when the fourth voltage terminal VDD_A inputs a high level, the fifth voltage terminal VDD_B inputs a low level, and when the fourth voltage terminal VDD_A inputs a low level, the fifth voltage terminal VDD_B inputs a high level.

[0070] In some embodiments, as shown in FIG. 3, the shift register unit 10 may further include a noise reduction circuit 500. The noise reduction circuit 500 is arranged to reduce the noise of the first node Q and the output terminal OUTPUT under the control of the level of the second node QB. For example, the noise reduction circuit 500 is connected to the first voltage terminal VGL1. When the noise reduction circuit 500 is turned on under the control of the level of the second node QB, it pulls down the first node Q and the output terminal OUTPUT via the first voltage terminal VGL1, thereby reducing the noise of the first node Q and the output terminal OUTPUT. When the output terminal OUTPUT includes a shift signal output terminal CR and a pixel signal output terminal OUT, the noise reduction circuit 500 can reduce the noise of the shift signal output terminal CR and the pixel signal output terminal OUT simultaneously.

[0071] In some embodiments, as shown in FIG. 3, the shift register unit 10 may further include a second control circuit 700, and the second control circuit 700 is arranged to control the level of the second node QB in response to a blanking control signal. For example, in one illustration, the second control circuit 700 is connected to the first clock signal terminal CLKA to receive the first clock signal and use this as the blanking control signal, and is connected to the first voltage terminal VGL1 to receive the first voltage which is at a low level. For example, during the blanking period of one frame, the second control circuit 700 may be turned on in response to the first clock signal, and thereby the second node QB may be pulled down via the first voltage terminal VGL1. By such a method, during the blanking period, the influence of the second node QB on the first node Q can be reduced, and the charging of the first node Q of the blanking input circuit 100 can be made more sufficient.

[0072] In addition, in the embodiments of the present disclosure, the second control circuit 700 may also be connected to other signal terminals to receive the blanking control signal, and the present disclosure does not limit this.

[0073] In some embodiments, as shown in FIG. 3, the shift register unit 10 may further include a third control circuit 800, and the third control circuit 800 is arranged to control the level of the second node QB in response to a display control signal. For example, in one illustration, the third control circuit 800 is connected to the display input signal terminal STU2 to receive a display input signal and use this as a display control signal, and is connected to the first voltage terminal VGL1 to receive a first voltage that is at a low level. For example, during the display period of one frame, the display input signal is supplied to the display input circuit 200 to charge the first node Q, and the display input signal is also supplied to the third control circuit 800 to turn on the third control circuit 800, whereby the second node QB may be pulled down via the first voltage terminal VGL1. By such a method, the influence of the second node QB on the first node Q during the display period can be reduced, and the charging of the first node Q of the display input circuit 200 can be made more sufficient.

[0074] Note that in the embodiments of the present disclosure, the third control circuit 800 may also be connected to other signal terminals to receive a display control signal, and the present disclosure does not limit this.

[0075] In some embodiments, as shown in FIG. 3, the shift register unit 10 may further include a blanking reset circuit 900, and the blanking reset circuit 900 is arranged to reset the first node Q in response to a blanking reset signal. For example, in one exemplary embodiment, the blanking reset circuit 900 is connected to the second clock signal terminal CLKB to receive the second clock signal and use this as the blanking reset signal, and is connected to the first voltage terminal VGL1 to receive the first voltage which is at a low level. For example, before the display period of one frame, the blanking reset circuit 900 may be turned on in response to the second clock signal, and thereby the first node Q may be reset via the first voltage terminal VGL1. Also for example, during the blanking period of one frame, the blanking reset circuit 900 may be turned on in response to the second clock signal, and thereby the first node Q may be reset via the first voltage terminal VGL1.

[0076] Note that in the embodiments of the present disclosure, in addition to the second clock signal, the blanking reset circuit 900 can also use other control signals as the blanking reset signal. For example, the blanking reset circuit 900 may also be connected to other signal terminals to receive the blanking reset signal, and the present disclosure does not limit this.

[0077] In some embodiments, as shown in FIG. 3, the shift register unit 10 may further include a display reset circuit 1000, and the display reset circuit 1000 is arranged to reset the first node Q in response to a display reset signal. For example, in one illustration, the display reset circuit 1000 may be connected to a display reset signal terminal STD to receive a display reset signal, and may also be connected to a first voltage terminal VGL1 to receive a first voltage that is at a low level. For example, during the display period of one frame, the display reset circuit 1000 may be turned on in response to the display reset signal, and thereby the first node Q may be reset via the first voltage terminal VGL1. For example, for the n-th stage shift register unit 10, the display reset signal terminal STD may be connected to the shift signal output terminal CR of the cascaded shift register unit 10 in the subsequent stage.

[0078] In the shift register unit 10 in FIG. 3, a noise reduction circuit 500, a first control circuit 600, a second control circuit 700, a third control circuit 800, a blanking reset circuit 900, and a display reset circuit 1000 are shown, but it will be understood by those skilled in the art that the above examples do not limit the claims of the present disclosure. In actual applications, those skilled in the art can choose to use or not use one or more of the above-described circuits according to the situation, and various combinations and modifications of the above-described circuits do not deviate from the principles of the present disclosure and will not be described in detail here.

[0079] In one illustration of an embodiment of the present disclosure, the shift register unit 10 shown in FIG. 3 may be implemented as the circuit structure shown in FIG. 4. As shown in FIG. 4, the shift register unit 10 includes transistors M1 to M17 of the first to seventeenth, and a first capacitor C1 and a second capacitor C2. The output terminal OUTPUT includes a shift signal output terminal CR and a pixel signal output terminal OUT, and both the shift signal output terminal CR and the pixel signal output terminal OUT may output a composite output signal. Note that the case where all the transistors shown in FIG. 4 are N-type transistors will be described as an example.

[0080] In the example shown in FIG. 4, more specifically, the compensation selection circuit 400 may be implemented as a first transistor M1. The gate of the first transistor M1 is connected to the compensation selection control terminal OE to receive a compensation selection control signal, the first pole of the first transistor M1 is connected to the shift signal output terminal CR (not shown for simplicity) to receive a composite output signal, and the second pole of the first transistor M1 is connected to the control node H to charge the control node H.

[0081] As shown in FIG. 4, the charging sub-circuit 110 in the blanking input circuit 100 may be implemented as a second transistor M2. The gate of the second transistor M2 is connected to the second clock signal terminal CLKB to receive a second clock signal, the first pole of the second transistor M2 is connected to the blanking input signal terminal STU1 to receive a blanking input signal, and the second pole of the second transistor M2 is connected to the control node H. For example, when the second clock signal is a high-level on signal, the second transistor M2 is turned on under the control of the second clock signal, whereby the blanking input signal can be input to the control node H to charge it. For example, when the shift register units 10 shown in FIG. 4 are cascaded to form one gate drive circuit, the blanking input signal terminal STU1 of the n + 1-stage shift register unit 10 may be electrically connected to the shift signal output terminal CR of the n-stage shift register unit 10, where n is an integer greater than 0.

[0082] As shown in FIG. 4, the storage sub-circuit 120 in the blanking input circuit 100 may be implemented as a first capacitor C1. The first pole of the first capacitor C1 is connected to the control node H, and the second pole of the first capacitor C1 is connected to the first voltage terminal VGL1 to receive a first voltage. The first capacitor C1 may be provided to hold the potential of the control node H. For example, during the display period of one frame, the charging sub-circuit 110 may charge the control node H to a high potential, and the first capacitor C1 may hold the high potential of the control node H until the blanking period of the frame.

[0083] As shown in FIG. 4, the separation sub-circuit 130 in the blanking input circuit 100 may be implemented as the third transistor M3 and the fourth transistor M4. The gate of the third transistor M3 is connected to the control node H. The first pole of the third transistor M3 is connected to the third clock signal terminal CLKC to receive the third clock signal, which is used as the blanking signal. The second pole of the third transistor M3 is connected to the first pole of the fourth transistor M4. The gate of the fourth transistor M4 is connected to the first clock signal terminal CLKA to receive the first clock signal. The second pole of the fourth transistor M4 is connected to the first node Q. For example, during the blanking period of one frame, when the third transistor M3 is turned on under the control of the control node H and the first clock signal becomes a high-level on signal, the fourth transistor M4 is turned on under the control of the first clock signal. As a result, the third clock signal can charge the first node Q through the third transistor M3 and the fourth transistor M4.

[0084] As shown in FIG. 4, the display input circuit 200 may be implemented as the fifth transistor M5. The gate of the fifth transistor M5 is connected to the display input signal terminal STU2 to receive the display input signal. The first pole of the fifth transistor M5 is connected to the second voltage terminal VDD to receive the second voltage, which is used as the display signal. The second pole of the fifth transistor M5 is connected to the first node Q. For example, during the display period of one frame, the fifth transistor M5 is turned on under the control of the display input signal, and as a result, the first node Q is charged by the second voltage. For example, when the shift register units 10 shown in FIG. 4 are cascaded to form a gate driving circuit, the display input signal terminal STU2 of the (n + 2)-th stage shift register unit 10 may be electrically connected to the shift signal output terminal CR of the (n + 1)-th stage or the n-th stage shift register unit 10, where n is an integer greater than 0.

[0085] As shown in FIG. 4, the output circuit 300 may be implemented by including a sixth transistor M6, a seventh transistor M7, and a second capacitor. The gate of the sixth transistor M6 is connected to the first node Q, the first pole of the sixth transistor M6 is connected to the fourth clock signal terminal CLKD to receive the fourth clock signal and use this as a composite output signal, the second pole of the sixth transistor M6 is connected to the shift signal output terminal CR, the gate of the seventh transistor M7 is connected to the first node Q, the first pole of the seventh transistor M7 is connected to the fourth clock signal terminal CLKD to receive the fourth clock signal and use this as a composite output signal, the second pole of the seventh transistor M7 is connected to the pixel signal output terminal OUT, the first pole of the second capacitor C2 is connected to the first node Q, and the second pole of the second capacitor C2 is connected to the second pole of the sixth transistor M6. For example, when the potential of the first node Q is at a high level, the sixth transistor M6 and the seventh transistor M7 are turned on, whereby the fourth clock signal can be output as a composite output signal to the shift signal output terminal CR and the pixel signal output terminal OUT.

[0086] As shown in FIG. 4, the first control circuit 600 may be implemented by including an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The gate of the eighth transistor M8 is connected to the first pole and is arranged to be connected to the fourth voltage terminal VDD_A to receive the fourth voltage. The second pole of the eighth transistor M8 is connected to the second node QB. The gate of the ninth transistor M9 is connected to the first pole and is arranged to be connected to the fifth voltage terminal VDD_B to receive the fifth voltage. The second pole of the ninth transistor M9 is connected to the second node QB. The gate of the tenth transistor M10 is connected to the first node Q. The first pole of the tenth transistor M10 is connected to the second node QB. The second pole of the tenth transistor M10 is connected to the first voltage terminal VGL1 and is arranged to receive the first voltage.

[0087] For example, the fourth voltage terminal VDD_A and the fifth voltage terminal VDD_B input high levels alternately. That is, when the fourth voltage terminal VDD_A inputs a high level, the fifth voltage terminal VDD_B inputs a low level, and when the fourth voltage terminal VDD_A inputs a low level, the fifth voltage terminal VDD_B inputs a high level. That is, only one of the eighth transistor M8 and the ninth transistor M9 may be arranged to be in an on state. By doing so, it is possible to avoid performance drift due to the transistor being on for a long time. When the eighth transistor M8 or the ninth transistor M9 is turned on, the fourth voltage or the fifth voltage can charge the second node QB, thereby pulling up the potential of the second node QB to a high level. When the potential of the first node Q is at a high level, the tenth transistor M10 is turned on. For example, in terms of the design of the transistor (for example, the arrangement of the size ratio, threshold voltage, etc. of both), when both the tenth transistor M10 and the eighth transistor M8 (or the ninth transistor) are turned on, the level of the second node QB can be pulled down to a low level, and the low level may be arranged so as to keep the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 off.

[0088] As shown in FIG. 4, the pull-down circuit 500 may be implemented by including an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The gate of the eleventh transistor M11 is connected to the second node QB, the first pole of the eleventh transistor M11 is connected to the first node Q, the second pole of the eleventh transistor M11 is connected to the first voltage terminal VGL1 to receive the first voltage, the gate of the twelfth transistor M12 is connected to the second node QB, the first pole of the twelfth transistor M12 is connected to the shift signal output terminal CR, the second pole of the twelfth transistor M12 is connected to the first voltage terminal VGL1 to receive the first voltage, the gate of the thirteenth transistor M13 is connected to the second node QB, the first pole of the thirteenth transistor M13 is connected to the pixel signal output terminal OUT, and the second pole of the thirteenth transistor M13 is connected to the third voltage terminal VGL2 to receive the third voltage. In an embodiment of the present disclosure, for example, the third voltage terminal VGL2 is arranged to input a DC low-level signal, that is, the third voltage is at a low level. The same applies to the following embodiments and will not be repeatedly described.

[0089] For example, when the potential of the second node QB is at a high level, the eleventh transistor M11 and the twelfth transistor M12 are turned on. As a result, the first node Q and the shift signal output terminal CR can be pulled down by the first voltage terminal VGL1, and the noise of the first node Q and the shift signal output terminal CR can be reduced. At the same time, when the potential of the second node QB is at a high level, the thirteenth transistor M13 is also turned on. As a result, the pixel signal output terminal OUT can be pulled down by the third voltage terminal VGL2, and the noise of the pixel signal output terminal OUT can be reduced.

[0090] In one example, the first voltage and the third voltage may be different. For example, the first voltage may be set to -10V and the third voltage may be set to -6V. In another example, the third voltage terminal VGL2 may not be provided, and the second pole of the thirteenth transistor M13 may be connected to the first voltage terminal VGL1 to receive the first voltage. The embodiments of the present disclosure do not limit this.

[0091] As shown in FIG. 4, the second control circuit 700 may be implemented as a fourteenth transistor M14. The gate of the fourteenth transistor M14 is connected to the first clock signal terminal CLKA to receive the first clock signal. The first pole of the fourteenth transistor M14 is connected to the second node QB, and the second pole of the fourteenth transistor M14 is connected to the first voltage terminal VGL1 to receive the first voltage. For example, when the first clock signal is at a high level, the fourteenth transistor M14 is turned on, and thereby the second node QB can be pulled down by the first voltage terminal VGL1. By such a method, in the blanking period of one frame, the influence of the second node QB on the first node Q can be reduced, and the charging of the first node Q of the blanking input circuit 100 can be made more sufficient.

[0092] As shown in FIG. 4, the third control circuit 800 may be implemented as a fifteenth transistor M15. The gate of the fifteenth transistor M15 is connected to the display input signal terminal STU2 to receive the display input signal. The first pole of the fifteenth transistor M15 is connected to the second node QB, and the second pole of the fifteenth transistor M15 is connected to the first voltage terminal VGL1 to receive the first voltage. For example, when the display input signal is at a high level, the fifteenth transistor M15 is turned on, so that the second node QB can be pulled down by the first voltage terminal VGL1. For example, when the shift register units 10 shown in FIG. 4 are cascaded to form one gate drive circuit, the display input signal terminal STU2 of the (n + 2)-th stage shift register unit 10 may be electrically connected to the shift signal output terminal CR of the (n + 1)-th stage or n-th stage shift register unit 10, where n is an integer greater than 0. By such a method, in the display period of one frame, the influence of the second node QB on the first node Q can be reduced, and the charging of the first node Q of the display input circuit 200 can be made more sufficient.

[0093] As shown in FIG. 4, the blanking reset circuit 900 may be implemented as the 16th transistor M16. The gate of the 16th transistor M16 is connected to the second clock signal terminal CLKB to receive the second clock signal, which is used as the blanking reset signal. The first pole of the 16th transistor M16 is connected to the first node Q, and the second pole of the 16th transistor M16 is connected to the first voltage terminal VGL1 to receive the first voltage. For example, when the second clock signal is at a high level, the 16th transistor M16 is turned on, so that the first node Q can be reset by the first voltage terminal VGL1.

[0094] As shown in FIG. 4, the display reset circuit 1000 may be implemented as the 17th transistor M17. The gate of the 17th transistor M17 is connected to the display reset signal terminal STD to receive the display reset signal. The first pole of the 17th transistor M17 is connected to the first node Q, and the second pole of the 17th transistor M17 is connected to the first voltage terminal VGL1 to receive the first voltage. For example, when the display reset signal is at a high level, the 17th transistor M17 is turned on, so that the first node Q can be reset by the first voltage terminal VGL1. For example, when the shift register units 10 shown in FIG. 4 are cascaded to form one gate driving circuit, the display reset signal terminal STD of the nth stage shift register unit 10 may be connected to the shift signal output terminal CR of the cascaded subsequent shift register unit 10.

[0095] As shown in FIG. 5, another embodiment of the present disclosure further provides a shift register unit 10. The shift register unit 10 shown in FIG. 5 may further include the 18th transistor M18 in the output circuit 300 compared with the shift register unit 10 shown in FIG. 4, and similarly, the noise reduction circuit 500 may further include the 19th transistor M19.

[0096] As shown in FIG. 5, the gate of the 18th transistor M18 is connected to the first node Q, the first pole of the 18th transistor M18 is connected to the fifth clock signal terminal CLKE to receive the fifth clock signal, and the second pole of the 18th transistor M18 is connected to another pixel signal output terminal OUT2. For example, when the potential of the first node Q is at a high level, the 18th transistor M18 is turned on, so that the fifth clock signal is output to the pixel signal output terminal OUT2. For example, in one example, the fifth clock signal input by the fifth clock signal terminal CLKE may be arranged to be the same as the fourth clock signal input by the fourth clock signal terminal CLKD. Also for example, in another example, the fifth clock signal may be different from the fourth clock signal terminal, so that different signals may be output from the pixel signal output terminals OUT and OUT2 respectively to enhance the driving ability.

[0097] As shown in FIG. 5, the gate of the 19th transistor M19 is connected to the second node QB, the first pole of the 19th transistor M19 is connected to the pixel signal output terminal OUT2, and the second pole of the 19th transistor M19 is connected to the third voltage terminal VGL2. For example, when the potential of the second node QB is at a high level, the 19th transistor M19 is turned on, so that the noise of the pixel signal output terminal OUT2 can be reduced by the third voltage terminal VGL2.

[0098] In the above, only the example in which the shift register unit includes two or three output terminals is given. However, based on the description of the present disclosure, more output terminals may be provided according to the actual situation, and those skilled in the art will understand that the above examples do not limit the scope of the claims of the present disclosure.

[0099] As described above, in the shift register unit 10 provided by the embodiments of the present disclosure, the potential at the control node H may be maintained by the first capacitor C1, and the potential of the first node Q may be maintained by the second capacitor C2. The first capacitor C1 and / or the second capacitor C2 may be a capacitor device fabricated by a manufacturing process, for example, a capacitor device realized by a dedicated capacitor electrode. Each electrode of the capacitor may be realized by a metal layer, a semiconductor layer (e.g., doped polycrystalline silicon), etc., or the first capacitor C1 and / or the second capacitor C2 may be realized by parasitic capacitors between devices. The connection method of the first capacitor C1 and / or the second capacitor C2 is not limited to the method described above, and other applicable connection methods may be used, as long as the level written to the control node H or the first node Q can be stored. When the potential of the first node Q and / or the control node H is maintained at a high level, the first poles of some transistors (e.g., the first transistor M1, the second transistor M2, the fourth transistor M4, the eleventh transistor M11, the sixteenth transistor M16, and the seventeenth transistor M17) are connected to the first node Q and / or the control node H, and the second poles are connected to a low-level signal. Even if the gates of these transistors input a non-on signal, there is a voltage difference between the first pole and the second pole, so leakage may occur, which may deteriorate the effect of maintaining the potential of the first node Q and / or the control node H in the shift register unit 10.

[0100] For example, as shown in FIG. 4, taking the control node H as an example, the first pole of the second transistor M2 is connected to the blanking input signal terminal STU1, and the second pole is connected to the control node H. When the control node H is at a high level and the signal input by the blanking input signal terminal STU1 is at a low level, the control node H may leak through the second transistor M2.

[0101] Regarding the above problem, as shown in FIG. 6, one embodiment of the present disclosure provides a shift register unit 10 for preventing leakage. The difference between the shift register unit 10 in FIG. 4 of the shift register unit 10 is that a first leakage prevention transistor M1_b, a second leakage prevention transistor M2_b, a fourth leakage prevention transistor M4_b, an eleventh leakage prevention transistor M11_b, a sixteenth leakage prevention transistor M16_b, a seventeenth leakage prevention transistor M17_b, a twelfth transistor M20, and a twenty-first transistor M21 are added. Hereinafter, taking the second leakage prevention transistor M2_b as an example, the operation principle of leakage prevention will be described.

[0102] The gate of the second leakage prevention transistor M2_b is connected to the second clock signal terminal CLKB, the first pole of the second leakage prevention transistor M2_b is connected to the second pole of the twentieth transistor M20, and the second pole of the second leakage prevention transistor M2_b is connected to the control node H. The gate of the twentieth transistor M20 is connected to the control node H, and the first pole of the twentieth transistor M20 is connected to the second voltage terminal VDD to receive the second voltage which is at a high level. When the control node H is at a high level, the twentieth transistor M20 is turned on under the control of the level of the control node H, so that the high-level signal input by the second voltage terminal VDD can be input to the first pole of the second leakage prevention transistor M2_b, thereby making both the first pole and the second pole of the second leakage prevention transistor M2_b in a high-level state, and preventing the charge at the control node H from leaking through the second leakage prevention transistor M2_b. At this time, since the gate of the second leakage prevention transistor M2_b is connected to the gate of the second transistor M2, the combination of the second transistor M2 and the second leakage prevention transistor M2_b can achieve the same effect as the second transistor M2 described above, and also has the effect of preventing leakage.

[0103] Similarly, by combining the 20th transistor M20 with the first anti-leakage transistor M1_b, the charge at the control node H can be prevented from leaking through the first anti-leakage transistor M1_b and the first transistor M1. Similarly, a leakage prevention structure can be realized by combining the 21st transistor M21 with the 4th anti-leakage transistor M4_b, the 11th anti-leakage transistor M11_b, the 16th anti-leakage transistor M16_b, and the 17th anti-leakage transistor M17_b respectively, thereby preventing the charge at the first node Q from leaking. The operating principle of preventing leakage at the first node Q is the same as the operating principle of preventing leakage at the control node H described above, and will not be repeated here.

[0104] Note that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, but in the embodiments of the present disclosure, thin film transistors will be described as examples. Since the source and drain of the transistors used here may be symmetric in structure, the source and drain are not distinguished in structure. In the embodiments of the present disclosure, in order to distinguish the two poles other than the gate of the transistor, one of the poles is directly described as the first pole and the other pole is described as the second pole. Also, due to the difference in the characteristics of the transistors, the transistors can be divided into N-type and P-type transistors.

[0105] When the transistor is a P-type transistor, the on-voltage is a low-level voltage (for example, 0V, -5V, -10V, or other appropriate voltages), and the off-voltage is a high-level voltage (for example, 5V, 10V, or other appropriate voltages). When the transistor is an N-type transistor, the on-voltage is a high-level voltage (for example, 5V, 10V, or other appropriate voltages), and the off-voltage is a low-level voltage (for example, 0V, -5V, -10V, or other appropriate voltages).

[0106] In addition, when an N-type transistor is taken as an example to describe the transistors used in the shift register unit 10 provided in the embodiments of the present disclosure, in the embodiments of the present disclosure, for example, transistors not limited to P-type transistors may be used as at least some of the transistors in the shift register unit 10, but not limited thereto.

[0107] An embodiment of the present disclosure provides a gate driving circuit 20. As shown in FIG. 7, the gate driving circuit 20 includes a plurality of cascaded shift register units 10. Any one or more of the shift register units 10 may use the structure of the shift register unit 10 provided in the embodiments of the present disclosure or a modification thereof. Note that in FIG. 7, only the first four stages of shift register units (A1, A2, A3, and A4) of the gate driving circuit 20 are exemplarily shown.

[0108] As shown in FIG. 7, the gate driving circuit 20 further includes a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, a third sub-clock signal line CLK_3, and a fourth sub-clock signal line CLK_4. When the shift register unit includes a fourth clock signal terminal CLK_D, the fourth clock signal terminal CLK_D of the (4n - 3)-th stage shift register unit is connected to the first sub-clock signal line CLK_1, the fourth clock signal terminal CLK_D of the (4n - 2)-th stage shift register unit is connected to the second sub-clock signal line CLK_2, the fourth clock signal terminal CLK_D of the (4n - 1)-th stage shift register unit is connected to the third sub-clock signal line CLK_3, and the fourth clock signal terminal CLK_D of the 4n-th stage shift register unit is connected to the fourth sub-clock signal line CLK_4, where n is an integer greater than 0.

[0109] As shown in FIG. 7, the gate driving circuit 20 may further include a fifth sub-clock signal line CLK_5 and a sixth sub-clock signal line CLK_6. When the shift register unit includes a second clock signal terminal CLK_B and a third clock signal terminal CLK_C, the second clock signal terminal CLK_B of the shift register unit at the (2n - 1)-th stage is connected to the fifth sub-clock signal line CLK_5, and the third clock signal terminal CLK_C is connected to the sixth sub-clock signal line CLK_6. The second clock signal terminal CLK_B of the shift register unit at the 2n-th stage is connected to the sixth sub-clock signal line CLK_6, and the third clock signal terminal CLK_C is connected to the fifth sub-clock signal line CLK_5, where n is an integer greater than 0.

[0110] As shown in FIG. 7, the gate driving circuit 20 may further include a seventh sub-clock signal line CLK_7, and the first clock signal terminal CLK_A of each stage of the shift register is connected to the seventh sub-clock signal line CLK_7.

[0111] As shown in FIG. 7, the blanking input signal terminal STU1, the display input signal terminal STU2 of the first-stage shift register unit, and the display input signal terminal STU2 of the second-stage shift register unit are all connected to the input signal line STU, and receive, for example, a trigger signal STV. The blanking input signal terminal STU1 of the (n + 1)-th stage shift register unit is connected to the shift signal output terminal CR of the n-th stage shift register unit in addition to the first-stage shift register unit. The display input signal terminal STU2 of the (n + 2)-th stage shift register unit is connected to the shift signal output terminal CR of the n-th stage shift register unit in addition to the first-stage and second-stage shift register units. The display reset signal terminal STD of the n-th stage shift register unit is connected to the shift signal output terminal CR of the (n + 3)-th stage shift register unit in addition to the last three-stage shift register units, where n is an integer greater than 0.

[0112] FIG. 8 is a signal timing chart for the gate driving circuit 20 shown in FIG. 7 to perform sequential compensation in row units, and FIG. 9 is a signal timing chart for the gate driving circuit 20 shown in FIG. 7 to perform random compensation. In FIGS. 8 and 9, Q<1> and Q<2> respectively represent the first node Q in the first-stage and second-stage shift register units in the gate driving circuit 20. OUT<1>, OUT<2>, OUT<3> and OUT<4> respectively represent the pixel signal output terminals OUT in the first-stage, second-stage, third-stage and fourth-stage shift register units in the gate driving circuit 20. 1F, 2F, 3F and 4F respectively indicate the first frame, the second frame, the third frame and the fourth frame. Display indicates the display period in one frame, and Blank indicates the blanking period in one frame. Note that since the potentials of the shift signal output terminal CR and the pixel signal output terminal OUT in each stage of the shift register unit are the same, the shift signal output terminal CR is not shown in FIGS. 8 and 9.

[0113] Note that the signal levels in the signal timing charts shown in FIGS. 8 and 9 are merely exemplary and do not represent actual level values.

[0114] Hereinafter, with reference to the signal timing chart in FIG. 8, the operating principle when performing sequential compensation on the gate driving circuit 20 shown in FIG. 7 in row units will be described. For example, as the shift register unit in the gate driving circuit 20 shown in FIG. 7, the shift register unit shown in FIG. 4 may be used.

[0115] When performing sequential compensation in line units, a DC low-level signal is input through the compensation selection control terminal OE to keep the first transistor M1 off. Before starting the first frame 1F, both the fifth sub-clock signal line CLK_5 and the sixth sub-clock signal line CLK_6 supply high levels. Since the fifth sub-clock signal line CLK_5 and the sixth sub-clock signal line CLK_6 are alternately connected to the second clock signal terminal CLK_B in the shift register unit, the second transistor M2 and the sixteenth transistor M16 in each shift register unit can be turned on, thereby resetting the control node H and the first node Q in each shift register unit to achieve a full reset. Then, the signal supplied by the sixth sub-clock signal line CLK_6 changes to a low level, and the signal supplied by the fifth sub-clock signal line CLK_5 continues to hold a high level.

[0116] Since the fifth voltage terminal VDD_B inputs a high level, the ninth transistor M9 is turned on, and the second node QB is charged to a high level. The high level of the second node QB turns on the eleventh transistor M11, thereby pulling down the first node Q to a low level.

[0117] During the display period Display of the first frame 1F, the operation process of the first-stage shift register unit is as follows.

[0118] In the first phase 1, since the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first-stage shift register unit are both connected to the input signal line STU, initially, both the blanking input signal terminal STU1 and the display input signal terminal STU2 input a high level. At the same time, since the second clock signal terminal CLKB (connected to the fifth sub-clock signal line CLK5) inputs a high level, the second transistor M2 is turned on, and the control node H is charged to a high level and stored in the first capacitor C1. Due to the high level of the display input signal terminal STU2, the fifteenth transistor M15 is turned on, which can help pull down the second node QB.

[0119] Next, the second clock signal terminal CLKB inputs a low level, and the second transistor M2 is turned off. Since the display input signal terminal STU2 continues to input a high level, the high-level signal of the second voltage terminal VDD can charge the first node Q through the fifth transistor M5, pull up the first node Q to a high potential, and store it in the second capacitor C2.

[0120] The sixth transistor M6 and the seventh transistor M7 are turned on under the control of the first node Q. However, since the fourth clock signal terminal CLKD (connected to the first sub-clock signal line CLK1) inputs a low-level signal at this time, both the shift signal output terminal CR and the pixel signal output terminal OUT output low-level signals.

[0121] In the second phase 2, the fourth clock signal terminal CLKD inputs a high-level signal, and since the potential of the first node Q is further pulled up for bootstrap, the sixth transistor M6 and the seventh transistor M7 remain on, whereby both the shift signal output terminal CR and the pixel signal output terminal OUT output high-level signals. For example, the high-level signal output from the shift signal output terminal CR may be used for the scanning shift of the previous-stage shift register unit, and the high-level signal output from the pixel signal output terminal OUT may be used to drive and display the sub-pixel unit in the display panel.

[0122] In the third phase 3, then, the fourth clock signal terminal CLKD inputs a low-level signal, and both the shift signal output terminal CR and the pixel signal output terminal OUT discharge through the fourth clock signal terminal CLKD, whereby the reset of the shift signal output terminal CR and the pixel signal output terminal OUT may be completed. Since the shift signal output terminal CR and the pixel signal output terminal OUT are reset to a low level, due to the coupling action of the transistors, the potential of the first node Q drops by one unit. At the same time, since the display reset signal terminal STD of the first-stage shift register unit and the shift signal output terminal CR of the fourth-stage shift register unit are connected, at this time, the shift signal output terminal CR of the fourth-stage shift register unit has not yet output a high-level signal and does not pull down the first node Q, so the first node Q can maintain a high level.

[0123] In the fourth phase 4, then, the shift signal output terminal CR of the fourth-stage shift register unit outputs a high level, inputs a high-level signal to the display reset signal terminal STD of the first-stage shift register unit, turns on the seventeenth transistor M17, pulls down the first node Q to a low level, and completes the reset of the first node Q.

[0124] Due to the above process, the potential of the first node Q in the first stage changes to exhibit a "tower shape". When the shift signal output terminal CR and the pixel signal output terminal OUT are at a high level, the potential of the first node Q rises due to bootstrap. When the shift signal output terminal CR and the pixel signal output terminal OUT discharge through the sixth transistor M6 and the seventh transistor M7 respectively, the current flowing through the transistor may be larger, and the discharge speed becomes faster. At the same time, the charges accumulated at the shift signal output terminal CR and the pixel signal output terminal OUT may be discharged through the sixth transistor M6 and the seventh transistor M7 respectively. Therefore, transistors with a relatively small size can be used for the twelfth transistor M12 and the thirteenth transistor M13 for reset, thereby reducing the area occupied by the shift register unit.

[0125] During the display period of the first frame described above, since the first clock signal terminal CLKA (connected to the seventh sub-clock signal line CLK7) always maintains a low level, the fourth transistor M4 remains in an off state, and the high level pre-stored at the control node H by the fourth transistor M4 is blocked from affecting the display period.

[0126] After the first-stage shift register unit drives the sub-pixels in the first row of the display panel to complete the display, similarly, the second-stage and third-stage shift register units drive the sub-pixels in the display panel row by row to complete the driving of the display of one frame. Thus, the display period of the first frame ends.

[0127] During the blanking period Blank of the first frame 1F, the operation process of the first-stage shift register unit is as follows.

[0128] In the fifth phase 5, since the first capacitor C1 stores data, the control node H holds the high level during the display period. The first clock signal terminal CLKA (connected to the seventh sub-clock signal line CLK7) and the third clock signal terminal CLKC (connected to the sixth sub-clock signal line CLK6) receive high-level signals, turning on the third transistor M3 and the fourth transistor M4. As a result, the high level of the third clock signal terminal CLKC can charge the first node Q and pull up the first node Q to a high level. The tenth transistor M10 is turned on under the control of the first node Q, pulling down the second node QB to a low level. At the same time, the fourteenth transistor M14 is also turned on under the control of the first clock signal terminal CLKA, further pulling down the second node QB.

[0129] In the sixth phase 6, the first clock signal terminal CLKA receives a low-level signal, turning off the fourth transistor M4. The fourth clock signal terminal CLKD (connected to the first sub-clock signal line CLK1) receives a high-level signal. To further pull up the potential of the first node Q for bootstrapping, the sixth transistor M6 and the seventh transistor M7 are turned on, and the high-level signal input by the fourth clock signal terminal CLKD can be output to the shift signal output terminal CR and the pixel signal output terminal OUT. For example, the signal output by the pixel signal output terminal OUT may be used to drive the sense transistor in the sub-pixel unit in the display panel to achieve external compensation.

[0130] At the same time, the second clock signal terminal CLKB of the second-stage shift register unit is connected to the sixth sub-clock signal line CLK6, and the blanking input signal terminal STU1 of the second-stage shift register unit is connected to the shift signal output terminal CR of the first-stage shift register unit. Therefore, the second transistor M2 in the second-stage shift register unit is turned on, pulling up the control node H<2> in the second-stage shift register unit to a high level.

[0131] In the seventh phase 7, after a high potential is fully written into the control node H<2> in the second-stage shift register unit, the sixth sub-clock signal line CLK6 inputs a low-level signal. At the same time, since the fourth clock signal terminal CLKD continuously inputs a high level, the shift signal output terminal CR and the pixel signal output terminal OUT of the first-stage shift register unit hold the output of the high-level signal. In this process, since the fourth transistor M4 always remains in the off state, leakage of the first node Q<1> through the fourth transistor M4 can be avoided.

[0132] In the eighth phase 8, that is, in the final phase of the blanking period, the fifth sub-clock signal line CLK_5 inputs a high-level signal. Since the second clock signal terminals CLKB of the odd-stage shift register units are all connected to the fifth sub-clock signal line CLK5, the reset of the control node H and the first node Q in all odd-stage shift register units can be completed. In particular, the first node Q of the first and third stages and the control node H of the first stage are reset. Since a positive drift may occur in the threshold voltage when a positive voltage is applied to the transistor, using the above method, the time for the control node H to hold the positive voltage is shortened, thereby shortening the time for positive drift to occur in the threshold voltage of the transistor and improving the reliability of the transistor.

[0133] Thus, the driving timing of the first frame ends.

[0134] During the display period of the second frame, the gate driving circuit 20 repeats the same operation as in the display period of the first frame, which will not be described repeatedly here.

[0135] During the blanking period of the second frame, for the second-stage shift register unit, since the third clock signal terminal CLKC is connected to the fifth sub-clock signal line CLK5, when the blanking period starts, the first clock signal terminal CLKA and the third clock signal terminal CLKA of the second-stage shift register unit input high-level signals, and the third transistor M3 and the fourth transistor M4 are turned on, and the high level input by the third clock signal terminal CLKC can charge the first node Q and pull up the first node Q to a high level. Then, when a high level is input to the second sub-clock signal line CLK2, the shift signal output terminal CR and the pixel signal output terminal OUT output high-level signals, and at the same time charge the control node H in the third-stage shift register unit. In the final phase of the blanking period of the second frame, the sixth sub-clock signal line CLK6 inputs a high-level signal, and since the second clock signal terminals CLKB of all even-stage shift register units are connected to the sixth sub-clock signal line CLK6, the reset of the control node H and the first node Q in all even-stage shift register units can be completed.

[0136] Thus, the driving timing of the second frame ends. For the driving of the gate driving circuit in more phases such as the subsequent third frame, fourth frame, fifth frame, etc., reference can be made to the above, and it will not be repeated here.

[0137] As described above, during the blanking period of each frame, the gate driving circuit outputs a driving signal used for the sense transistor in the sub-pixel unit in the display panel, and the driving signals are sequentially supplied row by row. For example, during the blanking period of the first frame, the gate driving circuit outputs a driving signal used for the sub-pixel unit in the first row of the display panel, and during the blanking period of the second frame, the gate driving circuit outputs a driving signal used for the sub-pixel unit in the second row of the display panel. Similarly, sequential compensation row by row is completed.

[0138] Hereinafter, while referring to the signal timing chart in FIG. 9, the operating principle of the gate driving circuit 20 when performing random compensation on the gate driving circuit 20 shown in FIG. 7 will be described. For example, for the shift register unit in the gate driving circuit 20 shown in FIG. 7, the shift register unit shown in FIG. 4 may be used.

[0139] During the display period of the first frame, the operating principle of the gate driving circuit is the same as the method when sequentially compensating in the above-described row unit, and only the differences will be described below. As shown in FIG. 9, when the pixel signal output terminal OUT<1> (i.e., the shift signal output terminal CR) of the first-stage shift register unit outputs a high-level signal, a high-level signal is also applied to the compensation selection control terminal OE. At this time, the control node H<1> of the first-stage shift register unit is charged to a high level. Next, since the output pulses of OUT<1> and OUT<2> overlap, the control node H<2> of the second-stage shift register unit is also charged to a high level.

[0140] In this way, during the display period of one frame, both the control node H<1> of the first-stage shift register unit and the control node H<2> of the second-stage shift register unit are charged to a high level. However, during the blanking period of one frame, for example, when it is necessary to output a driving signal for detecting the sub-pixel unit of the first row in the display panel during the frame, the following operations are performed during the blanking period of the first frame.

[0141] In the first phase T1, a high-level signal is input through the sixth sub-clock signal line CLK6, thereby discharging the control node H of the even-stage shift register unit, that is, eliminating the high potential of H<2> (for example, when it is necessary to detect the nth row in the frame, eliminating the high potential of the control node H in the (n - 1)th-stage and (n + 1)th-stage shift register units).

[0142] In the second phase T2, the seventh sub-clock signal line CLK7 (connected to the first clock signal terminal CLKA) inputs a high-level signal, the third clock signal terminal CLKC of the first-stage shift register unit holds the input of the high-level signal, the third transistor M3 and the fourth transistor M4 are turned on, and the charging of the first node Q is completed.

[0143] In the third phase T3, since the sixth sub-clock signal line CLK6 and the seventh sub-clock signal line CLK7 input low-level signals and the first sub-clock signal line CLK1 inputs a high-level signal, the shift signal output terminal and the pixel signal output terminal OUT output high-level signals. For example, the signal output from the pixel signal output terminal OUT may be used to drive the sense transistor in the sub-pixel unit of the first row in the display panel to achieve external compensation.

[0144] Then, the first sub-clock signal line CLK1 changes to a low-level signal, and correspondingly, the shift signal output terminal and the pixel signal output terminal OUT output low-level signals.

[0145] In the fourth phase T4, that is, in the final phase of the blanking period of the first frame, the fifth sub-clock signal line CLK5 inputs a high-level signal. Since the second clock signal terminals CLKB of all odd-stage shift register units are connected to the fifth sub-clock signal line CLK5, the reset of the control node H and the first node Q in all odd-stage shift register units can be completed. In particular, the first node Q and the control node H of the first-stage shift register unit are reset.

[0146] For example, when it is necessary to output a driving signal for detecting the sub-pixel unit of the second row in the display panel during the blanking period of the second frame, the following operations are performed in the second frame.

[0147] In the display phase of the second frame, the signal input by the compensation selection control terminal OE is made the same as the signal output by the pixel signal output terminal OUT<2> of the second-stage shift register unit (i.e., the shift signal output terminal CR). Since the output pulses of OUT<2>, OUT<1>, and the pixel signal output terminal OUT<3> of the third-stage shift register unit (not shown in FIG. 9) overlap, the control nodes H<1>, H<2>, and H<3> of the first-stage, second-stage, and third-stage shift register units are all charged to a high level under the control of the compensation selection control terminal OE. Since the first pole of the first transistor M1 in the first-stage shift register unit is connected to the shift signal output terminal CR of the first-stage shift register unit, after H<1> is charged to a high level, it is quickly pulled down by the low level of the shift signal output terminal CR (i.e., OUT<1>).

[0148] Regarding the operating principle during the blanking period of the second frame, reference can be made to the corresponding description during the blanking period of the first frame, which will not be repeated here.

[0149] Note that for easier illustration of the signal timing, in the above description of the operating principle of random compensation, the case of outputting a drive signal corresponding to the sub-pixel unit of the first row of the display panel during the blanking period of the first frame was used as an example for explanation. However, the present disclosure is not limited thereto. For example, in the timing simulation diagram shown in FIG. 11, when it is necessary to output a drive signal corresponding to the sub-pixel unit of the fifth row of the display panel during the blanking period of a certain frame, it is necessary to control so that the timing of the signal supplied to the compensation selection control terminal OE is the same as the signal of the shift signal output terminal CR<5> of the fifth-stage shift register unit. Here, the same timing of the two signals means that the time at the high level is synchronized, and it is not necessary for the amplitudes of the two signals to be the same. In FIG. 11, CR<4> and CR<6> respectively represent the shift signal output terminal of the fourth-stage shift register unit and the shift signal output terminal of the sixth-stage shift register unit.

[0150] As described above, by providing the compensation selection circuit 400 (the first transistor M1), when it is necessary to output a drive signal corresponding to the sub-pixel unit of the n-th row of the display panel during the blanking period of a certain frame, the signals supplied to the compensation selection control terminal OE and the signal of the shift signal output terminal CR of the n-th stage shift register unit need to be at the same timing, whereby random compensation can be realized, where n is an integer greater than 0.

[0151] As shown in FIG. 10, another embodiment of the present disclosure further provides a gate driving circuit 20. The difference between the gate driving circuit 20 shown in FIG. 10 and the gate driving circuit 20 shown in FIG. 7 is that, in addition to the first-stage shift register unit, the blanking input signal terminal STU1 and the display input signal terminal STU2 of the (n + 1)-th stage shift register unit are also connected to the shift signal output terminal CR of the n-th stage shift register unit, and in addition to the last-stage shift register unit, the display reset signal terminal STD of the n-th stage shift register unit is also connected to the shift signal output terminal CR of the (n + 1)-th stage shift register unit. The signal pulses output by the gate driving circuit 20 shown in FIG. 10 do not overlap with each other.

[0152] Embodiments of the present disclosure further provide a display device 1. As shown in FIG. 12, the display device 1 includes the gate driving circuit 20 provided by the embodiments of the present disclosure. The display device 1 further includes a display panel 40, and the display panel 40 includes an array composed of a plurality of sub-pixel units 410. For example, the display device 1 may further include a data driving circuit 30. The data driving circuit 30 is for providing a data signal to the pixel array. The gate driving circuit 20 is for providing a drive signal to the pixel array. For example, the drive signal may drive the scanning transistor and the sense transistor in the sub-pixel unit 410. The data driving circuit 30 is electrically connected to the sub-pixel unit 410 via a data line DL, and the gate driving circuit 20 is electrically connected to the sub-pixel unit 410 via a gate line GL.

[0153] Note that the display device 1 in this embodiment may be any product or component having a display function, such as a liquid crystal panel, a liquid crystal TV, a display, an OLED panel, an OLED TV, an electronic paper display, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, etc.

[0154] Regarding the technical effects of the display device 1 provided by the embodiments of the present disclosure, reference may be made to the corresponding descriptions regarding the gate drive circuit 20 in the above embodiments, and details will not be repeated here.

[0155] The embodiments of the present disclosure further provide a driving method 1300 that can be used to drive the shift register unit 10 provided by the embodiments of the present disclosure, and the driving method 1300 includes the following operations.

[0156] Step S1302 includes a first input phase in which, during the display period of one frame, the display input circuit 200 inputs a display signal to the first node Q in response to a display input signal, and a first output phase in which the output circuit 300 outputs a first output signal under the control of the level of the first node Q. For example, the first output signal may be used to drive and display the sub-pixel unit in the display panel.

[0157] Step S1304 includes a second input phase in which, during the blanking period of one frame, the blanking input circuit 100 inputs a blanking input signal to the control node H and inputs a blanking signal to the first node Q, and a second output phase in which the output circuit 300 outputs a second output signal under the control of the level of the first node Q. For example, the second output signal may be used to drive the sub-pixel unit in the display panel to perform external compensation. The composite output signal includes the first output signal and the second output signal.

[0158] In another embodiment, the driving method 1300 may further include, during the display period of one frame, the compensation selection circuit 40 charging the control node with the first output signal in response to the compensation selection control signal.

[0159] Embodiments of the present disclosure further provide a driving method 1400 that can be used to drive the gate driving circuit 20 provided by the embodiments of the present disclosure, and the driving method includes the following operations.

[0160] In step S1402, when the gate driving circuit 20 drives one display panel, during the display period of any one frame, the output terminal of the n-th stage shift register unit 10 outputs a first output signal, and the compensation selection circuit 400 in the n-th stage shift register unit 10 responds to the compensation selection control signal and charges the control node H in the n-th stage shift register unit 10 with the first output signal.

[0161] In step S1404, during the blanking period of one frame, the output terminal of the n-th stage shift register unit outputs a second output signal. The composite output signal includes the first output signal and the second output signal, and n is an integer greater than 0.

[0162] For a detailed description and technical effects of the driving method provided by the embodiments of the present disclosure, reference can be made to the description of the operating principles of the shift register unit 10 and the gate driving circuit 20 in the embodiments of the present disclosure, which will not be repeated here.

[0163] The above are only specific embodiments of the present disclosure. The scope of the claims of the present disclosure is not limited thereto, and shall be subject to the scope of the claims.

Description of Reference Numerals

[0164] 20 Gate driving circuit 30 Data driving circuit 100 Blanking input circuit 110 Charging sub-circuit 120 Memory sub-circuit 130 Separation sub-circuit 200 Display input circuit 300 Output circuit 400 Compensation selection circuit 500 Noise reduction circuit 600 First control circuit 700 Second control circuit 800 Third control circuit 900 Blanking reset circuit 1000 Display reset circuit

Claims

1. A shift register unit comprising a blanking input circuit, a display input circuit, an output circuit, and a compensation selection circuit, the blanking input circuit is arranged to input a blanking signal to a first node during a blanking period of one frame; the display input circuit is arranged to input a display signal to the first node in a display period of one frame in response to a display input signal; the output circuit is arranged to output a composite output signal to an output terminal under control of a level of the first node; The compensation selection circuit is electrically connected to the output terminal and is configured to charge a control node with the composite output signal in response to a compensation selection control signal, the shift register unit.

2. the composite output signal includes a first output signal and a second output signal; during a display period of the one frame, the output circuit is arranged to output the first output signal to the output terminal under control of a level of the first node; 2. The shift register unit of claim 1, wherein in a blanking period of the one frame, the output circuit is arranged to output the second output signal to the output terminal under control of a level of the first node.

3. 3. The shift register unit of claim 2, wherein during a display period of the one frame, the compensation selection circuit is configured to charge the control node with the first output signal in response to the compensation selection control signal.

4. the output terminal comprises a shift signal output terminal, the shift signal output terminal outputs the composite output signal, the compensation selection circuit comprises a first transistor; 4. The shift register unit of claim 3, wherein a gate of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first pole of the first transistor is connected to the shift signal output terminal to receive the composite output signal, and a second pole of the first transistor is connected to the control node.

5. The blanking input circuit includes: a charging subcircuit configured to input the blanking input signal to the control node in response to a second clock signal; 5. The shift register unit of claim 4, further comprising a storage subcircuit arranged to store the blanking input signal received by the charging subcircuit.

6. the charging subcircuit comprises a second transistor, a gate of the second transistor connected to a second clock signal terminal for receiving the second clock signal, a first pole of the second transistor connected to a blanking input signal terminal for receiving the blanking input signal, and a second pole of the second transistor connected to the control node; 6. The shift register unit of claim 5, wherein the storage sub-circuit comprises a first capacitor, a first pole of the first capacitor connected to the control node and a second pole of the first capacitor connected to a first voltage terminal to receive a first voltage.

7. the display input circuit comprises a fifth transistor; 2. The shift register unit of claim 1, wherein a gate of the fifth transistor is connected to a display input signal terminal to receive the display input signal, and a second pole of the fifth transistor is connected to the first node.

8. the output terminal further comprises a pixel signal output terminal, the pixel signal output terminal outputs the composite output signal, and the output circuit comprises a sixth transistor, a seventh transistor, and a second capacitor; a gate of the sixth transistor is connected to the first node, a first pole of the sixth transistor is connected to a fourth clock signal terminal to receive a fourth clock signal as the composite output signal, and a second pole of the sixth transistor is connected to the shift signal output terminal; a gate of the seventh transistor is connected to the first node, a first pole of the seventh transistor is connected to the fourth clock signal terminal to receive the fourth clock signal as the composite output signal, and a second pole of the seventh transistor is connected to the pixel signal output terminal; 5. The shift register unit of claim 4, wherein a first pole of the second capacitor is connected to the first node and a second pole of the second capacitor is connected to a second pole of the sixth transistor.

9. A shift register unit further comprising a noise reduction circuit and a first control circuit, the output terminal further comprises a pixel signal output terminal, the pixel signal output terminal outputs the composite output signal; the first control circuit is arranged to control a level of a second node under control of a level of the first node; 5. The shift register unit of claim 4, wherein the noise reduction circuit is arranged to reduce noise at the first node, the shift signal output terminal, and the pixel signal output terminal under control of a level of the second node.

10. the first control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor; a gate of the eighth transistor connected to a first pole and connected to a fourth voltage terminal to receive a fourth voltage, a second pole of the eighth transistor connected to the second node; a gate of the ninth transistor connected to a first pole and connected to a fifth voltage terminal to receive a fifth voltage, a second pole of the ninth transistor connected to the second node; 10. The shift register unit of claim 9, wherein a gate of the tenth transistor is connected to the first node, a first pole of the tenth transistor is connected to the second node, and a second pole of the tenth transistor is connected to a first voltage terminal and arranged to receive a first voltage.

11. the noise reduction circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; a gate of the eleventh transistor is connected to the second node, a first pole of the eleventh transistor is connected to the first node, and a second pole of the eleventh transistor is connected to a first voltage terminal to receive a first voltage; a gate of the twelfth transistor is connected to the second node, a first pole of the twelfth transistor is connected to the shift signal output terminal, and a second pole of the twelfth transistor is connected to the first voltage terminal to receive the first voltage; 10. The shift register unit of claim 9, wherein a gate of the thirteenth transistor is connected to the second node, a first pole of the thirteenth transistor is connected to the pixel signal output terminal, and a second pole of the thirteenth transistor is connected to a third voltage terminal to receive a third voltage.

12. A shift register unit further comprising a second control circuit, 10. The shift register unit of claim 9, wherein the second control circuit is arranged to control the level of the second node in response to a blanking control signal.

13. the second control circuit comprises a fourteenth transistor, and the blanking control signal comprises a first clock signal; 13. The shift register unit of claim 12, wherein a gate of the fourteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first pole of the fourteenth transistor is connected to the second node, and a second pole of the fourteenth transistor is connected to a first voltage terminal to receive a first voltage.

14. A shift register unit further comprising a third control circuit, 10. The shift register unit of claim 9, wherein the third control circuit is arranged to control a level of the second node in response to a display control signal.

15. the third control circuit comprises a fifteenth transistor, and the display control signal includes the display input signal; 15. The shift register unit of claim 14, wherein a gate of the fifteenth transistor is connected to a display input signal terminal to receive the display input signal, a first pole of the fifteenth transistor is connected to the second node, and a second pole of the fifteenth transistor is connected to a first voltage terminal to receive a first voltage.

16. A shift register unit further comprising a blanking reset circuit, 16. The shift register unit of claim 15, wherein the blanking reset circuit is arranged to reset the first node in response to a blanking reset signal.

17. the blanking reset circuit comprises a sixteenth transistor; 17. The shift register unit of claim 16, wherein a gate of the sixteenth transistor is connected to a second clock signal terminal to receive a second clock signal as the blanking reset signal, a first pole of the sixteenth transistor is connected to the first node, and a second pole of the sixteenth transistor is connected to a first voltage terminal to receive a first voltage.

18. A shift register unit further comprising a display reset circuit, 15. The shift register unit of claim 14, wherein the display reset circuit is arranged to reset the first node in response to a display reset signal.

19. the display reset circuit comprises a seventeenth transistor; 19. The shift register unit of claim 18, wherein a gate of the seventeenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first pole of the seventeenth transistor is connected to the first node, and a second pole of the seventeenth transistor is connected to a first voltage terminal to receive a first voltage.

20. a twenty-first transistor and a fourth leakage prevention transistor arranged to prevent leakage at the first node; the blanking input circuit comprises an isolation sub-circuit arranged to input the blanking signal to the first node under control of a level of the control node and a first clock signal; 2. The shift register unit of claim 1, wherein the isolation sub-circuit comprises a third transistor and a fourth transistor, a gate of the third transistor connected to the control node, a first pole of the third transistor receiving the blanking signal, a second pole of the third transistor connected to a first pole of the fourth transistor, a gate of the fourth transistor connected to a first clock signal terminal to receive the first clock signal, a second pole of the fourth transistor connected to a first pole of the fourth leakage prevention transistor, a gate of the fourth leakage prevention transistor connected to a first clock signal terminal to receive the first clock signal, a second pole of the fourth leakage prevention transistor connected to the first node, a first pole of the second-first transistor connected to a second voltage terminal, a gate of the second-first transistor connected to the first node, and a second pole of the second-first transistor connected to the first pole of the fourth leakage prevention transistor.

21. A gate drive circuit comprising a plurality of cascaded shift register units according to any one of claims 1 to 20.

22. A gate drive circuit comprising a first sub-clock signal line, a second sub-clock signal line, a third sub-clock signal line, and a fourth sub-clock signal line, When the shift register unit includes a fourth clock signal terminal, a fourth clock signal terminal of the (4n-3)-th shift register unit is connected to the first sub-clock signal line; a fourth clock signal terminal of the (4n-2)-th shift register unit is connected to the second sub-clock signal line; a fourth clock signal terminal of the (4n-1)-th shift register unit is connected to the third sub-clock signal line; a fourth clock signal terminal of the (4n)-th stage shift register unit is connected to the fourth sub-clock signal line; 22. The gate drive circuit of claim 21, wherein n is an integer greater than 0.

23. A gate drive circuit further comprising a fifth sub-clock signal line and a sixth sub-clock signal line, When the shift register unit includes a second clock signal terminal and a third clock signal terminal, a second clock signal terminal of the (2n-1)-th shift register unit is connected to the fifth sub-clock signal line, and a third clock signal terminal of the (2n-1)-th shift register unit is connected to the sixth sub-clock signal line; a second clock signal terminal of the 2n-th stage shift register unit is connected to the sixth sub-clock signal line, and a third clock signal terminal of the 2n-th stage shift register unit is connected to the fifth sub-clock signal line; 23. The gate drive circuit of claim 22, wherein n is an integer greater than 0.

24. When the shift register unit includes a blanking input signal terminal, a display input signal terminal, and a shift signal output terminal, The blanking input signal terminal of the (n+1)th shift register unit is connected to the shift signal output terminal of the (n)th shift register unit, The display input signal terminal of the (n+2)th shift register unit is connected to the shift signal output terminal of the (n)th shift register unit, 22. The gate drive circuit of claim 21, wherein n is an integer greater than 0.

25. A display device comprising the gate drive circuit according to any one of claims 21 to 24.

26. During the display period of one frame, a first input phase in which the display input circuitry is responsive to the display input signal to input the display signal to the first node; a first output phase in which the output circuit outputs a first output signal under control of a level of the first node; During the blanking period of one frame, a second input phase in which the blanking input circuit inputs the blanking input signal to the control node and inputs the blanking signal to the first node; a second output phase in which the output circuit outputs a second output signal under control of a level of the first node, 21. The method of claim 1, wherein the composite output signal comprises the first output signal and the second output signal.

27. 27. The driving method according to claim 26, further comprising: in a display period of one frame, the compensation selection circuit charges the control node with the first output signal in response to the compensation selection control signal.

28. When the gate driving circuit drives one display panel, During a display period of any one frame, an output terminal of an n-th stage shift register unit outputs a first output signal, a compensation selection circuit in the n-th stage shift register unit responds to the compensation selection control signal, and a control node in the n-th stage shift register unit is charged by the first output signal; In a blanking period of the one frame, an output terminal of the n-th stage shift register unit outputs a second output signal, 25. The method of claim 21, wherein the composite output signal includes the first output signal and the second output signal, and n is an integer greater than 0.

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