Display device and method of manufacturing display device

Abstract

To provide a display device with improved reliability.SOLUTION: A display device includes a substrate including a display area and a peripheral area outside the display area, a pixel circuit layer disposed in the display area on the substrate and including a thin film transistor and a plurality of insulating layers, a light emitting element layer disposed in the display area on the substrate and including a light emitting element electrically connected to the thin film transistor, an encapsulation layer disposed on the light emitting element layer, and a pattern part disposed in a portion of the peripheral area on the substrate and having an uneven structure on the upper surface thereof.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a display device and a method for manufacturing the display device.

Background Art

[0002] A display device is manufactured through process steps of forming a pixel circuit layer including a thin film transistor or the like, a light emitting element layer or the like on a substrate. In the manufacturing process of the display device that is sequentially performed, a protective film or the like is used for protecting the light emitting element layer or the like.

[0003] However, recently, the needs for display devices having various shapes have increased. Due to the protective film with limited shape processing, there is a limit in protecting display devices with various shapes. For this reason, a method for effectively protecting the display device in the display device manufacturing process has been studied.

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device with improved reliability.

[0005] Another object of the present invention is to provide a method for manufacturing a display device with improved reliability.

[0006] However, the object of the present invention is not limited to this, and can be variously extended without departing from the spirit and scope of the present invention.

Means for Solving the Problems

[0007] In order to achieve the object of the present invention described above, the display device according to the present invention includes a substrate including a display region and a peripheral region located outside the display region, a pixel circuit layer disposed in the display region on the substrate and including a thin film transistor and a plurality of insulating layers, a light emitting element layer disposed in the display region on the substrate and including a light emitting element electrically connected to the thin film transistor, a sealing layer disposed on the light emitting element layer, and a pattern portion disposed in a part of the peripheral region on the substrate and having an uneven structure on the upper surface.

[0008] The pattern portion includes a plurality of protruding portions spaced apart from each other and grooves defining the protruding portions.

[0009] The interval between adjacent protruding portions is 10 μm or more and 50 μm or less.

[0010] Each of the protruding portions has a rectangular shape in a cross section perpendicular to the substrate.

[0011] Each of the protruding portions has an inverted taper shape in a cross section perpendicular to the substrate.

[0012] The bottom surface of the groove has insulating properties.

[0013] The light emitting element includes a pixel electrode, a light emitting layer, and a common electrode. The common electrode extends from the display region to the peripheral region, and in the peripheral region, a part of the pattern portion overlaps a part of the common electrode.

[0014] In a region where the part of the pattern portion overlaps the part of the common electrode, the bottom surface of the groove is spaced apart from the upper surface of the common electrode in the upper direction.

[0015] The sealing layer includes a first inorganic sealing layer disposed on the light-emitting element layer, an organic sealing layer disposed on the first inorganic sealing layer, and a second inorganic sealing layer disposed on the organic sealing layer. At least one insulating layer among the plurality of insulating layers included in the pixel circuit layer, the first inorganic sealing layer, and the second inorganic sealing layer extends from the display region to the peripheral region. In the peripheral region, at least the uppermost layer of the at least one insulating layer defines the groove of the pattern portion.

[0016] The pattern portion is disposed corresponding to a corner portion of the display region.

[0017] The substrate further includes a pad region located on one side of the display region. The peripheral region includes a first peripheral region between the display region and the pad region, and a second peripheral region separated from the pad region. The pattern portion is disposed only in the second peripheral region among the peripheral regions.

[0018] The pattern portion is in contact with the edge of the substrate.

[0019] The pattern portion is separated outward from the display region and is continuously disposed from a first virtual line located within the peripheral region to a second virtual line located at the edge of the substrate.

[0020] The substrate further includes a first dam portion disposed in the peripheral region on the substrate, separated outward from the display region, and surrounding the display region. The pattern portion overlaps the first dam portion.

[0021] The substrate further includes a crack prevention portion disposed in the peripheral region on the substrate, separated outward from the first dam portion. The pattern portion further overlaps the crack prevention portion.

[0022] The substrate further includes a second dam portion disposed in the peripheral region on the substrate so as to be adjacent to the edge of the substrate, separated outward from the crack prevention portion. The pattern portion further overlaps the second dam portion.

[0023] It further includes an antireflection member disposed on the sealing layer.

[0024] In order to achieve the above-described other objects of the present invention, a display device according to the present invention includes a pixel circuit layer, a light-emitting element layer, and a sealing layer on a mother substrate including a plurality of cell regions each including a display region and a peripheral region located outside the display region, forms a pattern portion having an uneven structure on the upper surface in the peripheral region of each of the cell regions, provides a protective layer resin on the sealing layer and the pattern portion of each of the cell regions to form a protective layer, cuts out each of the cell regions, and removing the protective layer from each of the cut-out display panels.

[0025] At least one insulating layer among the plurality of insulating layers included in the pixel circuit layer and at least one inorganic sealing layer included in the sealing layer extends from the display region to the peripheral region, and forming the pattern portion includes partially etching the at least one insulating layer in the peripheral region to form a plurality of protruding portions spaced apart from each other and grooves defining the protruding portions.

[0026] Forming the protective layer includes providing ultraviolet light on the provided protective layer resin to cure the protective layer resin.

[0027] Forming the protective layer includes providing the protective layer resin such that an edge of the protective layer resin is located on the pattern portion.

[0028] It further includes providing an antireflection member on each of the display panels from which the protective layer has been removed.

Effects of the Invention

[0029] According to the present invention, in the process of manufacturing a display device, it is possible to prevent or reduce the remaining of a protective layer that is formed on a display panel and then removed later. Therefore, the reliability of the display device can be improved.

[0030] However, the effects of the present invention are not limited thereto, and can be variously extended without departing from the spirit and scope of the present invention.

Brief Description of the Drawings

[0031]

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Figure 21

BEST MODE FOR CARRYING OUT THE INVENTION

[0032] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components on the accompanying drawings.

[0033] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention.

[0034] As shown in FIG. 1, in one embodiment, the display device 10 displays an image in a third direction DR3 through a display surface defined by a first direction DR1 and a second direction DR2 that intersects the first direction DR1. The third direction DR3 is substantially parallel to the normal direction of the display surface. The display surface corresponds to the front surface (or, upper surface) of the display device 10.

[0035] The display device 10 includes a display area DA and a peripheral area PA. The image is displayed in the display area DA.

[0036] The peripheral area PA is located around the display area DA. The peripheral area PA is located outside the display area DA. For example, the peripheral area PA surrounds the display area DA on a plane.

[0037] The display device 10 includes a display panel 100 and an anti-reflection member 200. A plurality of pixels for generating the image are arranged in the display area DA of the display panel 100.

[0038] Each of the pixels includes a pixel circuit and a light-emitting element. The pixel circuit includes at least one thin-film transistor and at least one capacitor. The thin-film transistor generates a drive current and provides the generated drive current to the light-emitting element. The light-emitting element emits light based on the drive current. For example, the light-emitting element includes an organic light-emitting element, an inorganic light-emitting element, or a quantum dot light-emitting element, etc. The light emitted by each of the pixels is combined to generate the image.

[0039] The anti-reflection member 200 is disposed on the display panel 100. The anti-reflection member 200 reduces the reflection of light incident from the outside. That is, the anti-reflection member 200 reduces the external light reflectance of the display device 10. In one embodiment, the anti-reflection member 200 includes a polarizing layer, a phase plate, a cancellation interference structure, or a plurality of color filters, etc.

[0040] In one embodiment, a cover window (not shown) is disposed on the anti-reflection member 200. The cover window has light transmissivity.

[0041] FIG. 2 is a cross-sectional view taken along the line I-I' of FIG. 1.

[0042] Hereinafter, with reference to FIGS. 1 and 2, the display area DA of the display device 10 will be described in detail.

[0043] As shown in FIGS. 1 and 2, in one embodiment, the display panel 100 includes a substrate 110, a pixel circuit layer PCL, a light-emitting element layer EDL, and a sealing layer 140. The pixel circuit layer PCL includes a pixel circuit PC and a plurality of insulating layers 120, 132, 134, 136. The pixel circuit PC includes at least one thin-film transistor TR and at least one capacitor (not shown). The light-emitting element layer EDL includes a light-emitting element ED and a pixel definition layer 138. The light-emitting element ED includes a pixel electrode AE, a light-emitting layer EL, and a common electrode CE. The pixel circuit PC and the light-emitting element ED constitute a pixel PX. The antireflection member 200 is disposed on the sealing layer 140.

[0044] The substrate 110 is an insulating substrate formed of a transparent or opaque material. In one embodiment, the substrate 110 is a rigid substrate including substances such as glass and quartz. In other embodiments, the substrate 110 is a flexible substrate including plastic.

[0045] A buffer layer 120 is disposed on the substrate 110. The buffer layer 120 prevents impurities such as oxygen and moisture from diffusing onto the substrate 110 from the substrate 110. The buffer layer 120 includes an inorganic insulating substance such as a silicon compound or a metal oxide. For example, the buffer layer 120 includes silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), etc. These can be used alone or in combination with each other. The buffer layer 120 has a single-layer structure or a multilayer structure including a plurality of insulating layers.

[0046] A thin-film transistor TR is disposed on the buffer layer 120. The thin-film transistor TR includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0047] The active layer ACT is disposed on the buffer layer 120. The active layer ACT includes an oxide semiconductor, a silicon semiconductor, an organic semiconductor, etc. For example, the oxide semiconductor includes at least one oxide of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor includes amorphous silicon, polycrystalline silicon, etc. The active layer ACT includes a source region, a drain region, and a channel region located between the source region and the drain region.

[0048] A gate insulating layer 132 is disposed on the active layer ACT. The gate insulating layer 132 covers the active layer ACT on the buffer layer 120. The gate insulating layer 132 includes an inorganic insulating material.

[0049] The gate electrode GE is disposed on the gate insulating layer 132. The gate electrode GE overlaps the channel region of the active layer ACT. The gate electrode GE includes a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material. For example, the gate electrode GE may be made of gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum, an alloy containing silver, an alloy containing copper, an alloy containing molybdenum, aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. The gate electrode GE has a single-layer structure or a multilayer structure including a plurality of conductive layers.

[0050] An interlayer insulating layer 134 is disposed on the gate electrode GE. The interlayer insulating layer 134 covers the gate electrode GE on the gate insulating layer 132. The interlayer insulating layer 134 includes an inorganic insulating material.

[0051] A source electrode SE and a drain electrode DE are disposed on the interlayer insulating layer 134. The source electrode SE and the drain electrode DE are respectively connected to the source region and the drain region of the active layer ACT. The source electrode SE and the drain electrode DE include a conductive material.

[0052] On the source electrode SE and the drain electrode DE, a via insulating layer 136 is disposed. The via insulating layer 136 contains an organic insulating material. For example, the via insulating layer 136 includes photoresist, fluorine acrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, etc. These can be used alone or in combination with each other.

[0053] FIG. 2 shows that the pixel circuit layer PCL includes four insulating layers and three conductive layers, but it is not limited thereto. For example, the pixel circuit layer PCL can include five or more insulating layers and four or more conductive layers.

[0054] On the via insulating layer 136, a pixel electrode AE is disposed. The pixel electrode AE contains a conductive material. The pixel electrode AE has a single-layer structure or a multilayer structure including a plurality of conductive layers. The pixel electrode AE is connected to the drain electrode DE through a contact hole formed in the via insulating layer 136. Thereby, the pixel electrode AE is electrically connected to the thin film transistor TR.

[0055] On the pixel electrode AE, a pixel defining layer 138 is disposed. The pixel defining layer 138 covers the peripheral portion of the pixel electrode AE and defines a pixel opening that exposes the central portion of the pixel electrode AE. The pixel defining layer 138 contains an organic insulating material.

[0056] On the pixel electrode AE, a light emitting layer EL is disposed. The light emitting layer EL is disposed within the pixel opening of the pixel defining layer 138. The light emitting layer EL includes at least one of an organic light emitting material and quantum dots.

[0057] In one embodiment, the organic light-emitting substance includes a low-molecular organic compound or a high-molecular organic compound. Examples of the low-molecular organic compound include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc. Examples of the high-molecular organic compound include poly(3,4-ethylenedioxythiophene), polyaniline, poly-phenylenevinylene, polyfluorene, etc., but are not limited thereto. These can be used alone or in combination with each other.

[0058] In one embodiment, the quantum dot includes a core containing a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and combinations thereof. In one embodiment, the quantum dot has a core-shell structure including the core and a shell surrounding the core. The shell serves as a protective layer for preventing chemical modification of the core and maintaining semiconductor characteristics, and as a charging layer for imparting electrophoretic characteristics to the quantum dot.

[0059] A common electrode CE is disposed on the light-emitting layer EL. The common electrode CE is also disposed on the pixel defining layer 138. The common electrode CE contains a conductive substance. The pixel electrode AE, the light-emitting layer EL, and the common electrode CE constitute a light-emitting element ED. The light-emitting element ED further includes various functional layers (for example, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc.) disposed between the pixel electrode AE and the light-emitting layer EL, or between the light-emitting layer EL and the common electrode CE.

[0060] A sealing layer 140 is disposed on the common electrode CE. The sealing layer 140 includes at least one inorganic sealing layer and at least one organic sealing layer. In one embodiment, the sealing layer 140 includes a first inorganic sealing layer 142 disposed on the common electrode CE, an organic sealing layer 144 disposed on the first inorganic sealing layer 142, and a second inorganic sealing layer 146 disposed on the organic sealing layer 144. The organic sealing layer 144 covers the entire display area DA. Although not shown in the drawings, the display panel 100 may further include various functional layers (for example, a touch sensing layer, a color filter layer, a light condensing layer, etc.) disposed on the sealing layer 140.

[0061] The anti-reflection member 200 is disposed on the display panel 100. The anti-reflection member 200 is disposed on the sealing layer 140. The anti-reflection member 200 is disposed on the second inorganic sealing layer 146. For example, the anti-reflection member 200 is attached to the display panel 100 by an adhesive member. The adhesive member includes an optical clear adhesive (OCA), a pressure sensitive adhesive (PSA), a photocurable resin, a thermosetting resin, etc.

[0062] FIG. 3 is a plan view showing an example of the display panel included in the display device of FIG. 1.

[0063] As shown in FIGS. 1 and 3, the display panel 100 includes a display area DA, a peripheral area PA, and a pad area PDA. A plurality of pixels PX are disposed in the display area DA. For example, the pixels PX are arranged in a matrix along a first direction DR1 and a second direction DR2.

[0064] The peripheral area PA is located outside the display area DA. For example, the peripheral area PA surrounds the display area DA on a plane.

[0065] The pad region PDA is disposed on at least one side of the display region DA. The pad region PDA is separated from the display region DA. In the pad region PDA, a pad portion PD electrically connected to a driving unit (e.g., a data driving unit, a scan driving unit, etc.) is disposed. The driving unit provides various driving signals for driving the pixels PX, such as a driving voltage, a gate signal, a data signal, etc., to the display region DA. Although FIG. 3 shows that the pad region PDA is disposed only on one side of the display region DA, it is not limited thereto. For example, the pad region PDA can be further disposed in other portions outside the display region DA.

[0066] The peripheral region PA includes a first peripheral region PA1 and a second peripheral region PA2. The first peripheral region PA1 is a region located between the display region DA and the pad region PDA. The second peripheral region PA2 is a region located outside the display region DA and separated from the pad region PDA. For example, the second peripheral region PA2 refers to the remaining region of the peripheral region PA surrounding the display region DA excluding the first peripheral region PA1 located between the display region DA and the pad region PDA. As a specific example, in the plan view of FIG. 3, the first peripheral region PA1 is a region adjacent to the lower side of the display region DA, and the second peripheral region PA2 is a region adjacent to the left side, upper side, and right side of the display region DA.

[0067] The display panel 100 includes a pattern portion PP disposed in the peripheral region PA. The pattern portion PP is a structure having an uneven structure on its upper surface. The pattern portion PP facilitates the removal of a protective layer formed on the display panel 100 and then removed therefrom (see FIG. 21). This will be described in detail later.

[0068] The pattern portion PP is disposed in a part of the peripheral region PA. In one embodiment, the pattern portion PP is disposed only in the second peripheral region PA2 excluding the first peripheral region PA1 in the peripheral region PA.

[0069] In one embodiment, as shown in FIG. 3, the pattern portion PP is disposed only in a part of the second peripheral region PA2 corresponding to the corner portion of the display region DA. For example, among the four corner portions of the display region DA, the pattern portion PP is disposed corresponding to two corner portions (the upper left corner and the upper right corner in FIG. 3) that are not adjacent to the pad region PDA. However, the present invention is not limited to this, and the pattern portion PP can also be disposed corresponding to at least one of the four corner portions of the display region DA, respectively.

[0070] FIG. 4 is a plan view showing another example of the display panel included in the display device of FIG. 1.

[0071] As shown in FIG. 4, in one embodiment, the pattern portion PP can also be disposed entirely in the second peripheral region PA2 corresponding to the edge of the display region DA. For example, among the edges of the display region DA, the pattern portion PP is disposed corresponding to the left edge, the upper edge, and the right edge that are not adjacent to the pad region PDA.

[0072] FIG. 5 is a cross-sectional view taken along the line II-II' of FIG. 3. FIG. 6 is a cross-sectional view showing an example taken along the line III-III' of FIG. 3.

[0073] Hereinafter, with reference to FIGS. 5 and 6, the peripheral region PA of the display panel 100 will be described in detail.

[0074] For example, FIG. 5 shows a part of the second peripheral region PA2 where the pattern portion PP is not disposed, and FIG. 6 shows another part of the second peripheral region PA2 where the pattern portion PP is disposed. First, with reference to FIG. 5, a part of the second peripheral region PA2 where the pattern portion PP is not disposed will be described.

[0075] As shown in FIGS. 3 and 5, the display panel 100 further includes a power transmission wiring 150, a first dam portion 162, a second dam portion 164, and a crack prevention portion 172 disposed in the peripheral region PA.

[0076] At least one insulating layer among the plurality of insulating layers included in the pixel circuit layer PCL described with reference to FIG. 2 and the inorganic sealing layer included in the sealing layer 140 extends from the display area DA to the peripheral area PA including the second peripheral area PA2. That is, at least one insulating layer among the buffer layer 120, the gate insulating layer 132, the interlayer insulating layer 134, the via insulating layer 136, the first inorganic sealing layer 142, and the second inorganic sealing layer 146 extends from the display area DA to the peripheral area PA. For example, as shown in FIG. 5, the buffer layer 120, the first inorganic sealing layer 142, and the second inorganic sealing layer 146 extend to the edge 110e of the substrate 110, and the gate insulating layer 132 and the interlayer insulating layer 134 extend to the crack prevention portion 172 located between the display area DA and the edge 110e of the substrate 110. However, the present invention is not limited thereto, and the arrangement structure of the insulating layer in the peripheral area PA can be variously deformed.

[0077] The power transmission wiring 150 is disposed in the peripheral area PA on the substrate 110. For example, the power transmission wiring 150 is disposed in the second peripheral area PA2 on the substrate 110. The power transmission wiring 150 is separated outward from the display area DA.

[0078] In one embodiment, the common electrode CE included in the light-emitting element layer EDL described with reference to FIG. 2 extends from the display area DA to the second peripheral area PA2. For example, the common electrode CE extends to the crack prevention portion 172. A part of the common electrode CE extending to the second peripheral area PA2 is electrically connected to the power transmission wiring 150. Thereby, the common electrode CE is transmitted with the low power supply voltage ELVSS from the power transmission wiring 150.

[0079] The first dam portion 162 is disposed in the peripheral area PA on the substrate 110. The first dam portion 162 is disposed in the first peripheral area PA1 and the second peripheral area PA2 on the substrate 110. For example, in a plane, the first dam portion 162 is separated outward from the display area DA and has a shape surrounding the entire display area DA. Of course, in some sections, the first dam portion 162 can have a discontinuous shape.

[0080] The second dam portion 164 is disposed in the peripheral region PA on the substrate 110. The second dam portion 164 is disposed in the first peripheral region PA1 and the second peripheral region PA2 on the substrate 110. For example, in a plane, the second dam portion 164 is spaced apart from the first dam portion 162 outward and has a shape surrounding the first dam portion 162 as a whole. Of course, in some sections, the second dam portion 164 can also have a discontinuous shape.

[0081] The first dam portion 162 and the second dam portion 164 each have a multilayer structure in which a plurality of layers are stacked. For example, as shown in FIG. 5, the first dam portion 162 includes a first layer 162a and a second layer 162b, and the second dam portion 164 includes a first layer 164a, a second layer 164b, and a third layer 164c. For example, the first layer 162a of the first dam portion 162 and the first layer 164a of the second dam portion 164 can be formed substantially simultaneously with the via insulating layer 136 in the display region DA. The second layer 162b of the first dam portion 162 and the second layer 164b of the second dam portion 164 are formed substantially simultaneously with the pixel defining layer 138 in the display region DA. The third layer 164c of the second dam portion 164 can be formed substantially simultaneously with a spacer (not shown) in the display region DA. However, the present invention is not limited thereto.

[0082] The first dam portion 162 and the second dam portion 164 are disposed in the display region DA and can prevent the overflow of the organic encapsulation layer 144 covering the light emitting element layer EDL.

[0083] The crack prevention portion 172 is disposed in the peripheral region PA on the substrate 110. For example, the crack prevention portion 172 is disposed in the first peripheral region PA1 and the second peripheral region PA2 on the substrate 110. For example, in a plane, the crack prevention portion 172 is spaced apart from the second dam portion 164 outward and has a shape surrounding the second dam portion 164 as a whole. Of course, in some sections, the crack prevention portion 172 can also have a discontinuous shape.

[0084] The crack prevention portion 172 includes at least one inorganic insulating layer. The crack prevention portion 172 is separated outward from at least one insulating layer that extends into the peripheral region PA including the second peripheral region PA2 among the inorganic insulating layers included in the pixel circuit layer PCL. For example, as shown in FIG. 5, the gate insulating layer 132 and the interlayer insulating layer 134 extend from the display region DA into the peripheral region PA. The crack prevention portion 172 is separated outward from the gate insulating layer 132 and the interlayer insulating layer 134 that extend into the peripheral region PA. For example, the crack prevention portion 172 is formed by removing a part of the gate insulating layer 132 and the interlayer insulating layer 134. That is, the first layer 172a of the crack prevention portion 172 is formed substantially simultaneously with the gate insulating layer 132, and the second layer 172b is formed substantially simultaneously with the interlayer insulating layer 134. For example, as shown in FIG. 5, a plurality of crack prevention portions 172 can also be provided.

[0085] In one embodiment, a cover layer 174 is disposed on the crack prevention portion 172. The cover layer 174 covers the crack prevention portion 172 and fills a transmission prevention groove formed on at least one side of the crack prevention portion 172. The cover layer 174 includes an organic insulating material. For example, the cover layer 174 can be formed substantially simultaneously with the via insulating layer 136 in the display region DA.

[0086] In one embodiment, the first inorganic sealing layer 142 and the second inorganic sealing layer 146 extend from the display region DA into the peripheral region PA including the second peripheral region PA2. For example, the first inorganic sealing layer 142 and the second inorganic sealing layer 146 extend to the edge 110e of the substrate 110. In the peripheral region PA, the first inorganic sealing layer 142 and the second inorganic sealing layer 146 cover the common electrode CE, the first dam portion 162, the second dam portion 164, and the cover layer 174.

[0087] On the one hand, although FIG. 5 shows that the second inorganic encapsulation layer 146 is the uppermost layer in the second peripheral region PA2, the present invention is not limited thereto. For example, in at least a partial region of the second peripheral region PA2, the second inorganic encapsulation layer 146 may be omitted, and another insulating layer disposed below the second inorganic encapsulation layer 146 may be the uppermost layer (see FIG. 11). For example, in at least a partial region of the second peripheral region PA2, another insulating layer (e.g., a touch insulating layer, etc.) disposed above the second inorganic encapsulation layer 146 may be the uppermost layer.

[0088] Next, with reference to FIG. 6, a partial region of the second peripheral region PA2 where the pattern portion PP is disposed will be described.

[0089] As shown in FIGS. 3 and 6, the pattern portion PP of the display panel 100 is disposed in a part of the second peripheral region PA2 on the substrate 110. The pattern portion PP is a structure having an uneven structure on its upper surface.

[0090] The pattern portion PP is formed by removing a part of at least one insulating layer extending into the second peripheral region PA2. That is, a part of the upper side of an insulating structure located in the second peripheral region PA2 and having at least one insulating layer laminated thereon is removed, and the portion having an uneven structure on its upper surface is defined as the pattern portion PP. For example, FIG. 6 shows that a part of the upper side of an insulating structure in which the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 are laminated is removed from the second peripheral region PA2 to form the pattern portion PP, but the present invention is not limited thereto.

[0091] FIG. 7 is a perspective view showing an example of the A region in FIG. 6.

[0092] As shown in FIGS. 6 and 7, the pattern portion PP includes a plurality of protruding portions PRT spaced apart from each other and grooves GV that define the protruding portions PRT. For example, the plurality of protruding portions PRT are arranged spaced apart from each other along a first direction DR1 and a second direction DR2. The grooves GV define the plurality of protruding portions PRT. That is, on a plane, the grooves GV surround the plurality of protruding portions PRT respectively. For example, in the insulating structure located in the second peripheral region PA2, a portion where an upper part is removed is defined as the groove GV, and the remaining part where the upper part is not removed is defined as the protruding portion PRT. Among the plurality of insulating layers included in the pixel circuit layer PCL and the inorganic encapsulation layer included in the encapsulation layer 140, at least the uppermost layer (for example, the second inorganic encapsulation layer 146) of at least one insulating layer extending in the second peripheral region PA2 can define the groove GV in the second peripheral region PA2.

[0093] The pattern portion PP allows a protective layer formed on the display panel 100 to be easily removed after being formed on the display panel 100 (see FIG. 21). For example, the protective layer can be formed by providing a protective layer resin on the display panel 100 by inkjet printing or the like and curing the provided protective layer resin. The protective layer resin is provided on the display panel 100 such that the edge of the protective layer resin is located on the pattern portion PP. Here, since the pattern portion PP includes protruding portions PRT spaced apart from each other, the contact angle of the protective layer resin is improved. That is, compared with a comparative example in which the pattern portion PP is not formed, the thickness of the edge portion of the protective layer is formed relatively thick, and thus, the protective layer can be easily removed from the display panel 100. Therefore, it is possible to prevent or reduce the remaining of the protective layer on the display panel 100, and the reliability of the display device 10 can be improved.

[0094] In one embodiment, the distance D between adjacent protruding portions PRT is about 10 μm to 50 μm. If the distance D between adjacent protruding portions PRT is less than 10 μm, the effect of improving the contact angle of the protective layer resin does not appear. If the distance D between adjacent protruding portions PRT is greater than 50 μm, the effect of improving the contact angle of the protective layer resin decreases. Therefore, it is desirable that the distance D between adjacent protruding portions PRT is 10 μm or more and 50 μm or less. More desirably, the distance D between adjacent protruding portions PRT is 25 μm or more and 50 μm or less.

[0095] In one embodiment, as shown in FIG. 7, each protruding portion PRT has a rectangular shape in a cross section perpendicular to the substrate 110. For example, an upper part of the insulating structure located in the second peripheral region PA2 is removed by dry etching. In this case, each protruding portion PRT can have a substantially rectangular shape in a cross section perpendicular to the substrate 110.

[0096] FIG. 8 is a perspective view showing another example of the A region in FIG. 6.

[0097] As shown in FIG. 8, in one embodiment, each protruding portion PRT has an inverted taper shape in a cross section perpendicular to the substrate 110, where the upper side is larger than the bottom side. That is, the groove GV has an undercut shape in cross section. When each protruding portion PRT has an inverted taper shape in a cross section perpendicular to the substrate 110, the effect of improving the contact angle of the protective layer resin is further increased. For example, the process conditions of the dry etching are appropriately adjusted so that each protruding portion PRT has an inverted taper shape in a cross section perpendicular to the substrate 110. For example, an upper part of the insulating structure located in the second peripheral region PA2 can also be removed by wet etching.

[0098] Referring again to FIGS. 6 and 7, the thickness T of each protrusion PRT can be determined in various ways. The thickness T of the protrusion PRT can be defined as the distance between the upper surface of the protrusion PRT and the bottom surface of the groove GV. That is, the thickness T of the protrusion PRT is the same as the depth of the groove GV. The insulating structure located in the second peripheral region PA2 has a conductive layer disposed below it (for example, in a range that does not expose the common electrode CE in FIG. 6, a part of the upper side is removed. That is, in the second peripheral region PA2, even if a part of the upper side of the insulating structure is removed to form the pattern portion PP, the pattern portion PP can cover the conductive layer disposed below it.

[0099] The bottom surface of the groove GV has insulating properties. That is, the bottom surface of the groove GV is a part of the insulating layer extending in the second peripheral region PA2. For example, as shown in FIG. 6, the bottom surface of the groove GV is a part of the first inorganic sealing layer 142 extending in the second peripheral region PA2, but the present invention is not limited thereto.

[0100] The pattern portion PP overlaps at least one conductive layer disposed in the second peripheral region PA2 in the third direction DR3. For example, as shown in FIG. 6, a part of the pattern portion PP overlaps a part of the common electrode CE located in the second peripheral region PA2 in the third direction DR3. In the region where the part of the pattern portion PP and the part of the common electrode CE overlap, the bottom surface of the groove GV is separated from the upper surface of the common electrode CE in the third direction DR3, which is the upward direction. That is, the common electrode CE is covered by the pattern portion PP. Thereby, the pattern portion PP can prevent impurities such as oxygen and moisture from penetrating into the common electrode CE.

[0101] For example, as shown in FIG. 6, the thickness of each protrusion PRT is greater than the thickness of the second inorganic sealing layer 146 and less than the sum of the thicknesses of the first inorganic sealing layer 142 and the second inorganic sealing layer 146. In this case, the bottom surface of the groove GV is a part of the first inorganic sealing layer 142 extending in the second peripheral region PA2.

[0102] FIG. 9 is a cross-sectional view showing another example along line III-III' of FIG. 3.

[0103] For example, as shown in FIG. 9, the thickness of each protrusion PRT is smaller than the thickness of the second inorganic sealing layer 146. In this case, the bottom surface of the groove GV is a part of the second inorganic sealing layer 146 extending into the second peripheral region PA2.

[0104] However, the thickness of each protrusion PRT shown in FIGS. 6 and 9 is merely illustrative. As described above, the thickness of each protrusion PRT can be variously deformed within a range that does not expose the conductive layer where the pattern portion PP is disposed at the lower part.

[0105] Referring back to FIGS. 3 and 6, a first virtual line VL1 and a second virtual line VL2 are defined in the second peripheral region PA2 of the display panel 100.

[0106] The first virtual line VL1 is away from the display area DA towards the outside. For example, the first virtual line VL1 is adjacent to the corner of the display area DA and has a "┌" shape (a broken line shape) on the plane.

[0107] The second virtual line VL2 is away from the first virtual line VL1 towards the outside. For example, the second virtual line VL2 is adjacent to the corner of the substrate 110 and has a "┌" shape (a broken line shape) on the plane.

[0108] The pattern portion PP is continuously disposed from the first virtual line VL1 to the second virtual line VL2 defined on the second peripheral region PA2. That is, among a part of the insulating structure overlapping the region between the first virtual line VL1 and the second virtual line VL2, the part where the upper part is removed by the etching process is defined as the groove GV, and the remaining part where the upper part is not removed is defined as the protrusion PRT.

[0109] In one embodiment, as shown in FIG. 6, the first virtual line VL1 is located between the display area DA and the first dam portion 162. The second virtual line VL2 is separated from the outside of the crack prevention portion 172. In this case, the pattern portion PP overlaps the first dam portion 162, the second dam portion 164, the crack prevention portion 172, and the cover layer 174. The levels of the upper surfaces of at least some of the plurality of protrusions PRT are different from each other. The level of the bottom surface of the groove GV is different from each other depending on the position.

[0110] In one embodiment, although not shown in the drawings, the first virtual line VL1 can also be located between the second dam portion 164 and the crack prevention portion 172. The second virtual line VL2 is separated from the outside of the crack prevention portion 172. In this case, the pattern portion PP overlaps the crack prevention portion 172 and the cover layer 174 and does not overlap the first dam portion 162 and the second dam portion 164. The levels of the upper surfaces of at least some of the plurality of protrusions PRT are different from each other. The level of the bottom surface of the groove GV is different from each other depending on the position.

[0111] In one embodiment, although not shown in the drawings, the first virtual line VL1 is located outside the crack prevention portion 172. The second virtual line VL2 is located outside the first virtual line VL1. In this case, the pattern portion PP does not overlap the first dam portion 162, the second dam portion 164, the crack prevention portion 172, and the cover layer 174. The levels of the upper surfaces of the plurality of protrusions PRT are the same. The level of the bottom surface of the groove GV is the same.

[0112] In one embodiment, as shown in FIG. 6, the second virtual line VL2 is located at the edge 110e of the substrate 110. In this case, the pattern portion PP is in contact with the edge 110e of the substrate 110.

[0113] FIG. 10 is a cross-sectional view showing another example along the line III-III' of FIG. 3.

[0114] In one embodiment, as shown in FIG. 10, the second virtual line VL2 is separated inward from the edge 110e of the substrate 110. In this case, the pattern portion PP is separated inward from the edge 110e of the substrate 110.

[0115] FIGS. 11 and 12 are cross-sectional views of a display panel according to an embodiment of the present invention.

[0116] Hereinafter, the display panel 100b in FIGS. 11 and 12 will be described, focusing on the differences from the display panel 100 described with reference to FIGS. 6 and 7, and overlapping descriptions will be omitted or simplified.

[0117] FIG. 11 corresponds to FIG. 5, and FIG. 12 corresponds to FIG. 6. For example, FIG. 11 shows a part of the second peripheral region PA2 where the pattern portion PP is not arranged, and FIG. 12 shows another part of the second peripheral region PA2 where the pattern portion PP is arranged.

[0118] As shown in FIG. 11, at least one insulating layer among the plurality of insulating layers included in the pixel circuit layer PCL and the inorganic sealing layer included in the sealing layer 140 extends from the display area DA to the peripheral area PA including the second peripheral area PA2. For example, the buffer layer 120 extends to the edge 110e of the substrate 110, and the gate insulating layer 132, the interlayer insulating layer 134, the first inorganic sealing layer 142, and the second inorganic sealing layer 146 extend to the crack prevention portion 172 located between the display area DA and the edge 110e of the substrate 110. For example, the cover layer 174 covers the edges of the gate insulating layer 132 and the interlayer insulating layer 134. The edges of the first inorganic sealing layer 142 and the second inorganic sealing layer 146 are disposed on the cover layer 174. A part of the upper surface of the cover layer 174 is not covered by the first and second inorganic sealing layers 142 and 146 and is exposed.

[0119] As shown in FIG. 12, the pattern portion PP is disposed in a part of the second peripheral region PA2 on the substrate 110. The pattern portion PP is a structure having an uneven structure on its upper surface.

[0120] The pattern portion PP is formed by removing a part of at least one insulating layer extending into the second peripheral region PA2. That is, a part of the upper side of the insulating structure located in the second peripheral region PA2 and having at least one insulating layer laminated thereon is removed, and the portion having an uneven structure on the upper surface is defined as the pattern portion PP.

[0121] In the insulating structure located in the second peripheral region PA2, the portion where a part of the upper side is removed is defined as the groove GV, and the remaining portion where a part of the upper side is not removed is defined as the protrusion PRT. For example, a part of the upper side of insulating layers different from each other depending on the position can be removed to define the groove GV. For example, at least a part of the plurality of protrusions PRT includes insulating layers different from each other. For example, the bottom surface of the groove GV is a part of insulating layers different from each other depending on the position.

[0122] In the first region between the first virtual line VL1 and the edges of the first and second inorganic sealing layers 142 and 146, a part of the upper sides of the first and second inorganic sealing layers 142 and 146 is removed, and the groove GV can be defined. The bottom surface of the groove GV is a part of the first inorganic sealing layer 142.

[0123] In the region between the edges of the first and second inorganic sealing layers 142 and 146 and the outer edge of the cover layer 174, a part of the upper side of the cover layer 174 is removed, and the groove GV can be defined. The bottom surface of the groove GV is a part of the cover layer 174.

[0124] In the region between the outer edge of the cover layer 174 and the second virtual line VL2, a part of the upper side of the buffer layer 120 is removed, and the groove GV can be defined. The bottom surface of the groove GV is a part of the buffer layer 120.

[0125] FIG. 13 and FIG. 14 are cross-sectional views of a display panel according to an embodiment of the present invention.

[0126] Hereinafter, the display panel 100c in FIGS. 13 and 14 will be described centering on the differences from the display panel 100 described with reference to FIGS. 6 and 7, and duplicate descriptions will be omitted or simplified.

[0127] FIG. 13 corresponds to FIG. 5, and FIG. 14 corresponds to FIG. 6. For example, FIG. 13 shows a part of the second peripheral region PA2 where the pattern part PP is not arranged, and FIG. 14 shows another part of the second peripheral region PA2 where the pattern part PP is arranged.

[0128] As shown in FIGS. 13 and 14, the display panel 100c further includes a third dam part 180 disposed in the second peripheral region PA2.

[0129] The third dam part 180 is disposed in the second peripheral region PA2 on the substrate 110. The third dam part 180 is away from the crack prevention part 172 outward. The third dam part 180 is disposed adjacent to the edge 110e of the substrate 110. For example, the third dam part 180 can be formed substantially simultaneously with the via insulating layer 136 or the pixel definition layer 138 of the display region DA. The third dam part 180 can prevent the overflow of the protective layer resin.

[0130] In one embodiment, the first inorganic sealing layer 142 and the second inorganic sealing layer 146 cover the third dam part 180. In other embodiments, the first inorganic sealing layer 142 and the second inorganic sealing layer 146 extend to the inside of the third dam part 180 and do not cover the third dam part 180.

[0131] The second virtual line VL2 is defined outside the third dam part 180. In this case, the pattern part PP overlaps the third dam part 180. That is, the pattern part PP including the protrusion PRT and the groove GV can be located on the upper part of the third dam part 180. Thereby, the protective layer can be easily removed from the display panel 100c.

[0132] FIGS. 15 to 21 are diagrams showing a manufacturing method of a display device according to an embodiment of the present invention.

[0133] Hereinafter, with reference to FIGS. 15 to 21, a manufacturing method of the display device 10 described with reference to FIGS. 1 to 14 will be described, and duplicate explanations will be omitted or simplified.

[0134] FIG. 15 is a plan view showing a mother substrate 110p on which a plurality of preliminary display panels 100p are formed. Each of the plurality of preliminary display panels 100p in FIG. 15 corresponds to any one of the display panels 100, 100b, 100c described with reference to FIGS. 1 to 14. FIGS. 16 to 21 are cross-sectional views showing the process from forming the protective layer PT on each preliminary display panel 100p to removing it subsequently. Each of FIGS. 16 to 21 corresponds to a cross-sectional view taken along the line IV-IV' of FIG. 15.

[0135] As shown in FIGS. 15 to 21, first, a plurality of preliminary display panels 100p are formed on the mother substrate 110p. The mother substrate 110p includes a plurality of cell regions CA spaced apart from each other. Each cell region CA includes a display region DA, a peripheral region located outside the display region DA, and a pad region. The peripheral region includes a first peripheral region located between the display region DA and the pad region, and a second peripheral region PA2 excluding the first peripheral region. A preliminary display panel 100p is formed in each of the plurality of cell regions CA on the mother substrate 110p.

[0136] In the display region DA included in each cell region CA, the pixel circuit layer PCL, the light-emitting element layer EDL, and the sealing layer 140 of FIG. 5 are formed. The organic sealing layer 144 included in the sealing layer 140 covers the entire display region DA. In the peripheral region included in each cell region CA, the power transmission wiring 150, the first dam portion 162, the second dam portion 164, and the crack prevention portion 172 of FIG. 5 are formed. At least one insulating layer among the plurality of insulating layers included in the pixel circuit layer PCL and at least one insulating layer among the at least one inorganic sealing layer included in the sealing layer 140 extend from the display region DA to the peripheral region including the second peripheral region PA2.

[0137] Next, in the second peripheral region PA2 included in each cell region CA, a pattern portion PP having an uneven structure on its upper surface is formed. The pattern portion PP has a plurality of protruding portions PRT and grooves GV that define the protruding portions PRT.

[0138] The pattern portion PP is formed by partially etching an insulating structure in which the at least one insulating layer is laminated in the second peripheral region PA2. That is, in the second peripheral region PA2, an upper part of the insulating structure is removed, and a portion having an uneven structure on its upper surface is defined as the pattern portion PP. For example, a portion where an upper part of the insulating structure is removed is defined as the groove GV, and the remaining portion where the upper part is not removed is defined as the protruding portion PRT.

[0139] The pixel circuit layer PCL, the light-emitting element layer EDL, the sealing layer, the power transmission wiring, the first dam portion 162, the second dam portion 164, the crack prevention portion, and the pattern portion PP formed in each cell region CA on the mother substrate 110p constitute the preliminary display panel 100p.

[0140] Next, a protective layer PT is formed on each cell region CA. First, as shown in FIG. 17, a protective layer resin P-PT is provided on each cell region CA. The protective layer resin P-PT is provided on the sealing layer and the pattern portion PP formed in each cell region CA.

[0141] The protective layer resin P-PT is provided in a liquid type on each cell region CA. For example, the protective layer resin P-PT is provided by inkjet printing or coating. For example, the protective layer resin P-PT contains an acrylic resin, but this is an example and the present invention is not limited thereto. The protective layer resin P-PT is provided so as to cover the entire organic sealing layer 144.

[0142] As shown in FIG. 18, the protective layer resin P-PT is provided such that the edge P-PTe is positioned on the pattern portion PP. By providing the protective layer resin P-PT such that the edge P-PTe is positioned on the pattern portion PP having an uneven structure on the upper surface, the contact angle θ of the protective layer resin P-PT is improved. The contact angle θ of the protective layer resin P-PT is defined as the angle between the upper surface of the protruding portion PRT in contact with the edge P-PTe and the tangent line of the edge P-PTe. For example, the contact angle θ of the protective layer resin P-PT is about 90° or more. Compared with a comparative example in which the pattern portion PP is not formed, the thickness of the edge portion of the protective layer resin P-PT is formed relatively thick.

[0143] In a portion where the pattern portion PP is not disposed, the edge P-PTe of the protective layer resin P-PT is located on the upper surface of the at least one insulating layer extending into the peripheral region or on the upper surface of the mother substrate 110p.

[0144] Next, as shown in FIGS. 18 and 19, the protective layer resin P-PT is cured to form the protective layer PT. For example, ultraviolet light UV is provided toward the protective layer resin P-PT at the upper portion of the protective layer resin P-PT. The protective layer resin P-PT is cured by the ultraviolet light UV to form the protective layer PT.

[0145] Next, as shown in FIGS. 19 and 20, each cell region CA of the mother substrate 110p is cut out. A cut line CTL is defined along the edge of each cell region CA. The protective layer PT can protect various structures formed in the cell region CA on the mother substrate 110p, such as pixel circuits, light-emitting elements, wirings, etc. during the cutting. Each of the preliminary display panels 100p separated by the cutting process is the display panel 100. Immediately after the cutting process, the protective layer PT is disposed on each display panel 100.

[0146] Remove the protective layer PT from each of the cut-out display panels 100. For example, the protective layer PT can be removed using a detaching mechanism (not shown). For example, the detaching mechanism is a knife including an edge portion inserted between the upper surface of the pattern portion PP and the lower surface of the protective layer PT, but this is an example and the present invention is not limited thereto.

[0147] As described above, by providing the protective layer resin P-PT such that the edge P-PTe is positioned on the pattern portion PP having an uneven structure on the upper surface, the contact angle θ of the protective layer resin P-PT is improved. The protective layer PT is formed by curing the protective layer resin P-PT. That is, compared with the comparative example in which the pattern portion PP is not formed, the thickness of the edge portion of the protective layer PT is formed relatively thick, and thus, the protective layer PT can be easily removed from the display panel 100. Therefore, it is possible to prevent or reduce the remaining of the protective layer PT on the display panel 100, and the reliability of the display device 10 can be improved.

[0148] On each of the display panels 100 from which the protective layer PT has been removed, an antireflection member (the antireflection member 200 in FIG. 1), a cover window, etc. are provided. The display panel 100, the antireflection member, and the cover window constitute the display device 10.

Industrial Applicability

[0149] The present invention is applicable to various display devices. For example, the present invention is applicable to various display devices such as vehicle, ship, and aircraft display devices, portable communication devices, display devices for exhibition or information transmission, and medical display devices.

[0150] In the above, the exemplary embodiments of the present invention have been described with reference thereto, but those having ordinary knowledge in the technical field will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the following claims.

Explanation of Reference Numerals

[0151] 10: Indicating device 100: Display panel 110: Substrate PCL: Pixel circuit layer EDL: Light-emitting element layer 140: Encapsulation layer 150: Power transmission wiring 162: First dam portion 162: Second dam portion 172: Crack prevention portion 174: Cover layer PP: Pattern portion PRT: Protrusion GV: Groove 180: Third dam portion VL1: First virtual line VL2: Second virtual line 200: Anti-reflection member 110p: Mother substrate 100p: Preliminary display panel P-PT: Protective layer resin PT: Protective layer

Claims

1. a substrate including a display area and a peripheral area located outside the display area; a pixel circuit layer disposed in the display region on the substrate, the pixel circuit layer including a thin film transistor and a plurality of insulating layers; a light emitting element layer including light emitting elements disposed in the display region on the substrate and electrically connected to the thin film transistor; a sealing layer disposed on the light emitting element layer; a pattern portion disposed in a portion of the peripheral region on the substrate, the pattern portion having an upper surface with a concave-convex structure.

2. The display device of claim 1 , wherein the pattern portion comprises a plurality of protrusions spaced apart from one another, and grooves defining the protrusions.

3. 3. The display device according to claim 2, wherein the distance between adjacent protrusions is 10 [mu]m or more and 50 [mu]m or more.

4. The display device according to claim 2 , wherein each of the protrusions has a rectangular shape in a cross section perpendicular to the substrate.

5. 3. The display device according to claim 2, wherein each of the protrusions has an inverse tapered shape in a cross section perpendicular to the substrate.

6. 3. The display device according to claim 2, wherein a bottom surface of the groove has insulating properties.

7. The light emitting element includes a pixel electrode, a light emitting layer, and a common electrode, the common electrode extends from the display region to the peripheral region; The display device according to claim 2 , wherein a portion of the pattern portion overlaps a portion of the common electrode in the peripheral region.

8. The display device of claim 7 , wherein in the region where the portion of the pattern unit and the portion of the common electrode overlap, a bottom surface of the groove is spaced upward from an upper surface of the common electrode.

9. the sealing layer includes a first inorganic sealing layer disposed on the light-emitting element layer, an organic sealing layer disposed on the first inorganic sealing layer, and a second inorganic sealing layer disposed on the organic sealing layer; At least one of the insulating layers, the first inorganic sealing layer, and the second inorganic sealing layer included in the pixel circuit layer extends from the display region to the peripheral region, 3. The display device of claim 2, wherein in the peripheral region, at least a top layer of the at least one insulating layer defines the grooves of the pattern portion.

10. The display device according to claim 1 , wherein the pattern portion is disposed in correspondence with a corner of the display area.

11. The substrate further includes a pad area located on one side of the display area, the peripheral region includes a first peripheral region between the display region and the pad region, and a second peripheral region spaced apart from the pad region; The display device according to claim 1 , wherein the pattern portion is disposed only in the second peripheral region of the peripheral region.

12. The display device according to claim 1 , wherein the pattern portion contacts an edge of the substrate.

13. The display device of claim 1 , wherein the pattern portion is spaced outward from the display area and is continuously arranged from a first virtual line located in the peripheral area to a second virtual line located at an edge of the substrate.

14. a first dam portion disposed in the peripheral region on the substrate and spaced apart from the display region to surround the display region; The display device according to claim 1 , wherein the pattern portion overlaps the first dam portion.

15. a crack prevention portion disposed on the substrate in the peripheral region and spaced outwardly from the first dam portion; The display device according to claim 14 , wherein the pattern portion further overlaps the crack prevention portion.

16. a second dam portion disposed in the peripheral region on the substrate so as to be adjacent to an edge of the substrate and spaced outwardly from the crack prevention portion; The display device according to claim 15 , wherein the pattern portion further overlaps the second dam portion.

17. The display device according to claim 1 , further comprising an anti-reflection member disposed on the sealing layer.

18. forming a pixel circuit layer, a light emitting element layer, and a sealing layer on a mother substrate including a display region and a plurality of cell regions including a peripheral region located outside the display region; forming a pattern portion having an upper surface with a concave-convex structure in the peripheral region of each of the cell regions; providing a protective layer resin on the sealing layer and the pattern portion of each of the cell regions to form a protective layer; Cut out each of the cell regions; removing the protective layer from each of the cut-out display panels.

19. At least one of the insulating layers included in the pixel circuit layer and the at least one inorganic sealing layer included in the sealing layer extends from the display region to the peripheral region, 20. The method of claim 18, wherein forming the pattern portion comprises partially etching the at least one insulating layer in the peripheral region to form a plurality of spaced apart protrusions and grooves defining the protrusions.

20. The method of claim 18, wherein forming the protective layer comprises applying ultraviolet light onto the provided protective layer resin to harden the protective layer resin.

21. The method of claim 18, wherein forming the protective layer comprises providing the protective layer resin such that an edge of the protective layer resin is positioned on the pattern portion.

22. The method of claim 18, further comprising providing an anti-reflection member on each of the display panels from which the protective layer has been removed.

Images