Semiconductor device

Abstract

To provide a semiconductor device having high storage capacity per unit area.SOLUTION: A semiconductor device includes a first memory cell, and a second memory cell provided thereon. The first memory cell includes first and second transistors, and a first capacitor element. The second memory cell includes third and fourth transistors, and a second capacitor element. A gate of the first transistor is connected to one of a source and a drain of the second transistor and to one electrode of the first capacitor element. A gate of the third transistor is connected to one of a source and a drain of the fourth transistor and to one electrode of the second capacitor element. One of a source and a drain of the first transistor is connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.SELECTED DRAWING: None

Description

Technical Field

[0001] The present invention relates to, for example, transistors and semiconductor devices. Or, the present invention relates to, for example, a method for manufacturing transistors and semiconductor devices. Or, the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, and an electronic device. Also or, it relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device. Also or, it relates to a driving method for a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification etc. relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Note that in this specification etc., the semiconductor device generally refers to any device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a memory device, a semiconductor circuit, and an electronic device may have a semiconductor device.

Background Art

[0004] A semiconductor device that enables data reading and writing by combining a transistor using silicon (Si) for a semiconductor layer and a transistor using an oxide semiconductor (OS) for a semiconductor layer has attracted attention (see Patent Document 1 ).

[0005] Also, in recent years, with the increase in the amount of data handled, semiconductor devices having a larger storage capacity​​​​ An arrangement is required. In order to increase the memory capacity per unit area, it is effective to stack memory cells (see Patent Document 2). By stacking and providing memory cells, the memory capacity per unit area can be increased according to the number of stacked memory cells.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] One of the problems is to provide a semiconductor device having a large memory capacity per unit area. Another problem is to provide a semiconductor device having a novel structure in which memory cells are stacked. Or, one of the problems is to provide a driving method for a semiconductor device having a novel structure.

[0008] Or, one of the problems is to provide a module having the semiconductor device. Or, one of the problems is to provide an electronic device having the semiconductor device or the module. Or, one of the problems is to provide a novel semiconductor device. Or, one of the problems is to provide a novel module. Or, one of the problems is to provide a novel electronic device.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that the present invention ​​​​​​​​One aspect is not required to solve all of these problems. Other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc.

[0010] One aspect of the present invention includes a first memory cell and a second memory cell provided on the first memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor element. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor element. The gate of the first transistor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the second transistor is electrically connected to one of the electrodes of the first capacitor element. The gate of the third transistor is electrically connected to one of the source or drain of the fourth transistor. One of the source or drain of the fourth transistor is electrically connected to one of the electrodes of the second capacitor element. One of the source or drain of the first transistor is

[0011] electrically connected to one of the source or drain of the third It has a second memory cell provided on the cell, and the first memory cell has a first transistor a first capacitor, and a second transistor, and the second memory cell has a third transistor, a fourth transistor, and a second capacitor, and the gate of the first transistor is electrically connected to one of the source or drain of the second transistor One of the source or drain of the second transistor is electrically connected to one of the electrodes of the first capacitor The gate of the third transistor is electrically connected to one of the source or drain of the fourth transistor One of the source or drain of the fourth transistor is electrically connected to one of the electrodes of the second capacitor, and one of the source or drain of the first transistor is electrically connected to one of the source or drain of the third transistor The second transistor and the fourth transistor have an oxide semiconductor, and the first transistor and the third transistor are characterized in that the channel length direction is substantially perpendicular to the upper surface of the substrate A semiconductor device.

[0012] Another aspect of the present invention has a first memory cell provided on a substrate and a second memory cell provided on the first memory cell. The first memory cell has a first transistor a first capacitor, and a second transistor, and the second memory cell has a third transistor, a fourth transistor, and a second capacitor, and the gate of the first transistor is electrically connected to one of the source or drain of the second transistor One of the source or drain of the second transistor is electrically connected to one of the electrodes of the first capacitor The gate of the third transistor is electrically connected to one of the source or drain of the fourth transistor One of the source or drain of the fourth transistor is One side of the rain is electrically connected, and one of the source or drain of the fourth transistor is electrically connected to one of the electrodes of the second capacitive element, and one of the source or drain of the first transistor is electrically connected to one of the source or drain of the third transistor. The second transistor and the fourth transistor have an oxide semiconductor, and the first transistor and the third transistor have a part of a semiconductor provided so as to extend substantially perpendicular to the upper surface of the substrate. A semiconductor device is

[0013] characterized by that. In another aspect of the present invention, the semiconductor provided so as to extend substantially perpendicular to the upper surface of the substrate is preferably polycrystalline

[0014] silicon. In another aspect of the present invention, the semiconductor provided so as to extend substantially perpendicular to the upper surface of the substrate is preferably cylindrical. In another aspect of the present invention, a plurality of memory cell arrays provided in an array in a first direction, a plurality of first wirings, and a plurality of second wirings are provided. The plurality of first wirings and the plurality of second wirings are provided so as to extend in a second direction substantially perpendicular to the first direction. The memory cell array has a plurality of memory cell strings provided in an array in the second direction. The plurality of memory cell strings are provided so as to extend in a third direction substantially perpendicular to the first direction and the second direction. The memory cell One of the source or drain of the transistor is electrically connected to one of the source or drain of the second transistor, which is electrically connected to one of the electrodes of the capacitive element, and a plurality of memory cells are mutually electrically connected to one of the source or drain of the first transistor and the other of the source or drain of the first transistor in one of the plurality of memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that. memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that. memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that. memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that. memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that. memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that. memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that. memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that. memory cell strings. The source or drain of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and the other of the source or drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring. The other of the source or drain of the second transistor of the plurality of memory cells is electrically connected to the fifth wiring. In one of the plurality of memory cell arrays, the other electrode of the capacitive element of the memory cells in the same row is electrically connected to one of the plurality of first wirings, and the gate of the second transistor of the memory cells in the same row is electrically connected to one of the plurality of second wirings. A semiconductor device is characterized in that.

[0015] Further, in another aspect of the present invention, in the above semiconductor device, in the writing operation, one of the plurality of memory cell arrays is selected, the second transistor is turned on through one of the plurality of second wirings, a writing potential is applied to the plurality of fifth wirings, the second transistor is turned off through one of the plurality of second wirings, and data corresponding to the writing potential is held. In the reading operation, one of the plurality of memory cell arrays is selected, a first potential is applied to the other electrode of the capacitive element through one of the plurality of first wirings, and a second potential different from the first potential is applied to the other electrode of the capacitive element through a first wiring in a row different from the row of the one of the plurality of first wirings to turn on the first transistor. memory cell arrays is selected, the second transistor is turned on through one of the plurality of second wirings, a writing potential is applied to the plurality of fifth wirings, the second transistor is turned off through one of the plurality of second wirings, and data corresponding to the writing potential is held. In the reading operation, one of the plurality of memory cell arrays is selected, a first potential is applied to the other electrode of the capacitive element through one of the plurality of first wirings, and a second potential different from the first potential is applied to the other electrode of the capacitive element through a first wiring in a row different from the row of the one of the plurality of first wirings to turn on the first transistor. memory cell arrays is selected, the second transistor is turned on through one of the plurality of second wirings, a writing potential is applied to the plurality of fifth wirings, the second transistor is turned off through one of the plurality of second wirings, and data corresponding to the writing potential is held. In the reading operation, one of the plurality of memory cell arrays is selected, a first potential is applied to the other electrode of the capacitive element through one of the plurality of first wirings, and a second potential different from the first potential is applied to the other electrode of the capacitive element through a first wiring in a row different from the row of the one of the plurality of first wirings to turn on the first transistor. memory cell arrays is selected, the second transistor is turned on through one of the plurality of second wirings, a writing potential is applied to the plurality of fifth wirings, the second transistor is turned off through one of the plurality of second wirings, and data corresponding to the writing potential is held. In the reading operation, one of the plurality of memory cell arrays is selected, a first potential is applied to the other electrode of the capacitive element through one of the plurality of first wirings, and a second potential different from the first potential is applied to the other electrode of the capacitive element through a first wiring in a row different from the row of the one of the plurality of first wirings to turn on the first transistor. memory cell arrays is selected, the second transistor is turned on through one of the plurality of second wirings, a writing potential is applied to the plurality of fifth wirings, the second transistor is turned off through one of the plurality of second wirings, and data corresponding to the writing potential is held. In the reading operation, one of the plurality of memory cell arrays is selected, a first potential is applied to the other electrode of the capacitive element through one of the plurality of first wirings, and a second potential different from the first potential is applied to the other electrode of the capacitive element through a first wiring in a row different from the row of the one of the plurality of first wirings to turn on the first transistor. memory cell arrays is selected, the second transistor is turned on through one of the plurality of second wirings, a writing potential is applied to the plurality of fifth wirings, the second transistor is turned off through one of the plurality of second wirings, and data corresponding to the writing potential is held. In the reading operation, one of the plurality of memory cell arrays is selected, a first potential is applied to the other electrode of the capacitive element through one of the plurality of first wirings, and a second potential different from the first potential is applied to the other electrode of the capacitive element through a first wiring in a row different from the row of the one of the plurality of first wirings to turn on the first transistor. memory cell arrays is selected, the second transistor is turned on through one of the plurality of second wirings, a writing potential is applied to the plurality of fifth wirings, the second transistor is turned off through one of the plurality of second wirings, and data corresponding to the writing potential is held. In the reading operation, one of the plurality of memory cell arrays is selected, a first potential is applied to the other electrode of the capacitive element through one of the plurality of first wirings, and a second potential different from the first potential is applied to the other electrode of the capacitive element through a first wiring in a row different from the row of the one of the plurality of first wirings to turn on the first transistor. Turn on the dista, apply a read potential to the third wiring, and read data from the change in the read potential. This is a method for driving a semiconductor device, characterized by the above.

[0016] Another aspect of the present invention is a memory device having the above-described semiconductor device.

Advantages of the Invention

[0017] It is possible to provide a semiconductor device with a large storage capacity per unit area. Or, it is possible to provide a semiconductor device having a novel structure in which memory cells are stacked. Or, it is possible to provide a method for driving a semiconductor device having a novel structure. Or, it is possible to provide a module having the semiconductor device. Or, it is possible to provide an electronic device having the semiconductor device or the module. Or, it is possible to provide a novel semiconductor device. Or, it is possible to provide a novel module. Or, it is possible to provide a novel electronic device.

[0018] Or, it is possible to provide a module having the semiconductor device. Or, it is possible to provide an electronic device having the semiconductor device or the module. Or, it is possible to provide a novel semiconductor device. Or, it is possible to provide a novel module. Or, it is possible to provide a novel electronic device. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Or, it is possible to provide a novel electronic device.

[0019] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0020]

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[0021] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below alone. In describing the configuration of the invention with reference to the drawings, the same reference numerals are used commonly among different drawings. When referring to similar components, the same hatch pattern is used, and there may be cases where no particular reference numerals are attached.

[0022] The configurations shown in the following embodiments can be appropriately applied, combined, or replaced with other configurations shown in the embodiments to form one aspect of the present invention.

[0023] Note that in the drawings, the size, thickness of a film (layer), or region may be exaggerated for clarity.

[0024] ​​In this specification, the terms "film" and "layer" can be interchanged with each other.

[0025] Also, voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential (GND) or source potential ). Therefore, it is possible to rephrase voltage as potential. Generally, potential (voltage) is relative and is determined by its relative magnitude from the reference potential. Thus, even when described as "ground potential," etc., the potential is not necessarily 0V. For example, in some cases, the lowest potential in a circuit becomes the "ground potential." Or, in some cases, a medium potential in a circuit becomes the "ground potential." In such cases, positive and negative potentials are defined with reference to that potential.

[0026] The ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the process order or the layer order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third," etc., for explanation. Also, the ordinal numbers described in this specification, etc., may not match the ordinal numbers used to specify an aspect of the present invention.

[0027] In this specification, when it is stated that A and B are connected, it means that in addition to the case where A and B are directly connected, it includes those that are electrically connected. Here, when A and B are electrically connected, it means that there is an object having some electrical action between A and B, enabling the exchange of electrical signals between A and B.

[0028] In this specification, the source of a transistor refers to a semiconductor film that functions as an active layer means a source region that is part of it, or a source electrode connected to the semiconductor film. Similarly for a transistor, the drain means a drain region that is part of the semiconductor film, or a drain electrode connected to the semiconductor film. Also, the gate means a gate electrode.

[0029] The source and drain of a transistor change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for convenience it is assumed that the source and drain are fixed, and the connection relationship of the transistor may be described However, in reality, the names of the source and drain are interchanged according to the relationship of the above potentials.

[0030] In this specification, unless otherwise specified, the off-current means the drain current when the transistor is in the off state. The off state means, unless otherwise specified, in an n-channel type transistor, the potential difference (V ) between the gate and the source is lower than the threshold voltage (Vth), and in a p-channel type transistor, V is higher than Vth. For example GS GS for example, the off-current of an n-channel type transistor may refer to the drain current when V GS is lower than Vth. The off-current of a transistor may depend on V GS Accordingly, the off-current of a transistor is 10 -21 ​​​​​​​"is A or less" may mean that there exists a value of V at which the off - current of the transistor is 10 A or less. -21 The off - current of the transistor may depend on the potential difference (V GS ) between the drain and the source. In this specification, unless otherwise specified, the off - current represents the off - current at V

[0031] whose absolute value is 0 DS .1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 1 2V, 16V, or 20V. Or it may represent the off - current at V DS at which the reliability of a semiconductor device including the transistor is guaranteed, or at V at which the transistor is used in a semiconductor device including the transistor, etc. Even when described as "semiconductor", for example, when the conductivity is sufficiently low, it may have the characteristics of an "insulator". Also, the boundary between "semiconductor" and "insulator" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification may be rephrased as "insulator". Similarly, the "insulator" described in this specification may be rephrased as "semiconductor". Even when described as "semiconductor", for example, when the conductivity is sufficiently high, it may have the characteristics of a "conductor". Also, the boundary between "semiconductor" and "conductor" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification may be rephrased as "conductor". Similarly, the "conductor" described in this specification may be rephrased as "semiconductor". DS

[0032] DS

[0033] ​​​​​​​​​​​​In some cases, this can be rephrased as "body."

[0034] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements present at less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the conductor and carrier movement The degree of conductivity may decrease, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group 1 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can cause In addition, when the semiconductor is silicon, the characteristics of the semiconductor Examples of impurities that change the value of the valence number include oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and These include Group 3 elements and Group 15 elements.

[0035] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source region or the channel region This refers to the distance between the drain (drain region or drain electrode) and the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value or the maximum value in the region where the channel is formed. Set it as the minimum value or the average value.

[0036] The channel width refers to, for example, the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. In one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. Set it as the minimum value or the average value.

[0037] Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. becomes larger.

[0038] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement. For example, it is difficult to estimate the effective channel width from the design value. estimate the effective channel width from the design value. For accumulation, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0039] Therefore, in this specification, in the top view of the transistor, the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap each other is defined as the apparent channel width, which may be referred to as the "surrounded channel width (SCW)". In this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or when simply described as the channel width in this specification, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image, etc. and analyzing the image.

[0040] Note that when calculating the field-effect mobility of the transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, it may take a different value from the case of calculating using the effective channel width.

[0041] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. In addition, "vertical" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0042] In addition, in this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system. That's it.

[0043] (Embodiment 1) In this embodiment, the circuit configuration and operation of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 7. That's it.

[0044] 〈Memory cell〉 First, the circuit configuration and operation of the memory cell of the semiconductor device to be described later will be described with reference to FIGS. 1 (A) and FIG. 1(B). Here, FIG. 1(A) is an example of a circuit diagram showing the circuit configuration of the memory cell 10 in a planar manner, and FIG. 1(B) is a three-dimensional circuit diagram showing the circuit configuration of the memory cell 10 in a three-dimensional manner corresponding to the three-dimensional configuration of the semiconductor device to be described later. That's it.

[0045] In the memory cell 10 shown in FIGS. 1(A) and 1(B), the wiring SL and the source electrode (or drain electrode) of the transistor 1 are electrically connected, and the wiring RBL and the drain electrode (or source electrode) of the transistor 11 are electrically connected. Also, the wiring WBL and the source electrode (or drain electrode) of the transistor 12 are electrically connected, and the wiring WW L and the gate electrode of the transistor 12 are electrically connected. And, the gate electrode of the transistor 1 1 and the drain electrode (or source electrode) of the transistor 12 are the capacitor element 1 is electrically connected to one of the electrodes of 4, and the other of the wiring RWL and the electrode of the capacitor element 14 is electrically connected.

[0046] Here, for the transistor 12, for example, a transistor using an oxide semiconductor is preferably used. Although details will be described later, a transistor using an oxide semiconductor has a feature that the off-current is extremely small. Therefore, by turning the transistor 12 off, it is possible to hold the potential of the gate electrode of the transistor 11 for an extremely long time. And by having the capacitor element 14, it becomes easy to hold the charge given to the gate electrode of the transistor 11, and it also becomes easy to read the held information.

[0047] Note that the transistor 11 is not particularly limited. From the viewpoint of improving the information readout speed, for example, a transistor with a high switching speed, such as a transistor using polycrystalline silicon or single-crystalline silicon, is preferably applied.

[0048] In the memory cell 10 shown in FIGS. 1(A) and 1(B), by taking advantage of the feature that the potential of the gate electrode of the transistor 11 can be held, information writing, holding, and reading can be performed as follows. is possible.

[0049] First, writing and holding of information will be described. First, the potential of the wiring WWL is set to a potential at which the transistor 12 is turned on, and the transistor 12 is turned on. By this, the potential of the wiring WBL is electrically connected to the drain electrode (or source electrode) of the transistor 12, the gate electrode of the transistor 11, and one electrode of the capacitor element 14. It is applied to a node (also denoted as node FN). That is, the gate of transistor 11 A predetermined charge is applied (written) to the electrode. Here, two different potentials are applied Charges (hereinafter, the charge for applying a low potential is charge Q L , and the charge for applying a high potential is charge Q H ) Let either one be applied. Note that charges for applying three or more different potentials may be applied to improve the storage capacity. Then, the potential of wiring WWL is set to a potential at which transistor 12 is in the off state, and by turning off transistor 12, the charge applied to the gate electrode of transistor 11 is retained (held).

[0050] Since the off - current of transistor 12 is extremely small, the charge on the gate electrode of transistor 11 is retained for a long time.

[0051] Next, the reading of information will be described. In a state where a predetermined potential (constant potential) is applied to wiring SL, when an appropriate potential (reading potential) is applied to wiring RWL, wiring RBL takes different potentials according to the amount of charge retained on the gate electrode of transistor 11. Generally, when transistor 11 is of the n - channel type, the apparent threshold voltage V in the case where Q is applied to the gate electrode of transistor 11 is lower than the apparent threshold voltage V H in the case where Q is applied to the gate electrode of transistor 11. Here, the apparent threshold voltage is defined as the potential of wiring RWL required to turn transistor 11 from the "off state" to the "on state" or from the "on state" to the "off state". Therefore, the potential of wiring RWL is V th_H when Q L is applied to the gate electrode of transistor 11, and the apparent threshold voltage V when Q th_L is applied to the gate electrode of transistor 11. Here, the apparent threshold voltage means the potential of wiring RWL required to turn transistor 11 from the "off state" to the "on state" or from the "on state" to the "off state". Thus, the potential of wiring RWL is set to V ​th_H and V th_L the potential V between 0 By setting it to be the charge applied to the gate electrode of transistor 11 can be determined. For example, in writing when Q H is applied, if the potential of wiring RWL is V 0 (>V th_H ) then transistor 11 will be in the "on state". When Q L is applied, even if the potential of wiring RWL is V 0 (<V th_L ) transistor 11 will remain in the "off state". Note that when transistor 11 is of p-channel type, when Q L is applied it will be in the "on state" and when Q H is applied it will remain in the "off state". Therefore, by looking at the potential of wiring RBL the stored information can be read out.

[0052] Note that when memory cells are arranged and used in a matrix, it is necessary to be able to read only the information of a desired memory cell. In this way, to read the information of a predetermined memory cell and not read the information of other memory cells, when transistors 11 are connected in series between each memory cell for the wiring RWL of the memory cell that is not the target of reading, regardless of the state of the gate electrode, a potential should be applied such that transistor 11 is in the "on state" , that is, a potential greater than V should be applied. At this time, when a potential greater than V is applied to wiring RWL th_L a potential that causes transistor 11 to be in the "on state" is applied to the gate electrode of transistor 11 via capacitor element 14, and transistor WL, a potential greater than V th_L is applied to wiring R 11 This allows the transistor 11 to be turned on independently of the data stored in the node FN.

[0053] Next, the rewriting of information will be described. That is, the potential of the wiring WWL is changed by turning on the transistor 12. This causes the potential of the wiring WBL ( A potential related to new information is applied to the gate electrode of the transistor 11 and the capacitor element 14. After that, the potential of the wiring WWL is set to a potential at which the transistor 12 is turned off. By turning off the transistor 12, the gate electrode of the transistor 11 is The charge related to the information is given.

[0054] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. This allows the information to be rewritten quickly during the erase operation of the flash memory. This eliminates the need to extract charge from the floating gate using the high voltages required for This makes it possible to suppress a decrease in the operating speed. In other words, high-speed operation of the semiconductor device is realized. do.

[0055] The drain electrode (or source electrode) of the transistor 12 and the The node FN to which the gate electrode and one electrode of the capacitor 14 are electrically connected is a nonvolatile Floating gate of floating gate type transistor used as memory element When the transistor 12 is off, the node FN is in the insulator. The node FN can be considered to be buried, and charge is stored in the node FN. The off-current of the transistor 12 used is less than one-hundred-thousandth of that of a transistor formed of silicon semiconductor, so that the charge accumulated in the node FN can be retained for a long period of time. That is, the transistor 12 using an oxide semiconductor can realize a memory device capable of retaining information for a long period of time without power supply. For example, when the off-current of the transistor 12 at room temperature (25 ° C) is 10 zA (1 zA (zepto ampere) is 1 × 10

[0056] A) or less and the capacitance value of the capacitor element 14 is about 10 fF , data can be retained for at least 10 -21 seconds or more. Note that it goes without saying that the retention time varies depending on transistor characteristics and capacitance values. 4

[0057] Further, in the memory cell 10 shown in this embodiment, there is no problem of deterioration of the gate insulating film (tunnel insulating film) pointed out in the conventional floating gate type transistor. That is, the problem of deterioration of the gate insulating film when injecting electrons into the floating gate, which has been a conventional problem, can be solved. This means that there is no limit on the principle number of write times. Further, the high voltage required for writing and erasing in the conventional floating gate type transistor is also unnecessary.

[0058] In the memory cell 10, the node FN acts equivalently to the floating gate of a floating gate type transistor such as a flash memory, but the node FN of this embodiment has characteristics essentially different from those of the floating gate of a flash memory or the like. In flash memory, the potential applied to the control gate is high, so In order not to affect the floating gates of adjacent cells, the spacing between cells is This is one of the factors that hinders the high integration of semiconductor devices. The cause of this is the flash tunneling effect, which is achieved by applying a high electric field to generate a tunnel current. This is due to the fundamental principles of memory.

[0059] On the other hand, the semiconductor device according to the present embodiment has a transistor switch using an oxide semiconductor. It operates by switching and does not use the principle of charge injection by tunnel current as described above. In other words, a high electric field for injecting charges, as in the case of flash memory, is not required. Therefore, there is no need to consider the effect of high electric fields due to the control gate on adjacent cells. This makes it easier to achieve high integration.

[0060] In order to increase the memory capacity of a semiconductor device, in addition to increasing the integration density, a method for multi-level data storage is also required. For example, it is possible to write three or more levels of information into one memory cell. This allows for a larger memory capacity than when writing binary (1-bit) information. For example, the charge Q L , charge Q giving high potential H In addition By applying a charge Q that gives another potential to the gate electrode of the transistor 11, multi-values ​​are realized. Multi-value data can be expressed as, for example, 4 values ​​(2 bits), 8 values ​​(3 bits), It would be good if it could hold data such as 16 values ​​(4 bits), 16 values ​​(4 values), etc.

[0061] The above explanation is for n-type transistors (n-channel transistors) that use electrons as carriers. This is about the case of using (タ), but instead of an n-type transistor, a p-type transistor with holes as carriers may be used.

[0062] In the memory cell array described later, as shown in FIG. 1(B), the memory cell 10 has transistors 11 in the channel length direction, transistors 12 in the channel length direction, wiring SL, wiring R BL, wiring WBL, wiring RWL, and wiring WWL are preferably provided so as to intersect three-dimensionally. Preferably.

[0063] It is preferable that the channel length direction of transistor 11 and the channel length direction of transistor 12 are substantially perpendicular. Also, with respect to the upper surface of the substrate on which the memory cell 10 is provided, the channel length direction of transistor 11 is substantially perpendicular, and the channel length direction of transistor 12 is substantially parallel. Preferably.

[0064] Also, with respect to wiring RBL, wiring SL, and wiring WBL, wiring WWL and wiring RWL are preferably substantially perpendicular. Also, with respect to the upper surface of the substrate on which the memory cell 10 is provided, wiring RBL, wiring SL, and wiring WBL are substantially perpendicular, and wiring WWL and wiring RWL are substantially parallel. Preferably.

[0065] By configuring the memory cell 10 in this way, as described later, a plurality of memory cells 1 0 can be stacked so as to be connected in series in each transistor 11. Thereby, a semiconductor device capable of increasing the storage capacity per unit area according to the number of stacked memory cells 10 can be provided. Preferably.

[0066] Also, as described above, the channel length direction of transistor 11 is perpendicular to the upper surface of the substrate. By adopting the circuit configuration provided therein, the gate electrode surrounds the semiconductor, and the source and drain are vertically arranged above and below the transistor, enabling easy use of a vertical transistor (SGT: Surrounding Gate Transistor). Taking the minimum processing dimension as F, while the occupied area of a standard planar transistor is 8F 2 whereas, the occupied area of the SGT is only 4F 2 which is extremely small. Thus, the storage capacity per unit area can be further increased.

[0067] 〈Memory Cell Array〉 Next, a more specific circuit configuration and operation applying the circuit shown in FIG. 1 will be described with reference to FIGS. 2 through 7.

[0068] An example of a block circuit diagram of a semiconductor device having a three-dimensional memory cell array 40, a selection transistor array 50, a drive circuit 51, a readout circuit 52, a drive circuit 53, and a drive circuit 54 is shown in FIG. 2. In the following description, for convenience, a rectangular coordinate system composed of the x-axis, y-axis, and z-axis is set as shown in FIG. 2 for explanation.

[0069] Also, since there are some parts where the drawing becomes complicated in FIG. 2, FIG. 3 shows an example of a block circuit diagram of only the three-dimensional memory cell array 40. FIG. 4 shows an example of a block circuit diagram of the two-dimensional memory cell array 30[1] included in the three-dimensional memory cell array 40. However, FIG. 4 shows an example of a block circuit diagram of the two-dimensional memory cell array 30[1] represented planarly, and some configurations in the z-axis direction are represented pseudo-planarly on the xy plane. FIG. 5 shows the selection transistor array 50, the drive circuit 51, the readout circuit 52, the drive circuit 53, and the drive circuit 54.​​ An example of a block circuit diagram of path 54 is shown.

[0070] The selection transistor array 50, the drive circuit 51, the read circuit 52, the drive circuit 53, and the drive circuit 54 are formed on a substrate surface substantially parallel to the xz plane, and a three-dimensional memory cell array 40 is formed on the selection transistor array 50.

[0071] The three-dimensional memory cell array 40 has 1 m 2 × m 3 × m 1 (m 2 、m 3 are natural numbers) memory cells 10, with m 1 in the x-axis direction, m 2 in the y-axis direction, and m 3 in the z-axis direction of the memory cells 10 are arranged in a rectangular parallelepiped shape. Hereinafter, as shown in FIG. 2, coordinates are assigned to the memory cells 10, and the memory cells 10(1,1,1) to (m ,m 1 ,m 2 ,m 3 ) are shown as such. There may be cases.

[0072] Also, as shown in FIG. 3, the three-dimensional memory cell array 40 has m × m 1 × m 3 wiring lines SL, RBL, and WBL extending in the y-axis direction, and m × m 2 × m 3 wiring lines RWL and WWL extending in the x-axis direction. Hereinafter, as shown in FIG. 3, coordinates in the x-axis and z-axis directions are assigned to the wiring line SL, and the wiring line SL[1,1] to [m ,m 1 ,m 3 may be shown as such. Similarly, the wiring line RBL[1,1] to [m 1 ,m 3 , the wiring line W BL[1,1] to [m 1 ,m 3 may be shown as follows. Also, as shown in FIG. 3, coordinates in the y-axis direction and z-axis direction are assigned to the wiring RWL, and the wirings RWL[1,1] to [m ,m 2 ,m 3 may be shown as follows. Similarly, the wirings WWL[1,1] to [m 2 ,m 3 may be shown as follows.

[0073] The 3D memory cell array 40 is composed of m 3 two-dimensional memory cell arrays 30 arranged in the z-axis direction. Hereinafter, as shown in FIG. 2, coordinates in the z-axis direction are assigned to the two-dimensional memory cell array 30, and the two-dimensional memory cell arrays 30[1] to [m may be shown as 3 follows. Each two-dimensional memory cell array 30 is composed of m

[0074] memory cell strings 20 arranged in the x-axis direction. Hereinafter, as shown in FIG. 2, coordinates in the x-axis direction and z-axis direction are assigned to the memory cell string 20, and the memory cell strings 20[1,1] to [m 1 , m may be shown as follows. Each memory cell string 20 has m 1 , memory cells 10 arranged in the y-axis direction. Here, since each two-dimensional memory cell array 30 is composed of m 3 memory cell strings 20, in the two-dimensional memory cell array 30, m memory cells are arranged in a matrix in the x-axis direction and m 2 memory cells are arranged in a matrix in the y-axis direction. 0, it means that m 1 memory cells are arranged in a matrix in the x-axis direction and m memory cells are arranged in a matrix in the y-axis direction. 1 memory cells are arranged in a matrix in the y-axis direction. 2 memory cells are arranged in a matrix. That's it.

[0075] As shown in FIG. 1(B), the memory cell 10 includes a transistor 11, a transistor 12, and a capacitor element 14, and is electrically connected to a wiring SL, a wiring RBL, a wiring WBL, a wiring RWL, and a wiring WWL. However, as shown in FIGS. 2 to 4, the memory cells 10 constituting each memory cell string 20 are connected in series in the y-axis direction in the transistor 11. . Therefore, only the memory cell (i 1 , 1, i 3 )(where i 1 is a natural number of 1 or more and m 1 or less, and i 3 is a natural number of 1 or more and m 3 or less) is connected to the wiring RBL i 1 , i 3 without passing through other memory cells 10. 1 Also, only the memory cell (i 2 , m 3 , i ) is connected to the wiring SL[i 1 , i 3 without passing through other memory cells 10. Other memory cells 10 are electrically connected to the wiring RBL and the wiring SL through other memory cells 10 in the same memory cell string 20.

[0076] Here, taking the two-dimensional memory cell array 30[1] shown in FIG. 4 as an example, the structure of the two-dimensional memory cell array 30 will be described. The two-dimensional memory cell array 30[1] shown in FIG. 4 includes m 1 wires of SL[1, 1] to [m 1 , 1], m 1 wires of RBL[1, 1] to [m 1 , 1], m 1 wires of WBL[1, 1] to [m 1 , 1], and m 2 wires of RWL[1 , 1] to [m2 , 1] and m 2 The wiring WWL[1, 1] to [m 2 , 1] and m 1 × m 2 memory cells 10(1, 1, 1) to (m 1 , m 2 , 1 ) and has.

[0077] In the following, the matrix wiring and memory cells of the two-dimensional memory cell array 30 10 may be expressed in matrix form. For example, in the same two-dimensional memory cell array 30 a plurality of memory cells 10 with the same y coordinate can be expressed as memory cells 10 in the same row . Also, in the same two-dimensional memory cell array 30, a plurality of memory cells 10 (which can also be said to form the same memory cell string 20) with the same x coordinate can be expressed as memory cells 10 in the same column. Also, the x-axis direction can be expressed as the row direction and the y-axis direction as the column direction. In the following, in the two-dimensional memory cell array 30 shown in FIG. 4, etc., from the bottom row in order are the first row, the second row,... m 2 th row, and from the left column in order the first column, the second column,... m 1 th column.

[0078] The wiring SL[i 1 , 1] is respectively electrically connected to the source electrode of the corresponding transistor 11 of the memory cell 10(i 1 , m 2 , 1), and the wiring RBL[i , 1] is respectively electrically connected to the drain electrode of the corresponding transistor 11 of the memory cell 10(i 1 , 1, 1) and is continued. memory cell 10(i 1 , 1, 1) and is electrically connected to the drain electrode of the corresponding transistor 11 .

[0079] Also, the wiring WBL[i 1 ,1] is electrically connected to the source electrodes of the corresponding transistors 12 of the memory cells 10(i 1 ,1,1) to (i 1 ,m 2 ,1). In other words, the source electrodes of the transistors 12 of the memory cells 10 in the same column are electrically connected to the wiring WB L in the same column.

[0080] The wiring RWL[i 2 ,1] (where i 2 represents a natural number greater than or equal to 1 and less than or equal to m 2 .) is electrically connected to the other electrode of the corresponding capacitor element 14 of the memory cells 10(1,i ,1) to (m 2 ,i 1 ,1). In other words, the other electrode of the capacitor element 14 of the memory cells 10 in the same row is electrically connected to the wiring RWL in the same row. 2

[0081] Also, the wiring WWL[i 2 ,1] is electrically connected to the gate electrodes of the corresponding transistors 12 of the memory cells 10(1,i 2 ,1) to (m 1 ,i 2 ,1). In other words, the gate electrodes of the transistors 12 of the memory cells 10 in the same row are electrically connected to the wiring WW L in the same row.

[0082] The source electrode of the transistor 11 of the memory cell 10(i 1 ,i 2A ,1) (where i 2A represents a natural number greater than or equal to 1 and less than or equal to m 2 -1.) is ) 1 ,i 2A +1,1) of the tra ​​​​​It is electrically connected to the drain electrode of the transistor 11. In other words, in the same column, a plurality of memory cells 10 are mutually connected such that the source electrode of the transistor 11 and the drain electrode of the transistor 11 are electrically connected.

[0083] In this way, between the wiring SL[i 1 ,1] and the wiring RBL[i 1 ,1], the memory cells 10(i ,1,1) to (i 1 ,m 1 ,1) connected in series in the transistor 1 2 1 thus constitute a memory cell string 20[i ,1]. 1

[0084] In this way, the memory cell string 20 contains a plurality of memory cells 10, and they can be stacked so that the respective transistors 11 are connected in series. The memory cell str ing 20 can increase the storage capacity of the memory cell string 20 according to the number of stacked memory cells 10. Therefore, the three-dimensional memory cell array 40 composed of a plurality of memory cell strings 20 can increase the storage capacity per unit area according to the number of stacked memory cells 10.

[0085] Here, the structure of the selection transistor array 50 shown in FIG. 5 will be described. The selection tr ansistor array 50 has m 1 ×m 3 selection transistor cells 6 0 arranged in a matrix, m 1 wiring RBLs and wiring WBLs provided extending in the z-axis direction, and m wiring SG1s and wiring SG2s provided extending in the x-axis direction. Hereinafter, the select 3 ion tr Assign the coordinates in the xz plane to the transistor cell 60, and the selected transistor cell 60(1,1) to up to (m 1 ,m 3 ) may be shown as such. Also, assign the coordinates in the x-axis direction to the wiring RBL and the wiring WBL, and the wiring RBL[1] to [m , the wiring WBL[1] to [m 1 may be shown as 1 as such. Also, assign the coordinates in the z-axis direction to the wiring SG1 and the wiring SG2, and the wiring S G1[1] to [m , the wiring SG2[1] to [m 3 may be shown as 3 as such.

[0086] Each selected transistor cell 60 has a transistor 61 and a transistor 62. In the selected transistor cell 60(i 1 ,i 3 ), the wiring RBL[i 1 and the drain electrode (or source electrode) of the transistor 61 are electrically connected, and the wiring RBL[i i 1 ,i 3 of the memory cell string 1 ,i 3 and the source electrode (or drain in electrode) of the transistor 61 are electrically connected, and the wiring SG1[i 3 and the gate electrode of the transistor 61 are electrically connected. Also, in the selected transistor cell 60(i 1 ,i 3 ), the wiring WBL[i 1 and the drain electrode (or source electrode) of the transistor 62 are electrically connected , and the wiring WBL[i 1 ,i 3 of the memory cell string [i 1 ,i 3 and the source electrode (or drain electrode) of the transistor 62 are electrically connected, and the wiring SG2[i3 and The gate electrodes of the transistors 62 are electrically connected.

[0087] In this way, each selection transistor cell 60 is provided corresponding to each memory cell string 20, and the conduction states between the wiring RBL[i 1 and the wiring RBL[i 1 , 1] to [i 1 , m 3 are selected by the transistor 61 of each selection transistor cell 60, and the conduction states between the wiring WBL[i 1 and the wiring WBL[i 1 , 1] to [i 1 , m 3 can be selected by the transistor 62 of each selection transistor cell 6 0.

[0088] Also, as shown in FIG. 5, around the selection transistor array 50, a drive circuit 51, a read out circuit 52, a drive circuit 53, and a drive circuit 54 are provided. The drive circuit 51 is connected to the wiring RBL[1] to [m 1 and the wiring WBL[1] to [m 1 . Also, the wiring RBL[1] to [m 1 is also connected to the readout circuit 52. Also, although not shown, the drive circuit 53 is connected to the wiring RWL[1, 1] to [m 2 , m 3 and the wiring WW L[1, 1] to [m 2 , m 3 . Also, the drive circuit 54 is connected to the wiring SG 1[1] to [m 3 and the wiring SG2[1] to [m 3 .

[0089] Next, an example of a readout circuit that can be used for the readout circuit 52 will be described with reference to FIG. 6. will be described below. Fig. 6(A) shows a schematic diagram of a read circuit. The read circuit has a transistor and a sense amplifier circuit.

[0090] At the time of reading, terminal A is connected to a wiring RBL to which a memory cell for performing reading is connected. Also, a bias potential Vbias is applied to the gate electrode of the transistor, and the potential of terminal A is controlled.

[0091] The memory cell 10 exhibits different electrical resistances according to the data stored therein. Specifically, when the transistor 11 of the selected memory cell 10 is in the on state, it is in a low-resistance state, and when the transistor 11 of the selected memory cell 10 is in the off state, it is in a high-resistance state.

[0092] When the memory cell is in the high-resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense amplifier outputs a potential (data "0") corresponding to the potential of terminal A. On the other hand, when the memory cell is in the low-resistance state, the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "1") corresponding to the potential of terminal A.

[0093] In this way, by using the read circuit, data can be read from the memory cell. Note that the read circuit shown in this embodiment is an example. Other known circuits may be used. Also, the read circuit may have a precharge circuit. Instead of the reference potential Vref, it may be configured to be connected to a reference memory cell.

[0094] Fig. 6(B) shows a differential sense amplifier, which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and Vin( +) amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), then Vout is, generally a High output, and if Vin(+) < Vin(-), then Vout is generally a Low output .

[0095] Fig. 6(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, with signal Sp set High and signal Sn set Low, the power supply potential (Vdd) is cut off. Then, the potentials for comparison are applied to V1 and V2. After that, with signal Sp set Low and signal S n set High, when the power supply potential (Vdd) is supplied, if the potentials for comparison V1in and V2 in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low , and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is Hig h. Utilizing such a relationship, the difference between V1in and V2in can be amplified. .

[0096] Note that in the above, the drive circuit 51, the readout circuit 52, the drive circuit 53, and the drive circuit 54 are each provided independently according to their functions, but the semiconductor device shown in this embodiment is not limited to this, and a plurality of circuits may be provided together as one circuit. Also, the arrangement of the drive circuit 51, the readout circuit 52, the drive circuit 53, and the drive circuit 54, and the wiring connected to each circuit is not limited to the configuration shown in Fig. 5 and may be appropriately set according to the semiconductor device.

[0097] Also, the wirings SL[1,1] to [m 1 ,m 3 are each provided separately in Fig. 3 However, it is not limited to this configuration. For example, a plurality of wirings SL may be electrically connected, or all of the wirings SL may be electrically connected. Also, the wiring SL[1,1] to [m may be connected to a low power supply potential that supplies, for example, a ground potential GND or 0V. 1 ,m 3 may be connected to a low power supply potential that supplies, for example, a ground potential GND or 0V. That's all right.

[0098] Also, in the semiconductor device shown in FIG. 2, a three-dimensional memory cell array 40 is provided on the selection transistor array 50, but the semiconductor device shown in the present embodiment is not limited to this. For example, a selection transistor array 50 may be provided on the three-dimensional memory cell array 40. In that case, the transistors 61 and 62 of the selection transistor cell 60 may be provided using, for example, an oxide semiconductor in the same manner as the transistor 12. It is not limited to this. For example, a selection transistor array 50 may be provided on the three-dimensional memory cell array 40. In that case, the transistors 61 and 62 of the selection transistor cell 60 may be provided using, for example, an oxide semiconductor in the same manner as the transistor 12. It is not limited to this. For example, a selection transistor array 50 may be provided on the three-dimensional memory cell array 40. In that case, the transistors 61 and 62 of the selection transistor cell 60 may be provided using, for example, an oxide semiconductor in the same manner as the transistor 12.

[0099] Also, a part of the peripheral circuits such as the drive circuit 51, the read circuit 52, the drive circuit 53, and the drive circuit 54 may be provided under the three-dimensional memory cell array 40. For example, a read circuit may be provided in a matrix corresponding to each memory cell string 20, and in this case, the read circuit provided in the matrix and the selection transistor cell 60 may be stacked and provided. 20, and in this case, the read circuit provided in the matrix and the selection transistor cell 60 may be stacked and provided. 20, and in this case, the read circuit provided in the matrix and the selection transistor cell 60 may be stacked and provided. That's all right.

[0100] The writing, holding, and reading of data are basically the same as in the case of FIG. 1. However, in the three-dimensional memory cell array 40, first, one of the two-dimensional memory cell arrays 30[1] to [m is selected, and then data is written or read. Also, the two-dimensional memory cell arrays 30[1] to [m 3 is selected, and then data is written or read. Also, the two-dimensional memory cell arrays 30[1] to [m is selected, and then data is written or read. Also, the two-dimensional memory cell arrays 30[1] to [m 3Writing and reading of data The writing and reading are performed at least in row units. That is, the specific writing operation is as follows . Here, as an example, the case where either a potential V2 (a potential lower than the power supply potential VDD) or a reference potential GND (which may be expressed as 0 V) is applied to the node FN will be described . However, the relationship of the potential applied to the node FN is not limited to this. Also, the data held when the potential V2 is applied to the node FN is defined as data "1", and the data held when the reference potential GND is applied to the node FN is defined as data "0". Also, the reference potential GND is applied to the wiring SL . In data writing, first, one of the plurality of two-dimensional memory cell arrays 30 is selected . In the selection of the two-dimensional memory cell array 30, the potential of the corresponding wiring SG2 is set to V1 (for example VDD), and the transistor 62 electrically connected to the wiring is turned on, and the wirings WBL[1] to [m

[0101] and the wiring WBL included in the selected two-dimensional memory cell array 30 are brought into a conductive state. At this time, the potential of the non-selected wiring SG2 is set to GND (0 V), and the wirings WBL[1] to [m and the wiring WBL included in the non-selected two-dimensional memory cell array 30 are in a non-conductive state 1 . Next, in the selected two-dimensional memory cell array 30, the potential of the wiring WWL connected to the memory cell 10 of the row to be written is set to V3 (a potential higher than V2, for example VDD), and the transistor 12 of the memory cell 1 10 is turned on. When writing data "0" to the memory cell 10, GND is applied as the writing potential to the wiring WBL, and to the memory cell 10 . .

[0102] . . . When writing data "0" to the memory cell 10, GND is applied as the writing potential to the wiring WBL, and to the memory cell 10 . . When writing data "1", a potential V2 is applied as the writing potential to the wiring WBL. Here, since the potential of the wiring WWL is V3, it is possible to apply the potential V2 to the node FN.

[0103] To hold data, the potential of the wiring WWL connected to the memory cell 10 to be held is set to GND and the transistor 12 of the memory cell 10 is turned off. The wiring When the potential of WWL is fixed to GND, the potential of the node FN is fixed to the potential at the time of writing . That is, when the potential V2 corresponding to data "1" is applied to the node FN, the potential of the node FN becomes V2, and if GND corresponding to data "0" is applied to the node FN, the potential of the node FN becomes GND.

[0104] Also, since GND is applied to the wiring WWL, even if either data "1" or data "0" is written , the transistor 12 is turned off. Since the off-current of the transistor 12 is extremely small, the charge of the gate electrode of the transistor 11 is held for a long time. In this way, the data corresponding to the writing potential can be held at the node FN of the memory cell 10 to be held.

[0105] In data reading, first, one of the plurality of two-dimensional memory cell arrays 30 is selected . In selecting the two-dimensional memory cell array 30, the potential of the corresponding wiring SG1 is set to V1 (for example, VDD), the transistor 61 electrically connected to the wiring is turned on, and the wirings RBL[1] to [m and the wiring RBL included in the selected two-dimensional memory cell array 30 1 are made conductive. At this time, the potential of the non-selected wiring SG1 is set to GND (0V), and the wiring ​ Wiring RBL[1] to [m 1 and the wiring RB included in the non-selected two-dimensional memory cell array 30 L is set to a non-conductive state.

[0106] Next, in the selected two-dimensional memory cell array 30, the potential of the wiring RWL connected to the memory cell 10 of the row to be read is set to GND, and the other electrode of the capacitive element 14 to which it is connected is set to GND. Also, the potential of the wiring RWL connected to the memory cell 10 of the row not to be read is set to V5 (for example, VDD), and the other electrode of the capacitive element 14 to which it is connected is set to V5.

[0107] When the potential of the wiring RWL connected to the memory cell 10 of the row to be read is set to GND, if the potential V2 corresponding to data "1" is applied to the node FN of the memory cell 10 to be read, the transistor 11 is turned on. On the other hand, if GND corresponding to data "0" is applied to the node FN, the transistor 11 is turned off. When the potential of the wiring RWL connected to the memory cell 10 of the row not to be read is set to V5 the transistor 11 is turned on in either case where data "1" or data "0" is written in the memory cell 10 not to be read.

[0108] Also, a read potential (for example, VDD) is applied to the wiring RBL. When the transistor 11 of the memory cell 10 to be read is turned on, the wiring RBL and the wiring SL are conducted and the potential of the wiring RBL drops. On the contrary, the transistor of the memory cell 10 to be read 11 is turned on.

[0109] Also, a read potential (for example, VDD) is applied to the wiring RBL. When the transistor 11 of the memory cell 10 to be read is in the on state, the wiring RBL and the wiring SL are conductive and the potential of the wiring RBL drops. In contrast, for the transistor of the memory cell 10 to be read 11 ​​When the switch 11 is in the off state, the wiring RBL and the wiring SL are not conductive, so the read potential of the wiring RBL is maintained. In this way, the data of the memory cell to be read can be read from the change in the read potential of the wiring RBL.

[0110] Also, as a driving method, it is preferable to provide a batch erasing operation of data for each block. For example, the two-dimensional memory cell array 30 may be regarded as one block. In this case, the selection of the two-dimensional memory cell array 30 for batch erasing of data may be performed in the same manner as the data writing. By turning on the wiring WWL connected to the two-dimensional memory cell array 30, the data of one block can be erased in a batch.

[0111] FIG. 7 shows an example of a timing chart related to the detailed operation of the semiconductor device according to FIG. 2. The timing chart shown in FIG. 7 shows the potential relationships of each wiring for the batch erasing of the two-dimensional memory cell array 30[1], the writing of the first row of the two-dimensional memory cell array 30[1], and the reading of the first row of the two-dimensional memory cell array 30 [1]. The batch erasing of the two-dimensional memory cell array 30[1] is an operation of erasing the data written in the memory cells 10(1,1,1) to (m ,m 1 ,m 2 ,1) of the two-dimensional memory cell array 30[1]. The writing of the first row of the two-dimensional memory cell array 30[1] is an operation of writing the data "1" into the memory cell at the first row and first column of the two-dimensional memory cell array 30 [1], and writing the data "0" into the memory cells of the other columns ( the second column to the m th column) of the first row. The reading of the first row of the two-dimensional memory cell array 30[1] is the first row of the two-dimensional memory cell array 30[1]. 1 ​​​​​​ This is an operation to read the data written in the eye. In this reading, the first row and the first column of the memory cell has the data "1", and the other columns (the second column to the m 1 th column) of the first row of the memory cell have the data "0" stored.

[0112] It is assumed that the read circuit 52 is provided with the read circuit shown in FIG. 6(A).

[0113] In the bulk erasure of the two-dimensional memory cell array 30[1], first, a potential V1 is applied to the wiring SG2[1] to turn on the transistors 62 of the selection transistor cells 60(1,1) to (m ,1), and the wirings WBL[1] to [m 1 are made conductive with the corresponding wirings WBL[1,1 to [m 1 . Also, the wirings SG2[2] to [m are set to GND to turn off the transistors 62 of the selection transistor cells 60(1,2) to (m 1 ,m 3 ), and the wirings WBL[1] to [m are made non-conductive with the corresponding wirings WBL[1,2] to [m 1 ,m 3 . In this way, the two-dimensional me mory cell array 30[1] is selected as the target of the bulk erasure operation. 1 are made non-conductive with the corresponding wirings WBL[1,2] to [m 1 ,m 3 . In this way, the two-dimensional memory cell array 30[1] is selected as the target of the bulk erasure operation.

[0114] In the two-dimensional memory cell array 30[1], a potential V3 is applied to the wirings WWL[1,1] to the wiring WWL m 2 ,1] to turn on the transistors 12 of the first row to the m 2 th row, and at the same time, the wirings WBL[1] to [m are set to GND to turn off the transistors 12 of the first row to the m 1 rows 2 ​​Node F of the row Set the potential of N to GND.

[0115] Note that the wiring WW 3 electrically connected to the two-dimensional memory cell array 30[2] to [m L[1,2] to [m 2 , m 3 is set to GND, and the potential of the node FN of the memory cells 10(1,1,2) to ([[]] m 1 , m 2 , m 3 ) is held.

[0116] In the first row writing of the two-dimensional memory cell array 30[1], first, the two-dimensional memory cell array 30[1] is selected as the target of the writing operation by the same operation as the bulk erasure of the two-dimensional memory cell array 30[1].

[0117] In the two-dimensional memory cell array 30[1], apply the potential V3 to the wiring WWL[1,1] to turn on the transistor 12 in the first row, and set the wiring WWL[2,1] to [m 2 ,1] to GND to turn off the transistors 12 in the second row to the m 2 th row. At this time, apply the potential V2 to the wiring WBL[1], and set the wiring WBL[2] to [m 1 to GND. Also , the wiring RWL[1,1] to [m 2 ,1] may be set to GND.

[0118] As a result, the potential V2 is applied to the node FN of the memory cell 10 in the first row and first column of the two-dimensional memory cell array 30[1], that is, the data "1" is written. Also , 0V 1 is applied to the nodes FN in the first row and second column to the m th column of the two-dimensional memory cell array 30[1], that is, the data "0" is written.

[0119] Note that, similar to the bulk erasure of the two-dimensional memory cell array 30[1], the two-dimensional memory cell array 30[2] to [m 3 and the wiring WWL[1,2] to [m 2 ,m 3 are grounded, and the nodes F 1 ,m 2 ,m 3 ) of the memory cells 10(1,1,2) to [m N hold the potential.

[0120] In the first row readout of the two-dimensional memory cell array 30[1], first, a potential V1 is applied to the wiring SG1 1] to turn on the transistors 61 of the selection transistor cells 60(1,1) to [m 1 ,1), and the wiring RBL[1] to [m is made conductive with the corresponding wiring RBL 1 1,1] to [m 1,1] to [m 1 ,1]. Also, the wiring SG1[2] to [m 3 is grounded as G ND to turn off the transistors 6 1 ,m 3 ) of the selection transistor cells 60(1,2) to [m 1, and the wiring RBL[1] to [m 1 is made non-conductive with the corresponding wiring RBL[1,2] to [m 1 ,m 3 and left in that state. In this way, the two-dimensional memory cell array 30[1] is selected as the target of the read operation. In the two-dimensional memory cell array 30[1], the wiring RWL[1,1] connected to the memory cell 10 of the first row to be read is grounded. Also, for the memory cells

[0121] that are not the read targets, the wiring RWL[2,1] to [m connected to the memory cells 10 is grounded, and for the memory cells 10 that are not the read targets, the wiring RWL[2,1] to [m 2,1] Apply a potential V4 to turn on the transistor 11 of the memory cell 10.

[0122] Here, connect the bias potential Vbias of the read circuit shown in Fig. 6(A) from the potential Vdd to the wiring to which the power supply potential Vdd is supplied as G ND and the wiring RBL.

[0123] As a result, the wiring RBL[1] connected to the memory cell 10(1,1,1 ) in which the data "1" is written to the memory cell 10 conducts with the wiring SL[1,1] and the potential drops. Also , the wiring RBL[2] to [m 1 ,1,1) connected to the memory cell 10(2,1,1) to which the data "0" is written to the memory cell 10 1 is non-conductive with the wiring SL[2,1] to m 1 ,1] and thus becomes the potential Vdd.

[0124] Note that the wiring WWL[1,1] to [m 2 ,m 3 is set to GND to hold the potential of the node FN of the memory cell 10(1 ,1,1) to (m 1 ,m 2 ,m 3 ).

[0125] Note that the above description is for the case of using an n-type transistor with electrons as carriers. However, instead of the n-type transistor, a p-type transistor with holes as carriers may be used. In this case, since the operation of the transistor is inverted, the applied potential may be appropriately set.

[0126] Note that in the above method of driving the semiconductor device, the case of writing a binary (1-bit) data to the memory cell has been described. However, when writing information of three or more levels to the memory cell, ​ A multi-valued approach may be adopted. For example, the memory cell may be configured to hold data such as 4 values (2 bits), 8 values (3 bits ), 16 values (4 bits), etc.

[0127] In the semiconductor device shown in this embodiment, since the transistor using an oxide semiconductor has an extremely small off-current, it is possible to hold the memory content for an extremely long period by using this transistor. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Moreover, even when there is no power supply (however, it is desirable that the potential is fixed), it is possible to hold the memory content for a long period. Also, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of element degradation. For example, unlike conventional non-volatile memories, since it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate,

[0128] problems such as degradation of the gate insulating layer due to electron extraction do not occur. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which has been a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can also be easily realized.

[0129] In addition, since a transistor using a material other than an oxide semiconductor can operate at a sufficiently high speed, by combining this with a transistor using an oxide semiconductor, a half

[0129] Moreover, since a transistor using a material other than an oxide semiconductor can achieve sufficiently high-speed operation, by using this in combination with a transistor using an oxide semiconductor, a semi The high speed of the operation of the conductor device (for example, the information reading operation) can be sufficiently ensured. . Further, each type of circuit (logic circuit, drive circuit, etc.) that requires high-speed operation can be preferably realized by a transistor using a material other than an oxide semiconductor.

[0130] In this way, by integrally providing a transistor using a material other than an oxide semiconductor (more broadly, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (more broadly, a transistor having a sufficiently small off-current), a semiconductor device having unprecedented characteristics can be realized.

[0131] Furthermore, in the semiconductor device shown in this embodiment, by laminating memory cells, the storage capacity per unit area can be increased according to the number of laminations. Therefore, good characteristics as described above can be obtained in the memory cell, and furthermore, a semiconductor device having a storage capacity per unit area equal to or larger than that of a conventional memory can be provided. Also, in the semiconductor device shown in this embodiment, by laminating memory cells in this way to increase the storage capacity per unit area, it is also possible to provide a storage device having a storage capacity of 1 TByte or more, 5 TByte or more, 10 TByte or more.

[0132] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0133] (Embodiment 2) In this embodiment, the configuration of the semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 8 to 14.

[0134] <Configuration of Memory Cell> First, the configuration of the memory cell 10 shown in the previous embodiment will be described with reference to FIGS. 8(A) to (C).

[0135] The memory cell 10 shown in FIGS. 8(A) to 8(C) includes a transistor 11, a transistor 12, and a capacitive element 14. FIG. 8(A) is a top view of the memory cell 10. FIG. 8(B ) is a cross-sectional view corresponding to the dashed line A1 - A2 in FIG. 8(A), and FIG. 8(C) is a cross-sectional view corresponding to the dashed line A3 - A4 in FIG. 8(A). Note that the region indicated by the dashed line A1 - A2 shows the structure in the channel length direction of the transistor 12, and the region indicated by the dashed line A3 - A4 shows the structure in the channel width direction of the transistor 12. Note that the channel length direction of the transistor 12 means the direction in which carriers move between the source (source region or source electrode) and the drain (drain region or drain electrode), and the channel width direction of the transistor 12 means the direction perpendicular to the channel length direction in a plane parallel to the substrate.

[0136] Here, it is desirable that the semiconductor material of the transistor 11 is different from the semiconductor material of the transistor 12. For example, the semiconductor material of the transistor 11 can be a semiconductor material other than an oxide semiconductor (such as silicon), and the semiconductor material of the transistor 12 can be an oxide semiconductor. Transistors using materials other than oxide semiconductors such as polycrystalline silicon are easy to operate at high speed. On the other hand, transistors using oxide semiconductors can hold charges for a long time due to their characteristics.

[0137] ​Note that all of the above transistors are described as n-channel transistors. However, it goes without saying that p-channel transistors can also be used. In addition, the technical essence of the disclosed invention lies in using a semiconductor material such as an oxide semiconductor, which can sufficiently reduce the off-current, in the transistor 12 to hold information. Therefore, the specific configuration of the semiconductor device, such as the material used in the semiconductor device and the structure of the semiconductor device, does not need to be limited to what is shown here. The transistor 11 has a conductor 108b, an insulator 132, a semiconductor 134, and an insulator 136. The insulator 132, the semiconductor 134, and the insulator 136 are formed in a cylindrical opening provided in the insulator 104, the conductor 108b, the insulator 116, and the insulator 118. The insulator 132 is formed in a cylindrical shape in contact with the inner wall of the opening. The semiconductor 134 is formed in a cylindrical shape inside the insulator 132, and the insulator 136 is formed in a cylindrical shape inside the semiconductor 134. The insulator 132, the semiconductor 134, and the insulator 136 are formed to extend substantially perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. Note that the insulator 136 may not be provided inside the semiconductor 134, and a columnar semiconductor 134 may be provided inside the insulator 132. Here, the conductor 108b functions as the gate of the transistor 11, the insulator 132 functions as the gate insulating film of the transistor 11, and the semiconductor 134 functions as the active layer, source, and drain of the transistor 11. In the semiconductor 134, the region 134a overlapping with the conductor 108b functions as the channel formation region of the transistor 11. There is no need to limit it to what is shown here.

[0138] The transistor 11 has a conductor 108b, an insulator 132, a semiconductor 134, and an insulator 136. The insulator 132, the semiconductor 134, and the insulator 136 are formed in a cylindrical opening provided in the insulator 104, the conductor 108b, the insulator 116, and the insulator 118. The insulator 132 is formed in a cylindrical shape in contact with the inner wall of the opening. The semiconductor 134 is formed in a cylindrical shape inside the insulator 132, and the insulator 136 is formed in a cylindrical shape inside the semiconductor 134. The insulator 132, the semiconductor 134, and the insulator 136 are formed to extend substantially perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. Note that the semiconductor 134 The insulator 132, the semiconductor 134, and the insulator 136 are formed to extend substantially perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. Note that the semiconductor 134 The insulator 132, the semiconductor 134, and the insulator 136 are formed to extend substantially perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. Note that the semiconductor 134 The insulator 132, the semiconductor 134, and the insulator 136 are formed to extend substantially perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. Note that the semiconductor 134 The insulator 136 may not be provided inside the semiconductor 134, and a columnar semiconductor 134 may be provided inside the insulator 132. This configuration is also acceptable.

[0139] Here, the conductor 108b functions as the gate of the transistor 11, the insulator 132 functions as the gate insulating film of the transistor 11, and the semiconductor 134 functions as the active layer, source, and drain of the transistor 11. In the semiconductor 134, the region 134a overlapping with the conductor 108b functions as the channel formation region of the transistor 11. 11 of the active layer, source, and drain functions. In the semiconductor 134, the region 134a overlapping with the conductor 108b functions as the channel formation region of the transistor 11. In the semiconductor 134, the region 134a overlapping with the conductor 108b functions as the channel formation region of the transistor 11. A region 134b that does not overlap with the conductor 108b functions as the source or drain of the transistor 11. It functions in this way.

[0140] In this way, the transistor 11 is an SGT in which a conductor 108b that functions as a gate electrode is formed so as to surround the periphery of the region 134a of the semiconductor 134 via the insulator 132. In the semiconductor 134 of the transistor 11, a region 134a that functions as a channel formation region is located at the same height as the conductor 108b, and regions 134b that function as a source or drain are located above and below the conductor 108b. Therefore, the channel length of the transistor 11 is approximately the same as the film thickness of the conductor 108b. Also, the channel length direction of the transistor 11 is substantially perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. Further, as shown in FIG. 8(B), the channel length direction of the transistor 11 is substantially perpendicular to the channel length direction of the transistor 12. Also, the channel width of the transistor 11 is approximately the same as the circumferential length of the cylindrical semiconductor 134. In the semiconductor 134 of the transistor 11, a region 134a that functions as a channel formation region is located at the same height as the conductor 108b, and regions 134b that function as a source or drain are located above and below the conductor 108b. Thus, the channel length of the transistor 11 is approximately the same as the film thickness of the conductor 108b. Also, the channel length direction of the transistor 11 is substantially perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. Also, as shown in FIG. 8(B), the channel length direction of the transistor 11 is substantially perpendicular to the channel length direction of the transistor 12. Also, the channel width of the transistor 11 is approximately the same as the circumferential length of the cylindrical semiconductor 134. 8(B), the channel length direction of the transistor 11 is substantially perpendicular to the channel length direction of the transistor 12. Also, the channel width of the transistor 11 is approximately the same as the circumferential length of the cylindrical semiconductor 134. It becomes approximately the same length.

[0141] In a standard planar-type transistor, a gate electrode, a source electrode, and a drain electrode are formed as seen from the upper surface, and the occupied area is about 8F. On the other hand, in the SGT-type transistor 11, as seen from the upper surface, other components are formed inside the gate electrode, and the occupied area is very small, about 4F. 2 Thus, the transistor 11 can make the occupied area very small. As a result, the occupied area of the memory cell 10 can be reduced, and the storage capacity per unit area of the semiconductor device can be increased. In this way, the occupied area of the transistor 11 can be made very small. 2 This enables the reduction of the occupied area of the memory cell 10 and an increase in the storage capacity per unit area of the semiconductor device. This can reduce the occupied area of the memory cell 10 and increase the storage capacity per unit area of the semiconductor device. By this, the occupied area of the memory cell 10 can be reduced, and the storage capacity per unit area of the semiconductor device can be increased.

[0142] Note that, like the transistor 11 in FIG. 8, there may be cases where the source electrode and the drain electrode are not explicitly provided. For the sake of convenience, such a state may be referred to as a transistor including this case. .

[0143] Note that the opening in which the transistor 11 is provided has a circular upper surface in FIG. 8(A), but it is not limited to this. For example, the upper surface may be elliptical, or may be polygonal such as triangular or quadrilateral. Also, when it is polygonal, the corners may be rounded. Further, in accordance with the upper surface shape of the opening, the upper surface shapes of the insulator 132, the semiconductor 134, and the insulator 136 may also change. Also, the opening may have a shape in which the cross-sectional area perpendicular to the y-axis of the opening on the lower side (semiconductor substrate 150 side) is smaller than the cross-sectional area perpendicular to the y-axis of the opening on the upper side (insulator 170 side).

[0144] The transistor 12 includes an insulator 106a formed on the insulator 104, a semiconductor 106b formed in contact with at least a part of the upper surface of the insulator 106a, an insulator 106c formed in contact with at least a part of the upper surface of the semiconductor 106b, conductors 108a and 108b electrically connected to the semiconductor 106b, an insulator 112 formed on the insulator 106c, and a conductor 114 formed on the insulator 112 and formed so as to be located at least partly between the conductor 108a and the conductor 108b. Also, an insulator 116 is formed on the insulator 106a, the semiconductor 106b, the conductor 108a, and the conductor 108b, and an insulator 118 is formed on the insulator 116.

[0145] The transistor 12 is provided with an opening reaching the semiconductor 106b in the insulator 118, and the opening An opening is provided such that an insulator 106c, an insulator 112, and a conductor 114 are embedded therein. Also, due to the opening, the conductor 108a and the conductor 108b are separated from each other. In the transistor 12, the conductor 114 that functions as a gate electrode is self - aligningly formed so as to fill an opening formed by an insulator 118 or the like. Therefore, it can also be called a TGSA s - channel FET (Trench Gate Self Align s - channel FET). In the transistor 12, the upper surfaces of the insulator 118, the insulator 106c, the insulator 112, and the conductor 114 are substantially aligned and are provided flat. This is because the upper surfaces of the insulator 117, the insulator 106c, the insulator 112, and the conductor 114 are planarized by a CMP method or the like. As a result, a region where the conductor 114 overlaps with the conductor 108a and the conductor 108b is hardly formed, so that the parasitic capacitance generated between the gate and the source, and between the gate and the drain of the transistor 24 can be reduced.

[0146]

[0147] Also, as shown in FIG. 8(C), the insulator 106c is preferably provided so as to cover the side surfaces of the insulator 106a and the semiconductor 106b in the channel width direction. Thereby, a continuous junction is formed between the insulator 106a or the insulator 106c and the side surface end portion in the channel width direction of the semiconductor 106b, and the density of defect levels is reduced. Therefore, even if on - currents flow easily by providing the low - resistance regions 109a and 109b, the side surface end portions in the channel width direction of the semiconductor 106b do not become parasitic channels, and stable electrical characteristics can be obtained. ​​​​​​​​​​​​

[0148] Here, the conductor 108a functions as one of the source or drain of the transistor 12 and the conductor 108b functions as the other of the source or drain of the transistor 12 The insulator 112 functions as a gate insulating film of the transistor 12, and the conductor 11 4 functions as a gate of the transistor 12

[0149] Note that in FIGS. 8(B) and 8(C), the insulator 106a and the semiconductor 106b are formed such that the ends thereof generally coincide. However, the configuration of the semiconductor device shown in this embodiment is not limited to this

[0150] Also, a columnar conductor 120 is formed in the columnar openings provided in the insulator 104, the conductor 108a, the insulator 116, and the insulator 118. That is, the conductor 120 is electrically connected to the conductor 108a. The conductor 120 is formed to extend substantially perpendicular to the upper surface of the substrate on which the memory cell 10 is provided . Note that the conductor 120 may be formed in a cylindrical shape, and the opening of the conductor 120 may be filled with an insulator

[0151] Note that the opening in which the conductor 120 is provided has a circular upper surface in FIG. 8(A) but is not limited to this. For example, the upper surface may be elliptical, or may be a polygonal shape such as a triangle or a quadrilateral . Also, when it is a polygonal shape, the corners may be rounded . Also, the upper surface shape of the conductor 120 may change according to the upper surface shape of the opening . Also, the opening may have a shape in which the cross-sectional area of the lower opening (on the semiconductor substrate 150 side) is smaller than the cross-sectional area of the upper opening (on the insulator 170 side) ​​​

[0152] The capacitive element 14 includes a conductor 108b, an insulator 116, and a conductor 122. The con ductor 108b functions as one of the electrodes of the capacitive element 14, and the conductor 122 functions as the other electrode of the capacitive element 14. The insulator 116 may function as a dielectric of the capacitive element 14, and it may be formed at least in a region where the conductor 108b and the conductor 122 overlap.

[0153] As described above, the conductor 108b functions as a gate in the transistor 11, functions as one of the source or drain in the transistor 12, and functions as one of the electrodes in the capacitive element 14. That is, the conductor 108b functions as the node FN shown in FIGS. 1(A) and 1(B). Also, the wiring WBL shown in FIGS. 1(A) and 1(B) corresponds to the conductor 120, the wiring WWL corresponds to the conductor 114, and the wiring RWL corresponds to the conductor 122. Further, the semiconductor 134 is provided in an extended manner and is electrically connected to the conductor corresponding to the wiring SL and the conductor corresponding to the wiring RBL.

[0154] Here, the insulators 104, 106a, 106c, 112, 11 6, 118, 132, and 136 may also be referred to as insulating films or insulating layers. Also, the conductors 108a, 108b, 114, 120, and conductor 122 may also be referred to as conductive films or conductive layers. Further, the semiconductors 106b and 13 4 may also be referred to as semiconductor films or semiconductor layers.

[0155] Note that, although details will be described later, the insulators 106a and 106c, when used alone ​​​​​​​​、There are cases where substances that can function as conductors, semiconductors, or insulators are used. However, when forming a transistor by laminating with semiconductor 106b, electrons flow through semiconductor 106b, near the interface between semiconductor 106b and insulator 106a, and near the interface between semiconductor 106b and insulator 106c, and insulators 106a and 106c have regions that do not function as the channel of the transistor. For this reason, in this specification and the like, insulators 1 06a and insulator 106c are not described as conductors and semiconductors, but are described as insulators.

[0156] <Semiconductor of Transistor 11> Hereinafter, the detailed configuration of semiconductor 134 will be described.

[0157] As semiconductor 134, for example, crystalline silicon such as polycrystalline silicon or single-crystalline silicon can be used. However, it is not limited to this, and microcrystalline silicon, amorphous silicon, etc. can also be used, and it is not limited to silicon, and germanium, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can also be used. In addition, a semiconductor that can be used for semiconductor 106b described later may be used.

[0158] When using polycrystalline silicon as semiconductor 134, it is preferable to reduce the film thickness of semiconductor 134. For example, it is preferably 20 nm or less, more preferably 10 nm or less. Thereby, variations in the characteristics of transistor 11 can be suppressed.

[0159] Also, when using polycrystalline silicon or the like as semiconductor 134, hydrogen is supplied to semiconductor 134. ​​​It may also be configured to terminate the dangling bonds in the semiconductor 134.

[0160] Further, the semiconductor 134 may contain an impurity that imparts a p-type conductivity or an impurity that imparts an n-type conductivity. Examples of the impurity that imparts a p-type conductivity include boron (B), aluminum (Al), etc. Examples of the impurity that imparts an n-type conductivity include phosphorus, arsenic, etc. may be used.

[0161] <Insulator of Transistor 11> Hereinafter, the detailed configurations of the insulator 132 and the insulator 136 will be described.

[0162] As the insulator 132, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used alone or in a stacked layer. For example, as the insulator 112, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used. In this specification, etc., silicon oxynitride refers to a composition in which the nitrogen content is higher than the oxygen content, and silicon nitride oxide refers to a composition in which the oxygen content is higher than the nitrogen content. refers to.

[0163] The insulator 132 preferably has an effect of blocking hydrogen, water, alkali metals, alkaline earth metals, etc. As such an insulator, for example, a nitride insulating film may be used. ​ can be formed. Examples of the nitride insulating film include silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. Instead of the nitride insulating film, an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc. may be provided. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc.

[0164] Particularly, when the dangling bonds of the semiconductor 134 are terminated with hydrogen, if the insulator 132 has an effect of blocking hydrogen and water, diffusion of the hydrogen into the semiconductor 106b can be suppressed. As will be described in detail later, when hydrogen is incorporated into the oxide semiconductor used for the semiconductor 106b, the electrical characteristics of the transistor 12 may deteriorate. In other words, by using an insulator 132 having an effect of blocking hydrogen and water, the electrical characteristics of the transistor 12 can be stabilized.

[0165] Basically, an insulator that can be used as the insulator 132 may be used as the insulator 136. However, when the dangling bonds of the semiconductor 134 are terminated with hydrogen, hydrogen may be included in the insulator 136 to supply hydrogen to the semiconductor 134. In this case, for example, silicon nitride containing hydrogen may be used as the insulator 136.

[0166] <Semiconductor of Transistor 12> Hereinafter, the detailed configuration of the semiconductor 106b will be described. In this section, the detailed configurations of the insulator 106a and the insulator 106c together with the semiconductor 106b will also be described.

[0167] The semiconductor 106b is, for example, an oxide semiconductor containing indium. The semiconductor 106b , for example, when containing indium, has a high carrier mobility (electron mobility). Also, the semi- conductor 106b preferably contains an element M. The element M preferably represents Ti, Ga, Y, Zr , La, Ce, Nd, Sn or Hf. However, there may be cases where a plurality of the aforementioned elements are combined as the element M. The element M is, for example, an element with a high binding energy with oxygen. For example, it is an element with a binding energy with oxygen higher than that of indium . Or, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor . Also, the semiconductor 106b preferably contains zinc. The oxide semiconductor may be more likely to crystallize when containing zinc .

[0168] However, the semiconductor 106b is not limited to an oxide semiconductor containing indium. The semiconductor 1 06b may be, for example, an oxide semiconductor that does not contain indium, such as zinc tin oxide, gallium tin oxide, etc., and contains zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, etc. and may be acceptable.

[0169] For example, the insulator 106a and the insulator 106c are oxide semiconductors composed of one or more elements other than oxygen that constitute the semiconductor 106b. Since the insulator 106a and the insulator 106c are composed of one or more elements other than oxygen that constitute the semiconductor 106b, at the interface between the insulator 10 6a and the semiconductor 106b, and at the interface between the semiconductor 106b and the insulator 106c , defect levels are less likely to be formed.

[0170] The insulator 106a, the semiconductor 106b, and the insulator 106c preferably contain at least indium. When the insulator 106a is an In-M-Zn oxide, when the sum of In and M is 100 atomic %, preferably In is less than 50 atomic %, M is higher than 50 atomic %, and more preferably In is less than 25 atomic %, M is higher than 75a tomic %. When the semiconductor 106b is an In-M-Zn oxide, when the sum of I n and M is 100 atomic %, preferably In is higher than 25 atomic %, M is less than 75 atomic %, and more preferably In is higher than 34 atomic %, M is less than 66 atomic %. When the insulator 106c is an In-M-Zn oxide, when the sum of In and M is 100 atomic %, preferably In is less than 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 less than 5 atomic %, M is higher than 75 atomic %. Note that the insulator 106c may use the same type of oxide as the insulator 106a. However, the insulator 106a or / and the insulator 106c may not contain indium. For example, the insulator 106a or / and the insulator 106c may be gallium oxide or a Ga-Zn oxide and it doesn't matter. Note that the atomic numbers of the respective elements contained in the insulator 106a, the semiconductor 106b, and the insulator 106c do not have to be in a simple integer ratio.

[0171] For example, when forming a film using the sputtering method, representative examples of the atomic number ratio of the metal elements of the target used for the insulator 106a or the insulator 106 c are In:M:Zn = 1:2 :4. The atomic ratios of In:M:Zn are 1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:3, 1:4:4, 1:4:5, 1:4:6, 1:6:3, 1:6:4, 1:6:5, 1:6:6, 1:6:7, 1:6:8, 1:6:9, 1:10:1, etc. Also, the atomic ratio of the metal elements of the target used for the insulator 106a or the insulator 106c may be M:Zn = 10:1. :3:6, In:M:Zn = 1:3:8, In:M:Zn = 1:4:3, In:M:Zn = 1:4:4, In:M:Zn = 1:4:5, In:M:Zn = 1:4:6, In:M: Zn = 1:6:3, In:M:Zn = 1:6:4, In:M:Zn = 1:6:5, In: M:Zn = 1:6:6, In:M:Zn = 1:6:7, In:M:Zn = 1:6:8, I n:M:Zn = 1:6:9, In:M:Zn = 1:10:1, etc. Also, the insulator 10 6a or the atomic ratio of the metal elements of the target used for the insulator 106c may be M:Zn = 10: 1.

[0172] Also, for example, when forming a film using a sputtering method, representative examples of the atomic ratio of the metal elements of the target used for the semiconductor 106b include In:M:Zn = 1:1:1, In:M :Zn = 1:1:1.2, In:M:Zn = 2:1:1.5, In:M:Zn = 2:1: 2.3, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, etc. In particular, when using a sputtering target with an atomic ratio of In:Ga:Zn = 4:2:4.1, the atomic ratio of the formed semiconductor 106b may be in the vicinity of In:Ga:Zn = 4:2:3. Note that indium gallium oxide has a small electron affinity and high oxygen blocking properties. Therefore, it is preferable that the insulator 106c contains indium gallium oxide. The gallium atomic ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more.

[0173] ​​​​​Preferably, it is 90% or more.

[0174] The semiconductor 106b uses, for example, an oxide having a large energy gap. The semiconductor 10 The energy gap of 6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2. 8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3.5 eV or less. Here , the energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b . Also, the energy gap of the insulator 106c is larger than the energy gap of the semiconductor 106b .

[0175] The semiconductor 106b uses an oxide having a larger electron affinity than the insulator 106a or the insulator 106c . For example, as the semiconductor 106b, an oxide having an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than those of the insulator 106a and the insulator 106c is used. Note that the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band. In other words, the energy level of the lower end of the conduction band of the insulator 106a or the insulator 106c is closer to the vacuum level than the energy level of the lower end of the conduction band of the semiconductor 106b. , the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band. In other words, the energy level of the lower end of the conduction band of the insulator 106a or the insulator 106c is closer to the vacuum level than the energy level of the lower end of the conduction band of the semiconductor 106b. At this time, when a gate voltage is applied, a channel is formed in the semiconductor 106b having a large electron affinity among the insulator 106a, the semiconductor 106b, and the insulator 10 6c. Note that when a high gate voltage is applied, current may flow also in the vicinity of the interface between the insulator 106a and the semiconductor 106b and in the vicinity of the interface between the insulator 10

[0176] 6c and the semiconductor 106b. 6c. Note that when a high gate voltage is applied, current may flow also in the vicinity of the interface between the insulator 106a and the semiconductor 106b and in the vicinity of the interface between the insulator 10 6c and the semiconductor 106b. In this case, when a gate voltage is applied, a channel is formed in the semiconductor 106b having a large electron affinity among the insulator 106a, the semiconductor 106b, and the insulator 106c. Note that when a high gate voltage is applied, current may flow also in the vicinity of the interface between the insulator 106a and the semiconductor 106b and in the vicinity of the interface between the insulator 106c and the semiconductor 106b.

[0177] As described above, when the insulators 106a and 106c are used alone, they are made of a material that can function as a conductor, a semiconductor, or an insulator. However, when stacked with the semiconductor 106b to form a transistor, electrons flow through the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c, and the insulators 106a and 106c have regions that do not function as the channel of the transistor. Therefore, in this specification and the like, the insulators 106a and 106c are not described as semiconductors, but are described as insulators. Note that the reason for describing the insulators 106a and 106c as insulators is that they have a function closer to that of an insulator in terms of the function of the transistor compared to the semiconductor 106b. Therefore, in some cases, a material that can be used for the semiconductor 106b may be used for the insulator 106a or the insulator 106c. and are made of a substance that can function as a conductor, a semiconductor, or an insulator. However, when stacked with the semiconductor 106b to form a transistor, electrons flow through the semiconductor 106b, the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c, and the insulators 106a and 106c have regions that do not function as the channel of the transistor. Therefore, in this specification and the like, the insulators 106a and 106c are not described as semiconductors, but are described as insulators. Note that the reason for describing the insulators 106a and 106c as insulators is that they have a function closer to that of an insulator in terms of the function of the transistor compared to the semiconductor 106b. Therefore, in some cases, a material that can be used for the semiconductor 106b may be used for the insulator 106a or the insulator 106c. through the semiconductor 106b, the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c, and the insulators 106a and 106c have regions that do not function as the channel of the transistor. Therefore, in this specification and the like, the insulators 106a and 106c are not described as semiconductors, but are described as insulators. Note that the reason for describing the insulators 106a and 106c as insulators is that they have a function closer to that of an insulator in terms of the function of the transistor compared to the semiconductor 106b. Therefore, in some cases, a material that can be used for the semiconductor 106b may be used for the insulator 106a or the insulator 106c. Note that the reason for describing the insulators 106a and 106c as insulators is that they have a function closer to that of an insulator in terms of the function of the transistor compared to the semiconductor 106b. Therefore, in some cases, a material that can be used for the semiconductor 106b may be used for the insulator 106a or the insulator 106c. Note that the reason for describing the insulators 106a and 106c as insulators is that they have a function closer to that of an insulator in terms of the function of the transistor compared to the semiconductor 106b. Therefore, in some cases, a material that can be used for the semiconductor 106b may be used for the insulator 106a or the insulator 106c. Note that the reason for describing the insulators 106a and 106c as insulators is that they have a function closer to that of an insulator in terms of the function of the transistor compared to the semiconductor 106b. Therefore, in some cases, a material that can be used for the semiconductor 106b may be used for the insulator 106a or the insulator 106c. Note that the reason for describing the insulators 106a and 106c as insulators is that they have a function closer to that of an insulator in terms of the function of the transistor compared to the semiconductor 106b. Therefore, in some cases, a material that can be used for the semiconductor 106b may be used for the insulator 106a or the insulator 106c. Note that the reason for describing the insulators 106a and 106c as insulators is that they have a function closer to that of an insulator in terms of the function of the transistor compared to the semiconductor 106b. Therefore, in some cases, a material that can be used for the semiconductor 106b may be used for the insulator 106a or the insulator 106c.

[0178] Here, there may be a mixed region between the insulator 106a and the semiconductor 106b. Also, there may be a mixed region between the semiconductor 106b and the insulator 106c. The mixed region has a lower density of defect levels. Therefore, the laminate of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface. Note that in some cases, the interface between the insulator 106a and the semiconductor 106b, or the interface between the insulator 106c and the semiconductor 106b may not be clearly distinguishable. Here, there may be a mixed region between the insulator 106a and the semiconductor 106b. Also, there may be a mixed region between the semiconductor 106b and the insulator 106c. The mixed region has a lower density of defect levels. Therefore, the laminate of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface. Note that in some cases, the interface between the insulator 106a and the semiconductor 106b, or the interface between the insulator 106c and the semiconductor 106b may not be clearly distinguishable. Here, there may be a mixed region between the insulator 106a and the semiconductor 106b. Also, there may be a mixed region between the semiconductor 106b and the insulator 106c. The mixed region has a lower density of defect levels. Therefore, the laminate of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface. Note that in some cases, the interface between the insulator 106a and the semiconductor 106b, or the interface between the insulator 106c and the semiconductor 106b may not be clearly distinguishable. Here, there may be a mixed region between the insulator 106a and the semiconductor 106b. Also, there may be a mixed region between the semiconductor 106b and the insulator 106c. The mixed region has a lower density of defect levels. Therefore, the laminate of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface. Note that in some cases, the interface between the insulator 106a and the semiconductor 106b, or the interface between the insulator 106c and the semiconductor 106b may not be clearly distinguishable. Here, there may be a mixed region between the insulator 106a and the semiconductor 106b. Also, there may be a mixed region between the semiconductor 106b and the insulator 106c. The mixed region has a lower density of defect levels. Therefore, the laminate of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface. Note that in some cases, the interface between the insulator 106a and the semiconductor 106b, or the interface between the insulator 106c and the semiconductor 106b may not be clearly distinguishable. Here, there may be a mixed region between the insulator 106a and the semiconductor 106b. Also, there may be a mixed region between the semiconductor 106b and the insulator 106c. The mixed region has a lower density of defect levels. Therefore, the laminate of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface. Note that in some cases, the interface between the insulator 106a and the semiconductor 106b, or the interface between the insulator 106c and the semiconductor 106b may not be clearly distinguishable. Here, there may be a mixed region between the insulator 106a and the semiconductor 106b. Also, there may be a mixed region between the semiconductor 106b and the insulator 106c. The mixed region has a lower density of defect levels. Therefore, the laminate of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface. Note that in some cases, the interface between the insulator 106a and the semiconductor 106b, or the interface between the insulator 106c and the semiconductor 106b may not be clearly distinguishable.

[0179] At this time, electrons do not flow in the insulator 106a and the insulator 106c, but in the semiconductor 106b. It mainly moves inside. As described above, at the interface between the insulator 106a and the semiconductor 106b the density of defect energy levels, and at the interface between the semiconductor 106b and the insulator 106c by reducing the density of defect energy levels, the movement of electrons in the semiconductor 106b is less inhibited, and the on-current of the transistor can be increased.

[0180] Also, the on-current of the transistor can be increased as the factors inhibiting the movement of electrons are reduced. For example, when there are no factors inhibiting the movement of electrons, it is estimated that electrons move efficiently. The movement of electrons is inhibited, for example, when the physical unevenness in the channel formation region is large.

[0181] To increase the on-current of the transistor, for example, the root mean square (RMS) roughness in the range of 1 μm × 1 μm on the upper surface or the lower surface (the surface to be formed, here the upper surface of the insulator 106a) of the semiconductor 106b should be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Also, the average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm should be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Also, the maximum height difference (also referred to as P-V) in the range of 1 μm × 1 μm should be less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. The RMS roughness, Ra, and P-V can be measured using a scanning probe microscope system SPA-500 manufactured by SII NanoTechnology Inc., etc.

[0182] Also, in order to increase the on-current of the transistor, it is preferable that the thickness of the insulator 106c be as small as possible. The thickness of the insulator 106c is preferably smaller than the thickness of the insulator 106a and smaller than the thickness of the semiconductor 106 b. For example, an insulator 106c having a region of less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less may be used. On the other hand, the insulator 1 06c has a function of blocking elements other than oxygen (such as hydrogen and silicon) that make up the adjacent insulator from entering the semiconductor 106 where the channel is formed. Therefore it is preferable that the insulator 106c has a certain thickness. For example, an insulator 10 having a region with a thickness of 0.3 nm or more , preferably 1 nm or more, and more preferably 2 nm or more may be used as 6c.

[0183] Also, in order to improve reliability, it is preferable that the insulator 106a be thick. For example, an insulator 106a having a region with a thickness of 1 0 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and even more preferably 60 nm or more may be used. By increasing the thickness of the insulator 106a, the distance from the interface between the adjacent insulator and the insulator 106a to the semiconductor 106 where the channel is formed can be increased. However, since the productivity of the semiconductor device may decrease , for example, an insulator 106a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used.

[0184] Silicon in the oxide semiconductor may serve as a carrier trap or a carrier generation source. Therefore, it is preferable that the silicon concentration in the semiconductor 106b be as low as possible. For example, the semiconductor 106 Between b and insulator 106a, for example, in secondary ion mass spectrometry (SIMS: Second ary Ion Mass Spectrometry), there is a region with a silicon concentration of 1×10 16 ato ms / cm 3 or more and 1×10 19 atoms / cm 3 or less, preferably 1×10 16 ato ms / cm 3 or more and 5×10 18 atoms / cm 3 or less, more preferably 1×10 16 atoms / cm 3 or more and 2×10 18 atoms / cm 3 or less. Also, between semiconductor 106b and insulator 106c, in SIMS, there is a region with a silicon concentration of 1×1 0 0 16 atoms / cm 3 or more and 1×10 19 atoms / cm 3 or less, preferably 1×1 0 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less, more preferably 1×10 16 atoms / cm 3 or more and 2×10 18 atoms / cm 3 or less. It is preferable to reduce the hydrogen concentration of insulator 106a and insulator 106c in order to reduce the hydrogen concentration of semiconductor 106b. Insulators 106a and 106c have a hydrogen concentration of 1×10

[0185] 6c in SIMS of 1×10 S is 1×10 16 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less. , preferably 1×10 16 atoms / cm 3 or more and 5×10 19 atoms / cm 3 or less , more preferably 1×10 16 atoms / cm 3 or more and 1×10 19 atoms / cm 3 or less, still more preferably 1×10 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3 has a region with a hydrogen concentration in the following range. Also, to reduce the nitrogen concentration of the semiconductor 106b , it is preferable to reduce the nitrogen concentrations of the insulator 106a and the insulator 106c. The insulators 106a and the insulator 106c have, in SIMS, 1×10 15 atoms / cm 3 or more and 5×10 19 atoms / cm 3 or less, preferably 1×10 15 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less, more preferably 1×10 15 atoms / c m 3 or more and 1×10 18 atoms / cm 3 or less, still more preferably 1×10 15 atom s / cm 3 or more and 5×10 17 atoms / cm 3 or less and have a nitrogen concentration in the following range.

[0186] The insulator 106a, the semiconductor 106b, and the insulator 106c shown in this embodiment, particularly the semiconductor 106b, is an oxide semiconductor with a low impurity concentration and a low density of defect levels (less oxygen deficiency). and can be called a high-purity genuine or substantially high-purity genuine oxide semiconductor. High-purity genuine or substantially high-purity genuine oxide semiconductors have few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor seldom has an electrical characteristic (also called normally-on) in which the threshold voltage becomes negative. . Also, since a high-purity genuine or substantially high-purity genuine oxide semiconductor has a low defect level density, the trap level density may also be low. Further, a high-purity genuine or substantially high-purity genuine oxide semiconductor has an extremely small off-current, and even in an element with a channel width W of 1 × 10 6 μm and a channel length L of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be made below the measurement limit of a semiconductor parameter analyzer, that is, 1 × 10 A or less. -13 That is, the following characteristics can be obtained.

[0187] Therefore, a transistor in which a channel region is formed in the above high-purity genuine or substantially high-purity genuine oxide semiconductor can be a highly reliable transistor with small fluctuations in electrical characteristics. Note that the time required for the charge trapped in the trap level of the oxide semiconductor to disappear is long, and it may behave like a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics. Examples of impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals.

[0188] The hydrogen contained in insulator 106a, semiconductor 106b, and insulator 106c reacts with oxygen that binds to metal atoms to form water, and oxygen vacancies are formed in the lattice from which oxygen has desorbed (or the portion from which oxygen has desorbed). When hydrogen enters these oxygen vacancies, carriers in the form of electrons may be generated. Also, a part of the hydrogen may bind to oxygen that binds to metal atoms to generate carriers in the form of electrons. In particular, hydrogen trapped in oxygen vacancies may form shallow donor levels with respect to the band structure of the semiconductor. Therefore, a transistor using a hydrogen-containing oxide semiconductor tends to have normally-on characteristics. For this reason, it is preferable that the hydrogen content in insulator 106a, semiconductor 106b, and insulator 106c is reduced as much as possible. Specifically, in insulator 106a, semiconductor 106b, and insulator 106c, the hydrogen concentration obtained by SIMS analysis is 2×10 atoms / cm or less, preferably 5 ×10 atoms / cm or less, more preferably 1×10 atoms / cm or less, 5×10 atoms / cm or less, preferably 1×10 20 atoms / cm 3 or less, more preferably 5×10 atoms / cm 19 or less, still more preferably 1×10 3 atoms / cm 19 or less, 5×10 3 or less, preferably 1×10 atoms / cm 18 or less, more preferably 5×10 3 atoms / cm 18 or less, still more preferably 1×10 3 atoms / cm 17 or less, and even more preferably 1×10 3 atoms / cm 16 or less, 5×10 3 atoms / cm

[0189] In addition, in insulator 106a, semiconductor 106b, and insulator 106c, the concentration of alkali metal or alkaline earth metal obtained by SIMS analysis is 1×10 atoms / cm 18atoms / cm 3 Hereinafter, preferably 2×10 16 atoms / cm 3 or less. Alkali metals and alkaline earth metals may generate carriers when combined with an oxide semiconductor, and the off-current of the transistor may increase. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the insulator 106a, semiconductor 10 6b, and insulator 106c.

[0190] In addition, if nitrogen is contained in the insulator 106a, semiconductor 106b, and insulator 106c, electrons, which are carriers, are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor film containing nitrogen tends to have normally-on characteristics. Therefore, in the oxide semiconductor film, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration obtained by SIMS analysis is 5×10 18 atoms / cm 3 or less is preferable.

[0191] Here, as shown in FIG. 8(B), low-resistance regions 109a and 109b are formed in a region (indicated by a dotted line in FIG. 8(B)) where a conductor 108a or conductor 108b such as the semiconductor 106b is in contact. The low-resistance regions 109a and 109b are mainly formed by oxygen being extracted from the conductor 108a or conductor 108b in contact with the semiconductor 106b, or by a conductive material contained in the conductor 108a or conductor 108b combining with an element in the semiconductor 106b. Such low-resistance regions 109a and 109b ​​By forming it, the contact between the conductor 108a or the conductor 108b and the semiconductor 106b Since it is possible to reduce the resistance, the on-current of the transistor 12 can be increased .

[0192] Also, as shown in FIG. 8(B), the semiconductor 106b has a region with a thickness thinner than the region overlapping the conductor 108a and the conductor 108b between the conductor 108a and the conductor 108b. This is formed by removing a part of the upper surface of the semiconductor 106b when forming the conductor 108a and the conductor 108b. When a conductor that becomes the conductor 108a and the conductor 108b is formed on the upper surface of the semiconductor 106b, a region with a low resistance similar to the low resistance region 109a and the low resistance region 109b may be formed. Thus, by removing the region located between the conductor 108a and the conductor 108b on the upper surface of the semiconductor 106b, it is possible to prevent a channel from being formed in the region with a low resistance on the upper surface of the semiconductor 106b. Also, in the subsequent drawings, even if a region with a thin film thickness is not shown in an enlarged view or the like, a region with a similar thin film thickness may be formed .

[0193] .

[0193] Note that the three-layer structure of the insulator 106a, the semiconductor 106b, and the insulator 106c described above is an example . For example, a two-layer structure in which either the insulator 106a or the insulator 106c is not provided may be used. Also, a single-layer structure in which neither the insulator 106a nor the insulator 106c is provided may be used. Or, an n-layer structure (n is an integer of 4 or more) having any of the insulator, semiconductor, or conductor exemplified as the insulator 106a, the semiconductor 106b, or the insulator 106c

[0194] is also acceptable

[0194] <Insulator and Conductor of Transistor 12> Details of each component other than the semiconductor of transistor 12 will be described below.

[0195] Insulator 104 preferably contains little water or hydrogen in the film. Also, insulator 104 is preferably an insulator having excess oxygen. For example, as insulator 104, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminate. For example, as insulator 104, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide may be used. Preferably, silicon oxide or silicon oxynitride is used.

[0196] Insulator 104 is preferably an insulator having excess oxygen. By providing such an insulator 104, oxygen can be supplied from insulator 104 to insulator 106a, semiconductor 106b, and insulator 106c. With this oxygen, oxygen deficiencies that are defects in insulator 106a, semiconductor 106b, and insulator 106c can be reduced. As a result, insulator 106a, semiconductor 106b, and insulator 106c can be made into oxide semiconductors having stable characteristics with a low defect level density.

[0197] In this specification and the like, excess oxygen means, for example, contained in excess of the stoichiometric composition. refers to oxygen. Alternatively, the excess oxygen refers to, for example, oxygen released from a film or layer by heating. The excess oxygen can move inside the film or layer, for example. The movement of the excess oxygen may occur when moving between atoms of the film or layer, or when moving like a ball while replacing the oxygen constituting the film or layer. etc.

[0198] The insulator 104 having excess oxygen has an oxygen molecule desorption amount of 1.0×10 or more and 1.0×10 molecules / cm 14 molecules / cm 2 or less in the surface temperature range of 10 16 molec ules / cm 2 or less, preferably 1.0×10 15 molecules / c m 2 or more and 5.0×10 15 molecules / cm 2 or less when analyzed by temperature programmed desorption gas spectrometry (TDS analysis).

[0199] The method for measuring the emission amount of molecules using TDS analysis will be described below taking the emission amount of oxygen as an example. as follows.

[0200] The total emission amount of gas when the measurement sample is analyzed by TDS analysis is proportional to the integral value of the ionic strength of the emission gas. And the total emission amount of gas can be calculated by comparison with a standard sample. For example, from the TDS analysis results of a silicon substrate containing hydrogen with a predetermined density as a standard sample and the TDS analysis results of the measurement sample, the oxygen molecule emission amount (N

[0201] ) of the measurement sample can be obtained by the following O2 formula. Here, the gas detected with a mass charge ratio of 32 obtained by TDS analysis ​ Assume that all of the S are derived from oxygen molecules. For example, CH 3 The mass-to-charge ratio of OH is 32, but it is not considered here as it is unlikely to exist. Also, for oxygen molecules containing oxygen atoms with mass number 17 and oxygen atoms with mass number 18, which are isotopes of oxygen atoms, they are not considered because their abundance ratios in nature are extremely low.

[0202] N O2 =N H2 / S H2 ×S O2 ×α

[0203] N H2 is the value obtained by converting the hydrogen molecules desorbed from the standard sample into density. S H2 is the integrated value of the ionic strength when the standard sample is analyzed by TDS. Here, the reference value of the standard sample is set as N H2 / S H2 Let it be. S O2 is the integrated value of the ionic strength when the measurement sample is analyzed by TDS α is a coefficient that affects the ionic strength in TDS analysis. For the details of the formula shown above, refer to Japanese Patent Laid-Open No. 6-275697. The amount of oxygen released above is measured using the temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electron Science Co., Ltd., with a silicon substrate containing a certain amount of hydrogen atoms as the standard sample.

[0204] Also, in TDS analysis, a part of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above-mentioned α includes the ionization rate of oxygen molecules, by evaluating the amount of oxygen molecules released, the amount of oxygen atoms released can also be estimated.

[0205] Note that NO2 is the amount of oxygen molecules released. When converted to oxygen atoms, the released amount is twice that of oxygen molecules. The released amount is twice that of oxygen molecules.

[0206] Alternatively, an insulator that releases oxygen by heat treatment may contain peroxide radicals. . Specifically, it means that the spin density due to peroxide radicals is 5×10 17 spins / cm 3 or more. Note that an insulator containing peroxide radicals may have an asymmetric signal with a g value in the vicinity of 2.01 by electron spin resonance (ESR). SR: Electron Spin Resonance). It may have an asymmetric signal with a g value in the vicinity of 2.01.

[0207] The amount of water or hydrogen contained in the insulator 104 is preferably small. For example, the insulator 104 has a desorption amount of water molecules in the range of surface temperature of 100 °C or higher and 700 °C or lower or 100 °C or higher and 500 °C or lower by TDS analysis. is 1.0×10 or more and 1.4×10 13 molecules / cm 2 or more and 4.0×10 16 molecules / cm 2 or more and 2.0×10 13 mol ecules / cm 2 or more and 4.0×10 15 molecules / cm 2 or more and 1 .0×10 13 molecules / cm 2 or more and 2.0×10 15 molecules / cm 2 or less. Also, by TDS analysis, in the range of surface temperature of 100 °C or higher and 700 °C or lower or 100 °C or higher and 500 °C or lower, the desorption amount of hydrogen molecules is 1.0×10 or 1.0×10 1 3 molecules / cm2 Above 1.2×10 15 molecules / cm 2 Below, Furthermore, 1.0×10 13 molecules / cm 2 Above 9.0×10 14 molecu les / cm 2 It is preferably below this value.

[0208] Also, as described above, it is preferable that the upper or lower surface of the semiconductor 106b has high flatness. For this reason, a planarization process may be performed on the upper surface of the insulator 104 by a method such as chemical mechanical polishing (CMP: Chemical Mechani cal Polishing) to improve the flatness. This is also acceptable.

[0209] The conductor 108a and the conductor 108b each function as either the source electrode or the drain electrode of the transistor 12.

[0210] As the conductor 108a and the conductor 108b, for example, a conductor containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium ium, tin, tantalum, and tungsten may be used in a single layer or in a stacked layer. For example, an alloy or a compound may be used, and conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin, and oxygen conductors containing titanium and nitrogen, etc. may be used.

[0211] The insulator 112 functions as the gate insulating film of the transistor 12. The insulator 112 ​An insulator having excess oxygen may be used in the same manner as the insulator 104. By providing such an insulator 112, oxygen can be supplied from the insulator 112 to the insulator 106a, the semiconductor 106b, and the insulator 106c.

[0212] As the insulator 112, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a laminated form. For example, as the insulator 112, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used.

[0213] The conductor 114 functions as the gate electrode of the transistor 12. As the conductor 114, a conductor that can be used as the conductor 108a and the conductor 108b may be used.

[0214] Here, as shown in FIG. 8(C), the semiconductor 106b can be electrically surrounded by an electric field such as that of the conductor 114 (a transistor structure in which the semiconductor is electrically surrounded by an electric field generated from the conductor is called a surrounded channel (s-channel) structure). Therefore, channels are formed on the entire surface (upper surface, lower surface, and side surfaces) of the semiconductor 106b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. ​

[0215] In addition, when the transistor has an s-channel structure, the side surface of the semiconductor 106b is Therefore, the thicker the semiconductor 106b, the larger the channel region. That is, the thicker the semiconductor 106b, the higher the on-state current of the transistor. In addition, the thicker the semiconductor 106b, the greater the proportion of the region with high carrier controllability. Therefore, the subthreshold swing value can be reduced. For example, it is preferably 10 nm or more. Preferably, the thickness is 20 nm or more, more preferably, 30 nm or more, and even more preferably, 50 nm or more. However, the productivity of the semiconductor device may be reduced. Therefore, for example, it is 300 nm or less, preferably 200 nm or less, and more preferably In this case, the semiconductor 106b may have a region with a thickness of 150 nm or less.

[0216] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. For example, The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. More preferably, the transistor has a channel width of 20 nm or less. or less than 40 nm, more preferably less than 30 nm, and even more preferably less than 20 nm. It has a range.

[0217] The insulator 116 serves not only as a dielectric for the capacitive element 14 but also as a protective insulator for the transistor 12. It is preferable that the insulator 116 also functions as an insulating film. It can be made m or more, or 20 nm or more. Further, at least a part of the insulator 116 is preferably formed in contact with the upper surface of the insulator 104.

[0218] As the insulator 116, for example, an insulator containing carbon, nitrogen, oxygen, fluorine, magnesium, aluminum um, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zir conium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminated form. The insulator 116 preferably has an effect of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. As such an insulator, for example , a nitride insulating film can be used. As the nitride insulating film, there are silicon nitride, oxynitride silicon, aluminum nitride, aluminum oxynitride, etc. Instead of the nitride insulating film, an oxide insulating film having an effect of blocking oxygen, hydrogen, water, etc. may be provided. As the oxide insulating film, there are aluminum oxide, aluminum oxynitride, gallium oxide, oxynitride gallium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. Here, the film formation of the insulator 116 is preferably performed by a sputtering method, and more preferably by a sputtering method in an atmosphere containing oxygen. By performing the film formation of the insulator 116 by the sputtering method, oxygen is added in the vicinity of the surface of the insulator 104 (the interface between the insulator 104 and the insulator 116 after the formation of the insulator 116) at the same time as the film formation. The insulator 116 is an insulator that is less permeable to oxygen than the insulator 104 and blocks oxygen.

[0219]

[0220] It preferably has a function of ~~クする~~. By providing such an insulator 116, when oxygen is supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c, it is possible to prevent the oxygen from being externally released above the insulator 116. When oxygen is supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c, it is possible to prevent the oxygen from being externally released above the insulator 116.

[0221] Note that aluminum oxide is preferable for application to the insulator 116 because it has a high blocking effect of not allowing the film to permeate impurities such as hydrogen and moisture, as well as both oxygen. Note that aluminum oxide is preferable for application to the insulator 116 because it has a high blocking effect of not allowing the film to permeate impurities such as hydrogen and moisture, as well as both oxygen.

[0222] The insulator 118 functions as an interlayer insulating film. As the insulator 118, an insulator that can be used as the insulator 104 may be used. As the insulator 118, an insulator that can be used as the insulator 104 may be used.

[0223] The conductor 120 functions as a wiring electrically connected to the source electrode or the drain electrode of the transistor 12. As the conductor 120, a conductor that can be used as the conductor 108a and the conductor 108b may be used. Further, as the conductor 120, a semiconductor such as polycrystalline silicon doped with impurities such as phosphorus may be used. The conductor 120 functions as a wiring electrically connected to the source electrode or the drain electrode of the transistor 12. As the conductor 120, a conductor that can be used as the conductor 108a and the conductor 108b may be used. Further, as the conductor 120, a semiconductor such as polycrystalline silicon doped with impurities such as phosphorus may be used. Further, as the conductor 120, a semiconductor such as polycrystalline silicon doped with impurities such as phosphorus may be used.

[0224] Also, the conductor 122 functions as the other electrode of the capacitor element. As the conductor 122, a conductor that can be used as the conductor 108a and the conductor 108b may be used. As the conductor 122, a conductor that can be used as the conductor 108a and the conductor 108b may be used.

[0225] By adopting the above configuration, it is possible to provide the transistor 12 having stable electrical characteristics. Or, it is possible to provide the transistor 12 having a small leakage current in the non-conducting state. Or, it is possible to provide the transistor 12 having high frequency characteristics. Or, it is possible to provide the transistor 12 having normally-off electrical characteristics. By adopting the above configuration, it is possible to provide the transistor 12 having stable electrical characteristics. Or, it is possible to provide the transistor 12 having a small leakage current in the non-conducting state. Or, it is possible to provide the transistor 12 having high frequency characteristics. Or, it is possible to provide the transistor 12 having normally-off electrical characteristics. It is possible. Or, a transistor 12 with a small subthreshold swing value can be provided. Or, a highly reliable transistor can be provided. By using such a transistor 12 in the memory cell 10, a semiconductor device capable of retaining stored contents for a longer period can be provided. It is possible. Or, a highly reliable transistor can be provided. By using such a transistor 12 in the memory cell 10, a semiconductor device capable of retaining stored contents for a longer period can be provided. It is possible.

[0226] <Configuration of Memory Cell Array> Next, an example of the configuration of the three-dimensional memory cell array shown in the previous embodiment will be described with reference to FIGS. 9 to 11.

[0227] As part of the three-dimensional memory cell array, the structures of the memory cells 10(1,1,1) to (1,4,4) of the two-dimensional memory cell array 30[1] are shown in FIGS. 9 to 11 as an example. FIG 9 is a three-dimensional schematic diagram of the memory cells 10(1,1,1) to (1,4,4). Note that in FIG. 9, similar to FIG. 2, a rectangular coordinate system composed of the x-axis, y-axis, and z-axis is set for convenience of explanation. Here, the upper surface of the substrate on which the three-dimensional memory cell array is provided is substantially parallel to the xz plane, and the y-axis is substantially perpendicular to the upper surface of the substrate. Note that in FIG. 9, some configurations of the memory cell 10 (for example, the insulator 106c, the insulator 112, etc.) are omitted for illustration. Here, the upper surface of the substrate on which the three-dimensional memory cell array is provided is substantially parallel to the xz plane, and the y-axis is substantially perpendicular to the upper surface of the substrate. Note that in FIG. 9, some configurations of the memory cell 10 (for example, the insulator 106c, the insulator 112, etc.) are omitted for illustration. 10 (for example, the insulator 106c, the insulator 112, etc.) are omitted for illustration. are shown.

[0228] FIG. 10 is a top view of the memory cells 10(1,4,1) to (1,4,4). FIG. 11( A) is a cross-sectional view corresponding to the dashed line B1 - B2 in FIG. 10, corresponding to the memory cells 10(1,1, 1) to (1,4,1). FIG. 11(B) is a cross-sectional view corresponding to the dashed line B3 - B4 in FIG. 10, corresponding to the memory cells 10(1,4,1) to (1,4,4). Note that in the region indicated by the dashed line B1 - B2, the structure in the channel length direction of the transistor 12 is shown. In the region indicated by the dashed line B3 - B4, the structure in the channel width direction of the transistors 12 of the memory cells 10(1 ,4,1) to (1,4,4) is shown. The structure of each memory cell 10 is the same, and the description of the structure of the memory cell 10 described above can be referred to. However, for the memory cells 10 formed on the same plane (for example, the memory cells 10(1,1,1) to (m ) shown in FIG. 2), the insulators 104

[0229] , the insulator 116, the insulator 118, etc. may be integrated. As shown in FIG. 11(A), the insulator 132, the semiconductor 134, and the insulator 136 are formed to extend in a direction substantially parallel to the y-axis and are shared in the memory cells 10(1,1,1) to (1,4, 1). That is, in the memory cells 10 arranged in the y-axis direction, the insulator 132, the semiconductor 134, and the insulator 136 are shared. Therefore, the region 134b that functions as the source or drain of the transistor 11 in the semiconductor 134 is in contact with the region 134b of the adjacent memory cell 10 in the y-axis direction. That is, in the memory cells 10 adjacent to each other in the y-axis direction, the respective transistors 11 are electrically connected in series. 1 ,1,m 3 ) etc.), the insulators 104 , the insulator 116, the insulator 118, etc. may be integrated.

[0230] As described above, the insulator 132, the semiconductor 134, and the insulator 136 together form a plurality of transistors 11 included in one memory string 20. For example, the transistors , the insulator 116, the insulator 118, etc. may be integrated. As shown in FIG. 11(A), the insulator 132, the semiconductor 134, and the insulator 136 are formed to extend in a direction substantially parallel to the y-axis and are shared in the memory cells 10(1,1,1) to (1,4, 1). That is, in the memory cells 10 arranged in the y-axis direction, the insulator 132, the semiconductor 134, and the insulator 136 are shared. Therefore, the region 134b that functions as the source or drain of the transistor 11 in the semiconductor 134 is in contact with the region 134b of the adjacent memory cell 10 in the y-axis direction. That is, in the memory cells 10 adjacent to each other in the y-axis direction, the respective transistors 11 are electrically connected in series. In this way, the insulator 132, the semiconductor 134, and the insulator 136 together form a plurality of transistors 11 included in one memory string 20. For example, the transistors As described above, the insulator 132, the semiconductor 134, and the insulator 136 together form a plurality of transistors 11 included in one memory string 20. For example, the transistors As shown in FIG. 11(A), the insulator 132, the semiconductor 134, and the insulator 136 are formed to extend in a direction substantially parallel to the y-axis and are shared in the memory cells 10(1,1,1) to (1,4, 1). That is, in the memory cells 10 arranged in the y-axis direction, the insulator 132, the semiconductor 134, and the insulator 136 are shared. Therefore, the region 134b that functions as the source or drain of the transistor 11 in the semiconductor 134 is in contact with the region 134b of the adjacent memory cell 10 in the y-axis direction. That is, in the memory cells 10 adjacent to each other in the y-axis direction, the respective transistors 11 are electrically connected in series.

[0231] As described above, the insulator 132, the semiconductor 134, and the insulator 136 together form a plurality of transistors 11 included in one memory string 20. For example, the transistors As described above, the insulator 132, the semiconductor 134, and the insulator 136 together form a plurality of transistors 11 included in one memory string 20. For example, the transistors When the transistor 11 was formed of a standard planar transistor, a structure in which plugs and wirings had to be formed for each layer. However, by using the SGT as the transistor 11, a structure in which the sources and drains of a plurality of transistors 11 are connected in series can be formed self-alignedly. 11 and the drains are connected in series can be formed self-alignedly. 11, a structure in which the sources and drains of a plurality of transistors 11 are connected in series can be formed self-alignedly.

[0232] In the semiconductor 134 of the topmost memory cell 10, a conductor electrically connected to the low power supply potential line that functions as the wiring SL may be formed so as to be in contact with the upper surface of the semiconductor 134. Also, regarding the connection between the transistor 6 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later. 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later. 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later.

[0233] Also, as shown in FIG. 11(A), the conductor 120 is formed to extend in a direction substantially parallel to the y-axis and is shared among the memory cells 10(1,1,1) to (1,4,1). That is, in the memory cells 10 arranged in the y-axis direction, the conductor 120 is shared. The conductor 120 is electrically connected to the other of the source or drain of the transistor 12 in the memory cell 10 and has a function as the wiring WBL shown in FIG. 2 and the like. 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later. 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later. 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later. 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later.

[0234] In the conductor 120 of the topmost memory cell 10, it is preferable to cover it with an insulator or the like so that the upper surface of the conductor 120 does not contact a conductor or the like that functions as the wiring SL. Also, regarding the connection between the transistor 62 and the conductor 120 of the lowermost memory cell 10 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later. 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later. 1 and the semiconductor 134 of the lowermost memory cell 10 will be described later.

[0235] Also, as shown in FIGS. 10 and 11(B), the conductor 114 is in a direction substantially parallel to the x-axis It is formed by elongation and is shared among the memory cells 10(1,4,1) to (1,4,4). That is, in the memory cells 10 arranged in the x-axis direction, the conductor 114 is shared. The conductor 114 also functions as the gate of the transistor 11 in the memory cell 10 and has the function as the wiring WWL shown in FIG. 2 and the like. In the three-dimensional memory cell array 40 shown in FIGS. 9 to 11, the insulator 106c and the insulator 112 are also patterned in the same manner as the conductor 114. Therefore, in the memory cells 10 arranged in the x-axis direction, the insulator 106c and the insulator 112 are also shared. However, it is not limited to this. For example, the conductor 114 and the insulator 112 are shared in the memory cells 10 arranged in the x-axis direction, but the insulator 106c is not shared in the memory cells 10 arranged in the x-axis direction and may be configured to be patterned in an island shape in each memory cell 10.

[0236] Also, as shown in FIG. 10, the conductor 122 is formed by elongating in a direction substantially parallel to the x-axis and is shared among the memory cells 10(1,4,1) to (1,4,4). That is, in the memory cells 10 arranged in the x-axis direction, the conductor 122 is shared. The conductor 122 also functions as the other electrode of the capacitor element 14 in the memory cell 10 and has the function as the wiring RWL shown in FIG. 2 and the like.

[0237] By adopting the above configuration, a three-dimensional memory cell array in which the memory cells 10 are stacked in a direction perpendicular to the upper surface of the substrate can be provided. In this way, by stacking the memory cells, the storage capacity per unit area can be increased according to the number of stacked layers. ​​​​​​​​​​​​​This is the case. In the memory cell, two transistors and one capacitor element are included, Since the number of elements is relatively large, the storage capacity per unit area tends to be smaller than that of conventional memories. On the other hand, by using the semiconductor device shown in this embodiment, in addition to the above such good characteristics, a semiconductor device with a storage capacity per unit area equal to or greater than that of conventional memories can be provided. Also, in the semiconductor device shown in this embodiment, by stacking memory cells in this way to increase the storage capacity per unit area, it is also possible to provide a storage device having a storage capacity of 1 TByte or more, 5 TByte or more, 10 TByte or more.

[0238] <Configuration of the selection transistor array> Next, an example of the configuration of the transistors included in the selection transistor array shown in the previous embodiment will be described with reference to FIGS. 12 and 13.

[0239] FIGS. 12(A) and 12(B) are cross-sectional views of the transistor 61 provided in the selection transistor array 50 shown in FIG. 5. The cross-section C1-C2 shown in FIG. 12(A) represents a cross-sectional view of the transistor 61 in the channel length direction, and the cross-section C3-C4 shown in FIG. 12(B) represents a cross-section of the transistor 61 in the channel width direction.

[0240] The transistor 61 shown in FIGS. 12(A) and 12(B) is a transistor using a semiconductor substrate 150. The transistor 61 has a region 172a in the semiconductor substrate 150, a region 172b in the semiconductor substrate 15 0, an insulator 162a, and a conductor 154a. Although not shown, a sidewall insulator is provided in contact with the side surface of the conductor 154a. ​​​​​​​​This is also acceptable. When a sidewall insulator is provided in contact with the side surface of the conductor 154a, in regions 172a and 172b, a region with a lower impurity concentration than the region not overlapping with the sidewall insulator may be formed in the region overlapping with the sidewall insulator. .

[0241] In the transistor 61, the regions 172a and 172b function as a source region and a drain region. Also, the insulator 162a functions as a gate insulator. Moreover, the conductor 154a functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled by the potential applied to the conductor 154a. That is, the conduction / non-conduction between the regions 172a and 172b can be controlled by the potential applied to the conductor 154a.

[0242] As the semiconductor substrate 150, for example, a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide lead, gallium oxide, etc. may be used. Preferably, a single crystal silicon substrate is used as the semiconductor substrate 150.

[0243] The semiconductor substrate 150 uses a semiconductor substrate having an impurity that imparts a p-type conductivity type. However, as the semiconductor substrate 150, a semiconductor substrate having an impurity that imparts an n-type conductivity type may also be used. In that case, a well having an impurity that imparts a p-type conductivity type may be arranged in the region that becomes the transistor 61. Or, it is also acceptable if the semiconductor substrate 150 is of i-type.

[0244] ​Note that the substrate used in the semiconductor device shown in this embodiment is not limited to a semiconductor substrate. For example, when forming an active layer such as transistor 61 by film formation or the like, an insulator substrate or a conductor substrate can also be used. Examples of the insulator substrate include a glass substrate , a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate ), a resin substrate, and the like. Further, a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate or the like can also be used. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. Or, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, , there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Also, those in which elements are provided on these substrates may be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0245] Further, as the substrate, a flexible substrate that can withstand the heat treatment during transistor fabrication may also be used. Note that as a method of providing a transistor on a flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to the flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that , as the substrate, a sheet, film, or foil in which fibers are woven may also be used. Also, the substrate may have stretchability. Further, when the bending and pulling of the substrate are stopped, the original shape It may have the property of returning to its original state. Or, it may have the property of not returning to its original shape. The thickness of the substrate is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. Making the substrate thinner can reduce the weight of the semiconductor device. Also, by making the substrate thinner, when using glass or the like, even if it has elasticity, or when it has the property of returning to its original shape when bending or pulling is stopped. Therefore, it is possible to mitigate the impact applied to the semiconductor device on the substrate due to dropping or the like. That is, a robust semiconductor device can be provided.

[0246] Regions 172a and 172b are regions having impurities that impart an n-type conductivity type. In this way, the transistor 61 constitutes an n-channel type transistor.

[0247] Note that the transistor 61 is separated from adjacent transistors by regions such as region 160. Region 160 is an insulating region.

[0248] The semiconductor device shown in FIGS. 12(A) and (B) includes an insulator 132, a semiconductor 134, an insulator 1 36, an insulator 164, an insulator 166, an insulator 168, an insulator 170, a conductor 1 80a, a conductor 180b, a conductor 178a, a conductor 178b, a conductor 176a, , and a conductor 174a. Here, the insulator 132, the semiconductor 134, and the insulator 136 were formed in the three-dimensional memory cell array 40 described above.

[0249] The insulator 164 is formed on the transistor 61. Also, the insulator 166 is an insulator 1 It is formed on 64. Also, the insulator 168 is formed on the insulator 166. Also, the insulator 170 is formed on the insulator 168.

[0250] The insulator 164, the insulator 166, the insulator 168, and the insulator 170 have a columnar opening reaching the region 172a, and the insulator 132, the semiconductor 134, and the insulator 1 36 are provided therein. The insulator 132 is formed in a cylindrical shape in contact with the inner wall of the opening, the semiconductor 134 is formed in a cylindrical shape inside the insulator 132, and the insulator 136 is formed in a columnar shape inside the semiconductor 134. The insulator 132, the semiconductor 134, and the insulator 136 are formed to extend substantially perpendicular to the upper surface of the semiconductor substrate 150. The bottom surface of the insulator 132 has at least a part of an opening formed therein, and the semiconductor 134 is in contact with the region 172a through the opening. Here, the semiconductor 134 shown in FIGS. 12(A) and (B) corresponds to any one of the wirings RBL[1,1] to [m ,m

[0251] shown in FIG. 3, etc., and the region 172a functions as a source region or a drain region of the transistor 61. With the above configuration, the wiring RBL at the bottom of the memory cell string can be electrically connected to the source region or the drain region of the transistor 61 of the selection transistor cell 60. Furthermore, the insulator 164 has an opening reaching the region 172b and an opening reaching the conductor 154a. 1 ,m 3 and the conductor 180a and the conductor 180b are embedded in the respective openings. Further, the insulator 166 has an opening reaching the conductor 180a and the conductor 180b reaches the opening. By adopting the above configuration, the wiring RBL at the bottom of the memory cell string can be electrically connected to the source region or the drain region of the transistor 61 of the selection transistor cell 60.

[0252] Furthermore, the insulator 164 has an opening reaching the region 172b and an opening reaching the conductor 154a. In the openings, the conductor 180a and the conductor 180b are respectively embedded. Further, the insulator 166 has an opening reaching the conductor 180a and the conductor 180b reaches the opening. It has an opening reaching [a certain state] and [another part]. In the said opening, there are a conductor 178a and a conductor 178b respectively embedded. Also, the insulator 168 has an opening reaching the conductor 178a . In the said opening, a conductor 176a is embedded. Also, the insulator 170 has an opening reaching the conductor 17 6a. In the said opening, a conductor 174a is embedded.

[0253] Here, the conductor 174a is in electrical contact with a region 172b that functions as a source region or a drain region of the transistor 61, and functions as any one of the wirings RBL[1] to [m shown in FIG. 5 etc. Also, the conductor 178b is electrically connected to a conductor 154a that functions as a gate of the transistor 61, and functions as the wiring SG1 shown in FIG. 5 etc. 1 . In reading data through the wiring SG1 and the transistor 61 formed in this way, any one of the two-dimensional memory cell arrays 30[1] to [m can be selected. 3

[0254] As the insulator 164, the insulator 166, the insulator 168, and the insulator 170, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium , hafnium or tantalum may be used in a single layer or in a laminated form.

[0255] One or more of the insulator 164, the insulator 166, the insulator 168, and the insulator 170 preferably have an insulator having a function of blocking impurities such as hydrogen and oxygen. Below the transistor 12 included in the three-dimensional memory cell array 40, impurities such as hydrogen and acid ​ By arranging an insulator having a function of blocking elements, the electrical characteristics of the transistor 12 can be stabilized.

[0256] As the insulator having a function of blocking impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminated form.

[0257] As the conductors 180a, 180b, 178a, 178b, 176a and 174a, for example, a conductor containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and tungsten may be used in a single layer or in a laminated form. For example, it may be an alloy or a compound, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen, etc. may be used.

[0258] Also, FIGS. 12(C) and (D) are cross-sectional views of the transistor 62 provided in the selection transistor array 50 shown in FIG. 5. The cross-section C5-C6 shown in FIG. 12(C) represents a cross-sectional view of the transistor 62 in the channel length direction, and the cross-section C7-C8 shown in FIG. 12(D) represents a cross-section of the transistor 6 2 in the channel width direction. is shown.

[0259] The configuration of the semiconductor device shown in FIGS. 12(C) and (D) is the same as that of the semiconductor device shown in FIGS. 12(A) and (B), except that a conductor 120 is formed instead of an insulator 132, a semiconductor 134, and an insulator 136 being formed. The transistor 62 includes a region 172c in the semiconductor substrate 150, a region 172d in the semiconductor substrate 150, an insulator 162b, and a conductor 154b. The configurations of the regions 172c and 172d can be considered with reference to the configurations of the regions 172a and 172b, the insulator 162b can be considered with reference to the configuration of the insulator 162a, and the conductor 154b can be considered with reference to the configuration of the conductor 154a. Also, the configurations of the conductors 180c, 180d, 178c, 178d, 176b, and 174b can be considered with reference to the configurations of the conductors 180a, 180b, 178a, 178b, 176a, and 174a. (A) and (B). The transistor 62 includes a region 172c in the semiconductor substrate 150, a region 172d in the semiconductor substrate 150, an insulator 162b, and a conductor 154b. However, the configurations of the regions 172c and 172d can be considered with reference to the configurations of the regions 172a and 172b, the insulator 162b can be considered with reference to the configuration of the insulator 162a, and the conductor 154b can be considered with reference to the configuration of the conductor 154a. The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m

[0260] The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m

[0261] The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m 1 ,m 3 , and the region 172c functions as a source region or a drain region of the transistor 62. With the above configuration, the wiring WBL electrically connected to the transistor 12 of the memory cell 10 is selected by the transistor 62 of the selection transistor cell 60. , and the region 172c functions as a source region or a drain region of the transistor 62. With the above configuration, the wiring WBL electrically connected to the transistor 12 of the memory cell 10 is selected by the transistor 62 of the selection transistor cell 60. , and the region 172c functions as a source region or a drain region of the transistor 62. With the above configuration, the wiring WBL electrically connected to the transistor 12 of the memory cell 10 is selected by the transistor 62 of the selection transistor cell 60. The insulators 164, 166, 168, and 170 have columnar openings reaching the region 172c, and the conductor 120 is provided in the openings. The conductor 120 is formed in a columnar shape in contact with the inner wall of the openings. The conductor 120 extends substantially perpendicular to the upper surface of the semiconductor substrate 150. Here, the conductor 120 shown in FIGS. 12(C) and (D) corresponds to any one of the wirings WBL[1,1] to [m - It can be electrically connected to the source region or the drain region.

[0262] Also, the conductor 174b is in electrical contact with the region 172d that functions as the source region or the drain region of the transistor 62, and functions as any one of the wirings WBL[1] to [m shown in FIG. 5 etc. 1 and so on. Further, the conductor 178d is electrically connected to the conductor 154b that functions as the gate of the transistor 62, and functions as the wiring SG2 shown in FIG. 5 etc. In writing data through the wiring SG2 and the transistor 62 formed in this way, any one of the two-dimensional memory cell arrays 30[1] to [m can be selected. shown in FIG. 5 etc. 3 and so on.

[0263] Note that the semiconductor devices shown in FIGS. 13(A)(B) and FIGS. 13(C)(D) are only different in the structure of the transistor 61 or the transistor 62 of the semiconductor devices shown in FIGS. 12(A) (B) and FIGS. 12(C)(D). Therefore, for the semiconductor devices shown in FIGS. 13(A)(B) and FIGS. 13(C)(D), the description of the semiconductor devices shown in FIGS. 12(A)(B) and FIGS. 12(C)(D) can be referred to. Specifically, the semiconductor devices shown in FIGS. 13(A)(B) and FIGS. 13(C (D) show the case where the transistor 61 or the transistor 62 is of the Fin type. By making the transistor 61 or the transistor 62 of the Fin type, the on characteristics of the transistor 61 or the transistor 62 can be improved by increasing the effective channel width. Also, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 61 or the transistor 62 can be improved. the off characteristics of the transistor 61 or the transistor 62 can be improved. the off characteristics of the transistor 61 or the transistor 62 can be improved. the on characteristics of the transistor 61 or the transistor 62 can be improved. 2 can be improved. Also, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 61 or the transistor 62 can be improved. ​​​

[0264] <Modification example of memory cell> Hereinafter, a modification example of the transistor 12 will be described with reference to FIG. 14. Note that FIG. 14 is Similar to FIGS. 8(B) and 8(C), it is a cross-sectional view of the transistor 12 in the channel length direction and a cross-sectional view of the transistor 12 in the channel width direction.

[0265] The memory cell 10a shown in FIGS. 14(A) and 14(B) mainly differs from the transistor 12 in the configuration of the transistor 12a. The transistor 12a is different from the transistor 12 in that an insulator 119, an insulator 101, an insulator 107, a conductor 102, an insulator 103, and an insulator 105 are formed under the insulator 104. The insulator 101 is formed on the insulator 119, the insulator 107 is formed on the insulator 101, the conductor 102 is formed so as to be embedded in the opening of the insulator 107, the insulator 105 is formed on the insulator 107 and the conductor 102, the insulator 103 is formed on the insulator 105, and the insulator 104 is formed on the insulator 103. For the insulator 119, an insulator that can be used as the insulator 104 may be used.

[0266] As the insulator 101, an insulator having a function of blocking hydrogen or water is used. Hydrogen and water in the insulator provided in the vicinity of the insulator 106a, the semiconductor 106b, and the insulator 106c are one of the factors for generating carriers in the insulator 106a, the semiconductor 106b, and the insulator 106c that also function as an oxide semiconductor. This may reduce the reliability of the transistor 12. In particular, for the memory cell 10(1,1,1) provided at the lowermost stage of the three-dimensional memory cell array 40

[0267] ​even up to (m 1 , 1, m 3 ) is provided with the insulator 101 because it is closest to the selection transistor array 50, which is more effective. When providing a silicon-based semiconductor element in the selection transistor array 50, hydrogen is used to terminate the dangling bonds of the semiconductor element, and there is a risk that the hydrogen will diffuse to the transistor 12. On the other hand, by providing the insulator 101 having a function of blocking hydrogen or water, diffusion of hydrogen or water from the underlying layer of the transistor 12 can be suppressed, and the reliability of the transistor 12 can be improved. Also, it is preferable that the insulator 101 also has a function of blocking oxygen. By blocking oxygen diffusing from the insulator 104, oxygen can be effectively supplied from the insulator 104 to the insulator 1 06a, the semiconductor 106b, and the insulator 106c. As the insulator 101, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide,

[0268] hafnium oxynitride, etc. can be used. By using these as the insulator 101, it can function as an insulating film showing an effect of blocking the diffusion of oxygen, hydrogen, or water. Also, as the insulator 101, for example, silicon nitride, silicon oxynitride, etc. can be used. By using these as the insulator 101, it can function as an insulating film showing an effect of blocking the diffusion of hydrogen and water. The conductor 102 is at least partially in a region sandwiched between the conductor 108a and the conductor 108b.

[0269] For the insulator 101, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used. By using these as the insulator 101, it can function as an insulating film showing an effect of blocking the diffusion of oxygen, hydrogen, or water. Also, as the insulator 101, for example, silicon nitride, silicon oxynitride, etc. can be used. By using these as the insulator 101, it can function as an insulating film showing an effect of blocking the diffusion of hydrogen and water. The conductor 102 is at least partially in a region sandwiched between the conductor 108a and the conductor 108b. For the insulator 101, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide,

[0270] The conductor 102 is at least partially in a region sandwiched between the conductor 108a and the conductor 108b. Preferably, it overlaps with the semiconductor 106b. The conductor 102 functions as the back gate of the transistor 12. By providing such a conductor 102, the threshold voltage of the transistor 12 can be controlled. By controlling the threshold voltage, when the voltage applied to the gate (conductor 114) of the transistor 12 is low, for example, when the applied voltage is 0 V or less, it is possible to prevent the transistor 12 from being in the conductive state. That is, it becomes easier to shift the electrical characteristics of the transistor 12 in the more normally-off direction. Note that as the conductor 102, a conductor that can be used as the conductor 114 may be used. Moreover, it is preferable that the length of the conductor 102 in the channel length direction is larger than the length of the semiconductor 106b in the channel length direction, and the conductor 102 covers the lower surface of the semiconductor 106b. Thus, by providing the conductor 102, the electric field generated in the memory cell provided below is shielded by the conductor 102, and it is possible to suppress the electric field from affecting the semiconductor 106b. As the insulator 107, an insulator that can be used as the insulator 104 may be used. Also, it is preferable to improve the flatness by performing a planarization process on the upper surfaces of the insulator 107 and the conductor 102 by a CMP method or the like. Thereby, even if the conductor 102 that functions as the back gate is provided, the flatness of the surface on which the semiconductor 106b is formed is not impaired, so that the mobility of carriers can be improved and the on-current of the transistor 12 can be increased. Also, since the step on the surface of the insulator 104 due to the shape of the conductor 102 disappears,

[0271]

[0272] ​​​​​​​​​​​​​​​​Between the drain of the drain electrode 108a or 108b and the conductor 102, an insulator 108 is provided. This reduces the leakage current that occurs through the step portion of the transistor. The off-current of the transistor 12 can be reduced.

[0273] As the insulator 105, an insulator that can be used as the insulator 104 may be used. .

[0274] The insulator 103 preferably has a function of blocking oxygen. By providing 103, the conductor 102 is prevented from extracting oxygen from the insulator 104. As a result, the insulator 104 is divided into the insulator 106a, the semiconductor 106b, and the insulator 106b. In addition, the insulator 103 can effectively supply oxygen to the electrode 06c. This reduces the amount of oxygen drawn out of the insulator 104, and the amount of oxygen drawn out of the insulator 104 is reduced. The insulator 106a, the semiconductor 106b, and the insulator 106c can be supplied with oxygen more effectively. can.

[0275] The insulator 103 may be boron, aluminum, silicon, scandium, titanium, or gallium. Sodium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, halide An oxide or nitride containing hafnium or thallium is used. Preferably, hafnium oxide is used. Aluminum or aluminum oxide is used.

[0276] In the insulators 105, 103, and 104, the insulator 103 traps electrons. It is preferable that the insulator 105 and the insulator 104 have a function of suppressing the emission of electrons. When the insulator 103 has the function of trapping electrons, the electrons trapped in the insulator 103 behave like negative fixed charges. Thus, the insulator 103 functions as a floating gate.

[0277] However, the memory cell 10a is not limited to the configuration shown in FIGS. 14(A) and (B). . For example, the insulators 107, 105, and 104 may not be provided, and the insulator 104 may be configured to protrude according to the shape of the conductor 102, or the insulator 101 may not be provided.

[0278] The memory cell 10b shown in FIGS. 14(C) and (D) mainly differs from the transistor 12 in the configuration of the transistor 12b. The transistor 12b is formed so as to cover the semiconductor 106b, the conductors 108a and 108b, etc. with the insulators 106c and 112, and the insulator 11 7 is formed on the insulators 112 and the conductor 114, etc., and the insulator 11 8 is formed on the insulator 117, which is different from the transistor 12.

[0279] Also, the capacitor element 14b differs from the capacitor element 14 in that the insulators 112 and 106c are used as the dielectric.

[0280] As the insulator 117, an insulator that can be used for the insulator 116 may be used. Here, the film formation of the insulator 117 is preferably performed by a sputtering method, and more preferably performed by a sputtering method in an oxygen-containing atmosphere. By forming the insulator 117 by the sputtering method, oxygen is added near the surface of the insulator 112 (the interface between the insulator 117 and the insulator 112 after the film formation of the insulator 117) during the film formation.

[0281] The insulator 117 is an insulator that is less permeable to oxygen than the insulator 112 and blocks oxygen. By providing such an insulator 117, When oxygen is supplied from the body 112 to the insulator 106a, the semiconductor 106b, and the insulator 106c, Therefore, it is possible to prevent the oxygen from being discharged to the outside above the insulator 112. Aluminum oxide is permeable to both impurities such as hydrogen and moisture, and oxygen. Since the insulating effect is high, it is preferable to use it for the insulator 117.

[0282] However, the memory cell 10b is not limited to the configuration shown in FIGS. 14(C) and 14(D). For example, a portion of the insulator 106 or the insulator 112 may be patterned.

[0283] The memory cell 10c shown in FIG. 14(E) and (F) is mainly a transistor 12c. The transistor 12c is different from the transistor 12 in that the conductor 108a and the conductor 108b are insulated from each other. The insulating layer 118 is formed on the semiconductor 106b and is in contact with the semiconductor 106b through an opening formed in the insulating layer 118. In this respect, an insulator 137 is formed on the conductor 108a and the conductor 108b, and an insulator 13 7, and an insulator 138 is formed on the insulator 137 and the conductor 122. The insulator 117 is formed to cover the insulator 106c and the like, and the conductive The side edges of the body 114 and the insulator 112 are generally aligned. The transistor 12 is different from the transistor 12. The low resistance regions 109a and 109b functioning as source and drain regions are used as gates. This is a gate last method in which the gate is formed before the formation of the functional conductor 114. In the transistor manufacturing process, the source region or the drain region of the transistor 12c is The low-resistance regions 109a and 109b that function as gates are formed after the formation of the conductor 114 that functions as a gate, which is a gate first process. It is formed later after the formation of the conductor 114 that functions as a gate, which is a gate first process.

[0284] In the transistor 12c, the low-resistance regions 109a and 109b contain at least one of the elements contained in the insulator 117. A part of the low-resistance regions 109a and 109b preferably substantially contacts or overlaps with the region (channel formation region) that overlaps with the conductor 114 of the semiconductor 106b. Also, since the elements contained in the insulator 117 are added to the low-resistance regions 109a and 109b, the concentration of the elements obtained by SIMS analysis is higher in the low-resistance regions 109a and 109b of the semiconductor 106b than in the regions excluding the low-resistance regions 109a and 109b (for example, the region that overlaps with the conductor 114 of the semiconductor 106b). A part of the low-resistance regions 109a and 109b preferably substantially contacts or overlaps with the region (channel formation region) that overlaps with the conductor 114 of the semiconductor 106b. It is preferably substantially in contact with or overlaps a part of the region.

[0285] Also, since the elements contained in the insulator 117 are added to the low-resistance regions 109a and 109b, the concentration of the elements obtained by SIMS analysis is higher in the low-resistance regions 109a and 109b of the semiconductor 106b than in the regions excluding the low-resistance regions 109a and 109b (for example, the region that overlaps with the conductor 114 of the semiconductor 106b). The elements added to the low-resistance regions 109a and 109b are preferably, for example, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, or tungsten. These elements are relatively likely to form oxides, and the oxides can function as semiconductors or insulators, so they are suitable as additive elements for the insulator 106a, the semiconductor 106b, or the insulator 106c. For example, the above elements are present in the low-resistance regions 109a and 109b at 1×10 / cm or more and 2×10

[0286] The elements added to the low-resistance regions 109a and 109b are preferably, for example, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, or tungsten. These elements are relatively likely to form oxides, and the oxides can function as semiconductors or insulators, so they are suitable as additive elements for the insulator 106a, the semiconductor 106b, or the insulator 106c. For example, the above elements are present in the low-resistance regions 109a and 109b at 1×10 / cm or more and 2×10 / cm The elements added to the low-resistance regions 109a and 109b are preferably, for example, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, or tungsten. These elements are relatively likely to form oxides, and the oxides can function as semiconductors or insulators, so they are suitable as additive elements for the insulator 106a, the semiconductor 106b, or the insulator 106c. For example, the above elements are present in the low-resistance regions 109a and 109b at 1×10 / cm or more and 2×10 / cm 14 / cm 2 or more and 2×10 16 / cm 2It is preferable to include the following Moreover, the low-resistance regions 109a and 109b in the insulator 106c have a higher concentration of the above-described elements than the regions that are not the low-resistance regions 109a and 109b of the insulator 106c (for example, the regions overlapping with the conductor 114 of the insulator 106c).

[0287] Also, since the low-resistance regions 109a and 109b can be n-type doped by including nitrogen, the nitrogen concentration obtained by SIMS analysis is higher than that of the regions other than the low-resistance regions 109a and 109b of the semiconductor 106b (for example, the regions overlapping with the conductor 114 of the semiconductor 106b).

[0288] By forming such low-resistance regions 109a and 109b, the contact resistance between the conductor 108a or conductor 108b and the insulator 106a, semiconductor 106b, or insulator 106c can be reduced, so that the on-current of the transistor 12c can be increased.

[0289] In the transistor 12c, the semiconductor 106b is provided so as to be surrounded by the insulator 106a and the insulator 106c. Therefore, the side end portions of the semiconductor 106b, particularly the vicinity of the side end portions in the channel width direction, are provided in contact with the insulator 106a and the insulator 106c. As a result, a continuous junction is formed between the insulator 106a or insulator 106c and the vicinity of the side end portions of the semiconductor 106b, and the density of defect levels is reduced. Therefore, even if the on-current easily flows by providing the low-resistance regions 109a and 109b, the side end portions of the semiconductor 106b in the channel width direction do not become parasitic channels, and stable electrical characteristics are obtained. ​​​​​​​​​​​​​can be obtained.

[0290] The capacitance element 14c is a capacitance element in that an insulator 137 is used as a dielectric. The insulator 137 and the insulator 138 are different from the insulator 118. Any insulator that can be used may be used.

[0291] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0292] (Embodiment 3) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using Figure 20.

[0293] In the following, the A1-A2 cross section of the memory cell 10 constituting the three-dimensional memory cell array 40 will be described. A method for fabricating the three-dimensional memory cell array 40 will be described with attention to the plane and the A3-A4 cross section. Although only one memory cell 10 is shown in the figure, memory cells formed on the same plane 10 (for example, memory cells 10(1,1,1) to (m 1 ,1,m 3 ) etc.) can be made simultaneously.

[0294] First, a substrate on which the selection transistor array 50 is formed is prepared. The transistor array 50 is made of an insulator 1 shown in FIGS. 32, the semiconductor 134, the insulator 136, and the conductor 120 before being formed. The selection transistor array 50 may be fabricated by any known method.

[0295] First, a film is formed as the insulator 104. As the insulator 104, any of the above insulators may be used.

[0296] The film formation of the insulator 104 can be carried out by using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecu lar Beam Epitaxy) method, or a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, an atomic layer deposition (ALD: Atomic Lay er Deposition) method, etc.

[0297] Note that the CVD method can be classified into a plasma-enhanced CVD (PECVD) method that uses plasma, a thermal CVD (TCVD) method that uses heat, a photo CVD method that uses light, etc. Further, depending on the raw material gas used, it can be divided into a metal CVD (MCVD) method and a metal organic CVD Enhanced CVD) method, a thermal CVD (TCVD: Thermal C VD) method, a photo CVD method that uses light, etc. Furthermore, depending on the raw material gas used, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method. (MOCVD: Metal Organic CVD) method.

[0298] Note that in order to reduce the water or hydrogen contained in the insulator 104, it is preferable to perform film formation while heating the substrate. It is preferable to perform film formation while heating the substrate in order to reduce the water or hydrogen contained in the insulator 104.

[0299] Also, it is preferable that the upper surface or the lower surface of the semiconductor 106b to be formed later has high flatness. For this reason, a planarization process such as a CMP process may be performed on the upper surface of the insulator 104 to improve the flatness. For this reason, a planarization process such as a CMP process may be performed on the upper surface of the insulator 104 to improve the flatness. It may be performed.

[0300] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the water or hydrogen in the insulator 104 can be further reduced. Also, in some cases, the insulator 104 can be made to have excess oxygen. The heat treatment is 250°C or higher and 650°C or lower, preferably 450 Next, it is preferable to perform a heat treatment. By performing the heat treatment, the water or hydrogen in the insulator 104 can be further reduced. Also, in some cases, the insulator 104 can be made to have excess oxygen. The heat treatment is 250°C or higher and 650°C or lower, preferably 450 °C or higher and 650°C or lower, preferably 450 It may be carried out at a temperature of 600 °C or lower, more preferably 520 °C or higher and 570 °C or lower. The heat treatment is carried out in an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment is carried out in an inert gas atmosphere, and then, in order to supplement the desorbed oxygen, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By the heat treatment, the crystallinity of the insulator 126a and the semiconductor 126b can be enhanced, and impurities such as hydrogen and water can be removed. The heat treatment can also be carried out using an RTA apparatus by lamp heating. Since the heat treatment by the RTA apparatus takes a shorter time than a furnace, it is effective for increasing productivity.

[0301] In addition, depending on the configuration of the selection transistor array 50, etc., it may be preferable to heat in a relatively low temperature range (for example, a temperature range of about 350 °C or higher and 445 °C or lower).

[0302] Next, an insulator that will become the insulator 106a is formed in a subsequent step. As the insulator, an insulator or semiconductor that can be used as the above-described insulator 106a can be used. The formation of the insulator can be carried out using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0303] Next, a semiconductor that will become the semiconductor 106b is formed in a subsequent step. As the semiconductor, a semiconductor that can be used as the above-described semiconductor 106b can be used. The formation of the semiconductor can be carried out using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. This can be achieved. By continuously performing the film formation of the insulator that becomes the insulator 106a and the film formation of the semiconductor that becomes the semiconductor 106b without exposing them to the atmosphere, the incorporation of impurities into the film and at the interface can be reduced.

[0304] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the hydrogen concentration of the insulator 106a and the semiconductor 106b may be reduced. Also, the oxygen deficiency of the insulator 106a and the semiconductor 106b may be reduced. The heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 450°C or higher and 600°C or lower, more preferably 520°C or higher and 570°C or lower. The heat treatment may be performed in an inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure condition. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere condition. By the heat treatment, the crystallinity of the insulator 106a and the semiconductor 106b can be increased and impurities such as hydrogen and water can be removed. The heat treatment can also use an RTA apparatus by lamp heating condition. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time compared to a furnace. When using CAAC-OS as the insulator 106a and the semiconductor 106b, by performing the heat treatment, the peak intensity increases and the full width at half maximum becomes smaller. That is, the crystallinity of CAAC-OS is increased by the heat treatment. Note that, according to the configuration of the selective transistor array 50 and the like, in a relatively low temperature range (for example

[0305] In some cases, it may be preferable to heat in a temperature range of 350°C or higher and 445°C or lower.

[0306] By this heat treatment, oxygen can be supplied to the insulator that becomes insulator 106a from insulator 104 and the semiconductor that becomes semiconductor 106 b. By supplying oxygen to the insulator that becomes insulator 106a and the semiconductor that becomes semiconductor 106b and reducing oxygen deficiency, it is possible to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low density of defect levels. and the semiconductor that becomes semiconductor 106b, and reducing oxygen deficiency, it is possible to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low density of defect levels. It is possible to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low density of defect levels. It is possible.

[0307] In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c. In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c. In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c. In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c. In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c. In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c. In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c. In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c. In addition, high-density plasma treatment or the like may be performed. The high-density plasma may be generated using microwaves. In the high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate. Thereby, oxygen ions and the like in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when performing the high-density plasma treatment instead of the above heat treatment, the same effect can be obtained at a temperature lower than the temperature of the above heat treatment. The high-density plasma treatment may be performed before the film formation of the insulator that becomes insulator 106a, before the film formation of insulator 116, or before the film formation of insulator 106c.

[0308] Next, a resist or the like is formed on the insulator that becomes insulator 106a and the semiconductor that becomes semiconductor 106b, and the insulator 106a and the semiconductor 106b are formed by processing using the resist or the like (see FIGS. 15(A) and (B)). When simply forming a resist, the resist Next, a resist or the like is formed on the insulator that becomes insulator 106a and the semiconductor that becomes semiconductor 106b, and the insulator 106a and the semiconductor 106b are formed by processing using the resist or the like (see FIGS. 15(A) and (B)). When simply forming a resist, the resist Next, a resist or the like is formed on the insulator that becomes insulator 106a and the semiconductor that becomes semiconductor 106b, and the insulator 106a and the semiconductor 106b are formed by processing using the resist or the like (see FIGS. 15(A) and (B)). When simply forming a resist, the resist This also includes the case where an anti-reflection layer is formed underneath.

[0309] The resist is removed after the object is processed by etching or the like. For this purpose, plasma treatment and / or wet etching are used. Plasma ashing is suitable for this purpose. If removal of resist, etc. is insufficient, Hydrofluoric acid and / or ozone at a concentration of 1% or more by volume and up to 1% by volume. Residual resist may be removed by using aqueous solution or the like.

[0310] Next, it is preferable to perform heat treatment. By performing heat treatment, water in the insulator 104, Alternatively, hydrogen can be further reduced. The heat treatment is performed at a temperature of 250°C to 650°C. The temperature is preferably 450° C. to 600° C., and more preferably 520° C. to 570° C. The heat treatment is preferably carried out in an inert gas atmosphere. The heat treatment may be carried out in an atmosphere containing the fluorine atomizer. The heat treatment may be carried out under reduced pressure. After heat treatment in an active gas atmosphere, oxidizing gas is added at 10 ppm to compensate for the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing 1% or more or 10% or more of lanthanide. An RTA device using a lamp heating system can also be used. Heating with an RTA device is much faster than with a furnace. This is effective in increasing productivity because it takes only a short time.

[0311] In addition, in accordance with the configuration of the selection transistor array 50, a relatively low temperature range (for example For example, it may be preferable to heat the material at a temperature in the range of about 350° C. or more and 445° C. or less.

[0312] Next, a conductor is formed as a film, a resist or the like is formed on the conductor, and the resist or the like is used to Perform processing to form the conductor 108 (see FIGS. 15(C) and (D)). As the conductor used for the conductor 108, the conductors that can be used as the above-described conductor 108a and conductor 108b may be used. For the conductor used for the conductor 108, a conductor that can be used as the above-described conductor 108a and conductor 108b may be used. The film formation of the conductor used for the conductor 108 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0313] Next, the insulator 116 is formed into a film. As the insulator 116, the above-described insulator may be used. The film formation of the insulator 116 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0314] Note that the film formation of the insulator 116 is preferably performed using plasma, more preferably performed using a sputtering method, and even more preferably performed using a sputtering method in an atmosphere containing oxygen. As the sputtering method, a DC (Direct Current) sputtering method using a DC power source for sputtering, a pulsed DC sputtering method for applying a bias pulse, an RF (Radio Frequency) sputtering method using a high-frequency power source for sputtering may be used. Also, a magnetron sputtering method equipped with a magnet mechanism inside the chamber, a bias sputtering method for applying a voltage to the substrate during film formation, a reactive sputtering method performed in a reactive gas atmosphere, or the like may be used. Further, the above-described PESP or VDSP may be used. Note that the oxygen gas flow rate and film formation power of sputtering may be appropriately determined according to the amount of oxygen added and the like.

[0315]

[0316] By forming the insulator 116 by sputtering, oxygen is added near the surface of the insulator 1 04 (the interface between the insulator 104 and the insulator 116 after the formation of the insulator 116). Here, oxygen is added to the insulator 104 as, for example, oxygen radicals, but the state when oxygen is added is not limited to this. Oxygen may be added to the insulator 104 in the state of oxygen atoms or oxygen ions etc. In addition, with the addition of oxygen, oxygen may be contained in the insulator 104 in excess of the stoichiometric composition, and the oxygen at this time can also be called excess oxygen.

[0317] Next, a conductor is formed, a resist or the like is formed on the conductor, and the conductor 122 is formed by processing using the resist or the like (see FIGS. 15(E) and (F)). As the conductor used for the conductor 122, a conductor that can be used as the above-mentioned conductor 122 may be used. The film formation of the conductor used for the conductor 122 can be performed using a sputtering method, a CVD method, an MBE method, or a P LD method, an ALD method, or the like.

[0318] Next, a resist or the like is formed on the conductor 128, and the conductor 108a and the conductor 108b are formed by processing using the resist or the like.

[0319] Next, an insulator that becomes the insulator 118 is formed. As the insulator that becomes the insulator 118, the above-mentioned insulator may be used. The film formation of the insulator that becomes the insulator 118 can be performed using a sputtering method, a CV D method, an MBE method, or a PLD method, an ALD method, or the like.

[0320] Next, a resist or the like is formed on the insulator that becomes the insulator 118, and the resist or the like is used Process and form insulator 118a, conductor 108a, and conductor 108b (see Fig. 16(A )(B)).

[0321] Also, in the regions of semiconductor 106b that are in contact with conductor 108a and conductor 108b, low resistance regions 109a and low resistance regions 109b may be formed. Also, semiconductor 106 b may have a region with a thinner film thickness than the regions where conductor 108a and conductor 108b overlap between conductor 108a and conductor 108b. This is formed by removing a part of the upper surface of semiconductor 106b when forming conductor 108a and conductor 108b. Here, a capacitor element 14 having conductor 108b, insulator 116, and conductor 122 is formed

[0322] Next, an insulator 106d that will become insulator 106c in a later process is formed. An insulator or semiconductor or the like that can be used as the above-mentioned insulator 106c may be used for insulator 106d. The film formation of insulator 106d can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Before the film formation of insulator 106d, the surface of semiconductor 10

[0323] 6b or the like may be etched. For example, etching can be performed using plasma containing a rare gas. Then, by continuously forming insulator 106d without exposing it to the atmosphere, the mixing of impurities into the interface between semiconductor 106b and insulator 106c can be reduced Impurities present at the interface between films or the like may diffuse more easily than impurities in the film. Therefore, by reducing the mixing of such impurities, stable electrical characteristics can be imparted to the transistor ​​​​​​​​

[0324] Next, an insulator 112a that will become the insulator 112 in a later process is formed. As the insulator 112a, an insulator that can be used as the above-described insulator 112 may be used. The formation of the insulator 112 a can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that by continuously performing the formation of the insulator 106d and the formation of the insulator 112a without exposing them to the atmosphere, the incorporation of impurities into the film and at the interface can be reduced.

[0325] Next, a conductor 114a that will become the conductor 114 in a later process is formed (see FIGS. 16(C) and (D)). As the conductor 114a, a conductor that can be used as the above-described conductor 114 may be used. The formation of the conductor 114a can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that by continuously performing the formation of the insulator 112a and the formation of the conductor 114a without exposing them to the atmosphere, the incorporation of impurities into the film and at the interface can be reduced.

[0326] Next, polishing is performed from above the conductor 114a until the insulator 118a is exposed, thereby forming the conductor 114, the insulator 112, the insulator 106c, and the insulator 118 (see FIGS. 16(E) and (F)). The conductor 114 and the insulator 112 each have a function as a gate electrode and a gate insulator of the transistor 12, respectively. By the method described above, the conductor 114 and the insulator 112 can be formed self-alignedly.

[0327] Note that an insulator similar to the above-described insulator 116 is used for the insulator 118, the insulator 106c, and the insulator 11 ​​​2 and the conductor 114 to add oxygen to the insulator 118.

[0328] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 104 (or The oxygen added to the insulator 106a, the semiconductor 106b, and the insulator 118 is diffused to form the insulator 106a, the semiconductor 106b, and the insulator 118. The heat treatment can be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably The heat treatment may be performed at a temperature of 350° C. to 450° C. The heat treatment may be performed in an inert gas atmosphere or in an oxidizing atmosphere. The heat treatment is carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of reactive gas. Heat treatment may be performed under pressure. Heat treatment may also be performed using an RTA device with lamp heating. .

[0329] In addition, the temperature of this heat treatment is preferably lower than that of the heat treatment performed after the formation of the semiconductor film 126b. The temperature difference between the heat treatment after the formation of the semiconductor 126b and the heat treatment after the formation of the semiconductor 126b is 20° C. or more and 150° C. or less, and preferably 4 The temperature is set to 0° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 104 and the like. The heat treatment after the formation of the insulator 118 can be performed in the same manner. In the case where the heat treatment for the insulating layer 118 can be performed by the heat treatment for the insulating layer 118 during the deposition of each layer, In some cases, this may not be necessary (when equivalent heating is performed in the deposition of the film).

[0330] The heat treatment converts the oxygen added to the insulator 104 (or the insulator 118) into an insulating material. The oxygen diffuses into the insulator 104 or the insulator 112. The insulator 116 is more permeable to oxygen than the insulator 104. It is an insulator that does not easily allow oxygen to pass through, and functions as a barrier film that blocks oxygen. Since the insulator 116 is formed on the insulator 104, oxygen diffusing through the insulator 104 is prevented from being absorbed by the insulator 116. It does not diffuse upward from the insulator 104, but mainly diffuses horizontally or downward from the insulator 104.

[0331] Oxygen diffusing in the insulator 104 is supplied to the insulator 106a, the insulator 106c, and the semiconductor 106 b. At this time, since an insulator having a function of blocking oxygen is provided below the insulator 104, oxygen diffused into the insulator 104 can be prevented from diffusing to a layer below the insulator 104. When an insulator similar to the insulator 116 is formed on the insulator 118, oxygen is similarly supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b in the insulator 118. In this way, oxygen can be effectively supplied to the region where the insulator 106a, the insulator 106c, and the semiconductor 106b, particularly the semiconductor 1 06b, form a channel. By supplying oxygen to the insulator 106a, the insulator 106c, and the semiconductor 106b in this way and reducing oxygen deficiency, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low defect level density can be obtained. In this way, the transistor 12 and the capacitor element 14 of the memory cell 10 can be formed. By repeating the above-described steps, memory cells 10 in which the transistor 12 and the capacitor element 14 are formed can be stacked. After stacking the memory cells 10 in which the transistor 12 and the capacitor element 14 are formed, the conductor 120 and the transistor 11 of the three-dimensional memory cell array 40 are formed collectively.

[0332] In the following, a method for manufacturing the conductor 120 and the transistor 11 will be described with reference to FIGS. 17 to 20. 06b, a channel is formed. By supplying oxygen to the insulator 106a, the insulator 106c, and the semiconductor 106b in this way and reducing oxygen deficiency, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low defect level density can be obtained. In this way, oxygen is supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b, and oxygen deficiency is reduced, whereby a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low defect level density can be obtained. By supplying oxygen to the insulator 106a, the insulator 106c, and the semiconductor 106b in this way and reducing oxygen deficiency, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low defect level density can be obtained. In this way, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low defect level density can be obtained.

[0333] In this way, the transistor 12 and the capacitor element 14 of the memory cell 10 can be formed. By repeating the above-described steps, memory cells 10 in which the transistor 12 and the capacitor element 14 are formed can be stacked. After stacking the memory cells 10 in which the transistor 12 and the capacitor element 14 are formed, the conductor 120 and the transistor 11 of the three-dimensional memory cell array 40 are formed collectively. After stacking the memory cells 10 in which the transistor 12 and the capacitor element 14 are formed, the conductor 120 and the transistor 11 of the three-dimensional memory cell array 40 are formed collectively. In the following, a method for manufacturing the conductor 120 and the transistor 11 will be described with reference to FIGS. 17 to 20.

[0334] In the following, a method for manufacturing the conductor 120 and the transistor 11 will be described with reference to FIGS. 17 to 20. This will be described. In the following description, the D1-D2 cross-section in which two memory cells 10 are stacked, the D3-D4 cross-section corresponding to the vicinity of the conductor 120 in FIGS. 12(C)(D), and the D5-D6 cross-section corresponding to the vicinity of the transistor 11 in FIGS. 12(A)(B) will be noted. (C)(D) corresponding to the vicinity of the conductor 120 of Focus on the D5-D6 cross-section corresponding to the vicinity of the transistor 11 in FIGS. 12(A)(B).

[0335] First, the method of forming the conductor 120 will be described with reference to FIG. 17.

[0336] First, a resist or the like is formed on the uppermost memory cell 10, and using the resist or the like, an opening 171 reaching the region 172c of the select transistor cell 60 from the uppermost memory cell 10 is formed (see FIGS. 17(A)(B)). The opening 171 is formed in the three-dimensional memory cell array 40 and is formed in at least the insulator 104, the conductor 108a, the insulator 116, and the insulator 118, and in the select transistor array 50, it is formed in at least the region 172a of the semiconductor substrate 150, the insulators 164, 166, 168, and 170. 1 is formed (see FIGS. 17(A)(B)). The opening 171 is formed to extend in a direction substantially perpendicular to the upper surface of the substrate and has a very high aspect ratio. Therefore, for forming the opening 171, it is preferable to use anisotropic etching in which the etching rate in a direction substantially perpendicular to the upper surface of the substrate is fast. For example, dry etching or the like may be used. Note that when forming the opening 171, a part of the region 172c of the semiconductor substrate 150 may be over-etched to form a concave portion on the surface of the semiconductor substrate 150. 0, and in the select transistor array 50, it is formed in at least the region 172a of the semiconductor substrate 150, the insulators 164, 166, 168, and 170. 8, and in the select transistor array 50, it is formed in at least the region 172a of the semiconductor substrate 150, the insulators 164, 166, 168, and 170. Region 172a, insulators 164, 166, 168, and 170 of the semiconductor substrate 150. It is formed.

[0337] The opening 171 is formed to extend in a direction substantially perpendicular to the upper surface of the substrate and has a very high aspect ratio. Therefore, for forming the opening 171, it is preferable to use anisotropic etching in which the etching rate in a direction substantially perpendicular to the upper surface of the substrate is fast. For example, dry etching or the like may be used. Note that when forming the opening 171, a part of the region 172c of the semiconductor substrate 150 may be over-etched to form a concave portion on the surface of the semiconductor substrate 150. Ratio is high. Therefore, for forming the opening 171, it is preferable to use anisotropic etching in which the etching rate in a direction substantially perpendicular to the upper surface of the substrate is fast. For example, dry etching or the like may be used. Note that when forming the opening 171, a part of the region 172c of the semiconductor substrate 150 may be over-etched to form a concave portion on the surface of the semiconductor substrate 150. Ratio is high. Therefore, for forming the opening 171, it is preferable to use anisotropic etching in which the etching rate in a direction substantially perpendicular to the upper surface of the substrate is fast. For example, dry etching or the like may be used. Note that when forming the opening 171, a part of the region 172c of the semiconductor substrate 150 may be over-etched to form a concave portion on the surface of the semiconductor substrate 150. Ratio is high. Therefore, for forming the opening 171, it is preferable to use anisotropic etching in which the etching rate in a direction substantially perpendicular to the upper surface of the substrate is fast. For example, dry etching or the like may be used. Note that when forming the opening 171, a part of the region 172c of the semiconductor substrate 150 may be over-etched to form a concave portion on the surface of the semiconductor substrate 150. c may be over-etched to form a concave portion on the surface of the semiconductor substrate 150. Yes.

[0338] Next, the conductor 120 is formed in the opening 171 (see FIGS. 17(C)(D)). As the conductor 120, a conductor that can be used as the above-described conductor 120 may be used. Body 120, a conductor that can be used as the above-described conductor 120 may be used. As described above, since the opening 171 has a very high aspect ratio, it is preferable to form the conductor 120 using either the ALD method or the CVD method. Also, when using the CVD method, it is preferable to form the film using the MOCVD method or the MCVD method.

[0339] In addition, in the topmost memory cell 10, it is preferable to cover the upper surface of the conductor 120 with an insulator or the like so that it is not exposed.

[0340] Next, a method for forming the transistor 11 will be described with reference to FIGS. 18 to 20.

[0341] First, a resist or the like is formed on the topmost memory cell 10, and using the resist or the like, an opening 181a is formed that reaches the region 172a of the selected transistor cell 60 from the topmost memory cell 10 (see FIGS. 18(A) and 18(B)). Similar to the opening 171, the opening 181a is also formed in the three-dimensional memory cell array 40 at least in the insulator 104, the conductor 108a, the insulator 116, and the insulator 118, and in the selected transistor array 50 at least in the region 172a of the semiconductor substrate 150, the insulator 164, the insulator 166, the insulator 168, and the insulator 170.

[0342] The opening 181a is formed to extend in a direction substantially perpendicular to the upper surface of the substrate and has a very high aspect ratio. Therefore, similar to the formation of the opening 171, it is preferable to use anisotropic etching with a high etching rate in a direction substantially perpendicular to the upper surface of the substrate when forming the opening 181a. For example, dry etching or the like may be used. When forming the opening 181a, A part of the region 172a of the semiconductor substrate 150 may be overetched, and a concave portion may be formed on the surface of the semiconductor substrate 150. On the surface, a recess may be formed.

[0343] Next, an insulator 132 is formed in contact with the inner wall of the opening 181a (see FIGS. 18(C) and (D)). . As the insulator 132, an insulator that can be used as the above-described insulator 132 may be used. As described above, since the aspect ratio of the opening 181a is very high, it is preferable to form the insulator 132 by using the ALD method or the CVD method or the like. Since the insulator 132 functions as a gate insulating film of the transistor 11, it is preferable that the film thickness uniformity is high. Therefore, in terms of high film thickness controllability, the ALD method is preferable. For this reason, since the insulator 132 functions as a gate insulating film of the transistor 11, it is preferable that the film thickness uniformity is high. Therefore, the ALD method is preferable in terms of high film thickness controllability.

[0344] Next, an opening 181b reaching the region 172a is formed at the bottom of the insulator 132 (see FIGS. 19(A) and (B)). The opening 181b may be formed in at least a part of the bottom surface of the insulator 132. Therefore, the diameter of the opening 181b is often smaller than that of the opening 181a.

[0345] Here, when forming the opening 181b, it is necessary to remove at least a part of the bottom surface of the insulator 132 without removing the insulator 132 formed on the side wall of the opening 181a. Therefore, similar to the formation of the opening 181a, it is preferable to use anisotropic etching in which the etching progress speed in the direction substantially perpendicular to the upper surface of the substrate is fast when forming the opening 181b. For example, dry etching or the like may be used. When forming the opening 181b, a part of the region 172a of the semiconductor substrate 150 may be overetched, and further recesses may be formed on the surface of the semiconductor substrate 150. When forming the opening 181b, a part of the region 172a of the semiconductor substrate 150 may be overetched, and further recesses may be formed on the surface of the semiconductor substrate 150. When forming the opening 181b, a part of the region 172a of the semiconductor substrate 150 may be overetched, and further recesses may be formed on the surface of the semiconductor substrate 150. On the surface, further recesses may be formed.

[0346] Next, a semiconductor 134 is formed inside the insulator 132 (see FIGS. 19(C) and (D)). As the semiconductor 134, a semiconductor that can be used as the above-described semiconductor 134 may be used. Here, the semiconductor 134 is provided in contact with the region 172a.

[0347] As described above, since the opening 181a has a very high aspect ratio, it is preferable to form the semiconductor 134 using the ALD method, the CVD method, or the epitaxial method or the like. By using such a method, for example, single-crystalline silicon or polycrystalline silicon can be formed as the semiconductor 134. Also, after forming amorphous silicon, it may be crystallized by heat treatment or the like to obtain a polycrystalline silicon semiconductor 134.

[0348] When the semiconductor 134 is made of polycrystalline silicon, it is preferable to reduce the film thickness of the semiconductor 134. For example, it is preferably 20 nm or less, more preferably 10 nm or less. By setting the semiconductor 134 to such a film thickness, variations in the characteristics of the transistor 11 can be reduced.

[0349] Also, when forming the semiconductor 134, the semiconductor 134 may be formed so that an impurity that imparts a p-type conductivity type or an impurity that imparts an n-type conductivity type is included in the semiconductor 134.

[0350] Next, an insulator 136 is formed inside the semiconductor 134 (see FIGS. 20(A) and (B)). As the insulator 136, a semiconductor that can be used as the above-described insulator 136 may be used. The film formation of the insulator 136 is preferably performed using the ALD method, the CVD method, or the like. .

[0351] In addition, when polycrystalline silicon is used for the semiconductor 134, hydrogen is contained in the insulator 136. Then, a heat treatment or the like may be performed to terminate the dangling bonds in the semiconductor 134. At this time, an insulator having a blocking effect against hydrogen, water, etc. is used as the insulator 132. This prevents hydrogen from diffusing out during heat treatment and more effectively bonds the semiconductor 134 to the dummy layer. Gring bonds can be terminated.

[0352] After the process shown in FIG. 19(A) and (B), a cylindrical A semiconductor 134 having a rectangular shape may be formed (see FIGS. 20C and 20D).

[0353] In the uppermost memory cell 10, a conductor is provided so as to contact the upper surface of the semiconductor 134. It is preferable to form a film so that the conductor is electrically connected to a low power supply potential.

[0354] In this manner, the conductor 108b, the insulator 132, the semiconductor 134 and the insulator 136 are formed. A vertical transistor 11 can be formed by using the above method. By fabricating the transistor 11, a plurality of transistors included in the three-dimensional memory cell array 40 Therefore, the transistor 11 can be manufactured in a very simple process. This allows shortening of the tact time and improving productivity.

[0355] Through the above steps, a semiconductor device according to one embodiment of the present invention can be manufactured.

[0356] By using the above manufacturing method, a semiconductor device with a large memory capacity per unit area can be manufactured. Alternatively, a semiconductor device having a novel structure in which memory cells are stacked can be provided. It is possible.

[0357] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0358] (Embodiment 4) In this embodiment, details of the oxide semiconductor included in the semiconductor device of one aspect of the present invention will be described below.

[0359] <Structure of Oxide Semiconductor> Hereinafter, the structure of the oxide semiconductor will be described.

[0360] Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semicon ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor), and amorphous oxide semiconductor. There are also others.

[0361] From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystalline oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductors, and nc-OS.

[0362] An amorphous structure is generally isotropic, has no inhomogeneous structure, is in a metastable state where the atomic arrangement is not fixed, has a flexible bond angle, has short-range order but no long-range order, and so on. It is said that there is no such thing.

[0363] That is, a stable oxide semiconductor cannot be called a completely amorphous (completely amorphou s) oxide semiconductor. Also, an anisotropic (for example, having a periodic structure in a minute region) oxide semiconductor cannot be called a completely amorphous oxide semiconductor. On the other hand, an a-l ike OS has an unstable structure that is anisotropic but has voids (also called voids). In terms of being unstable, an a-like OS is physically close to an amorphous oxide semiconductor.

[0364] <caac-os> First, CAAC-OS will be described.

[0365] CAAC-OS is an oxide semiconductor having a plurality of c-axis oriented crystal parts (also referred to as pellets). It is a type of semiconductor.

[0366] The case of analyzing CAAC-OS by X-ray diffraction (XRD) will be described. For example, for CAAC-OS having a crystal of InGaZnO classified into the space group R-3m, when performing a structural analysis by the out-of-plane method, as shown in Fig. 21(A), a peak appears at around a diffraction angle (2θ) of 31°. This peak 4 is attributed to the (009) plane of the InGaZnO crystal. Therefore, it can be confirmed that in CAAC-OS, the crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface (also referred to as the surface to be formed) on which the CAAC-OS film is formed, or the upper surface. In addition to the peak around 2θ of 31°, a peak may also appear at around 2θ of 36°. The peak around 2θ of 36° is caused by a crystal structure classified into the space group Fd-3m. Therefore, it is preferable that CAAC-OS does not show this peak. -peak is attributed to the (009) plane of the InGaZnO crystal. Therefore, in CAAC-OS, 4 it can be confirmed that the crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface (also referred to as the surface to be formed) on which the CAAC-OS film is formed, or the upper surface. In addition to the peak around 2θ of 31°, a peak may also appear at around 2θ of 36°. The peak around 2θ of 36° is caused by a crystal structure classified into the space group Fd-3m. Therefore, it is preferable that CAAC-OS does not show this peak. -peak is attributed to the (009) plane of the InGaZnO crystal. Therefore, in CAAC-OS, it can be confirmed that the crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface (also referred to as the surface to be formed) on which the CAAC-OS film is formed, or the upper surface. In addition to the peak around 2θ of 31°, a peak may also appear at around 2θ of 36°. The peak around 2θ of 36° is caused by a crystal structure classified into the space group Fd-3m. Therefore, it is preferable that CAAC-OS does not show this peak. -peak is attributed to the (009) plane of the InGaZnO crystal. Therefore, in CAAC-OS,

[0367] On the other hand, when performing a structural analysis of CAAC-OS by the in-plane method in which X-rays are incident from a direction parallel to the surface to be formed, a peak appears at around 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO crystal. And even when the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed around 56°, as shown in Fig. 21(B), no distinct peak appears. On the other hand, for single crystal InGa 4 -peak is attributed to the (110) plane of the InGaZnO crystal. And even when the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed around 56°, as shown in Fig. 21(B), no distinct peak appears. On the other hand, for single crystal InGa as shown in Fig. 21(B), no distinct peak appears. On the other hand, for single crystal InGa ZnO 4 When φ scan is performed with 2θ fixed near 56° for ZnO, as shown in Fig. 21(C), six peaks attributed to crystal planes equivalent to the (110) plane are observed. Therefore, from the structural analysis using XRD, it can be confirmed that CAAC-OS has irregular orientations of the a-axis and b-axis.

[0368] Next, CAAC-OS analyzed by electron diffraction will be described. For example, for CAAC-OS having a crystal of InGa ZnO 4 when an electron beam with a probe diameter of 300 nm is incident parallel to the surface to be formed of CAAC-OS, a diffraction pattern ( also referred to as a limited-field electron diffraction pattern.) as shown in Fig. 21(D) may appear. This diffraction pattern includes spots due to the (009) plane of the crystal of I nGaZnO nGaZnO 4 Therefore, it can also be seen by electron diffraction that the pellets included in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface. On the other hand, for the same sample, the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface is shown in Fig. 21(E ). As shown in Fig. 21(E), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen by electron diffraction using an electron beam with a probe diameter of 300 nm that the a-axis and b-axis of the pellets included in CAAC-OS have no orientation. Note that in Fig. 21(E), the first ring is considered to be due to the (010) plane and (100) plane of the crystal of InGaZnO and so on. Also, the second ring in Fig. 21(E) is considered to be due to the (110) plane and so on. the first ring is considered to be due to the (010) plane and (100) plane of the crystal of InGaZnO 4 and so on. Also, the second ring in Fig. 21(E) is considered to be due to the (110) plane and so on.

[0369] ​​​​​Also, by using a transmission electron microscope (TEM), a composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and diffraction pattern of CAAC-OS is observed, and a plurality of pellets can be confirmed. On the other hand, even in a high-resolution TEM image, the boundaries between pellets, that is, grain boundaries (also referred to as grain boundaries), may not be clearly confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur.

[0370]

[0371] Figure 22(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. For the observation of the high-resolution TEM image, a spherical aberration corrector function is used. The high-resolution TEM image using the spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed, for example, by a JEOL JEM-ARM200F atomic-resolution analytical electron microscope manufactured by JEOL Ltd.

[0371] From Figure 22(A), it can be confirmed that there are pellets, which are regions where metal atoms are arranged in layers. It can be seen that the size of one pellet is more than 1 nm or more than 3 nm. Therefore, the pellet can also be called a nanocrystal (nc). Also, CAAC-OS can be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The pellet reflects the unevenness of the formed surface or the upper surface of CAAC-OS and is parallel to the formed surface or the upper surface of CAAC-OS. ​​​​

[0372] Also, FIGS. 22(B) and 22(C) show CAA observed from a direction substantially perpendicular to the sample surface The Cs-corrected high-resolution TEM image of the plane of C-OS is shown. FIGS. 22(D) and 22(E) are images obtained by image processing of FIGS. 22(B) and 22(C), respectively. Hereinafter, the method of image processing will be described. First, an FFT image is obtained by performing a fast Fourier transform (FFT) on FIG. 22(B). Next, in the obtained FFT image, a range between 2.8 nm and 5.0 nm -1 is masked with reference to the origin. -1 Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT :Inverse Fast Fourier Transform) to obtain an image processed image. The image thus obtained is called an FFT filtering image. The FFT filtering image is an image obtained by extracting the periodic components from the Cs-corrected high-resolution TEM image and shows the lattice array. In FIG. 22(D), the disrupted portions of the lattice array are indicated by broken lines. The region surrounded by the broken lines is one pellet. And the portions indicated by the broken lines are the connection parts between the pellets

[0373] In FIG. 22(D), the disrupted portions of the lattice array are indicated by broken lines. The region surrounded by the broken lines is one pellet. And the portions indicated by the broken lines are the connection parts between the pellets Since the broken lines are hexagonal, it can be seen that the pellets are hexagonal. Note that the shape of the pellets is not always a regular hexagon and is often an irregular hexagon.

[0374] In FIG. 22(E), the line between the region where the lattice arrays are aligned and another region where the lattice arrays are aligned is indicated by a dotted line, and the direction of the lattice array is indicated by a broken line. Even in the vicinity of the dotted line, a clear grain boundary cannot be confirmed. When connecting the surrounding lattice points with the lattice points in the vicinity of the dotted line as the center, a distorted hexagon is formed. shapes, pentagons, and / or heptagons can be formed. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because CAAC-OS has a less dense atomic arrangement in the a-b plane direction and can tolerate strain due to changes in the bond distance between atoms caused by the substitution of metal elements. As shown above, CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of pellets (nanocrystals) are connected and have strain. Therefore, CAAC-OS can also be referred to as an oxide semiconductor having CAA crystal (c-axis-aligned a-b-p

[0375] lane-anchored crystal). CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiency). Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element with a stronger binding force to oxygen than the metal elements constituting the oxide semiconductor, such as silicon, will

[0376] deprive the oxide semiconductor of oxygen, disrupt the atomic arrangement of the oxide semiconductor, and become a factor in reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so they will disrupt the atomic arrangement of the oxide semiconductor and become a factor in reducing the crystallinity.

[0377] Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element with a stronger binding force to oxygen than the metal elements constituting the oxide semiconductor, such as silicon, will deprive the oxide semiconductor of oxygen, disrupt the atomic arrangement of the oxide semiconductor, and become a factor in reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so they will disrupt the atomic arrangement of the oxide semiconductor and become a factor in reducing the crystallinity.

[0378] ​When an oxide semiconductor has impurities or defects, its characteristics may vary due to light, heat, etc. This is the case. For example, impurities contained in an oxide semiconductor may act as carrier traps or carrier generation sources. For example, oxygen deficiencies in an oxide semiconductor may act as carrier traps or may become carrier generation sources by capturing hydrogen.

[0379] CAAC-OS with few impurities and oxygen deficiencies is an oxide semiconductor with a low carrier density. Specifically, less than 8×10 11 per cm 3 , preferably less than 1×10 11 / cm 3 less than , more preferably less than 1×10 10 per cm 3 and an oxide semiconductor with a carrier density of 1×10 -9 per cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor with stable characteristics.

[0380] <nc-os> Next, nc-OS will be described.

[0381] The case of analyzing nc-OS by XRD will be described. For example, when performing structure analysis by the out-of-plane method on nc-OS, no peak indicating orientation appears. That is, the crystal of nc-OS has no

[0382] orientation. Also, for example, when a thin film of nc-OS having a crystal 4 of InGaZnO is thinned and an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on a region with a thickness of 34 nm, a ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in Fig. 23(A) is observed. Also, the diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample is shown in Fig. 23(B). From Fig. 23(B), a plurality of spots are observed in the ring-shaped region. Therefore, the order of nc-OS cannot be confirmed by incident

[0383] an electron beam with a probe diameter of 50 nm, but the order can be confirmed by incident an electron beam with a probe diameter of 1 nm. Also, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, as shown in Fig. 23(C), an electron diffraction pattern in which spots are arranged in a substantially

[0384] regular hexagonal shape may be observed. Therefore, it can be seen that The TEM image of the decomposition energy is shown. In the high-resolution TEM image, nc-OS has regions where crystal parts can be confirmed as indicated by the auxiliary lines and regions where clear crystal parts cannot be confirmed. The crystal parts contained in nc-OS have a size of 1 nm or more and 10 nm or less, and particularly often have a size of 1 nm or more and 3 nm or less. An oxide semiconductor having a crystal part with a size larger than 10 nm and 100 nm or less may be called a microcrystalline oxide semiconductor. In nc-OS, for example, in a high-resolution TEM image, there are cases where grain boundaries cannot be clearly confirmed. Note that the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, hereinafter, the crystal parts of nc-OS may sometimes be referred to as pellets. As described above, nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS does not show regularity in the crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. Note that since there is no regularity in the crystal orientation between the pellets (nanocrystals), nc-OS can also be called an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide semiconductor having NANC (Non-Aligned nanocrystals).

[0385]

[0386]

[0387] ​​​​​​​​​​​​​nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore , the density of defect levels in nc-OS becomes lower than that in a-like OS and amorphous oxide semiconductors . However, no regularity is observed in the crystal orientation among different pellets of nc-OS. Therefore , the density of defect levels in nc-OS becomes higher than that in CAAC-OS.

[0388] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors .

[0389] Fig. 24 shows a high-resolution cross-sectional TEM image of a-like OS. Here, Fig. 24(A) is the high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Fig. 24( B) is the high-resolution cross-sectional TEM image of a-like OS after irradiation with 4.3×10 8 e - / nm 2 electrons (e - ). From Fig. 24(A) and Fig. 24(B), it can be seen that in a-like OS, stripe-like bright regions extending in the longitudinal direction are observed from the start of electron irradiation. Also , it can be seen that the shape of the bright regions changes after electron irradiation. Note that the bright regions are presumed to be loose or low density regions. Since it has looseness, a-like OS has an unstable structure. Below, to show that a-like OS has a more unstable structure compared to CAAC-OS and nc-OS, the change in structure due to electron irradiation is shown.

[0390] As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Any of the samples is In-Ga-Zn oxide.

[0391] ​

[0392] First, high-resolution cross-sectional TEM images of each sample are obtained. All of the materials have crystalline parts.

[0393] In addition, InGaZnO 4 The unit cell of the crystal has three In-O layers and Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers in the c-axis direction. The distance between these adjacent layers is the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is called InGaZ. nO 4 The lattice fringes are considered to be the crystal parts of InGaZnO. 4 It corresponds to the ab plane of the crystal do.

[0394] Figure 25 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes is the size of the crystal part. e. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. As can be seen from Fig. 25, in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was raised (also called the initial nucleus) absorbs electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that within the range up to, there is no change in the size of the crystal part. FIG. 25 From , regardless of the cumulative electron irradiation dose, the sizes of the crystal parts of nc-OS and CAAC-OS are , about 1.3 nm and about 1.8 nm respectively. Note that the electron beam irradiation and TEM observations were carried out using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7×10 5 e - / (nm 2 ·s), and the diameter of the irradiation area was 230 nm.

[0395] Thus, in the case of a-like OS, crystal part growth may be observed by electron irradiation. On the other hand, for nc-OS and CAAC-OS, almost no crystal part growth due to electron irradiation is observed. That is, it can be seen that a-like OS has a less stable structure compared to nc-OS and CAAC-OS.

[0396] Also, because it has looseness, a-like OS has a lower density structure compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal with the same composition. Also, the density of nc-OS and the density of CAA C-OS are 92.3% or more and less than 100% of the density of a single crystal with the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself.

[0397] For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO having a rhombohedral crystal structure 4 is 6.357 g / cm 3 . Thus ​​​​​​​That is, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0398] Note that when there is no single crystal with the same composition, the density corresponding to the single crystal in the desired composition can be estimated by combining single crystals with different compositions at an arbitrary ratio. The density corresponding to the single crystal of the desired composition may be estimated using the weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor has various structures, each having various characteristics. Note that the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0399] As described above, the configurations and methods shown in the present embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments. Note that the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0400] As described above, the configurations and methods shown in the present embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0401] (Embodiment 5) In this embodiment, an application example of a memory device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the previous embodiment is used, for example, in various electronic devices (for example, information devices). ​It can be applied to the storage devices of terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), video recording / playback devices, navigation systems, etc. Here, a computer includes tablet computers, notebook computers, desktop computers, and also large computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, SSDs (solid state drives), etc. Several configuration examples of removable storage devices are schematically shown in FIG. 26. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. FIG. 26(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105, etc. on the substrate 1104. FIG. 26(B) is a schematic diagram of the appearance of an SD card, and FIG. 26(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. In addition to the above, the semiconductor device shown in the previous embodiment can be applied to various storage devices such as memory cards (e.g., SD cards), USB memories, SSDs (solid state drives), etc. FIG. 26 schematically shows several configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. It can be applied to the storage devices of terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), video recording / playback devices, navigation systems, etc. Here, a computer includes tablet computers, notebook computers, desktop computers, and also large computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, SSDs (solid state drives), etc.

[0402] FIG. 26(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105, etc. on the substrate 1104. FIG. 26(B) is a schematic diagram of the appearance of an SD card, and FIG. 26(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. In addition to the above, the semiconductor device shown in the previous embodiment can be applied to various storage devices such as memory cards (e.g., SD cards), USB memories, SSDs (solid state drives), etc.

[0403] FIG. 26(B) is a schematic diagram of the appearance of an SD card, and FIG. 26(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. In addition to the above, the semiconductor device shown in the previous embodiment can be applied to various storage devices such as memory cards (e.g., SD cards), USB memories, SSDs (solid state drives), etc. FIG. 26 schematically shows several configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. By providing a memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip with a wireless communication function may be provided on the substrate 1113. Thereby, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. A semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 etc. of the substrate 1113.

[0404] FIG. 26(D) is a schematic diagram of the appearance of an SSD, and FIG. 26(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DRAM chip may be used. By providing a memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 etc. of the substrate 1153.

Description of Reference Numerals

[0405] 10 Memory cell 10a Memory cell 10b Memory cell 10c Memory cell 11 Transistor 12 Transistor 12a Transistor 12b Transistor 12c Transistor 14 Capacitance element 14b Capacitance element​​​​​​​​​ 14c capacity element 20 memory cell strings 24 transistors 30 two-dimensional memory cell array 40 three-dimensional memory cell array 50 selection transistor array 51 drive circuit 52 circuit 53 drive circuit 54 drive circuit 60 selection transistor cell 61 transistor 62 transistor 101 insulator 102 conductor 103 insulator 104 insulator 105 insulator 106 insulator 106a insulator 106b semiconductor 106c insulator 106d insulator 107 insulator 108 conductor 108a conductor 108b conductor 109a low-resistance region 109b low-resistance region 112 insulator 112a insulator 114 conductor 114a conductor 116 insulator 117 insulator 118 insulator 118a insulator 119 insulator 120 conductor 122 conductor 126a insulator 126b semiconductor 128 conductor 132 insulator 134 semiconductor 134a region 134b region 136 Insulator 137 Insulator 138 Insulator 150 Semiconductor Substrate 154a Conductor 154b Conductor 160 Region 162a Insulator 162b Insulator 164 Insulator 166 Insulator 168 Insulator 170 Insulator 171 Opening 172a Region 172b Region 172c Region 172d Region 174a Conductor 174b Conductor 176a Conductor 176b Conductor 178a Conductor 178b Conductor 178c Conductor 178d Conductor 180a Conductor 180b Conductor 180c Conductor 180d Conductor 181a Opening 181b Opening 1100 USB Memory 1101 Housing 1102 Cap 1103 USB Connector 1104 Substrate 1105 Memory Chip 1106 Controller Chip 1110 SD Card 1111 Housing 1112 Connector 1113 Substrate 1114 Memory Chip 1115 Controller Chip 1150 SSD 1151 Housing 1152 Connector 1153 Substrate 1154 Memory Chip 1155 Memory Chip 1156 Controller Chip

Claims

1. A memory cell is disposed above a substrate; The memory cell includes a first transistor, a second transistor, and a capacitance element, the first transistor includes a cylindrical semiconductor having a height in a direction perpendicular to an upper surface of the substrate, and a first conductive layer; the cylindrical semiconductor has a channel forming region; the first conductive layer has a region functioning as a gate electrode of the first transistor, a region functioning as one of electrodes of the capacitor, and a region functioning as one of a source electrode and a drain electrode of the second transistor; the second transistor has an oxide semiconductor layer and an insulating layer; the oxide semiconductor layer has a channel formation region, the insulating layer has a region located above the oxide semiconductor layer, the first conductive layer has a region in contact with the oxide semiconductor layer through an opening provided in the insulating layer.

2. In claim 1, the second transistor has a second conductive layer; the second conductive layer has a region functioning as the other of the source electrode and the drain electrode, The second conductive layer has a region in contact with a cylindrical conductor having a height in a direction perpendicular to an upper surface of the substrate.

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