Quantizer design

Abstract

To provide a method, a computer program, and a computer system for video coding.SOLUTION: Video data which includes one or more quantization coefficients is received. One or more index values associated with the quantization coefficients are mapped to one or more step values on the basis of an exponential mapping. Video data is decoded on the basis of one or more step values.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] (Reference to Related Application) This application claims priority from U.S. Provisional Patent Application No. 63 / 035,642, filed in the U.S. Patent and Trademark Office on June 5, 2020, and U.S. Provisional Patent Application No. 17 / 098,825, filed on November 16, 2020, both of which are incorporated by reference in their entireties herein.

[0002] The present disclosure relates generally to the field of data processing, and more specifically, to video processing. [Background technology]

[0003] AOMedia Video 1 (AV1) was developed as the successor to VP9 by the Alliance for Open Media (AOMedia), a consortium founded in 2015 that includes semiconductor companies, video-on-demand providers, video content creators, software developers, and web browser vendors. Many of the components of the AV1 project were sourced from previous research efforts by the Alliance members. Individual contributors initiated experimental technology platforms years ago: Xiph / Mozilla's Daala, which already released its code in 2010, Google's experimental VP9 evolution project VP10 announced on September 12, 2014, and Cisco's Thor announced on August 11, 2015. Based on the VP9 code base, AV1 incorporates additional technologies, some of which were developed on these experimental formats. The first version 0.1.0 of the AV1 reference codec was released on April 7, 2016. The Alliance announced the release of the AV1 Bitstream Specification on March 28, 2018, with references to software-based encoders and decoders. A validated version 1.0.0 of the specification was released on June 25, 2018. A validated version 1.0.0 with Errata 1 of the specification was released on January 8, 2019. The AV1 Bitstream Specification includes reference video codecs. AOMedia Video2 (AV2) is currently under development. Summary of the Invention

[0004] Embodiments relate to a method, a computer program, and a computer system for coding video data. According to one aspect, a method for coding video data is provided. The method may include receiving video data including one or more quantized coefficients. One or more index values ​​associated with the one or more quantized coefficients are mapped to one or more step values ​​based on an exponential mapping. The video data is decoded based on the one or more step values.

[0005] According to another aspect, a computer system for coding video data is provided. The computer system may include one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage devices, and program instructions stored in at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, thereby enabling the computer system to perform a method. The method may include receiving video data including one or more quantization coefficients. One or more index values ​​associated with the one or more quantization coefficients are mapped to one or more step values ​​based on an exponential mapping. The video data is decoded based on the one or more step values.

[0006] According to yet another aspect, a computer-readable medium for coding video data is provided. The computer-readable medium may include one or more computer-readable storage devices and program instructions stored in at least one of the one or more tangible storage devices, the program instructions being executable by a processor. The program instructions are executable by the processor for performing a method that may include correspondingly receiving video data including one or more quantization coefficients. One or more index values ​​associated with the one or more quantization coefficients are mapped to one or more step values ​​based on an exponential mapping. The video data is decoded based on the one or more step values.

[0007] These and other objects, features and advantages will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings, in which the various features are not to scale since the illustrations are for clarity in facilitating understanding by those skilled in the art of the detailed description together. [Brief description of the drawings]

[0008] [Figure 1] 1 illustrates a networked computing environment in accordance with at least one embodiment.

[0009] [Figure 2A] FIG. 13 is a diagram of Q_index vs. Qstep mapping for DC & AC coefficients in AV1 in accordance with at least one embodiment.

[0010] [Figure 2B] FIG. 13 is a diagram of a unified Q_index vs. Qstep linear mapping for AV2 in accordance with at least one embodiment.

[0011] [Figure 2C] FIG. 1 is a diagram of a unified Q_index vs. QstepLog2 mapping for AV2 in accordance with at least one embodiment.

[0012] [Diagram 3] 1 is an operational flow diagram illustrating steps performed by a program for compressing a neural network model in accordance with at least one embodiment.

[0013] [Figure 4] FIG. 2 is a block diagram of internal and external components of the computer and server shown in FIG. 1 according to at least one embodiment.

[0014] [Diagram 5] FIG. 2 is a block diagram of an exemplary cloud computing environment that includes the computer system shown in FIG. 1 in accordance with at least one embodiment.

[0015] [Figure 6] FIG. 6 is a block diagram of functional layers of the example cloud computing environment of FIG. 5 in accordance with at least one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Although detailed embodiments of the claimed structures and methods are disclosed herein, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in various forms. However, these structures and methods may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope to those skilled in the art. In the description, details of well-known constructions and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0017] FIELD OF THE DISCLOSURE Embodiments relate generally to the field of data processing, and more specifically to video encoding and decoding. The exemplary embodiments described below provide, among other things, systems, methods, and computer programs for encoding / decoding video data. Thus, some embodiments have the ability to advance the field of computing by enabling improved video coding efficiency through the use of AV2.

[0018] As mentioned above, AOMedia Video 1 (AV1) was developed as a successor to VP9 by the Alliance for Open Media (AOMedia), a consortium founded in 2015 that includes semiconductor companies, video-on-demand providers, video content creators, software developers, and web browser vendors. Many of the components of the AV1 project were sourced from previous research efforts by the Alliance members. Individual contributors started experimental technology platforms many years ago: Xiph / Mozilla's Daala, which already released its code in 2010, Google's experimental VP9 evolution project VP10, which was announced on September 12, 2014, and Cisco's Thor, which was announced on August 11, 2015. Based on the VP9 code base, AV1 incorporates additional technologies, some of which were developed in these experimental formats. The first version 0.1.0 of the AV1 reference codec was released on April 7, 2016. The Alliance announced the release of the AV1 Bitstream Specification along with reference software-based encoders and decoders on March 28, 2018. The validated version 1.0.0 of the specification was released on June 25, 2018. The validated version 1.0.0 with Errata 1 of the specification was released on January 8, 2019. The AV1 Bitstream Specification includes the reference video codecs. Currently, AOMedia Video 2 (AV2) is under development.

[0019] In AV1, the quantization of transform coefficients may apply different quantization step sizes for DC and AC transform coefficients, and different quantization step sizes for luma and chroma transform coefficients. To specify the quantization step size, a base_q_idx syntax element is signaled first in the frame header, which is an 8-bit fixed-length code that specifies the quantization step size for luma AC coefficients. The valid range of base_q_idx is [0,255]. Then, a delta value to base_q_idx for luma DC coefficients, denoted as DeltaQYDc, is further signaled. Furthermore, if there is more than one color plane, a flag diff_uv_delta is signaled to indicate whether Cb and Cr color components apply different quantization index values. If diff_uv_delta is signaled as 0, then only the delta values ​​for base_q_idx for the chroma DC coefficients (denoted as DeltaQUDc) and the AC coefficients (denoted as DeltaQUAc) are signaled. Otherwise, the delta values ​​for base_q_idx for both the Cb and Cr DC coefficients (denoted as DeltaQUDc and DeltaQVDc) and the AC coefficients (denoted as DeltaQUAc and DeltaQVAC) are signaled. However, the AV1 quantization step size has limited resolution.

[0020] Therefore, it may be advantageous to increase the resolution of the quantization step size. In the ongoing AV2 development process, several tools may be used in the quantizer design. For example, separate lookup tables Dc_Qlookup[3]

[0256] and Ac_Qlookup[3]

[0256] may be integrated. Ac_Qlookup[3]

[0256] is retained, and the DC quantization step size is obtained using an offset from it. The default offset is set to 8. In addition, separate lookup tables were used to obtain the quantizer step sizes for 8-bit, 10-bit, and 12-bit internal bit depths, and the step sizes did not show any mathematical relationship. This may be replaced with a modified lookup table for 8-bit internal bit depth. The quantization step size generation process is integrated in such a way that for 10-bit and 12-bit internal bit depths, the corresponding 8-bit step sizes (obtained using Q_index) are scaled by 4 and 16, respectively. Moreover, the range of supported step sizes may be increased without increasing within the range of Q_index.

[0021] Aspects are described herein with reference to flow diagrams and / or block diagrams of methods, apparatus (systems), and computer-readable media according to various embodiments. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer-readable program instructions.

[0022] Referring now to Figure 1, a functional block diagram of a networked computing environment illustrating a video coding system 100 (hereinafter "system") for compressing neural network models is shown. It should be understood that Figure 1 provides only one implementation illustration and does not imply any limitations with respect to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made based on design and implementation requirements.

[0023] The system 100 may include a computer 102 and a server computer 114. The computer 102 may communicate with the server computer 114 via a communication network 110 (hereinafter referred to as the "network"). The computer 102 may include a processor 104 and a software program 108 stored in a data storage device 106 that allows the computer 102 to interface with a user and communicate with the server computer 114. As discussed below with reference to FIG. 4, the computer 102 may include internal components 800A and external components 900A, respectively, and the server computer 114 may include internal components 800B and external components 900B, respectively. The computer 102 may be, for example, a mobile device, a phone, a personal digital assistant, a netbook, a laptop computer, a tablet computer, a desktop computer, or any type of computing device capable of running programs, accessing a network, and accessing a database.

[0024] The server computer 114 may operate in a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS), as discussed below with respect to Figures 5 and 6. The server computer 114 may also be located within a cloud computing deployment model, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud.

[0025] The server computer 114, which may be used to compress the neural network model, is enabled to execute a video coding program 116 (hereinafter "program"), which may interact with the database 112. The video coding program method is described in more detail below with respect to FIG. 3. In one embodiment, the computer 102 may act as an input device, including a user interface, while the program 116 may operate primarily on the server computer 114. In an alternative embodiment, the program 116 may operate primarily on one or more computers 102, while the server computer 114 may be used for processing and storing data used by the program 116. It should be noted that the program 116 may be a stand-alone program or may be integrated into a larger video coding program.

[0026] It should be noted, however, that processing for the program 116 may in some cases be shared between the computer 102 and the server computer 114 in any ratio. In another embodiment, the program 116 may run on more than one computer, a server computer, or some combination of computers and server computers, such as multiple computers 102 in communication with a single server computer 114 across the network 110. In another embodiment, for example, the program 116 may run on multiple server computers 114 in communication with multiple client computers across the network 110. Alternatively, the program may run on a network server in communication with the server and multiple client computers across the network.

[0027] The network 110 may include wired, wireless, or fiber optic connections, or a combination thereof. In general, the network 110 can be any combination of connections and protocols that support communication between the computer 102 and the server computer 114. The network 110 may include various types of networks, such as, for example, a local area network (LAN), a wide area network (WAN) such as the Internet, a telecommunications network such as a public switched telephone network (PSTN), a wireless network, a public switched network, a satellite network, a cellular network (e.g., a fifth generation (5G) network, a long term evolution (LTE) network, a third generation (3G) network, a code division multiple access (CDMA) network, etc.), a public land mobile network (PLMN), a metropolitan area network (MAN), a dedicated network, an ad-hoc network, an intranet, an optical fiber-based network, or the like, and / or a combination of these or other types of networks.

[0028] The number and arrangement of devices and networks shown in Figure 1 are provided as an example. In practice, there may be additional devices and / or networks, fewer devices and / or networks, different devices and / or networks, or different arrangements of devices and / or networks than those shown in Figure 1. Furthermore, two or more devices shown in Figure 1 may be implemented within a single device, or a single device shown in Figure 1 may be implemented as multiple distributed devices. Additionally or alternatively, a set of devices (e.g., one or more devices) of system 100 may perform one or more functions that are described as being performed by another set of devices of system 100.

[0029] 2A, a diagram 200A of Q_index mapping to Qstep for DC and AC coefficients in AV1 is shown. The decoded DeltaQYDc, DeltaQUAc, DeltaQUDc, DeltaQVAc, and DeltaQVDc values ​​may be added to base_q_idx to derive quantization indexes Q_index. These Q_indexes are further mapped to quantization step sizes according to two tables. For DC coefficients, the mapping from quantization index to quantization step size for 8-bit, 10-bit, and 12-bit internal bit depth is specified by lookup table Dc_Qlookup[3]

[0256] , and the mapping from quantization index to quantization step size for 8-bit, 10-bit, and 12-bit is specified by lookup table Ac_Qlookup[3]

[0256] .

[0030] Referring now to FIG. 2B, a diagram 200B of the unified Qstep to Q_index linear mapping for AV2 is shown. The valid range of Q_index is [0,255], which maps to a step size range [4,6879]. Although the step size range is increased, the valid range of Q_index remains the same. This limitation in quantization step resolution is more evident with internal bit depths of 10 and 12 bits, where the corresponding 8-bit step sizes (obtained using q_idx) are scaled by 4 and 16, respectively. This can impact the bitrate granularity that can be achieved by the codec.

[0031] Referring now to FIG. 2C, a diagram 200C of Q_indexLog2 mapping to integrated Qstep for AV2 is shown. The mapping from Q_index to quantization step size may not show a consistent mathematical relationship. While the initial entries of step size show a linear relationship with Q_index, the rest of the mapping is almost exponential. The switch from linear to exponential mapping is not smooth. Moreover, at lower Q_index, there is a sudden jump in step size, which is more obvious for 10-bit and 12-bit internal bit depth coding, because they are scaled up by 4 and 16, respectively.

[0032] While the exponential mapping of Q_index to Qstep can be expressed as

number

number

[0033] In one embodiment, the Q_index can be divided into multiple ranges, and in each range, a, b, and c are kept constant (piecewise exponential). In one embodiment, the value for b can include, but is not limited to, 2. In one embodiment, the value for a can include, but is not limited to, 4, 8, 16, 19, 24, 32. In one embodiment, c can be, but is not limited to, a factor of the range or upper limit of the Q_index. An example of the range of Q_index applied in AV1 is 256. In one embodiment, the value for c can include, but is not limited to, 3, 4, 5, 6, 7, 8, 9, 10, 11, ..., 32, ..., 64.

[0034] According to one or more embodiments, a combination of piecewise linear and exponential mappings of Q_index to Qstep may be used. In one embodiment, the full range of Q_index (e.g., [0,T N ]) can be used to express multiple ranges, e.g., [0,T 0 ], [T 0 +1,T 1 ],...,[T N-1 +1,T N]), and in each range, a linear or exponential mapping can be used. In one embodiment, the value for b can include, but is not limited to, 2. In one embodiment, the value for a can include, but is not limited to, 4, 8, 16, 19, 24, 32. In one embodiment, c can be, but is not limited to, a factor of the range or upper limit of the Q_index. An example of a range of Q_index applied in AV1 is 256. In one embodiment, the value for x can include, but is not limited to, 1, 2, 4, 8. In one embodiment, the value for y can include, but is not limited to, 4, 8, 16, 32.

[0035] According to one or more embodiments, an extended Q_index to Qstep mapping scheme may be used. In one embodiment, the Q_index range can be increased without increasing the Qstep range. In one embodiment, the extended Q_index range is available for 8, 10, 12, 16-bit internal bit depth codec configurations. In one embodiment, the 8-bit internal bit depth codec configuration uses a subset of the extended Q_index. In one embodiment, the extended Q_index range can be flexibly assigned to a subset of the quantization step size range to achieve greater granularity across the range. In one embodiment, the extended Q_index range can be used to achieve more granularity for very high bit rates (lower quantization step size). In one embodiment, the extended Q_index range can be used to achieve more granularity for very low bit rates (higher quantization step size). In one embodiment, the extended Q_index range can be used to achieve more granularity at bit rates other than very high and very low bit rates. In one embodiment, both the Q_index and Qstep ranges are increased.

[0036] According to one or more embodiments, the range of Q_index values ​​depends on the internal bit depth of the codec. In one embodiment, for larger internal bit depths, the range of Q_index values ​​is larger. In one embodiment, when an exponential mapping of Q_index to Qstep is used, for internal bit depth a and internal bit depth b, b is greater than a, and the range of Q_index values ​​for internal bit depths a and b are denoted as [0,QA] and [0,QB], respectively, where QB=QA+(ba). * In one example, the range of Q_index values ​​is [0, 255] for an internal bit depth of 8 bits, and then the range of Q_index values ​​is [0, 255+2] for internal bit depths of 10 bits and 12 bits, respectively. * c] and [0,255+4 * c]. Exemplary values ​​of c include, but are not limited to, 4, 5, 6, 7, 8, 9, 10, 11,..., 32,..., 64. In one embodiment, the Qstep values ​​available for one internal bit depth setting a are a subset of the Qstep values ​​available for a larger internal bit depth setting b, where b is greater than a. In one embodiment, the Qstep values ​​available for one internal bit depth setting a are [Q 0 ,Q 1 ,...,Q NA-1 ], and the available Qstep values ​​for one internal bit depth setting b are [Q 0 ,Q 1 ,...,Q NA-1 ,...,Q NB-1 ].

[0037] In one example, the available Qstep values ​​for one internal bit depth setting of 8 are as follows:

number

[0038] In one example, the available Qstep values ​​for one internal bit depth setting 10 are as follows:

number

[0039] Referring now to Figure 3, an operational flow chart illustrating steps of a method 300 for video coding is shown. In some implementations, one or more process blocks of Figure 3 may be performed by computer 102 (Figure 1) and server computer 114 (Figure 1). In some implementations, one or more process blocks may be performed by another device or devices separate from or including computer 102 and server computer 114.

[0040] At 302, the method 300 includes receiving video data including one or more quantized coefficients.

[0041] At 304, the method 300 includes mapping one or more index values ​​associated with one or more quantized coefficients to one or more step values ​​based on an exponential mapping.

[0042] At 306, the method 300 includes decoding the video data based on the one or more step values.

[0043] It may be appreciated that Figure 3 is only intended to provide an illustration of one implementation and is not intended to imply any limitations on how different embodiments may be implemented. Many modifications to the depicted environment may be made based on design and implementation requirements.

[0044] Figure 4 is a block diagram 400 of internal and external components of the computer shown in Figure 1 in accordance with an exemplary embodiment. It should be appreciated that Figure 4 is only intended to provide an illustration of one implementation and is not intended to imply any limitations regarding the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made based on design and implementation requirements.

[0045] The computer 102 (FIG. 1) and the server computer 114 (FIG. 1) may include respective sets of internal components 800A,B and external components 900A,B shown in FIG. 4. Each of the set of internal components 800 includes one or more processors 820, one or more computer-readable RAMs 822, and one or more computer-readable ROMs 824 on one or more buses 826, one or more operating systems 828, and one or more computer-readable tangible storage devices 830.

[0046] The processor 820 is implemented in hardware, firmware, or a combination of hardware and software. The processor 820 is a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or another type of processing component. In some embodiments, the processor 820 includes one or more processors that can be programmed to perform functions. The bus 826 includes components that enable communication between the internal components 800A,B.

[0047] One or more operating systems 828, software programs 108 (FIG. 1), and video coding programs 116 (FIG. 1) on the server computer 114 (FIG. 1) are stored in one or more computer-readable tangible storage devices 830 for execution by one or more of the respective processors 820 via one or more of the respective RAMs 822 (typically including cache memory). In the embodiment shown in FIG. 4, each of the computer-readable tangible storage devices 830 is a magnetic disk storage device of an internal hard drive. Alternatively, each of the computer-readable tangible storage devices 830 is a semiconductor storage device, such as ROM 824, EPROM, flash memory, optical disk, magneto-optical disk, solid-state disk, compact disk (CD), digital versatile disk (DVD), floppy disk, cartridge, magnetic tape, and / or another type of non-transitory computer-readable tangible storage device capable of storing computer programs and digital information.

[0048] Each set of internal components 800A,B also includes a R / W drive or interface 832 for reading from and writing to one or more portable computer-readable tangible storage devices 936, such as a CD-ROM, a DVD, a memory stick, a magnetic tape, a magnetic disk, an optical disk, or a semiconductor storage device. Software programs, such as software program 108 (FIG. 1) and video coding program 116 (FIG. 1), can be stored in one or more of the respective portable computer-readable tangible storage devices 936, read via the respective R / W drive or interface 832, and loaded onto the respective hard drive 830.

[0049] Each set of internal components 800A,B also includes a network adapter or interface 836, such as a TCP / IP adapter card, a wireless Wi-Fi interface card, or a 3G, 4G, or 5G wireless interface card, or other wired or wireless communication link. The software program 108 (FIG. 1) and the video coding program 116 (FIG. 1) on the server computer 114 (FIG. 1) can be downloaded from an external computer to the computer 102 (FIG. 1) and the server computer 114 via a network (e.g., the Internet, a local area network, or other wide area network) and the respective network adapter or interface 836. From the network adapter or interface 836, the software program 108 and the video coding program 116 on the server computer 114 are loaded onto the respective hard drives 830. The network may include copper wire, optical fiber, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers.

[0050] Each of the set of external components 900A,B may include a computer display monitor 920, a keyboard 930, and a computer mouse 934. The external components 900A,B may also include touch screens, virtual keyboards, touch pads, pointing devices, and other human interface devices. Each of the set of internal components 800A,B also includes a device driver 840 for interfacing to the computer display monitor 920, the keyboard 930, and the computer mouse 934. The device driver 840, the R / W drive or interface 832, and the network adapter or interface 836 include hardware and software (stored in the storage device 830 and / or ROM 824).

[0051] Although this disclosure includes detailed descriptions of cloud computing, it is understood in advance that implementation of the teachings described herein is not limited to a cloud computing environment. Rather, some embodiments may be implemented in conjunction with any other type of computing environment now known or later developed.

[0052] Cloud computing is a model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. The cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0053] Its features are as follows. On-demand self-service: Cloud consumers can unilaterally provide computing capacity, such as server time or network storage, as needed, automatically and without the need for human interaction with the service provider. Broad network access: Capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin and thick client platforms (eg, cell phones, laptops, and PDAs). Resource pooling: Provider computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated according to demand. Consumers generally have no control or knowledge over the exact location of the resources provided, although there is a sense of location independence in that location may be specified at a higher level of abstraction (e.g., country, state, or data center). Rapid elasticity: Capacity can be rapidly and elastically provided, possibly automatically, to rapidly scale out and rapidly release to rapidly scale in. To the consumer, the capacity available for provisioning often appears unlimited and can be purchased at any time and in any amount. Measured service: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported to provide transparency for both providers and consumers of the services utilized.

[0054] The service model is as follows: Software as a Service (SaaS): The capability offered to the consumer is to utilize a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through thin client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying infrastructure, including networks, servers, operating systems, storage, or even individual application capabilities, with the possible exception of user-specific application configuration settings. Platform as a Service (PaaS): The ability offered to consumers to deploy consumer-created or acquired applications, written using programming languages ​​and tools supported by the provider, on a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does have control over the applications deployed and, in some cases, over the configuration of the environment that hosts the applications. Infrastructure as a Service (laaS): The capability offered to consumers is to provide processing, storage, network, and other basic computing resources on which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, deployed applications, and possibly limited control of selected network components (e.g., host firewalls).

[0055] The deployment model is as follows: Private Cloud: The cloud infrastructure is operated exclusively for the organization. It may be managed by the organization or a third party and may be on-site or off-site. Community Cloud: The cloud infrastructure is shared by several organizations to support a particular community with common concerns (e.g., mission, security requirements, policies, and compliance considerations). It may be managed by the organization or a third party and may reside on-site or off-site. Public Cloud: The cloud infrastructure may be made available to the general public or large industry entities and is owned by an organization that sells cloud services. Hybrid Cloud: A cloud infrastructure consists of two or more clouds (private, community or public) that remain unique entities but are joined by standardized or proprietary technologies that allow data and application portability (e.g., cloud bursting for load-balancing between clouds).

[0056] Cloud computing environments are service-oriented with a focus on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0057] Referring to FIG. 5, an exemplary cloud computing environment 500 is shown. As shown, the cloud computing environment 500 includes one or more cloud computing nodes 10 with which local computing devices used by cloud consumers, such as, for example, a personal digital assistant (PDA) or mobile phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N, may communicate. The cloud computing nodes 10 may communicate with each other. The cloud computing nodes 10 may be physically or virtually grouped in one or more networks, such as a private, community, public, or hybrid cloud, or combinations thereof, as described above (not shown). This allows the cloud computing environment 500 to provide infrastructure, platform, and / or software as a service without the cloud consumer having to maintain resources on a local computing device. It will be understood that the types of computing devices 54A-54N shown in FIG. 5 are intended to be merely exemplary, and that the cloud computing node 10 and cloud computing environment 500 may communicate with any type of computerized device over any type of network and / or network-addressable connection (e.g., using a web browser).

[0058] Referring to Figure 6, a set of functional abstraction layers 600 provided by cloud computing environment 500 (Figure 5) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 6 are intended to be merely exemplary, and embodiments are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0059] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, Reduced Instruction Set Computer (RISC) architecture based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0060] The virtualization layer 70 provides an abstraction layer that may provide examples of the following virtual entities: virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75.

[0061] In one example, management layer 80 may provide the following functions: Resource provisioning 81 provides dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, and protection for data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides allocation and management of cloud computing resources such that required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides advance arrangement and procurement of cloud computing resources where future requirements are forecasted according to SLAs.

[0062] Workload tier 90 provides examples of functionality for which a cloud computing environment may be utilized. Examples of workloads and functions that may be provided from this tier include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and video coding 96. Video coding 96 may encode and / or decode video data.

[0063] Some embodiments may relate to systems, methods, and / or computer-readable media at any possible level of technical detail. The computer-readable media may include a computer-readable non-transitory storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform operations.

[0064] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or a suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, punch cards, or mechanically encoded devices such as ridge structures in grooves having instructions recorded thereon, or any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed as being a transitory signal per se, such as electric waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through wires.

[0065] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing / processing device.

[0066] The computer readable program code / instructions for performing the operations may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or object oriented programming languages ​​such as Smalltalk, C++ or equivalent, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform an aspect or operation.

[0067] These computer readable program instructions may be provided to a processor of a general purpose computer, a special purpose computer, or other programmable data processing apparatus to manufacture a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, generate means for implementing the function / acts identified in the block or blocks of the flowcharts and / or block diagrams. These computer readable program instructions may be stored on a computer readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions that implement an aspect of the function / acts identified in the block or blocks of the flowcharts and / or block diagrams.

[0068] The computer readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational steps to generate a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the function / act identified in a block or blocks of the flowcharts and / or block diagrams.

[0069] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer-readable media according to various embodiments. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of instructions, including one or more executable instructions for implementing the specified logical function. The methods, computer systems, and computer-readable media may include additional, fewer, different, or differently arranged blocks than those shown in the figures. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed simultaneously or substantially simultaneously, or the blocks may be executed in the reverse order depending on the functionality involved. It should be noted that each block in the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a special-purpose hardware-based system that performs the specified functions or acts or executes a combination of special-purpose hardware and computer instructions.

[0070] It will be apparent that the systems and / or methods described herein may be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual specialized control hardware or software code used to implement these systems and / or methods is not intended to limit the implementation. Thus, the operation and behavior of the systems and / or methods are described herein without reference to specific software code, and it will be understood that software and hardware may be designed to implement the systems and / or methods based on the description herein.

[0071] No element, act, or instruction used herein should be construed as critical or essential unless expressly stated as such. Also, as used herein, the singular articles are intended to include one or more items and may be used interchangeably with "one or more." Additionally, as used herein, the term "set" is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.) and may be used interchangeably with "one or more." When only one item is intended, "one" or similar terms are used. Also, as used herein, the terms "has," "have," "having," or equivalent terms are intended to be open-ended terms. Additionally, "based on" is intended to mean "based, at least in part, on," unless expressly stated otherwise.

[0072] The description of various aspects and embodiments is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Even if combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of possible implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and / or disclosed in the specification. Although each dependent claim recited below may depend directly on only one claim, the disclosure of possible implementations includes each dependent claim in combination with any other claims in the set of claims. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used in this specification has been selected to best explain the principles of the embodiments, practical applications or technical improvements to the technology found in the marketplace, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A processor-executable method for coding video data, comprising: The method comprises: Encoding the video data into an encoded bitstream; storing the encoded bitstream on a storage medium; the encoding includes quantizing with one or more step values ​​to generate quantized coefficients; the one or more step values ​​are mapped to one or more index values ​​associated with the quantized coefficients based on an extended mapping, a first range associated with the index values ​​is divided into one or more sub-ranges, and one of a linear mapping and an exponential mapping is used for each of the sub-ranges; the linear mapping is of the form Qstep=x*Q_index+y, the exponential mapping is of the form Qstep=a*b Q_index / c, where Qstep is the step value, Q_index is the index value, and a, b, c, x, y are constants within the subrange. method.

2. The method of claim 1 , wherein the extended mapping is based on a combination of a piecewise linear mapping and the exponential mapping.

3. The method of claim 1 , wherein the first range associated with the index value is increased without increasing a second range associated with the step value.

4. The method of claim 3 , wherein the increased first range is increased based on a required granularity of extreme bitrates.

5. The method of claim 3 , wherein the increased first range is flexibly allocated to a subset of the second range.

6. The method of claim 1 , wherein the first range depends on an internal bit depth associated with the video data.

7. The method of claim 6 , wherein the first range is larger for larger internal bit depths.

8. 7. The method of claim 6, wherein the second range for the first internal bit depth is a subset of the second range for the second internal bit depth based on the second internal bit depth being greater than the first internal bit depth.

9. A method described in any one of claims 1 to 8, wherein b is 2.

10. 1. A computer system for coding video data, comprising: one or more computer-readable non-transitory storage media configured to store computer program code; one or more computer processors configured to access said computer program code and to perform the method of any one of claims 1 to 9 as instructed by said computer program code.

11. 1. A non-transitory computer-readable medium having stored thereon a computer program for coding video data, comprising: A non-transitory computer readable medium, the computer program causing one or more computer processors to perform the method of any one of claims 1 to 9.

12. A processor-executable method for coding video data, comprising: The method comprises: Encoding the video data into an encoded bitstream; storing the encoded bitstream on a storage medium; the encoding includes quantizing with one or more step values ​​to generate quantized coefficients; the one or more step values ​​are mapped to one or more index values ​​associated with the quantized coefficients based on a piecewise exponential mapping, a first range associated with the index values ​​is divided into one or more sub-ranges, and a constant exponential mapping is used for each of the sub-ranges. method.

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