Programmable controller and data transfer method

Abstract

To prevent, between a data providing module and a data obtaining module, data from not being retrieved or from being obtained redundantly.SOLUTION: A data obtaining module includes a data receiving unit which, when confirmation information is set, executes data synchronization, and which, after the data synchronization completes, sets obtainment completion information representing the completion of a data transfer. Regarding a data providing module, when the obtainment completion information is set, a confirmation information setting unit discards the confirmation information.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a programmable controller and a data transfer method, and is suitable for application to a programmable controller related to a technique for transferring data between a plurality of modules, for example.

Background Art

[0002] Generally, a programmable controller (hereinafter referred to as "PLC") includes a CPU (Central Processing Unit) module that performs calculations according to a program, and a plurality of modules having dedicated functions such as input / output of data such as analog data or digital data, temperature measurement, or each communication method such as serial communication. When synchronizing data with the CPU module, these plurality of modules generally communicate with each other in a refresh process synchronized with the execution of the program. As techniques for transferring data between the CPU module and the plurality of modules, there are techniques disclosed in Patent Documents 1 and 2.

[0003] Patent Document 1 discloses a technique for confirming data consistency between a plurality of devices through connection states of a plurality of devices operating asynchronously, data acquired in time series, and loopback checks of a confirmation tool. Patent Document 2 discloses a technique for synchronizing the processing cycle of data between a plurality of devices with the timing of refresh.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the technique disclosed in Patent Document 1, it is not considered to check whether data acquired in time series is acquired repeatedly among a plurality of devices operating asynchronously. Therefore, there is a possibility that synchronization of the data acquisition states among the plurality of devices cannot be achieved, and it is conceivable that data is acquired repeatedly. In particular, if one device continues slow processing at regular intervals and the other device operates even slightly faster, there is a risk that the other device may miss data or acquire it repeatedly. On the other hand, in the technique disclosed in Patent Document 2, completion information indicating that the processing of the data has been completed is not managed for the data to be processed, and there is a risk that data may be missed or acquired repeatedly.

[0006] The present invention has been made in consideration of the above points, and intends to propose a programmable controller and a data transfer method capable of preventing data omission or duplicate acquisition between a data providing module and a data acquisition module.

Means for Solving the Problems

[0007] In order to solve such problems, in the present invention, there is provided a programmable controller including a data acquisition module that acquires data, and a data providing module that transfers data from an external device to the data acquisition module, wherein the data providing module includes a determination information setting unit that sets determination information indicating that the preparation of the data to be output to the data acquisition module has been completed, and a synchronization unit that transfers the data to the data acquisition module when the determination information is set; the data acquisition module has a data reception unit that executes synchronization of the data when the determination information is set, and sets acquisition completion information indicating that the transfer of the data has been completed when the synchronization of the data is completed; and when the acquisition completion information is set, the data providing module causes the determination information setting unit to discard the determination information.

[0008] In the present invention, there is also provided a data transfer method for a programmable controller in which a data providing module transfers data from an external device to a data acquisition module. The data providing module includes a confirmation information setting step of setting confirmation information indicating that the preparation of the data to be output to the data acquisition module has been completed, a synchronization step of transferring the data to the data acquisition module to synchronize the data when the confirmation information is set, and a data reception step of the data acquisition module executing the synchronization of the data and setting acquisition completion information indicating that the transfer of the data has been completed when the synchronization of the data is completed. In the confirmation information setting step, the data providing module discards the confirmation information when the acquisition completion information is set.

Effect of the Invention

[0009] According to the present invention, it is possible to prevent data omission or duplicate acquisition between the data providing module and the data acquisition module.

Brief Description of the Drawings

[0010]

Figure 1

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments are examples for explaining the present invention, and for the sake of clarity of explanation, omissions and simplifications are made as appropriate. The present invention can be implemented in various other forms. Unless otherwise particularly limited, each component may be singular or plural. In the drawings, the positions, sizes, shapes, ranges, etc. of the components shown may not represent the actual positions, sizes, shapes, ranges, etc. in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.

[0012] As examples of various types of information, it may be described in expressions such as "table", "list", "queue", etc., but the various types of information may be represented by data structures other than these. For example, various types of information such as "XX table", "XX list", "XX queue" may be referred to as "XX information". When explaining identification information, expressions such as "identification information", "identifier", "name", "ID", "number" are used, but these can be mutually replaced.

[0013] When there are a plurality of components having the same or similar functions, they may be described by attaching different subscripts to the same reference numeral. Also, when it is not necessary to distinguish these plurality of components, the subscripts may be omitted in the description.

[0014] In an embodiment, the processing performed by executing a program may be described. Here, a computer executes a program by a processor (e.g., CPU, GPU), and performs the processing defined by the program while using a storage resource (e.g., memory) and an interface device (e.g., communication port), etc. Therefore, the subject of the processing performed by executing the program may be the processor. Similarly, the subject of the processing performed by executing the program may be a controller, a device, a system, a computer, or a node having a processor. The subject of the processing performed by executing the program only needs to be an arithmetic unit, and may include a dedicated circuit for performing a specific processing. Here, the dedicated circuit is, for example, an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), a CPLD (Complex Programmable Logic Device), etc.

[0015] The program may be installed in a computer from a program source. The program source may be, for example, a program distribution server or a storage medium readable by a computer. When the program source is a program distribution server, the program distribution server includes a processor and a storage resource for storing the program to be distributed, and the processor of the program distribution server may distribute the program to be distributed to other computers. Also, in an embodiment, two or more programs may be realized as one program, or one program may be realized as two or more programs.

[0016] (1) First Embodiment FIG. 1 is a block diagram showing a configuration example of a programmable controller (hereinafter referred to as "PLC") 1 according to the first embodiment. The PLC 1 includes a plurality of modules, and includes at least one data providing module that provides data (and instructions) and a data acquisition module that acquires data. In the present embodiment, as an example of the data providing module, an analog module 100 that measures voltage and current from an external device 10 is cited. On the other hand, as an example of the data acquisition module, a CPU module 200 that communicates with a module having a dedicated function including program processing and the analog module 100 is cited.

[0017] In the illustrated example, the external device 10 is connected to the analog module 100, and the program creation device 7 is connected to the CPU module 200. The external device 10 is a device that generates analog data (hereinafter referred to as "unit analog data") for each time series. On the other hand, the program creation device 7 is, for example, a device that writes a control program to the CPU module 200.

[0018] The processing speed of the CPU module 200 is different from the processing speed of the analog module 100. Specifically, the processing speed of the CPU module 200 is higher than the processing speed of the analog module 100.

[0019] The analog module 100 includes an AD (Analog-to-digital) converter 5 and an MPU (Micro-processing unit) 2. Preferably, the analog module 100 further includes a buffer 3 for storing data from an external device and a built-in register capable of storing each flag.

[0020] The AD converter 5 is an example of a conversion unit and has a function of performing A / D conversion on data for each time series. The AD converter 5 converts, for example, unit analog data for each time series input from the external device 10 into digital data for each time series (hereinafter referred to as "unit digital data").

[0021] The MPU 2 receives the unit digital data after conversion by the AD converter 5, performs calculation processing such as scaling on the unit digital data as necessary, and stores the unit digital data in the buffer 3.

[0022] The buffer 3 is a storage area capable of temporarily storing data and various flags. This buffer 3 has a function of temporarily storing data for communication with, for example, an MPU (Micro-processing unit) 2 that performs arithmetic processing. The buffer 3 includes, for example, a flag area 3a and a data area 3b. The flag area 3a stores a data confirmation flag and a data capture completion flag, which will be described later. The flag area 3a preferably further stores a data non-captured flag, which will be described later.

[0023] The data area 3b is a storage area capable of temporarily storing data to be output to the CPU module 200. In the data area 3b, the unit digital data for each time series on which calculation processing has been performed by the MPU 2 is gradually stored. When all the unit digital data is stored, a block of digital data is stored. In this embodiment, the completion of the preparation for acquiring the digital data when a block of digital data is aligned in the data area 3b is referred to as "confirmation".

[0024] In this embodiment, the buffer 3 described above is described as being provided in the analog module 100. Instead, the buffer 3 may be provided in the CPU module 200, or may be provided in each of the CPU module 200 and the analog module 100. The buffer 3 may be configured to be built into the MPU 2. Also, in this embodiment, information regarding data transfer and setting information of the above-described modules 200 and 300 may be held in the buffer 3. Further, in this embodiment, a dedicated IC such as an ASIC may be provided for speeding up, and part of the processing may be performed.

[0025] The PLC1 has the above configuration, and next, an overview of its operation will be briefly described. The CPU module 200 requests data from the analog module 100. When the analog module 100 receives a data request from the CPU module 200, it delivers the digital data stored in the data area 3b of the buffer 3 to the CPU module according to the settings of each flag. The timing of the data request may be based on any trigger.

[0026] When requesting data, the CPU module 200 can also request not only digital data but also setting information of the analog module 100, etc. After the analog module 100 finishes delivering digital data to the CPU module 200, it cancels the data request from the CPU module 200. The CPU module 200 stores the content input from the program creation device 7 in the memory 6 and performs program processing based on that content.

[0027] Figure 2 is a software configuration diagram showing a configuration example of the functional blocks of the analog module 100 and the CPU module 200. The analog module 100 includes a determination information setting unit 100a and a synchronization unit 100b.

[0028] The determination information setting unit 100a sets the data determination flag, which is an example of determination information, to "1" to indicate that the preparation of the digital data to be output to the CPU module 200 is completed. Note that as the determination information, other forms of information may be used instead of a flag such as this data determination flag.

[0029] When the A / D conversion is completed by the AD converter 5, the determination information setting unit 100a sets the data determination flag to "1".

[0030] When the data confirmation flag is "1", the synchronization unit 100b outputs (delivers) digital data to the CPU module 200. Additionally, the synchronization unit 100b may also output to the CPU module 200 that the data confirmation flag is "1". Thereby, the CPU module 200 can accurately grasp the timing at which it can acquire digital data from the analog module 100.

[0031] On the other hand, the CPU module 200 includes a data reception unit 200a. When the data confirmation flag is "1", the data reception unit 200a executes synchronization of the digital data, and when the synchronization of the digital data is completed, it sets the data capture completion flag, which is an example of acquisition completion information, to "1". Note that as the acquisition completion information, information in other forms may be used instead of a flag such as this data capture completion flag.

[0032] The data reception unit 200a may, for example, transmit the data capture completion flag to the analog module 100. When the data reception unit 200a of the CPU module 200 cannot acquire digital data, for example, it transmits a data non-captured flag set to "1" to the analog module 100. By doing so, the analog module 100 can accurately grasp that the CPU module 200 could not capture the digital data.

[0033] The analog module 100 that has acquired the data non-captured flag which is "1" holds the digital data until the data capture completion flag is set to "1". By doing so, the analog module 100 can accurately grasp that the CPU module 200 has not captured the digital data until the CPU module 200 surely captures the digital data.

[0034] When the analog module 100 that has acquired the data non-captured flag which is "1" acquires the data capture completion flag of the CPU module 200, it sets the data non-captured flag to "0" (that is, discards the data non-captured flag).

[0035] In the analog module 100, when the data acquisition completion flag set to "1" is acquired, the determination information setting unit 100a sets the data determination flag to "0" (that is, discards the data determination flag). When the data determination flag is set to "0" in this way, if data of different time series is being converted by the AD converter 5, the data determination flag is set to "1" again by the determination information setting unit 100a.

[0036] If the data reception unit 200a fails to acquire digital data, it sends the data acquisition completion flag "0" to the analog module 100. Thereby, the analog module 100 can surely grasp that the CPU module 200 has failed to acquire digital data.

[0037] When the analog module 100 acquires the data acquisition completion flag "0", it holds the information until it acquires the data acquisition completion flag "0" of the CPU module 200. By doing so, the analog module 100 can surely grasp whether the CPU module 200 has received the data.

[0038] When the analog module 100 holding the data acquisition completion flag "0" acquires the data acquisition completion flag "1" (acquisition completion information) from the CPU module 200, it sets the data non-acquisition flag, which is an example of the acquisition incomplete information, to "0" (that is, discards the data non-acquisition flag). Note that, as the acquisition incomplete information, information in other forms may be used instead of a flag such as this data non-acquisition flag.

[0039] Here, the outline of the data transfer method according to the present embodiment will be described. The data transfer method is a data transfer method of the programmable controller 1 in which the analog module 100 transfers data from the external device 10 to the CPU module 200. The analog module 100 sets a data confirmation flag indicating that the preparation of the data to be output to the CPU module 200 is completed to "1" in a confirmation information setting step, and when the data confirmation flag is set to "1", the analog module 100 transfers the data to the CPU module 200 in a synchronization step. When the data confirmation flag is set to "1", the CPU module 200 executes data synchronization, and when the data synchronization is completed, the CPU module 200 sets a data reception completion flag indicating that the data transfer is completed to "1" in a data reception step. In the confirmation information setting step, when the data reception completion flag is set to "1", the analog module 100 discards the data confirmation flag and sets it to "0".

[0040] FIG. 3 is a flowchart showing the procedure when the analog module 100 writes the acquired data to the CPU module 200 after the measurement is completed.

[0041] The synchronization unit 100b of the analog module 100 starts a data writing process of writing each unit digital data input from the external device 10 to the data area 3b of the buffer 3 at the stage when all the unit digital data are aligned and the preparation is completed (step S101).

[0042] If it is the first process of the above-described process cycle for aligning each unit digital data (that is, the process of aligning the first unit digital data) (step S102: YES), the confirmation information setting unit 100a of the analog module 100 reads each flag in the flag area 3a of the buffer 3 (data confirmation flag, data reception completion flag, preferably data confirmation flag) (step S103). Here, "the process cycle is the first process" indicates, for example, that it is the first unit digital data of the digital data composed of a plurality of unit digital data.

[0043] When the result of referring to the data acquisition completion flag by the confirmation information setting unit 100a of the analog module 100 is "1" and the CPU module 200 has completed data acquisition (step S104: YES), all flags (data confirmation flag, data acquisition completion flag, data not acquired flag) are set to "0" and written to the flag area 3a of buffer 3 (step S107).

[0044] On the other hand, when the result of referring to the data acquisition completion flag by the confirmation information setting unit 100a of the analog module 100 is "0" and the CPU module 200 has not completed data acquisition, the data not acquired flag is set to "1" (step S106), written to the flag area 3a of buffer 3 (step S107), and digital data is written to the CPU module 200 (step S108).

[0045] When it is determined that the processing cycle is the last processing (step S109: YES), the confirmation information setting unit 100a of the analog module 100 reads each flag from the flag area 3a of buffer 3 (step S110), sets the data confirmation flag to "1" and the data acquisition completion flag to "0" (step S111), and writes it to the flag area 3a of buffer 3 (step S112). Here, "the processing cycle is the last processing" indicates, for example, that it is the last unit digital data of digital data composed of a plurality of unit digital data.

[0046] On the other hand, when it is determined in step S109 that it is not the last processing of the processing cycle, the analog module 100 returns to step S102 described above and executes each step in the same manner as above instead of executing steps S110 to S112 described above.

[0047] FIG. 4 is a flowchart showing an example of the procedure of the monitoring process of the data acquisition completion flag on the analog module 100 side. The monitoring process is executed at regular intervals.

[0048] When the monitoring process of the data capture completion flag is started (step S201), the determination information setting unit 100a of the analog module 100 checks the data capture completion flag read from the flag area 3a of the buffer 3 (step S202).

[0049] When the data capture completion flag is "1" and the capture of digital data is completed (step S203), the determination information setting unit 100a sets each flag (data determination flag, data capture completion flag, data not captured flag) to "0" (step S204) and writes it to the flag area 3a of the buffer 3 (step S205).

[0050] On the other hand, when the capture of digital data is not completed, the determination information setting unit 100a does not execute steps S204 and S205.

[0051] FIG. 5 is a flowchart showing an example of the procedure of the data capture process on the CPU module 200 side. When reading digital data, the CPU module 200 reads each flag (data determination flag, data capture completion flag, data not captured flag) from the flag area 3a of the buffer 3 (step S301) and checks each flag.

[0052] If the data capture completion flag is "0" and the capture of digital data is not completed (step S302:0), next, the CPU module 200 checks whether the digital data is determined by checking the data determination flag. If the data determination flag is "1" and it can be confirmed that the data is determined (step S303), the CPU module 200 captures the target digital data from the data area 3b of the buffer 3 (step S304).

[0053] The CPU module 200 checks the data unacquired flag. When the data unacquired flag is "0" and there is no unacquired digital data (step S306:0), it sets the data acquisition completion flag to "1" and writes the data acquisition completion flag to the flag area 3a of buffer 3 (step S309).

[0054] When there is unacquired data (step S306:1), the CPU module 200 handles the unacquired digital data (step S307). Specifically, in this embodiment, for example, a mechanism for recording the timing when there is unacquired data in an application or the like as needed may be provided.

[0055] If the unacquired data has been handled, the CPU module 200 sets the data acquisition completion flag to "1" (step S308) and writes the data acquisition completion flag to the flag area 3a of buffer 3 (step S309).

[0056] In this embodiment, by providing buffer 3, a certain amount of data can be stored, and by reading and writing digital data in batches, the number of accesses between the CPU module 200 and the analog module 100 can be reduced, and the processing speed can be increased.

[0057] FIG. 6 is a timing chart showing an example of the digital data transfer timing between a plurality of modules. As shown in the figure, in the analog module 100, when the digital data is determined, the data determination flag is set to "1" and rises. The CPU module 200 captures the first digital data (corresponding to "Data 1" shown in the figure), sets "0" to the data determination flag and the data acquisition completion flag, and lowers them, thereby determining that the first digital data has been normally captured.

[0058] Also, the data confirmation flag of the analog module 100 has risen to "1". If the CPU module 200 fails to capture the target digital data (corresponding to "Data 2" shown in the figure) for some reason before the data confirmation flag falls, the data non-captured flag is raised to "1", and the state of the data non-captured flag is maintained until the capture of the next digital data is completed.

[0059] By managing the acquisition status of digital data in this way, it is possible to easily determine whether the data is measured at regular intervals. Even when the CPU module 200 acquires the same data multiple times due to its high speed, it is possible to select and acquire the data without duplication. This is effective in the scenario of FFT (Fast Fourier Transform) analysis that requires time-series data.

[0060] The programmable controller 1 according to this embodiment includes a CPU module 200 that acquires data, and an analog module 100 that delivers data from an external device to the CPU module 200. The analog module 100 has a confirmation information setting unit 100a that sets the data confirmation flag indicating that the preparation of the data to be output to the CPU module 200 is confirmed to "1", and a synchronization unit 110b that delivers the data to the CPU module 200 when the data confirmation flag is set to "1". When the data confirmation flag is set to "1", the CPU module 200 executes data synchronization, and when the data synchronization is completed, it has a data reception unit 200a that sets the data capture completion flag indicating that the data delivery is completed to "1". When the data capture completion flag is set to "1", the analog module 100 causes the confirmation information setting unit 100a to discard the confirmation information and sets the data confirmation flag to "0".

[0061] In this way, it is possible to prevent data omission or duplicate acquisition between the analog module 100 and the CPU module 200.

[0062] In this embodiment, the processing speed of the CPU module 200 is different from the processing speed of the analog module 100. By doing so, it is possible to prevent data loss or duplicate acquisition between the analog module 100 and the CPU module 200 with different processing speeds.

[0063] In this embodiment, the processing speed of the CPU module 200 is higher than the processing speed of the analog module 100. By doing so, even if the CPU module 200 has a higher processing speed than the analog module 100, it is possible to prevent data loss or duplicate acquisition between the analog module 100 and the CPU module 200.

[0064] In this embodiment, the analog module 100 includes an AD converter 5 that converts data into A / D (Analog to Digital) conversion for each time series. When the data conversion is completed by the AD converter 5, the determination information setting unit 100a sets the data determination flag to "1". By doing so, it is possible to prevent data loss or duplicate acquisition even between the analog module 100, which takes more processing time, and the CPU module 200.

[0065] In this embodiment, when the determination information setting unit 100a sets the data determination flag to "0" and discards the data determination flag, if data of different time series is being converted by the AD converter 5, the data determination flag is set to "1" again.

[0066] The programmable controller 1 according to this embodiment includes a buffer 3 that can temporarily store data output to the CPU module 200. By doing so, it is possible to reliably transfer data between the CPU module 200 and the analog module 100 while temporarily storing the data in the buffer 3.

[0067] In this embodiment, when the data reception unit 200a fails to acquire data, it transmits a data non-import flag set to "1" to the analog module 100. By doing so, the analog module 100 can surely grasp that it has failed to acquire data.

[0068] In this embodiment, the analog module 100 that has acquired the data non-import flag set to "1" holds the data until the data import completion flag is set to "1". By doing so, the analog module 100 can surely grasp whether the CPU module 200 has received the data.

[0069] In this embodiment, when the analog module 100 that has already acquired the data non-import flag set to "1" acquires the data import completion flag set to "1" from the CPU module 200, it sets the data non-import flag to "0" and discards the data non-import flag. By doing so, the analog module 100 can surely grasp that the CPU module 200 has been able to acquire the data, so it is possible to prevent data omission or duplicate acquisition between the analog module 100 and the CPU module 200.

[0070] (2) Second Embodiment In the second embodiment, since the configuration and operation are almost the same as those in the first embodiment, the description of the same configuration and operation will be omitted.

[0071] In the second embodiment, different from the first embodiment, a buffer 3 is not provided, and the above-described data area 3b and flag area 3a are provided in at least one of the registers and caches built in the MPU2 of the analog module 100. Hereinafter, parts different from the first embodiment will be described with reference to FIGS. 1 to 4.

[0072] In the second embodiment, the MPU2 of the analog module and the MPU4 of the CPU module directly exchange data and each flag (and instruction) via the register and cache. Note that the MPU2 and MPU4 may each be provided with an external memory or the like to store data. In the second embodiment, it is almost the same as the first embodiment except that the buffer 3 does not exist.

[0073] By adopting such a configuration in which data and each flag (and instruction) are exchanged without passing through the buffer 3, internal processing without passing through the buffer can be performed. Therefore, the system configuration is simplified, and it becomes easier to identify the cause and manage it when a problem occurs.

[0074] Note that the present invention is not limited to the above-described embodiments, and includes various modifications and equivalent configurations within the scope of the appended claims. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and the present invention is not necessarily limited to those having all the configurations described. Also, each element described in parallel in this embodiment may be in a mode in which at least one of the elements is connected in series to another element.

Industrial Applicability

[0075] The present invention can be applied to a programmable controller related to a technique for transferring data between a plurality of modules.

Explanation of Signs

[0076] 100... Analog module, 200... CPU module, 3... AD converter, 5... Buffer, 6... Memory, 7... Program creation device

Claims

1. A data acquisition module for acquiring data, A data providing module for delivering data from an external device to the data acquisition module, A programmable controller comprising: The data providing module, A confirmation information setting unit for setting confirmation information indicating that the preparation of the data to be output to the data acquisition module has been completed; A synchronization unit for delivering the data to the data acquisition module when the confirmation information is set, and having: The data acquisition module, When the confirmation information is set, a data reception unit for executing synchronization of the data and setting acquisition completion information indicating that the delivery of the data has been completed when the synchronization of the data is completed, and having: The data providing module, when the acquisition completion information is set, the confirmation information setting unit discards the confirmation information. A programmable controller characterized by this.

2. The processing speed of the data acquisition module is different from the processing speed of the data providing module. The programmable controller according to claim 1, characterized by this.

3. The processing speed of the data acquisition module is higher than the processing speed of the data providing module. The programmable controller according to claim 2, characterized by this.

4. The data providing module, Includes a conversion unit for performing A / D (Analog to Digital) conversion on the data for each time series, The confirmation information setting unit, When the conversion of the data is completed by the conversion unit, sets the confirmation information. The programmable controller according to claim 1, characterized by this.

5. The confirmation information setting unit, When the confirmation information is discarded, if data of different time series is being converted by the conversion unit, sets the confirmation information again. The programmable controller according to claim 4, characterized by this.

6. The data providing module, Is provided with a buffer capable of temporarily storing the data to be output to the data acquisition module. The programmable controller according to claim 1, characterized by this.

7. When the data reception unit cannot acquire the data, it transmits acquisition incomplete information to the data providing module. The programmable controller according to claim 1, characterized by this.

8. The data providing module that has acquired the incomplete acquisition information holds the data until the complete acquisition information is set. The programmable controller according to claim 7, characterized in that.

9. When the data providing module that has acquired the incomplete acquisition information acquires the complete acquisition information from the data acquisition module, the data providing module discards the incomplete acquisition information. The programmable controller according to claim 8, characterized in that.

10. A data transfer method for a programmable controller in which a data providing module transfers data from an external device to a data acquisition module, a confirmation information setting step in which the data providing module sets confirmation information when preparation of data to be output to the data acquisition module is completed; a synchronization step in which the data providing module transfers the data to the data acquisition module when the confirmation information is set; a data reception step in which when the confirmation information is set, the data acquisition module executes synchronization of the data and sets acquisition completion information indicating that the transfer of the data is completed when the synchronization of the data is completed, and in the confirmation information setting step, the data providing module discards the confirmation information when the complete acquisition information is set. A data transfer method, characterized in that.

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