Semiconductor device

Abstract

To provide a semiconductor device capable of preventing yield deterioration caused by electrostatic breakdown.SOLUTION: A semiconductor device comprises a scan line drive circuit which supplies a signal for selecting a plurality of pixels to a scan line and has a shift register for creating the above-described signal. In the shift register, one conductive film functioning as gate electrodes of a plurality of transistors is divided into a plurality of conductive films, and the conductive films are electrically connected by a conductive film formed in a layer different from a layer of the divided conductive films. The plurality of transistors include a transistor on an output side of the shift transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device using an insulated gate field effect transistor. [Background technology]

[0002] In recent years, the high mobility provided by polycrystalline silicon and microcrystalline silicon and the high mobility provided by amorphous silicon have been Oxide semiconductors are a new semiconductor material that combines uniform device characteristics with Metal oxides that exhibit semiconducting properties, known as semiconductors, are attracting attention. For example, indium oxide, a well-known metal oxide, is used in liquid crystal displays. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors using metal oxides that exhibit excellent semiconductor properties in the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0004] By the way, a semiconductor display including a transistor having amorphous silicon or an oxide semiconductor The equipment is capable of handling glass substrates of 5th generation or higher (1200mm wide x 1300mm long). It has the advantages of high productivity and low cost. As the panel size increases, the semiconductor In the pixel portion of the display device, a wiring called a bus line connected to a plurality of pixels, for example, a running The load of inspection lines and signal lines increases. Therefore, a large current supply capacity is required for the drive circuit that supplies potential to the scanning lines and signal lines. Thus, the transistors constituting the drive circuit, especially the transistors located on the output side, tend to increase in size as the panel size increases, although it also depends on their electrical characteristics.

[0005] When the size of the above transistors increases, the area of the wiring that functions as the gate electrode of the transistors in the drive circuit increases due to layout reasons. Therefore, in a manufacturing process using plasma such as dry etching a phenomenon called the so-called antenna effect, in which charges are accumulated in the wiring, easily occurs, and the probability of electrostatic breakdown of the wiring due to the discharge of the charges accumulated in the wiring increases.

[0006] In particular, transistors having amorphous silicon or an oxide semiconductor tend to have a smaller on-current compared to transistors using polycrystalline silicon or single-crystalline silicon. When using transistors having amorphous silicon or an oxide semiconductor, the panel size can be increased in terms of process, but it is necessary to design transistors of an even larger size to satisfy the current supply capacity of the drive circuit. Therefore, the probability of electrostatic breakdown of the wiring due to the increase in the area of the wiring increases, and as a result, the yield is likely to decrease.

[0007] Based on the technical background as described above, one of the problems of the present invention is to provide a semiconductor device that can prevent a decrease in yield due to electrostatic breakdown. ​​​

Means for Solving the Problem

[0008] In one aspect of the present invention, in order to prevent the accumulation of charges on the conductive film due to the antenna effect, a single conductive film that functions as the gate electrode of a plurality of transistors is divided into a plurality. The divided conductive films are separated. And the divided conductive films are electrically connected by a conductive film different from the divided conductive films. The plurality of transistors shall include the transistors on the output side of the drive circuit. Or, in one aspect of the present invention, a scan line drive circuit that supplies a signal for selecting a plurality of pixels to a scan line has a shift register that generates the signal. In the shift register, a single conductive film that functions as the gate electrode of a plurality of transistors is divided into a plurality. The divided conductive films are separated. And the divided conductive films are electrically connected by a conductive film different from the divided conductive films. The plurality of transistors shall include the transistors on the output side of the shift register. The conductive film different from the divided conductive films may be provided in a layer different from the divided conductive films. And the conductive film formed in the different layer may be formed in the same layer as the source electrodes and drain electrodes of the plurality of transistors. In one aspect of the present invention, the plurality of transistors may have amorphous silicon or an oxide semiconductor in the active layer.

[0009] In one aspect of the present invention, a plurality of conductive films that function as gate electrodes are formed in different layers. In one aspect of the present invention, a plurality of conductive films that function as gate electrodes are formed in different layers. In one aspect of the present invention, a plurality of conductive films that function as gate electrodes are formed in different layers. In one aspect of the present invention, a plurality of conductive films that function as gate electrodes are formed in different layers. In one aspect of the present invention, a plurality of conductive films that function as gate electrodes are formed in different layers. In one aspect of the present invention, a plurality of conductive films that function as gate electrodes are formed in different layers.

[0010] The conductive film different from the divided conductive films may be provided in a layer different from the divided conductive films. And the conductive film formed in the different layer may be formed in the same layer as the source electrodes and drain electrodes of the plurality of transistors. The conductive film different from the divided conductive films may be provided in a layer different from the divided conductive films. And the conductive film formed in the different layer may be formed in the same layer as the source electrodes and drain electrodes of the plurality of transistors. The conductive film different from the divided conductive films may be provided in a layer different from the divided conductive films. And the conductive film formed in the different layer may be formed in the same layer as the source electrodes and drain electrodes of the plurality of transistors.

[0011] In one aspect of the present invention, the plurality of transistors may have amorphous silicon or an oxide semiconductor in the active layer. In one aspect of the present invention, the plurality of transistors may have amorphous silicon or an oxide semiconductor in the active layer.

[0012] In one aspect of the present invention, a plurality of conductive films that function as gate electrodes are formed in different layers. By electrically connecting with the formed conductive film, one conductive film functions as a plurality of gate electrodes The area of each conductive film functioning as a gate electrode can be suppressed to be smaller than the case of using a single conductive film as a plurality of gate electrodes Therefore, even if the size of the transistor located on the output side of the driving circuit increases due to the increase in the size of the panel The area of the conductive film functioning as the gate electrode of the transistor can be suppressed to be small, thereby preventing the conductive film from being electrostatically broken down by the antenna effect in the manufacturing process using plasma, such as the process of forming the gate electrode by etching

[0013] Specifically, a semiconductor device according to an aspect of the present invention includes a driving circuit that supplies signals to a plurality of pixels The driving circuit includes a plurality of transistors. Among the plurality of transistors, at least one transistor on the output side of the signal and at least one transistor other than the transistor on the output side have their gate electrodes electrically connected by a conductive film different from the gate electrode

Effect of the Invention

[0014] In the semiconductor device according to an aspect of the present invention, the above configuration can prevent the reduction in yield due to electrostatic breakdown

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Embodiments for Carrying Out the Invention

[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0017] Note that the present invention includes any semiconductor device using transistors, such as integrated circuits, RF tags, and semiconductor display devices. Among integrated circuits, there are microprocessors, image processing circuits, DSP (Digital Signal Processor), microcontrollers including LSI (Large Scale Integrated Circuit t) containing a microcontroller, FPGA (Field Programmable Gate Array), and C PLD (Complex PLD) and other programmable logic circuits (PLD: Progr ammable Logic Device). The (flammable logic device) is included in its scope. Also, the semiconductor display devices include liquid crystal display devices, light-emitting devices having light-emitting elements typified by organic light-emitting elements (OLEDs) in each pixel , electronic paper, DMD (Digital Micromirror D evice), PDP (Plasma Display Panel), FED (Fie ld Emission Display), etc. Semiconductor display devices having circuit elements using semiconductor films in the drive circuit are included in its scope.

[0018] In this specification, the semiconductor display device means a panel in which display elements such as liquid crystal elements and light-emitting elements are formed in each pixel and a module in a state where an IC including a controller is mounted on the panel are included in its scope.

[0019] (Embodiment 1) FIG. 1 shows an example of the circuit configuration of a semiconductor device according to one aspect of the present invention. The semiconductor device 100 shown in FIG. 1 has a plurality of transistors including at least transistor 101 and transistor 102.

[0020] A high-level potential VH or a low-level potential VL is applied to the semiconductor device 100 via wiring 105 and wiring 106. In FIG. 1, the potential VH is applied to the semiconductor device 100 via wiring 105, and the potential VL is applied to the semiconductor device 100 via wiring 106 are exemplified. Also, an input signal potential Vin is applied to the semiconductor device 100 via wiring 103. In the semiconductor device 100, a plurality of transistors including transistor 101 and transistor 102 perform switching according to the potential Vin. And Then, either the potential VH or the potential VL is selected by the above switching, and the selected potential is output from the semiconductor device 100 via the wiring 104 as the potential Vout of the output signal.

[0021] One of the source terminal or the drain terminal of the transistor 102 is connected to the wiring 104. That is, the transistor 102 is located on the output side of the semiconductor device 100 and has a function of controlling the output of the potential Vout to the wiring 104. And in one aspect of the present invention, the gate electrode of the transistor 101 (indicated by G) and the gate electrode of the transistor 102 ( indicated by G) are electrically connected by a wiring 107 different from the above gate electrode.

[0022] In addition, in this specification, connection means both electrical connection and direct connection unless otherwise specified, and it corresponds to a state where current, voltage or potential can be supplied or transmitted. Therefore, the connected state does not necessarily mean the directly connected state, and a state where current, voltage or potential is indirectly connected via elements such as wiring, conductive film, resistor, diode, transistor, etc. so that they can be supplied or transmitted is also included in that category.

[0023] In addition, the source terminal of the transistor means a source region that is a part of the active layer or a source electrode connected to the active layer. Similarly, the drain terminal of the transistor means a drain region that is a part of the active layer or a drain electrode connected to the active layer.

[0024] The source terminal and the drain terminal of the transistor are related to the polarity of the transistor and the application to each electrode. ​​​​​​​​Depending on the level of the potential obtained, the naming convention is reversed. Generally, in an n-channel type transistor dist, the electrode to which a low potential is applied is called the source terminal, and the electrode to which a high potential is applied is called the drain terminal. Also, in a p-channel type transistor, the electrode to which a low potential is applied is called the drain terminal, and the electrode to which a high potential is applied is called the source terminal. In this specification, for convenience, assuming that the source terminal and the drain terminal are fixed, the connection relationship of the transistor may be described, but in reality, the naming of the source terminal and the drain terminal is reversed according to the above potential relationship.

[0025] Note that when supplying the potential Vout output from the semiconductor device 100 to a wiring with a large load, such as a bus line connected to a plurality of pixels, for example, a scanning line or a signal line, the transistor 102 that controls the output of the potential Vout is required to have a large current supply capacity. Therefore, it is desirable to design the channel width W of the transistor 102 to be larger than the channel width W of the transistor 101.

[0026] In Fig. 2(A), a top view of the transistors 101 and 102 shown in Fig. 1 is shown as an example. However, in Fig. 2(A), a top view with the gate insulating film 111 omitted is shown in order to clarify the layout of the transistors 101 and 102. Also, an example of a cross-sectional view of the transistor 102 shown in Fig. 2(A) along the dashed-dotted line A1 - A2 is shown in Fig. 2(B). In Fig. 2(A), the transistor 101 has a conductive film 110 that functions as a gate electrode and a conductive

[0027] film 110 that functions as a gate electrode and a conductive The gate insulating film 111 on the electrofilm 110, and the semiconductor film 112 provided at a position overlapping the conductive film 110 on the gate insulating film 111, and the conductive films 113 and 114 that function as source electrodes or drain electrodes on the semiconductor film 112. And it has a semiconductor film 116 provided at a position overlapping the conductive film 115 on the gate insulating film 111 on the conductive film 115, and the gate insulating film 111 on the conductive film 115. And the conductive films 117 and 118 that function as source electrodes or drain electrodes on the semiconductor film 116.

[0028] Also, in FIGS. 2(A) and 2(B), the transistor 102 includes a conductive film 115 that functions as a gate electrode, a gate insulating film 111 on the conductive film 115, and a semiconductor film 116 provided at a position overlapping the conductive film 115 on the gate insulating film 111. And the conductive films 117 and 118 that function as source electrodes or drain electrodes on the semiconductor film 116. And it has a semiconductor film 116 provided at a position overlapping the conductive film 115 on the gate insulating film 111 on the conductive film 115, and the gate insulating film 111 on the conductive film 115. And the conductive films 117 and 118 that function as source electrodes or drain electrodes on the semiconductor film 116. It has.

[0029] And in one aspect of the present invention, the transistor 102 located on the output side has a higher current supply ability than the transistor 101. Therefore, in one aspect of the present invention, as shown in FIG. 2(A), the ratio of the channel width W to the channel length L of the transistor 102 is designed to be larger than the ratio of the channel width W to the channel length L of the transistor 101. Specifically, it is desirable that the ratio of the channel width W to the channel length L is 2 times or more, more preferably 3 times or more, than the ratio of the channel width W to the channel length L of the transistor 101. 102 of the channel width W with respect to the channel length L 102 is larger than the ratio of the channel width W to the channel length L of the transistor 101. of the channel width W with respect to the channel length L 101 is larger than the ratio of the channel width W to the channel length L of the transistor 101. 101 It is desirable to design it to a larger value. Specifically, the ratio of the channel width W to the channel length L 102 is 2 times or more, more preferably 3 times or more, than the ratio of the channel width W to the channel length L of the transistor 101. 10 2 of the channel width W with respect to the channel length L 101 is 2 times or more, more preferably 3 times or more, than the ratio of the channel width W to the channel length L of the transistor 101. 101 It is desirable that it is 3 times or more. It is preferably 3 times or more.

[0030] Also, the conductive film 110 and the conductive film 115 are separated. Here, separation in this specification means being physically separated. And in FIGS. 2(A) and 2(B), it is shown that The conductive film 110 and the conductive film 115 are electrically connected via the conductive film 119 that functions as a wiring. Specifically, the conductive film 110 and the conductive film 115 are

[0031] connected to the conductive film 119 through the openings 120 and 121 formed in the gate insulating film 111. Also, the conductive film 110 and the conductive film 115 shown in FIG. 2(A) and FIG. 2(B) can be formed by processing a single conductive film formed on the insulating surface into a desired shape by etching or the like. And the conductive film 113 and the conductive film 114, the conductive film 117 and the conductive film

[0032] 118, and the conductive film 119 can be formed by processing a single conductive film formed on the gate insulating film 111 so as to cover the openings 120 and 121 into a desired shape by etching or

[0033] the like. That is, the conductive film 119 is formed in a layer different from the conductive film 110 and the conductive film 115. As shown in FIG. 2(A) and FIG. 2(B), in one aspect of the present invention, the conductive film 110 and the conductive film 115 that

[0034] function as gate electrodes are electrically connected by a A gate insulating film on the electrofilm 122, and a semiconductor film 123 provided at a position overlapping the conductive film 122 on the gate insulating film and conductive films 124 and 125 that function as source electrodes or drain electrodes on the semiconductor film 123. It has

[0035] Also, in FIG. 2(C), the transistor 102 includes a conductive film 122 that functions as a gate electrode, a gate insulating film on the conductive film 122, and a semiconductor film 126 provided at a position overlapping the conductive film 122 on the gate insulating film, and conductive films 127 and 128 that function as source electrodes or drain electrodes on the semiconductor film 126. It has

[0036] That is, in FIG. 2(C), the transistor 101 and the transistor 102 share the conductive film 12 2, and the conductive film 122 functions as the gate electrode of the transistor 101 and the gate electrode of the transistor 1 02. Therefore, in the case of FIG. 2(C), the area of the conductive film 122 that functions as the gate electrode is larger than the areas of the conductive films 110 and 115 that function as the gate electrodes in FIGS. 2(A) and 2(B). Therefore, in one aspect of the present invention, the areas of the conductive films 110 and 115 that function as the gate electrode can be kept smaller than the area of the conductive film 122 of the comparative example. Thus, when the conductive films 110 and 115 are fabricated by etching, the amount of charge accumulated in each of the conductive films 110 and 115 can be kept small, that is, the antenna effect can be reduced.

[0037] Therefore, in one aspect of the present invention, when the conductive films 110 and 115 are fabricated by etching, compared with the comparative example, the amount of charge discharged from the conductive films 110 and 11 can be reduced, that is, the antenna effect can be reduced. Therefore, in one aspect of the present invention, when the conductive films 110 and 115 are fabricated by etching, compared with the comparative example, the amount of charge discharged from the conductive films 110 and 11 due to the discharge of the above charge can be reduced. It is possible to make it difficult to cause electrostatic breakdown of 5.

[0038] Also, in one aspect of the present invention, when the semiconductor films 112 and 116 on the conductive films 110 and 115 are formed by etching, it is also possible to make it difficult to cause electrostatic breakdown of the conductive films 110 and 115 due to the antenna effect. When manufacturing the semiconductor films 112 and 116 on the conductive films 110 and 115 by etching, it is also possible to make it difficult to cause electrostatic breakdown of the conductive films 110 and 115 due to the antenna effect. It is possible to make it difficult to cause electrostatic breakdown of 5.

[0039] Next, FIG. 3(A) shows an example different from FIG. 2(A) of the top view of the transistors 101 and 102 shown in FIG. 1. However, in FIG. 3(A), a top view with the gate insulating film 211 omitted is shown in order to clarify the layout of the transistors 101 and 102. Also, an example of a cross-sectional view of the transistor 102 shown in FIG. 3(A) along the dashed-dotted line B1 - B2 is shown in FIG. 3(B). In FIG. 3(A), an example different from FIG. 2(A) of the top view of the transistors 101 and 102 shown in FIG. 1 is shown. However, in FIG. 3(A), a top view with the gate insulating film 211 omitted is shown in order to clarify the layout of the transistors 101 and 102. Also, an example of a cross-sectional view of the transistor 102 shown in FIG. 3(A) along the dashed-dotted line B1 - B2 is shown in FIG. 3(B). In FIG. 3(A), in order to clarify the layout of the transistors 101 and 102, a top view with the gate insulating film 211 omitted is shown. Also, an example of a cross-sectional view of the transistor 102 shown in FIG. 3(A) along the dashed-dotted line B1 - B2 is shown in FIG. 3(B). In FIG. 3(A), an example of a cross-sectional view of the transistor 102 shown in FIG. 3(A) along the dashed-dotted line B1 - B2 is shown in FIG. 3(B). In FIG. 3(A), the transistor 101 has a conductive film 213 and a conductive film 214 that function as a source electrode or a drain electrode, a semiconductor film 212 on the conductive films 213 and 214, a gate insulating film 211 on the semiconductor film 212, and a conductive film 210 that functions as a gate electrode provided at a position overlapping the semiconductor film 212 on the gate insulating film 211.

[0040] In FIG. 3(A), the transistor 101 has a conductive film 213 and a conductive film 214 that function as a source electrode or a drain electrode, a semiconductor film 212 on the conductive films 213 and 214, a gate insulating film 211 on the semiconductor film 212, and a conductive film 210 that functions as a gate electrode provided at a position overlapping the semiconductor film 212 on the gate insulating film 211. In FIG. 3(A), the transistor 101 has a conductive film 213 and a conductive film 214 that function as a source electrode or a drain electrode, a semiconductor film 212 on the conductive films 213 and 214, a gate insulating film 211 on the semiconductor film 212, and a conductive film 210 that functions as a gate electrode provided at a position overlapping the semiconductor film 212 on the gate insulating film 211. In FIG. 3(A), the transistor 101 has a conductive film 213 and a conductive film 214 that function as a source electrode or a drain electrode, a semiconductor film 212 on the conductive films 213 and 214, a gate insulating film 211 on the semiconductor film 212, and a conductive film 210 that functions as a gate electrode provided at a position overlapping the semiconductor film 212 on the gate insulating film 211. In FIG. 3(A), the transistor 101 has a conductive film 213 and a conductive film 214 that function as a source electrode or a drain electrode, a semiconductor film 212 on the conductive films 213 and 214, a gate insulating film 211 on the semiconductor film 212, and a conductive film 210 that functions as a gate electrode provided at a position overlapping the semiconductor film 212 on the gate insulating film 211.

[0041] Also, in FIGS. 3(A) and 3(B), the transistor 102 has a conductive film 217 and a conductive film 218 that function as a source electrode or a drain electrode, a semiconductor film 216 on the conductive films 217 and 218, a gate insulating film 211 on the semiconductor film 216, and a conductive film 215 that functions as a gate electrode provided at a position overlapping the semiconductor film 216 on the gate insulating film 211. In FIGS. 3(A) and 3(B), the transistor 102 has a conductive film 217 and a conductive film 218 that function as a source electrode or a drain electrode, a semiconductor film 216 on the conductive films 217 and 218, a gate insulating film 211 on the semiconductor film 216, and a conductive film 215 that functions as a gate electrode provided at a position overlapping the semiconductor film 216 on the gate insulating film 211. In FIGS. 3(A) and 3(B), the transistor 102 has a conductive film 217 and a conductive film 218 that function as a source electrode or a drain electrode, a semiconductor film 216 on the conductive films 217 and 218, a gate insulating film 211 on the semiconductor film 216, and a conductive film 215 that functions as a gate electrode provided at a position overlapping the semiconductor film 216 on the gate insulating film 211. In FIGS. 3(A) and 3(B), the transistor 102 has a conductive film 217 and a conductive film 218 that function as a source electrode or a drain electrode, a semiconductor film 216 on the conductive films 217 and 218, a gate insulating film 211 on the semiconductor film 216, and a conductive film 215 that functions as a gate electrode provided at a position overlapping the semiconductor film 216 on the gate insulating film 211. In FIGS. 3(A) and 3(B), the transistor 102 has a conductive film 217 and a conductive film 218 that function as a source electrode or a drain electrode, a semiconductor film 216 on the conductive films 217 and 218, a gate insulating film 211 on the semiconductor film 216, and a conductive film 215 that functions as a gate electrode provided at a position overlapping the semiconductor film 216 on the gate insulating film 211.

[0042] And, in one aspect of the present invention, the transistor 102 located on the output side has a higher current supply capacity than the transistor 101. Therefore, in one aspect of the present invention, as shown in FIG. 3(A), the ratio of the channel width W 102 to the channel length L 102 of the transistor 102 is designed to be a value greater than the ratio of the channel width W 101 to the channel length L 101 of the transistor 101. Specifically, the ratio of the channel width W to the channel length L 102 is desirably 2 times or more, more preferably 10 2 3 times or more the ratio of the channel width W 101 to the channel length L 101 .

[0043] Also, the conductive film 210 and the conductive film 215 are separated. And, in FIGS. 3(A) and 3( B), the conductive film 210 and the conductive film 215 are electrically connected via the conductive film 219 that functions as a wiring. Specifically, the conductive film 210 and the conductive film 215 are connected to the conductive film 219 via the openings 220 and 221 formed in the gate insulating film 211.

[0044] Also, the conductive film 210 and the conductive film 215 shown in FIGS. 3(A) and 3(B) can be formed by processing a single conductive film formed on the gate insulating film 211 so as to cover the openings 220 and 221 into a desired shape by etching or the like. And, the conductive film 21 3 and the conductive film 214, the conductive film 217 and the conductive film 218, and the conductive film 219 can be formed by processing a single conductive film formed on the insulating surface into a desired shape by etching or the like. It is possible. That is, the conductive film 219 is different from the conductive film 210 and the conductive film 215. It is formed in a different layer.

[0045] As shown in FIGS. 3(A) and 3(B), in one aspect of the present invention, the conductive films 210 and 215 that function as gate electrodes are formed in a layer different from the conductive films 210 and 215. They are electrically connected by a conductive film 219 formed in a layer different from the conductive films 210 and 215.

[0046] As a comparative example, FIG. 3(C) shows another example of the top view of the transistors 101 and 102 shown in FIG. 1. However, in FIG. 3(C), a top view with the gate insulating film omitted is shown to clarify the layout of the transistors 101 and 102.

[0047] In FIG. 3(C), the transistor 101 includes conductive films 224 and 225 that function as a source electrode or a drain electrode, a semiconductor film 223 on the conductive films 224 and 225, a gate insulating film on the semiconductor film 223, and a conductive film 222 that functions as a gate electrode provided at a position overlapping the semiconductor film 223 on the gate insulating film.

[0048] Also, in FIG. 3(C), the transistor 102 includes conductive films 227 and 228 that function as a source electrode or a drain electrode, a semiconductor film 226 on the conductive films 227 and 228, a gate insulating film on the semiconductor film 226, and a conductive film 222 that functions as a gate electrode provided at a position overlapping the semiconductor film 226 on the gate insulating film.

[0049] That is, in FIG. 3(C), the transistors 101 and 102 are connected by the conductive film 22 sharing 2, and the conductive film 222 functions as the gate electrode of the transistor 101 and the gate electrode of the transistor 1 02. Therefore, in the case of FIG. 3(C), the area of the conductive film 222 functioning as the gate electrode is larger than the respective areas of the conductive films 210 and 215 functioning as the gate electrodes in FIGS. 3(A) and 3(B). Therefore, in one aspect of the present invention, the areas of the conductive films 210 and 215 functioning as the gate electrodes can be kept smaller than the area of the conductive film 222 in the comparative example. Thus, when the conductive films 210 and 215 are fabricated by etching, the amount of charge accumulated in each of the conductive films 210 and 215 can be kept small, that is, the antenna effect can be reduced. Therefore, in one aspect of the present invention, when the conductive films 210 and 215 are fabricated by etching, electrostatic breakdown of the conductive films 210 and 215 due to the discharge of the above charges can be made less likely to occur compared with the comparative example.

[0050] Also, in one aspect of the present invention, when various conductive films on the conductive films 210 and 215 are processed into a desired shape by etching, electrostatic breakdown of the conductive films 210 and 215 due to the antenna effect can be made less likely to occur. Next, the configuration of a pulse generation circuit, which is one of the semiconductor devices according to one aspect of the present invention, will be described. FIG. 4 shows an example of a pulse generation circuit included in the semiconductor device according to one aspect of the present invention. The pulse generation circuit 300 shown in FIG. 4 includes transistors 301 to 3015 and capacitors and so on. When fabricating the conductive films 210 and 215 by etching, compared with the comparative example, electrostatic breakdown of the conductive films 210 and 215 due to the discharge of the above charges can be made less likely to occur.

[0051] Also, in one aspect of the present invention, when various conductive films on the conductive films 210 and 215 are processed into a desired shape by etching, electrostatic breakdown of the conductive films 210 and 215 due to the antenna effect can be made less likely to occur. When fabricating the conductive films 210 and 215 by etching, compared with the comparative example, electrostatic breakdown of the conductive films 210 and 215 due to the discharge of the above charges can be made less likely to occur.

[0052] Next, the configuration of a pulse generation circuit, which is one of the semiconductor devices according to one aspect of the present invention, will be described. FIG. 4 shows an example of a pulse generation circuit included in the semiconductor device according to one aspect of the present invention. FIG. 4 shows an example of a pulse generation circuit included in the semiconductor device according to one aspect of the present invention. shown.

[0053] The pulse generation circuit 300 shown in FIG. 4 includes transistors 301 to 3015 and capacitors ​​It has the quantum element 316. The transistor 302 corresponds to the transistor 101 shown in FIG. 1. The transistor 309, the transistor 312, or the transistor 315 corresponds to the transistor 102 shown in FIG. 1. Further, the pulse generation circuit 300 has a configuration in which various potentials are applied from the wiring 317 to the wiring 326 and a potential is output to the wiring 327 to the wiring 329. Corresponding. The transistor 309, the transistor 312, or the transistor 315 corresponds to the transistor 102 shown in FIG. 1. Also, the pulse generation circuit 300 has a configuration in which various potentials are applied from the wiring 31 7 to the wiring 326 and a potential is output to the wiring 327 to the wiring 329. It has a configuration.

[0054] By connecting a plurality of stages of the pulse generation circuit 300, a shift register can be configured. It is possible.

[0055] Specifically, when the transistors 301 to 315 are n-channel type, a high-level potential VDD is applied to the wiring 317, a low-level potential VSS is applied to the wiring 318, and a low-level potential VEE is applied to the wiring 326. The potential VEE is desirably the same potential as the potential VSS or a higher potential than that. Also, a potential LIN is applied to the wiring 319, a potential INRES is applied to the wiring 320, a potential CLK2 is applied to the wiring 321, a potential RIN is applied to the wiring 322, a potential C LK1 is applied to the wiring 323, a potential PWC2 is applied to the wiring 324, and a potential PWC 1 is applied to the wiring 325. VSS and a higher potential than that. Also, a potential LIN is applied to the wiring 319, a potential INRES is applied to the wiring 320, a potential CLK2 is applied to the wiring 321, a potential RIN is applied to the wiring 322, a potential C LK1 is applied to the wiring 323, a potential PWC2 is applied to the wiring 324, and a potential PWC 1 is applied to the wiring 325. LK1 is applied to the wiring 323, a potential PWC2 is applied to the wiring 324, and a potential PWC 1 is applied to the wiring 325.

[0056] Also, the potential GOUT1 output from the pulse generation circuit 300 is applied to the wiring 327. The potential GOUT2 output from the pulse generation circuit 300 is applied to the wiring 328. The potential SROUT output from the pulse generation circuit 300 is applied to the wiring 329. It is applied to the wiring 327. The potential GOUT2 output from the pulse generation circuit 300 is applied to the wiring 328. The potential SROUT output from the pulse generation circuit 300 is applied to the wiring 329. The potential GOUT2 output from the pulse generation circuit 300 is applied to the wiring 328. The potential SROUT output from the pulse generation circuit 300 is applied to the wiring 329.

[0057] The potential LIN, the potential RIN, the potential CLK2, and the potential INRES are the semiconductor shown in FIG. 1. corresponds to the potential Vin in the device 100. The potentials GOUT1, GOUT2, and the potential SROUT correspond to the potential Vout in the semiconductor device 100 shown in FIG. 1. The potential VS S, the potential VEE, the potential PWC1, the potential PWC2, and the potential CLK1 correspond to the potential VH or the potential VL in the semiconductor device 100 shown in FIG. 1.

[0058] Specifically, for the transistor 301, its gate electrode is connected to the wiring 319. Also , for the transistor 301, one of its source terminal and drain terminal is connected to the wiring 317, and the other is connected to one of the source terminal and drain terminal of the transistor 302, respectively . For the transistor 302, its gate electrode is connected to the gate electrode of the transistor 315 . Also, for the transistor 302, the other of its source terminal and drain terminal is connected to the wiring 318. For the transistor 303, its gate electrode is connected to the wiring 320 . Also, for the transistor 303, one of its source terminal and drain terminal is connected to the wiring 317, and the other is connected to the gate electrode of the transistor 302, respectively. For the tran sistor 304, its gate electrode is connected to the wiring 321. Also, for the transistor 3 04, one of its source terminal and drain terminal is connected to the wiring 317, and the other is connected to the gate electrode of the transistor 3 02, respectively. For the transistor 305, its gate electrode is connected to the wiring 322. Also, for the transistor 305, one of its source terminal and drain in terminals is connected to the wiring 317, and the other is connected to the gate electrode of the transistor 302, respectively, and is continued. For the transistor 306, its gate electrode is connected to the wiring 319. Also, for transistor 306, one of its source terminal and drain terminal is connected to the gate electrode of transistor 3 02, and the other is connected to wiring 318, respectively. For transistor 30 7, its gate electrode is connected to wiring 317. Also, for transistor 307, one of its source terminal and drain terminal is connected to the other of the source terminal and drain terminal of transistor 301, and the other is connected to the gate electrode of transistor 308, respectively. For tra nsistor 308, one of its source terminal and drain terminal is connected to wiring 323, and the other is connected to wiring 329, respectively. For transistor 309, its gate electrode is connected to the gate electrode of transistor 30 2. Also, for transistor 309, one of its source terminal and drain terminal is connected to wiring 329, and the other is connected to wiring 318, respectively. For transistor 310, its gate electrode is connected to wiring 317. Also, for tra nsistor 310, one of its source terminal and drain terminal is connected to the other of the source terminal and drain terminal of transistor 301, and the other is connected to the gate electrode of transistor 311, respectively. For transistor 311, one of its source terminal and drain terminal is connected to wiring 324, and the other is connected to wiring 328, respectively. For transistor 312, its gate electrode is connected to the gate electrode of transistor 302. Also, for transistor 3 12, one of its source terminal and drain terminal is connected to wiring 328, and the other is connected to wiring 318, respectively. For transistor 313, its gate electrode is connected to wiring 317. Also, for transistor 313, one of its source terminal and drain terminal is connected to the other of the source terminal and drain terminal of tra nsistor 301, and the other is connected to the gate of transistor 314 electrode, respectively. For transistor 311, one of its source terminal and drain terminal is connected to wiring 324, and the other is connected to wiring 328, respectively. For transistor 312, its gate electrode is connected to the gate electrode of transistor 302. Also, for transistor 312, one of its source terminal and drain terminal is connected to wiring 328, and the other is connected to wiring 318, respectively. For transistor 313, its gate electrode is connected to wiring 317. Also, for transistor 313, one of its source terminal and drain terminal is connected to the other of the source terminal and drain terminal of transistor 301, and the other is connected to the gate electrode of transistor 314, respectively. gate electrode is connected to the gate electrode of transistor 302. Also, for transistor 3 12, one of its source terminal and drain terminal is connected to wiring 328, and the other is connected to wiring 318, respectively. For transistor 313, its gate electrode is connected to wiring 317. Also, for transistor 313, one of its source terminal and drain terminal is connected to the other of the source terminal and drain terminal of tra nsistor 301, and the other is connected to the gate electrode of transistor 314 electrode, respectively. For transistor 313, one of its source terminal and drain terminal is connected to the other of the source terminal and drain terminal of transistor 301, and the other is connected to the gate electrode of transistor 314, respectively. - The electrodes are respectively connected. The transistor 314 has its source terminal and drain One of the input terminals is connected to the wiring 325 and the other is connected to the wiring 327, respectively. The transistor 315 has one of its source terminal and drain terminal connected to the wiring 327 and the other connected to the wiring 326, respectively. The capacitive element 316 has one electrode connected to the gate electrode of the transistor 302 and the other electrode connected to the wiring 318, respectively.

[0059] In FIG. 4, the other of the source terminal and drain terminal of the output-side transistor 315 is connected to the wiring 326, but the present invention is not limited to this configuration. The other of the source terminal and drain terminal of the output-side transistor 315 may be connected to the wiring 318. However, since the output-side transistor 315 is large in size, when the transistor 315 is a normally-on type, the drain current is larger than that of other transistors. Therefore, when the transistor 315 is a normally-on type, when the other of the source terminal and drain terminal of the transistor 315 is connected to the wiring 318, a phenomenon is likely to occur in which the potential of the wiring 318 rises due to the above drain current, and the amplitude of the potential GOUT1, which is the output potential, becomes small. However, as shown in FIG. 4, when the other of the source terminal and drain terminal of the output-side transistor 315 is connected to the wiring 326 instead of the wiring 318, even if the transistor 315 is a normally-on type and thereby the potential of the wiring 326 rises, the potential of the wiring 318 for supplying the potential to the gate electrode of the transistor is independent of the rise in the potential of the wiring 326. Therefore, due to the drain current of the transistor 315, the potential of the wiring 326 When the potential rises, the gate voltage of transistor 315 approaches the threshold voltage having a negative value, so that even if transistor 315 is normally on, it can be turned off.

[0060] In one aspect of the present invention, at least one of transistors 309, 312, and 315 corresponding to the output-side transistor and transistor 302 have their gate electrodes electrically connected via a conductive film different from the above gate electrode. With the above configuration, compared to the case where all the gate electrodes of transistors 309, 312, 315, and 302 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode can be made less likely to occur.

[0061] Note that in one aspect of the present invention, the configuration is not limited to the case where two conductive films functioning as gate electrodes are electrically connected via a single conductive film different from the above two conductive films. For example, the two conductive films functioning as gate electrodes may be electrically connected via a plurality of conductive films different from the above two conductive films. In this case, at least one of the plurality of conductive films is formed in a layer different from the two conductive films functioning as gate electrodes.

[0062] Also, in one aspect of the present invention, the configuration is not limited to the case where an insulating film is provided between a plurality of conductive films functioning as gate electrodes and a conductive film for electrically connecting the plurality of conductive films. In one aspect of the present invention, a plurality of conductive films functioning as gate electrodes and the plurality of conductive films ​​​​​​​​​​​​It is only necessary that the conductive film for electrically connecting the first and second electrodes and the second electrode are formed in different manufacturing steps. Therefore, the plurality of conductive films functioning as gate electrodes and the plurality of conductive films are electrically connected to each other. For this purpose, an insulating film does not necessarily have to be formed between the conductive film and the insulating film.

[0063] (Embodiment 2) In this embodiment, the pulse generating circuit 300 shown in FIG. 4 is connected in multiple stages. The shift register used in this embodiment will now be described.

[0064] The shift register shown in FIG. 5 includes pulse generating circuits 300_1 to 300_y. (y is a natural number) and a dummy pulse generating circuit 300_d. 0_1 to 300_y are the same as the pulse generating circuit 300 shown in FIG. The pulse generating circuit 300_d has the same configuration as that of the wiring 300_d to which the potential RIN is applied. 4 in that it is not connected to 322 and does not have transistor 305. The configuration is different from that of the pulse generating circuit 300 shown in FIG.

[0065] In the shift register shown in FIG. 5, a pulse generating circuit 300_j (j is y or less) The positions of the wiring 319 to the wiring 325 and the wiring 327 to the wiring 329 connected to the 5 and 7, the wiring of the pulse generating circuit 300_j is A potential SR output from a wiring 329 of the preceding stage pulse generating circuit 300_j-1 is input to a terminal 319. OUTj-1 is given as a potential LIN. However, the first-stage pulse generating circuit 300 The wiring 319 of _1 is configured to receive the potential of a start pulse signal GSP.

[0066] Also, the potential SROUTj+1 output from the wiring 329 of the subsequent-stage pulse generation circuit 300_j+1 is provided as the potential RIN to the wiring 322 connected to the pulse generation circuit 300_j. However, for the wiring 322 of the pulse generation circuit 300_y at the y-th stage, SROUTd output from the wiring 329 of the pulse generation circuit 300_d is provided as the potential RIN.

[0067] The potentials of any two of the clock signals GCK1 to GCK4 are respectively provided to the wiring 321 and the wiring 323. Specifically, in the pulse generation circuit 300_4m+1, the potential of the clock signal GCK1 is provided as the potential CLK1 to the wiring 323, and the potential of the clock signal GCK2 is provided as the potential CLK2 to the wiring 321. In the pulse generation circuit 300_4m+2, the potential of the clock signal GCK2 is provided as the potential CLK1 to the wiring 323, and the potential of the clock signal GCK3 is provided as the potential CLK2 to the wiring 321. In the pulse generation circuit 300_4m+3, the potential of the clock signal GCK3 is provided as the potential CLK1 to the wiring 323, and the potential of the clock signal GCK4 is provided as the potential CLK2 to the wiring 321. In the pulse generation circuit 300_4m+4, the potential of the clock signal GCK4 is provided as the potential CLK1 to the wiring 323, and the potential of the clock signal GCK1 is provided as the potential CLK2 to the wiring 321. In the pulse generation circuit 300_d, the potential of the clock signal GCK1 is provided as the potential CLK1 to the wiring 323, and the potential of the clock signal GCK2 is provided as the potential CLK2 to the wiring 321. However, m is an arbitrary integer that satisfies the condition that the total number of the pulse generation circuits 300 is y. ​​​​​​​​​​​​​​​​​

[0068] Also, the pulse width control signals PWCA to PWCD and any two of the pulse width control signals PWCa to PWCd are applied to the wirings 324 and 325, respectively. Specifically, in the pulse generation circuit 300_4m+1, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+2, the potential of the pulse width control signal PWCb is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCB is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+3, the potential of the pulse width control signal PWCc is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCC is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+4, the potential of the pulse width control signal PWCd is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCD is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_d, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. Also, the pulse width control signals PWCA to PWCD and any two of the pulse width control signals PWCa to PWCd are applied to the wirings 324 and 325, respectively. Specifically, in the pulse generation circuit 300_4m+1, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+2, the potential of the pulse width control signal PWCb is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCB is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+3, the potential of the pulse width control signal PWCc is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCC is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+4, the potential of the pulse width control signal PWCd is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCD is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_d, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. Also, the pulse width control signals PWCA to PWCD and any two of the pulse width control signals PWCa to PWCd are applied to the wirings 324 and 325, respectively. Specifically, in the pulse generation circuit 300_4m+1, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+2, the potential of the pulse width control signal PWCb is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCB is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+3, the potential of the pulse width control signal PWCc is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCC is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+4, the potential of the pulse width control signal PWCd is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCD is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_d, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. In 300_4m+1, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. In 300_4m+1, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+2, the potential of the pulse width control signal PWCb is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCB is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+2, the potential of the pulse width control signal PWCb is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCB is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+3, the potential of the pulse width control signal PWCc is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCC is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+3, the potential of the pulse width control signal PWCc is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCC is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+3, the potential of the pulse width control signal PWCc is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCC is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+4, the potential of the pulse width control signal PWCd is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCD is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_4m+4, the potential of the pulse width control signal PWCd is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCD is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_d, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_d, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2. In the pulse generation circuit 300_d, the potential of the pulse width control signal PWCa is applied to the wiring 325 as the potential PWC1, and the potential of the pulse width control signal PWCA is applied to the wiring 324 as the potential PWC2.

[0069] The potential GOUT1 of the wiring 327 connected to the pulse generation circuit 300_j is applied to the scanning line GLaj. The potential GOUT1 of the wiring 327 connected to the pulse generation circuit 300_j is applied to the scanning line GLaj.

[0070] The potential SROUT_j of the wiring 329 connected to the pulse generation circuit 300_j is the inverter Its polarity is inverted by 351_j and applied to the scanning line GLbj. Specifically, the inverter 351_4m + 1 has the clock signal GCK2 input thereto, and when the potential of the clock signal GCK2 is at a low level, it inverts the polarity of the potential SROUT_4m + 1 and applies it to the scanning line GLb4m + 1. The inverter 351_4m + 2 has the clock signal GCK3 input thereto, and when the potential of the clock signal GCK3 is at a low level, it inverts the polarity of the potential SROUT_4m + 2 and applies it to the scanning line GLb4m + 2. The inverter 351_4m + 3 has the clock signal GCK4 input thereto, and when the potential of the clock signal GCK4 is at a low level, it inverts the polarity of the potential SROUT_4m + 3 and applies it to the scanning line GLb4m + 3. The inverter 351_4m + 4 has the clock signal GCK1 input thereto, and when the potential of the clock signal GCK1 is at a low level, it inverts the polarity of the potential SROUT_4m + 4 and applies it to the scanning line GLb4m + 4. The inverter 351_d has the clock signal GCK2 input thereto, and when the potential of the clock signal GCK2 is at a low level, it inverts the polarity of the potential SROUT_d and applies it to the scanning line GLbd. Also, the potential GOUT2 of the wiring 328 connected to the pulse generation circuit 300_j has its polarity inverted by the inverter 350_j and is applied to the scanning line GLcj. Specifically, the inverter 350_4m + 1 has the clock signal GCK2 input thereto, and when the potential of the clock signal GCK2 is at a low level, it inverts the polarity of the potential GOUT2 and applies it to the scanning line GLc4

[0071] m + 1. The inverter 350_4m + 2 has the clock signal GCK3 input thereto, and when the potential of the clock signal GCK3 is at a low level, it inverts the polarity of the potential GOUT2 and applies it to the scanning line GLc4m + 2. The inverter 350_4m + 3 has the clock signal GCK3 input thereto, and when the potential of the clock signal GCK3 is at a low level, it inverts the polarity of the potential GOUT2 and applies it to the scanning line GLc4m + 3. The inverter 350_4m + 4 has the clock signal GCK4 input thereto, and when the potential of the clock signal GCK4 is at a low level, it inverts the polarity of the potential GOUT2 and applies it to the scanning line GLc4m + 4. The inverter 350_d has the clock signal GCK2 input thereto, and when the potential of the clock signal GCK2 is at a low level, it inverts the polarity of the potential GOUT2 and applies it to the scanning line GLcd. The inverter 350_d has the clock signal GCK2 input thereto, and when the potential of the clock signal GCK2 is at a low level, it inverts the polarity of the potential GOUT2 and applies it to the scanning line GLcd.​ and supplies it to the scanning line GLc4m+2. The inverter 350_4m+3 has the clock signal GC K4 input thereto, and when the potential of the clock signal GCK4 is at the low level, it inverts the polarity of the potential GOUT 2 and supplies it to the scanning line GLc4m+3. The inverter 350_4m+4 has the clock signal GCK1 input thereto, and when the potential of the clock signal GCK1 is at the low level it inverts the polarity of the potential GOUT2 and supplies it to the scanning line GLc4m+4. The inverter 350_d has the clock signal GCK2 input thereto, and when the potential of the clock signal GCK2 is at the low level, it inverts the polarity of the potential GOUT2 and supplies it to the scanning line GLcd.

[0072] Next, the operation of the pulse generation circuit 300 shown in FIG. 4 will be described with reference to the timing chart shown in FIG. 6. It is assumed that the potential INRES is at the low level throughout all periods. As shown in FIG. 6, in period t1, the potential CLK1 supplied to the wiring 323 is at the low level , the potential CLK2 supplied to the wiring 321 is at the low level, the potential of the pulse width control signal PWC1 supplied to the wiring 325 is at the low level, the potential of the pulse width control signal PW

[0073] C2 supplied to the wiring 324 is at the low level, the potential LIN supplied to the wiring 319 is at the high level, and the potential RIN supplied to the wiring 322 is at the low level. Therefore, in period t1, in the pulse generation circuit 300, the potential (low level) of the pulse width control signal PWC1 supplied to the wiring 325 is supplied to the wiring 327 as the potential GOUT1 . Also, the potential (low level) of the pulse width control signal PWC2 supplied to the wiring 324 is as follows.

[0074] Thus, in period t1, in the pulse generation circuit 300, the potential (low level) of the pulse width control signal PWC1 supplied to the wiring 325 is supplied to the wiring 327 as the potential GOUT1 and the potential (low level) of the pulse width control signal PWC2 supplied to the wiring 324 is supplied to the wiring 327 as the potential GOUT2. is applied to wiring 328 as potential GOUT2. Also, potential C applied to wiring 323 LK1 (low level) is applied to wiring 329 as potential SROUT.

[0075] Next, as shown in FIG. 6, in period t2, the potential CLK1 applied to wiring 323 is high level, the potential CLK2 applied to wiring 321 is low level, the potential of the pulse width control signal PWC1 applied to wiring 325 changes from low level to high level, the potential of the pulse width control signal PWC2 applied to wiring 324 is low level, the potential LIN applied to wiring 319 is high level, and the potential RIN applied to wiring 322 is low level. Therefore, in period t2, in the pulse generation circuit 300, the potential (changing from low level to high level) of the pulse width control signal PWC1 applied to wiring 325 is used as potential GOUT1

[0076] and applied to wiring 327. Also, the potential (low level) of the pulse width control signal PWC2 applied to wiring 324 is applied to wiring 328 as potential GOUT2. Also, the potential CLK1 (high level) applied to wiring 3 23 is applied to wiring 329 as potential SROUT. 24 is applied to wiring 328 as potential GOUT2. Also, the potential CLK1 (high level) applied to wiring 3 23 is applied to wiring 329 as potential SROUT.

[0077] Next, as shown in FIG. 6, in period t3, the potential CLK1 applied to wiring 323 is high level, the potential CLK2 applied to wiring 321 is low level, the potential of the pulse width control signal PWC1 applied to wiring 325 is high level, the potential of the pulse width control signal PWC2 applied to wiring 324 is high level, the potential LIN applied to wiring 319 changes from high level to low level, and the potential RIN applied to wiring 322 is low level.

[0078] Therefore, in period t3, in the pulse generation circuit 300, the pulse applied to the wiring 325 width control signal PWC1 potential (high level) is applied to the wiring 327 as the potential GOUT1 is. Also, the potential (high level) of the pulse width control signal PWC2 applied to the wiring 324 is applied to the wiring 328 as the potential GOUT2. Further, the potential CLK1 (high level) applied to the wiring 323 is applied to the wiring 329 as the potential SROUT.

[0079] Next, as shown in FIG. 6, in period t4, the potential CLK1 applied to the wiring 323 is high level, the potential CLK2 applied to the wiring 321 is low level, the potential of the pulse width control signal PWC1 applied to the wiring 325 changes from high level to low level, the potential of the pulse width control signal PWC2 applied to the wiring 324 is high level, the potential LIN applied to the wiring 319 is low level, and the potential RIN applied to the wiring 322 is low level. Therefore, in period t4, in the pulse generation circuit 300, the potential (changing from high level to low level) of the pulse width control signal PWC1 applied to the wiring 325 is applied to the wiring 327 as the potential GOUT1

[0080] is. Also, the potential (high level) of the pulse width control signal PWC2 applied to the wiring 324 is applied to the wiring 328 as the potential GOUT2. Further, the potential CLK1 (high level) applied to the wiring 323 is applied to the wiring 329 as the potential SROUT. is applied to the wiring 327 as the potential GOUT1. Also, the potential (high level) of the pulse width control signal PWC2 applied to the wiring 324 is applied to the wiring 328 as the potential GOUT2. Further, the potential CLK1 (high level) applied to the wiring 3 23 is applied to the wiring 329 as the potential SROUT. is applied.

[0081] Next, as shown in FIG. 6, in period t5, the potential CLK1 applied to the wiring 323 is low level, the potential CLK2 applied to the wiring 321 is high level, the potential of the pulse width control signal PWC1 applied to the wiring 325 The potential of the pulse width control signal PWC1 is at a low level, and the pulse width control signal PWC2 applied to the wiring 324 is at a low level, the potential LIN applied to the wiring 319 is at a low level, and the potential RIN applied to the wiring 322 becomes a high level.

[0082] Therefore, in the period t5, in the pulse generation circuit 300, the potential V EE (low level) applied to the wiring 326 is applied to the wiring 327 as the potential GOUT1. Also, the potential VSS (low level) applied to the wiring 31 8 is applied to the wiring 328 as the potential GOUT2 . Also, the potential VSS (low level) applied to the wiring 318 is applied to the wiring 329 as the potential SROUT .

[0083] In one aspect of the present invention, as described in Embodiment 1, at least one of the transistors 309, 312, and 315 corresponding to the output-side transistor and the transistor 302 have their gate electrodes electrically connected via a conductive film different from the above gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 309, 312, 315, and 302 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode can be made less likely to occur. Therefore, the semiconductor device according to one aspect of the present invention using the above shift register is less likely to have a reduction in yield due to electrostatic breakdown.

[0084] This embodiment can be implemented in appropriate combination with other embodiments.

[0085] (Embodiment 3) A configuration example of a pulse generation circuit included in a semiconductor device according to an aspect of the present invention will be described.

[0086] The pulse generation circuit 400 shown in FIG. 8(A) includes transistors 402 to 404 and transistors 415 to 420. By connecting a plurality of the pulse generation circuits 400 in series, a shift register can be configured.

[0087] The gate electrode of transistor 402 is connected to the gate electrodes of transistors 403 and 404, and one of its source and drain terminals is connected to wiring 406 and the other is connected to the gate electrode of transistor 420. One of the source and drain terminals of transistor 403 is connected to wiring 406 and the other is connected to wiring 414 . One of the source and drain terminals of transistor 404 is connected to wiring 407 and the other is connected to wiring 413.

[0088] Also, the gate electrode of transistor 415 is connected to wiring 408, and one of its source and drain terminals is connected to the gate electrode of transistor 420 and the other is connected to wiring 40 5. The gate electrode of transistor 416 is connected to wiring 409, and one of its source and drain terminals is connected to the gate electrodes of transistors 402, 403, and 404 and the other is connected to wiring 405. The gate electrode of transistor 417 is connected to wiring 410, and one of its source and drain terminals is connected to the gate electrodes of transistors 402, 403, and 404 terminals is connected to the gate electrodes of transistors 402, 403, and 404 ​​​One is connected to the gate electrode and the other is connected to wiring 405. Transistor 418 has its gate electrode connected to wiring 408, and one of its source and drain terminals is connected to wiring 4 06, and the other is connected to the gate electrodes of transistors 402, 403, and transistor 4 04. Transistor 419 has its gate electrode connected to the gate electrode of transistor 4 20, and one of its source and drain terminals is connected to wiring 41 4, and the other is connected to wiring 411. Transistor 420 has one of its source and drain terminals connected to wiring 413, and the other is connected to wiring 412.

[0089] When transistors 402 to 404 and transistors 415 to 4 20 are of n-channel type, specifically, a potential VDD is applied to wiring 405, and a potential VSS is applied to wiring 406, and a potential VEE is applied to wiring 407. Also, potentials of various signals such as a clock signal are applied to wiring 408 to wiring 412. Then a potential GOUT is output from wiring 413 and a potential SROUT is output from wiring 414.

[0090] In one aspect of the present invention, at least one of transistors 403 and transistor 404 corresponding to the output-side transistors and transistor 402 have their gate electrodes electrically connected via a conductive film provided in a layer different from the above gate electrode. With the above configuration , compared to the case where all the gate electrodes of transistors 403, 404, and transistor 402 are formed of a single conductive film, each conductive film functioning as a gate electrode ​​​​The area of the film can be kept small. Therefore, electrostatic breakdown due to the antenna effect of the conductive film functioning as the gate electrode can be made less likely to occur. Thus, a reduction in the yield due to electrostatic breakdown of the semiconductor device according to one aspect of the present invention, in which the pulse generation circuit 400 is used in a shift register or the like, can be made less likely to occur. Alternatively, in one aspect of the present invention, the transistor 420 corresponding to the transistor on the output side and the transistor 419 may be electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, a reduction in the yield due to electrostatic breakdown of the semiconductor device according to one aspect of the present invention, in which the pulse generation circuit 400 is used in a shift register or the like, can be made less likely to occur. Note that in FIG. 8(A), one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 404 on the output side may be connected to the wiring 406. However, as shown in FIG. 8(A), if one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407 instead of the wiring 406, the transistor 404 can be turned off when it should be turned off even if the transistor 404 is normally on. The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured.

[0091] Alternatively, in one aspect of the present invention, the transistor 420 corresponding to the transistor on the output side and the transistor 419 may be electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, a reduction in the yield due to electrostatic breakdown of the semiconductor device according to one aspect of the present invention, in which the pulse generation circuit 400 is used in a shift register or the like, can be made less likely to occur. Note that in FIG. 8(A), one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 404 on the output side may be connected to the wiring 406. However, as shown in FIG. 8(A), if one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407 instead of the wiring 406, the transistor 404 can be turned off when it should be turned off even if the transistor 404 is normally on. The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured. Note that in FIG. 8(A), one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 404 on the output side may be connected to the wiring 406. However, as shown in FIG. 8(A), if one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407 instead of the wiring 406, the transistor 404 can be turned off when it should be turned off even if the transistor 404 is normally on. The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured.

[0092] Note that in FIG. 8(A), one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 404 on the output side may be connected to the wiring 406. However, as shown in FIG. 8(A), if one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407 instead of the wiring 406, the transistor 404 can be turned off when it should be turned off even if the transistor 404 is normally on. The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured. Note that in FIG. 8(A), one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 404 on the output side may be connected to the wiring 406. However, as shown in FIG. 8(A), if one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407 instead of the wiring 406, the transistor 404 can be turned off when it should be turned off even if the transistor 404 is normally on. The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured. Note that in FIG. 8(A), one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 404 on the output side may be connected to the wiring 406. However, as shown in FIG. 8(A), if one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407 instead of the wiring 406, the transistor 404 can be turned off when it should be turned off even if the transistor 404 is normally on. The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured. Note that in FIG. 8(A), one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 404 on the output side may be connected to the wiring 406. However, as shown in FIG. 8(A), if one of the source terminal and the drain terminal of the transistor 404 on the output side is connected to the wiring 407 instead of the wiring 406, the transistor 404 can be turned off when it should be turned off even if the transistor 404 is normally on.

[0093] The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured. The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured. The pulse generation circuit 430 shown in FIG. 8(B) includes transistors 432 to 434 and transistors 446 to 452. By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured.

[0094] The gate electrode of transistor 432 is connected to the gate electrodes of transistor 433 and transistor 434, and one of its source terminal and drain terminal is connected to wiring 436 while the other is connected to the gate electrodes of transistor 451 and transistor 452. The source terminal or drain terminal of transistor 433 is connected to wiring 436, while the other is connected to wiring 445. The source terminal or drain terminal of transistor 434 is connected to wiring 437, while the other is connected to wiring 444.

[0095] Also, the gate electrode of transistor 446 is connected to wiring 438, and one of its source terminal and drain terminal is connected to the gate electrodes of transistor 451 and transistor 452, while the other is connected to wiring 435. The gate electrode of transistor 447 is connected to wiring 439, and one of its source terminal and drain terminal is connected to the gate electrodes of transistor 432, transistor 433, and transistor 434, while the other is connected to wiring 43 5. The gate electrode of transistor 448 is connected to wiring 440, and one of its source terminal and drain terminal is connected to the gate electrodes of transistor 432, transistor 433, and transistor 434, while the other is connected to wiring 435. The gate electrode of transistor 449 is connected to wiring 438, and one of its source terminal and drain terminal is connected to wiring 436, while the other is connected to the gate electrodes of transistor 432, transistor 43 3, and transistor 434. The gate electrode of transistor 450 is connected to wiring 441, and one of its source terminal and drain terminal is connected to the gate of the transistor is connected to the gate electrodes of transistor 432, transistor 433, and transistor 434, and the other is connected to wiring 435. One of the source terminal and the drain terminal of transistor 451 is connected to wiring 445, and the other is connected to wiring 442. The transistor 452 has one of its source terminal and drain terminal connected to wiring 444, and the other connected to wiring 443.

[0096] When transistors 432 to 434 and transistors 446 to 4 52 are of n-channel type, specifically, potential VDD is applied to wiring 435, potential VSS is applied to wiring 436, and potential VEE is applied to wiring 437. Also, the potentials of various signals such as clock signals are applied to wiring 438 to wiring 443. And potential GOUT is output from wiring 444, and potential SROUT is output from wiring 445.

[0097] In one aspect of the present invention, at least one of transistor 433 and transistor 434 corresponding to the output-side transistor and transistor 432 have their gate electrodes electrically connected via a conductive film provided in a layer different from the above gate electrode. With the above configuration, compared to the case where all the gate electrodes of transistor 433, transistor 434, and transistor 432 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode can be made less likely to occur. It is possible to make it difficult for the yield to decrease due to breakdown.

[0098] Alternatively, in one aspect of the present invention, a transistor 452 corresponding to the transistor on the output side, and the transistor 451 may be electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, the pulse generation circuit 430 can be used as a shift register or the like, and it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention to decrease due to electrostatic breakdown. 430 can be used as a shift register or the like, and it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention to decrease due to electrostatic breakdown. It is possible to make it difficult for the yield to decrease due to breakdown.

[0099] In FIG. 8(B), one of the source terminal and the drain terminal of the output-side transistor 434 is connected to the wiring 437, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 434 may be connected to the wiring 436. However, as shown in FIG. 8(B), if one of the source terminal and the drain terminal of the output-side transistor 434 is connected to the wiring 437 instead of the wiring 436, even if the transistor 4 34 is normally on, it can be turned off when the transistor 434 should be turned off. It can be turned off. 34 is normally on, it can be turned off when the transistor 434 should be turned off. 34 is normally on, it can be turned off when the transistor 434 should be turned off. It can be turned off.

[0100] The pulse generation circuit 460 shown in FIG. 9(A) includes transistors 462 to 464 and transistors 476 to 482. By connecting a plurality of the pulse generation circuits 460 in series, a shift register can be configured. By connecting a plurality of the pulse generation circuits 460 in series, a shift register can be configured.

[0101] The gate electrode of the transistor 462 is connected to the gate electrodes of the transistors 463 and 464, and one of its source terminal and drain terminal is connected to the wiring 466 and the other is connected to the wiring 467. , the other party is connected to one of the source terminal and the drain terminal of the transistor 477. The transistor 463 has one of its source terminal and drain terminal connected to the wiring 466, and the other is connected to the wiring 475. The transistor 464 has one of its source terminal and drain terminal connected to the wiring 467, and the other is connected to the wiring 474.

[0102] Also, for the transistor 476, its gate electrode is connected to the wiring 468, and one of its source terminal and drain terminal is connected to one of the source terminal and the drain terminal of the transistor 477, and the other is connected to the wiring 465. For the transistor 477, its gate electrode is connected to the wiring 465, and the other of its source terminal and drain terminal is connected to the gate electrodes of the transistor 481 and the transistor 482. For the transistor 478, its gate electrode is connected to the wiring 469, and one of its source terminal and drain terminal is connected to the gate electrodes of the transistor 462, the transistor 463, and the transistor 464, and the other is connected to the wiring 465. For the transistor 479, its gate electrode is connected to the wiring 468, and one of its source terminal and drain terminal is connected to the wiring 466, and the other is connected to the gate electrodes of the transistor 462, the transistor 463, and the transistor 464. For the transistor 480, its gate electrode is connected to the wiring 470, and one of its source terminal and drain terminal is connected to the gate electrodes of the transistor 462, the transistor 463, and the transistor 464, and the other is connected to the wiring 465. For the transistor 48 1, one of its source terminal and drain terminal is connected to the wiring 475, and the other is connected to the wiring 47 is connected to 1. One of the source terminal and the drain terminal of the transistor 482 is connected to the wiring 474, and the other is connected to the wiring 472.

[0103] When the transistors 462 to 464 and the transistors 476 to 4 82 are of n-channel type, specifically, the potential VDD is applied to the wiring 465, and the potential VSS is applied to the wiring 466, and the potential VEE is applied to the wiring 467. Also, the potentials of various signals such as a clock signal are applied to the wirings 468 to 472. Then the potential GOUT is output from the wiring 474, and the potential SROUT is output from the wiring 475.

[0104] In one aspect of the present invention, at least one of the transistors 463 and 464 corresponding to the output-side transistors, and the transistor 462 have their gate electrodes electrically connected via a conductive film provided in a layer different from the above gate electrode. With the above configuration compared to the case where all the gate electrodes of the transistors 463, 464, and 462 are formed of one conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode can be made less likely to occur. Thus, a decrease in the yield due to electrostatic breakdown of the semiconductor device according to one aspect of the present invention using the above pulse generation circuit 460 in a shift register or the like can be made less likely to occur.

[0105] Or, in one aspect of the present invention, the transistor 482 corresponding to the output-side transistor and the transistor 481 have their gate electrodes provided in a layer different from the above gate electrode.​​​​​​ It may be electrically connected via a conductive film. With the above configuration, the above pulse generation circuit 460 is used in a shift register or the like, and the yield reduction due to electrostatic breakdown of a semiconductor device according to an aspect of the present invention can be made less likely to occur.

[0106] In FIG. 9(A), one of the source terminal and the drain terminal of the output-side transistor 464 is connected to the wiring 467, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 464 may be connected to the wiring 466. However, as shown in FIG. 9(A), if one of the source terminal and the drain terminal of the output-side transistor 464 is connected to the wiring 467 instead of the wiring 466, even if the transistor 464 is normally on, it can be turned off when the transistor 464 should be turned off.

[0107] The pulse generation circuit 500 shown in FIG. 9(B) includes transistors 502 to 504 and transistors 516 to 523. By connecting a plurality of stages of the above pulse generation circuit 500, a shift register can be configured.

[0108] The gate electrode of the transistor 502 is connected to the gate electrodes of the transistors 503 and 504, and one of its source terminal and drain terminal is connected to the wiring 506, and the other is connected to one of the source terminal and drain terminal of the transistor 517. One of the source terminal and drain terminal of the transistor 503 is connected to the wiring 506, and the other is connected to the wiring 515. One of the source terminal and drain terminal of the transistor 504 is connected to the wiring 506, and the other is connected to the wiring 515. One of the terminals of the N terminal is connected to wiring 507, and the other is connected to wiring 514.

[0109] Also, for transistor 516, its gate electrode is connected to wiring 508, and one of its source and drain terminals is connected to one of the source and drain terminals of transistor 517, and the other is connected to wiring 505. For transistor 517, its gate electrode is connected to wiring 505, and the other of its source and drain terminals is connected to the gate electrode of transistor 521. For transistor 518, its gate electrode is connected to wiring 509, and one of its source and drain terminals is connected to the gate electrodes of transistors 502, 503, and 504, and the other is connected to wiring 505. For transistor 519, its gate electrode is connected to wiring 508, and one of its source and drain terminals is connected to wiring 506, and the other is connected to the gate electrodes of transistors 502, 503, and 504. For transistor 520, its gate electrode is connected to wiring 510, and one of its source and drain terminals is connected to the gate electrodes of transistors 502, 503, and 504, and the other is connected to wiring 505. For transistor 521, one of its source and drain terminals is connected to wiring 515, and the other is connected to wiring 511. For transistor 522, its gate electrode is connected to wiring 505, and one of its source and drain terminals is connected to the gate electrode of transistor 521, and the other is connected to the gate electrode of transistor 523. For transistor 523, one of its source and drain terminals is connected to wiring 515, and the other is connected to One of the input terminals is connected to wiring 514, and the other is connected to wiring 512.

[0110] When transistors 502 to 504 and transistors 516 to 5 23 are of the n-channel type, specifically, a potential VDD is applied to wiring 505, a potential VSS is applied to wiring 506, and a potential VEE is applied to wiring 507. Also, potentials of various signals such as a clock signal are applied to wiring 508 to wiring 512. Then, a potential GOUT is output from wiring 514, and a potential SROUT is output from wiring 515.

[0111]

[0112]

[0112] Yes. However, as shown in FIG. 9(B), if one of the source terminal and the drain terminal of the output-side transistor 504 is connected to the wiring 507 instead of the wiring 506, the transistor 5 04 can be turned off when it should be turned off even if the transistor 504 is in the normal-on state. It is possible.

[0113] The pulse generation circuit 530 shown in FIG. 10 includes transistors 532 to 534 and transistors 546 to 553. By connecting a plurality of stages of the pulse generation circuit 530 in series, a shift register can be configured.

[0114] The gate electrode of the transistor 532 is connected to the gate electrodes of the transistors 533 and 534, and one of its source terminal and drain terminal is connected to the wiring 536 and the other is connected to one of the source terminal and drain terminal of the transistor 452. The source terminal and drain terminal of the transistor 533 are connected to the wiring 536, and the other is connected to the wiring 545. One of the source terminal and drain terminal of the transistor 534 is connected to the wiring 537, and the other is connected to the wiring 544.

[0115] Also, the gate electrode of the transistor 546 is connected to the wiring 538, and one of its source terminal and drain terminal is connected to one of the source terminal and drain terminal of the transistor 532, and the other is connected to the wiring 535. The gate electrode of the transistor 547 is connected to the wiring 539, and one of its source terminal and drain terminal is connected to the gate electrodes of the transistors 532, 533, and 534, and the other is connected to the wiring 53 ​​​It is connected to 5. The gate electrode of transistor 548 is connected to wiring 540, and one of its source and drain terminals is connected to the gate electrodes of transistors 532, 533, and 534, and the other is connected to wiring 535. The gate electrode of transistor 549 is connected to wiring 538, and one of its source and drain terminals is connected to wiring 536, and the other is connected to the gate electrodes of transistors 532, 53 3, and 534. The gate electrode of transistor 550 is connected to wiring 535, and one of its source and drain terminals is connected to one of the source and drain terminals of transistor 552, and the other is connected to the gate electrode of transistor 551. The source and drain terminals of transistor 551 are connected to wiring 545 and wiring 541, respectively. The gate electrode of transistor 552 is connected to wiring 535, and the other of its source and drain terminals is connected to the gate electrode of transistor 553. The source and drain terminals of transistor 553 are connected to wiring 544 and wiring 542, respectively, and the connection continues. When transistors 532 to 534 and transistors 546 to 5 53 are of the n-channel type, specifically, a potential VDD is applied to wiring 535, a potential VSS is applied to wiring 536, and a potential VEE is applied to wiring 537. Also, potentials of various signals such as a clock signal are applied to wiring 538 to wiring 542. Then, a potential GOUT is output from wiring 544, and a potential SROUT is output from wiring 545.

[0116] When transistors 532 to 534 and transistors 546 to 5 53 are of the n-channel type, specifically, a potential VDD is applied to wiring 535, a potential VSS is applied to wiring 536, and a potential VEE is applied to wiring 537. Also, potentials of various signals such as a clock signal are applied to wiring 538 to wiring 542. Then, a potential GOUT is output from wiring 544, and a potential SROUT is output from wiring 545.

[0117] In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown. In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown. In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown. In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown. In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown. In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown. In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown. In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown. In one aspect of the present invention, at least one of the transistors 533 and 534 corresponding to the output-side transistor and the transistor 532 have their gate electrodes electrically connected via a conductive film provided in a layer different from the gate electrode. With the above configuration, compared to the case where all the gate electrodes of the transistors 533, 534, and 532 are formed of a single conductive film, the area of each conductive film functioning as a gate electrode can be suppressed to be small. Therefore, it is possible to make it difficult for electrostatic breakdown due to the antenna effect of the conductive film functioning as a gate electrode to occur. Accordingly, it is possible to make it difficult for the yield of the semiconductor device according to one aspect of the present invention using the pulse generation circuit 530 in a shift register or the like to decrease due to electrostatic breakdown.

[0118] Note that in FIG. 10, one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 534 may be connected to the wiring 536. However, as shown in FIG. 10, if one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537 instead of the wiring 536, even if the transistor 534 is a normally-on transistor, it can be turned off when the transistor 534 is to be turned off. Note that in FIG. 10, one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 534 may be connected to the wiring 536. However, as shown in FIG. 10, if one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537 instead of the wiring 536, even if the transistor 534 is a normally-on transistor, it can be turned off when the transistor 534 is to be turned off. Note that in FIG. 10, one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 534 may be connected to the wiring 536. However, as shown in FIG. 10, if one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537 instead of the wiring 536, even if the transistor 534 is a normally-on transistor, it can be turned off when the transistor 534 is to be turned off. Note that in FIG. 10, one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 534 may be connected to the wiring 536. However, as shown in FIG. 10, if one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537 instead of the wiring 536, even if the transistor 534 is a normally-on transistor, it can be turned off when the transistor 534 is to be turned off. Note that in FIG. 10, one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 534 may be connected to the wiring 536. However, as shown in FIG. 10, if one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537 instead of the wiring 536, even if the transistor 534 is a normally-on transistor, it can be turned off when the transistor 534 is to be turned off. Note that in FIG. 10, one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 534 may be connected to the wiring 536. However, as shown in FIG. 10, if one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537 instead of the wiring 536, even if the transistor 534 is a normally-on transistor, it can be turned off when the transistor 534 is to be turned off. Note that in FIG. 10, one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the output-side transistor 534 may be connected to the wiring 536. However, as shown in FIG. 10, if one of the source terminal and the drain terminal of the output-side transistor 534 is connected to the wiring 537 instead of the wiring 536, even if the transistor 534 is a normally-on transistor, it can be turned off when the transistor 534 is to be turned off.

[0119] This embodiment can be implemented in appropriate combination with other embodiments.

[0120] (Embodiment 4) Taking a light-emitting device using an OLED as an example, the pixel and the cross-sectional structure of the driving circuit will be described with reference to FIG. 11. FIG. 11 shows a cross-sectional view of the pixel 840 and the driving circuit 841 as an example.

[0121] In FIG. 11, the pixel 840 includes a light-emitting element 832 and a transistor 831 that controls the supply of current to the light-emitting element 832. The pixel 840 may further include various semiconductor elements such as a transistor that controls the input of an image signal to the pixel 840 and a capacitor element that holds the potential of the image signal, in addition to the light-emitting element 832 and the transistor 831. In addition to the light-emitting element 832 and the transistor 831, the pixel 840 may have various semiconductor elements such as a transistor that controls the input of an image signal to the pixel 840 and a capacitor element that holds the potential of the image signal.

[0122] Also, in FIG. 11, the driving circuit 841 includes a transistor 830. Specifically, the transistor 830 corresponds to an output-side transistor of a shift register that is part of the driving circuit 841. The driving circuit 841 may further include various semiconductor elements such as transistors and capacitor elements, in addition to the transistor 830. The transistor 830 corresponds to an output-side transistor of a shift register that is part of the driving circuit 841. In addition to the transistor 830, the driving circuit 841 may have various semiconductor elements such as transistors and capacitor elements.

[0123] The transistor 831 has a conductive film 816 that functions as a gate electrode, a gate insulating film 802 on the conductive film 816, a semiconductor film 817 provided on the gate insulating film 802 at a position overlapping the conductive film 816, and conductive films 815 and 818 that function as source or drain terminals and are located on the semiconductor film 817, on a substrate 800 having an insulating surface. The conductive film 816 also functions as a scanning line. The conductive film 816 also functions as a scanning line. The transistor 831 has a conductive film 816 that functions as a gate electrode, a gate insulating film 802 on the conductive film 816, a semiconductor film 817 provided on the gate insulating film 802 at a position overlapping the conductive film 816, and conductive films 815 and 818 that function as source or drain terminals and are located on the semiconductor film 817, on a substrate 800 having an insulating surface. The conductive film 816 also functions as a scanning line.

[0124] The transistor 830 has a conductive film 812 that functions as a gate electrode, a gate insulating film 802 on the conductive film 812, a semiconductor film 817 provided on the gate insulating film 802 at a position overlapping the conductive film 812, on a substrate 800 having an insulating surface. The transistor 830 has a conductive film 812 that functions as a gate electrode, a gate insulating film 802 on the conductive film 812, and a semiconductor film 817 provided on the gate insulating film 802 at a position overlapping the conductive film 812, on a substrate 800 having an insulating surface. ​​​A semiconductor film 813 provided on the gate insulating film 802, and a conductive film 814 and a conductive film 819 that function as a source terminal or a drain terminal and are located on the semiconductor film 813. And it has. .

[0125] In addition, a conductive film 850 provided on a substrate 800 having an insulating surface functions as a gate electrode of a transistor different from the transistor 830. And the conductive film 812 and the conductive film 850 are connected to a conductive film 851 on the gate insulating film 802 through an opening provided in the gate insulating film 802 on the conductive film 812 and the conductive film 850. Through.

[0126] In addition, an insulating film 820 and an insulating film 821 are provided so as to be sequentially stacked on the conductive film 814, the conductive film 815, the conductive film 818, the conductive film 819, and the conductive film 851. And on the insulating Film 821, a conductive film 852 and a conductive film 853 are provided. The conductive film 852 and The conductive film 853 is connected to the conductive film 8 51 and the conductive film 818 through openings provided in the insulating film 820 and the insulating film 821, respectively. Connected respectively.

[0127] In addition, an insulating film 854 is provided on the conductive film 852 and the conductive film 853. And on the insulating Film 854, a conductive film 822 that functions as an anode is provided. The conductive film 822 is Connected to the conductive film 853 through an opening formed in the insulating film 854.

[0128] In addition, an insulating film 824 having an opening through which a part of the conductive film 822 is exposed is provided on the insulating film 85 4. An EL layer 825 and A conductive film 826 that functions as a cathode are provided so as to be sequentially stacked on a part of the conductive film 822 and the insulating film 854. Conductive film 82 The region where 2, the EL layer 825, and the conductive film 826 overlap corresponds to the light-emitting element 832. That is.

[0129] In one aspect of the present invention, the transistors 830 and 831 may use a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, as the semiconductor film, or a wide-gap semiconductor such as an oxide semiconductor may be used as the semiconductor film. That is, a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, may be used for the semiconductor films of the transistors 830 and 831, or a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor films. That is, a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, may be used for the semiconductor films of the transistors 830 and 831, or a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor films. That is.

[0130] When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor films of the transistors 830 and 831, an impurity element that imparts one conductivity is added to the semiconductor film to form an impurity region that functions as a source region or a drain region. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed. When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor films of the transistors 830 and 831, an impurity element that imparts one conductivity is added to the semiconductor film to form an impurity region that functions as a source region or a drain region. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed. When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor films of the transistors 830 and 831, an impurity element that imparts one conductivity is added to the semiconductor film to form an impurity region that functions as a source region or a drain region. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed. When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor films of the transistors 830 and 831, an impurity element that imparts one conductivity is added to the semiconductor film to form an impurity region that functions as a source region or a drain region. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed. When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor films of the transistors 830 and 831, an impurity element that imparts one conductivity is added to the semiconductor film to form an impurity region that functions as a source region or a drain region. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed. When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor films of the transistors 830 and 831, an impurity element that imparts one conductivity is added to the semiconductor film to form an impurity region that functions as a source region or a drain region. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed.

[0131] When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, a dopant may be added to the semiconductor film to form an impurity region that functions as a source region or a drain region. The dopant can be added using an ion implantation method. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, a dopant may be added to the semiconductor film to form an impurity region that functions as a source region or a drain region. The dopant can be added using an ion implantation method. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, a dopant may be added to the semiconductor film to form an impurity region that functions as a source region or a drain region. The dopant can be added using an ion implantation method. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, a dopant may be added to the semiconductor film to form an impurity region that functions as a source region or a drain region. The dopant can be added using an ion implantation method. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, a dopant may be added to the semiconductor film to form an impurity region that functions as a source region or a drain region. The dopant can be added using an ion implantation method. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, a dopant may be added to the semiconductor film to form an impurity region that functions as a source region or a drain region. The dopant can be added using an ion implantation method. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 19 / cm 3 or more and 1× 10 22 / cm 3 It is desirable that it is as follows.

[0132] As for the silicon semiconductor, amorphous silicon produced by a vapor phase growth method such as plasma CVD method or sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by treatment such as laser annealing and single crystal silicon obtained by implanting hydrogen ions or the like into a single crystal silicon wafer and peeling off the surface layer portion can be used.

[0133] As for the oxide semiconductor, it preferably contains at least indium (In) or zinc (Zn). Particularly, it is preferable to contain In and Zn. Further, as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide, in addition to those it preferably has gallium (Ga). Further, it preferably has tin (Sn) as a stabilizer. Further, it preferably has hafnium (Hf) as a stabilizer. Further, it preferably has aluminum (Al) as a stabilizer. Further, it preferably has aluminum (Al) as a stabilizer.

[0134] Further, as other stabilizers, it may contain any one or more of lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu) which are lanthanoids.

[0135] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, oxide of binary metal Substances such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, and ternary metal oxides such as In-Ga-Zn oxides (also denoted as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, I n-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In -Lu-Zn oxides, and quaternary metal oxides such as In-Sn-Ga-Zn oxides, I n-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al- Zn oxides, In-Sn-Hf-Zn oxides, and In-Hf-Al-Zn oxides can be used. Further, the above oxide semiconductors may contain silicon. Note that, for example, In-Ga-Zn oxides mean oxides containing In, Ga, and Zn,

[0136] and the ratio of In, Ga, and Zn is not limited. Also, it may contain metal elements other than In, Ga, and Zn. In-Ga-Zn oxides have a sufficiently high resistance in the absence of an electric field, can sufficiently reduce the off-current, and also have a high mobility, so they are suitable as semiconductor materials for semiconductor devices.

[0137] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) In-Ga-Zn oxide with an atomic ratio of or an oxide near its composition can be used. Alternatively, In:Sn:Zn = 1: 1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) atomic ratio of In-Sn-Zn oxide and oxides near its composition are preferably used.

[0138] For example, in the In-Sn-Zn oxide, a relatively high mobility can be obtained relatively easily. However, even in the In-Ga-Zn oxide, the mobility can be increased by reducing the bulk defect density.

[0139] In addition, an oxide semiconductor that is highly purified by reducing impurities such as moisture or hydrogen that act as electron donors (donors) and reducing oxygen deficiency is of type i (intrinsic semiconductor) or very close to type i. Therefore, a transistor using the above oxide semiconductor has the characteristic that the off-current is extremely low. Also, the bandgap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor film that is highly purified by sufficiently reducing the impurity concentration of impurities such as moisture or hydrogen and reducing oxygen deficiency, the off-current of the transistor can be reduced.

[0140] Specifically, the fact that the off-current of a transistor using a highly purified oxide semiconductor for the semiconductor film is low can be proven by various experiments. For example, when the channel width is 1 × 10 6 μm and the ch Even for an element with a channel length of 10 μm, when the voltage between the source terminal and the drain terminal (drain voltage) is in the range of 1 V to 10 V, the off-current can be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 A or less. In this case, it can be seen that the off-current corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 zA / μm or less. Also, a circuit is used in which a capacitive element and a transistor are connected and the charge flowing into or flowing out of the capacitive element is controlled by the transistor, and the off-current -13 is measured. In this measurement, an oxide semiconductor film with high purity is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitive element. As a result, it was found that when the voltage between the source terminal and the drain terminal of the transistor is 3 V, an even lower off-current of several tens of yA / μm can be obtained . Therefore, a transistor using an oxide semiconductor film with high purity for the channel formation region has an off-current that is significantly lower than that of a transistor using crystalline silicon . Note that, unless otherwise specified, in this specification, the off-current means, in an n-channel type transistor, the current flowing between the source terminal and the drain terminal when the potential of the gate electrode is 0 or less with respect to the potential of the source terminal in a state where the drain terminal is at a higher potential than the source terminal and the gate electrode . Alternatively, in this specification, the off-current means, in a p-channel type transistor, the current flowing between the source terminal and the drain terminal when the potential of the gate electrode is 0 or more with respect to the potential of the source terminal in a state where the drain terminal is at a lower potential than the source terminal and the gate electrode . In the above measurement, an oxide semiconductor film with high purity is used for the channel formation region of the above transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitive element . As a result, it was found that when the voltage between the source terminal and the drain terminal of the transistor is 3 V, an even lower off-current of several tens of yA / μm can be obtained . Therefore, a transistor using an oxide semiconductor film with high purity for the channel formation region has an off-current that is significantly lower than that of a transistor using crystalline silicon . Note that, unless otherwise specified, in this specification, the off-current means, in an n-channel type transistor, the current flowing between the source terminal and the drain terminal when the potential of the gate electrode is 0 or less with respect to the potential of the source terminal in a state where the drain terminal is at a higher potential than the source terminal and the gate electrode . Alternatively, in this specification, the off-current means, in a p-channel type transistor, the current flowing between the source terminal and the drain terminal when the potential of the gate electrode is 0 or more with respect to the potential of the source terminal in a state where the drain terminal is at a lower potential than the source terminal and the gate electrode . That is, in an n-channel type transistor, when the potential of the gate electrode is 0 or less with respect to the potential of the source terminal in a state where the drain terminal is at a higher potential than the source terminal and the gate electrode, the off-current means the current flowing between the source terminal and the drain terminal

[0141] . Note that, unless otherwise specified, in this specification, the off-current means, in an n-channel type transistor, the current flowing between the source terminal and the drain terminal when the potential of the gate electrode is 0 or less with respect to the potential of the source terminal in a state where the drain terminal is at a higher potential than the source terminal and the gate electrode . Or, in this specification, the off-current means, in a p-channel type transistor, the current flowing between the source terminal and the drain terminal when the potential of the gate electrode is 0 or more with respect to the potential of the source terminal in a state where the drain terminal is at a lower potential than the source terminal and the gate electrode . That is, in an n-channel type transistor, when the potential of the gate electrode is 0 or less with respect to the potential of the source terminal in a state where the drain terminal is at a higher potential than the source terminal and the gate electrode, the off-current means the current flowing between the source terminal and the drain terminal . Or, in this specification, the off-current means, in a p-channel type transistor, the current flowing between the source terminal and the drain terminal when the potential of the gate electrode is 0 or more with respect to the potential of the source terminal in a state where the drain terminal is at a lower potential than the source terminal and the gate electrode . That is, in a p-channel type transistor, when the potential of the gate electrode is 0 or more with respect to the potential of the source terminal in a state where the drain terminal is at a lower potential than the source terminal and the gate electrode, the off-current means the current flowing between the source terminal and the drain terminal . That is, in a p-channel type transistor, when the potential of the gate electrode is 0 or more with respect to the potential of the source terminal in a state where the drain terminal is at a lower potential than the source terminal and the gate electrode, the off-current means the current flowing between the source terminal and the drain terminal When it is as described above, it means the current flowing between the source terminal and the drain terminal.

[0142] Note that, for example, the oxide semiconductor film can be formed by a sputtering method using a target containing In (indium), Ga (gallium), and Zn ( zinc). When forming an In-Ga- Zn-based oxide semiconductor film by a sputtering method, preferably, a target of an In-Ga-Zn-based oxide having an atomic ratio of In :Ga:Zn = 1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 is used. By forming an oxide semiconductor film using a target of an In-Ga-Zn-based oxide having the above-described atomic ratio , polycrystals or CAAC (C Axis Aligned Crystal) are likely to be formed. In addition, the relative density of the target containing In, Ga, and Zn is 90% or more and 1 00% or less, preferably 95% or more and less than 100%. By using a target with a high relative density , the formed oxide semiconductor film becomes a dense film. Note that when using an In-Zn-based oxide material as the oxide semiconductor, the atomic ratio of the metal elements in the target used

[0143] is, in terms of atomic ratio, In:Zn = 50:1 to 1:2 (when converted to molar ratio, In O :ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1 2 O 3 :ZnO = 10:1 to 1:2), more preferably In:Zn = 1.5:1 to 15:1 (when converted to molar ratio, In 2 O 3 :ZnO = 3: 4 to 15:2). For example, when forming an oxide semiconductor film that is an In-Zn-based oxide, it is used 2 O 3 :ZnO = 3: For example, for the formation of an oxide semiconductor film that is an In-Zn-based oxide, The target is such that when the atomic ratio is In:Zn:O = X:Y:Z, Z > 1.5X + Y. By keeping the ratio of Zn within the above range, an improvement in mobility can be achieved.

[0144] Note that the oxide semiconductor film can be in any state of single crystal, polycrystal (also referred to as polycrystalline), or amorphous.

[0145] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film.

[0146] The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed-phase structure with crystal parts and amorphous parts in an amorphous phase. Note that the crystal parts are often sized to fit within a cube with a side length of less than 100 nm. Also, in an observation image by a transmission electron microscope (TEM: Transmission Electron Microscope), the boundary between the amorphous part and the crystal part contained in the CAAC-OS film is not clear. Also, grain boundaries (also referred to as grain boundaries) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is suppressed.

[0147] The crystal parts contained in the CAAC-OS film have their c-axes aligned in a direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab plane, they have a triangular shape or a hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are arranged in layers. Note that between different crystal parts, the a-axes respectively, The directions of the y-axis and the b-axis may be different. In this specification, when simply described as perpendicular, it also includes the range of 8 5° or more and 95° or less. Also, when simply described as parallel, it also includes the range of -5 ° or more and 5° or less.

[0148] Note that in the CAAC-OS film, the distribution of the crystal parts does not have to be uniform. For example, in the process of forming the CAA C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of the crystal parts may be higher near the surface than near the formation surface. Also, by adding impurities to the CA AC-OS film, the crystal parts may be amorphous in the impurity addition region.

[0149] The c-axis of the crystal parts included in the CAAC-OS film aligns in a direction parallel to the normal vector of the formation surface or the normal vector of the surface of the CAAC-OS film. Therefore, depending on the shape of the CAAC-OS film (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Also note that the direction of the c-axis of the crystal parts is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS film is formed. The crystal parts are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation.

[0150] A transistor using the CAAC-OS film can reduce the change in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0151] The CAAC-OS film is formed, for example, by a sputtering method using a polycrystalline oxide semiconductor sputtering target. Ions are applied to the sputtering target. ​​​​​​​​ When there is a conflict, the crystal region contained in the sputtering target splits from the a-b plane and peels off as plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a -b plane. In this case, the plate-shaped sputtering particles can form a CAAC-OS film by reaching the substrate while maintaining the crystalline state. By reaching the substrate while maintaining the crystalline state, a CAAC-OS film can be formed.

[0152] In addition, in order to form a CAAC-OS film, it is preferable to apply the following conditions.

[0153] By reducing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystalline state by the impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced. In addition, the impurity concentration in the film formation gas may be reduced. Specifically, a film formation gas having a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0154] In addition, by increasing the substrate heating temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower for film formation. By increasing the substrate heating temperature during film formation, when plate-shaped sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate.

[0155] In addition, it is preferable to reduce the plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is 30% by volume or higher, preferably 100% by volume .

[0156] ​​As an example of a sputtering target, an In-Ga-Zn-O compound target will be described below. It is shown as follows.

[0157] InO X powder, GaO Y powder, and ZnO Z powder are mixed in a predetermined number of moles, and after pressure treatment , heat treatment is performed at a temperature of 1000°C or higher and 1500°C or lower to obtain a polycrystalline In-Ga -Zn-O compound target. Here, X, Y, and Z are arbitrary positive numbers. Here , the predetermined mole ratio is, for example, InO X powder, GaO Y powder, and ZnO Z powder are 2 :2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. Note that the type of powder and the mole ratio for mixing can be appropriately changed depending on the sputtering target to be produced. It may be appropriately changed.

[0158] This embodiment can be implemented in appropriate combination with other embodiments.

[0159] (Embodiment 5) In this embodiment, an example of a panel corresponding to one form of a semiconductor display device will be described. . The panel shown in FIG. 12 includes a substrate 700, a pixel portion 701 on the substrate 700, a signal line driving circuit 702a, a signal line driving circuit 702b, a scanning line driving circuit 703a, and a scanning line driving circuit 70 3b.

[0160] The pixel portion 701 has a plurality of pixels, and each pixel is provided with a display element and one or more transistors for controlling the operation of the display element. The scanning line driving circuits 703a and 70 3b supply a potential to the scanning lines connected to each pixel, thereby causing the pixel portion 70 to operate. Select the pixels that 1 has. The signal line drive circuits 702a and 702b are for the supply of the image signal to the pixels selected by the scan line drive circuits 703a and 703b. Control the supply.

[0161] In FIG. 12, the case where the scan line drive circuits 703a and 703b supply potentials to each scan line from both ends of the pixel portion 701 is illustrated. With the above configuration, even if the scan lines become long due to the enlargement of the pixel portion 701, it is possible to prevent the potential drop caused by the wiring resistance of the scan lines within the pixel portion 701.

[0162] Also, the supply of the image signal to the pixels by the signal line drive circuits 702a and 702b is performed via the signal lines. In FIG. 12, the case where the signal line drive circuit 702a supplies the image signal to the pixels via the odd-numbered signal lines and the signal line drive circuit 702b supplies the image signal to the pixels via the even-numbered signal lines is illustrated.

[0163] Also, in FIG. 12, the scan line drive circuits 703a and 703b are formed on the substrate 700 together with the pixel portion 701, and the signal line drive circuits 702a and 702b formed on the chip are mounted on the substrate 700 using the TAB (Tape Automated Bonding) method. The scan line drive circuits 703a and 703b formed on the chip may be mounted on the substrate 700, or alternatively, the signal line drive circuits 702a and 702b may be formed on the substrate 700 together with the pixel portion 701. Also, the mounting of the chip is not limited to the TAB method. ​​​​​The chip may be mounted on the substrate 700 using an FPC (Flexible Printed Circuit) or the like. Alternatively, the chip may be mounted on the substrate 700 using the COF (Chip On Film) method. The scanning lines are connected to a plurality of pixels, so the scanning line driving circuits 703a and 703b are required to have a large current supply capacity. Therefore, the transistors located on the output side of the pulse output circuits of the scanning line driving circuits 703a and 703b need to have large sizes. In particular, when the number of pixels in the pixel portion 701 increases, or when the area of the pixel portion 701 increases, an increase in the wiring resistance of the scanning lines or an increase in the load connected to the scanning lines will occur. Therefore, in order to satisfy a larger current supply capacity, it is necessary to further increase the size of the above-mentioned transistors. And when the size of the above-mentioned transistors becomes large, the area of the conductive film that functions as the gate electrodes of the plurality of transistors in the scanning line driving circuits 703a and 703b will increase, and electrostatic breakdown of the wiring due to the antenna effect is likely to occur. However, in one aspect of the present invention, a plurality of gate electrodes are electrically connected via a conductive film provided in a layer different from the above-mentioned gate electrodes. Therefore, the area of each conductive film that functions as a gate electrode can be kept small, so that even when the number of pixels in the pixel portion 701 increases or the area of the pixel portion 701 increases, electrostatic breakdown due to the antenna effect can be made less likely to occur. The scanning lines are connected to a plurality of pixels, so the scanning line driving circuits 703a and 703b are required to have a large current supply capacity. Therefore, the transistors located on the output side of the pulse output circuits of the scanning line driving circuits 703a and 703b need to have large sizes. In particular, when the number of pixels in the pixel portion 701 increases, or when the area of the pixel portion 701 increases, an increase in the wiring resistance of the scanning lines or an increase in the load connected to the scanning lines will occur. Therefore, in order to satisfy a larger current supply capacity, it is necessary to further increase the size of the above-mentioned transistors. And when the size of the above-mentioned transistors becomes large, the area of the conductive film that functions as the gate electrodes of the plurality of transistors in the scanning line driving circuits 703a and 703b will increase, and electrostatic breakdown of the wiring due to the antenna effect is likely to occur. However, in one aspect of the present invention, a plurality of gate electrodes are electrically connected via a conductive film provided in a layer different from the above-mentioned gate electrodes. Therefore, the area of each conductive film that functions as a gate electrode can be kept small, so that even when the number of pixels in the pixel portion 701 increases or the area of the pixel portion 701 increases, electrostatic breakdown due to the antenna effect can be made less likely to occur.

[0164] Since the scanning lines are connected to a plurality of pixels, the scanning line driving circuits 703a and 703b are required to have a large current supply capacity. Therefore, the transistors located on the output side of the pulse output circuits of the scanning line driving circuits 703a and 703b need to have large sizes. In particular, when the number of pixels in the pixel portion 701 increases, or when the area of the pixel portion 701 increases, an increase in the wiring resistance of the scanning lines or an increase in the load connected to the scanning lines will occur. Therefore, in order to satisfy a larger current supply capacity, it is necessary to further increase the size of the above-mentioned transistors. And when the size of the above-mentioned transistors becomes large, the area of the conductive film that functions as the gate electrodes of the plurality of transistors in the scanning line driving circuits 703a and 703b will increase. Electrostatic breakdown of the wiring due to the antenna effect is likely to occur. However, in one aspect of the present invention, a plurality of gate electrodes are electrically connected via a conductive film provided in a layer different from the above-mentioned gate electrodes. Therefore, the area of each conductive film that functions as a gate electrode can be kept small. So that even when the number of pixels in the pixel portion 701 increases or the area of the pixel portion 701 increases, electrostatic breakdown due to the antenna effect can be made less likely to occur. However, in one aspect of the present invention, a plurality of gate electrodes are electrically connected via a conductive film provided in a layer different from the above-mentioned gate electrodes. Therefore, the area of each conductive film that functions as a gate electrode can be kept small. So that even when the number of pixels in the pixel portion 701 increases or the area of the pixel portion 701 increases, electrostatic breakdown due to the antenna effect can be made less likely to occur. Since the scanning lines are connected to a plurality of pixels, the scanning line driving circuits 703a and 703b are required to have a large current supply capacity. Therefore, the transistors located on the output side of the pulse output circuits of the scanning line driving circuits 703a and 703b need to have large sizes.

[0165] In addition, in this embodiment, the scanning line driving circuits 703a and 703b are provided with the present invention. Although the case where the configuration according to the embodiment of the present invention is applied has been described, in one embodiment of the present invention, A structure according to one embodiment of the present invention is applied to the driver circuit 702a and the signal line driver circuit 702b. is also good.

[0166] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0167] (Embodiment 6) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, personal digital assistants, e-books, video cameras, digital cameras, etc. Cameras such as Talstill cameras, goggle-type displays (head-mounted displays) , navigation systems, audio playback devices (car audio, digital audio players) Copiers, fax machines, printers, printer-combination machines, automated teller machines, Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 13. .

[0168] FIG. 13A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, A driving circuit for a portable game machine, or a display unit 5003 or By using a semiconductor device according to one embodiment of the present invention for the display portion 5004, a mobile phone with high yield can be manufactured. A belt-type game machine can be provided. Note that the portable game machine shown in Fig. 13(A) has two display units 5003 and 5004, but the number of display units of the portable game machine is not limited to this.

[0169] Fig. 13(B) is a display device, which has a housing 5201, a display unit 5202, a support base 5203, etc. By using the drive circuit of the display device or the semiconductor display device according to one aspect of the present invention for the display unit 5202, a display device with a high yield can be provided. Note that the display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, etc.

[0170] Fig. 13(C) is a notebook personal computer, which has a housing 5401, a display unit 5402 , a keyboard 5403, a pointing device 5404, etc. By using the drive circuit of the notebook personal computer or the semiconductor display device according to one aspect of the present invention for the display unit 5402, a notebook personal computer with a high yield can be provided.

[0171] Fig. 13(D) is a portable information terminal, which has a first housing 5601, a second housing 5602, a first display unit 5603, a second display unit 5604, a connection part 5605, operation keys 5606, etc. The first display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 02. The first housing 5601 and the second housing 5602 are connected by the connection part 56 05, and the angle between the first housing 5601 and the second housing 5602 is movable by the connection part 5605. The switching of the video on the first display unit 5603 is performed by the connection ​​​​​It may be configured to switch according to the angle between the first housing 5601 and the second housing 5602 in the unit 5605. Also, at least one of the first display unit 5603 and the second display unit 5604 may use a semiconductor display device with a function as a position input device. Note that the function as a position input device can be added by providing a touch panel to the semiconductor display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, to the pixel portion of the semiconductor display device. By using the drive circuit of the portable information terminal, or the semiconductor device according to one aspect of the present invention in the first display unit 5603 or the second display unit 5604, a portable information terminal with a high yield can be provided. Figure 13(E) shows a mobile phone, which has a housing 5801, a display unit 5802, a voice input unit 5803, a voice output unit 5804, operation keys 5805, a light receiving unit 5806, etc. By converting the light received by the light receiving unit 5806 into an electrical signal, an external image can be captured. By using the drive circuit of the mobile phone, or the semiconductor device according to one aspect of the present invention in the display unit 5802, a mobile phone with a high yield can be provided. This embodiment can be implemented in appropriate combination with other embodiments.

Description of Reference Numerals

[0172] 105 Wiring 106 Wiring

[0173]

[0174] ​​​​​​​​​​​107 Wiring 110 Conductive Film 111 Gate Insulating Film 112 Semiconductor Film 113 Conductive Film 114 Conductive Film 115 Conductive Film 116 Semiconductor Film 117 Conductive Film 118 Conductive Film 119 Conductive Film 120 Opening 121 Opening 122 Conductive Film 123 Semiconductor Film 124 Conductive Film 125 Conductive Film 126 Semiconductor Film 127 Conductive Film 128 Conductive Film 210 Conductive Film 211 Gate Insulating Film 212 Semiconductor Film 213 Conductive Film 214 Conductive Film 215 Conductive Film 216 Semiconductor Film 217 Conductive Film 218 Conductive Film 219 Conductive Film 220 Opening 221 Opening 222 Conductive Film 223 Semiconductor Film 224 Conductive Film 225 Conductive Film 226 Semiconductor Film 227 Conductive Film 228 Conductive Film 300 Pulse Generation Circuit 301 Transistor 302 Transistor 303 Transistor 304 Transistor 305 Transistor 306 Transistor 307 Transistor 308 Transistor 309 Transistor 310 Transistor 311 Transistor 312 Transistor 313 Transistor 314 Transistor 315 Transistor 316 Capacitor element 317 Wiring 318 Wiring 319 Wiring 320 Wiring 321 Wiring 322 Wiring 323 Wiring 324 Wiring 325 Wiring 326 Wiring 327 Wiring 328 Wiring 329 Wiring 350 Inverter 351 Inverter 400 Pulse generation circuit 402 Transistor 403 Transistor 404 Transistor 405 Wiring 406 Wiring 407 Wiring 408 Wiring 409 Wiring 410 Wiring 411 Wiring 412 Wiring 413 Wiring 414 Wiring 415 Transistor 416 Transistor 417 Transistor 418 Transistor 419 Transistor 420 Transistor 430 Pulse generation circuit 432 Transistor 433 Transistor 434 Transistor 435 Wiring 436 Wiring 437 Wiring 438 Wiring 439 Wiring 440 Wiring 441 Wiring 442 Wiring 443 Wiring 444 Wiring 445 Wiring 446 Transistor 447 Transistor 448 Transistor 449 Transistor 450 Transistor 451 Transistor 452 Transistor 460 Pulse Generation Circuit 462 Transistor 463 Transistor 464 Transistor 465 Wiring 466 Wiring 467 Wiring 468 Wiring 469 Wiring 470 Wiring 471 Wiring 472 Wiring 474 Wiring 475 Wiring 476 Transistor 477 Transistor 478 Transistor 479 Transistor 480 Transistor 481 Transistor 482 Transistor 500 Pulse Generation Circuit 502 Transistor 503 Transistor 504 Transistor 505 Wiring 506 Wiring 507 Wiring 508 Wiring 509 Wiring 510 Wiring 511 Wiring 512 Wiring 514 Wiring 515 Wiring 516 Transistor 517 Transistor 518 Transistor 519 Transistor 520 Transistor 521 Transistor 522 Transistor 523 Transistor 530 Pulse Generation Circuit 532 Transistor 533 Transistor 534 Transistor 535 Wiring 536 Wiring 537 Wiring 538 Wiring 539 Wiring 540 Wiring 541 Wiring 542 Wiring 544 Wiring 545 Wiring 546 Transistor 547 Transistor 548 Transistor 549 Transistor 550 Transistor 551 Transistor 552 Transistor 553 Transistor 700 Substrate 701 Pixel Section 702a Signal Line Driving Circuit 702b Signal Line Driving Circuit 703a Scanning Line Driving Circuit 703b Scanning Line Driving Circuit 800 Substrate 802 Gate Insulating Film 812 Conductive Film 813 Semiconductor Film 814 Conductive Film 815 Conductive Film 816 Conductive film 817 Semiconductor film 818 Conductive film 819 Conductive film 820 Insulating film 821 Insulating film 822 Conductive film 824 Insulating film 825 EL layer 826 Conductive film 830 Transistor 831 Transistor 832 Light-emitting element 840 Pixel 841 Driving circuit 850 Conductive film 851 Conductive film 852 Conductive film 853 Conductive film 854 Insulating film 5001 Housing 5002 Housing 5003 Display unit 5004 Display unit 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Housing 5202 Display unit 5203 Support stand 5401 Housing 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 Housing 5602 Housing 5603 Display unit 5604 Display unit 5605 Connection part 5606 Operation key 5801 Housing 5802 Display unit 5803 Audio input section 5804 Audio output section 5805 Operation key 5806 Light-receiving section

Claims

1. a first transistor to an eighth transistor and a first wiring to a fifth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, one of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor is always electrically connected to the third wiring to which a first potential is supplied; the other of the source and the drain of the fourth transistor is always electrically connected to the second wiring; one of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring, one of the source and the drain of the sixth transistor is always electrically connected to the second wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the gate of the eighth transistor is always electrically connected to the fifth wiring; when one of the source or the drain of the sixth transistor is electrically connected to the other of the source or the drain of the fifth transistor through at least a channel formation region of the sixth transistor, a second potential supplied to the second wiring is supplied to the other of the source or the drain of the fifth transistor through at least a channel formation region of the sixth transistor; Semiconductor device.

2. a first transistor to an eighth transistor and a first wiring to a fifth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, one of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor is always electrically connected to the third wiring to which a first potential is supplied; the other of the source and the drain of the fourth transistor is always electrically connected to the second wiring; one of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring, one of the source and the drain of the sixth transistor is always electrically connected to the second wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the gate of the eighth transistor is always electrically connected to the fifth wiring; when one of the source or the drain of the fifth transistor is electrically connected to the other of the source or the drain of the sixth transistor through at least a channel formation region of the fifth transistor, a potential of a clock signal supplied to the fourth wiring is supplied to the other of the source or the drain of the sixth transistor through at least a channel formation region of the fifth transistor; Semiconductor device.

3. a first transistor to an eighth transistor and a first wiring to a fifth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, one of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor is always electrically connected to the third wiring to which a first potential is supplied; the other of the source and the drain of the fourth transistor is always electrically connected to the second wiring; one of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring, one of the source and the drain of the sixth transistor is always electrically connected to the second wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the gate of the eighth transistor is always electrically connected to the fifth wiring; when one of the source or the drain of the sixth transistor is electrically connected to the other of the source or the drain of the fifth transistor through at least a channel formation region of the sixth transistor, a second potential supplied to the second wiring is supplied to the other of the source or the drain of the fifth transistor through at least a channel formation region of the sixth transistor, a period in which a potential applied to the other of the source and the drain of the first transistor is different from a potential applied to the fourth wiring; Semiconductor device.

4. a first transistor to an eighth transistor and a first wiring to a fifth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, one of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor is always electrically connected to the third wiring to which a first potential is supplied; the other of the source and the drain of the fourth transistor is always electrically connected to the second wiring; one of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring, one of the source and the drain of the sixth transistor is always electrically connected to the second wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the gate of the eighth transistor is always electrically connected to the fifth wiring; when one of the source or the drain of the fifth transistor is electrically connected to the other of the source or the drain of the sixth transistor through at least a channel formation region of the fifth transistor, a potential of a clock signal supplied to the fourth wiring is supplied to the other of the source or the drain of the sixth transistor through at least a channel formation region of the fifth transistor, a period in which a potential applied to the other of the source and the drain of the first transistor is different from a potential applied to the fourth wiring; Semiconductor device.

5. In any one of claims 1 to 4, The first transistor to the eighth transistor all have the same polarity. Semiconductor device.

Images