Recording element substrate, liquid discharge head and recording device

Abstract

To alleviate constraint on the design of a recording element substrate.SOLUTION: A recording element substrate includes: a nozzle for discharging liquid; an energy generation part for generating energy for discharging the liquid from the nozzle; a latch input terminal 305 for inputting a latch signal; a data input terminal 306 for inputting a data signal for controlling a driving state of the energy generation part; a heat pulse generation circuit 313 for generating a heat pulse signal for determining a driving timing of the energy generation part; a latch circuit 311 to which the data signal is transferred from the data input terminal 306, and that inputs the data signal at a timing when the latch signal is input; a driving element 315 to which the heat pulse signal and the data signal are transferred, and that outputs a driving signal for determining the driving state of the energy generation part, by a logic product of the heat pulse signal and the data signal; and a delay circuit 312 for delaying the latch signal and inputting the delayed latch signal to the latch circuit 311.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a recording element substrate, a liquid ejection head including the recording element substrate, and a recording apparatus including the liquid ejection head.

Background Art

[0002] As a recording apparatus such as a printing apparatus, a configuration including a liquid ejection head in which a plurality of nozzles for ejecting a liquid such as an ink droplet are arranged is typical. For example, when a print job is input from an external device (such as a personal computer) to the recording apparatus, print data corresponding to the print job is transmitted to the liquid ejection head. Then, the liquid ejection head drives the recording element substrate based on the transmitted print data. And the recording element substrate of the liquid ejection head ejects a liquid to perform a printing operation.

[0003] Patent Document 1 discloses a technique for converting serial data sent at a constant period into parallel data with respect to a circuit provided on a recording element substrate, the circuit driving a plurality of heater elements based on serial data input from the outside. Further, Patent Document 1 discloses a technique for transferring parallel data to a register at the timing of a latch signal, and a technique for driving a heater by switching the conduction / non-conduction state of the heater based on a specific bit of the register and the value of a heat pulse.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In Patent Document 1, in order to correctly drive the conduction / non-conduction state of the heater according to the timing (pattern) of the heat pulse signal, it is necessary to appropriately set the update timing of the register with respect to the period of the heat pulse signal. For example, if the value of the register changes negatively during the period when the heat pulse signal is active, the heater will enter the non-conduction state, resulting in a deviation between the pattern of the heat pulse signal and the conduction / non-conduction state of the heater, and the heater cannot be driven as intended. In the case of a recording element substrate with such a configuration, in order to avoid the above problems, the degree of freedom in designing the switching timing of the latch signal and the switching timing of the heat pulse signal is reduced, which may become a design constraint for the recording element substrate.

[0006] In order to solve the above problems, an object of the present invention is to relax the design constraints of the recording element substrate.

Means for Solving the Problems

[0007] In order to achieve the above object, the recording element substrate of the present invention is a recording element substrate that discharges liquid toward a recording medium to record an image, a nozzle for discharging the liquid, an energy generation unit that generates energy for discharging the liquid from the nozzle, a latch input terminal for inputting a latch signal, a data input terminal for inputting a data signal for controlling the driving state of the energy generation unit, a heat pulse generation circuit that generates a heat pulse signal for determining the driving timing of the energy generation unit, a latch circuit that inputs the data signal from the data input terminal and inputs the data signal at the timing when the latch signal is input, a driving element to which the heat pulse signal is input from the heat pulse generation circuit and the data signal is input from the latch circuit, and outputs a driving signal for determining the driving state of the energy generation unit by the logical product of the heat pulse signal and the data signal A delay circuit that delays the latch signal and inputs it to the latch circuit, characterized by comprising.

Advantages of the Invention

[0008] According to the present invention, design constraints of the recording element substrate can be relaxed.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0010] Hereinafter, with reference to the drawings, embodiments for carrying out the present invention will be illustratively and in detail described based on examples. Note that the dimensions, materials, shapes, relative arrangements, etc. of the components described in this embodiment should be appropriately changed according to the configuration of the apparatus to which the invention is applied and various conditions. That is, the scope of the present invention is not intended to be limited to the following embodiments.

[0011] <First Embodiment> (Printing Device 101) First, the printing device 101 according to the first embodiment will be described. FIG. 1(a) is a perspective view of the printing device 101 according to the first embodiment. The printing device 101 is a recording device including a main body 102, a paper feed tray 103, a print head 104, and a paper discharge tray 105.

[0012] A medium, which is a printing target (recording medium) on which a printing operation (recording operation) is performed by the printing device 101, is stored in the paper feed tray 103 and supplied from the paper feed tray 103 to the main body 102 along with the printing operation. In the main body 102, the medium is conveyed at a determined time and speed pattern toward the paper discharge tray 105. At this time, while the print head 104 built in the main body 102 reciprocates in the direction of arrow E orthogonal to the conveyance direction of the medium, droplets (ink) are applied to the medium at appropriate timing, thereby executing the printing operation. The medium on which printing is completed is conveyed to the paper discharge tray 105, and the printing operation is completed.

[0013] The printing device 101 according to the first embodiment is a printer generally called a serial head type, but the present invention is also applicable to a recording device such as a line head type printer. The line head type printer is different from the serial head type printer in that the print head is substantially fixed to the main body of the printing device and does not involve reciprocating movement of the head during the printing operation.

[0014] FIG. 1(b) is a block diagram showing the circuit configuration inside the print head 104. The print head 104 is a liquid ejection head including a head substrate 106 and a recording element substrate 107 that ejects liquid onto a medium to record an image. The head substrate 106 and the recording element substrate 107 are connected to each other by signal wirings and power supply wirings, and power and signals are supplied from the head substrate 106 side to the recording element substrate 107. The power supplies (potentials) supplied from the head substrate 106 to the recording element substrate 107 include a power supply Vh, a reference potential GNDh, a power supply Vgate, a power supply VDD, and a reference potential VSS. Also, the signals supplied from the head substrate 106 to the recording element substrate 107 include a signal LT as a latch signal, a signal CLK as a clock signal, and a signal DATA as a data signal.

[0015] The power supply Vh is a heater power supply for ejecting droplets in the recording element substrate 107, and is, for example, a power supply of 24V to 32V. The reference potential GNDh supplies the reference potential of the power supply Vh. The power supply Vgate is a gate power supply for a transistor element that drives the heater, and is, for example, a power supply of 5V. The power supply VDD is a power supply for operating a drive circuit in the recording element substrate, and is, for example, a power supply of 3.3V. The reference potential VSS is the reference potential of the power supply Vgate and the power supply VDD.

[0016] The signals LT, CLK, and DATA are signals for controlling the operation and operation timing of the recording element substrate 107. In FIG. 1(b), the above power supplies and signals are each illustrated by a single wiring, but for example, for power supply wirings, etc., a plurality of wirings of the same type may be provided for the purpose of ensuring the current capacity.

[0017] (Recording element substrate 107) Next, with reference to FIGS. 2(a) to 2(d), the configuration of the recording element substrate 107 will be described. Among the components of the recording element substrate 107, the arrangement of circuits and elements, the structure of the elements, and the operating principle of the elements will be described in particular detail.

[0018] Fig. 2(a) is an explanatory diagram showing the circuit arrangement and the arrangement positions of elements on the recording element substrate 107. The element substrate 201 is the basic structure constituting the recording element substrate 107. The circuits and elements formed on the recording element substrate 107 are formed on the element substrate 201. The element substrate 201 is provided with ejection elements 202, column circuits 203, end circuits 204, pads 205, etc.

[0019] The ejection element 202 is an element that ejects droplets necessary for the printing operation. Although details will be described later, the ejection element 202 is composed of one heater and one nozzle, and forms the minimum element of the ejection function. A plurality of ejection elements 202 are formed on the element substrate 201 and arranged in an array (columnar) shape. Hereinafter, a group of the horizontal array arrangement in Fig. 2(a) will be described as a column.

[0020] The column circuit 203 is arranged along the column of the ejection elements 202. The column circuit 203 includes drive elements for driving the ejection elements 202 and circuit elements associated therewith. The end circuit 204 includes a signal generation circuit for controlling the recording element substrate 107. Signals for connecting a power supply (potential) and control signals to the recording element substrate 107 are connected to the pads 205.

[0021] Fig. 2(b) is a top view for explaining the structure of the ejection element 202, showing three ejection elements 202. Fig. 2(c) is a cross-sectional view taken along the line A-A of Fig. 2(b). The element substrate 201 and the top plate 206 are arranged to face each other with a certain space in the direction perpendicular to the paper surface of Fig. 2(b). One ejection element 202 includes one heater 207 and one nozzle 208. The heater 207 is formed on the element substrate 201 and current is supplied by a drive circuit (not shown). The nozzle 208 is an opening provided in the top plate 206 and is arranged at a position overlapping the heater 207 when viewed in the facing direction of the element substrate 201 and the top plate 206. In the space formed by the element substrate 201 including the inside of the nozzle 208 and the top plate 206, liquid 209 is supplied from a droplet supply path (not shown). And the said space is filled with the liquid 209.

[0022] FIG. 2(d) is a diagram for explaining the operating principle of the ejection element 202, and shows how droplets 211 are ejected from the nozzle 208 in the A-A cross section of FIG. 2(b). As described above, a current is supplied to the heater 207, and the heater 207 generates heat due to the current, forming a foaming portion 210 above the heater 207. The liquid 209 that filled the periphery of the foaming portion 210 is pushed out near the nozzle 208, and a part of it is ejected outside the recording element substrate 107 to form the droplets 211. The droplets 211 eventually reach the medium and form an image. That is, the heaters 207 having the same number as the nozzles 208 constitute an energy generation portion that generates the energy for ejecting the droplets 211 (liquid 209) from the nozzles 208.

[0023] (Circuit configuration of the recording element substrate 107) Next, with reference to FIG. 3, the circuit formed on the recording element substrate 107 will be described. FIG. 3 is a diagram showing the configuration of the circuit of the recording element substrate 107. In FIG. 3, a configuration having n ejection elements 202, that is, n heaters 207 is shown as an example.

[0024] The heater 207 is equivalent to a resistance element. FIG. 3 shows three heaters 207 and their drive circuits. Hereinafter, among the three heaters 207, the one shown on the right side of FIG. 3 will be referred to as the heater 207n, and n will be appropriately added to the elements corresponding to the heater 207n and described separately as necessary.

[0025] One terminal of the heater 207 is connected to the Vh pad 301 (205). Here, the notation (205) appended after the symbol of the pad means that the Vh pad 301 is one of the pads 205 in FIG. 2(a). The Vgate pad 302, GNDh pad 303, pad 304, pad 305, pad 306, and pad 307 described below are also one of the pads 205, and (205) is appended after the symbol in FIG. 3. In the following description, for the sake of simplicity of notation, the appended part will be omitted.

[0026] The other terminal of the heater 207 is connected to the transistor 308. The transistor 308 is configured to enable a switching operation of switching between a conductive state in which the heater 207 and the GNDh pad 303 are electrically connected and a non-conductive state in which they are not electrically connected according to the potential of the terminal P4 which is the gate terminal. More specifically, the heater 207 and the GNDh pad 303 are in the non-conductive state when the terminal P4 is near the reference potential VSS, and are in the conductive state when the terminal P4 is near the same potential (5V) as the Vgate pad 302. In the conductive state, a heater current flows from the Vh pad 301 toward the GNDh pad 303 in the heater 207.

[0027] The pad 306 is a data input terminal for the serial data D as a data signal, and the pad 307 is a clock input terminal for the signal CLK. The serial data D input from the pad 306 is input in synchronization with the rising edge and the falling edge of the signal CLK. This serial data D is the same as the signal DATA in FIG. 1. In the shift register 310, the serial data D is shifted 1 bit to the left direction in FIG. 3 at the timings of the rising edge and the falling edge of the signal CLK.

[0028] The output-side terminal of the shift register 310 is connected to the register 311. A pad 305 which is a latch input terminal to which the signal LT is input is connected to the register 311 via a delay element 312 disposed within the end circuit 204. The value of the shift register 310 is copied to the register 311 at the timing when the rising edge of the signal LT delayed by the delay element 312 reaches the register 311. Hereinafter, this copying operation is expressed as "update of the register value". In other words, the signal CLK and the serial data D are transferred to the shift register 310, and the shift register 310 transfers the serial data D to the register 311 in synchronization with the signal CLK. Then, the register 311 which is a latch circuit transfers the copied value (serial data D) of the shift register 310 at the timing when the signal LT is transferred.

[0029] In the end loop 204, in addition to the delay element 312, a heat pulse generation circuit 313 is provided. The heat pulse generation circuit 313 is connected to a plurality of AND elements 315, and the generated heat pulse signal (hereinafter referred to as signal HE) is transferred to the AND elements 315. The signal HE is a signal that determines the driving timing of the heater 207. Heat delay elements 314 are dispersedly arranged in the wiring path from the heat pulse generation circuit 313 to the AND elements 315, and the signal HE reaches the AND elements 315 on the right side from the left side of the drawing while increasing the delay. With such a configuration, the signal HE is transferred to the plurality of AND elements 315 at different timings from each other.

[0030] Details will be described later with reference to FIG. 5. When both the signal HE input to the terminal P2 of the AND element 315 and the value of the register 311 input to the terminal P3 are active (3.3V), a voltage of 3.3V is input to the level converter 309 by the AND element 315. At this time, the voltage of the terminal P4 of the transistor 308 becomes around 5V, and the transistor 308 becomes conductive. That is, the AND element 315 is a driving element that outputs a driving signal that determines the driving state of the heater 207 by the logical product of the signal HE and the serial data D.

[0031] The level converter 309 is provided between the transistor 308 and the AND element 315. The level converter 309 has the effect of reducing the on-resistance of the transistor 308 by increasing the voltage of the terminal P4 of the transistor 308.

[0032] (Circuit configuration of the delay element 312) Next, with reference to FIG. 4, the circuit configuration of the delay element 312 will be described. FIG. 4 is a circuit diagram for explaining the configuration of the delay element 312. The delay element 312 is a delay circuit including a delay element 401 configured by connecting a plurality of inverters 402 in series. In FIG. 4, two types of circuit symbols are used for the inverter 402 which is an inverter element, but since the circuits are the same, the same name and reference numeral are assigned to each circuit symbol. The signal LT input from the pad 305 is input to the first stage of the inverter 402. There is a finite time required for signal transmission between the input and output of the inverter 402. By combining these in series in multiple stages, a desired delay time can be obtained. The output of the delay element 312 is connected to the terminal P1.

[0033] (Operation of the recording element substrate 107) Next, with reference to FIG. 5, the operation of the recording element substrate 107 will be described. FIG. 5 is a timing diagram showing the operation of the recording element substrate 107. In the first embodiment, the heater 207 is driven by BLK driving. In BLK driving, the heaters 207 are grouped (BLK divided) electrically in advance, and time-division driving is performed in which the driving of each BLK is allocated within one column period (a period in which all the heaters 207 on the recording element substrate 107 can be driven once). Taking a specific example, one column period is about 42 microseconds, which corresponds to a frequency of 24 kHz. For example, in 16-time division driving in which the driving of the heater 207 once is divided into 16 groups, the BLK in the BLK-divided period is approximately 1 / 16 of one column, which is 2 to 3 microseconds.

[0034] Each period (section) based on the rising edge of the signal LT is defined as the period BLK. That is, the period from the rising edge of the signal LT to the next rising edge of the rising edge is defined as the period BLK. Hereinafter, as also shown in FIG. 5, when distinguishing and explaining a plurality of periods BLK, each period BLK is numbered. The period BLK is for the recording element substrate 10 Define the start point of the periodic operation of 7. A series of operations of the recording element substrate 107 in each period will be described as the operation of one period BLK. In FIG. 5, as an example, the operations of period BLK0, period BLK1 after period BLK0, and period BLK2 after period BLK1 are shown.

[0035] Hereinafter, with reference to FIG. 5, taking the heater 207n provided at the right end of FIG. 3 as an example, the operation of the recording element substrate 107 will be described. Note that the heaters 207 other than the heater 207n are also driven in the same manner. FIG. 5 shows the signal LT, the signal HE, and the states of the signals input to the terminals P1 to P5. Each signal is shown as 1 when active and 0 when inactive. Further, FIG. 5 shows the signal CLK, the serial data D, and the state of the register 311.

[0036] When the recording element substrate 107 is driven, following the rising of the signal LT at time t0, the signal CLK and the serial data D are input. Hereinafter, the set of serial data D input in period BLK0 will be denoted as serial data D1. Similarly, that input in period BLK1 will be denoted as serial data D2, that input in period BLK2 will be denoted as serial data D3, and that input in the period BLK immediately before period BLK1 will be denoted as serial data D0.

[0037] The serial data D1 includes the data d31. The data d31 determines the value of the terminal P3 which is the input terminal of the AND element 315n shown in FIG. 3. Note that the data arrangement in the serial data D1 described here is an example for explanation, and other arrangements may also be adopted. Similarly, the serial data D0 includes the data d30, and the serial data D2 includes the data d32.

[0038] In period BLK0, the data of all the shift registers 310 is determined after the data d31 is input. After the data of the shift register 310 is determined, the input of the signal CLK is stopped. When the signal CLK stops, the preparation for updating the register 311 is completed.

[0039] The update timing of register 311n is the rising timing of the signal at terminal P1 after a delay time TdLt has elapsed since the rising edge of signal LT. At time t1, when the signal at terminal P1 rises, register 311n is updated and the value of register 311n changes from serial data D0 to serial data D1. With such a configuration, serial data D is transferred from register 311 to AND element 315 when signal HE is 0 (inactive).

[0040] During period BLK0, data d31 is the last to be input among serial data D1. Therefore, the value of data d31 is held in the shift register 310n closest to the input side. When register 311 is updated at time t1, data d31 is transferred to register 311n that determines the value of terminal P3 during period BLK1. From the relationship that the value of register 311 during a certain period BLK is determined by the serial data D of the previous BLK period, data d30 of serial data D0 determines the state of terminal P3 during period BLK0. Similarly, serial data D1 determines the state of terminal P3 during period BLK1, and serial data D2 determines the state of terminal P3 during period BLK2. Figure 5 shows an example where d30 = 1 (active), d31 = 0 (inactive), and d32 = 1 (active). At this time, the state of terminal P3 changes to 1 ( active) during BLK0, 0 (inactive) during BLK1, and 1 (active) during BLK2.

[0041] As described above, signal HE is generated by heat pulse generation circuit 313 and transmitted to a plurality of AND elements 315 while passing through a plurality of heat delay elements 314. Among the transmission paths of signal HE, the signal HE that has passed through the most heat delay elements 314 is transmitted to terminal P2 of AND element 315n, which is arranged farthest from heat pulse generation circuit 313. Therefore, the delay time of signal HE transmitted to terminal P2 of AND element 315n is the largest, and that delay time is time Tdh.

[0042] Regarding the conduction operation of the heater 207, the current at the terminal P5 of the heater 207n will be taken as an example for explanation. As described above, the heater 207n conducts when both the states of the terminals P2 and P3 of the AND element 315n are active (3.3V in the circuit diagram and 1 in the timing diagram). Therefore, for example, during the period BLK0, current flows through the terminal P5 only during the period when the terminal P3 becomes active within the timing when the terminal P2 is active, that is, the timing when the delayed signal HE is 1.

[0043] Since the signal input to the terminal P3 has the function of selecting whether to be driven or not based on the signal HE depending on its state, it can be rephrased as a heater selection signal. In order to normally perform the printing operation of the recording element substrate 107, the selected heater 207 needs to be faithfully driven in response to the state change of the signal HE. In particular, in recent years, due to the demand for speeding up the printing operation of the printing apparatus, the update timing cycle of the register and the conduction / non - conduction state switching cycle of the heater tend to be set shorter. That is, speeding up the printing operation increases the likelihood of a deviation occurring between the pattern of the signal HE and the conduction / non - conduction state of the heater. In the first embodiment, the signal input to the terminal P3 is the data d3k (k = 0, 1, 2,...) updated at the timing of the signal LT delayed by the delay element 312. With such a configuration, in preventing the occurrence of such a deviation, the design constraints on the timing of the signal LT and the timing of the signal HE are relaxed. Hereinafter, the operation of the recording element substrate 107 of the first embodiment will be described in more detail while comparing with the operation of the comparative example.

[0044] Next, with reference to FIG. 6, the operations of the recording element substrate 107 of the first embodiment and the comparative example will be described while making a comparison. FIG. 6 is a timing diagram for explaining the operations of the first embodiment and the comparative example. In FIG. 6, signals input to terminals P2, P3, and P4 as signals related to the column circuit 203 of the first embodiment, and the states of the registers 311 are shown. Also, in FIG. 6, signals input to terminals P2, P3c, and P4c as signals related to the column circuit 203c (not shown) of the comparative example, and the states of the register 311c are shown. That is, in the first embodiment and the comparative example, the signals input to terminal P2 exhibit similar behavior. Also, the signal LT and the signals input to terminal P1 exhibit similar behavior. Also, the serial data D in each period BLK is the same as that shown in FIG. 5.

[0045] The register 311c represents the time change of the register 311 when the signal LT is input without passing through the delay element 312. When the signal LT is not delayed, the rising timing of the signal LT becomes the update timing of the register 311c. And at that timing, the value of the register 311c changes from the serial data D0 to the serial data D1, and from the serial data D1 to the serial data D2. And with the change in the value of the register 311c, the state of the terminal P3c changes at the rising timing of the signal LT.

[0046] At this time, the terminal P4c whose state changes in synchronization with the output of the AND element 315n has a waveform as shown in FIG. 6. In FIG. 6, the timings from when the signal input to the terminal P3c becomes active to when the signal input to the terminal P2 becomes inactive are shown as intervals T60, T61, and T62. The interval T60 is the interval of the period BLK0, the interval T61 is the interval of the period BLK1, and the interval T62 is the interval of the period BLK2.

[0047] In the comparative example, in intervals T60 and T62, before the input signal (delayed signal HE) of terminal P2 falls, the input signal of terminal P3c rises, and the input signal of terminal P4c switches to the 1 (active) state. On the other hand, in interval T61, before the input signal of terminal P2 falls, the input signal of terminal P3c falls, and the input signal of terminal P4c becomes 0 (inactive) state. Therefore, in intervals T60, T61, and T62, the heater 207 does not change in synchronization with the change in the state of the signal HE input to terminal P2. Such a situation should be avoided because the heater 207 cannot be driven as intended. Also, such problems are more likely to occur as the delay of the signal HE increases.

[0048] On the other hand, in the first embodiment, the input signal of terminal P3 is delayed by the delay element 312 and input. And in each period BLK, the rise of the input signal of terminal P3 is earlier than the rise of the input signal of terminal P2, and the fall of the input signal of terminal P3 is later than the fall of the input signal of terminal P2. And the input signal of terminal P4, which is the output of the AND element 315n, changes its state in synchronization with the input signal of terminal P2. Thus, in the first embodiment, due to the delay in the update timing of the register 311, it is possible to appropriately set the timing of the signal HE and the register update timing. As a result, in all heaters 207, the occurrence of the above-mentioned problems can be suppressed.

[0049] From the above, according to the configuration of the first embodiment, it is possible to adjust the relationship between the timing of the LT signal and the register update timing according to the delay time of the LT signal, and the direct timing constraint between the LT signal and the HE pulse is relaxed. As a result, the degree of freedom in the design of the HE pulse and the LT timing increases, and the design constraints on the recording element substrate can be relaxed.

[0050] In this example, the ejection element 202 is described as being configured by the heater 207. However, even when it is configured by a piezo element, the same problems are assumed, and the same effects can be obtained by the present invention.

[0051] <Second Embodiment> Next, a second embodiment according to the present invention will be described. The second embodiment differs from the first embodiment in the configuration of the delay element that delays the signal LT. Hereinafter, in the configuration of the second embodiment, only the points different from the configuration of the first embodiment will be described, and the same components as those in the configuration of the first embodiment will be denoted by the same reference numerals and the description thereof will be omitted.

[0052] (Circuit Configuration of Recording Element Substrate 107) Referring to FIG. 7, the circuit formed on the recording element substrate 107 according to the second embodiment will be described. FIG. 7 is a diagram showing the configuration of the circuit of the recording element substrate 107 according to the second embodiment. Hereinafter, the circuit configuration of the recording element substrate 107 according to the second embodiment will be described in terms of the difference from the circuit according to the first embodiment shown in FIG. 3.

[0053] In the end circuit 204 of the recording element substrate 107 according to the second embodiment, in addition to the heat pulse generation circuit 313, a delay element 701 is provided. The signal LT input from the pad 305 is input to the delay element 701. Also, the signal CLK of the pad 307 is input to the delay element 701, and the output of the delay element 701 is connected to the terminal P1.

[0054] (Delay Element 701) Next, referring to FIGS. 8(a) and 8(b), the configuration and operation of the delay element 701 will be described. FIG. 8(a) is an explanatory diagram of the circuit configuration of the delay element 701. FIG. 8(b) is an explanatory diagram of the operation of the delay element 701.

[0055] The delay element 701 is a delay circuit including an edge detection circuit 702, a counter 703, a numerical comparator 704, and a constant Nck. The signal LT input from the pad 305 has its rising edge detected by the edge detection circuit 702. The rising edge of the signal LT is input to the counter 703 and used as a reset signal for the counter 703.

[0056] The signal CLK of the pad 307 is input to the counter 703. The counter 703 is the letter Each time the rising or falling edge of signal CLK is input, the count value is incremented by one. The counter 703 is composed of, for example, a plurality of flip-flop circuits.

[0057] The numerical comparator 704 compares the value of the counter 703 with the numerical value Nck, and outputs state 1 when the respective values do not match each other, and outputs state 0 when they match. Then, the numerical comparator 704 is connected to terminal P1, and the output of the numerical comparator 704 is input to terminal P1.

[0058] With such a configuration, in the second embodiment, the delay element 701 is configured as a logic circuit whose output state changes with the signal LT and the signal CLK as inputs. And the signal input to terminal P1 is used as the update signal of the register 311. That is, in the second embodiment, the value of the register 311 is updated with the signal CLK as a trigger.

[0059] From the above, also in the configuration of the second embodiment, it is possible to adjust the relationship between the timing of the LT signal and the register update timing by the delay time of the LT signal, and the direct timing constraint between the LT signal and the HE pulse can be relaxed. As a result, the degree of freedom in the design of the HE pulse and the LT timing increases, and the design constraints on the recording element substrate can be relaxed.

[0060] The heat pulse generation circuit 313 of the end circuit 204 is generally configured using a digital circuit. Therefore, in the second embodiment in which the delay element 701 is configured by a digital circuit, the end circuit 204 including the heat pulse generation circuit 313 and the delay element 701 can be configured with one technology. Furthermore, in the second embodiment, by changing the numerical value Nck, the delay time TdLt of the signal LT can be easily adjusted.

[0061] In the second embodiment, the circuit of the delay element 701 includes a counter circuit, but it may be configured to include a flip-flop circuit that uses the signal CLK as an update signal. Further, in the second embodiment, the numerical value Nck is built into the delay element 701, but the configuration is not limited to this. For example, the numerical value Nck may be incorporated into a part of the serial data D and may be settable from outside the recording element substrate 107.

[0062] <Third Embodiment> Next, a third embodiment of the present invention will be described. In the third embodiment, the configuration of the delay element that delays the signal LT is different from that of the first embodiment. Hereinafter, only the differences from the configuration of the first embodiment in the configuration of the third embodiment will be described. In the configuration of the third embodiment, the same components as those in the configuration of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0063] (Circuit Configuration of Recording Element Substrate 107) With reference to FIG. 9, the circuit formed on the recording element substrate 107 according to the third embodiment will be described. FIG. 9 is a diagram showing the configuration of the circuit of the recording element substrate 107 according to the third embodiment. Hereinafter, the difference between the circuit configuration of the recording element substrate 107 according to the second embodiment and the circuit according to the first embodiment shown in FIG. 3 will be described.

[0064] In the end circuit 204 of the recording element substrate 107 according to the second embodiment, in addition to the heat pulse generation circuit 313, a delay element 901 is provided. The signal LT input from the pad 305 is input to the delay element 901. The signal CLK of the pad 307 is input to the delay element 901, and the output of the delay element 901 is connected to the terminal P1.

[0065] (Delay Element 901) Next, with reference to FIGS. 10(a) and (b), the configuration and operation of the delay element 901 will be described. FIG. 10(a) is an explanatory diagram of the circuit configuration of the delay element 901. FIG. 10(b) is an explanatory diagram of the operation of the delay element 901. element 901.

[0066] The delay element 901 has a circuit configuration in which the delay element 701 according to the second embodiment and the delay element 312 according to the first embodiment are connected in series. The rising edge of the signal LT input from the pad 305 is delayed based on the numerical value Nck and output to the terminal P6. The signal input to the terminal P6 is transferred to the first stage of the delay element 401 composed of a series connection of a plurality of inverters 402. By the delay element 401, the rising edge of the signal LT increases the delay amount by the time Tdinv with respect to the terminal P6. With such a configuration, in the third embodiment, the delay element 901 is configured as a logic circuit whose output state changes with the signal LT and the signal CLK as inputs.

[0067] As described above, also in the configuration of the third embodiment, the relationship between the timing of the LT signal and the register update timing can be adjusted by the delay time of the LT signal, and the direct timing constraint between the LT signal and the HE pulse can be relaxed. As a result, the degree of freedom in designing the HE pulse and the LT timing increases, and the design constraints on the recording element substrate can be relaxed.

[0068] Also, in the configuration of the third embodiment, the delay time of the signal LT can be roughly adjusted by the numerical value Nck with respect to the period of the signal CLK, and finely adjusted by adjusting the number of stages of the inverter. Since the numerical value Nck is determined by the connection destination of the circuit wiring, the dependency between the numerical value Nck and the circuit area is small. That is, in the third embodiment, it is possible to enable fine adjustment of the delay time and reduce the dependency between the magnitude of the delay time and the circuit area compared to the case where the delay of the signal LT is configured only by inverters.

[0069] The disclosure of this embodiment includes the following configurations. (Configuration 1) A recording element substrate that discharges liquid toward a recording medium to record an image, a nozzle that discharges liquid, an energy generation unit that generates energy for discharging liquid from the nozzle, a latch input terminal for inputting a latch signal, a data input terminal for inputting a data signal for controlling the driving state of the energy generation unit, A heat pulse generation circuit that generates a heat pulse signal for determining the driving timing of the energy generation unit; A latch circuit that receives the data signal from the data input terminal and inputs the data signal at the timing when the latch signal is input; A drive element that receives the heat pulse signal from the heat pulse generation circuit and the data signal from the latch circuit, and outputs a drive signal for determining the drive state of the energy generation unit by a logical product of the heat pulse signal and the data signal; A delay circuit that delays the latch signal and inputs it to the latch circuit; A recording element substrate comprising the above. (Configuration 2) The recording element substrate according to Configuration 1, wherein the drive element outputs the drive signal so as to drive the energy generation unit when both the heat pulse signal and the data signal are active. (Configuration 3) The recording element substrate according to Configuration 1 or 2, wherein the data signal is input to the drive element when the heat pulse signal is inactive. (Configuration 4) Comprising a plurality of the nozzles; The recording element substrate according to any one of Configurations 1 to 3, wherein the energy generation unit includes the same number of heaters as the nozzles. (Configuration 5) The same number of drive elements as the heaters; Comprising a plurality of heat delay elements that delay the heat pulse signal and input it to the drive element, and The recording element substrate according to Configuration 4, wherein the timings at which the heat pulse signal is input to the plurality of drive elements are different from each other. (Configuration 6) A clock input terminal for inputting a clock signal; A shift register that receives the clock signal and the data signal and inputs the data signal to the latch circuit in synchronization with the clock signal; A recording element substrate according to any one of Configurations 1 to 5, characterized by comprising (Configuration 7) A recording element substrate according to any one of Configurations 1 to 6, characterized in that the delay circuit includes a delay element configured by connecting a plurality of inverter elements in series. (Configuration 8) Comprising a clock input terminal for inputting a clock signal, A recording element substrate according to any one of Configurations 1 to 6, characterized in that the delay circuit is a logic circuit whose output state changes with the latch signal and the clock signal as inputs. (Configuration 9) A recording element substrate according to Configuration 8, characterized in that the delay circuit includes a counter whose count value is increased in response to the input of the clock signal and reset in response to the input of the latch signal. (Configuration 10) A recording element substrate according to Configuration 9, characterized in that the delay circuit includes a delay element configured by connecting a plurality of inverter elements in series. (Configuration 11) A recording element substrate according to Configuration 8, characterized in that the delay circuit includes a flip-flop circuit using the clock signal as an update signal. (Configuration 12) A liquid ejection head characterized by comprising a recording element substrate according to any one of Configurations 1 to 11. (Configuration 13) A recording apparatus characterized by comprising the liquid ejection head according to Configuration 12 and ejecting liquid onto a recording medium by the liquid ejection head to record an image.

Explanation of Reference Numerals

[0070] 107... recording element substrate, 208... nozzle, 305... pad (latch input terminal), 306... pad (data input terminal), 311... register (latch circuit), 312... delay element (delay circuit), 313... heat pulse generation circuit, 315... AND element (drive element), D... serial data (data signal), HE... heat pulse signal, LT... latch signal

Claims

1. A recording element substrate that discharges a liquid toward a recording medium to record an image, a nozzle that discharges the liquid, an energy generation unit that generates energy for discharging the liquid from the nozzle, a latch input terminal to which a latch signal is input, a data input terminal to which a data signal for controlling the driving state of the energy generation unit is input, a heat pulse generation circuit that generates a heat pulse signal for determining the driving timing of the energy generation unit, a latch circuit that inputs the data signal when the data signal is input from the data input terminal and the latch signal is input, A driving element to which the heat pulse signal is input from the heat pulse generation circuit and the data signal is input from the latch circuit, and outputs a driving signal for determining the driving state of the energy generation unit by a logical product of the heat pulse signal and the data signal, a delay circuit that delays the latch signal and inputs it to the latch circuit, A recording element substrate, characterized by comprising the above.

2. The recording element substrate according to claim 1, wherein the driving element outputs the driving signal so as to drive the energy generation unit when both the heat pulse signal and the data signal are active.

3. The recording element substrate according to claim 1, wherein the data signal is input to the driving element when the heat pulse signal is inactive.

4. Comprising a plurality of the nozzles, The recording element substrate according to claim 1, wherein the energy generation unit includes the same number of heaters as the nozzles.

5. The same number of the driving elements as the heaters, A plurality of heat delay elements that delay the heat pulse signal and input it to the drive element. The recording element substrate according to claim 4, wherein the timings at which the heat pulse signal is input to the plurality of drive elements are different from each other.

6. A clock input terminal for inputting a clock signal. A shift register into which the clock signal and the data signal are input, and the data signal is input to the latch circuit in synchronization with the clock signal. The recording element substrate according to claim 1, comprising:

7. The delay circuit includes a delay element configured by connecting a plurality of inverter elements in series. The recording element substrate according to claim 1.

8. A clock input terminal for inputting a clock signal. The delay circuit is a logic circuit whose output state changes with the latch signal and the clock signal as inputs. The recording element substrate according to claim 1.

9. The delay circuit includes a counter whose count value is increased in response to the input of the clock signal and reset in response to the input of the latch signal. The recording element substrate according to claim 8.

10. The delay circuit includes a delay element configured by connecting a plurality of inverter elements in series. The recording element substrate according to claim 9.

11. The delay circuit includes a flip-flop circuit using the clock signal as an update signal. The recording element substrate according to claim 8.

12. A liquid ejection head comprising the recording element substrate according to any one of claims 1 to 11.

13. A recording apparatus comprising the liquid ejection head according to claim 12, wherein liquid is ejected onto a recording medium by the liquid ejection head to record an image.

Images