Semiconductor device

Abstract

To suppress deterioration and variation in threshold voltage even in the case of contracting a trench mosfet in order to increase a channel density in a trench MOSFET in a vertical channel fin structure.SOLUTION: A semiconductor device 1 includes: a plurality of trenches 2 that has a long direction in a first direction in a plan view and a short direction in a second direction, and is arranged in the second direction; a first conductive type source region 3 that contains a fin structure separated by the plurality of trenches 2; a second conductive type channel region 5 in the fin structure separated by the plurality of trenches 2; and a second conductive type body region 9. The channel region 5 is connected to the body region 9, and a channel current flows in a vertical direction in the channel region 5. The channel region 5 includes: a first channel region 5A in contact with a lower surface of the source region 3; and a second channel region 5B arranged below the first channel region 5A. The first channel region 5A has a second conductive type impurity density that is higher than that of the second channel region 5B.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As a type of trench MOSFET, a trench MOSFET having a vertical channel fin structure has been proposed.

[0003] FIG. 7 is a perspective view schematically illustrating the structure of a conventional trench MOSFET having a vertical channel fin structure. In FIG. 7, the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are not shown.

[0004] The conventional semiconductor device 1 shown in FIG. 7 has a plurality of trenches 2 that have a longitudinal direction in a first direction and a short side direction in a second direction when viewed in plan and are arranged in a plurality in the second direction. Note that the trench 2 indicated by the dotted line in the cross section in front of FIG. 7 shows a position virtually corresponding to the trench 2 for explaining the positional relationship between the other components and the trench 2.

[0005] The source region 3 of the first conductivity type includes a region having a fin structure in which at least a part is partitioned by a plurality of trenches 2. On the lower surface of the source region 3, a channel region 5 of the second conductivity type having a fin structure partitioned by a plurality of trenches 2 is formed in contact with the source region 3. Below the channel region 5, a JFET region 8 of the first conductivity type is formed, and a body region 9 of the second conductivity type is formed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. Below the JFET region 8, a drift region 10 of the first conductivity type is formed, and below the drift region 10, a drain region 11 of the first conductivity type is formed.

[0006] The conventional semiconductor device 1 shown in FIG. 7 has a gate insulating film disposed inside the trench 2 and a gate electrode including a region at least partially disposed inside the trench 2, and a channel current flows in the longitudinal direction (depth direction) in the channel region 5. Note that the gate electrodes embedded inside the trench 2 are connected to each other outside the trench 2.

[0007] As a patent document related to such a technique, for example, there is Patent Document 1. Although the names and detailed structures of the respective components are different, paragraphs 0048 to 0052, FIGS. 3, and FIGS. 14 to 18 of Patent Document 1 describe a configuration similar to that of FIG. 7 described above.

Prior Art Document

Patent Document

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] According to the structure of the conventional semiconductor device 1 shown in FIG. 7, the number of channels can be increased by reducing the trench pitch and increasing the channel density, so that the on-resistance as seen in the entire semiconductor chip can be reduced.

[0010] However, in the conventional semiconductor device 1 shown in FIG. 7, when the trench pitch is reduced to increase the channel density and the dimension (Fin width WF) in the second direction of the channel region 5 is reduced, depletion layers extending from two gate electrodes sandwiching the channel region 5 are connected inside the channel region 5, and the threshold voltage (Vth) is lower than the intended threshold voltage (Vth) (the threshold voltage (Vth) when the depletion layers are not connected inside the channel region 5). There is also a problem that when the Fin width WF varies due to manufacturing variations in such a case, the threshold voltage (Vth) varies.

[0011] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing a decrease and variation in threshold voltage (Vth) even when the trench pitch is reduced to increase the channel density in a trench MOSFET having a vertical channel fin structure.

Means for Solving the Problem

[0012] To solve the above problems, a semiconductor device of the present invention includes a plurality of trenches having a longitudinal direction in a first direction and a short side direction in a second direction when viewed in plan view, and arranged in a plurality in the second direction, and a source region of a first conductivity type including a region having a fin structure at least partially separated by the plurality of trenches, a channel region of a second conductivity type having a fin structure separated by the plurality of trenches and in contact with the lower surface of the source region, a gate insulating film disposed inside the trench, a gate electrode including a region at least partially disposed inside the trench, a JFET region of the first conductivity type disposed below the channel region, and a body region of the second conductivity type disposed laterally of the JFET region. An end portion of the bottom surface of the plurality of trenches in the first direction is disposed in the body region, the channel region is connected to the body region, a channel current flows vertically in the channel region, the channel region has a first channel region in contact with the lower surface of the source region and a second channel region disposed below the first channel region, and the first channel region is characterized in that the impurity concentration of the second conductivity type is higher than that of the second channel region.

Effects of the Invention

[0013] According to the semiconductor device of the present invention, even when the trench pitch is reduced to increase the channel density, a decrease and variation in threshold voltage (Vth) can be suppressed.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Best Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant descriptions are omitted.

Embodiment

[0016] FIG. 1 is a perspective view of the semiconductor device of Example 1. FIG. 2 is a cross-sectional view taken along line X1-X1' of FIG. 1. FIG. 3 is a cross-sectional view taken along line X2-X2' of FIG. 1. FIG. 4 is a cross-sectional view taken along line Y1-Y1' of FIG. 1. In FIG. 1, the gate electrode 7, the gate insulating film 6, the interlayer insulating film 14, the source electrode 12, and the drain electrode 13 are not shown.

[0017] The semiconductor device 1 of this embodiment includes a plurality of trenches 2, a source region 3 of the first conductivity type, a channel region 5 of the second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of the first conductivity type, a body region 9 of the second conductivity type, a drift region 10 of the first conductivity type, and a drain region 11 of the first conductivity type.

[0018] In this embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example, but it is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0019] The plurality of trenches 2 have a longitudinal direction in a first direction (the direction of X1-X1' in FIG. 1) and a short-side direction in a second direction (the direction of Y1-Y1' in FIG. 1) when viewed in plan view, and are arranged in a plurality in the second direction. Further, although not shown, the trench group composed of the trenches 2 arranged in a plurality in the second direction is also arranged in a plurality in the first direction. Note that the trenches 2 indicated by the dotted lines in the cross section in front of FIG. 1 and the cross-sectional view of FIG. 2 virtually show the positions corresponding to the trenches 2 for explaining the positional relationship between the other components and the trenches 2. The depth of the trench 2 is shallower than the body region 9 and deeper than the channel region 5.

[0020] The width (length in the first direction) of the trench 2 is desirably 0.2 um or more and 0.6 um or less. In this embodiment, the width of the trench 2 is set to 0.5 um. The depth of the trench 2 is desirably 0.6 um or more and 1.2 um or less. In this embodiment, the depth of the trench 2 is set to 1.0 um.

[0021] The source region 3 of the first conductivity type includes a region having a fin structure in which at least a part is separated by a plurality of trenches 2. On the lower surface of the source region 3, a channel region 5 of the second conductivity type having a fin structure separated by a plurality of trenches 2 is formed in contact with the source region 3. Below the channel region 5, a JFET region 8 of the first conductivity type is arranged, and a body region 9 of the second conductivity type is arranged on the side of the JFET region 8. The channel region 5 is connected to the body region 9. Therefore, the width (length in the first direction) of the channel region 5 is the width obtained by subtracting the overlapping width between the trench 2 and the body region 9 from the width (length in the first direction) of the trench 2. Also, the width (length in the first direction) of the channel region 5 is the same as the JFET width WJ which is the width (length in the first direction) of the JFET region 8.

[0022] In this embodiment, the source region 3 has a depth of 0.3 um at the lower surface, and the impurity concentration of the first conductivity type is 1×10 20 cm -3It was set to a certain level. The channel region 5 has a bottom depth set to 0.6 μm. Therefore, the thickness of the channel region 5 is 0.3 μm. The body region 9 can be formed, for example, by ion implantation using aluminum as a P-type impurity. It is desirable that the bottom depth of the body region 9 be 1.2 μm or more and 2.0 μm or less. The impurity concentration of the second conductivity type in the body region 9 was set to about 1×10 18 cm -3 or so.

[0023] Below the JFET region 8, a drift region 10 of the first conductivity type is arranged. The drift region 10 is also arranged below the body region 9. Further, below the drift region 10, a drain region 11 of the first conductivity type with an impurity concentration higher than that of the drift region 10 is arranged.

[0024] The drift region 10 is, for example, an epitaxial layer of SiC formed on an SiC wafer, and desirably contains N-type impurities (nitrogen) in the range of 1×10 14 cm -3 or more and 1×10 17 cm -3 or less. The thickness is desirably 5 μm or more and 100 μm or less. In this embodiment, the concentration was set to 1×10 16 cm -3 and the thickness was set to 10 μm. The breakdown voltage in the off state is determined by the drift region 10. In this embodiment, the breakdown voltage specification is 1200 V. The drain region 11 is, for example, an SiC wafer, and desirably contains N-type impurities (nitrogen) of about 1×10 18 cm -3 or so. The thickness is desirably 50 μm or more and 500 μm or less. In this embodiment, the thickness was set to 150 μm.

[0025] Inside the trench 2, a gate insulating film 6 is arranged. Also, at least a part of the gate electrode 7 is arranged inside the trench 2. Note that the gate electrodes 7 arranged inside the trench 2 are connected to each other outside the trench 2.

[0026] The gate insulating film 6 can use, for example, a film mainly composed of SiO2. In this embodiment, the thickness was set to about 50 nm. It is desirable that nitrogen is introduced near the interface between SiC and SiO2 in order to improve the interface characteristics. The gate electrode 7 can be formed of, for example, polysilicon containing a high concentration of an N-type dopant.

[0027] In the semiconductor device 1 of this embodiment, a channel current flows in the vertical direction (depth direction) in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. That is, it is a trench MOSFET having a vertical channel fin structure. Therefore, by reducing the trench pitch and increasing the channel density, the number of channels can be increased, so that the on-resistance when viewed over the entire semiconductor chip can be reduced.

[0028] As shown in FIG. 3, in the semiconductor device 1 of this embodiment, the ends in the first direction of the bottom surfaces of the plurality of trenches 2 are arranged in the body region 9. As a result, a structure is formed in which the three-dimensional corners of the trench 2 are present in the body region 9. Therefore, in the three-dimensional corner portion of the trench 2 where the electric field is likely to concentrate and the gate insulating film 6 is likely to be damaged, the concentration of the electric field is alleviated even when a high voltage is applied, and the breakdown of the gate insulating film 6 can be suppressed.

[0029] Further, in the semiconductor device 1 of this embodiment, it is desirable that the width (length in the first direction) of the gate electrode 7 disposed inside the trench 2 is set to be longer than the width (length in the first direction) (JFET width WJ) of the JFET region 8. Note that the width of the gate electrode 7 is the size obtained by subtracting the thickness of the gate insulating film (for two locations, one and the other in the first direction) from the width (length in the first direction) of the trench 2. And, it is desirable that the end portion in the first direction of the bottom surface of the gate electrode 7 in the trench 2 is disposed in the body region 9. Thereby, since the three-dimensional corners of the trench 2 and the gate electrode 7 are present in the body region 9, in the three-dimensional corner portion of the trench 2 where the electric field is likely to concentrate and the gate insulating film 6 is likely to be broken, the concentration of the electric field is alleviated even when a high voltage is applied, and the breakage of the gate insulating film 6 can be suppressed.

[0030] In the semiconductor device 1 of this embodiment, when a high voltage is applied between the drain and the source, the depletion layer starts to spread laterally from the body regions 9 on both sides of the JFET region 8, and when an even higher voltage is applied, the depletion layer closes and pinch-off occurs. Thereby, the breakdown voltage can be ensured. It is desirable that the impurity concentration of the first conductivity type in the JFET region 8 is set to be higher than the impurity concentration of the first conductivity type in the drift region 10. Thereby, the resistance of the JFET region 8 can be reduced, and the on-resistance can be reduced. Note that the present invention is not limited to this, and the impurity concentration of the first conductivity type in the JFET region 8 may be set to be the same as the impurity concentration of the first conductivity type in the drift region 10.

[0031] In a trench MOSFET having a vertical channel fin structure, when the trench pitch is reduced to increase the channel density and the dimension of the channel region 5 in the second direction (Fin width WF shown in FIG. 4) is decreased, the depletion layers extending from the two gate electrodes 7 sandwiching the channel region 5 are connected inside the channel region 5, and there is a problem that the threshold voltage (Vth) decreases below the intended threshold voltage (Vth) (the threshold voltage (Vth) when the depletion layers are not connected inside the channel region 5). This is because when the gate voltage is increased, normally, an inversion layer (channel) is formed in the channel region 5 when the maximum depletion layer width is reached. However, if the Fin width WF becomes smaller than a predetermined value, the depletion layers are connected before the maximum depletion layer width is reached, and the threshold voltage (Vth) decreases below the intended threshold voltage (Vth). Also, in such a case, since the threshold voltage (Vth) becomes smaller as the Fin width WF becomes smaller, there is a problem that the threshold voltage (Vth) varies when the Fin width WF varies due to manufacturing variations.

[0032] Therefore, in the semiconductor device 1 of the present embodiment, the channel region 5 has a first channel region 5A in contact with the lower surface of the source region 3 and a second channel region 5B disposed below the first channel region 5A, and the first channel region 5A has a higher impurity concentration of the second conductivity type than the second channel region 5B. By increasing the impurity concentration of the second conductivity type in the first channel region 5A disposed closer to the source region 3, it becomes difficult for the depletion layer to spread in the first channel region 5A. As a result, even when the Fin width WF is small, when the gate voltage is increased, it is possible to suppress the connection of the depletion layers before reaching the maximum depletion layer width, so that the intended threshold voltage (Vth) can be maintained. Therefore, according to the semiconductor device 1 of the present embodiment, even when the trench pitch is reduced to increase the channel density, it is possible to suppress a decrease and variation in the threshold voltage (Vth).

[0033] Note that the occurrence of the problem of the decrease in the threshold voltage (Vth) described above is related to the impurity concentration of the second conductivity type in the first channel region 5A and the dimension in the second direction (Fin width WF) of the first channel region 5A. Therefore, in the semiconductor device 1 of the present embodiment, the impurity concentration of the second conductivity type in the first channel region 5A and the dimension in the second direction (Fin width WF) of the first channel region 5A are set so that depletion layers extending from two gate electrodes 7 sandwiching the first channel region 5A do not connect inside the first channel region 5A even when a predetermined threshold voltage (Vth) is applied to the gate electrode 7. For this purpose, the impurity concentration of the second conductivity type in the first channel region 5A is desirably 5×10 17 cm -3 or more. Note that if the impurity concentration of the second conductivity type in the first channel region 5A is too high, the threshold voltage (Vth) will become too high. Therefore, it is desirably 2×10 18 cm -3 or less. In the present embodiment, the impurity concentration of the second conductivity type in the first channel region 5A is set to about 5×10 17 cm -3 . Also, the Fin width WF is desirably 0.2 um or more and 0.6 um or less. In the present embodiment, the Fin width WF is set to 0.5 um. Note that in the present embodiment, the depth of the lower surface of the first channel region 5A is set to 0.4 um, and the depth of the lower surface of the second channel region 5B is set to 0.6 um. Therefore, the thickness of the first channel region 5A is 0.1 um, and the thickness of the second channel region 5B is 0.2 um. Note that these thicknesses are merely examples and are not limited thereto.

[0034] Also, when the impurity concentration of the second conductivity type in the channel region 5 is low as in the prior art, when the impurity of the second conductivity type is ion-implanted into the body region 9, it spreads in the lateral direction in FIG. 2, and the JFET width WJ and the width of the channel region 5 are likely to vary. At the same time, it is considered that the impurity concentration of the second conductivity type in the channel region 5 is likely to become locally high due to the influence of the lateral spread. When the impurity concentration of the second conductivity type becomes locally high, the threshold voltage (Vth) of that portion increases. And, when the width (length in the first direction) of the trench 2 is reduced for high density in a state where the impurity concentration of the second conductivity type in the channel region 5 is low as in the prior art, the ratio of the portion where the impurity concentration of the second conductivity type becomes locally high inside the channel region 5 due to the influence of the lateral spread increases. Therefore, the influence on the variation of the threshold voltage (Vth) may increase. On the other hand, by increasing the impurity concentration of the second conductivity type in the first channel region 5A as in the present embodiment, when the impurity of the second conductivity type is ion-implanted into the body region 9, the impurity of the second conductivity type hardly spreads laterally in the first channel region 5A. Therefore, there is an effect that the threshold voltage (Vth) also hardly fluctuates.

[0035] Furthermore, since the first channel region 5A with a high impurity concentration of the second conductivity type is arranged at a position close to the source region 3, there is also an effect that the barrier lowering of the channel region 5 due to the drain voltage (drain-induced barrier lowering (DIBL), the phenomenon that the threshold voltage decreases when the drain voltage is large) hardly occurs. This is because the barrier is likely to decrease when the concentration is low, and the influence of the concentration in the vicinity of the source region 3 is particularly large.

[0036] In addition, the semiconductor device 1 of the present embodiment also has, among others, a source electrode 12 arranged on the front surface side, a drain electrode 13 arranged on the back surface side, an interlayer insulating film 14, and a contact region 4 of the second conductivity type.

[0037] The source electrode 12 is an electrode formed of a metal such as aluminum, for example.

[0038] The drain electrode 13 is an electrode formed of, for example, a laminated metal film (for example, titanium / nickel / gold), and is electrically connected to the drain region 11.

[0039] The interlayer insulating film 14 is formed between the connected portions of the gate electrode 7 and the source region 3. Further, the interlayer insulating film 14 is formed so as to cover the upper and side portions of the connected portions of the gate electrode 7.

[0040] The contact region 4 is provided between the body region 9 and the source electrode 12, and is a region having a higher impurity concentration of the second conductivity type than the body region 9. By providing the contact region 4, the body region 9 of the second conductivity type and the source electrode 12 can be connected with low resistance, rather than being connected via the source region 3 of the first conductivity type or directly connected to the body region 9. Note that the contact region 4 is not essential, and the source electrode 12 and the body region 9 may be directly connected without providing the contact region 4.

[0041] Regarding the impurity concentration, in this embodiment, as an example, the JFET region 8 is n, the body region 9 and the first channel region 5A are p, the second channel region 5B is low-concentration p−, the drift region 10 is low-concentration n−, the source region 3 and the drain region 11 are high-concentration n+, and the contact region 4 is high-concentration p+. However, the impurity concentration may be changed within a range that can realize the intended operation in this embodiment.

[0042] The semiconductor device 1 of this embodiment can be formed using, for example, an n+-type SiC substrate, but is not limited thereto, and an Si substrate or the like may be used. Also, for parts of the manufacturing method not specifically described in this specification, for example, an n+-type drain region 11 is formed on an n+-type SiC substrate, and an n−-type drift region 10 is formed by epitaxial growth. Since it can be manufactured by a general semiconductor device manufacturing method, detailed description is omitted.

[0043] FIG. 5 is an impurity concentration profile with respect to the depth in the Z1-Z1' direction of FIG. 2. The vertical axis represents the impurity concentration IC, shown on a log scale. The horizontal axis represents the depth DP.

[0044] In FIG. 5, the impurity concentration profiles of the source region 3, the first channel region 5A, the second channel region 5B, and the JFET region 8 are shown. As shown in FIG. 5, it is desirable that the peak depth of the impurity concentration of the second conductivity type in the first channel region 5A is deeper than the junction position between the source region 3 and the first channel region 5A (the intersection of the profile of the source region 3 and the profile of the first channel region 5A in FIG. 5). If there is a peak of the impurity concentration of the second conductivity type in the first channel region 5A inside the source region 3, it intersects on the right side of the peak in FIG. 5, so there is a problem that the intersection position is likely to shift and the effective channel concentration as the first channel region 5A is likely to shift. Therefore, by doing as in this embodiment, the peak impurity concentration in the first channel region 5A can be stabilized, and the variation in the threshold voltage (Vth) can be reduced.

Embodiment

[0045] Embodiment 2 is a modification of Embodiment 1, and the configuration of the body region 9 is different from that of Embodiment 1.

[0046] FIG. 6 is a cross-sectional view taken along the X1-X1' corresponding to FIG. 2 of Embodiment 1 in the semiconductor device of Embodiment 2.

[0047] In the semiconductor device 1 of this embodiment, the body region 9 has a first body region 9A disposed laterally of the channel region 5 and a second body region 9B disposed at a position deeper than the lower surface of the channel region 5, and the first body region 9A has a lower impurity concentration of the second conductivity type than the second body region 9B. Note that it is desirable that the impurity concentration of the second conductivity type in the first body region 9A is equal to or lower than the impurity concentration of the second conductivity type in the second channel region 5B. In FIG. 6, as an example, a case where the impurity concentration of the second conductivity type in the first body region 9A is equal to the impurity concentration of the second conductivity type in the second channel region 5B and the impurity concentration of the second conductivity type in the second body region 9B is equal to the impurity concentration of the second conductivity type in the body region 9 of the first embodiment is illustrated.

[0048] According to this embodiment, since the impurity concentration of the second conductivity type in the first body region 9A is lower than that in the first embodiment, when the impurity of the second conductivity type is ion-implanted into the first body region 9A, the spread in the lateral direction in FIG. 6 can be suppressed more than in the first embodiment, and as a result, the threshold voltage (Vth) can be made less likely to vary than in the first embodiment. Further, the impurity concentration of the second conductivity type in the second body region 9B is as high as that in the first embodiment, and since the ends in the first direction of the bottoms of the plurality of trenches 2 are disposed in the second body region 9B, as in the first embodiment, in the three-dimensional corner portions of the trenches 2 where the electric field is likely to concentrate and the gate insulating film 6 is likely to be broken, the concentration of the electric field can be alleviated even when a high voltage is applied, and the breakdown of the gate insulating film 6 can be suppressed.

[0049] As described above, the embodiments of the present invention have been described, but the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical idea of the present invention. Further, a part or all of the configurations described in each embodiment may be combined and applied.

Description of Reference Numerals

[0050] 1: Semiconductor device 2: Trench 3: Source region 4: Contact region 5: Channel region 5A: First Channel Region 5B: Second Channel Region 6: Gate Insulating Film 7: Gate Electrode 8: JFET Region 9: Body Region 9A: First Body Region 9B: Second Body Region 10: Drift Region 11: Drain Region 12: Source Electrode 13: Drain Electrode 14: Interlayer Insulating Film IC: Impurity Concentration DP: Depth WJ: JFET Width WF: Fin Width

Claims

1. having a longitudinal direction in a first direction and a short side direction in a second direction when viewed in plan view, and a plurality of trenches arranged in the second direction; a source region of a first conductivity type including a region having a fin structure at least partially separated by the plurality of trenches; a channel region of a second conductivity type having a fin structure separated by the plurality of trenches and in contact with the lower surface of the source region; a gate insulating film disposed inside the trench; a gate electrode including a region at least partially disposed inside the trench; a JFET region of a first conductivity type disposed below the channel region; and a body region of a second conductivity type disposed laterally of the JFET region, an end portion of the bottom surface of the plurality of trenches in the first direction is disposed in the body region; the channel region is connected to the body region, and a channel current flows vertically in the channel region; the channel region has a first channel region in contact with the lower surface of the source region and a second channel region disposed below the first channel region, and the first channel region has a higher impurity concentration of the second conductivity type than the second channel region. A semiconductor device characterized by that.

2. In claim 1, the impurity concentration of the second conductivity type in the first channel region and the dimension of the first channel region in the second direction are such that depletion layers extending from two gate electrodes sandwiching the first channel region do not connect inside the first channel region even when a predetermined threshold voltage is applied to the gate electrode. A semiconductor device characterized by being set to a value.

3. In claim 2, the impurity concentration of the second conductivity type in the first channel region is 5×10 １７ cm －３ or more and 2×10 １８ cm －３A semiconductor device characterized by the following.

4. In claim 3, A semiconductor device characterized in that the dimension of the first channel region in the second direction is 0.2 μm or more and 0.6 μm or less.

5. In claim 1, A semiconductor device characterized in that the peak depth of the impurity concentration of the second conductivity type in the first channel region is deeper than the junction position between the source region and the first channel region.

6. In claim 1, The body region has a first body region disposed laterally of the channel region and a second body region disposed at a position deeper than the lower surface of the channel region, and the first body region has an impurity concentration of the second conductivity type lower than that of the second body region. A semiconductor device characterized by this.

7. In claim 6, A semiconductor device characterized in that the impurity concentration of the second conductivity type in the first body region is equal to or lower than the impurity concentration of the second conductivity type in the second channel region.

8. In claim 1, A first conductivity type drift region disposed below the JFET region, A semiconductor device having a first conductivity type drain region disposed below the drift region and having a higher impurity concentration than the drift region.

9. In claim 1, A semiconductor device characterized in that the gate electrodes disposed inside the trench are connected to each other outside the trench.

10. In claim 1, A semiconductor device characterized in that the first conductivity type is n-type and the second conductivity type is p-type.

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