Signal generation device and signal generation method

Abstract

To provide a signal generation device capable of reducing the time required for phase matching while remarkably increasing a maximum phase difference, with which phases can be matched, between signals outputted from a plurality of transceivers and a signal generation method.SOLUTION: In a signal generation device, a phase synchronization control section 31 executes first phase move processing for moving a phase of a toggle pattern from an initial value just by a first initial phase difference PC1 and second phase move processing for moving the phase of the toggle pattern, which is moved by the first phase move processing, just by a second initial phase difference PC2. The second phase move processing is repeatedly executed while decreasing a frequency division ratio step by step by a frequency division ratio setting section 33. After the first phase move processing or the second phase move processing is executed when the frequency division ratio is equal to or less than a predetermined value, a clock selection section selects an external clock in place of a frequency divided clock.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a signal generation device and a signal generation method, and more particularly to a signal generation device and a signal generation method including a transceiver that converts parallel data into high-speed serial data and outputs it.

Background Art

[0002] With the increase in the speed of communication standards such as Ethernet (registered trademark) 800GbE (Gigabit Ethernet) and PCIe (registered trademark) (Peripheral Component Interconnect Express) Gen (Generation) 6, the signal transmission method has also changed from a simple binary digital signal such as NRZ (Non Return to Zero) to PAM (Pulse Amplitude Modulation) 4. In the future, it is also conceivable that transmission methods such as PAM8 and PAM16 will be standardized. When developing and testing products using these signals, a test signal source is required.

[0003] Naturally, such a signal source should be able to generate signals such as PAM4 and PAM8, and it is desirable that it can generate signals that have passed through a specific transmission path or signals that have been subjected to emphasis or filter processing. Therefore, an analog arbitrary waveform generator (AWG) that can generate an arbitrary waveform and has a high speed exceeding 100 Gsps (G Symbol / s) is required.

[0004] In an AWG, it is necessary for the user to be able to freely set the analog waveform to be output. Also, as a matter of course, since the generation of arbitrary signals is required, it is necessary to be able to set the waveform with numerical data. Therefore, the AWG requires a mechanism inside to convert digital data output from an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc. into analog data. This conversion itself is possible with a Digital Analog Converter (DAC).

[0005] However, when the output rate of the required analog data is high, not only is it necessary to input a signal speeded up by multiplexing with a multiplexer (MUX) to the DAC, but the influence of the phase difference between a plurality of input signals input to the DAC and the MUX in the previous stage cannot be ignored. For example, when the output rate of the FPGA is 32 Gsps and the bit resolution of the DAC is 8 bits, it is desirable that the maximum phase difference between all signals input to the MUX is less than 0.1 UI (Unit Interval) (3.125 ps).

[0006] Here, by using the technique described in Patent Document 1, it is possible to adjust the maximum phase difference between all signals input to the MUX to be less than or close to 0.1 UI.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] However, the technique described in Patent Document 1 may adjust the phase between the signals input to the MUX at a position shifted by one clock (1UI). This occurs when the phase between the signals before this adjustment is significantly shifted.

[0009] Specifically, the technique described in Patent Document 1 cannot handle the case where a phase difference exceeding 1UI occurs between the signals before adjustment. Furthermore, even when the phase difference between the signals before adjustment is suppressed to within 1UI in advance by other means, there are also technical and cost issues such as the need for an additional mechanism to adjust the clock phase applied to the transceiver of the FPGA, etc., and the measurement of the phase adjustment amount that varies depending on the frequency. In the case of an FPGA, the phase difference between transceivers may change every time startup or reset is performed. In this case, re-measurement of the phase adjustment amount is required every time startup or reset is performed. Also, depending on the FPGA used, even when the internal connection routes of the FPGA are fixed, there may be a possibility that the phase difference of the output signals cannot be suppressed to within 1UI in the first place.

[0010] In this case, unintended data is generated when the signals are multiplexed using the MUX. For example, if this data is used as a test signal for a bit error rate tester (BERT), since there are errors in the test signal itself, it becomes impossible to measure the correct error rate.

[0011] The applicant attempted to solve these problems in Japanese Patent Application No. 2023-160154 (hereinafter referred to as the "prior application"). By using the technique of the prior application, the phase differences of the signals input to the DAC and the MUX in front of it can be aligned, but this technique requires approximately ten to several tens of milliseconds, and in some cases, several hundreds of milliseconds to align the phases.

[0012] Therefore, in a signal generation device, when the phase acquisition process, the phase difference calculation process, and the phase shift process according to the prior art are performed multiple times, or due to a complex factor including a delay caused by using this technology, there is a risk of a large delay occurring from the time when the user operates the signal generation device to start signal transmission until the signal is actually transmitted. If the delay becomes large, the usability of the signal generation device itself will be impaired.

[0013] The present invention has been made to solve such conventional problems, and an object thereof is to provide a signal generation device and a signal generation method capable of significantly increasing the maximum phase difference that can be phase-matched between signals output from a plurality of transceivers and reducing the time required for phase matching.

Means for Solving the Problems

[0014] In order to solve the above problems, a signal generation device according to the present invention includes a parallel data output unit (11) that outputs parallel data of multiple bits, a FIFO (21) that stores N-bit parallel data among the multiple-bit parallel data output from the parallel data output unit, a plurality of transceivers (20) that convert the N-bit parallel data stored in the FIFO into 1-bit serial data, a phase synchronization control unit (31) that controls the phase of the 1-bit serial data converted by each transceiver, a divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock, a divided ratio setting unit (33) that sets the divided ratio of the divided clock to the divided clock output unit, a clock selection unit (17) that selects either the external clock or the divided clock, a rate control unit (34) that performs control to cause each transceiver to output a toggle pattern having a frequency half of the frequency of the divided clock or the external clock selected by the clock selection unit as the 1-bit serial data, and a phase detection unit (40) that outputs a detection voltage corresponding to the phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern. The phase synchronization control unit includes a phase acquisition processing unit (31b) that executes a phase acquisition process of acquiring the initial value, maximum value, and minimum value of the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value, a phase difference calculation processing unit (31d) that executes a first phase difference calculation process of calculating a first initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the initial value, maximum value, and minimum value of the detection voltage acquired by the phase acquisition processing unit, a phase shift processing unit (31e) that moves the phase of the toggle pattern so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern falls within a predetermined range of values, and an initial voltage acquisition processing unit (31c) that executes an initial voltage acquisition process of acquiring the detection voltage output from the phase detection unit as an initial voltage after the phase of the toggle pattern is moved by the phase shift processing unit.The phase difference calculation processing unit further executes a second phase difference calculation process for calculating a second initial phase difference between the divided clock selected by the clock selection unit and the phase of the toggle pattern moved by the phase shift processing unit, based on the maximum value and the minimum value of the detected voltage acquired by the phase acquisition processing unit and the initial voltage acquired by the initial voltage acquisition processing unit. The phase shift processing unit executes a first phase shift process for shifting the phase of the toggle pattern from the initial value by the amount of the first initial phase difference, and a second phase shift process for shifting the phase of the toggle pattern moved by the first phase shift process by the amount of the second initial phase difference. The phase synchronization control unit repeatedly executes the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio by the division ratio setting unit. The clock selection unit is configured to select the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is equal to or less than a predetermined value set in advance.

[0015] With this configuration, the signal generator according to the present invention can reduce the maximum phase difference between the serial data output from each of the plurality of transceivers to 0.1 UI or less based on the external clock reference.

[0016] In addition, since the signal generator according to the present invention reduces the number of times of the phase acquisition process to one, it is possible to shorten the time required for phase alignment between lanes as compared with the prior art technique that repeats the phase acquisition process every time the division ratio changes.

[0017] In addition, the signal generator according to the present invention can significantly increase the maximum phase difference that allows phase alignment between the serial data output from each of the plurality of transceivers after startup or reset.

[0018] Furthermore, since the signal generation device according to the present invention does not require an additional mechanism such as a delay circuit outside the FPGA to suppress the phase difference between the serial data before adjustment to within 1 UI in advance, it is not necessary to investigate the parameters given to the additional mechanism after product manufacturing.

[0019] Also, in the signal generation device according to the present invention, the clock selection unit may be configured to select the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is 4 or less.

[0020] In addition, the signal generation device according to the present invention includes a PISO (22) in which each of the transceivers converts the N-bit parallel data read from the FIFO into the 1-bit serial data in response to a read clock signal, a usage amount determination unit (23) that executes first and second usage amount determination processes for determining whether the usage amount of the FIFO is equal to or greater than a usage amount threshold, a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount, and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount. The phase adjustment unit (24) has a configuration including a usage amount control processing unit (31a) that executes a usage amount control process for controlling the usage amount of the FIFO before the phase acquisition process is executed by the phase acquisition processing unit. The usage amount control process of the usage amount control processing unit includes a process of causing the usage amount determination unit to execute the first usage amount determination process on the condition that the output of the serial data from each of the transceivers is started, a process of causing the phase adjustment unit to execute the first phase adjustment process on the condition that the usage amount determination unit determines that the usage amount of the FIFO of each of the transceivers is equal to or greater than the usage amount threshold by the first usage amount determination process, and a process of causing the usage amount determination unit to execute the second usage amount determination process on the condition that the number of consecutive determinations that the usage amount of the FIFO of each of the transceivers is less than the usage amount threshold by the first usage amount determination process reaches a first determination number, and a process of causing the phase adjustment unit to execute the second phase adjustment process on the condition that the usage amount determination unit determines that the usage amount of the FIFO of each of the transceivers is less than the usage amount threshold by the second usage amount determination process, and a process of causing the phase adjustment unit to end the adjustment of the phase of the read clock signal on the condition that the number of consecutive determinations that the usage amount of the FIFO of each of the transceivers is equal to or greater than the usage amount threshold by the second usage amount determination process reaches a second determination number. It may have a configuration including these processes.

[0021] Further, before starting the global phase measurement process using the divided clock including the phase acquisition process, the signal generation device according to the present invention executes a usage control process for aligning the usage amounts of the FIFOs in all lanes to half. As a result, the signal generation device according to the present invention can move the phase of the toggle pattern in both positive and negative directions within a maximum range of -1UI to +1UI, for example, when the usage amount of the FIFO is equivalent to 2UI of the divided clock with the maximum division ratio, during the phase acquisition process.

[0022] In addition, the signal generation method according to the present invention includes a parallel data output unit (11) that outputs parallel data of multiple bits, a FIFO (21) that stores N-bit parallel data among the multiple-bit parallel data output from the parallel data output unit, a plurality of transceivers (20) that convert the N-bit parallel data stored in the FIFO into 1-bit serial data, a divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock, a clock selection unit (17) that selects either the external clock or the divided clock, and a phase detection unit (40) that outputs a detection voltage corresponding to the phase difference between the divided clock or the external clock selected by the clock selection unit and the 1-bit serial data. A signal generation method for controlling the phase of the 1-bit serial data converted by each transceiver using a signal generation device (1), the method including: a divided ratio setting step (S14, S18) of setting the divided ratio of the divided clock in the divided clock output unit; a rate control step (S31, S37) of causing each transceiver to output a toggle pattern having a frequency half of the frequency of the divided clock or the external clock selected by the clock selection unit as the 1-bit serial data; a phase acquisition processing step (S32, S35) of executing a phase acquisition process of obtaining an initial value, a maximum value, and a minimum value of the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing step (S33, S36, S39) of executing a first phase difference calculation process of calculating a first initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the initial value, the maximum value, and the minimum value of the detection voltage obtained in the phase acquisition processing step; and a phase shift processing step (S16,S22) and an initial voltage acquisition processing step (S38) that executes an initial voltage acquisition process of acquiring, as an initial voltage, the detection voltage output from the phase detection unit after the phase of the toggle pattern is moved by the phase shift processing step; The phase difference calculation processing step further executes a second phase difference calculation process of calculating a second initial phase difference between the divided clock selected by the clock selection unit and the phase of the toggle pattern moved by the phase shift processing step based on the maximum value and the minimum value of the detection voltage acquired by the phase acquisition processing step and the initial voltage acquired by the initial voltage acquisition processing step; The phase shift processing step executes a first phase shift process of shifting the phase of the toggle pattern from the initial value by the amount of the first initial phase difference and a second phase shift process of shifting the phase of the toggle pattern moved by the first phase shift process by the amount of the second initial phase difference; The signal generation method includes a step (S16 to S19) of repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio in the division ratio setting step; and an external clock selection step (S20) of selecting the external clock instead of the divided clock by the clock selection unit after the first phase shift process or the second phase shift process is executed when the division ratio is equal to or less than a predetermined value determined in advance. ,

[0023] Further, in the signal generation method according to the present invention, the external clock selection step may be configured to select the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is 4 or less.

Advantages of the Invention

[0024] The present invention provides a signal generation device and a signal generation method capable of significantly increasing the maximum phase difference capable of phase matching between signals output from a plurality of transceivers and reducing the time required for phase matching.

Brief Description of the Drawings

[0025]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

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Figure 8

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Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Embodiments for Carrying Out the Invention

[0026] Hereinafter, embodiments of the signal generation device and the signal generation method according to the present invention will be described with reference to the drawings.

[0027] The signal generation device 1 according to the present embodiment shown in FIG. 1 includes a data output unit 10, a clock selection unit 17, a phase detection unit 40, a MUX 50, an amplifier 52, an ADC 55, a DAC 60, an operation unit 65, and a control unit 70. Note that the data output unit 10 is configured, for example, on an FPGA or an ASIC. Hereinafter, it will be described assuming that these are configured on an FPGA.

[0028] The data output unit 10 includes a parallel data output unit 11, a plurality of transceiver units 12-1 to 12-p, a clock generation unit 13, a divided clock output unit 14, and an FPGA control unit 15.

[0029] The parallel data output unit 11 has an internal memory (not shown) that stores a series of data columns of a predetermined pattern in advance, or an arithmetic circuit (not shown) that generates this data column. For example, in the example shown in FIG. 2, the parallel data output unit 11 is configured to output 32×N-bit parallel data.

[0030] The parallel data output unit 11 outputs, as 32×N-bit parallel data, a pattern of a PAM signal composed of, for example, a multi-value K (K is an integer of 2 or more) of 2 values or more, based on the pattern information input from the operation unit 65. The parallel data output unit 11 generates a pattern of a PAM signal composed of an arbitrary multi-value K such as an NRZ signal (K = 2), a PAM3 signal (K = 3), a PAM4 signal (K = 4), a PAM5 signal (K = 5), a PAM6 signal (K = 6), a PAM7 signal (K = 7), and a PAM8 signal (K = 8). Here, the pattern information is information on the pattern of the PAM signal such as the value of K and the type of pattern (for example, PRBS (Pseudo Random Binary Sequence) pattern, SSPRQ (Short Stress Pattern Random Quaternary) pattern, arbitrary pattern).

[0031] The data output unit 10 includes p transceiver units 12-1 to 12-p. FIGS. 1 and 2 show an example where p = 8. However, in the present invention, the number of transceiver units 12 is not limited to 8 and may be any number.

[0032] As shown in FIG. 2, the clock signal generated by the clock generation unit 13 is distributed to each transceiver unit 12.

[0033] Each transceiver unit 12 includes, for example, four transceivers 20-0 to 20-3. Each transceiver 20 is an output unit of the FPGA and outputs a digital signal of 0 or 1. Each transceiver 20 converts the N-bit parallel data stored in the FIFO 21, which will be described later, among the 32×N-bit parallel data output from the parallel data output unit 11 into 1-bit serial data at the timing of the clock signal generated by the clock generation unit 13. Here, N is an integer of 2 or more.

[0034] That is, each transceiver unit 12 is configured to convert the 4×N-bit parallel data output from the parallel data output unit 11 into 4-bit parallel data and output it. That is, the data output unit 10 outputs 4-bit parallel data for 8 channels, in other words, serial data for 32 lanes.

[0035] The divided clock output unit 14 is configured to output a divided clock obtained by dividing the frequency of the external clock. The maximum frequency of the divided clock is half of the frequency of the external clock. For example, the divided clock output unit 14 includes a transceiver having the same configuration as each transceiver 20.

[0036] The clock selection unit 17 is configured to select either an external clock or a divided clock according to the clock selection signal output from a clock selection signal output unit 35, which will be described later. In this specification, the divided clock and the external clock are collectively referred to simply as "clock". The external clock is, for example, a 32 GHz pulse signal.

[0037] The phase detection unit 40 is configured to output a detection voltage corresponding to the phase difference between the divided clock or the external clock selected by the clock selection unit 17 and the toggle pattern output from each transceiver 20. The toggle pattern is 1-bit serial data in which "0" and "1" are alternately repeated, and is output from each transceiver 20 when a phase acquisition process or an initial voltage acquisition process, which will be described later, is executed. One phase detection unit 40 is arranged at the subsequent stage of each transceiver 20. Since the phase detection unit 40 is for checking the phase of the toggle pattern output from each transceiver 20, it may be incorporated in the MUX 50 or may be independently arranged in front of the MUX 50.

[0038] A schematic diagram of the phase detection unit 40 for one lane is shown in FIG. 3. As shown in the figure, the phase detection unit 40 includes, for example, a D flip-flop 41, an EXOR circuit 42, and an averaging circuit 43.

[0039] The D flip-flop 41 includes a D terminal and a CLK terminal, which are two input terminals, and a Q terminal, which is one output terminal. The toggle pattern from the corresponding transceiver 20 is input to the D terminal, and the clock selected by the clock selection unit 17 is input to the CLK terminal.

[0040] The EXOR circuit 42 is configured to output a phase detection signal by taking the exclusive OR of the toggle pattern from the corresponding transceiver 20 and the output signal from the Q terminal of the D flip-flop 41. When a toggle pattern having a period twice that of the clock is input to the D terminal, the phase detection signal becomes a pulse-like signal having a duty ratio corresponding to the phase of the toggle pattern input to the D terminal.

[0041] The averaging circuit 43 is constituted by, for example, a low-pass filter and is configured to average the phase detection signal. When a toggle pattern having a period twice that of the clock is input to the D terminal, the averaging circuit 43 outputs a signal of a detection voltage corresponding to the duty ratio of the phase detection signal. Thereby, the phase of the toggle pattern from the corresponding transceiver 20 can be obtained as the detection voltage.

[0042] The amplifier 52 is configured to amplify the signal of the detection voltage from the phase detection unit 40 to a voltage level suitable for the subsequent ADC 55 as necessary.

[0043] The ADC 55 is configured to sample the signal of the detection voltage amplified by the amplifier 52 at a predetermined sampling rate and convert it into digital data. That is, the ADC 55 outputs digital data of the detection voltage corresponding to the phase difference between the divided clock or the external clock selected by the clock selection unit 17 and the toggle pattern. Here, the predetermined sampling rate may be a value in the range of several hundred ksps to several Msps, such as 500 ksps or 1 Msps. For this reason, an ADC having a plurality of input channels, such as a 4-channel ADC, can also be used as the ADC 55.

[0044] The MUX 50 latches the m-bit parallel data output from each transceiver unit 12, selects n bits at a time in a predetermined order in synchronization with the external clock selected by the clock selection unit 17, and outputs n-bit data corresponding to the frequency of the external clock selected by the clock selection unit 17. Here, n is an integer greater than or equal to 1 and less than or equal to m−1. In the example shown in FIG. 1, n = 1 and m = 4. That is, the MUX 50 can multiplex the m-bit data from each transceiver unit 12 into n-bit data.

[0045] The DAC60 is an n×p-bit DAC, and is configured to output an analog signal with a resolution of n×p bits, i.e., a PAM signal with a multi-value K, according to the n×p-bit data output from all the MUX50s. In the example shown in FIG. 1, n = 1 and p = 8.

[0046] The operation unit 65 is for receiving operation inputs by the user, and is configured by, for example, a touch panel including a touch sensor for detecting a contact position by a contact operation on an input surface corresponding to a display screen of a display device (not shown). Alternatively, the operation unit 65 may be configured to include an input device such as a keyboard or a mouse. Operation inputs to the operation unit 65 are to be detected by the control unit 70.

[0047] The control unit 70 is configured by a control device such as a computer including, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA, a ROM (Read Only Memory), a RAM (Random Access Memory), an HDD (Hard Disk Drive), etc., and controls the operations of the above-described respective parts constituting the signal generator 1.

[0048] FIG. 4 is a diagram showing the configuration of one lane of the data output unit 10. Each transceiver 20 includes a FIFO (First-In First-Out) 21 for storing N-bit parallel data out of the 32×N-bit parallel data output from the parallel data output unit 11, a PISO (Parallel-In Serial-Out) 22 for converting the N-bit parallel data read from the FIFO 21 according to a read clock signal into 1-bit serial data, a usage amount determination unit 23 that executes first and second usage amount determination processes for determining whether the usage amount of the FIFO 21 is equal to or greater than a usage amount threshold, a phase adjustment unit 24 that adjusts the phase of the read clock signal of the FIFO 21 to decrease or increase, and frequency dividers 25, 26 and a subtractor 27.

[0049] That is, the transceiver 20 reads out the stored N-bit parallel data from the FIFO 21, performs parallel / serial conversion on the read parallel data by the PISO 22, and outputs serial data.

[0050] In the signal generator 1 of the present embodiment, each transceiver unit 12 can be configured by a transceiver equipped with a function of adjusting the phase of the read clock signal, such as a TX Phase Interpolator PPM Controller (hereinafter referred to as "TXPI") provided by Xilinx. Further, for example, as the FPGA in which the data output unit 10 is configured, an UltraScale+ equipped with a GTY transceiver manufactured by Xilinx can be preferably used.

[0051] Generally, the timings until actual data is output after activation or reset of a plurality of transceivers configured on the FPGA do not always match each other. For this reason, at the timing when data output starts, the usage amounts of the FIFO 21 of the transceiver 20 are usually different. Also, when focusing on one transceiver 20, the usage amounts when data output starts may be different for each activation or reset.

[0052] Hereinafter, the basic operation of the TXPI will be described with reference to FIG. 4.

[0053] The FIFO 21 functions as a buffer for the parallel data output from the parallel data output unit 11 and can store up to M words of N-bit parallel data. The FIFO 21 writes or reads N-bit parallel data at the rising timing of the input write clock signal or read clock signal. The write clock signal and the read clock signal are signals based on the clock signal generated by the clock generation unit 13, for example.

[0054] The frequency divider 25 divides the read clock signal by the maximum number of words M of the FIFO 21 to obtain the read address of the FIFO 21. On the other hand, the frequency divider 26 divides the write clock signal by the maximum number of words M of the FIFO 21 to obtain the write address of the FIFO 21.

[0055] The subtractor 27 outputs the difference between the read address and the write address respectively output from the frequency dividers 25 and 26. The difference output from the subtractor 27 reflects the usage amount of the FIFO 21.

[0056] The usage amount determination unit 23 executes first and second usage amount determination processes for determining whether the difference output from the subtractor 27 is equal to or greater than the usage amount threshold every one clock of the operation clock of the FPGA in which the data output unit 10 is configured. The usage amount determination unit 23 constantly monitors the difference between the read address and the write address of the FIFO 21 as the usage amount of the FIFO 21, and outputs 0 when the usage amount is less than the usage amount threshold and 1 when the usage amount is equal to or greater than the usage amount threshold. For example, the usage amount threshold is M / 2, that is, one half of the maximum number of words M of the FIFO 21. The usage amount of the FIFO 21 changes as the phase of the read clock signal changes.

[0057] The phase adjustment unit 24 executes a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount in the usage amount control process described later. The first phase adjustment process is a process for decreasing the usage amount of the FIFO 21, and the second phase adjustment process is a process for increasing the usage amount of the FIFO 21.

[0058] The phase adjustment unit 24 can shift the read address value of the FIFO 21 by adjusting the phase of the read clock signal of the FIFO 21. As a result, the phase of the parallel data output from the FIFO 21 is shifted. However, the phase adjustment unit 24 cannot adjust the phase of the parallel data output from the FIFO 21 to an arbitrary value, and the phase adjustment width that can be adjusted at one time and the maximum adjustable amount are also limited. For example, when the output data speed of the transceiver 20 is 32 Gbps, the phase adjustment width that the phase adjustment unit 24 can adjust is 1 / 64 UI step width, and the maximum amount that the phase adjustment unit 24 can adjust is 64 UI.

[0059] Hereinafter, with reference to the state transition diagram of FIG. 5, the usage control process executed by the usage control processing unit 31a of the phase synchronization control unit 31 (see FIG. 6) provided in the FPGA control unit 15 will be described. The usage control process of the usage control processing unit 31a is a process for controlling the usage amount of the FIFO 21 of each transceiver 20, and is executed independently for each lane, that is, for each transceiver 20.

[0060] As shown in FIG. 5, the usage control processing unit 31a includes eight states of S1 to S7, that is, an initial state, a PRESET state, a BUFCHK1 state, a TXPI_DEC state, a TXPI_INC state, a BUFCHK2 state, and a PHASEADJ state. The arrows between the states represent transitions and their directions.

[0061] First, the usage control processing unit 31a transitions from the initial state S1 to the PRESET state S2. The PRESET state S2 is a state in which each transceiver 20 waits until the output of serial data starts. Here, each transceiver 20 starts generating a clock in a clock generation circuit (not shown) when it becomes a state where it can start outputting serial data after startup or reset. The usage control processing unit 31a can detect the timing at which each transceiver 20 starts outputting serial data by detecting the rising edge of this clock.

[0062] When the usage control processing unit 31a detects that each transceiver 20 has started outputting serial data, it transitions from the PRESET state S2 to the BUFCHK1 state S3. The BUFCHK1 state S3 is a state in which the usage control processing unit 31a causes the usage determination unit 23 to execute the first usage determination process.

[0063] The usage control processing unit 31a transitions from the BUFCHK1 state S3 to the TXPI_DEC state S4 on the condition that it is determined by the first usage determination process that the usage amount of the FIFO 21 of each transceiver 20 is equal to or greater than the usage threshold. The TXPI_DEC state S4 is a state in which the usage control processing unit 31a causes the phase adjustment unit 24 to execute the first phase adjustment process.

[0064] The usage control processing unit 31a transitions from the TXPI_DEC state S4 back to the BUFCHK1 state S3 on the condition that the phase of the read clock signal of the FIFO 21 of each transceiver 20 has been decreased by a predetermined amount by the first phase adjustment process.

[0065] The usage control processing unit 31a transitions from the BUFCHK1 state S3 to the TXPI_INC state S5 on the condition that the number of consecutive determinations that the usage amount of the FIFO 21 of each transceiver 20 is less than the usage threshold by the first usage determination process has reached the first determination count. The TXPI_INC state S5 is a state in which the usage control processing unit 31a causes the phase adjustment unit 24 to execute the second phase adjustment process.

[0066] The usage control processing unit 31a transitions from the TXPI_INC state S5 to the BUFCHK2 state S6 on the condition that the phase of the read clock signal of the FIFO 21 of each transceiver 20 has been increased by a predetermined amount by the second phase adjustment process. The BUFCHK2 state S6 is a state in which the usage control processing unit 31a causes the usage determination unit 23 to execute the second usage determination process.

[0067] The usage control processing unit 31a transitions from the BUFCHK2 state S6 back to the TXPI_INC state S5 on the condition that the usage amount of the FIFO 21 of each transceiver 20 is determined to be less than the usage amount threshold by the second usage amount determination process.

[0068] The usage control processing unit 31a transitions from the BUFCHK2 state S6 to the PHASEADJ state S7 on the condition that the number of consecutive determinations that the usage amount of the FIFO 21 of each transceiver 20 is equal to or greater than the usage amount threshold by the second usage amount determination process reaches the second determination count. The PHASEADJ state S7 is a state in which the usage control processing unit 31a finishes adjusting the phase of the read clock signal to the phase adjustment unit 24 and waits until there is an input of a reset signal to each transceiver 20.

[0069] By performing the processes shown in FIG. 5 for all the transceivers 20, the usage control processing unit 31a can equalize the usage amounts of the FIFOs 21 of all the lanes to half, and thus can equalize the data latencies of all the lanes. Since the phases of the 32×N-bit parallel data output from the parallel data output unit 11 are in the same phase among all the lanes, the phases of the serial data output from all the transceivers 20 will also be approximately in the same phase.

[0070] According to the process shown in FIG. 5, when the phase adjustment width by the phase adjustment unit 24 is 1 / 64 UI, the phase of the serial data output from the transceiver 20 can be adjusted with a precision of ±0.008 UI (theoretical limit value) in calculation. Note that the first and second determination counts may be equal to each other or may be different from each other.

[0071] In the process of the usage control processing unit 31a shown in FIG. 5, if the transitions from the BUFCHK1 state S3 to the TXPI_DEC state S4, from the BUFCHK2 state S6 to the TXPI_INC state S5, from the BUFCHK1 state S3 to the TXPI_INC state S5, and from the BUFCHK2 state S6 to the PHASEADJ state S7 are each executed when their respective determination conditions are satisfied once, the maximum phase difference between the serial data output from all the transceivers 20 after the phase adjustment will be a value larger than the above theoretical limit value. This is presumably because the usage amount of the FIFO 21 constantly fluctuates due to the jitter components of the write clock signal and the read clock signal, resulting in fluctuations in the determination results of the first and second usage amount determination processes by the usage amount determination unit 23.

[0072] Therefore, in the process of the usage control processing unit 31a shown in FIG. 5, for the transitions from the BUFCHK1 state S3 to the TXPI_INC state S5 and from the BUFCHK2 state S6 to the PHASEADJ state S7, the signal generation device 1 of the present embodiment stipulates the first and second determination times for continuously satisfying the transition conditions, and executes the transition only when the transition conditions are continuously met for those times.

[0073] As shown in FIG. 6, the FPGA control unit 15 includes a phase synchronization control unit 31, a division ratio setting unit 33, a rate control unit 34, and a clock selection signal output unit 35.

[0074] The phase synchronization control unit 31 is configured to control the phase of the toggle pattern, which is 1-bit serial data converted by each transceiver 20.

[0075] The phase synchronization control unit 31 includes a usage control processing unit 31a, a phase acquisition processing unit 31b, an initial voltage acquisition processing unit 31c, a phase difference calculation processing unit 31d, and a phase shift processing unit 31e.

[0076] As described above, the usage control process of the usage control processing unit 31a includes a process of causing the usage determination unit 23 to execute a first usage determination process, a process of causing the phase adjustment unit 24 to execute a first phase adjustment process, a process of causing the usage determination unit 23 to execute a second usage determination process, a process of causing the phase adjustment unit 24 to execute a second phase adjustment process, and a process of causing the phase adjustment unit 24 to end the adjustment of the phase of the read clock signal. The usage control processing unit 31a executes the above-described usage control process before the phase acquisition process described later is executed by the phase acquisition processing unit 31b.

[0077] The phase acquisition processing unit 31b controls the phase adjustment unit 24 of each transceiver 20 to change the phase of the toggle pattern output from each transceiver 20 from the initial value, and the initial value V0, the maximum value V H and the minimum value V L of the detected voltage output from the phase detector 40 are acquired. Here, the digital data of the detected voltage is input from the ADC 55 to the phase acquisition processing unit 31b.

[0078] Hereinafter, a specific example of the phase acquisition process by the phase acquisition processing unit 31b will be described. The phase acquisition processing unit 31b performs the phase acquisition process simultaneously or sequentially for all of the toggle patterns for 32 lanes. FIG. 7 shows the relationship between the toggle pattern and the clock output from one transceiver 20 of the data output unit 10.

[0079] First, the phase acquisition processing unit 31b acquires the detected voltage output from the phase detector 40 at the start point of the phase acquisition process. Here, the phase of the toggle pattern at the start point is set to 0UI. Further, the phase synchronization control unit 31 sets one cycle of the clock at that time point to 1UI, and acquires the detected voltage output from the phase detector 40 while moving the phase of the toggle pattern within the range of -0.75UI to +0.75UI. For example, as shown by the arrow in FIG. 7, the phase synchronization control unit 31 moves the phase of the toggle pattern from the initial value of 0UI at the start point of the phase acquisition process to -0.75UI, then from -0.75UI to +0.75UI, and finally from +0.75UI to the initial 0UI at the start point.

[0080] This means, for example, repeating an operation of measuring the detected voltage output from the phase detector 40 each time the phase of the toggle pattern is moved by about 0.1UI. As a result, a result as shown in FIG. 8 can be obtained. In the graph of FIG. 8, the horizontal axis indicates the change amount [UI] from the initial value of the phase of the toggle pattern, and the vertical axis indicates the detected voltage [V] output from the phase detector 40.

[0081] In the phase acquisition process, for example, eight ADC55s with 4-channel input and 500 ksps are used. For averaging, digital data of the detected voltage is acquired 10 times per channel for each measurement point. In this case, a measurement time of about 80 μs is required for each measurement point. If the movement and measurement of the phase of the toggle pattern are performed at 32 measurement points, a measurement time of approximately 3 ms is required.

[0082] Since TXPI adjusts the phase of the serial data from each transceiver 20 based on the usage amount of the FIFO21, if the usage amount in the initial state is biased, there is a possibility that an adjustment range of ±0.75UI cannot be ensured. Therefore, the phase synchronization control unit 31 performs the usage amount control process described above so that the phase of the toggle pattern can be moved within the range of ±0.75UI.

[0083] In the above description, the range of the phase change of the toggle pattern is set to -0.75UI to +0.75UI, but the present invention is not limited thereto. The range of the phase change of the toggle pattern only needs to be at least 1UI. For example, the phase of the toggle pattern may be changed within the range of -0.5UI to +0.5UI.

[0084] Furthermore, based on the relationship between the acquired detected voltage and the phase of the toggle pattern, the phase acquisition processing unit 31b determines the initial value V0, which is the detected voltage at the start time of the phase acquisition processing, and the maximum value V of the detected voltage H , the minimum value V of the detected voltage L .

[0085] As shown in FIG. 8, linearity can be seen in the relationship between the detected voltage and the phase of the toggle pattern in units of 1UI. Therefore, the phase acquisition processing unit 31b does not use the output value itself from the phase detector 40, but obtains an approximate straight line of the relationship between the detected voltage and the phase of the toggle pattern using the linear least squares method, and calculates the initial value V0, the maximum value V H , the minimum value V L from the result.

[0086] As a result, the influence of disturbances such as noise is reduced in the measurement result of the phase difference between the clock and the toggle pattern by the phase detector 40, and the accuracy of each value of the initial value V0, the maximum value V H , the minimum value V L can be improved.

[0087] The initial voltage acquisition processing unit 31c executes an initial voltage acquisition process of acquiring, as the initial voltage V0', the detected voltage output from the phase detector 40 after the phase of the toggle pattern output from each transceiver 20 is moved by a phase shift processing unit 31e described later.

[0088] That is, the initial voltage acquisition process by the initial voltage acquisition unit 31c assumes that the phase acquisition process by the phase acquisition unit 31b has already been performed. In the initial voltage acquisition process, the phase of the toggle pattern is not shifted, and only the initial voltage V0' which is the detected voltage at the time when the initial voltage acquisition process is executed is acquired. The initial voltage acquisition unit 31c is configured to perform the initial voltage acquisition process simultaneously or sequentially for all of the toggle patterns for 32 lanes.

[0089] The phase difference calculation unit 31d executes a first phase difference calculation process for calculating a first initial phase difference P H , between the divided clock or the external clock selected by the clock selection unit 17 and the initial value of the phase of the toggle pattern, based on the initial value V0, the maximum value V L of the detected voltage acquired by the phase acquisition process of the phase acquisition unit 31b, and the minimum value V C1 .

[0090] Furthermore, the phase difference calculation unit 31d executes a second phase difference calculation process for calculating a second initial phase difference P H between the divided clock selected by the clock selection unit 17 and the phase of the toggle pattern shifted by the phase shift processing unit 31e described later, based on the maximum value V L and the minimum value V C2 of the detected voltage acquired by the phase acquisition process of the phase acquisition unit 31b, and the initial voltage V0' acquired by the initial voltage acquisition process of the initial voltage acquisition unit 31c. In this specification, the first phase difference calculation process and the second phase difference calculation process are collectively referred to simply as "phase difference calculation process".

[0091] The phase difference calculation unit 31d substitutes the initial value V0, the maximum value V H , and the minimum value V L of the detected voltage acquired by the phase acquisition process into the following formula (1) to obtain the first initial phase difference P C1 [UI] of the toggle pattern at the start time of the phase acquisition process. Further, the phase difference calculation unit 31d calculates the maximum value V H and the minimum value VL By substituting the initial voltage V0' obtained through the initial voltage acquisition process into the following formula (2), the second initial phase difference P C2 [UI] at the time of execution of the initial voltage acquisition process can be obtained. In this specification, the first initial phase difference P C1 and the second initial phase difference P C2 are collectively simply referred to as "initial phase difference P C ".

[0092]

Number

[0093]

Number

[0094] That is, in the second phase difference calculation process, since the maximum value V H and the minimum value V L of the detected voltage obtained through the phase acquisition process are reused, although the accuracy of the calculation result decreases compared to the first phase difference calculation process, it is possible to significantly shorten the measurement time required to obtain the initial phase difference P C . For example, when the measurement conditions are the same as those exemplified for the phase acquisition process, the measurement time required by the initial voltage acquisition process is about 80 μs.

[0095] The phase synchronization control unit 31 performs the same phase difference calculation process for all of the 32 - lane toggle patterns simultaneously or sequentially. As a result, for example, a correspondence relationship between the lane numbers and the initial phase difference P C as shown in FIGS. 9(a) to (c) can be obtained.

[0096] Here, lane numbers 1 to 4 respectively correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-1. Lane numbers 5 to 8 respectively correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-2. Lane numbers 9 to 12 respectively correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-3. Lane numbers 13 to 16 respectively correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-4. Lane numbers 17 to 20 respectively correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-5. Lane numbers 21 to 24 respectively correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-6. Lane numbers 25 to 28 respectively correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-7. Lane numbers 29 to 32 respectively correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-8.

[0097] The phase shift processing unit 31e controls the phase adjustment unit 24 of each transceiver 20 so that the phase difference between the divided clock or external clock selected by the clock selection unit 17 and the toggle pattern is within a predetermined range, thereby shifting the phase of the toggle pattern output from each transceiver 20. Here, the value (phase difference) within the predetermined range is the value closest to 0 with the accuracy of the phase adjustment range adjustable by the phase adjustment unit 24.

[0098] The phase shift processing unit 31e performs a first phase shift process of shifting the phase of the toggle pattern output from each transceiver 20 by the first initial phase difference P C1 from the initial value at the start of the phase acquisition process, and a second phase shift process of shifting the phase of the toggle pattern shifted by the first phase shift process by the second initial phase difference P C2 . In this specification, the first phase shift process and the second phase shift process are collectively referred to simply as the "phase shift process".

[0099] Hereinafter, with reference to FIGS. 9(a) to 9(c), the phase shift processing of the toggle pattern of each lane by the phase shift processing unit 31e will be described.

[0100] FIG. 9(a) shows a case where the initial phase difference P of the toggle patterns output from the transceivers 20 of all lanes C is positively distributed and the distribution width is less than 0.5 UI. In this case, the phase shift processing unit 31e shifts the phases of the toggle patterns of all lanes by -P C toward 0. The same applies when the initial phase difference P of all lanes C is negatively distributed.

[0101] FIG. 9(b) shows a case where the initial phase difference P of the toggle patterns output from the transceivers 20 of each lane C is distributed either positively or negatively and the distribution width is less than 0.5 UI. In this case, the phase shift processing unit 31e shifts the phase of the toggle pattern distributed positively by -P C toward 0, and shifts the phase of the toggle pattern distributed negatively by -P C toward 0.

[0102] FIG. 9(c) shows a case where the initial phase difference P of the toggle patterns output from the transceivers 20 of each lane C is distributed either positively or negatively, and the positive distribution and the negative distribution are separated by 0.5 UI or more. In this case, it is considered that a part of the distribution of the initial phase difference P that should be within a width of less than 0.5 UI is apparently shifted by 1 UI. Therefore, the phase shift processing unit 31e, for example, shifts the phase of the toggle pattern distributed positively by 1 + P C in the positive direction toward 0, and shifts the phase of the toggle pattern distributed negatively by -P C in the positive direction toward 0. C

[0103] As can be seen from FIGS. 9(a) to 9(c), the four transceivers 20 included in the same transceiver unit 12 have similar initial phase differences P C ​shows the distribution. In such a case, for only one transceiver 20 included in each transceiver unit 12, a phase acquisition process, an initial voltage acquisition process, and a phase difference calculation process are performed, and the obtained initial phase difference P C may be regarded as a common initial phase difference among the four transceivers 20 included in each transceiver unit 12.

[0104] The division ratio setting unit 33 is configured to set the division ratio of the divided clock based on the external clock to the divided clock output unit 14. The phase synchronization control unit 31 repeatedly executes the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio by the division ratio setting unit 33.

[0105] In the prior art, the division ratio was an integer power of 2 and was repeatedly halved, changing in the order of, for example, 64, 32, 16, 8, 4, 2.

[0106] In the signal generation device 1 of the present embodiment, the division ratio is, for example, an integer power of 2 or 4, and the minimum value is 4 or less. The division ratio setting unit 33 repeatedly decreases the division ratio by a factor of 1 / 4. For example, when the maximum value of the division ratio is 64, the division ratio setting unit 33 changes the division ratio in the order of 64, 16, 4. Also, for example, when the maximum value of the division ratio is 32, the division ratio setting unit 33 changes the division ratio in the order of 32, 8, 2.

[0107] Compared with the prior art in which the division ratio is decreased by 1 / 2, the signal generation device 1 of the present embodiment can speed up the process of aligning the maximum phase difference between the toggle patterns of each lane to an accuracy of 0.1 UI or less based on the divided clock by decreasing the division ratio by 1 / 4, and can reduce the time required for phase alignment between lanes.

[0108] Note that as long as the maximum phase difference between the toggle patterns of each lane can be adjusted to an accuracy of 0.1 UI or less based on the divided clock, the division ratio is not limited to 1 / 4, and may be the reciprocal of an integer power of 2 such as 1 / 8, 1 / 16, etc.

[0109] FIG. 10 is a diagram showing, for 1 UI of the divided clock, the ratio of the amount of phase shift of the toggle pattern due to the phase acquisition process to the capacity of the FIFO 21 for each division ratio when the phase of the toggle pattern is moved in the range of -0.75 UI to +0.75 UI. For example, the capacity of the FIFO 21 is equivalent to 128 UI when one clock of the external clock is set to 1 UI, and is equivalent to 2 UI (±1 UI) for the divided clock obtained by dividing the external clock by a maximum of 64.

[0110] When the division ratio is 64, 75% of the capacity of the FIFO 21 is used for the phase shift of the toggle pattern. Thereafter, each time the division ratio becomes 1 / 4, the amount of movement also becomes 1 / 4, and when the division ratio is 1, the amount of movement is equivalent to 1.17% of the capacity of the FIFO 21.

[0111] The rate control unit 34 controls each transceiver 20 to output a toggle pattern having a frequency that is half the frequency of the divided clock or the external clock selected by the clock selection unit 17 as 1-bit serial data output from each transceiver 20. For example, the rate control unit 34 causes the parallel data output unit 11 to output N-bit parallel data such that the frequency of the toggle pattern output from each transceiver 20 is half the frequency of the divided clock or the external clock.

[0112] The clock selection signal output unit 35 outputs a clock selection signal for selecting either the external clock or the divided clock to the clock selection unit 17. Specifically, the clock selection signal output unit 35 outputs a clock selection signal for causing the clock selection unit 17 to select the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio set by the division ratio setting unit 33 is equal to or less than a predetermined value set in advance. The minimum value of the division ratio is, for example, an integer of 4 or less.

[0113] Next, a signal generation method using the signal generator 1 of the present embodiment will be described with reference to the flowcharts of FIGS. 11, 12(a), (b), and (c), and an example of the processing will be explained. Note that descriptions overlapping with the description of the configuration of the signal generator 1 described above will be omitted as appropriate. The processing shown in this flowchart is performed for all of the outputs of 32 lanes, respectively.

[0114] When each transceiver unit 12 is activated or reset (step S11: YES), the phase synchronization control unit 31 executes usage control processing (step S12). For example, when the bit rate of the PAM signal output from the signal generator 1 is changed by an operation input to the operation unit 65 by the user, each transceiver unit 12 is reset. By the usage control processing, the usage amounts of the FIFOs 21 of the respective transceivers 20 are made uniform at half.

[0115] FIG. 13 is a diagram schematically showing an example of the phase relationship of the toggle patterns output from the transceivers 20 of each lane after the usage control processing. The vertical broken line in the figure indicates the rising timing of the external clock. Each transceiver unit 12 includes four lanes from lane 0 to lane 3. "Ch1 Lane0", "Ch1 Lane2", "Ch4 Lane0", and "Ch7 Lane3" in the figure indicate lane 0 of the transceiver unit 12-1, lane 2 of the transceiver unit 12-1, lane 0 of the transceiver unit 12-4, and lane 3 of the transceiver unit 12-7, respectively. The data indicated by "0" in the toggle pattern of each lane should be in the same phase in all lanes. The same notation will be used in the following figures. After the usage control processing, the phases of the toggle patterns of each lane are normally shifted from each other by more than one clock of the external clock.

[0116] Next, the clock selection unit 17 selects a divided clock (divided clock selection step S13).

[0117] Next, the frequency division ratio setting unit 33 sets the value of the frequency division ratio of the frequency division clock in the frequency division clock output unit 14 to 64 (frequency division ratio setting step S14). At this time, there is a phase difference between the frequency division clock and the external clock, but there is no need to consider it at this point.

[0118] Next, the FPGA control unit 15 executes global phase measurement processing using the frequency division clock (step S15). As shown in FIG. 12(a), the processing in step S15 includes the processing in steps S31 to S33.

[0119] In step S31, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency that is half the frequency of the frequency division clock whose frequency division ratio is set to 64 in the frequency division ratio setting step S14 (rate control step S31).

[0120] Next, while changing the phase of the toggle pattern output from each transceiver 20 in the range of -0.75UI to +0.75UI from the initial value with one cycle of the frequency division clock having a frequency division ratio of 64 as 1UI, the phase acquisition processing unit 31b acquires the initial value V0, the maximum value V H , and the minimum value V L of the detected voltage output from the phase detector 40, and executes phase acquisition processing (phase acquisition processing step S32).

[0121] Next, the phase difference calculation processing unit 31d, based on the initial value V0, the maximum value V H , and the minimum value V L of the detected voltage acquired in the phase acquisition processing step S32, executes first phase difference calculation processing for calculating the first initial phase difference P C1 between the frequency division clock having a frequency division ratio of 64 and the initial value of the phase of the toggle pattern output from each transceiver 20 (phase difference calculation processing step S33).

[0122] FIG. 14(a) shows the first initial phase difference P C1It is a diagram that simplifies and shows the timing of the toggle pattern for each lane immediately after it is calculated. At this time, if the maximum phase difference between the toggle patterns of each lane is 32 UI or less based on the external clock reference, the subsequent phase shift processing can be executed without errors.

[0123] Next, the phase shift processing unit 31e adjusts the phase of the toggle pattern from the initial value by the first initial phase difference P so that the phase difference between the divided clock with the division ratio set to 64 in the division ratio setting step S14 and the toggle pattern output from each transceiver 20 becomes a value within a predetermined range. C1 Execute the first phase shift processing to move by the amount of (phase shift processing step S16).

[0124] FIG. 14(b) is a diagram that simplifies and shows the timing of the toggle pattern for each lane immediately after the phase is shifted by the first phase shift processing when the division ratio of the divided clock is 64. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI or less based on the divided clock reference, that is, 6.4 UI (0.1 UI × 64 division) or less based on the external clock reference.

[0125] If the current division ratio is greater than 4 (step S17: NO), the division ratio setting unit 33 sets the division ratio of the divided clock in the divided clock output unit 14 to a value that is 1 / 4 of the current value (division ratio setting step S18).

[0126] Next, the FPGA control unit 15 executes the current phase measurement processing (step S19). As shown in FIG. 12(c), the processing in step S19 includes the processing in steps S37 to S39.

[0127] In step S37, the rate control unit 34 causes each transceiver 20 to output a toggle pattern with a frequency that is half of the frequency of the divided clock with the division ratio set in the division ratio setting step S18 (rate control step S37).

[0128] Next, the initial voltage acquisition processing unit 31c executes an initial voltage acquisition process of acquiring the detected voltage output from the phase detector 40 as the initial voltage V0' (initial voltage acquisition process step S38).

[0129] Next, the phase difference calculation processing unit 31d, based on the maximum value V H and the minimum value V L of the detected voltage acquired in the phase acquisition process step S32, and the initial voltage V0' acquired in the initial voltage acquisition process step S38, calculates the second initial phase difference P C2 between the divided clock selected by the clock selection unit 17 and the phase of the toggle pattern output from each transceiver 20, and executes a second phase difference calculation process (phase difference calculation process step S39).

[0130] Next, in step S16, the phase shift processing unit 31e moves the phase of the toggle pattern by the amount of the second initial phase difference P C2 from the current value so that the phase difference between the divided clock with the division ratio set in the division ratio setting step S18 and the toggle pattern output from each transceiver 20 becomes a value within a predetermined range, and executes a second phase shift process (phase shift process step S16). Then, the processes after step S17 are executed again.

[0131] That is, steps S16 to S19 are steps of repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio in the division ratio setting step S18.

[0132] FIG. 15(a) is a diagram simply showing the timings of the toggle patterns of each lane immediately after the second initial phase difference P C2 is calculated by the second phase difference calculation process when the division ratio of the divided clock decreases by 1 / 4 from 64 to reach 4 by the division ratio setting unit 33.

[0133] FIG. 15(b) is a diagram schematically showing the timing of the toggle pattern of each lane immediately after the phase is shifted by the second phase shift process when the division ratio of the divided clock is 4. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to be 0.1 UI or less based on the divided clock, that is, 0.4 UI (0.1 UI × 4 division) or less based on the external clock.

[0134] On the other hand, when the current division ratio is 4 or less (step S17: YES), the clock selection unit 17 selects an external clock instead of the divided clock (external clock selection step S20). The external clock corresponds to a divided clock with a division ratio of 1, but its phase does not match that of the normal divided clock.

[0135] Next, the FPGA control unit 15 executes global phase measurement processing using the external clock (step S21). As shown in FIG. 12(b), the processing in step S21 includes the processing in steps S34 to S36.

[0136] In step S34, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency half that of the external clock (rate control step S34).

[0137] Next, the phase acquisition processing unit 31b changes the phase of the toggle pattern output from each transceiver 20 from the initial value within the range of -0.75 UI to +0.75 UI with one cycle of the external clock as 1 UI, and based on the initial value V0, the maximum value V H , and the minimum value V L of the detection voltage output from the phase detector 40, executes a phase acquisition process for acquisition (phase acquisition process step S35).

[0138] Next, the phase difference calculation processing unit 31d, based on the initial value V0, the maximum value V H , and the minimum value V L of the detection voltage acquired in the phase acquisition process step S35, calculates the first initial phase difference P C1Execute the first phase difference calculation process for calculating (phase difference calculation process step S36).

[0139] Figure 16(a) shows the timing of the toggle pattern of each lane immediately after the first initial phase difference P is calculated by the first phase difference calculation process when an external clock is selected by the clock selection unit 17. C1 It is a diagram showing in a simplified manner the timing of the toggle pattern of each lane immediately after the first initial phase difference P is calculated by the first phase difference calculation process when an external clock is selected by the clock selection unit 17.

[0140] Next, the phase shift processing unit 31e moves the phase of the toggle pattern from the initial value by the amount of the first initial phase difference P so that the phase difference between the external clock selected in the external clock selection step S20 and the toggle pattern output from each transceiver 20 becomes a value within a predetermined range. Execute the first phase shift process for moving (phase shift process step S22). C1 Execute the first phase shift process for moving (phase shift process step S22).

[0141] Figure 16(b) is a diagram showing in a simplified manner the timing of the toggle pattern of each lane immediately after the phase is shifted by the first phase shift process when an external clock is selected by the clock selection unit 17. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1UI (0.1UI × frequency division) or less based on the external clock.

[0142] Then, the phase synchronization control unit 31 waits again until each transceiver unit 12 is activated or reset (step S11).

[0143] In step S11, it is assumed that the processing after step S12 is automatically executed when each transceiver unit 12 is activated or reset, but the present invention is not limited to this. For example, in step S11, the user can press an execution button provided on an operation screen (not shown) of the signal generator 1 via the operation unit 65, so that the user can execute the processing after step S12 at an arbitrary timing. It may be possible.

[0144] When the phase adjustment of the toggle pattern output from each transceiver 20 is completed in step S22, the FPGA control unit 15 automatically shifts to the mode of generating the PAM signal during normal operation, and causes the parallel data output unit 11 to output the N-bit parallel data for normal operation according to the frequency of the external clock.

[0145] As described above, the signal generation method using the signal generation apparatus 1 of the present embodiment initially uses the divided clock with a large division ratio to roughly adjust the phase of the toggle pattern of each lane with a large movement amount, and finally uses the external clock corresponding to a division ratio of 1 to finely adjust the phase of the toggle pattern of each lane with a small movement amount.

[0146] In the processes of steps S16 to S19 of repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio, as the frequencies of the clock and the toggle pattern increase, the maximum value V of the detected voltage H and the minimum value V L are assumed to change somewhat. For this reason, the signal generation method using the signal generation apparatus 1 of the present embodiment re-measures the relationship between the detected voltage and the phase of the toggle pattern as shown in FIG. 8 by the global phase measurement process using the external clock in step S21, and obtains the maximum value V of the detected voltage corresponding to the frequency of the external clock H and the minimum value V L as described above.

[0147] As described above, the signal generation apparatus 1 according to the present embodiment repeatedly executes the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio of the divided clock by the division ratio setting unit 33.

[0148] With this configuration, the signal generation apparatus 1 according to the present embodiment can reduce the maximum phase difference between the serial data output from each of the plurality of transceivers 20 to 0.1 UI or less based on the external clock.

[0149] Also, the signal generation device 1 according to the present embodiment calculates the second initial phase difference P between the maximum value V of the detected voltage obtained by one phase acquisition process, the minimum value V, the current initial voltage V0' obtained by the initial voltage acquisition process, the divided clock selected by the clock selection unit 17, and the phase of the toggle pattern shifted by the phase shift processing unit 31e. H and the minimum value V L Based on this, the signal generation device 1 according to the present embodiment reduces the number of times of the phase acquisition process to one time. Therefore, compared with the prior art that repeats the phase acquisition process every time the division ratio changes, the time required for phase alignment between lanes can be shortened. C2 is calculated to be.

[0150] Specifically, the signal generation device 1 according to the present embodiment can reduce the total measurement time required for generating the digital data of the detected voltage by the ADC 55 in the phase acquisition process and the initial voltage acquisition process by about 70% compared with the prior art by reducing the number of times of the phase acquisition process to one time.

[0151] On the other hand, the total phase shift time required for the phase shift of the toggle pattern in the phase acquisition process and the phase shift process is about 1 / 100 of the total measurement time, and the measurement time is dominant in the overall required time. Therefore, the signal generation device 1 according to the present embodiment can also expect a reduction effect of about 70% on the overall required time.

[0152]

[0153] In addition, the signal generation device 1 according to the present embodiment can significantly increase the maximum phase difference that enables phase alignment between the serial data output from the plurality of transceivers 20 after startup or reset.

[0154] ​For example, the signal generator 1 according to the present embodiment can set the maximum phase difference that can be phase-matched between the serial data from each transceiver 20 to 32 UI based on an external clock reference. This value corresponds to 1000 ps if, for example, the data rate is 32 Gbps. For example, since the phase error on the data sheet of the GTY transceiver of Xilinx's UltraScale+ is 500 ps, the signal generator 1 according to the present embodiment can converge this phase error.

[0155] Furthermore, since the signal generator 1 according to the present embodiment does not require an additional mechanism such as a delay circuit outside the FPGA to suppress the phase difference between the serial data before adjustment to within 1 UI in advance, it is not necessary to investigate the parameters given to the additional mechanism after product manufacturing.

[0156] Note that the signal generator 1 according to the present embodiment requires ADC55 for each lane. However, since their required speed performance is low (several hundred ksps to several Msps), it is also possible to use an ADC with multiple input channels, and miniaturization of the ADC peripheral circuit can be expected. Furthermore, since the signal generator 1 according to the present embodiment does not require an external delay circuit, it is also possible to reduce the circuit scale and the board size.

[0157] Also, the signal generator 1 according to the present embodiment is configured to execute a usage control process for aligning the usage amounts of the FIFOs 21 in all lanes to half before starting the global phase measurement process using the divided clock including the phase acquisition process. As a result, the signal generator 1 according to the present embodiment can, for example, when the usage amount of the FIFO 21 is equivalent to 2 UI of the divided clock with the maximum division ratio, move the phase of the toggle pattern in both the positive and negative directions within a range of up to -1 UI to +1 UI during the phase acquisition process.

Explanation of Reference Numerals

[0158] 1 Signal generator 10 Data output unit 11 Parallel data output unit 12, 12-1 to 12-8 Transceiver unit 14 Divide-by-N Clock Output Section 15 FPGA Control Section 17 Clock Selection Section 20, 20-0 to 20-3 Transceiver 21 FIFO 22 PISO 23 Usage Determination Section 24 Phase Adjustment Section 31 Phase Synchronization Control Section 31a Usage Control Processing Section 31b Phase Acquisition Processing Section 31c Initial Voltage Acquisition Processing Section 31d Phase Difference Calculation Processing Section 31e Phase Shift Processing Section 33 Divide Ratio Setting Section 34 Rate Control Section 40 Phase Detector

Claims

1. A parallel data output unit (11) that outputs parallel data of a plurality of bits; It has a FIFO (21) that stores N-bit parallel data among the parallel data of the plurality of bits output from the parallel data output unit, and a plurality of transceivers (20) that convert the N-bit parallel data stored in the FIFO into 1-bit serial data; A phase synchronization control unit (31) that controls the phase of the 1-bit serial data converted by each of the transceivers; A divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock; A division ratio setting unit (33) that sets a division ratio of the divided clock to the divided clock output unit; A clock selection unit (17) that selects either the external clock or the divided clock; A rate control unit (34) that controls to output, from each of the transceivers, a toggle pattern having a frequency half of the frequency of the divided clock or the external clock selected by the clock selection unit as the 1-bit serial data; A phase detector (40) that outputs a detection voltage corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern; and is provided with The phase synchronization control unit is A phase acquisition processing unit (31b) that executes a phase acquisition process of acquiring an initial value, a maximum value, and a minimum value of the detection voltage output from the phase detector while changing the phase of the toggle pattern from an initial value; Based on the initial value, the maximum value, and the minimum value of the detection voltage acquired by the phase acquisition processing unit, a first phase difference calculation process for calculating a first initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern is executed by a phase difference calculation processing unit (31d); A phase shift processing unit (31e) that shifts the phase of the toggle pattern so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern is within a predetermined range; An initial voltage acquisition processing unit (31c) that executes an initial voltage acquisition process of acquiring the detection voltage output from the phase detection unit as an initial voltage after the phase of the toggle pattern is shifted by the phase shift processing unit; The phase difference calculation processing unit further executes a second phase difference calculation process of calculating a second initial phase difference between the divided clock selected by the clock selection unit and the phase of the toggle pattern shifted by the phase shift processing unit based on the maximum value and the minimum value of the detection voltage acquired by the phase acquisition processing unit and the initial voltage acquired by the initial voltage acquisition processing unit; The phase shift processing unit executes a first phase shift process of shifting the phase of the toggle pattern by the amount of the first initial phase difference from the initial value, and a second phase shift process of shifting the phase of the toggle pattern shifted by the first phase shift process by the amount of the second initial phase difference; The phase synchronization control unit repeatedly executes the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio by the division ratio setting unit; The clock selection unit is characterized in that, when the division ratio is equal to or less than a predetermined value determined in advance, after the first phase shift process or the second phase shift process is executed, the external clock is selected instead of the divided clock.

2. The signal generation device according to claim 1, wherein the clock selection unit selects the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is 4 or less.

3. Each of the transceivers A PISO (22) that converts the N-bit parallel data read from the FIFO according to the read clock signal into the 1-bit serial data, A usage amount determination unit (23) that executes first and second usage amount determination processes for determining whether the usage amount of the FIFO is equal to or greater than a usage amount threshold value, A phase adjustment unit (24) that executes a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount, The phase synchronization control unit further includes a usage amount control processing unit (31a) that executes a usage amount control process for controlling the usage amount of the FIFO before the phase acquisition process is executed by the phase acquisition processing unit, The usage amount control process of the usage amount control processing unit is as follows: A process of causing the usage amount determination unit to execute the first usage amount determination process on the condition that the output of the serial data from each of the transceivers has started, A process of causing the phase adjustment unit to execute the first phase adjustment process on the condition that it is determined by the first usage amount determination process that the usage amount of the FIFO of each transceiver is equal to or greater than the usage amount threshold value, A process of causing the usage amount determination unit to execute the second usage amount determination process on the condition that the number of consecutive determinations by the first usage amount determination process that the usage amount of the FIFO of each transceiver is less than the usage amount threshold value has reached a first determination number, A process of causing the phase adjustment unit to execute the second phase adjustment process on the condition that it is determined by the second usage amount determination process that the usage amount of the FIFO of each transceiver is less than the usage amount threshold value, The signal generation device according to claim 1 or claim 2, characterized by including a process of causing the phase adjustment unit to end the adjustment of the phase of the read clock signal on the condition that the number of consecutive determinations by the second usage amount determination process that the usage amount of the FIFO of each transceiver is equal to or greater than the usage amount threshold value has reached a second determination number.

4. A parallel data output unit (11) that outputs parallel data of a plurality of bits; It has a FIFO (21) that stores N-bit parallel data among the parallel data of the plurality of bits output from the parallel data output unit, and a plurality of transceivers (20) that convert the N-bit parallel data stored in the FIFO into 1-bit serial data; A divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock; A clock selection unit (17) that selects either the external clock or the divided clock; A signal generation method for controlling the phase of the 1-bit serial data converted by each of the transceivers using a signal generation device (1) including a phase detection unit (40) that outputs a detection voltage corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the 1-bit serial data, comprising: A division ratio setting step (S14, S18) of setting the division ratio of the divided clock in the divided clock output unit; A rate control step (S31, S37) of causing each of the transceivers to output a toggle pattern having a frequency that is half the frequency of the divided clock or the external clock selected by the clock selection unit as the 1-bit serial data; A phase acquisition processing step (S32, S35) of executing a phase acquisition process of acquiring an initial value, a maximum value, and a minimum value of the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; A phase difference calculation processing step (S33, S36, S39) of executing a first initial phase difference calculation for calculating a first initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the initial value, the maximum value, and the minimum value of the detection voltage acquired in the phase acquisition processing step; A phase shift processing step (S16, S22) of shifting the phase of the toggle pattern so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern becomes a value within a predetermined range; An initial voltage acquisition processing step (S38) of executing an initial voltage acquisition process of acquiring, as an initial voltage, the detection voltage output from the phase detector after the phase of the toggle pattern is shifted by the phase shift processing step; The phase difference calculation processing step further executes a second phase difference calculation process of calculating a second initial phase difference between the divided clock selected by the clock selection unit and the phase of the toggle pattern shifted by the phase shift processing step, based on the maximum value and the minimum value of the detection voltage acquired by the phase acquisition processing step and the initial voltage acquired by the initial voltage acquisition processing step; The phase shift processing step executes a first phase shift process of shifting the phase of the toggle pattern by the amount of the first initial phase difference from the initial value, and a second phase shift process of shifting the phase of the toggle pattern shifted by the first phase shift process by the amount of the second initial phase difference; The signal generation method is as follows: A step (S16 to S19) of repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio by the division ratio setting step; An external clock selection step (S20) of selecting the external clock instead of the divided clock by the clock selection unit after the first phase shift process or the second phase shift process is executed when the division ratio is equal to or less than a predetermined value determined in advance. The signal generation method according to claim 4, further comprising the above.

5. The external clock selection step is characterized in that the external clock is selected instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is 4 or less. The signal generation method according to claim 4.

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