Display device and method of controlling the display device

Abstract

To improve the reliability of a display device by detecting defects in the display device.SOLUTION: A sensing circuit is configured to in response to applying a first reference voltage to a subpixel via a reference line during a first sensing period, acquire a first sensing voltage charged in the reference line as a first sampling value when the switching and sensing transistors are turned on and acquire the first sensing voltage charged in the reference line as a second sampling value when the switching and sensing transistors are turned off, and the timing controller determines that a display device has a defect on the basis of the first difference value between the first sampling value and the second sampling value.SELECTED DRAWING: Figure 13

Description

Technical Field

[0001] This specification relates to a display device and a method of controlling the display device.

Background Art

[0002] As information technology develops, the market for display devices, which are the connection medium between users and information, is growing. As a result, the use of display devices such as light emitting display devices (LED), quantum dot display devices (QDD), and liquid crystal display devices (LCD) is increasing.

[0003] The above-described display device includes a display panel including sub-pixels, a driving unit that outputs a driving signal for driving the display panel, a power supply unit that generates a power supply to be supplied to the display panel or the driving unit, and the like.

[0004] When a driving signal, such as a scan signal or a data signal, is supplied to the sub-pixels formed on the display panel of such a display device, the selected sub-pixels can transmit light or directly emit light, thereby displaying an image.

Summary of the Invention

Problems to be Solved by the Invention

[0005] This specification improves the driving stability and driving reliability of a display device.

Means for Solving the Problems

[0006] This specification relates to a display device including a display panel including a sub-pixel having a switching transistor connected to a data line and a sensing transistor connected to a reference line, a driving circuit connected to the data line, a sensing circuit connected to the reference line, and a timing controller for controlling at least one of the driving circuit and the sensing circuit. The sensing circuit obtains, as a first sampling value, a first sensing voltage charged on the reference line during a period in which the switching transistor and the sensing transistor are turned on, in response to applying a first reference voltage to the sub-pixel via the reference line in a first sensing period. The sensing circuit obtains, as a second sampling value, the first sensing voltage charged on the reference line during a period in which the switching transistor and the detection transistor are turned off. The timing controller may provide a display device that determines that the display device has a defect based on a first difference value between the first sampling value and the second sampling value.

[0007] The sensing circuit obtains, as a third sampling value, a second sensing voltage charged on the reference line during a period in which the second reference voltage is applied to the reference line, in response to applying, via the reference line, a second reference voltage different from the first reference voltage to the sub-pixel in a second sensing period in which the switching transistor and the sensing transistor are turned off. The sensing circuit may obtain, as a fourth sampling value, the second sensing voltage charged on the reference line during a period in which the second reference voltage is not applied to the reference line.

[0008] The display device further includes a data driving unit including the driving circuit and the sensing circuit, and the timing controller may determine that the display device has a defect based on a second difference value between the third sampling value and the fourth sampling value.

[0009] The second sensing period is scheduled to be executed when the first difference value is greater than a predetermined value. When the first difference value is smaller than the predetermined value, the second sensing period may be skipped or scheduled not to be executed.

[0010] The first sensing period and the second sensing period may be included in a driving start period in which power is applied to the display panel.

[0011] The first sensing period and the second sensing period may be included in a driving end period in which an instruction to cut off the power applied to the display panel is given.

[0012] The first sensing period is included in a driving start period in which power is applied to the display panel, and the second sensing period may be included in a driving end period in which an instruction to cut off the power applied to the display panel is given.

[0013] In another aspect, the present specification provides a method for controlling a display device, including: applying a first reference voltage to a reference line connected to a sub-pixel included in a display panel of the display device by a sensing circuit included in the display device; obtaining, by the sensing circuit, a first sampled value of the first reference voltage charged in the reference line during a period when a switching transistor and a sensing transistor included in the sub-pixel are turned on, and obtaining, as a second sampled value, the first reference voltage charged in the reference line during a period when the switching transistor and the sensing transistor are turned off; and determining, by a timing controller of the display device, that there is a defect in the display device based on a first difference value between the first sampled value and the second sampled value.

[0014] When the switching transistor and the sensing transistor are turned off, applying a second reference voltage different from the first reference voltage via the reference line; and obtaining, as a third sampling value, a second sensing voltage charged on the reference line during a period in which the second reference voltage is applied to the reference line, and obtaining, as a fourth sampling value, the second sensing voltage charged on the reference line during a period in which the second reference voltage is not applied to the reference line.

[0015] Based on a second difference value between the third sampling value and the fourth sampling value, it can be determined that the display device has a defect.

Advantages of the Invention

[0016] This specification improves the lifespan of a display device through a compensation operation of elements included in sub-pixels that make up a display panel, detects the presence or absence of defects in the entire display device including the display panel and the driving unit, and can improve the stability and reliability of the display device.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Mode for Carrying Out the Invention

[0018] This specification can be implemented in, but not limited to, televisions, video players, personal computers (PCs), home theaters, automotive electrical equipment, smartphones, etc. This specification can be composed of a light emitting display device (Light Emitting Display Device; LED), a quantum dot display device (Quantum Dot Display Device; QDD), a liquid crystal display device (Liquid Crystal Display Device; LCD), etc. However, for the sake of convenience of explanation below, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is taken as an example.

[0019] FIG. 1 is a block diagram schematically showing a light emitting display device, FIG. 2 is a configuration diagram schematically showing the sub-pixels shown in FIG. 1, and FIG. 3 is an exemplary diagram of a pixel composed of sub-pixels.

[0020] As shown in FIGS. 1 to 3, the light emitting display device may include a video supply unit 110, a timing controller 120, a gate driving unit 130, a data driving unit 140, a display panel 150, a power supply unit 180, etc.

[0021] The video supply unit (set or host system) 110 can output various driving signals in addition to the video data signal supplied from the outside or the video data signal stored in the internal memory. The video supply unit 110 can supply the data signal and various driving signals to the timing controller 120.

[0022] The timing controller 120 can output a gate timing control signal GDC for controlling the operation timing of the gate driving unit 130, a data timing control signal DDC for controlling the operation timing of the data driving unit 140, various synchronization signals, etc. The timing controller 120 can supply the data signal DATA supplied from the video supply unit 110 to the data driving unit 140 together with the data timing control signal DDC. The timing controller 120 may be formed in the form of an IC (Integrated Circuit) and mounted on a printed circuit board, but is not limited thereto.

[0023] The gate driving unit 130 can output a gate signal (or gate voltage) in response to the gate timing control signal GDC and the like supplied from the timing controller 120. The gate driving unit 130 can supply a gate signal to the sub-pixels included in the display panel 150 via the gate lines GL1 to GLm. The gate driving unit 130 may be formed in the form of an IC, or may be directly formed on the display panel 150 by a gate in panel method, but is not limited thereto.

[0024] The data driving unit 140 samples and latches the data signal (DATA) in response to the data timing control signal DDC and the like supplied from the timing controller 120, and can convert the digital-form data signal into an analog-form data voltage based on the gamma reference voltage and output it. The data driving unit 140 can supply a data voltage to the sub-pixels included in the display panel 150 via the data lines DL1 to DLn. The data driving unit 140 is formed in the form of an IC and may be mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0025] The power supply unit 180 can generate a high-potential first power supply and a low-potential second power supply based on an external input voltage supplied from the outside. The power supply unit 180 can output the first power supply via the first power supply line EVDD and output the second power supply via the second power supply line EVSS. The power supply unit 180 can generate and output not only the first power supply and the second power supply, but also voltages necessary for driving the gate driving unit 130 (for example, a scan high voltage and a scan low voltage) and voltages necessary for driving the data driving unit 140 (a drain voltage and a half drain voltage).

[0026] The display panel 150 can display an image corresponding to a driving signal including a gate signal and a data voltage, the first power supply, the second power supply, and the like. The sub-pixels of the display panel 150 can emit light directly. The display panel 150 can be manufactured based on a rigid or ductile substrate such as glass, silicon, or polyimide. For example, one sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power supply line EVDD, and a second power supply line EVSS, and can include a pixel circuit composed of a switching transistor, a driving transistor, a capacitor, an organic light emitting diode, and the like.

[0027] Since the sub-pixel SP used in the light-emitting display device emits light directly, the circuit configuration is complicated. In addition to the organic light emitting diode that emits light, there are also various compensation circuits for compensating for the deterioration of driving transistors and the like that supply the driving current necessary for driving the organic light emitting diode. Therefore, please refer to the fact that the sub-pixel SP is simply shown in the form of a block.

[0028] The light-emitting sub-pixels can be composed of pixels including red, green, and blue or pixels including red, green, blue, and white. For example, one pixel P may include a red sub-pixel SPR connected to a first data line DL1, a white sub-pixel SPW connected to a second data line DL2, and is connected to a third data line DL3. It may include a green sub-pixel SPG and a blue sub-pixel SPB connected to a fourth data line DL4. The red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB may be commonly connected to a first reference line VREF1. The first reference line VREF1 can be used to detect degradation of elements included in one of the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB, and will be described below.

[0029] On the other hand, in the above description, the timing controller 120, the gate driving unit 130, the data driving unit 140, etc. were described as if they were individual configurations. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, the gate driving unit 130, and the data driving unit 140 can be integrated into one IC. Note that the timing controller 120, the gate driving unit 130, the data driving unit 140, the power supply unit 180, and the display panel 150 can be defined as a display module as an aggregate for displaying an image.

[0030] Note that in the above, the pixel P arranged in the order of the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB was shown as an example. However, depending on the implementation method of the light-emitting display device, the arrangement order and direction of the sub-pixels can change.

[0031] FIG. 4 and FIG. 5 are diagrams for explaining the configuration of the gate driving unit of the gate-in-panel method, and FIG. 6 is a diagram showing an arrangement example of the gate driving unit of the gate-in-panel method.

[0032] As shown in FIG. 4, the gate-in-panel type gate driving unit may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a driving clock signal Clks, a start signal Vst, etc. based on signals and voltages output from the timing controller 120 and the power supply unit 180.

[0033] The shift register 131 operates based on signals (Clks, Vst, etc.) output from the level shifter 135, and may output gate signals (Gate[1]~Gate[m]) that can turn on or off transistors formed on the display panel. The shift register 131 may be formed in a thin film shape on the display panel by the gate-in-panel method.

[0034] As shown in FIGS. 4 and 5, unlike the shift register 131, the level shifter 135 may be independently formed in an IC form, or may be included inside the power supply unit 180. However, this is only an example and is not limited thereto.

[0035] As shown in FIG. 6, the shift registers 131a and 131b that output gate signals from the gate-in-panel type gate driving unit may be arranged in the non-display area NA of the display panel 150. The shift registers 131a and 131b are exemplified as being arranged in the left and right non-display areas NA of the display panel 150, but they may also be arranged in the upper and lower non-display areas NA of the display panel 150. They may be arranged within the display area AA of the display panel 150.

[0036] FIG. 7 is an exemplary diagram briefly showing a sub-pixel and a data driving unit according to the first example of the embodiment, FIG. 8 is an exemplary diagram briefly showing a sub-pixel and a data driving unit according to the second example of the embodiment, and FIG. 9 is a waveform diagram for explaining a sensing period and a display period shown in the embodiment.

[0037] As shown in FIG. 7, according to the first example, one sub-pixel SP may include a switching transistor SW, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light emitting diode OLED.

[0038] The driving transistor DT may have its gate electrode connected to the first electrode of the capacitor CST, its first electrode connected to the first power supply line EVDD, and its second electrode connected to the anode electrode of the organic light-emitting diode OLED. The capacitor CST has its first electrode connected to the gate electrode of the driving transistor DT and its second electrode connected to the anode electrode of the organic light-emitting diode OLED. The organic light-emitting diode OLED has its anode electrode connected to the second electrode of the driving transistor DT and its cathode electrode connected to the second power supply line EVSS.

[0039] The switching transistor SW may have its gate electrode connected to the first scan line Gate1 included in the first gate line GL1, its first electrode connected to the first data line DL1, and its second electrode connected to the gate electrode of the driving transistor DT. The sensing transistor ST may have its gate electrode connected to the second scan line Gate2 included in the first gate line GL1, its first electrode connected to the first reference line VREF1, and its second electrode connected to the anode electrode of the organic light-emitting diode OLED.

[0040] The sensing transistor ST is a kind of compensation circuit added to compensate for the degradation (such as threshold voltage, mobility, etc.) of the driving transistor DT or the organic light-emitting diode OLED. The sensing transistor ST may enable physical threshold voltage sensing based on the source follower operation of the driving transistor DT. The sensing transistor ST may operate to obtain a sensing voltage through a sensing node defined between the driving transistor DT and the organic light-emitting diode OLED.

[0041] According to one embodiment, the data driving unit 140 may include a driving circuit 141 for driving the sub-pixel SP and a sensing circuit 145 for sensing the sub-pixel SP. The driving circuit 141 is connected to the first data line DL1 via the first data channel DCH1. The driving circuit 141 may output a data voltage Vdata or the like for driving the sub-pixel SP via the first data channel DCH1.

[0042] The sensing circuit 145 is connected to the first reference line VREF1 via the first sensing channel SCH1. The sensing circuit 145 may acquire a sensing voltage Vsen sensed from the sub-pixel SP via the first sensing channel SCH1. The sensing circuit 145 may acquire the sensing voltage Vsen based on a current sensing method, a voltage sensing method, or the like.

[0043] As shown in FIG. 8, according to the second example, the first gate line GL1 may be integrated into one. That is, unlike the first example, the first gate line GL1 may not be distinguished into a first scan line and a second scan line. In this case, since the switching transistor SW and the sensing transistor ST are commonly connected to the first gate line GL1, they may be turned on or off simultaneously.

[0044] As shown in FIG. 9, the light-emitting display device according to the embodiment corresponds to a first driving period PWR_ON, a second driving period DISPLAY, and a third driving period PWR_OFF during operation for driving the display panel. Each may adopt a distinguishable driving method.

[0045] The first driving period PWR_ON corresponds to the driving start period when power is applied to the display panel. The second driving period DISPLAY corresponds to the panel driving period when driving such as video display is performed after power is applied to the display panel. The third driving period PWR_OFF may correspond to the driving end period when the power applied to the display panel is cut off. On the other hand, the third driving period PWR_OFF is a period during which the display panel is driven for a certain time while displaying black so that the sensing operation of the display panel can be performed. That is, during the third driving period (PWR_OFF), the power applied to the display panel and the like is not completely cut off.

[0046] The light-emitting display device according to the embodiment can sense the display panel in at least one of the first driving period PWR_ON, the second driving period DISPLAY, and the third driving period PWR_OFF. Taking the second driving period DISPLAY as an example, the blank period BLK included in the vertical synchronization signal Vsync may be defined as the sensing period PSP, and the active period (ACT) included in the vertical synchronization signal Vsync may be defined as the display period DSP.

[0047] FIG. 10 is an exemplary diagram showing a part of the configuration included in the data driving unit according to the embodiment, and FIGS. 11 and 12 are exemplary diagrams showing a method of sensing the display panel according to the embodiment. Hereinafter, the sub-pixel SP will be described by taking the structure shown in FIG. 7 as an example.

[0048] As in the embodiment shown in FIG. 10, the driving circuit 141 may include a digital-to-analog conversion unit DAC or the like for outputting a sensing data voltage, a black data voltage, or a display data voltage via the first data line DL1. The sensing circuit 145 may include a first voltage circuit SPRE, a second voltage circuit RPRE, a sampling circuit SAM, an analog-to-digital conversion unit ADC, etc. for outputting a voltage via the first reference line VREF1 to perform sensing.

[0049] The first voltage circuit SPRE and the second voltage circuit RPRE can perform a voltage output operation for initializing the nodes and circuits included in the sub-pixel SP or charging to a specific level of voltage. The first voltage circuit SPRE and the second voltage circuit RPRE can each include a first reference voltage source VPRES and a second reference voltage source VPRER. The first voltage circuit SPRE may output a first reference voltage based on the first reference voltage source VPRES, and the second voltage circuit RPRE may output a second reference voltage based on the second reference voltage source VPRER. The first reference voltage can be set to a voltage lower than the second reference voltage.

[0050] The sampling circuit SAM can perform a sampling operation for acquiring a sensing voltage via the first reference line VREF1. For example, the sampling circuit SAM can acquire the sensing voltage from the sensing capacitor PCAP formed on the first reference line VREF1 based on the sensing capacitor PCAP.

[0051] The analog-to-digital conversion unit ADC can convert the analog-form sensing voltage acquired by the sampling circuit SAM into a digital-form sensing voltage and output it. For example, the analog-to-digital conversion unit ADC can convert the analog-type sensing voltage charged in the sensing capacitor PCAP into a digital-type sensing voltage and output it.

[0052] The timing controller 120 may be provided with a sensing voltage (sensing data value) from the sensing circuit 145. The timing controller 120 can determine the presence or absence of degradation of the driving transistor DT and the organic light-emitting diode OLED included in the sub-pixel SP based on the sensing voltage and perform an operation for compensating for the degradation. Also, the timing controller 120 can determine the presence or absence of a defect in the light-emitting display device based on the sensing voltage and perform an operation for notifying or eliminating the defect.

[0053] As shown in FIG. 11, according to the first example, the light-emitting display device can execute a sequential sensing method of sensing from the first gate line GL1 to the M-th gate line GLm of the display panel 150. In FIG. 11, as an example, sequential sensing is performed starting from the first gate line GL1 at the upper end of the display panel 150, but the sensing may start from the M-th gate line GLm at the lower end of the display panel 150.

[0054] As shown in FIG. 12, according to the second example, the light-emitting display device can execute a random sensing method of sensing only the first gate line GLi of the display panel 150. In FIG. 12, as an example, only the first gate line GLi, which is one of the specific gate lines, is sensed, but the sensing target may be a plurality of gate lines.

[0055] FIG. 13 is a drive waveform diagram of the first sensing step for determining the presence or absence of a defect in the light-emitting display device according to the embodiment, and FIG. 14 is an illustrative diagram showing the difference between the sensing voltages sensed in the first sensing step. It is a drive waveform diagram of the second sensing step for determining the presence or absence of a defect in the light-emitting display device according to the embodiment, and FIGS. 16 and 17 are illustrative diagrams showing the operation of the device performed in the second sensing step.

[0056] As shown in FIGS. 9, 10, 13, and 14, the light-emitting display device according to the embodiment can sense the display panel over at least one of the first drive period PWR_ON, the second drive period DISPLAY, and the third drive period PWR_OFF to determine the presence or absence of a defect.

[0057] In order to make the display panel drivable at an appropriate time, an operation for determining the presence or absence of a defect in the light-emitting display device can be performed during the first driving period PWR_ON or the third driving period PWR_OFF excluding the second driving period DISPLAY. Hereinafter, as an example, it will be described that the presence or absence of a defect in the light-emitting display device is determined through the first sensing step in FIG. 13 and the second sensing step in FIG. 15. However, the first sensing step can be performed during the first driving period PWR_ON, and the second sensing step can be executed during the third driving period PWR_OFF.

[0058] As shown in FIGS. 10 and 13, the first sensing step is a step of primarily determining the presence or absence of a defect between the display panel and the data driving unit that drives the display panel based on a method of randomly sensing specific gate lines of the display panel or a method of sequentially sensing all gate lines of the display panel. The first sensing step may include a first-1 sensing period P1, a first-2 sensing period P2, and a first-3 sensing period P3. Hereinafter, the first sub-pixel is defined as the sub-pixel to be sensed, and the operations performed in the first sensing step will be described.

[0059] During the first-1 sensing period P1, a first reference voltage is applied to the first reference line VREF1 of the first sub-pixel included in the display panel. During the first-1 sensing period P1, the first voltage circuit SPRE including the first reference voltage source VPRES is turned on in response to the high-voltage first voltage circuit control signal VpreS. The first voltage circuit control signal VpreS is applied at a high voltage during the first-1 sensing period P1 and then changed to a low voltage. During the first-1 sensing period P1, the sensing node of the driving transistor DT included in the first sub-pixel can be initialized by the first reference voltage.

[0060] During the first to second sensing period P2, a sensing data voltage Sdata can be applied to the first data line DL1 of the first sub-pixel included in the display panel. During the first to second sensing period P2, a high-voltage first scan signal and a first sensing signal Scan&Sense can be applied to the first scan line Gate1 and the second scan line Gate2. The switching transistor SW and the sensing transistor ST included in the first sub-pixel can be turned on by the high-voltage first scan signal and the first sensing signal Scan&Sense. The first scan signal and the first sensing signal Scan&Sense are applied at a high voltage during the first to second sensing period P2 and then changed to a low voltage.

[0061] During the first to second sensing period P2, the driving transistor DT of the first sub-pixel can perform a source follower operation by the sensing data voltage Sdata. Due to the source follower operation of the driving transistor DT, the first sensing voltage Vsen1 applied to the sensing node of the first sub-pixel decreases to the first reference voltage level and gradually increases, and can be saturated to a voltage level close to the threshold voltage.

[0062] During the first to second sensing period P2, the sampling circuit SAM can be turned on in response to the temporarily generated first to first sampling control signal Sam1-1. During the first to second sensing period P2, the sampling circuit SAM and the like can acquire the first sensing voltage Vsen1 applied to the sensing node of the first sub-pixel as the first sampling value a. The first to first sampling control signal Sam1-1 is applied at a high voltage in the second half of the first to second sensing period P2 and then can be changed to a low voltage. The first to first sampling control signal Sam1-1 may be temporarily generated from the time when the first sensing voltage Vsen1 is saturated to a level close to the threshold voltage of the driving transistor DT until the first scan signal and the first sensing signal (Scan&Sense) change to a low voltage.

[0063] During the first to third sensing periods P3, the sampling circuit SAM can be turned on in response to the temporarily generated first to second sampling control signals Sam1-2. During the first to third sensing periods P3, the sampling circuit SAM or the like can obtain the first sensing voltage Vsen1 applied to the sensing node of the first sub-pixel as the second sampling value b. The first to second sampling control signals Sam1-2 are applied at a high voltage during the first to third sensing periods P3 and can then be changed to a low voltage. The first to second sampling control signals Sam1-2 can be temporarily generated after a certain delay time after the first scan signal and the first sensing signal Scan&Sense are changed to a low voltage.

[0064] The light-emitting display device according to the embodiment can primarily determine the presence or absence of a defect between the display panel and the data driving unit that drives the display panel through comparison of the first sampling value (a) and the second sampling value (b). At this time, the determination procedure can be performed by the timing controller 120 provided with the first sensing voltage (Vsen1) in digital form for the first sampling value (a) and the second sampling value (b), or by the video supply unit corresponding to a device higher than the timing controller.

[0065] As shown in FIG. 14, when there is a first voltage difference value (ΔV) between the first sampling value (a) and the second sampling value (b) obtained in the two sensing processes, the timing controller 120 can store in the memory the number of the gate line where the first voltage difference value ΔV occurred or the position of the sub-pixel where the difference value occurred. On the other hand, when there is no first voltage difference value ΔV between the first sampling value (a) and the second sampling value (b), the timing controller 120 can control the device so as to omit (skip) the processing of the next second sensing step.

[0066] As shown in FIGS. 10 and 15 to 17, the second sensing step is to sense again the gate line number where the difference value occurred in the first sensing step or the sub-pixel where the difference value occurred, and it is data of the display panel and the data that drives it. It is a step of secondarily determining the presence or absence of a defect between the driving units. The second sensing step may include a second-1 sensing period P1', a second-2 sensing period P2', and a second-3 sensing period P3'.

[0067] During the second-1 sensing period P1', a first scan signal of a low voltage and a first sensing signal Scan&Sense may be applied to the first scan line Gate1 and the second scan line Gate2. The switching transistor SW and the sensing transistor ST included in the first sub-pixel may be turned off by the first scan signal of a low voltage and the first sensing signal Scan&Sense.

[0068] During the second-2 sensing period P2', a second reference voltage Vprer may be applied to the first reference line VREF1 of the first sub-pixel included in the display panel. During the second-2 sensing period P2', a second voltage circuit RPRE including a second reference voltage source VPRER may be turned on in response to a high-voltage second voltage circuit control signal VpreR. The second voltage circuit control signal VpreR is applied at a high voltage during the second-2 sensing period P2' and then changed to a low voltage. During the second-2 sensing period P2', since the switching transistor SW and the sensing transistor ST included in the first sub-pixel are in the turned-off state, the second reference voltage Vprer may be in a state of being charged to the second sensing voltage Vsen2 by the sensing capacitor PCAP of the first reference line VREF1. On the other hand, the second reference voltage Vprer may be variably output at a higher level than before in order to enhance the judgment ability for the presence or absence of a defect.

[0069] During the second sensing period P2', the sampling circuit SAM can be turned on in response to the temporarily generated second sampling control signal Sam2-1. During the second sensing period P2', the sampling circuit SAM and the like can obtain the second sensing voltage Vsen2 charged in the sensing capacitor PCAP of the first reference line VREF1 of the first sub-pixel as the third sampling value (c). The second sampling control signal Sam2-1 is applied at a high voltage in the middle to latter half of the second sensing period P2', and then changed to a low voltage.

[0070] During the second sensing period P3', the sampling circuit SAM can be turned on in response to the temporarily generated second sampling control signal Sam2-2. During the second sensing period P3', the sampling circuit SAM and the like can obtain the second sensing voltage Vsen2 charged in the sensing capacitor PCAP of the first reference line VREF1 of the first sub-pixel as the fourth sampling value (d). The second sampling control signal Sam2-2 can be applied at a high voltage during the second sensing period P3' and then changed to a low voltage. The second to third sensing period P3' can be temporarily generated after a certain delay time after the second voltage circuit control signal VpreR is changed to a low voltage.

[0071] The light-emitting display device according to the embodiment can secondarily determine the presence or absence of a defect between the display panel and the data driving unit for driving the same based on the second voltage difference value between the third sampling value (c) and the fourth sampling value (d). At this time, the determination procedure can be performed by the timing controller 120 provided with the second sensing voltage Vsen2 in digital form for the third sampling value (c) and the fourth sampling value (d) or the video supply unit corresponding to a device higher than the timing controller.

[0072] On the other hand, the timing controller 120 can also secondarily determine the presence or absence of a defect between the display panel and the data driving unit that drives the same under the same driving conditions by comparing the sampling value (or reference sampling value) obtained from the normal sub-pixel with the third sampling value (c) or the fourth sampling value (d) without deriving the second voltage difference value.

[0073] FIG. 18 is a diagram exemplarily showing defects that may appear in the elements, signal lines, and power supply lines of the light-emitting display device according to the embodiment, and FIG. 19 is a diagram exemplarily showing defects that may appear in the signal lines of the light-emitting display device according to the embodiment. Hereinafter, as an example, the determination of the presence or absence of a defect in the light-emitting display device by the timing controller will be described.

[0074] As shown in FIGS. 18 and 19, the display panel and the data driving unit 140 can be electrically connected to each other via pads PD1 and PD2 existing in the pad region PDA (or bonding region). In addition to the signal lines DL1 and VREF1 that electrically connect the display panel and the data driving unit 140, a power supply line may also exist in the pad region PDA. Therefore, when there is an open defect (or bonding defect) due to non-contact (non-contact due to cracks) between the same type of signal lines in the pad region PDA (or bonding region) or a short defect due to foreign matter PTC contact (or moisture-permeable contact) between different types of signal lines, the sensing range may be deviated due to current leakage or the like, or an incorrect sensing value may be obtained.

[0075] The timing controller according to the embodiment can comprehensively determine the presence or absence of a defect in the light-emitting display device based on the first voltage difference value obtained in the first sensing stage and the second voltage difference value obtained in the second sensing stage. The explanation is as follows.

[0076] The timing controller 120 can determine the presence or absence of defects in at least one of the elements SW, CST, DT, OLED, and ST included in the sub-pixel SP of the display panel, the presence or absence of defects in the power supply lines EVDD or EVSS of the display panel, and the presence or absence of defects in the signal lines DL1 and VREF1 located between the display panel and the data driver unit 140, based on the first voltage difference value obtained in the first sensing stage.

[0077] When the first voltage difference value occurs, data lines, reference lines, etc. arranged between the sensing target sub-pixel and the data driver unit, together with the elements included in the sensing target sub-pixel, can be selected as a defect candidate group. And when the second voltage difference value occurs, only the reference line arranged between the sensing target sub-pixel and the data driver unit can be selected as the defect candidate group.

[0078] In the first example, when only the first voltage difference value occurs, the timing controller can determine that at least one of the elements included in the sensing target sub-pixel and the data line and reference line connected thereto is a defect factor. In the second example, when only the second voltage difference value occurs, the timing controller can determine that only the reference line is the defect factor. In the third example, when the first voltage difference value and the second voltage difference value occur, the timing controller can determine that both the elements included in the sensing target sub-pixel and the data line and reference line connected thereto are defect factors.

[0079] On the other hand, the timing controller may include a look-up table in which defect determination data for determining the presence or absence of defects in the components included in the light-emitting display device based on the first voltage difference value and the second voltage difference value is stored. In this case, the timing controller can more easily determine what kind of component has a defect due to the increase or decrease of the first voltage difference value or the second voltage difference value. Here, the defect determination data can be prepared through experiments.

[0080] FIG. 20 is a block diagram exemplarily showing the internal configuration of a data driving unit according to an embodiment, and FIGS. 21 to 23 are flowcharts exemplarily showing a process of digitally processing a sensing voltage and configuring it in a form transferable to a timing controller based on the data driving unit of FIG. 20.

[0081] As shown in FIG. 20, the data driving unit 40 according to the embodiment may include a driving circuit 141 and a sensing circuit 145. The driving circuit 141 may include a data reception and recovery unit RX&CDR, a first data processing and logic unit S2P&PLOG, a shift register unit SRES, a first latch unit LAT1, a second latch unit LAT2, a digital-to-analog conversion unit DAC, an output circuit COC, and the like.

[0082] The data reception and recovery unit RX&CDR receives and processes the packet data transmitted from the timing controller, and may play a role of recovering it when a reception error such as a data signal or a clock signal included in the packet data occurs.

[0083] The first data processing and logic unit S2P&PLOG changes the serial signal output from the data reception and recovery unit RX&CDR to a parallel signal, and may play a role of separating and outputting a control signal applied to the controller TCL and a data signal applied to the first latch unit LAT1.

[0084] The shift register unit SRES may play a role of generating a signal so that the data signal applied to the first latch unit LAT1 or the second latch unit LAT2 is sampled and latched one line at a time.

[0085] The first latch unit LAT1 and the second latch unit LAT2 may play a role of sampling and latching the data signal output from the first data processing and logic unit S2P&PLOG one line at a time and outputting it. Here, the second latch unit LAT2 may output a data signal based on the source output activation signal output from the first data processing and logic unit S2P&PLOG.

[0086] The digital-to-analog converter DAC can convert the data signal in digital format output from the second latch unit LAT2 based on the gamma reference voltage into a data voltage in analog format and output it.

[0087] The output circuit COC can perform additional modulation such as amplifying the data voltage output from the digital-to-analog converter DAC, and then output it via the data channel.

[0088] The sensing circuit 145 may include a controller TCL, a sensing processing unit CIA, a multiplexer MUX, a sampling and downscaling unit SAM&DS, a gain amplifier GA, an analog-to-digital converter ADC, a second data processing unit P2S, a data transmission unit TX, and the like.

[0089] The controller TCL can control the operation timing of the devices included inside the sensing circuit 145 based on the control signal output from the first data processing and logic unit S2P&PLOG.

[0090] The sensing processing unit CIA can obtain a sensing voltage via a sensing channel connected to the reference line, process it, and output it. The sensing processing unit CIA can be configured according to the sensing method of the sensing circuit 145. For example, the sensing processing unit CIA may be composed of a current integration circuit or a voltage sensing circuit.

[0091] The multiplexer MUX can selectively output the first reference voltage and the second reference voltage applied from the outside. The multiplexer MUX may include a first voltage circuit that outputs the first reference voltage and a second voltage circuit that outputs the second reference voltage.

[0092] The sampling and downscaling unit SAM&DS can sample the sensing voltage acquired by the sensing processing unit CIA and can also play a role in scaling down the sensing voltage. As shown in FIGS. 20 and 21, the sampling and downscaling unit SAM&DS samples the sensing voltage in the form of an analog signal (Analog Signal) output from the sensing processing unit CIA in the form of a sampled analog signal (Sampled Analog Signal), and then can downscale it and output it in the form of a sampled and downscaled analog signal (Sampled & Down scaled Analog Signal).

[0093] The gain amplifier GA can play a role in adjusting the gain for the sensing voltage output from the sampling and downscaling unit SAM&DS.

[0094] The analog-to-digital conversion unit ADC can convert the analog-form sensing voltage output from the gain amplifier GA into a digital-form sensing voltage (sensing data value) and output it. As shown in FIGS. 20 and 22, the analog-to-digital conversion unit ADC can output the analog-form sensing voltage output from the sampling and downscaling unit SAM&DS as a digital-form sensing voltage.

[0095] On the other hand, the circuit blocks (SHA, MDAC, FLASH, Digital Correction Logic) and the analog voltage (Analog Voltage) and digital data (Digital Data) in FIG. 22 are exemplarily shown to assist in understanding the detailed circuit configuration of the analog-to-digital conversion unit ADC, the conversion method thereby, and related aspects, so specific descriptions are omitted.

[0096] The second data processing unit P2S can align the parallel digital sensing voltage output from the analog-to-digital conversion unit ADC into a serial digital sensing voltage. As shown in FIGS. 20 and 23, the second data processing unit P2S can sort the parallel digital sensing voltage Vsen(Parallel Data) output from the analog-to-digital conversion unit ADC in the form of a serial digital sensing voltage Vsen(Serial Data).

[0097] The data transmission unit TX can transmit the serial digital sensing voltage and the like output from the second data processing unit P2S to the timing controller. As shown in FIGS. 20 and 23, the data transmission unit TX can configure the digital sensing voltage Vsen(Parallel Data) output from the second data processing unit P2S in a bus-low voltage differential signalling (B-LVDS) transmission format (TX Format) and transmit it to the timing controller. On the other hand, since the transmission format (TX Format) in FIG. 23 is shown exemplarily to assist in understanding the data packet, specific descriptions are omitted.

[0098] As described above, this specification can improve the lifespan of the display device by the compensation operation of the elements included in the sub-pixels constituting the display panel, and can improve the driving stability and driving reliability of the display device by detecting the presence or absence of defects in the entire display device.

Description of Reference Numerals

[0099] 120 Timing controller 140 Data driving unit 150 Display panel SP Sub-pixel 141 Driving circuit 145 Sensing circuit DL1 First data line VREF1 First reference line

Claims

1. a display panel including sub-pixels each having a switching transistor connected to a data line and a sensing transistor connected to a reference line; A driving circuit connected to the data line; a sensing circuit connected to the reference line; A display device including a timing controller that controls at least one of the driving circuit and the sensing circuit, The sensing circuit includes: in response to applying a first reference voltage to the subpixel via the reference line during a first sensing period, a first sensing voltage charged to the reference line is acquired as a first sampling value during a period in which the switching transistor and the sensing transistor are turned on, and the first sensing voltage charged to the reference line is acquired as a second sampling value during a period in which the switching transistor and the sensing transistor are turned off; The timing controller includes: The display device determining that the display device has a defect based on a first difference value between the first sampled value and the second sampled value.

2. The sensing circuit includes:

2. The display device of claim 1, wherein in response to applying a second reference voltage different from the first reference voltage to the subpixel via the reference line during a second sensing period in which the switching transistor and the sensing transistor are turned off, the display device obtains the second sensing voltage charged to the reference line as a third sampling value during a period in which the second reference voltage is applied to the reference line, and obtains the second sensing voltage charged to the reference line as a fourth sampling value during a period in which the second reference voltage is not applied to the reference line.

3. a data driver including the driving circuit and the sensing circuit, The timing controller includes: The display device of claim 2 , further comprising: determining that the display device has a defect based on a second difference value between the third sampled value and the fourth sampled value.

4. the second sensing period is scheduled to be executed when the first difference value is greater than a predetermined value; The display device of claim 2 , wherein the second sensing period is skipped or scheduled not to be executed if the first difference value is less than the predetermined value.

5. The display device according to claim 2 , wherein the first sensing period and the second sensing period are included in a drive start period during which power is applied to the display panel.

6. The display device according to claim 2 , wherein the first sensing period and the second sensing period are included in a drive end period during which an instruction to cut off the power applied to the display panel is issued.

7. the first sensing period is included in a drive start period in which power is applied to the display panel, The display device according to claim 2 , wherein the second sensing period is included in a drive end period during which an instruction to cut off the power applied to the display panel is given.

8. 1. A method for controlling a display device, comprising the steps of: applying a first reference voltage to a reference line connected to a subpixel included in a display panel of the display device by a sensing circuit included in the display device; obtaining, by the sensing circuit, the first reference voltage charged to the reference line during a period in which a switching transistor and a sensing transistor included in the subpixel are turned on, as a first sampling value, and obtaining, by the sensing circuit, the first reference voltage charged to the reference line during a period in which the switching transistor and the sensing transistor are turned off, as a second sampling value; determining, by a timing control device of the display device, that the display device is defective based on a first difference value between the first sampled value and the second sampled value.

9. The method according to claim 8 , wherein the first reference voltage is applied to the reference line during a first sensing period included in a driving start period during which power is applied to the display panel.

10. applying a second reference voltage different from the first reference voltage through the reference line when the switching transistor and the sensing transistor are turned off; 9. The method of claim 8, further comprising the steps of: acquiring a second sensing voltage charged to the reference line as a third sampling value during a period in which the second reference voltage is applied to the reference line; and acquiring the second sensing voltage charged to the reference line as a fourth sampling value during a period in which the second reference voltage is not applied to the reference line.

11. 11. The method of claim 10, further comprising determining that the display device is defective based on a second difference value between the third sampled value and the fourth sampled value.

12. The method according to claim 10 , wherein the second reference voltage is applied to the reference line in a second sensing period included in a drive end period during which an instruction to shut off power to the display panel is given.

13. 11. The method of claim 10, further comprising determining that the display device is defective based on a comparison of either the third sampled value or the fourth sampled value to a sampled value obtained from a normal subpixel.

Images