Memory controller, and method of controlling memory controller

Abstract

To suppress decrease in utilization efficiency of a memory.SOLUTION: A memory controller is configured to issue read and write commands for accessing a plurality of memories that shares a data signal, the memory controller comprising: a hold circuit configured to hold access requests for the commands; and a control circuit configured to select an arbitrary access request from among access requests held in the hold circuit and issue a command. The control circuit is configured, in a case where a command is issued to a second memory different from a first memory to which a command has been issued immediately before, to control a command to be issued preferentially on the basis of respective predetermined periods set in advance for each set of the type of command issued immediately before to the first memory and the type of command to be issued to the second memory.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory controller and a method for controlling the memory controller, and more particularly to a technique for connecting to a DRAM (Dynamic Random Access Memory), selecting an arbitrary memory access request from a plurality of memory access requests, and issuing a command.

Background Art

[0002] Generally, DRAM is used as the main memory device of a computer system. With the increasing functionality and performance of computer systems, the performance requirements for DRAM have been increasing, and various techniques for memory controllers have been proposed to maximize its performance.

[0003] When transferring in different transfer directions such as from a read command to a write command or from a write command to a read command, it is necessary to leave a command interval compared to continuing the transfer in the same transfer direction, which becomes a factor in reducing the memory utilization efficiency.

[0004] Patent Document 1 discloses determining a preferred transfer direction, outputting all transfers in the preferred transfer direction from the command queue, and then switching the preferred transfer direction to the other transfer direction.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, the method disclosed in Patent Document 1 does not mention the case of switching the memory to which the memory controller issues read / write commands for a plurality of memories that share data. For example, when switching the access destination memory occurs, depending on the type of the command issued immediately before, it may be necessary to leave a command interval by continuing to issue commands in the same direction rather than issuing commands in a different transfer direction (e.g., from write to read), which may cause a decrease in memory utilization efficiency.

[0007] The present invention has been made in view of the above problems, and an object thereof is to provide a technique for suppressing a decrease in memory utilization efficiency.

Means for Solving the Problems

[0008] The memory controller according to the present invention that achieves the above object is a memory controller that issues read or write commands to access a plurality of memories that share a data signal, a holding circuit that holds an access request of the command, and a control circuit that selects an arbitrary access request from the access requests held in the holding circuit and issues a command, and when the control circuit issues a command to a second memory different from a first memory to which a command was immediately previously issued, the control circuit controls the command to be preferentially issued based on each predetermined period preset for each combination of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory.

Effects of the Invention

[0009] According to the present invention, it becomes possible to suppress a decrease in memory utilization efficiency.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0012] (Embodiment) This embodiment can be used in various memory controllers that are connected to a DRAM and select an arbitrary memory access request from a plurality of memory access requests to issue a command.

[0013] <Configuration of Memory Controller> FIG. 1 is a configuration diagram of a memory controller 100 in an embodiment. The memory controller 100 issues read or write commands to access a plurality of memories that share data signals. The memory controller 100 is connected to a DRAM 110 composed of a plurality of banks and a bus master 120. The DRAM 110 is composed of two memory devices (memory 0 and memory 1), and memory 0 and memory 1 share data signals. In this embodiment, two DRAMs share data signals, but the number of DRAMs sharing data signals is not limited to two and may be three or more. The bus master 120 transmits a memory access request including address information and write data to the memory controller 100. The memory controller 100 generates a DRAM command based on the memory access request received from the bus master 120 and transmits it to one of the plurality of DRAMs 110. Further, the memory controller 100 performs data transfer with the DRAM 110 based on the transmitted DRAM command.

[0014] The memory controller 100 includes an access holding circuit 101, a read / write control circuit 102, a page control circuit 103, a bank state management circuit 104, and a command selector 105.

[0015] <Operation of the access holding circuit 101> First, the operation of the access holding circuit 101 will be described. The access holding circuit 101 is a buffer that holds a plurality of memory access requests. The access holding circuit 101 is composed of m (m >= 2) entries. Note that this embodiment does not depend on the number of m.

[0016] Here, FIG. 2 is a configuration diagram of the access hold circuit entry 1011 in one embodiment. In this embodiment, there are m access hold circuit entries 1011 shown in FIG. 2 in the access hold circuit 101. As shown in FIG. 2, the access hold circuit entry 1011 has fields 10111 to 10116 for the access type, target memory, target bank, target page, target column, and the remaining number of read / write commands. The access hold circuit 101 converts and holds the memory access request received from the bus master 120 so as to correspond to each field. The information stored in each field is as follows.

[0017] (a) Access type field 10111 Indicates the access type of the memory access request stored in the entry WRITE: The memory access request is a write (data writing) READ: The memory access request is a read (data reading) (b) Target memory field 10112 Indicates the memory to which the memory access request stored in the entry accesses (c) Target bank field 10113 Indicates the bank address to which the memory access request stored in the entry accesses (d) Target page field 10114 Indicates the page address to which the memory access request stored in the entry accesses (e) Target column field 10115 Indicates the starting column address to which the memory access request stored in the entry accesses (f) Remaining number of read / write commands field 10116 Indicates the number of remaining DRAM read / write commands to be executed by the memory access request stored in the entry When storing a memory access request in the access holding circuit 101, it is stored in an entry following the last entry of the stored memory access requests. When reading a memory access request from the access holding circuit 101, it can be read from any entry.

[0018] Subsequently, the entry control signal input from the read / write control circuit 102 to the access holding circuit 101 will be described. The entry control signal is composed of an entry number field, a deletion field, and an update field. When 1 is set in the deletion field, the access holding circuit 101 deletes the entry indicated by the entry number field. When 1 is set in the update field, the access holding circuit 101 updates the column field of the entry indicated by the entry number field to the head column address to be accessed by the next DRAM command. Also, it updates to the value obtained by subtracting 1 from the remaining read / write command count field.

[0019] <Operation of the read / write control circuit 102> Next, the operation of the read / write control circuit 102 will be described. The read / write control circuit 102 can refer to all of the memory access requests stored in the access holding circuit 101. The read / write control circuit 102 selects an arbitrary memory access request from among the memory access requests stored in the access holding circuit 101 for which the page to be accessed is open and no command issue wait due to memory switching occurs. Whether the page to be accessed by the memory access request is open or not is determined from the target memory field 10112, the target bank field 10113, the target page field 10114 of the access holding circuit entry 1011, and the bank state generated by the bank state management circuit 104 described later.

[0020] Then, the read / write control circuit 102 generates a read command or a write command from the selected memory access request and outputs it to the command selector 105. The read / write control circuit 102 of the present embodiment has a function of selecting a memory access request so as to continuously issue a read command and a write command to the same memory in order to suppress the read / write switching penalty.

[0021] Subsequently, a procedure for the read / write control circuit 102 to generate an entry control signal will be described. When the last read command or write command to be executed by the memory access request is issued, the processing of the corresponding memory access request is completed. Therefore, the read / write control circuit 102 generates an entry control signal to delete the corresponding entry from the access holding circuit 101. On the other hand, when a read command or a write command that is not the last one is issued, the read / write control circuit 102 generates an entry control signal to update the corresponding entry of the access holding circuit 101.

[0022] However, when the last read command or write command is issued, it is not necessary to update the corresponding entry. Whether the issued read command or write command is the last one can be determined by whether the remaining read / write command count field 10116 of the access holding circuit entry 1011 is 1.

[0023] <Operation of Page Control Circuit 103> Next, the operation of the page control circuit 103 will be described. The page control circuit 103 can refer to all of the memory access requests stored in the access holding circuit 101. The inputs to the page control circuit 103 are the memory access requests stored in the access holding circuit 101 and the bank state output by the bank state management circuit 104. The page control circuit 103 generates a page control command such as an active command or a precharge command based on the memory access request stored in the access holding circuit 101 and the bank state, and outputs it to the command selector 105.

[0024] <Operation of Bank State Management Circuit 104> Next, the operation of the bank state management circuit 104 will be described. The bank state management circuit 104 updates the bank state based on the command issuance state input from the command selector 105. The command issuance state is composed of the command type issued to the DRAM 110, and the memory, bank, and page to which the command was issued. The bank state includes whether a page is open for each bank constituting the DRAM 110 and the open page address.

[0025] <Operation of Command Selector 105> Finally, the operation of the command selector 105 will be described. The command selector 105 selects one from the read / write command input from the read / write control circuit 102 and the page control command input from the page control circuit 103 and issues it to the DRAM 110. Although not described in this embodiment, commands such as refresh may also be selected. Further, the command selector 105 outputs the command issuance state composed of the command type of the command issued to the DRAM 110 and the memory, bank, and page to which the command was issued to the read / write control circuit 102 and the bank state management circuit 104.

[0026] <Configuration of Read / Write Control Circuit 102> FIG. 3 is a configuration diagram of the read / write control circuit 102 in this embodiment. The read / write control circuit 102 includes a page open determination circuit 1051, a priority access type determination circuit 1052, a memory switching determination circuit 1053, a memory access request selection circuit 1054, and timers 1055, 1056, 1057, 1058.

[0027] Timer 1055 corresponds to the read commands of memory 0 of a plurality of DRAMs 110, and timer 1056 corresponds to the write commands of memory 0. Timer 1057 corresponds to the read commands of memory 1 of a plurality of DRAMs 110, and timer 1058 corresponds to the write commands of memory 1.

[0028] The page open determination circuit 1051 determines, based on the bank state, whether or not the target bank of the target memory has opened the target page for each of the memory access requests stored in the access holding circuit 101. The page open determination circuit 1051 outputs only the memory access requests for which the target page is open among the memory access requests stored in the access holding circuit 101 to the priority access type determination circuit 1052, and masks the other memory access requests.

[0029] The priority access type determination circuit 1052 determines whether or not the access type of each of the memory access requests output by the page open determination circuit 1051 corresponds to the priority access type. The priority access type is generated based on the memory access requests stored in the access holding circuit 101 and the bank state by the priority access type determination circuit 1052, and indicates a period during which either the read command or the write command is preferentially issued. The priority access type determination circuit 1052 outputs only the memory access requests corresponding to the priority access type among the memory access requests output by the page open determination circuit 1051 to the memory switching determination circuit 1053, and masks the other memory access requests.

[0030] When the command issuance state output from the command selector 105 indicates issuance of a read or write command to a memory other than memory 0, the timer 1055 sets the period during which a read command cannot be issued to a different memory after the command is issued. Note that the period to be set varies depending on whether the command issued from the command selector 105 is a read or write command. The value of the timer 1055 is decremented over time and stops at 0 except when being set. In the present embodiment, the period during which a read command cannot be issued to a different memory after a read command or write command is issued to a certain memory is set in the timer, but the present invention is not limited thereto. The period during which a read / write command cannot be issued to a different memory after a read / write command is issued to a certain memory may be increased or decreased, whereby the relationship between the frequency of memory switching and the waiting time for memory access requests can be adjusted.

[0031] When the command issuance state output from the command selector 105 indicates issuance of a read or write command to a memory other than memory 0, the timer 1056 sets the period during which a write command cannot be issued to a different memory after a command is issued to a certain memory. Other behaviors of this timer are the same as those of the timer 1055.

[0032] When the command issuance state output from the command selector 105 indicates issuance of a read or write command to a memory other than memory 1, the timer 1057 sets the period during which a read command cannot be issued to a different memory after a command is issued to a certain memory. Other behaviors of this timer are the same as those of the timer 1055.

[0033] When the command issuance state output from the command selector 105 indicates issuance of a read or write command to a memory other than memory 1, the timer 1058 sets the period during which a write command cannot be issued to a different memory after a command is issued to a certain memory. Other behaviors of this timer are the same as those of the timer 1055.

[0034] The memory switching determination circuit 1053 determines whether it is necessary to wait for the timing constraint for memory switching for each of the memory access requests output by the priority access type determination circuit 1052. Whether it is necessary to wait for the timing constraint for memory switching for a memory access request is determined by whether the value of the timer corresponding to the target memory of the memory access request is non-zero. When the target memory of the memory access request is Memory 0 and it is a read, the timer 1055 is referred to. When the target memory of the memory access request is Memory 0 and it is a write, the timer 1056 is referred to. When the target memory of the memory access request is Memory 1 and it is a read, the timer 1057 is referred to. When the target memory of the memory access request is Memory 1 and it is a write, the value of the timer 1058 is referred to.

[0035] The memory switching determination circuit 1053 outputs only the memory access requests for which no command issuance wait due to memory switching occurs among the memory access requests output by the priority access type determination circuit 1052 to the memory access request selection circuit 1054. Memory access requests for which command issuance wait occurs are masked.

[0036] The memory access request selection circuit 1054 selects an arbitrary memory access request from the memory access requests output by the memory switching determination circuit 1053. Then, it generates a read command or a write command for the selected memory access request and outputs it to the command selector 105.

[0037] <Operation> Subsequently, FIGS. 4(a)-4(c) and FIGS. 5(a)-5(c) are diagrams showing operation examples of memory access request selection in the present embodiment. FIGS. 4(a)-4(c) show an example of memory access request selection when issuing a read command to another memory after a write command in the present embodiment. Also, FIGS. 5(a)-5(c) show an example of memory access request selection when issuing a read command to another memory after a read command in the present embodiment.

[0038] Figures 4(a) and 5(a) show the states of the access holding circuit 101 in a certain cycle. Also, for each memory access request held in the access holding circuit 101, for the sake of explanation, memory access requests 0 to 2 and identifiers are assigned.

[0039] Figures 4(b) and 5(b) show the cycles (predetermined periods) to be opened between each command. The timing constraints shown in Figure 4(b) are as follows.

[0040] ·tCCD = 2 cycles @ dram_clock · Period during which a read command cannot be issued to a different memory from a write command = 4 cycles @ dram_clock · Period during which a write command cannot be issued to a different memory from a write command = 6 cycles @ dram_clock · Period during which a write command cannot be issued to the same memory from a read command = 4 cycles @ dram_clock On the other hand, the timing constraints shown in Figure 5(b) are as follows.

[0041] ·tCCD = 2 cycles @ dram_clock · Period during which a read command cannot be issued to a different memory from a read command = 4 cycles @ dram_clock · Period during which a write command cannot be issued to a different memory from a read command = 6 cycles @ dram_clock · Period during which a write command cannot be issued to the same memory from a read command = 4 cycles @ dram_clock Figures 4(c) and 5(c) show, in time series, the command issuance states to memories 0 and 1 of the DRAM 110 and the count values of the RD timer 1057 for memory 1 and the WR timer 1058 for memory 1. As a premise for these operation examples, it is assumed that the target bank of the target memory has opened the target page for the memory access request held in the access holding circuit 101.

[0042] First, using FIGS. 4(a) - 4(c), an example of selecting a memory access request when issuing a read command to another memory after a write command will be described.

[0043] At T1, a memory access request 0 with a relatively old reception order and a memory access request 1 with a relatively new reception order are held. Memory access request 0 has an access type = WR, target memory = 0, target bank = Don't care, target page = Don't care, target column = Don't care, and remaining read / write command count = 2. Memory access request 1 has an access type = WR, target memory = 1, target bank = Don't care, target page = Don't care, target column = Don't care, and remaining read / write command count = 1.

[0044] At T1, the read / write control circuit 102 can select either the write memory access request 0 to memory 0 or the write memory access request 1 to memory 1. In this operation example, it is assumed that a write command for the previously received memory access request 0 is issued. As a result, the RD timer 1057 for memory 1 sets a period (4 cycles) during which a read command cannot be issued to a different memory after issuing a read command to a certain memory and starts decrementing. Similarly, the WR timer 1058 for memory 1 also sets a period (6 cycles) during which a write command cannot be issued to a different memory after issuing a read command to a certain memory and starts decrementing.

[0045] At T3, since the timers 1057 and 1058 are not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0. More specifically, since the memory access request 1 is a write to memory 1, the WR timer 1058 for memory 1 is referenced. And since the timer 1058 is not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0.

[0046] From T4 to T7, only the memory access request 1 is held in the access holding circuit 101. However, since the timers 1057 and 1058 are not 0, the memory access request 1 is masked, and the read / write control circuit 102 does not select the memory access request. More specifically, since the memory access request 1 is a write to memory 1, the WR timer 1058 for memory 1 is referenced. And since the timer 1058 is not 0, the memory access request 1 is masked. Also, since there are no other memory access requests, the read / write control circuit 102 does not select the memory access request.

[0047] At T8, assume that a read memory access request 2 to memory 1 is stored in the access holding circuit 101. Since the timer 1058 is not 0, the memory access request 1 is masked. On the other hand, since the RD timer 1057 for memory 1 is 0, the read / write control circuit 102 selects the read memory access request 2 to memory 1. Then, at T15, the WR timer 1058 for memory 1 becomes 0 and the mask of the memory access request 1 is released, and the read / write control circuit 102 selects the memory access request 1.

[0048] Next, with reference to FIGS. 5(a) - 5(c), an example of memory access request selection when issuing a read command to another memory after a read command will be described.

[0049] At T1, a memory access request 0 with a relatively old reception order and a memory access request 1 with a relatively new reception order are held. The memory access request 0 has an access type = RD, target memory = 0, target bank = Don't care, target page = Don't care, target column = Don't care, and remaining read / write command count = 2. The memory access request 1 has an access type = WR, target memory = 1, target bank = Don't care, target page = Don't care, target column = Don't care, and remaining read / write command count = 1.

[0050] In T1, the read / write control circuit 102 can select either the write memory access request 0 to memory 0 or the write memory access request 1 to memory 1. In this operation example, it is assumed that a read command for the previously received memory access request 0 is issued. As a result, the RD timer 1057 for memory 1 sets a period (4 cycles) during which a read command cannot be issued to a different memory after a read command is issued to a certain memory, and starts decrementing. Similarly, the WR timer 1058 for memory 1 also sets a period (6 cycles) during which a write command cannot be issued to a different memory after a read command is issued to a certain memory, and starts decrementing.

[0051] In T3, since the timer 1057 and the timer 1058 are not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0. More specifically, since the memory access request 1 is a write to memory 1, the WR timer 1058 for memory 1 is referred to. And since the timer 1058 is not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0.

[0052] From T4 to T7, only the memory access request 1 is held in the access holding circuit 101. However, since the timer 1057 and the timer 1058 are not 0, the memory access request 1 is masked, and the read / write control circuit 102 does not select any memory access request. More specifically, since the memory access request 1 is a write to memory 1, the WR timer 1058 for memory 1 is referred to. And since the timer 1058 is not 0, the memory access request 1 is masked. Also, since there is no other memory access request for the read / write control circuit 102, it does not select any memory access request.

[0053] Assume that at T8, a read memory access request 2 to memory 1 is stored in the access holding circuit 101. Since the timer 1058 is not 0, the memory access request 1 is masked. On the other hand, since the RD timer 1057 for memory 1 is 0, the read / write control circuit 102 selects the read memory access request 2 to memory 1. Then, at T15, the WR timer 1058 for memory 1 becomes 0 and the mask of the memory access request 1 is released, and the read / write control circuit 102 selects the memory access request 1.

[0054] As described above, in this embodiment, when the read / write control circuit 102 issues a command to a second memory different from the first memory to which the command was immediately previously issued, based on each preset period for each combination of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory, it controls the command to be preferentially issued. For example, the command corresponding to the shortest preset period is preferentially issued after the elapse of the shortest preset period from the immediate previous issuance of the command.

[0055] When the read / write control circuit 102 issues a command to a second memory different from the first memory to which the command was immediately previously issued, it may preferentially issue a read command over a write command. As shown in FIGS. 4(b) and 5(b), when the previous one is a read command and a read command is issued to a different memory, the cycle time is 4 cycles. Also, when the previous one is a read command and a write command is issued to a different memory, the cycle time is 6 cycles. Since 6 cycles > 4 cycles, a read command is preferred over a write command. Similarly, when the previous one is a write command and a read command is issued to a different memory, the cycle time is 4 cycles. Also, when the previous one is a write command and a write command is issued to a different memory, the cycle time is 6 cycles. Since 6 cycles > 4 cycles, in this case as well, a read command is preferred over a write command.

[0056] In other words, when the read / write control circuit 102 issues a read command to a second memory different from the first memory to which a write command was issued immediately before, it controls to issue the read command to the second memory in response to the elapse of a predetermined period (for example, 4 cycles) from the issuance of the write command. Also, when the read / write control circuit 102 issues a write command to a second memory different from the first memory to which a write command was issued immediately before, it controls to issue the write command to the second memory in response to the elapse of a predetermined period (for example, 6 cycles) from the issuance of the write command.

[0057] Further, when the read / write control circuit 102 issues a read command to a second memory different from the first memory to which a read command was issued immediately before, it controls to issue the read command to the second memory in response to the elapse of a predetermined period (for example, 4 cycles) from the issuance of the read command. And when the read / write control circuit 102 issues a write command to a second memory different from the first memory to which a read command was issued immediately before, it controls to issue the write command to the second memory in response to the elapse of a predetermined period (for example, 6 cycles) from the issuance of the read command.

[0058] As described above, in the present embodiment, when a switch of the access destination memory occurs, commands in a transfer direction (write → read, read → write, etc.) with a short command interval are preferentially issued according to the immediately preceding command type (write, read). That is, memory access requests with a short command issuance waiting time due to the switch of the memory are preferentially issued. Thereby, it is possible to suppress a decrease in memory utilization efficiency.

[0059] [Modification Example] When issuing a read command or a write command, the read / write control circuit 102 may control to preferentially issue a command that has the shortest predetermined period among the following: (1) a predetermined period (penalty period during which a command cannot be selected) set for different memories and different transfer directions, (2) a predetermined period set for different memories and the same transfer direction, (3) a predetermined period set for the same memory and different transfer directions, and (4) a predetermined period set for the same memory and the same transfer direction.

[0060] For example, the predetermined period set for different memories and different transfer directions may be 9 cycles, and the predetermined period set for different memories and the same transfer direction (e.g., write → write) may be 13 cycles. Also, the predetermined period set for the same memory and different transfer directions may be 23 cycles, and the predetermined period set for the same memory and the same transfer direction (e.g., write → write) may be 4 cycles.

[0061] The disclosure of this specification includes the following memory controller and a method for controlling the memory controller.

[0062] (Item 1) A memory controller that issues a read or write command to access a plurality of memories that share a data signal, a holding circuit that holds an access request for the command, and a control circuit that selects an arbitrary access request from the access requests held in the holding circuit and issues a command, and when the control circuit issues a command to a second memory different from a first memory to which a command was immediately previously issued, the control circuit controls a command to be preferentially issued based on each predetermined period preset for each combination of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory.

[0063] (Item 2) When the control circuit issues a command to the second memory different from the first memory to which the command was issued immediately before, the control circuit preferentially issues the command corresponding to the shortest predetermined period among the preset respective predetermined periods after the elapse of the shortest predetermined period from the immediate previous issue of the command. The memory controller according to item 1, characterized in that.

[0064] (Item 3) When the control circuit issues a command to the second memory different from the first memory to which the command was issued immediately before, the control circuit preferentially issues a read command rather than a write command. The memory controller according to item 1 or 2, characterized in that.

[0065] (Item 4) When the control circuit issues a write command or a read command to the second memory different from the first memory to which the write command was issued immediately before, the control circuit preferentially issues a read command rather than a write command. The memory controller according to any one of items 1 to 3, characterized in that.

[0066] (Item 5) When the control circuit issues a write command or a read command to the second memory different from the first memory to which the read command was issued immediately before, the control circuit preferentially issues a read command rather than a write command. The memory controller according to any one of items 1 to 4, characterized in that.

[0067] (Item 6) The control circuit When issuing a read command to the second memory different from the first memory to which the write command was issued immediately before, the read command is issued to the second memory in response to the elapse of a first predetermined period from the issue of the write command, When issuing a write command to the second memory different from the first memory to which the write command was issued immediately before, the write command is issued to the second memory in response to the elapse of a second predetermined period from the issue of the write command control as follows, The memory controller according to any one of items 1 to 5, wherein the second predetermined period is longer than the first predetermined period.

[0068] (Item 7) When the control circuit issues a write command to the first memory that is the same as the first memory to which a read command was immediately previously issued, the control circuit issues the write command to the first memory in response to the elapse of a third predetermined period from the issuance of the read command. The memory controller according to any one of items 1 to 6.

[0069] (Item 8) The control circuit, when issuing a read command to a second memory different from the first memory to which a read command was immediately previously issued, issues the read command to the second memory in response to the elapse of a fourth predetermined period from the issuance of the read command, when issuing a write command to a second memory different from the first memory to which a read command was immediately previously issued, issues the write command to the second memory in response to the elapse of a fifth predetermined period from the issuance of the read command, control as follows, The memory controller according to any one of items 1 to 7, wherein the fifth predetermined period is longer than the fourth predetermined period.

[0070] (Item 9) When the control circuit issues a write command to the first memory that is the same as the first memory to which a read command was immediately previously issued, the control circuit issues the write command to the first memory in response to the elapse of a sixth predetermined period from the issuance of the read command. The memory controller according to any one of items 1 to 8.

[0071] (Item 10) A control method for a memory controller that issues a read or write command to access a plurality of memories that share data signals, a holding step of holding the access request of the command in a holding circuit; a control step of selecting an arbitrary access request from the access requests held in the holding circuit and issuing a command, and having, in the control step, when issuing a command to a second memory different from a first memory to which a command was immediately previously issued, based on each predetermined period set in advance for each combination of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory, controlling the command to be preferentially issued. A control method for a memory controller, characterized in that

[0072] (Other embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiment to a system or apparatus via a network or a storage medium and causing one or more processors in a computer of the system or apparatus to read and execute the program. Further, it can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

[0073] The invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, claims are attached to disclose the scope of the invention.

Explanation of reference numerals

[0074] 100: Memory controller, 101: Access holding circuit, 102: Read / write control circuit, 103: Page control circuit, 104: Bank state management circuit, 105: Command selector, 110: DRAM, 120: Bus master, 1011: Access holding circuit entry, 1051: Page open determination circuit, 1052: Priority access type determination circuit, 1053: Memory switching determination circuit, 1054: Memory access request selection circuit, 1055: Timer (for memory 0 read), 1056: Timer (for memory 0 write), 1057: Timer (for memory 1 read), 1058: Timer (for memory 1 write)

Claims

1. A memory controller that issues a read or write command to access a plurality of memories that share data signals, a holding circuit that holds an access request for the command, and a control circuit that selects an arbitrary access request from the access requests held in the holding circuit and issues a command. When the control circuit issues a command to a second memory different from a first memory to which a command was immediately previously issued, the control circuit controls the command to be preferentially issued based on each preset periodic period for each combination of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory. A memory controller characterized by that.

2. When the control circuit issues a command to a second memory different from the first memory to which a command was immediately previously issued, the control circuit preferentially issues the command corresponding to the shortest preset periodic period after the elapse of the shortest preset periodic period from the immediate previous issuance of the command. The memory controller according to claim 1, characterized by that.

3. When the control circuit issues a command to a second memory different from the first memory to which a command was immediately previously issued, the control circuit preferentially issues a read command over a write command. The memory controller according to claim 1, characterized by that.

4. When the control circuit issues a write command or a read command to a second memory different from the first memory to which a write command was immediately previously issued, the control circuit preferentially issues a read command over a write command. The memory controller according to claim 1, characterized by that.

5. When the control circuit issues a write command or a read command to a second memory different from the first memory to which a read command was immediately previously issued, the control circuit preferentially issues a read command over a write command. The memory controller according to claim 1, characterized by that.

6. The control circuit when issuing a read command to a second memory different from the first memory to which a write command was immediately previously issued, issues the read command to the second memory in response to the elapse of a first preset period from the issuance of the write command, When issuing a write command to a second memory different from the first memory to which a write command was most recently issued, issue the write command to the second memory in response to the elapse of a second predetermined period since the issuance of the write command so as to control, The memory controller according to claim 1, wherein the second predetermined period is longer than the first predetermined period.

7. The memory controller according to claim 1, wherein when the control circuit issues a write command to the first memory that is the same as the first memory to which a read command was most recently issued, the control circuit issues the write command to the first memory in response to the elapse of a third predetermined period since the issuance of the read command.

8. The control circuit, when issuing a read command to a second memory different from the first memory to which a read command was most recently issued, issues the read command to the second memory in response to the elapse of a fourth predetermined period since the issuance of the read command, when issuing a write command to a second memory different from the first memory to which a read command was most recently issued, issues the write command to the second memory in response to the elapse of a fifth predetermined period since the issuance of the read command so as to control, The memory controller according to claim 1, wherein the fifth predetermined period is longer than the fourth predetermined period.

9. The memory controller according to claim 1, wherein when the control circuit issues a write command to the first memory that is the same as the first memory to which a read command was most recently issued, the control circuit issues the write command to the first memory in response to the elapse of a sixth predetermined period since the issuance of the read command.

10. A control method for a memory controller that issues a read or write command to access a plurality of memories that share a data signal, comprising: a holding step of holding the access request of the command in a holding circuit; a control step of selecting an arbitrary access request from the access requests held in the holding circuit and issuing a command. In the control step, when issuing a command to a second memory different from the first memory to which a command was most recently issued, control is performed over the command to be preferentially issued based on respective preset periodic intervals for each combination of the type of the command most recently issued to the first memory and the type of the command to be issued to the second memory. A control method for a memory controller characterized by this is provided.

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