Scanning circuit

Abstract

To prevent the characteristics of a thin film transistor in a scanning circuit from deteriorating.SOLUTION: A scanning circuit is controlled by a clock signal having a m phase. Multi-stage shift registers sequentially outputs a high level pulse having two or more horizontal periods in a transmission step having one horizontal period. Each shift register is controlled by a two-phase clock signal composed of first and second clock signals. PW expresses the pulse widths of the first and second clock signals. H expresses the one horizontal period. PW / mH expresses High duties of the first and second clock signals. On-duty of each thin film transistor in all thin film transistors is equal to or less than PW / mH.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present disclosure relates to a scanning circuit.

Background Art

[0002] Current-driven self-emitting elements such as OLED (Organic Light-Emitting Diode) elements have advantages such as eliminating the need for a backlight, low power consumption, a wide viewing angle, and a high contrast ratio, and are expected in the development of flat panel displays.

[0003] An active matrix (AM) type OLED display device includes a plurality of switch transistors for selecting a pixel and writing a data signal into a holding capacitor, and a driving transistor for supplying current to the pixel. The transistors in the OLED display device are TFTs (Thin Film Transistors), and in addition to LTPS (Low Temperature Poly-silicon) TFTs, oxide semiconductor TFTs and amorphous silicon TFTs can also be used.

[0004] In order to write a more appropriate data signal to the pixel, it is important to correct the variation and change in the threshold voltage of the TFT. By lengthening the control period of the pixel circuit for correcting the threshold voltage (also referred to as the threshold correction period), a more appropriate data signal can be written into the holding capacitor.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In order to provide a pixel circuit with a threshold correction period longer than the data writing period for writing a data signal into a holding capacitance, a scanning circuit that outputs a control signal with a pulse width longer than one horizontal period (1H period) is required. The scanning circuit transfers a pulse that is an integer multiple of the 1H period to the next stage after the 1H period. That is, the output lines of a plurality of consecutive stages are activated during the same period. The active output signal maintains the TFT to be controlled in the pixel circuit in the ON state.

[0007] Generally, since the emission duty is as high as 99% or more, the output of each output line is almost always in an inactive state. Therefore, in the output stage circuit of the scanning circuit, there may be a transistor TFT that is almost always in the ON state. If the TFT is maintained in the ON state for a long time, its characteristics may deteriorate. In particular, in the case of an oxide TFT or an amorphous silicon TFT, etc., the degree of deterioration is large. Here, an N-type TFT circuit has been described as an example, but it is not limited to the N-type.

Means for Solving the Problem

[0008] One aspect of the present disclosure is a scanning circuit that outputs a gate signal to a pixel circuit of a display panel, including a plurality of cascaded shift registers. The scanning circuit is controlled by an m-phase clock signal, where m is an integer greater than or equal to 2. The plurality of cascaded shift registers sequentially output high-level pulses of two or more horizontal periods in a transfer step of one horizontal period. Each shift register of the plurality of cascaded shift registers is controlled by a two-phase clock signal composed of a first clock signal and a second clock signal in the m-phase clock signal. The conductivity types of all thin-film transistors of each shift register of the plurality of cascaded shift registers are common. Each shift register of the plurality of cascaded shift registers includes a high-level output thin-film transistor including a source connected to the output terminal of the shift register and a drain connected to a high power line, a low-level output thin-film transistor including a drain connected to the output terminal of the shift register and a source connected to a low power line, and a buffer thin-film transistor including one of the source / drain to which the first clock signal is input and the other of the source / drain connected to the gate of the low-level output thin-film transistor. During a period when the output terminal outputs a low level, a control signal having the same pulse width and period as the first clock signal is input to the gate of the buffer thin-film transistor. The pulse widths of the first clock signal and the second clock signal are represented by PW, and one horizontal period is represented by H. The high duty of the first clock signal and the second clock signal is represented by PW / mH. The ON duty of each thin-film transistor of all the thin-film transistors is PW / mH or less.

[0009] Another aspect of the present disclosure is a scanning circuit that outputs a gate signal to a pixel circuit of a display panel, including a plurality of connected stages of shift registers. The scanning circuit is controlled by an m-phase clock signal, where m is an integer greater than or equal to 2. In the transfer step of one horizontal period, the plurality of stages of shift registers sequentially output high-level pulses of two or more horizontal periods. Each shift register of the plurality of stages of shift registers is controlled by a two-phase clock signal composed of a first clock signal and a second clock signal in the m-phase clock signal. The conductivity types of all thin-film transistors of each shift register of the plurality of stages of shift registers are common. Each shift register of the plurality of stages of shift registers includes a high-level output thin-film transistor including a drain connected to the output terminal of the shift register and a source connected to a high power supply line, a low-level output thin-film transistor including a source connected to the output terminal of the shift register and a drain connected to a low power supply line, and a buffer thin-film transistor including one of the source / drain to which the first clock signal is input and the other of the source / drain connected to the gate of the low-level output thin-film transistor. During the period when the output terminal outputs a low level, a control signal having the same pulse width and period as the first clock signal is input to the gate of the buffer thin-film transistor. The pulse widths of the first clock signal and the second clock signal are represented by PW, one horizontal period is represented by H, the high duty of the first clock signal and the second clock signal is represented by PW / mH, and the ON duty of each thin-film transistor of all the thin-film transistors is PW / mH or less.

Advantages of the Invention

[0010] According to one aspect of the present disclosure, deterioration of TFTs in the scanning circuit can be suppressed.

Brief Description of the Drawings

[0011]

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Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments will be specifically described with reference to the drawings. The same reference numerals are given to common configurations in each figure. For the sake of clarity of explanation, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0013] Hereinafter, a technique for improving a scanning circuit in a light-emitting display device that uses a light-emitting element that emits light by a driving current, such as an OLED (Organic Light-Emitting Diode) display device or an inorganic LED display device, will be disclosed. Note that the type of display device to which the technique of the present disclosure is applicable is not limited, and it may be used in a device different from the display device.

[0014] The display device according to an embodiment of the present specification writes a more appropriate data signal to the holding capacitance by lengthening the control period (also referred to as the threshold correction period) of the pixel circuit for correcting the threshold voltage of the thin film transistor (TFT). The display device includes a plurality of scanning circuits that output different control signals respectively.

[0015] At least one scanning circuit outputs a control signal having a pulse width longer than 1 horizontal period (1H period) in order to give a longer threshold correction period to the pixel circuit as compared with the data writing period for writing the data signal to the holding capacitance. The pulse width of this control signal indicates the period of the signal level for maintaining the TFT to be controlled in the ON state. When the TFT to be controlled is an N-type TFT, it indicates the period of the H level. The signal for turning on the TFT to be controlled is also called an active signal.

[0016] Note that the 1H period is calculated from the frame rate and the number of rows of the pixel circuit. That is, 1H period = 1 / frame rate / number of rows. For example, when the frame rate is 120 Hz and the number of rows is 2952, the 1H period is 2.82 μs.

[0017] The scanning circuit transfers a pulse that is an integer multiple of the 1H period to the next stage after the 1H period. That is, the output line of each stage of the scanning circuit starts to output a pulse 1H period after the pulse is output from the output line of the previous stage. In this way, the pulse transfer step is the 1H period, and the output lines of a plurality of consecutive stages are activated during the same period. Such scanning is also called overlapping scanning.

[0018] Since the light emission duty of the display device is generally as high as 99% or more, the output of each output line is almost always in an inactive state. That is, in the output stage circuit of the scanning circuit, there may be a TFT that is almost always in an on state. When the TFT is maintained in the on state for a long time, its characteristics may deteriorate. In particular, in the case of oxide TFTs, amorphous silicon TFTs, etc., the degree of deterioration is large. Here, an N-type TFT circuit is described as an example, but it is not limited to N-type.

[0019] One embodiment of this specification proposes a circuit configuration of a scanning circuit that suppresses the deterioration of the TFT. FIG. 1 schematically shows a configuration example of an OLED display device 10 that is a display device. The horizontal direction in FIG. 1 is the X-axis direction, and the vertical direction is the Y-axis direction perpendicular to the X-axis direction. Note that the features of the present disclosure can be applied to display devices including other types of self-emitting elements such as inorganic LEDs. The OLED display device 10 includes a TFT substrate 100 on which OLED elements (light-emitting elements) are formed, and a sealing substrate 150 that seals the OLED elements.

[0020] An inert gas such as dry nitrogen is sealed between the TFT substrate 100 and the sealing substrate 150. A sealing structure portion with another structure, for example, a sealing structure portion that uses thin film sealing instead of the sealing substrate 150, may be used.

[0021] Around the cathode electrode formation region 114 outside the display region 125 of the TFT substrate 100, scanning circuits 131, 132, 133 (also called gate driver circuits), a driver IC 134, and a demultiplexer 136 are arranged. The driver IC 134 is connected to an external device via an FPC (Flexible Printed Circuit) 135. The scanning circuits 131, 132, 133 drive the scanning lines of the TFT substrate 100.

[0022] The driver IC 134 is mounted, for example, using an anisotropic conductive film (ACF: Anisotropic Conductive Film). The driver IC 134 supplies a power supply and a timing signal (control signal) to the scanning circuits 131, 132, 133. Further, the driver IC 134 supplies a data signal to the demultiplexer 136.

[0023] The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer of 2 or more). The demultiplexer 136 drives d times the number of data lines of the output pins of the driver IC 134 by switching the output destination data line of the data signal from the driver IC 134 d times during the scanning period.

[0024] The display region 125 includes a plurality of OLED elements (pixels) and a plurality of pixel circuits that control the light emission of each of the plurality of pixels. In a color OLED display device, each OLED element emits light of, for example, one of red, blue, or green. The plurality of pixel circuits constitute a pixel circuit array.

[0025] As will be described later, each pixel circuit includes a driving TFT (driving transistor) and a holding capacitor that holds a signal voltage that determines the driving current of the driving TFT. The data signal transmitted through the data line is corrected by the threshold voltage Vth of the driving TFT and accumulated in the holding capacitor. The voltage of the holding capacitor determines the gate voltage (Vgs) of the driving TFT. The corrected control voltage of the holding capacitor analogously changes the conductance of the driving TFT and supplies a forward bias current corresponding to the emission gradation to the OLED element. [Pixel Circuit Configuration]

[0026] FIG. 2 shows a configuration example of a pixel circuit 200 and control signals according to an embodiment of the present specification. Note that FIG. 2 only shows an example of a pixel circuit, and the configuration of the pixel circuit controlled by the scanning circuit of the present disclosure is not limited thereto. The pixel circuit 200 is included in the pixel circuit row of the k-th stage (k is an integer). The pixel circuit 200 includes five transistors (TFTs) P1 to P4 having gates, sources, and drains. In this example, the conductivity types of all the transistors P1 to P4 are N-type. The transistor is, for example, an oxide semiconductor transistor.

[0027] The transistor P1 is a driving transistor that controls the amount of current flowing to the OLED element E1. The drain of the driving transistor P1 is connected to a power line 241 that transmits the positive power supply potential VDD. The driving transistor P1 controls the amount of current supplied from the power line 241 to the OLED element E1 according to the voltages held by the holding capacitor elements CS1 and CS2 connected in series. The holding capacitor elements CS1 and CS2 hold the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to a power line 204 that transmits the negative power supply potential VEE from the cathode power supply.

[0028] The capacitor elements CS1 and CS2 are connected in series between the power line 204 that transmits the negative power supply potential VEE and the gate of the driving transistor P1. One end of the capacitor element CS1 is connected to the power line 204. One end of the capacitor element CS2 is connected to the other end of the capacitor element CS1. The other end of the capacitor element CS2 is connected to the gate of the driving transistor P1. The source of the transistor P1 and the anode of the OLED element E1 are connected to the intermediate node between the capacitor elements CS1 and CS2.

[0029] The series combined capacitance of the holding capacitor elements CS1 and CS2 holds the voltage between the gate of the driving transistor P1 and the power line 204. The source of the driving transistor P1 is connected to the OLED element E1. The holding capacitor elements CS1 and CS2 hold the gate-source voltage of the driving transistor P1.

[0030] Transistor P4 operates to supply the reset potential Vrst to the anode of the OLED element E1 and the intermediate node of the holding capacitor elements CS1 and CS2. One end of the source / drain (source or drain) of transistor P4 is connected to the power line 242 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1 and the intermediate node of the capacitor elements CS1 and CS2. The reset potential Vrst may be, for example, at the same potential as the cathode negative power supply potential VEE.

[0031] The gate of transistor P4 is connected to the control signal line 231 that transmits the selection signal S1, and transistor P4 is controlled by the selection signal S1. When transistor P4 is turned on by the selection signal S1 from the scanning circuit 131, it supplies the reset potential Vrst transmitted by the power line 242 to the anode of the OLED element E1 and the intermediate node of the capacitor elements CS1 and CS2.

[0032] Transistor P3 controls the supply of the reference potential Vref to the gate of transistor P1. For example, the reference potential Vref is a negative constant potential like the reset potential Vrst and is higher than the reset potential. One end of the source / drain of transistor P3 is connected to the power line 202 that transmits the reference potential Vref, and the other end is connected to the gate of transistor P1. The gate of transistor P3 is connected to the control signal line 233 that transmits the selection signal S3, and transistor P3 is controlled by the selection signal S3 input to the gate from the scanning circuit 133.

[0033] Transistor P2 is a switch transistor that selects the pixel circuit that supplies the data signal and writes the data signal (data signal voltage) Vdata to the holding capacitor elements CS1 and CS2. One end of the source / drain of transistor P2 is connected to the holding capacitor element CS2 and the gate of transistor P1, and the other end is connected to the data line 237 that transmits the data signal Vdata.

[0034] The gate of transistor P2 is connected to a control signal line 232 that transmits a selection signal S2 from the scanning circuit 132. Transistor P2 is controlled by the selection signal S2. In the pixel circuit 200, the selection signal S2 is a selection signal that controls the supply of the data signal Vdata to the holding capacitor elements CS1 and CS2. When transistor P2 is ON, transistor P2 supplies the data signal Vdata supplied from the driver IC 134 via the data line 237 to the holding capacitor elements CS1 and CS2. [Pixel Circuit Operation]

[0035] FIG. 3 shows a timing chart of signals for controlling the pixel circuit 200 shown in FIG. 2 during one frame period. FIG. 3 shows a timing chart for selecting the k-th row and writing a data signal to the pixel circuit 200. Specifically, FIG. 3 shows the selection signals S1, S2, S3, and the data signal Vdata.

[0036] The period before time T1 is the light emission period. The selection signals S1, S2, and S3 are Low. During this period, transistors P2 to P4 are OFF. A driving current is supplied from the power supply line 241 to the OLED element E1 via the driving transistor P1 by the voltage held in the series combined capacitance of the holding capacitor elements CS1 and CS2, and the OLED element E1 is emitting light.

[0037] The period from time T1 to T2 is the initialization period. At time T1, the selection signals S1 and S3 change from Low to High. The selection signal S2 remains Low. At time T1, transistors P3 and P4 turn ON. Transistor P2 remains OFF. This state is maintained from time T1 to time T2. This period is the initialization period, and its length is the length of one horizontal period (1H). The reference potential Vref and the reset potential Vrst are supplied to the pixel circuit.

[0038] At time T2, the selection signal S1 changes from High to Low. The selection signal S2 remains Low, and the selection signal S3 remains High. In response to the change in the selection signal S1, the transistor P4 turns OFF. This state is maintained from time T2 to time T3. From time T2 to time T3 is the correction period of the threshold voltage Vth of the driving transistor P1. In the example shown in FIG. 3, the length of the correction period is 5H.

[0039] At time T3, the selection signal S1 maintains Low. The selection signal S2 changes from Low to High. The selection signal S3 changes from High to Low. Since the selection signal S1 remains Low, the transistor P4 remains OFF. In response to the change in the selection signal S2, the transistor P2 turns ON. In response to the change in the selection signal S3, the transistor P3 turns OFF. From time T3 to time T4 is the data writing period for writing the data signal to the holding capacitor elements CS1 and CS2. The length of this period is 1H. The period after time T4 is the light emission period. The driving transistor P1 flows a driving current to the OLED element E1 according to the voltage held in the holding capacitor. This state continues until time T1 of the next frame.

[0040] In the example shown in FIG. 3, the initialization period is 1H, and the Vth correction period has a length that is an integer multiple of 1H. In the example of FIG. 3, the Vth correction period has a length that is 5 times that of 1H. The initialization period can be set, for example, from 1H to 3H, and the Vth correction period can be set, for example, from 3H to 40H. 1H is, for example, about 3 μs.

[0041] FIG. 4 shows the time change of the selection signal S3 for consecutive pixel rows. The selection signal S3 is sequentially output from the scanning circuit of the scanning circuit 133 to each pixel row. FIG. 4 shows the time change of the selection signal S3_k-1 for the (k - 1)-th row, the selection signal S3_k for the k-th row, and the selection signal S3_k+1 for the (k + 1)-th row. The selection signals S3 for consecutive stages are shifted by 1H period. The length of the selection signal S3 is the same as the example shown in FIG. 3.

[0042] The scanning circuit 133 sequentially outputs a selection signal S3 having a pulse width longer than one horizontal period. The scanning circuit 133 transfers a pulse that is an integral multiple of the 1H period, in this example, a 6H period pulse, to the next stage after 1H period. That is, the output line of each stage of the scanning circuit 133 starts outputting a pulse 1H period after a pulse is output from the output line of the previous stage. The pulse transfer step is 1H period, and the output lines of a plurality of consecutive stages are activated during the same period. In this way, the scanning circuit 133 performs overlapping scanning.

[0043] FIG. 5 shows a configuration example of a shift register 300 that constitutes a part of the scanning circuit included in the scanning circuit 133. The shift register 300 generates and outputs a signal from the output terminal of one stage of the scanning circuit. The scanning circuit includes a plurality of shift registers 300 connected in series. FIG. 5 shows the k-th stage shift register.

[0044] In the configuration example shown in FIG. 5, an output OUT_k-1 from the previous stage shift register, a first clock signal CK1, a second clock signal CK2, a high power supply potential VGH, and a low power supply potential VGL are input to the shift register 300. The shift register 300 includes nine transistors and two capacitive elements. The transistors are thin film transistors, and their conductivity type is N-type. They are, for example, oxide semiconductor TFTs. Note that the conductivity type of the thin film transistor may be P-type. The shift register 300 may be formed on the insulating substrate of the TFT substrate 100 in the same manner as the pixel circuit 200.

[0045] The shift register 300 includes transistors M1, M3 to M9, M11, and capacitance elements C1 and C3. The capacitance elements may be omitted. The gate of transistor M1 (the first thin-film transistor) is connected to the transmission line of clock signal CK2, and the clock signal CK2 is input. One of the source / drain is connected to the output line of the previous-stage shift register, and the output signal OUT_k-1 from the previous-stage shift register is input. The other of the source / drain is connected to the gates of transistor M3 (the third thin-film transistor) and transistor M4 (the fourth thin-film transistor), and further connected to the gate of transistor M8 (the high-level output thin-film transistor) via node Q.

[0046] The gate of transistor M11 is connected to the transmission line of clock signal CK1, the drain is connected to the power line of high power supply potential VGH, and the source is connected to node N1. The source of transistor M3 is connected to the power line of low power supply potential VGL, and the drain is connected to node N1.

[0047] The drain of transistor M4 is connected to the power line of high power supply potential VGH, and the source is connected to node N2. The source of transistor M5 (the fifth thin-film transistor) is connected to the power line of low power supply potential VGL, and the drain is connected to node N2.

[0048] The gate of transistor M6 (the first buffer thin-film transistor) is connected to node N1, the drain is connected to the transmission line of clock signal CK1, and the source is connected to node QB. The source of transistor M7 (the second buffer thin-film transistor) is connected to the power line of low power supply potential VGL, and the drain is connected to node QB.

[0049] The gate of transistor M8 is connected to the source / drain of transistor M1 via node Q. The drain is connected to the power supply line of the high power supply potential VGH, and the source is connected to the output terminal (output line) of the output signal OUT_k from the shift register. The gate of transistor M9 (low-level output thin film transistor) is connected to the source of transistor M6 and the drain of transistor M7 via node QB. The source is connected to the power supply line of the low power supply potential VGL, and the drain is connected to the output terminal (output line) of the output signal OUT_k from the shift register.

[0050] The capacitive element C1 is connected to the output terminal (output line) of the output signal OUT_k from the shift register and node Q. That is, it is connected to the source and gate of transistor M8. The capacitive element C3 is connected to node QB and node N1. That is, the capacitive element C3 is connected to the source and gate of transistor M6.

[0051] Transistors M8 and M9 are output transistors, each for outputting a High-level signal and an L-level signal. Transistors M6 and M7 are buffer transistors for transistor M9. The source / drain (source or drain) of the buffer transistor is connected to the gate of the output transistor. Also, a signal generated internally by the shift register 300 in response to an external signal is input to the gate. An aperiodic signal different from a periodic signal such as a clock signal is input to the gates of transistors M6 and M7 within one frame period.

[0052] The gate widths (sizes) of the output transistors M8 and M9 are larger than those of the buffer transistors M6 and M7. The gate widths of the buffer transistors M6 and M7 are larger than those of transistors M3 to M5 and M11.

[0053] FIG. 6 shows another configuration example 310 of the shift register. In the shift register 310, the transistor M11 is omitted from the configuration of the shift register 300 shown in FIG. 5, and a capacitive element C2 is added. The capacitive element C2 is connected to the transmission line of the clock signal CK1 and the node N1, and contributes to suppressing the through-current flowing through the transistors M11 and M3 in FIG. 5. The through-current will be described later.

[0054] FIG. 7 shows another configuration example 320 of the shift register. With respect to the shift register 310 shown in FIG. 6, transistors M2 (second thin-film transistor) and M10 (sixth thin-film transistor) are added. Note that either one of the transistors M2 and M10 may be omitted. The gate of the transistor M2 is connected to the transmission line of the reset signal RST, and the reset signal RST is input thereto. The source of the transistor M2 is connected to the power supply line of the low power supply potential VGL. The drain of the transistor M2 is connected to the gates of the transistors M3 and M4. The transistor M2 is ON for a predetermined period in one frame period, and resets the potential of the node Q.

[0055] The gate of the transistor M10 is connected to the transmission line of the reset signal RST, and the reset signal RST is input thereto. The source of the transistor M10 is connected to the power supply line of the low power supply potential VGL. The drain of the transistor M10 is connected to the output terminal of the output signal OUT_k. The transistor M10 is ON for a predetermined period in one frame period, and resets the potential of the output terminal.

[0056] FIG. 8 shows the time changes of the signals input to the shift registers 300, 310, and 320, the potentials at the circuit internal nodes, and the output signals. Specifically, FIG. 8 shows the time changes of the clock signals CK1 and CK2, the output signal OUT_k-1 of the previous stage, the potentials of the nodes N1 and N2, the output signal OUT_k, the potentials of the nodes Q and QB, and the reset signal. The dashed lines extending vertically indicate the 1H period (transfer step).

[0057] Hereinafter, taking the shift register 320 as an example, the operation of the shift register will be described. As described above, the time change of the signals shown in FIG. 8 is common to the other shift registers 300 and 310. The High level and Low level of the clock signals CK1 and CK2 are substantially the same as the respective power supply potentials VGH and VGL. Hereinafter, the description will be made using the power supply potentials VGH and VGL. Note that the potential of each node in the shift register 320 may take a value slightly different from VGH or VGL, but for ease of explanation, it is assumed to be either VGL or VGH.

[0058] Referring to FIGS. 8 and 9A, the operation during the period from time T11 to T12 will be described. The period from time T11 to T12 is the reset period of the node Q and the output OUT_k. FIG. 9A shows the ON / OFF states of the transistors in the shift register 320 at time T11. Hereinafter, the pulse of each signal indicates the length of one period of the High level (VGH) that turns on the target transistor.

[0059] Referring to FIG. 8, at time T11, the clock signal CK1 changes from VGL to VGH. The pulse width (width of one High period) of the clock signal CK1 is shorter than the 1H period and changes from VGH to VGL before time T12. The clock signal CK2 maintains VGL from time T11 to T12. The clock signal CK2 changes from VGL to VGH at time T12.

[0060] Note that the widths and periods of the pulses of the clock signals CK1 and CK2 are common. The pulse widths of the clock signals CK1 and CK2 are shorter than the 1H period, for example, 1H / 2 period. The periods of the clock signals CK1 and CK2 are 2H.

[0061] The input OUT_k - 1 from the previous - stage shift register to the present shift register maintains VGL from time T11 to T12. The reset signal RST changes from VGL to VGH at time T11. The reset signal RST maintains VGH from time T11 to T12. The reset signal RST changes from VGH to VGL at time T12.

[0062] Referring to FIG. 9A, since the clock signal CK2 is VGL, the transistor M1 is OFF. Since the reset signal RST is VGH, the transistors M2 and M10 are ON. VGL is applied to the gates of the transistors M3, M4, and M8 via the transistor M2, and they are OFF. Similarly, as shown in FIG. 8, the potential of the node Q is VGL.

[0063] As shown in FIG. 8, since the clock signal CK1 changes from VGL to VGH, the potential of the node N1 changes from VGL to VGH due to the capacitive coupling of C2. Therefore, the transistor M5 is ON. Since the transistor M5 is ON, the potential of the node N2 is VGL. Therefore, the transistor M7 is OFF. In response to the change in the node N1, the transistor M6 is turned ON by the capacitive element C3, and the potential of the node QB changes to VGH. Since the potential of the node QB is VGH, the transistor M9 is ON.

[0064] As described above, the transistors M2 and M10 are turned ON by the reset signal, and the potential of the node Q and the output OUT_k are reset to VGL.

[0065] As shown in FIG. 8, before time T12, the clock signal CK1 changes from VGH to VGL, and accordingly, the potential of the node N1 changes to VGL. The transistors M5 and M6 are turned OFF. Also, the node QB changes to VGL, and the transistor M9 is turned OFF. Since the reset signal RST maintains VGH, the transistors M2 and M10 remain ON.

[0066] Next, the operation during the period from time T12 to T13 will be described. Note that the state of the transistors during the period from time T14 to T15 is the same, and the signal changes are the same except that the reset signal RST maintains VGL. During this period, the node Q is refreshed to VGL. FIG. 9B shows the ON / OFF states of the transistors in the shift register 320 at time T12.

[0067] Referring to FIG. 8, at time T12, the reset signal RST changes from VGH to VGL. Thereby, transistors M2 and M10 turn off. The clock signal CK2 changes from VGL to VGH. The clock signal CK1 maintains VGL. Also, the input OUT_k-1 from the previous-stage shift register also maintains VGL.

[0068] When the clock signal CK2 changes to VGH, transistor M1 turns on. Since the input OUT_k-1 from the previous-stage shift register is VGL, VGL is applied to node Q (refresh), and transistor M8 is off. Also, transistors M3 and M4 are off. The potential of node N2 is maintained at VGL, and transistor M7 is off.

[0069] Since the clock signal CK1 is VGL, the potential of node N1 is maintained at VGL, and transistors M5 and M6 are off. The potential of node QB is VGL, and transistor M9 is off. The output OUT_k maintains VGL.

[0070] Before time T13, the clock signal CK2 changes from VGH to VGL, and transistor M1 turns off. However, the potentials of nodes N1, N2, Q, and QB in the shift register 320 do not change. The states of transistors other than transistor M1 also do not change.

[0071] Next, the operation during the period from time T15 to T16 will be described. During this period, the output OUT_k is refreshed to VGL. FIG. 9C shows the ON / OFF states of the transistors in the shift register 320 at time T15.

[0072] Referring to FIG. 8, at time T15, the clock signal CK1 and the input OUT_k-1 from the previous-stage shift register change from VGL to VGH. Even if the input OUT_k-1 from the previous-stage shift register changes to VGH, since the clock signal CK2 remains at VGL, the potential of node Q is maintained at VGL.

[0073] When the clock signal CK1 changes to VGH, the potential of node N1 changes to VGH. Transistor M5 is turned on. Also, in response to the change of node N1, transistor M6 is turned on and the potential of node QB changes to VGH due to the capacitor element C3. As a result, transistor M9 is turned on and VGL is supplied from the power line to the output OUT_k (refresh).

[0074] Before time T16, the clock signal CK1 changes to VGL. The input OUT_k-1 from the previous-stage shift register remains at VGH. In response to the change of the clock signal CK1, the potential of node N1 changes to VGL. Transistors M5 and M6 are turned off. In response to the potential change of node N1, the potential of node QB becomes VGL and transistor M9 is turned off. The output line of the output OUT_k is in a floating state and the output OUT_k is maintained at VGL.

[0075] Next, the operation during the period from time T16 to T17 will be described. The output OUT_k is inverted from VGL to VGH. FIG. 9D shows the ON / OFF states of the transistors in the shift register 320 at time T16.

[0076] Referring to FIG. 8, at time T16, the clock signal CK2 changes from VGL to VGH. As shown in FIG. 9D, transistor M1 is turned on. Since the input OUT_k-1 from the previous-stage shift register is VGH, transistor M3 is turned on. Since the potential of node N1 is maintained at VGL, transistor M6 also remains off.

[0077] Also, since the input OUT_k-1 from the previous-stage shift register is VGH, the transistor M4 is turned on. As a result, the potential of node N2 changes from VGL to VGH. In response to the potential change of node N2, the transistor M7 is turned on. Since the potential of node QB maintains VGL, the transistor M9 also maintains OFF.

[0078] The transistor M1 is turned on, and since the input OUT_k-1 from the previous-stage shift register is VGH, the potential of node Q changes from VGL to VGH. The transistor M8 is turned on by the bootstrap effect of the capacitive element C1, and the output OUT_k changes from VGL to VGH.

[0079] Before time T17, the clock signal CK2 changes from VGH to VGL, and the transistor M1 turns off. However, the Q potential is maintained at VGH. Node N1 in the shift register 320 is maintained at VGL via M3, N2 is maintained at VGH via M4, and QB is maintained at VGL via M7. The states of transistors other than transistor M1 do not change. The output OUT_k is maintained at VGH via M8.

[0080] Next, the operation during the period from time T17 to T18 will be described. During this period, the output OUT_k is maintained at VGH. FIG. 9E shows the ON / OFF states of the transistors in the shift register 320 at time T17.

[0081] Referring to FIG. 8, at time T17, the clock signal CK1 changes from VGL to VGH. Node Q is VGH (actually slightly higher than VGH), and as shown in FIG. 9E, the transistors M3 and M4 are ON. Since the transistor M3 is ON, the node N1 is maintained at VGL. The potential of node QB also maintains VGL, and the transistor M9 is OFF. Before time T18, the clock signal CK1 changes to VGL. However, there is no change in the node potentials in the circuit shown in FIG. 8, and the states of the transistors do not change.

[0082] Next, the operation during the period from time T18 to T19 will be described. During this period, the output OUT_k is maintained at VGH. Also, the potential of node Q is refreshed to VGH. FIG. 9F shows the ON / OFF states of the transistors in the shift register 320 at time T18.

[0083] Referring to FIG. 8, at time T18, the clock signal CK2 changes from VGL to VGH, and the transistor M1 is turned on. Since the input OUT_k-1 from the previous-stage shift register is VGH, the potential of node Q is refreshed to VGH. There is no change in the node potentials in the circuit shown in FIG. 8, and the states of the other transistors also do not change. The output OUT_k is maintained at VGH.

[0084] Before time T19, the clock signal CK2 changes from VGH to VGL, and the transistor M1 turns off. There is no change in the node potentials in the circuit shown in FIG. 8, and the states of the other transistors also do not change. The output OUT_k is maintained at VGH.

[0085] Next, the operation during the period from time T19 to T20 will be described. At time T19, the clock signal CK1 changes from VGL to VGH, and further changes from VGH to VGL before time T20. In response to the change in the clock signal CK1, there is no change in the node potentials in the circuit shown in FIG. 8, and the states of the transistors also do not change.

[0086] Next, the operation during the period from time T20 to T21 will be described. During this period, the output OUT_k is maintained at VGH. Also, the transistors M4 and M8 turn off. FIG. 9G shows the ON / OFF states of the transistors in the shift register 320 at time T20.

[0087] At time T20, the input OUT_k-1 from the previous-stage shift register changes from VGH to VGL. Also, in response to the change of the clock signal CK2 from VGL to VGH, the transistor M1 is turned on. Since the input OUT_k-1 from the previous-stage shift register is VGL, the potential of node Q changes from VGH to VGL. As a result, the transistors M3, M4, and M8 are turned off. However, due to the capacitance of the output line, the output OUT_k is maintained at VGH. The potential of node N1 is maintained at VGL, and the potential of node N2 is maintained at VGH.

[0088] Before time T21, the clock signal CK2 changes from VGH to VGL, and the transistor M1 turns off. There is no change in the node potentials within the circuit shown in FIG. 8, and the states of the other transistors also do not change. The output OUT_k is maintained at VGH.

[0089] Next, the operation during the period from time T21 to T22 will be described. During this period, the output OUT_k toggles from VGH to VGL. FIG. 9H shows the ON / OFF states of the transistors within the shift register 320 at time T21.

[0090] Referring to FIG. 8, at time T21, the clock signal CK1 changes from VGL to VGH. Accordingly, the potential of node N1 changes from VGL to VGH. In response to the change in the potential of node N1, the transistor M5 is turned on. Also, the transistor M6 is turned on in response to the change in the potential of node N1.

[0091] When the transistor M5 is turned on, VGL is supplied to node N2 from the low-power supply line, and its potential changes from VGH to VGL. When the transistor M6 is turned on, VGH of the clock signal CK1 is supplied to node QB, and its potential changes from VGL to VGH. Due to the change in the potential of node QB from VGL to VGH, the transistor M9 is turned on. As a result, the output OUT_k changes from VGH to VGL.

[0092] Before time T22, the clock signal CK1 changes from VGH to VGL. Accordingly, the potentials of node N1 and node QB change from VGH to VGL. In response to the potential change of node N1, transistors M5 and M6 are turned off. In response to the potential change of node QB, transistor M9 is turned off. The output OUT_k is in a floating state, but maintains VGL due to the capacitance of the output line.

[0093] Next, the operation during the period T22 - T23 will be described. During this period, the potential of node Q is refreshed to VGL. The output OUT_k maintains VGL. FIG. 9I shows the ON / OFF states of the transistors in the shift register 320 at time T22.

[0094] Referring to FIG. 8, at time T22, the clock signal CK2 changes from VGL to VGH. As shown in FIG. 9I, transistor M1 is turned on. Since the input OUT_k-1 from the previous-stage shift register is VGL, the potential of node Q, which is VGL, is refreshed to VGL. There is no change in the node potentials in the circuit shown in FIG. 8, and the states of the other transistors do not change.

[0095] Before time T23, the clock signal CK2 changes from VGH to VGL. In response to the change in the clock signal CK2, transistor M1 is turned off. There is no change in the node potentials in the circuit shown in FIG. 8, and the states of the other transistors do not change. The output OUT_k is maintained at VGL.

[0096] Next, the operation during the period T23 - T24 will be described. During this period, the output OUT_k, which is VGL, is refreshed to VGL. FIG. 9J shows the ON / OFF states of the transistors in the shift register 320 at time T23.

[0097] At time T23, the clock signal CK1 changes from VGL to VGH. In response to the change in the clock signal CK1, the potential of node N1 changes from VGL to VGH. Transistor M6 turns on, and the potential of node QB changes from VGL to VGH. In response to the potential change of node QB, transistor M9 turns on. Transistor M9 supplies VGL from the low power line to the output line and refreshes the output OUT(n) (which is VGL) to VGL.

[0098] Before time T24, the clock signal CK1 changes from VGH to VGL. Along with this, the potentials of node N1 and node QB change from VGH to VGL. In response to the potential change of node N1, transistors M5 and M6 are turned off. In response to the potential change of node QB, transistor M9 is turned off. The output OUT_k is in a floating state and maintains VGL due to the capacitance of the output line. Hereinafter, the operation during the period from time T22 to T24 is repeated until time T11 of the next frame.

[0099] The ON duty of each transistor of the shift register 320 will be described. The ON duty indicates the ratio of the period during which the transistor is ON within one frame period in the operation of the shift register. As described above, transistor M1 is controlled by the clock signal CK2. Transistors M2 and M10 are controlled by the reset signal RST. Transistors M3, M4, and M8 are controlled by the potential of node Q. Transistors M5 and M6 are controlled by the potential of node N1. Transistor M7 is controlled by the potential of node N2. Transistor M9 is controlled by the potential of node QB.

[0100] Since all the transistors of the shift register 320 are N-type transistors, the H duty, which is the ratio of the period during which the gate signal (control signal) is High (VGH), corresponds to the ON duty of the transistor.

[0101] Referring to FIG. 8, among the reset signal RST, clock signals CK1 and CK2, the potential of node N1, the potential of node N2, the potential of node Q, and the potential of node QB, the signals with the longest total period of VGH are the clock signals CK1 and CK2. The H duty of each of the clock signals CK1 and CK2 depends on the length of each clock pulse with respect to the 1H period, but is 50% or less.

[0102] Next, the relationship between the shift registers 300, 310, and 320 will be described. As described above, the timing chart of the signals shown in FIG. 8 is applicable to the shift registers 300 and 310 except for the reset signal.

[0103] First, the shift register 320 shown in FIG. 7 is compared with the shift register 310 shown in FIG. 6. In the shift register 310, the transistors M2 and M10 of the shift register 320 are omitted. The other configurations are common. The transistors M2 and M10 are controlled by the reset signal. The shift register 320 resets the potential of node Q and the output OUT_k to VGL (low potential) for each frame. This can prevent malfunction of the scanning circuit and improve stability.

[0104] On the other hand, in the shift register 310, the input of the reset signal RST is also omitted. That is, the reset signal is not required for the shift register 310. This can simplify the circuit configuration.

[0105] Next, the shift register 320 shown in FIG. 7 is compared with the shift register 300 shown in FIG. 5. Similar to the shift register shown in FIG. 6, in the shift register 300, the transistors M2 and M10 of the shift register 320 are omitted. Further, the shift register 300 includes a transistor M11 instead of the capacitive element C2 of the shift register 320. The transistor M11 is controlled by the clock signal CK1, one end of the source / drain is connected to the high power line, and the other end is connected to node N1.

[0106] The operation of transistor M11 will be described. Transistor M11 is turned ON / OFF by clock signal CK1. Referring to FIG. 8, when the clock signal CK1 changes from VGL to VGH at time T17, transistor M11 is turned ON. However, since transistor M3 remains ON at the same time, node N1 is maintained at VGL. Here, it is preferable that the resistance of M3 is low. Specifically, the channel width of M3 is made sufficiently larger than that of M11. However, in this state, a through-current passing through transistors M11 and M3 is generated from the high power supply line to the low power supply line.

[0107] On the other hand, the shift register 310 shown in FIG. 6 and the shift register 320 shown in FIG. 7 include a capacitive element C2 instead of transistor M11. Thereby, the potential of node N1 is changed according to the clock signal CK1 without reducing the impedance, and the through-current is suppressed.

[0108] The state at time T17 continues until the clock signal CK1 changes to VGL before time T18. Also, the same state appears during the period from time T19 to before the clock signal CK1 changes to VGL at time T20.

[0109] After time T21, the input OUT_k-1 from the previous-stage shift register is VGL, and transistor M3 is OFF (see FIGS. 9H to 9J). After time T21, the potential level of node N1 changes in the same manner as the potential level change of the clock signal CK1. When the clock signal CK1 is VGH, transistor M11 is ON, and VGH is supplied to node N1 from the high power supply line. Thereafter, when the clock signal CK1 changes to VGL, node N1 changes to VGL through the gate capacitances of transistors M11 and M6. In this way, by repeating the potential levels of VGH and VGL at node N1, the ON duty of transistor M6 is reduced.

[0110] Figures 10A to 10J show the time variations of the potentials of the gates, sources, and drains of transistors M1 to M10 operating according to the timing chart shown in FIG. 8. As shown in FIGS. 10A to 10J, the H duty of the transistors of the shift register is 27% or less. This will be specifically described below.

[0111] In FIG. 10A, lines 401G, 401S, and 401D respectively show the time variations of the potentials of the gate, source, and drain of transistor M1. The H duty of transistor M1 is 26.67%. In FIG. 10B, lines 402G, 402S, and 402D respectively show the time variations of the potentials of the gate, source, and drain of transistor M2. The H duty of transistor M2 is 0.04%.

[0112] In FIG. 10C, lines 403G, 403S, and 403D respectively show the time variations of the potentials of the gate, source, and drain of transistor M3. The H duty of transistor M3 is 0.19%. In FIG. 10D, lines 404G, 404S, and 404D respectively show the time variations of the potentials of the gate, source, and drain of transistor M4. The H duty of transistor M4 is 0.19%.

[0113] In FIG. 10E, lines 405G, 405S, and 405D respectively show the time variations of the potentials of the gate, source, and drain of transistor M5. The H duty of transistor M5 is 26.67%. In FIG. 10F, lines 406G, 406S, and 406D respectively show the time variations of the potentials of the gate, source, and drain of transistor M6. The H duty of transistor M6 is 0%.

[0114] In FIG. 10G, lines 407G, 407S, and 407D respectively show the time variations of the potentials of the gate, source, and drain of transistor M7. The H duty of transistor M7 is 0.19%. In FIG. 10H, lines 408G, 408S, and 408D respectively show the time variations of the potentials of the gate, source, and drain of transistor M8. The H duty of transistor M8 is 0.19%.

[0115] In FIG. 10I, lines 409G, 409S, and 409D respectively show the time variations of the potentials of the gate, source, and drain of transistor M9. The H duty of transistor M9 is 26.67%. In FIG. 10J, lines 410G, 410S, and 410D respectively show the time variations of the potentials of the gate, source, and drain of transistor M10. The H duty of transistor M10 is 0.04%.

[0116] The relationship between the number of phases of the clock signal for controlling the scanning circuit and the High duty of the signals (including the input signals and the internally generated signals) of the shift register will be described below. FIG. 11 shows a partial configuration of a scanning circuit 133 (scanning circuit) controlled by a two-phase clock. Specifically, FIG. 11 shows the shift registers 350 of the (k - 1)-th stage, k-th stage, and (k + 1)-th stage, and the input and output signals of each shift register 350. As an example, FIG. 11 indicates the shift register of the (k - 1)-th stage with reference numeral 350. The shift register 350 can have any of the circuit configuration examples shown in FIGS. 5 to 7.

[0117] Each shift register 350 includes a first clock terminal CK, a second clock terminal XCK, an input terminal IN, and an output terminal SR. A first clock signal CK1 is input to the first clock terminal CK, and a second clock signal CK2 is input to the second clock terminal XCK. The output signal from the previous-stage shift register 350 is input to the input terminal IN. A start signal is input to the input terminal IN of the first-stage shift register 350. The output terminal SR outputs an output signal OUT.

[0118] FIG. 12 shows the time variation of the signals of the shift register shown in FIG. 11. Specifically, it shows the time variations of the clock signals CK1, CK2, the output signal OUT, and the potentials of nodes N1 and QB. The time variations of the potentials of nodes N1 and QB are the same. The period between each dashed line is a 1H period. Also, the clock signals CK1 and CK2 have a pulse width PW. The time variations of each signal (potential) are the same as those of the signals shown in FIG. 8.

[0119] FIG. 13 shows a partial configuration of a scanning circuit controlled by three-phase clocks. Specifically, FIG. 13 shows the shift registers 350 at the k-1 stage, k stage, and k+1 stage, and the input and output signals of each shift register 350. The terminal configuration of the shift register 350 is the same as that of the shift register 350 shown in FIG. 11. Also, each shift register 350 can have any of the circuit configuration examples shown in FIGS. 5 to 7.

[0120] Each shift register 350 is controlled by three-phase clocks. Different clock signals are input to the first clock terminals CK of three consecutive stages of shift registers 350, and different clock signals are input to the second clock terminals XCK.

[0121] In the example of FIG. 13, the first clock signal CK1 is input to the first clock terminal CK of the shift register 350_k-1 at the k-1 stage, and the second clock signal CK2 is input to the second clock terminal XCK. The second clock signal CK2 is input to the first clock terminal CK of the shift register 350_k at the k stage, and the third clock signal CK3 is input to the second clock terminal XCK. The third clock signal CK3 is input to the first clock terminal CK of the shift register 350_k+1 at the k+1 stage, and the first clock signal CK1 is input to the second clock terminal XCK.

[0122] The output signal from the previous-stage shift register 350 is input to the input terminal IN of the shift register 350. A start signal is input to the input terminal IN of the first-stage shift register 350. The output terminal SR outputs the output signal OUT.

[0123] Figure 14 shows the time variations of the clock signals CK1, CK2, CK3, and the signals (including the node potentials) of the shift register 350_k-1. Specifically, it shows the time variations of the clock signals CK1, CK2, CK3, the output signal OUT_k-1, and the potentials of nodes N1 and QB. The time variations of the potentials of nodes N1 and QB are the same. The period between each pair of dashed lines is a 1H period. Also, the clock signals CK1, CK2, CK3 have the same pulse width (the length of one period at the High level) PW and period.

[0124] The timing chart of the time variations of the clock signals CK1, CK2, CK3, and the signals (including the node potentials) of the shift register 350_k is such that in the timing chart shown in Figure 14, CK1 is rewritten as CK2, CK2 is rewritten as CK3, and CK3 is rewritten as CK1. The timing chart of the time variations of the clock signals CK1, CK2, CK3, and the signals (including the node potentials) of the shift register 350_k+1 is such that in the timing chart shown in Figure 14, CK1 is rewritten as CK3, CK2 is rewritten as CK1, and CK3 is rewritten as CK2.

[0125] That is, in Figure 14, the top clock signal is the clock signal input to the clock terminal CK, the clock signal below it is the clock signal input to the clock terminal XCK. The bottom clock signal is the clock signal not input to the shift register.

[0126] The scanning circuit shown in Figure 13 is controlled by three clock signals (three-phase clock signals), and the period of each clock signal is 3H. On the other hand, the clock period of the two-phase clock shown in Figure 12 is 2H. The pulse width PW of the clock has a finite length of 1H or less and does not depend on the number of phases of the control clock. During the period when the output OUT is at VGL, the pulse period of nodes N1 and QB is the same as the period of the clock signal input to the register 350.

[0127] As described above, the number of clocks for controlling each shift register of the scanning circuit 133 that performs overlapping scanning is 2. However, the number of clocks for controlling a scanning circuit composed of a plurality of stages of shift registers can be any integer m of 2 or more. As can be understood from the description with reference to FIGS. 11 to 13, as the number of phases m of the control clock of the scanning circuit increases, the clock period increases.

[0128] More specifically, the clock period CKP = m×H. H indicates one horizontal period. Also, the pulse width PW of each clock signal is 1H or less. The pulse widths PW and clock periods CKP of different clock signals are common. The phase differences of different clock signals are different. The phase difference between the two clock signals with the closest phases is 1H.

[0129] The H duty (HDuty), which is the ratio of the period during which the clock signal is at the High level, depends on the pulse width of the clock signal, the number of phases m of the clock of the scanning circuit, and one horizontal period H. Specifically, the following formula holds. HDuty = PW / mH

[0130] As the number of phases m of the control clock signal of the scanning circuit increases, the clock period CKP = m×H becomes longer. As described with reference to FIGS. 12 and 13, the potentials of nodes N1 and QB are at the L level during the period when the output OUT of the shift register is at the H level. Also, during the period when the output OUT of the shift register is at the L level, it changes in the same manner as the clock signal CK1. That is, these pulse widths, periods, and phases match. That is, during this period, the H duty of nodes N1 and QB is the same as that of the clock signal CK1. Also, during one frame period, the H duty of nodes N1 and QB is less than or equal to the H duty of the clock signal CK1.

[0131] In the signals (potentials) applied to the gates of the transistors of the shift register, the potentials of nodes N1 and QB are the highest at the HDuty in one frame period. The potential of node N1 is applied to the gates of transistors M5 and M6, and the potential of node QB is applied to the gate of transistor M9. Therefore, the ON duty of transistors M5, M6, and M9 is PW / mH or less.

[0132] That is, in the configuration of one embodiment of the present disclosure, in the scanning circuit of the control clock signal of two or more phases, the ON duty of transistors M5, M6, and M9 is made 1 / 2 (50%) or less. As understood from the above description, the ON duty of other transistors is smaller than the ON duty of these transistors. That is, the ON duty of each transistor in the shift register is PW / mH or less. Thereby, the characteristic deterioration of each transistor and the characteristic deterioration of the shift register including the same can be effectively suppressed.

[0133] Also, by reducing the H duty of nodes N1 and QB, the ON duty of transistors M5, M6, and M9 can be reduced. The H duty of nodes N1 and QB can be reduced by reducing the pulse width of clock signal CK1 or increasing the number of clock phases.

[0134] The inventors evaluated the influence of the pulse width of the control clock signal on the output of the scanning circuit configured by the shift register shown in FIGS. 5-7. The control clock of the scanning circuit was a two-phase clock. As a result, it was found that when the pulse width of clock signal CK1 was too small, the shift register could not form an appropriate output waveform.

[0135] FIGS. 15A-15C show the simulation results of the output waveforms of the shift register at several different pulse widths of clock signal CK1. The 1H period is 3 μs. As shown in FIGS. 15A-15C, according to the evaluation by the inventors, it was found that an appropriate output waveform can be obtained when the H duty of clock signal CK1 (similarly for CK2) is in the range of 1.3% or more.

[0136] FIG. 16 shows another configuration example 330 of the shift register. In the shift register 330, transistors M4 and M5 are omitted from the configuration of the shift register 310 shown in FIG. 6, and the second clock signal CK2 is input to the gate of transistor M7. Other components are the same as those of the shift register 310. By controlling the ON / OFF of transistor M7 with the second clock signal CK2, transistors M4 and M can be omitted. As a result, while reducing the on-duty of the transistors, the number of transistors can be reduced and the circuit area can be made smaller.

[0137] FIG. 17 shows the time variation of the signals of the shift register shown in FIG. 16. Specifically, it shows the time variations of the clock signals CK1, CK2, the output signal OUT_k-1 of the previous stage, the output signal OUT_k of the current stage, the node N1, the node Q, and the potential of the node QB. The period between each dashed line is a 1H period. Also, the clock signals CK1 and CK2 have a pulse width PW. The time variations of each signal (potential) are the same as those of each signal shown in FIG. 8.

[0138] FIG. 18 shows another configuration example 370 of the shift register. In the shift register 370, the N-type thin film transistors M1-M9 of the shift register 310 shown in FIG. 6 are replaced with P-type thin film transistors M21-M29, and further, the inputs of the power supplies VGL and VGH are swapped. That is, the power supply VGL is input to the drain of transistor M28, and the power supply VGH is input to the sources of transistors M23, M25, M27, and M29. Note that it is also possible to change the transistors of the shift registers shown in FIGS. 5, 7, and 16 from N-type transistors to P-type transistors in the same manner.

[0139] FIG. 19 shows the time variation of the signals of the shift register shown in FIG. 18. Specifically, it shows the time variations of the clock signals CK1, CK2, the output signal OUT_k-1 of the previous stage, the output signal OUT_k of the current stage, the node N1, the node N2, the node Q, and the potential of the node QB. The time variations of each signal (potential) are compared with those of each signal shown in FIG. 8, and the H level and the L level are reversed.

[0140] The embodiments of the present disclosure have been described above, but the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

Description of Reference Numerals

[0141] 10 OLED display device 133 Scanning 200 Pixel circuit 300 - 330, 350, 370 Shift register C1 - C3 Capacitive element M1 - M11 Thin film transistor

Claims

1. A scanning circuit that outputs a gate signal to a pixel circuit of a display panel, A shift register including a plurality of stages connected together; the scanning circuit is controlled by an m-phase clock signal, m being an integer equal to or greater than 2; the multiple-stage shift register sequentially outputs high-level pulses of two or more horizontal periods in a transfer step of one horizontal period; each shift register of the plurality of stages of shift registers is controlled by a two-phase clock signal including a first clock signal and a second clock signal of the m-phase clock signal; The conductivity type of all thin film transistors in each shift register of the multiple stages of shift registers is common; Each of the multiple stages of shift registers comprises: a high-level output thin film transistor including a source connected to an output terminal of the shift register and a drain connected to a high power supply line; a low-level output thin-film transistor including a drain connected to an output terminal of the shift register and a source connected to a low power supply line; a buffer thin film transistor including a source / drain to which the first clock signal is input and a source / drain connected to a gate of the low-level output thin film transistor; Including, During a period in which the output terminal outputs a low level, a control signal having the same pulse width and period as the first clock signal is input to a gate of the buffer thin film transistor; The pulse width of the first clock signal and the second clock signal is represented by PW, and one horizontal period is represented by H, The high duty of the first clock signal and the second clock signal is expressed in PW / mH, The ON duty of each thin film transistor of all the thin film transistors is PW / mH or less; Scanning circuit.

2. A scanning circuit according to claim 1 , the buffer thin film transistor is a first buffer thin film transistor; a second buffer thin film transistor, the source of which is connected to the low power line and the drain of which is connected to the gate of the low level output thin film transistor; A first thin film transistor including a source / drain to which a signal is input from a previous stage and a source / drain connected to the gate of the high-level output thin film transistor, the first thin film transistor being controlled by the second clock signal; a third thin film transistor, the third thin film transistor having a gate connected to the gate of the high level output thin film transistor and a source connected to the low power line; a fourth thin film transistor, the fourth thin film transistor having a gate connected to the gate of the high-level output thin film transistor, a drain connected to the high power line, and a source connected to the gate of the second buffer thin film transistor; a fifth thin film transistor, the fifth thin film transistor including a gate connected to the gate of the first buffer thin film transistor, a source connected to the low power line, and a drain connected to the gate of the second buffer thin film transistor; The scanning circuit further includes:

3. A scanning circuit according to claim 1 , the buffer thin film transistor is a first buffer thin film transistor; a second buffer thin film transistor including a source connected to the low power line, a drain connected to the gate of the low level output thin film transistor, and a gate to which the second clock signal is input; A first thin film transistor including a source / drain to which a signal is input from a previous stage and a source / drain connected to the gate of the high-level output thin film transistor, the first thin film transistor being controlled by the second clock signal; a third thin film transistor, the third thin film transistor having a gate connected to the gate of the high level output thin film transistor and a source connected to the low power line; The scanning circuit further includes:

4. A scanning circuit according to claim 2 or 3. a gate of the first buffer thin film transistor is connected to a transmission line of the first clock signal via a capacitive element; Scanning circuit.

5. A scanning circuit according to claim 2 or 3. A second thin film transistor including a source connected to the low power line and a drain connected to the gate of the high level output thin film transistor; The second thin film transistor is turned on for a predetermined period every frame period. Scanning circuit.

6. A scanning circuit according to claim 2 or 3. a sixth thin film transistor having a source connected to the low power line and a drain connected to the output terminal; The sixth thin film transistor is turned on for a predetermined period every frame period. Scanning circuit.

7. A scanning circuit according to claim 5 . a sixth thin film transistor having a source connected to the low power line and a drain connected to the output terminal; The sixth thin film transistor is turned on for a predetermined period every frame period. Scanning circuit.

8. A scanning circuit according to claim 7. a gate of the first buffer thin film transistor is connected to a transmission line of the first clock signal via a capacitive element; Scanning circuit.

9. A scanning circuit according to claim 1 , m is 3 or more; Scanning circuit.

10. 2. A scanning circuit according to claim 1, The high duty is 1.3% or more. Scanning circuit.

11. A scanning circuit that outputs a gate signal to a pixel circuit of a display panel, A shift register including a plurality of stages connected together; the scanning circuit is controlled by an m-phase clock signal, m being an integer equal to or greater than 2; the multiple-stage shift register sequentially outputs high-level pulses of two or more horizontal periods in a transfer step of one horizontal period; each shift register of the plurality of stages of shift registers is controlled by a two-phase clock signal including a first clock signal and a second clock signal of the m-phase clock signal; The conductivity type of all thin film transistors in each shift register of the multiple stages of shift registers is common; Each of the multiple stages of shift registers comprises: a high-level output thin film transistor including a drain connected to an output terminal of the shift register and a source connected to a high power supply line; a low-level output thin film transistor including a source connected to an output terminal of the shift register and a drain connected to a low power supply line; a buffer thin film transistor including a source / drain to which the first clock signal is input and a source / drain connected to a gate of the low-level output thin film transistor; Including, During a period in which the output terminal outputs a low level, a control signal having the same pulse width and period as the first clock signal is input to a gate of the buffer thin film transistor; The pulse width of the first clock signal and the second clock signal is represented by PW, and one horizontal period is represented by H, The high duty of the first clock signal and the second clock signal is expressed in PW / mH, The ON duty of each thin film transistor of all the thin film transistors is PW / mH or less; Scanning circuit.

12. A scanning circuit according to claim 11, the buffer thin film transistor is a first buffer thin film transistor; a second buffer thin film transistor, the drain of which is connected to the low power line and the source of which is connected to the gate of the low level output thin film transistor; A first thin film transistor including a source / drain to which a signal is input from a previous stage and a source / drain connected to the gate of the high-level output thin film transistor, the first thin film transistor being controlled by the second clock signal; a third thin film transistor, the third thin film transistor having a gate connected to the gate of the high level output thin film transistor and a drain connected to the low power line; a fourth thin film transistor, the fourth thin film transistor having a gate connected to the gate of the high-level output thin film transistor, a source connected to the high power line, and a drain connected to the gate of the second buffer thin film transistor; a fifth thin film transistor, the fifth thin film transistor having a gate connected to the gate of the first buffer thin film transistor, a drain connected to the low power line, and a source connected to the gate of the second buffer thin film transistor; The scanning circuit further includes:

13. A scanning circuit according to claim 11, the buffer thin film transistor is a first buffer thin film transistor; a second buffer thin film transistor including a drain connected to the low power line, a source connected to the gate of the low level output thin film transistor, and a gate to which the second clock signal is input; A first thin film transistor including a source / drain to which a signal is input from a previous stage and a source / drain connected to the gate of the high-level output thin film transistor, the first thin film transistor being controlled by the second clock signal; a third thin film transistor, the third thin film transistor having a gate connected to the gate of the high level output thin film transistor and a drain connected to the low power line; The scanning circuit further includes:

14. A scanning circuit according to claim 11, m is 3 or more; Scanning circuit.

15. 12. A scanning circuit as claimed in claim 11, The high duty is 1.3% or more. Scanning circuit.

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