Imaging device and electronic apparatus

Abstract

To provide an imaging device that has high imaging quality and can be manufactured at low cost.SOLUTION: A first circuit including a first transistor and a second transistor, and a second circuit including a second transistor and a photodiode are provided. The first transistor is provided on a first surface of a silicon substrate. The second transistor is provided over the first surface of the silicon substrate with a first insulating layer interposed therebetween. The silicon substrate includes a second insulating layer. The second insulating layer is provided so as to surround a side surface of the photodiode. The first transistor is a p-channel type transistor having an active region in the silicon substrate. The second transistor is an n-channel type transistor using an oxide semiconductor layer as an active layer. The photodiode has, as a light-receiving surface, a surface on the opposite side to the first surface of the silicon substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to an imaging device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention disclosed in this specification includes semiconductor devices, display devices, and their driving An example of the present invention is a method for producing the same.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Display devices, imaging devices, and electronic devices each include a semiconductor device. [Background technology]

[0004] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). Semiconductors that can be used in transistors are widely used in electronic devices such as Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are attracting attention.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2).

[0006] In addition, Patent Document 3 discloses a transistor that includes an oxide semiconductor and has an extremely low off-state current. At least part of the pixel circuit is made of CMOS (Complementary Metal Oxide Semiconductor) having a silicon semiconductor on which an (oxide semiconductor) circuit can be fabricated By using the transistor for a peripheral circuit, an imaging device with high speed and low power consumption can be fabricated. This is disclosed.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0008] Since imaging devices are assumed to be used in all environments, high imaging quality etc. are required even when the subject is a low-illuminance environment or a moving object. Also, an imaging device that can be fabricated at a lower cost while satisfying those requirements is desired. Therefore, in one aspect of the present invention, an object is to provide an imaging device capable of imaging under low illuminance. Or, an object is to provide an imaging device with a wide dynamic range. Or, an object is to provide an imaging device with high resolution.

[0009] Or, an object is to provide an imaging device with high integration. Or, an object is to provide an imaging device that can be used in a wide temperature range. Or, an object is to provide an imaging device suitable for high-speed operation. Or, an object is to provide an imaging device with low power consumption. Or, an object is to provide an imaging device with high integration. Or, an object is to provide an imaging device that can be used in a wide temperature range. Or, an object is to provide an imaging device suitable for high-speed operation. Or, an object is to provide an imaging device with low power consumption. Another object of the present invention is to provide an imaging device with a high aperture ratio. Another object of the present invention is to provide a low-cost imaging device. One of the objects is to provide a highly reliable imaging device.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a pixel circuit including a transistor formed using an oxide semiconductor; A photoelectric conversion element formed using silicon and a transistor formed using an oxide semiconductor An imaging device including a peripheral circuit having a transistor formed using a silicon Regarding.

[0012] One embodiment of the present invention is an imaging device having a first circuit and a second circuit, The second circuit has a first transistor and a second transistor, and the second circuit has a third transistor and The first transistor is provided on a first surface of a silicon substrate, and The photodiode is provided on the silicon substrate, and the second transistor is The silicon substrate has a first insulating layer, and the first insulating layer is a photodiode. The first transistor is a p-ch type transistor, and the first The first transistor has an active region on a silicon substrate, and the second and third transistors are n-ch type transistors. The active layers of the second and third transistors have an oxide semiconductor, and the light receiving surface of the photodiode is provided on the surface opposite to the first surface of the silicon substrate. The second and third transistors are n-ch type transistors. The active layers of the second and third transistors have an oxide semiconductor, and the light receiving surface of the photodiode is provided on the surface opposite to the first surface of the silicon substrate. It is characterized in that.

[0013] The first transistor and the second transistor can form a CMOS circuit. .

[0014] The second circuit further has fourth to sixth transistors. The fourth to sixth transistors are n-ch type transistors. The active layers of the fourth to sixth transistors have an oxide semiconductor. One of the source or drain of the third transistor is electrically connected to the anode or cathode of the photodiode. The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. The other of the source or drain of the third transistor is electrically connected to the gate of the fifth transistor. One of the source or drain of the fifth transistor may be electrically connected to one of the source or drain of the sixth transistor. The fourth to sixth transistors are n-ch type transistors. The active layers of the fourth to sixth transistors have an oxide semiconductor. One of the source or drain of the third transistor is electrically connected to the anode or cathode of the photodiode. The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. The other of the source or drain of the third transistor is electrically connected to the gate of the fifth transistor. One of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor. It may be.

[0015] The oxide semiconductor layer preferably contains In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). It preferably contains In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0016] Also, the crystal plane orientation on the first surface of the silicon substrate is preferably the (110) plane. .

Advantages of the Invention

[0017] According to one aspect of the present invention, an imaging device capable of imaging under low illuminance can be provided. Or, an imaging device with a wide dynamic range can be provided. Or, an imaging device with high resolution can be provided. Or, an imaging device with high integration can be provided. Or, an imaging device that can be used in a wide temperature range can be provided. Or, an imaging device suitable for high-speed operation can be provided. Or, an imaging device with low power consumption can be provided. Or, an imaging device with a high aperture ratio can be provided. Or, a low-cost imaging device can be provided. Or, a highly reliable imaging device can be provided. It should be noted that the description of these effects does not prevent the existence of other effects. It should be noted that one aspect of the present invention does not necessarily have all of these effects. Other effects will naturally become clear from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

[0018]

[0019]

Brief Description of the Drawings

[0019]

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Mode for Carrying Out the Invention

[0020] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function in different drawings, and the repeated description may be omitted. In addition, the hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings. In addition, in this specification and the like, when it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected, the case where X and Y are functionally connected, and X and Y are physically connected. When X and Y are physically connected, it means that X and Y are directly connected or indirectly connected through other elements. In the following description, when it is described that X and Y are electrically connected, it means that there is an electrical conduction path between X and Y, and current can flow between them. When it is described that X and Y are functionally connected, it means that X and Y cooperate with each other to perform a specific function, even if there is no direct electrical connection between them.

[0021] In this specification and the like, when it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are physically connected. including the case where X and Y are directly connected. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in a figure or text, but also includes those other than the connection relationship shown in the figure or text.

[0022] As an example of the case where X and Y are electrically connected, an element (e.g., a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y can be connected between X and Y by one or more. Note that a switch has a function of controlling on / off. That is, a switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, a switch has a function of selecting and switching a path for current to flow.

[0023] As an example of the case where X and Y are functionally connected, a circuit (e.g., a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) that enables the functional connection between X and Y can be connected between X and Y by one or more. Note that, for example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y shall be considered to be functionally connected.

[0024] Note that when it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected (that is, connected with another element or another circuit interposed between X and Y ), the case where X and Y are functionally connected (that is, functionally connected with another circuit interposed between X and Y), and the case where X and Y are directly connected (that is, connected without another element or another circuit interposed between X and Y). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as the case where it is only explicitly described that they are connected.

[0025] Note that even if components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of a plurality of components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of a plurality of components.

[0026] Note that, for example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the transistor The source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X, and the drain of the transistor (or the second terminal, etc.) is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. In this case, it can be expressed as follows like this.

[0027] For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and they are electrically connected in the order of X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), Y." Or it can be expressed as "The source of the transistor (or the first terminal, etc.) is electrically connected to X, the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), Y are electrically connected in this order." Or it can be expressed as "X is electrically connected to Y through the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), Y are provided in this connection order." By using an expression method similar to these examples to define the connection order in the circuit configuration, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, By stipulating the connection order in the circuit configuration in this way, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, Let Z2 be present in an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). Suppose so.

[0028] (Embodiment 1) In this embodiment, an imaging device which is one aspect of the present invention will be described with reference to the drawings.

[0029] FIG. 1 is a cross-sectional view showing the configuration of an imaging device according to one aspect of the present invention. The imaging device shown in FIG. 1(A) includes a transistor 51 having an active region on a silicon substrate 40, transistors 52 and 53 having an oxide semiconductor layer as an active layer, and a photodiode 60 provided on the silicon substrate 40. Each transistor and the photodiode 60 have electrical connections with a conductor 70 embedded in an insulating layer and each wiring layer. Further, the anode 61 of the photodiode 60 has an electrical connection with the conductor 70 via a low-resistance region 63. The imaging device includes a transistor 51 having an active region on a silicon substrate 40, transistors 52 and 53 having an oxide semiconductor layer as an active layer, and a photodiode 60 provided on the silicon substrate 40. Each transistor and the photodiode 60 have electrical connections with a conductor 70 embedded in an insulating layer and each wiring layer. Further, the anode 61 of the photodiode 60 has an electrical connection with the conductor 70 via a low-resistance region 63. and transistors 52 and 53 having an oxide semiconductor layer as an active layer, and a photodiode 60 provided on the silicon substrate 40. Each transistor and the photodiode 60 have electrical connections with a conductor 70 embedded in an insulating layer and each wiring layer. Further, the anode 61 of the photodiode 60 has an electrical connection with the conductor 70 via a low-resistance region 63. Each transistor and the photodiode 60 have electrical connections with a conductor 70 embedded in an insulating layer and each wiring layer. Further, the anode 61 of the photodiode 60 has an electrical connection with the conductor 70 via a low-resistance region 63. Note that the low-resistance region 63 can be formed as a p-type region in which impurities are added to the silicon substrate 40, but as shown in FIG. 58(A), a metal may be used instead. Further, as shown in FIG. 58(B), a configuration in which a metal is provided so as to penetrate the p-type region may also be used. Note that the low-resistance region 63 can be formed as a p-type region in which impurities are added to the silicon substrate 40, but as shown in FIG. 58(A), a metal may be used instead. Further, as shown in FIG. 58(B), a configuration in which a metal is provided so as to penetrate the p-type region may also be used. .

[0030] Note that the form of the electrical connection in the above elements is an example. In addition, wirings, electrodes, etc. provided on the same surface or provided in the same process use the same reference numerals, and reference numerals are attached only to representative portions. Further, the conductor 70 embedded in the insulating layer will be denoted by the same reference numeral throughout. Further, in the drawings, each wiring, each electrode, and the conductor 70 are illustrated as individual elements, but those which are electrically connected are regarded as the same element. Note that the form of the electrical connection in the above elements is an example. In addition, wirings, electrodes, etc. provided on the same surface or provided in the same process use the same reference numerals, and reference numerals are attached only to representative portions. Further, the conductor 70 embedded in the insulating layer will be denoted by the same reference numeral throughout. Further, in the drawings, each wiring, each electrode, and the conductor 70 are illustrated as individual elements, but those which are electrically connected are regarded as the same element. Note that the form of the electrical connection in the above elements is an example. In addition, wirings, electrodes, etc. provided on the same surface or provided in the same process use the same reference numerals, and reference numerals are attached only to representative portions. Further, the conductor 70 embedded in the insulating layer will be denoted by the same reference numeral throughout. Further, in the drawings, each wiring, each electrode, and the conductor 70 are illustrated as individual elements, but those which are electrically connected are regarded as the same element.

[0031] Note that the form of the electrical connection in the above elements is an example. In addition, wirings, electrodes, etc. provided on the same surface or provided in the same process use the same reference numerals, and reference numerals are attached only to representative portions. Further, the conductor 70 embedded in the insulating layer will be denoted by the same reference numeral throughout. Further, in the drawings, each wiring, each electrode, and the conductor 70 are illustrated as individual elements, but those which are electrically connected are regarded as the same element. Note that the form of the electrical connection in the above elements is an example. In addition, wirings, electrodes, etc. provided on the same surface or provided in the same process use the same reference numerals, and reference numerals are attached only to representative portions. Further, the conductor 70 embedded in the insulating layer will be denoted by the same reference numeral throughout. Further, in the drawings, each wiring, each electrode, and the conductor 70 are illustrated as individual elements, but those which are electrically connected are regarded as the same element. Note that the form of the electrical connection in the above elements is an example. In addition, wirings, electrodes, etc. provided on the same surface or provided in the same process use the same reference numerals, and reference numerals are attached only to representative portions. Further, the conductor 70 embedded in the insulating layer will be denoted by the same reference numeral throughout. Further, in the drawings, each wiring, each electrode, and the conductor 70 are illustrated as individual elements, but those which are electrically connected are regarded as the same element. Note that the form of the electrical connection in the above elements is an example. In addition, wirings, electrodes, etc. provided on the same surface or provided in the same process use the same reference numerals, and reference numerals are attached only to representative portions. Further, the conductor 70 embedded in the insulating layer will be denoted by the same reference numeral throughout. Further, in the drawings, each wiring, each electrode, and the conductor 70 are illustrated as individual elements, but those which are electrically connected are regarded as the same element. Note that the form of the electrical connection in the above elements is an example. In addition, wirings, electrodes, etc. provided on the same surface or provided in the same process use the same reference numerals, and reference numerals are attached only to representative portions. Further, the conductor 70 embedded in the insulating layer will be denoted by the same reference numeral throughout. Further, in the drawings, each wiring, each electrode, and the conductor 70 are illustrated as individual elements, but those which are electrically connected are regarded as the same element. In some cases, a committee may be established.

[0032] The imaging device also includes a transistor 51 and a photodiode disposed on a silicon substrate 40. A first layer 1100 having a gate 60 and a light control layer 64, a wiring layer 71 and an insulating layer 81 , 82, and a second layer 1200 having transistors 52, 53 and an insulating layer. A third layer 1300 having a wiring layer 72, a wiring layer 73 and insulating layers 84 and 85. The first layer 1100, the second layer 1200, the third layer 1100, and the fourth layer 1400 are connected to each other. 300, and the fourth layer 1400 are laminated in that order.

[0033] In addition, there may be cases where some of the above-mentioned wirings are not provided, or where wirings, transistors, etc. other than those described above are provided. Each layer may contain the above-mentioned layers. Also, layers other than those mentioned above may be contained in the laminate structure. In addition, some of the above layers may not be included. It functions as an insulating film.

[0034] The side surface of the photodiode 60 in the first layer 1100 is surrounded by a light control layer 64. The light control layer 64 also acts as an isolation layer between adjacent photodiodes. The light incident on the side of the photodiode 60 from the light receiving surface is reflected by the light control layer 64. Therefore, the photodiode 60 of the adjacent pixel can be attenuated. This makes it possible to prevent light from entering the device, thereby making it possible to obtain images with less noise.

[0035] It is preferable to use a material having a refractive index lower than that of silicon for the light control layer 64. For example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, etc. Insulators can be used. Also, organic materials such as acrylic resin and polyimide can be used. By using a material with a refractive index lower than that of silicon, the light incident on the side of the photodiode 60 is more likely to be totally reflected. Also, instead of the above materials, gases such as air, nitrogen, oxygen, argon, helium, etc. can be used. In this case, a pressure lower than atmospheric pressure can also be used.

[0036] As the light control layer 64, a material that easily absorbs light may be used. For example, carbon-based black pigments such as carbon black, titanium-based black pigments such as titanium black, iron oxides, composite oxides of copper and chromium, composite oxides of copper, chromium, and zinc, etc., and resins added with such materials can be used.

[0037] Note that, as shown in Fig. 58(C), a part of the side of the photodiode 60 does not necessarily need to be provided with the light control layer 64. Here, by using metals such as tungsten, tantalum, titanium, and aluminum in the low-resistance region 63, the incident light can be reflected and made to function as a light control layer. Also, metals with low reflectivity such as molybdenum and chromium may be used.

[0038] Also, as shown in Fig. 58(D), a metal may be provided so as to penetrate the light control layer 64. Note that a part of the metal in the light control layer 64 can be electrically connected to the anode 61 of the photodiode 60.

[0039] ​​​​Also, in the depth direction of the portion (photodiode portion) indicated by the dashed line A1 - A2 in Fig. 1(A) The top view can be in the form shown in, for example, Figs. 59(A), (B), (C), (D), (E), and (F). It can be in such a form.

[0040] In Fig. 59(A), the top surface shape of the light - receiving portion 60p of the photodiode 60 is substantially rectangular, and a light control layer 64 is provided around it. A light control layer 64 is provided around it.

[0041] In Fig. 59(B), the top surface shape of the light - receiving portion 60p is substantially rectangular, and a light control layer 64 is fragmentarily provided around it. Note that the light - receiving portion 60p in Figs. 59(A) and (B) is shown as substantially square, but it may also be substantially rectangular, substantially trapezoidal, or the like. It may also be substantially rectangular, substantially trapezoidal, or the like.

[0042] Fig. 59(C) is an example of the top view of the photodiode portion in the configuration of Fig. 58(C). .

[0043] In Fig. 59(D), the top surface shape of the light - receiving portion 60p is substantially hexagonal, and a light control layer 64 is provided around it. A light control layer 64 is provided around it.

[0044] In Fig. 59(E), the top surface shape of the light - receiving portion 60p is substantially triangular, and a light control layer 64 is provided around it. A light control layer 64 is provided around it.

[0045] In Fig. 59(F), the top surface shape of the light - receiving portion 60p is substantially circular, and a light control layer 64 is provided around it. A light control layer 64 is provided around it.

[0046] Note that in the configurations shown in Figs. 59(C) to 59(F) as well, a configuration in which the light control layer 64 is fragmentarily provided may be adopted. Also, the light - receiving portion 60p may be a polygon or an ellipse other than the above. It may also be a polygon or an ellipse other than the above. It may be.

[0047] Further, the low-resistance region 63 can be replaced with a structure having metal as shown in FIG. 58(B). Also, the light control layer 64 can be replaced with a structure having metal as shown in FIG. 58(D).

[0048] Since the side surface of the photodiode is covered with the light control layer 64 or the like as described above, light incident on the side surface of the photodiode 60 from various angles can be reflected or attenuated within the photodiode 60.

[0049] Further, the low-resistance region 63 can be shared by a plurality of photodiodes (a plurality of pixels). By sharing the low-resistance region 63, the number of wirings and the like can be reduced. For example, when the upper surface shape of the light receiving portion 60p as shown in FIG. 59(A) is substantially square, the low-resistance region 63 can be shared by four photodiodes as shown in FIG. 60(A). When the upper surface shape of the light receiving portion 60p is substantially square as shown in FIG. 59(A), the low-resistance region 63 can be shared by four photodiodes as shown in FIG. 60(A).

[0050] When the upper surface shape of the light receiving portion 60p is substantially hexagonal as shown in FIG. 59(D), the low-resistance region 63 can be shared by three photodiodes as shown in FIG. 60(B).

[0051] When the upper surface shape of the light receiving portion 60p is substantially triangular as shown in FIG. 59(E), the low-resistance region 63 can be shared by six photodiodes as shown in FIG. 60(C).

[0052] Note that the silicon substrate 40 is not limited to a bulk silicon substrate, and may be an SOI substrate. Further, instead of the silicon substrate 40, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductor ​​​​​​​​​​ A substrate made of a body can also be used.

[0053] In the above laminate structure, between the first layer 1100 having the transistor 51 and the photodiode 60, and the third layer 1300 having the transistor 52 and the transistor 53 an insulating layer 80 is provided. Hydrogen in the insulating layer provided near the active region of the transistor 51 terminates the dangling

[0054] bond of silicon. Therefore, the hydrogen has the effect of improving the reliability of the transistor 51 . On the other hand, hydrogen in the insulating layer provided near the oxide semiconductor layer which is the active layer of the transistor 52 and the transistor 53 etc. is one of the factors for generating carriers in the oxide semiconductor . Therefore, the hydrogen may be a factor for lowering the reliability of the transistor 52 and the transistor 53 etc. Therefore, when laminating one layer having a transistor using a silicon-based semiconductor material and the other layer having a transistor using an oxide semiconductor it is preferable to provide an insulating layer 80 having a function of preventing the diffusion of hydrogen between them. By confining hydrogen in one layer with the insulating layer 80, the reliability of the transistor 51 can be improved. Also, the reliability of the transistor 52 and the transistor 53 etc. can be simultaneously improved by suppressing the diffusion of hydrogen from one layer to the other layer . As the insulating layer 80, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0055] ​

[0056] The above transistor 52 and photodiode 60 form circuit 91, and transistors 5 1 and transistor 53 form circuit 92. Circuit 91 can function as a pixel circuit, and circuit 92 can function as a driving circuit for driving circuit 91.

[0057] Circuit 91 can have a configuration such as the circuit diagram shown in FIG. 1(B), for example. One of the source or drain of transistor 52 and the cathode 62 of photodiode 60 are electrically connected, and the other of the source or drain of transistor 52, the gate of transistor 54 (not shown in FIG. 1(A)), and one of the source or drain of transistor 55 (not shown in FIG. 1(A)) are electrically connected to a charge storage part (FD). Specifically, the charge storage part is composed of, for example, the depletion layer capacitance of the source or drain of transistors 52 and 53, the gate capacitance of transistor 54, and wiring capacitance.

[0058] Here, transistor 52 can have a function as a transfer transistor for controlling the potential of the charge storage part (FD) according to the output of photodiode 60. Also, transistor 54 can have a function as an amplification transistor for outputting a signal according to the potential of the charge storage part (FD). Also, transistor 55 can have a function as a reset transistor for initializing the potential of the charge storage part (FD).

[0059]

[0060] Circuit 92 can have a configuration including, for example, a CMOS inverter as shown in the circuit diagram of FIG. 1(C).​​​​​​​​​​​ It can be done. The gates of transistor 51 and transistor 53 are electrically connected. One of the source or drain of transistor 51 is electrically connected to one of the source or drain of transistor 53. Also, the other of the source or drain of both transistors is electrically connected to separate wirings respectively. That is, a CMOS circuit is formed by transistor 51 having an active region on a silicon substrate and transistor 53 having an oxide semiconductor layer as an active layer.

[0061] In the above imaging device, transistor 51 having an active region on silicon substrate 40 is of p-ch type, and transistors 52 to 55 having an oxide semiconductor layer as an active layer are of n-ch type.

[0062] In circuit 91, by forming all the transistors included in circuit 91 in the third layer 1300, its electrical connection form can be facilitated, and the manufacturing process can be simplified.

[0063] Also, since a transistor having an oxide semiconductor has extremely low off-current characteristics, the dynamic range of imaging can be expanded. In the circuit configuration shown in Fig. 1(B), when the intensity of light incident on photodiode 60 is large, the potential of the charge accumulation part (FD) becomes small. Since a transistor using an oxide semiconductor has an extremely low off-current, even when the gate potential is extremely small, a current corresponding to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be widened.

[0064] Also, due to the low off-current characteristics of transistor 52 and transistor 55, the period during which the charge storage section (FD) can hold charges can be made extremely long. Therefore, a global shutter method that performs charge accumulation operations simultaneously for all pixels without complicating the circuit configuration and operation method can be applied. Accordingly, even if the subject is a moving object, an image with little distortion can be easily obtained. Also, since the exposure time (the period during which the charge accumulation operation is performed) can be lengthened by the global shutter method, it is also suitable for imaging in low-illumination environments.

[0065] In addition, a transistor using an oxide semiconductor has a smaller temperature dependence of electrical characteristic variations than a transistor using silicon, so it can be used in an extremely wide temperature range. Thus, imaging devices and semiconductor devices having transistors using an oxide semiconductor are also suitable for mounting on automobiles, aircraft, spacecraft, etc.

[0066] Also, for transistors 52 and transistor 55 for controlling the potential of the charge storage section (FD), transistors with less noise are preferred. Transistors having two-layer or three-layer oxide semiconductor layers to be described later have an embedded channel type and have extremely noise-resistant characteristics. Therefore, by using such transistors, an image with less noise can be obtained.

[0067] Also, in circuit 91, since the photodiode 60 provided in the first layer 1100 and the transistor provided in the third layer 1300 can be formed so as to overlap, the integration degree of the pixels can be increased. That is, the resolution of the imaging device can be increased. Also, the On Route 91, since no transistors are formed on the silicon substrate, the area of the photodiode can be increased. Therefore, an image with less noise can be obtained even in a low-illumination environment.

[0068] Also, in Circuit 92, since the process of forming an n-ch type transistor having an active region on the silicon substrate 40 is unnecessary, the formation processes such as the p-well and the n-type impurity region can be omitted, and the processes can be significantly reduced. Also, the n-ch type transistor of the CMOS circuit can be fabricated simultaneously with the transistors included in Circuit 91 described above.

[0069] The imaging device shown in FIG. 1 has a light-receiving surface of the photodiode 60 on the surface opposite to the surface on which the transistor 51 is formed in the silicon substrate 40. Therefore, an optical path can be secured without being affected by various transistors and wirings, and a pixel with a high aperture ratio can be formed. It should be noted that the light-receiving surface of the photodiode 60 can also be the same as the surface on which the transistor 51 is formed.

[0070] Also, the structures of the transistors and the photodiodes included in the imaging device in the present embodiment are examples. Therefore, for example, Circuit 91 can also be configured with transistors having an active region or an active layer made of silicon or the like. Also, Circuit 92 can be configured with transistors having an oxide semiconductor layer in the active layer. Also, the photodiode 60 can be configured with an amorphous silicon layer as a photoelectric conversion layer. Also, the transistor 51 having an active region on the silicon substrate 40 can be an n-ch type.

[0071] FIG. 2(A) is a cross-sectional view of an example of an embodiment in which a color filter or the like is added to the imaging device shown in FIG. 1(A). The cross-sectional view shows an area having a circuit 91 for three pixels (area 91a, area 91b , region 91c), and region 92a having a portion of circuitry 92. An insulating layer 1500 is formed on the photodiode 60 formed at 1500. For the 00, a silicon oxide film or the like having high transparency to visible light can be used. A silicon nitride film may be laminated as the ionization film. Alternatively, a dielectric film such as hafnium oxide may be laminated. 15), a configuration may be adopted in which the insulating layer 1500 is not provided.

[0072] A light-shielding layer 1510 is formed on the insulating layer 1500. The light-shielding layer 1510 is formed by The filter has a function of preventing the mixing of colors of light passing through it. 510 is a graph showing the characteristic change caused by light irradiation of a transistor having an active region on a silicon substrate 40. The light-shielding layer 1510 is a metal layer such as aluminum or tungsten. Alternatively, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated. As shown in FIG. 56(B), the light-shielding layer 1510 may not be provided. Cut.

[0073] An organic resin layer 1520 is formed as a planarizing film on the insulating layer 1500 and the light-shielding layer 1510. The color filters 153 are disposed on the regions 91a, 91b, and 91c, respectively. 0a, color filter 1530b and color filter 1530c are formed in pairs. The color filter 1530a, the color filter 1530b, and the color filter 1530c are By assigning colors such as R (red), G (green), and B (blue) to 530c respectively, , a color image can be obtained. As shown in Fig. 56(C), the organic resin layer 152 can also be configured not to be provided. Also, as shown in Fig. 56(D), the insulating layer 150 0, the light-shielding layer 1510, and the organic resin layer 1520 can also be configured not to be provided. Also, although not shown in the figure, a configuration can be adopted in which any two of the insulating layer 1500, the light-shielding layer 1510, and the organic resin layer 1520 are not provided.

[0074] A microlens array 1540 is provided on the color filters 1530a, 1530b, and 1530c. Therefore, the light passing through the individual lenses of the microlens array 1540 passes through the color filter directly below and is irradiated onto the photodiode.

[0075] Also, as shown in Fig. 57(A), a light-shielding layer 1510 may be provided between the respective color filters.

[0076] Also, as shown in Fig. 57(B), a light-shielding layer 1510 may be provided so as to cover the boundaries of the respective lenses in the microlens array 1540.

[0077] Also, as shown in Fig. 57(C), the light-shielding layer 1510 may be omitted, and the light control layer 64 may extend between the respective color filters.

[0078] Also, as shown in Fig. 57(D), the light-shielding layer 1510 may be omitted, and the light control layer 64 may extend between the respective lenses in the microlens array 1540.

[0079] Also, as shown in FIG. 61(A), the light control layer 64 is formed to cover the side surface of the photodiode 60 not over the entire depth direction of the photodiode 60, but only in a part closer to the light receiving surface. It may be formed so as to cover the side surface of the photodiode 60 in a part closer to the light receiving surface. Also, as shown in FIG. 61(B), it may be formed so as to cover the side surface of the photodiode 60 in a part farther from the light receiving surface. Note that the region 66 is a part of the silicon substrate 40 and may be a part of the configuration of the photodiode 60. Also, as shown in FIG. 61(B), it may be formed so as to cover the side surface of the photodiode 60 in a part farther from the light receiving surface. Note that the region 66 is a part of the silicon substrate 40 and may be a part of the configuration of the photodiode 60. It may be formed so as to cover the side surface of the photodiode 60 in a part farther from the light receiving surface. Note that the region 66 is a part of the silicon substrate 40 and may be a part of the configuration of the photodiode 60. It may be formed so as to cover the side surface of the photodiode 60 in a part farther from the light receiving surface. Note that the region 66 is a part of the silicon substrate 40 and may be a part of the configuration of the photodiode 60.

[0080] Also, FIG. 62(A) shows a top view of the photodiode 60 and the light control layer 64. FIG. 62(B) shows a top view of the light shielding layer 1510. FIG. 62(C) shows a top view of the color filter 1530. FIG. 62(D) is a diagram showing a superposition of FIGS. 62(A), (B), (C) and the transistor 50 included in the circuit 91. Since the transistor 50 included in the circuit 91 can be formed so as to overlap with the photodiode 60, the aperture ratio of the photodiode 60 can be increased. Also, FIG. 62(A) shows a top view of the photodiode 60 and the light control layer 64. FIG. 62(B) shows a top view of the light shielding layer 1510. FIG. 62(C) shows a top view of the color filter 1530. FIG. 62(D) is a diagram showing a superposition of FIGS. 62(A), (B), (C) and the transistor 50 included in the circuit 91. Since the transistor 50 included in the circuit 91 can be formed so as to overlap with the photodiode 60, the aperture ratio of the photodiode 60 can be increased. Also, FIG. 62(A) shows a top view of the photodiode 60 and the light control layer 64. FIG. 62(B) shows a top view of the light shielding layer 1510. FIG. 62(C) shows a top view of the color filter 1530. FIG. 62(D) is a diagram showing a superposition of FIGS. 62(A), (B), (C) and the transistor 50 included in the circuit 91. Since the transistor 50 included in the circuit 91 can be formed so as to overlap with the photodiode 60, the aperture ratio of the photodiode 60 can be increased. Also, FIG. 62(A) shows a top view of the photodiode 60 and the light control layer 64. FIG. 62(B) shows a top view of the light shielding layer 1510. FIG. 62(C) shows a top view of the color filter 1530. FIG. 62(D) is a diagram showing a superposition of FIGS. 62(A), (B), (C) and the transistor 50 included in the circuit 91. Since the transistor 50 included in the circuit 91 can be formed so as to overlap with the photodiode 60, the aperture ratio of the photodiode 60 can be increased. Also, FIG. 62(A) shows a top view of the photodiode 60 and the light control layer 64. FIG. 62(B) shows a top view of the light shielding layer 1510. FIG. 62(C) shows a top view of the color filter 1530. FIG. 62(D) is a diagram showing a superposition of FIGS. 62(A), (B), (C) and the transistor 50 included in the circuit 91. Since the transistor 50 included in the circuit 91 can be formed so as to overlap with the photodiode 60, the aperture ratio of the photodiode 60 can be increased. Also, FIG. 62(A) shows a top view of the photodiode 60 and the light control layer 64. FIG. 62(B) shows a top view of the light shielding layer 1510. FIG. 62(C) shows a top view of the color filter 1530. FIG. 62(D) is a diagram showing a superposition of FIGS. 62(A), (B), (C) and the transistor 50 included in the circuit 91. Since the transistor 50 included in the circuit 91 can be formed so as to overlap with the photodiode 60, the aperture ratio of the photodiode 60 can be increased.

[0081] The support substrate 1600 is provided in contact with the fourth layer 1400. As the support substrate 1600, a semiconductor substrate such as a silicon substrate, a glass substrate, a metal substrate, a hard substrate such as a ceramic substrate can be used. Note that an inorganic insulating layer or an organic resin layer serving as an adhesive layer may be formed between the fourth layer 1400 and the support substrate 1600. The support substrate 1600 is provided in contact with the fourth layer 1400. As the support substrate 1600, a semiconductor substrate such as a silicon substrate, a glass substrate, a metal substrate, a hard substrate such as a ceramic substrate can be used. Note that an inorganic insulating layer or an organic resin layer serving as an adhesive layer may be formed between the fourth layer 1400 and the support substrate 1600. The support substrate 1600 is provided in contact with the fourth layer 1400. As the support substrate 1600, a semiconductor substrate such as a silicon substrate, a glass substrate, a metal substrate, a hard substrate such as a ceramic substrate can be used. Note that an inorganic insulating layer or an organic resin layer serving as an adhesive layer may be formed between the fourth layer 1400 and the support substrate 1600. The support substrate 1600 is provided in contact with the fourth layer 1400. As the support substrate 1600, a semiconductor substrate such as a silicon substrate, a glass substrate, a metal substrate, a hard substrate such as a ceramic substrate can be used. Note that an inorganic insulating layer or an organic resin layer serving as an adhesive layer may be formed between the fourth layer 1400 and the support substrate 1600.

[0082] Note that the circuit 91 and the circuit 92 may be connected to an external power supply circuit, a control circuit, etc. using the wiring layer 72 or the wiring layer 73 in the fourth layer 1400. Note that the circuit 91 and the circuit 92 may be connected to an external power supply circuit, a control circuit, etc. using the wiring layer 72 or the wiring layer 73 in the fourth layer 1400.

[0083] In the configuration of the above imaging device, the color filters 1530a, 1530b, and By using the optical conversion layer 1550 (see Fig. 2(B)) instead of the call color filter 1530c An imaging device capable of obtaining images in various wavelength regions can be obtained.

[0084] For example, if a filter that blocks light with a wavelength equal to or less than that of visible light is used for the optical conversion layer 1550, an infrared imaging device can be obtained. Further, if a filter that blocks light with a wavelength equal to or less than that of near-infrared light is used for the optical conversion layer 1550 a far-infrared imaging device can be obtained. Also, if a filter that blocks light with a wavelength equal to or greater than that of visible light is used for the optical conversion layer 1550, an ultraviolet imaging device can be obtained .

[0085] In addition, when an infrared imaging device is used, germanium may be added so that the bandgap of the photoelectric conversion layer of the photodiode 60 becomes narrow to improve the sensitivity to infrared rays. Further, when an ultraviolet imaging device is used, an oxide semiconductor layer having a wide bandgap or the like may be used for the photoelectric conversion layer to improve the sensitivity to ultraviolet rays.

[0086] Also, if a scintillator is used for the optical conversion layer 1550, an imaging device that obtains an image visualizing the intensity of radiation used for an X-ray imaging device or the like can be obtained. When radiation such as X-rays transmitted through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence. Then, the image data is acquired by detecting the light with the photodiode 6 0. Further, an imaging device having such a configuration may be used for a radiation detector or the like. When radiation such as X-rays or gamma rays is irradiated, the scintillator absorbs the energy thereof and is converted into light (fluorescence) such as visible light or ultraviolet light. Then, the image data is acquired by detecting the light with the photodiode 60. Further, an imaging device having such a configuration may be used for a radiation detector or the like.

[0087] When irradiated with radiation such as X-rays or gamma rays, the scintillator absorbs the energy ​​​​It is made of a substance that emits visible light or ultraviolet light, or a material containing such a substance. For example, Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO and other materials, or those dispersed in resins or ceramics are known.

[0088] Figure 3 is a conceptual diagram showing the configuration of the imaging device. Circuit 1730 and circuit 1740 are arranged on the side of the pixel matrix 1700 having circuit 91. Circuit 1730 can act as, for example, a driving circuit for a reset transistor. In this case, circuit 1730 and the transistor 55 in FIG. 1(B) are electrically connected. Circuit 1740 can act as, for example, a driving circuit for a transfer transistor. In this case, circuit 1740 and the transistor 52 in FIG. 1(B) are electrically connected. Note that in FIG. 3, circuit 17 30 and circuit 1740 are shown arranged separately, but they may be arranged together in one area as a circuit 1 730 and circuit 1740 configuration.

[0089] Also, circuit 1750 is connected to the pixel matrix 1700. Circuit 1750 can function as, for example , a driving circuit for selecting a vertical output line electrically connected to transistor 54 and operate.

[0090] Also, circuit 1760 may be connected to the pixel matrix 1700. Circuit 1760 can , for example, have functions such as a circuit obtained by dividing circuit 1750, a power supply circuit, or a memory circuit . Note that a configuration without circuit 1760 can also be adopted.

[0091] An example of the specific positional relationship of each of the above circuits is shown in FIG. 3(B). For example, each of circuit 1730, circuit 1740, circuit 1750, and circuit 1760 is provided in, for example, four regions. Note that the position and occupied area of each circuit are not limited to the illustrated example. And a pixel matrix 1700 is provided inside the region where these circuits are arranged. Signal lines, power supply lines, etc. that are respectively connected to each of the circuits 1730, circuit 1740, circuit 1750, circuit 1760, and the pixel circuits of the pixel matrix 1700 are electrically connected to the wiring formed on the silicon substrate 40. Also, the wiring is electrically connected to a terminal 1 770 formed around the silicon substrate 40. The terminal 1770 formed on the silicon substrate 40 can be electrically connected to an external circuit by wire bonding or the like.

[0092] Circuits 1730 and 1740 are drive circuits with a binary output of "Low" or "High". Therefore, as shown in FIG. 4(A), it can be driven by a combination of a shift register 1800 and a buffer circuit 1900.

[0093] Also, circuit 1750 can be constituted by a shift register 1810, a buffer circuit 1910, and an analog switch 2100 as shown in FIG. 4(B). Each vertical output line 21 10 is selected by the analog switch 2100, and the potential of the selected vertical output line 2110 is output to the output line 2200. The analog switch 2100 is sequentially selected by the shift register 1810 and the buffer circuit 1910.

[0094] In one aspect of the present invention, all or part of circuits 1730, 1740, and 1750 ​Let it be configured to include circuit 92. That is, the above shift register 1800, buffer circuit 1900, shift register 1810, buffer circuit 1910, and analog switch 2 100 are all or any of them p-ch type transistors having active regions on the silicon substrate 40 and n-ch type transistors with an oxide semiconductor layer as the active layer, forming a CMOS circuit having.

[0095] In addition, in this embodiment, one aspect of the present invention has been described. Or, in other embodiments one aspect of the present invention is described. However, one aspect of the present invention is not limited to these For example, as one aspect of the present invention, an example of applying it to an imaging device has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may not be applied to an imaging device. For example, one aspect of the present invention may be applied to a semiconductor device having another function .

[0096] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments .

[0097] (Embodiment 2) In this embodiment, circuit 91 described in Embodiment 1 will be described.

[0098] Details of the connection form between circuit 91 and various wirings shown in FIG. 1(B) are shown in FIG. 5(A). FIG. 5 (A) shows a circuit including a photodiode 60, a transistor 52, a transistor 54, a transistor 55 and a transistor 56.

[0099] The anode of the photodiode 60 is connected to the wiring 316, and the cathode is connected to the transistor 52 is connected to one of the source or drain. The source or drain of transistor 52 The other is connected to the charge storage part (FD), and the gate is connected to the wiring 312 (TX). The One of the source or drain of transistor 54 is connected to the wiring 314 (GND), and the other of the source or drain is connected to one of the source or drain of transistor 56, and the gate is connected to the charge storage part (FD). The source or drain of transistor 55 One is connected to the charge storage part (FD), and the other of the source or drain is connected to the wiring 317 and the gate is connected to the wiring 311 (RS). The other of the source or drain of transistor 56 is connected to the wiring 315 (OUT), and the gate is connected to the wiring 313 (SE) It should be noted that all the above connections are electrical connections.

[0100] It should be noted that potentials such as GND, VSS, and VDD may be supplied to the wiring 314. Here, potential and voltage are relative. Therefore, the magnitude of the potential of GND is not necessarily 0 volts.

[0101] The photodiode 60 is a light-receiving element and can have a function of generating a current corresponding to the light incident on the pixel circuit. Transistor 52 can have a function of controlling the charge storage in the charge storage part (FD) by the photodiode 60. Transistor 54 can have a function of performing an operation of outputting a signal corresponding to the potential of the charge storage part (FD). Transistor 55 can have a function of performing an operation of resetting the potential of the charge storage part (FD). Transistor 56 can have a function of performing an operation of controlling the selection of the pixel circuit at the time of reading. Transistor 56 can have a function of performing an operation of controlling the selection of the pixel circuit at the time of reading. Transistor 56 can have a function of performing an operation of controlling the selection of the pixel circuit at the time of reading.

[0102] Note that the charge storage unit (FD) is a charge holding node and holds charges that change according to the amount of light received by the photodiode 60.

[0103] Note that the transistor 54 and the transistor 56 can be connected in series between the wiring 315 and the wiring 314. They may be arranged in the order of the wiring 314, the transistor 54, the transistor 56, and the wiring 315, or they may be arranged in the order of the wiring 314, the transistor 56, the transistor 54, and the wiring 315.

[0104] The wiring 311 (RS) can function as a signal line for controlling the transistor 55. The wiring 312 (TX) can function as a signal line for controlling the transistor 52. The wiring 313 (SE) can function as a signal line for controlling the transistor 56. The wiring 314 (GND) can function as a signal line for setting a reference potential (for example, GND). The wiring 315 (OUT) can function as a signal line for reading out the signal output from the transistor 54. The wiring 316 can function as a signal line for outputting charges from the charge storage unit (FD) via the photodiode 60 and is a low potential line in the circuit of FIG. 5(A). Further, the wiring 317 can function as a signal line for resetting the potential of the charge storage unit (FD) and is a high potential line in the circuit of FIG. 5(A).

[0105] Further, the circuit 91 may have the configuration shown in FIG. 5(B). The circuit shown in FIG. 5(B) has the same components as the circuit shown in FIG. 5(A), but the anode of the photodiode 60 is... ​ is electrically connected to one of the source or drain of the transistor 52, and the cathode of the photodiode 60 is different in that it is electrically connected to the wiring 316. In this case, the wiring 316 serves as a signal line for supplying electric charges to the charge storage section (FD) via the photodiode 60 and becomes a high potential line in the circuit of FIG. 5(B). Also, the wiring 317 becomes a low potential line

[0106] Next, the configuration of each element shown in FIGS. 5(A) and 5(B) will be described

[0107] For the photodiode 60, an element in which a pn junction or a pin junction is formed on a silicon substrate can be used

[0108] The transistors 52, 54, 55, and 56 can be formed using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon, but it is preferable to form them using transistors made of an oxide semiconductor. A transistor having a channel formation region formed of an oxide semiconductor has a characteristic of extremely low off-current In particular, if the leakage current of the transistors 52 and 55 connected to the charge storage section (FD) is large, the time during which the charges stored in the charge storage section (FD) can be held becomes insufficient. Therefore, by using transistors made of an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD)

[0109]

[0110] ​​​​​​​​​​​Also, in the transistors 54 and 56, if the leakage current is large, unnecessary charge output occurs in the wiring 314 or the wiring 315. Therefore, it is preferable to use a transistor in which a channel formation region is formed of an oxide semiconductor. Here, an example of the operation of the circuit of FIG. 5(A) will be described using the timing chart shown in FIG. 6(A). In FIG. 6(A), for simplicity of explanation, the potential of each wiring is given as a signal that changes binary. .

[0111] However, since each potential is an analog signal, in reality, it can take various values not limited to binary depending on the situation. Note that the signal 701 shown in the figure corresponds to the potential of the wiring 311 (RS), the signal 702 corresponds to the potential of the wiring 312 (TX), the signal 703 corresponds to the potential of the wiring 313 (SE), the signal 704 corresponds to the potential of the charge storage section (FD), and the signal 705 corresponds to the potential of the wiring 315 (OUT). The potential of the wiring 316 is always "Low", and the potential of the wiring 317 is always "High". At time A, when the potential of the wiring 311 (signal 701) is set to "High" and the potential of the wiring 312 (signal 702) is set to "High", the potential of the charge storage section (FD) (signal 704) is initialized to the potential of the wiring 317 ("High"), and the reset operation is started. The potential of the wiring 315 (signal 705) is pre-charged to "High".

[0112] At time B, when the potential of the wiring 311 (signal 701) is set to "Low", the reset operation ends and the accumulation operation starts. Here, a reverse bias is applied to the photodiode 60. However, since each potential is an analog signal, in reality, it can take various values not limited to binary depending on the situation. Note that the signal 701 shown in the figure corresponds to the potential of the wiring 311 (RS), the signal 702 corresponds to the potential of the wiring 312 (TX), the signal 703 corresponds to the potential of the wiring 313 (SE), the signal 704 corresponds to the potential of the charge storage section (FD), and the signal 705 corresponds to the potential of the wiring 315 (OUT). The potential of the wiring 3 16 is always "Low", and the potential of the wiring 317 is always "High". At time A, when the potential of the wiring 311 (signal 701) is "High" and the potential of the wiring 312 (

[0113] signal 702) is "High", the potential of the charge storage section (FD) (signal 704) is initialized to the potential of the wiring 317 ("High"), and the reset operation starts. The potential of the wiring 3 15 (signal 705) is pre-charged to "High". At time B, when the potential of the wiring 311 (signal 701) is "Low", the reset operation

[0114] ends and the accumulation operation starts. Here, a reverse bias is applied to the photodiode 60. Here, a reverse bias is applied to the photodiode 60. Since a reverse current is applied, the potential (signal 704) of the charge storage section (FD) starts to decrease. Since the reverse current increases when the photodiode 60 is irradiated with light, the rate of decrease in the potential (signal 704) of the charge storage section (FD) changes according to the amount of light irradiated. That is, according to the amount of light irradiated to the photodiode 60, the channel resistance between the source and drain of the transistor 54 changes.

[0115] When the potential (signal 702) of the wiring 312 is set to "Low" at time C, the accumulation operation ends, and the potential (signal 704) of the charge storage section (FD) becomes constant. Here, the potential is determined by the amount of charge generated by the photodiode 60 during the accumulation operation. That is, it changes according to the amount of light irradiated to the photodiode 60. Further, since the transistors 52 and 55 are composed of transistors with extremely low off-current in which the channel formation region is formed in the oxide semiconductor layer, it is possible to keep the potential of the charge storage section (FD) constant until the subsequent selection operation (read operation) is performed.

[0116] Note that when the potential (signal 702) of the wiring 312 is set to "Low", a change may occur in the potential of the charge storage section (FD) due to the parasitic capacitance between the wiring 312 and the charge storage section (FD). If the amount of change in the potential is large, the amount of charge generated by the photodiode 60 during the accumulation operation cannot be accurately obtained. To reduce the amount of change in the potential, measures such as reducing the gate-source (or gate-drain) capacitance of the transistor 52, increasing the gate capacitance of the transistor 54, and providing a holding capacitance in the charge storage section (FD) are taken. ​​​​​​​​​is effective. In this embodiment, it is assumed that the change in the potential can be ignored by these measures. is assumed to be possible.

[0117] When the potential (signal 703) of the wiring 313 is set to "High" at time D, the transistor 56 conducts and the selection operation starts, and the wiring 314 and the wiring 315 conduct via the transistor 54 and the transistor 56. Then, the potential (signal 705) of the wiring 315 decreases. Note that the precharge of the wiring 315 may be completed before time D. Here, the speed at which the potential (signal 705) of the wiring 315 decreases depends on the current between the source and the drain of the transistor 54. That is, it changes according to the amount of light irradiated on the photodiode 60 during the accumulation operation.

[0118] When the potential (signal 703) of the wiring 313 is set to "Low" at time E, the transistor 56 is cut off and the selection operation ends, and the potential (signal 705) of the wiring 315 becomes constant, and its value changes according to the amount of light irradiated on the photodiode 60. Therefore, by acquiring the potential of the wiring 315, the amount of light irradiated on the photodiode 60 during the accumulation operation can be known.

[0119] More specifically, when the light irradiated on the photodiode 60 is strong, the potential of the charge storage section (FD ), that is, the gate voltage of the transistor 54 decreases. Therefore, the current flowing between the source and the drain of the transistor 54 becomes small, and the potential (signal 705) of the wiring 315 decreases slowly. Therefore, a relatively high potential can be read from the wiring 315.

[0120] ​​Conversely, when the light irradiating the photodiode 60 is weak, the potential of the charge storage section (FD), that is, the gate voltage of the transistor 54 becomes high. Therefore, the current flowing between the source and drain of the transistor 54 increases, and the potential of the wiring 315 (signal 705) rapidly decreases. Thus, a relatively low potential can be read from the wiring 315.

[0121] Next, the operation example of the circuit in Fig. 5(B) will be described using the timing chart shown in Fig. 6(B). Note that the potential of the wiring 316 is always "High", and the potential of the wiring 317 is always "Low".

[0122] At time A, when the potential of the wiring 311 (signal 701) is set to "High" and the potential of the wiring 312 (signal 702) is set to "High", the potential of the charge storage section (FD) (signal 704) is initialized to the potential of the wiring 317 ("Low"), and the reset operation is started. Note that the potential of the wiring 315 (signal 705) is pre-charged to "High".

[0123] At time B, when the potential of the wiring 311 (signal 701) is set to "Low", the reset operation ends and the accumulation operation starts. Here, since a reverse bias is applied to the photodiode 60, the potential of the charge storage section (FD) (signal 704) begins to rise due to the reverse current.

[0124] The operations after time C can be referred to the description of the timing chart in Fig. 6(A). At time E, by acquiring the potential of the wiring 315, the amount of light irradiating the photodiode 60 during the accumulation operation can be known.

[0125] ​​​​​​​​​​​Further, the circuit 91 may have the configuration shown in FIGS. 7(A) and (B).

[0126] The circuit shown in FIG. 7(A) is obtained by removing the transistor 55, the wiring 31 6, and the wiring 317 from the configuration of the circuit shown in FIG. 5(A). The wiring 311 (RS) is electrically connected to the anode of the photodiode 60. Other configurations are the same as those of the circuit shown in FIG. 5(A).

[0127] The circuit shown in FIG. 7(B) has the same components as the circuit shown in FIG. 7(A), but differs in that the anode of the photodiode 60 is electrically connected to either the source or the drain of the transistor 52, and the cathode of the photodiode 60 is electrically connected to the wiring 311 (RS).

[0128] Similar to the circuit of FIG. 5(A), the circuit of FIG. 7(A) can be operated according to the timing chart shown in FIG. 6(A).

[0129] At time A, when the potential of the wiring 311 (signal 701) is set to "High" and the potential of the wiring 312 ( signal 702) is set to "High", a forward bias is applied to the photodiode 60, and the potential of the charge storage section (FD) (signal 704) becomes "High". That is, the potential of the charge storage section (FD) is initialized to the potential of the wiring 311 (RS) ("High"), and it enters the reset state. The above is the start of the reset operation. Note that the potential of the wiring 315 (signal 705 ) is pre-charged to "High".

[0130] At time B, when the potential of the wiring 311 (signal 701) is set to "Low", the reset operation ends and the accumulation operation starts. Here, a reverse bias is applied to the photodiode 60. ​​​​​Since it is added, the potential (signal 704) of the charge storage unit (FD) begins to decrease due to the reverse current. begin.

[0131] The operations after time C can be referred to the description of the circuit operation in Fig. 5(A). At time E, by obtaining the potential of the wiring 315, the amount of light irradiated on the photodiode 60 during the accumulation operation can be known. By obtaining the potential of the wiring 315, the amount of light irradiated on the photodiode 60 during the accumulation operation can be known. can be known.

[0132] The circuit in Fig. 7(B) can be operated according to the timing chart shown in Fig. 6(C).

[0133] At time A, when the potential (signal 701) of the wiring 311 is set to "Low" and the potential (signal 702) of the wiring 312 is set to "High", a forward bias is applied to the photodiode 60, and the potential (signal 704) of the charge storage unit (FD) becomes the reset state of "Low". The above is the start of the reset operation. Note that the potential (signal 705) of the wiring 315 is pre-charged to "High". When a forward bias is applied to the photodiode 60, the potential (signal 704) of the charge storage unit (FD) becomes the reset state of "Low". and the potential (signal 704) of the charge storage unit (FD) becomes the reset state of "Low". The above is the start of the reset operation. Note that the potential (signal 705) of the wiring 315 is pre-charged to "High". This is the start of the reset operation. Note that the potential (signal 705) of the wiring 315 is pre-charged to "High". Pre-charge it to "High".

[0134] At time B, when the potential (signal 701) of the wiring 311 is set to "High", the reset operation ends and the accumulation operation starts. Here, since a reverse bias is applied to the photodiode 60, the potential (signal 704) of the charge storage unit (FD) begins to increase due to the reverse current. ends and the accumulation operation starts. Here, since a reverse bias is applied to the photodiode 60, the potential (signal 704) of the charge storage unit (FD) begins to increase due to the reverse current. Since a reverse bias is applied to the photodiode 60, the potential (signal 704) of the charge storage unit (FD) begins to increase due to the reverse current. begin to rise.

[0135] The operations after time C can be referred to the description of the circuit operation in Fig. 5(A). At time E, by obtaining the potential of the wiring 315, the amount of light irradiated on the photodiode 60 during the accumulation operation can be known. By obtaining the potential of the wiring 315, the amount of light irradiated on the photodiode 60 during the accumulation operation can be known. can be known.

[0136] Note that in Fig. 5(A), (B) and Fig. 7(A), (B), the transistor 52 is provided 8A and 8B, an example in which the ion exchange layer 14 is formed is shown, but one embodiment of the present invention is not limited to this. It is also possible to omit transistor 52, as shown in FIG.

[0137] The transistor used in the circuit 91 is, as shown in FIG. A structure in which the transistor 52, the transistor 54, and the transistor 56 are provided with back gates. FIG. 9(A) shows a configuration in which a constant potential is applied to the back gate, and the threshold In addition, the back gate is at the same potential as the front gate in Figure 9(B). This is a configuration in which the voltage is applied to the terminal, and the on-current can be increased. In the above example, the back gate is electrically connected to the wiring 314 (GND). Alternatively, the electrode may be electrically connected to another wiring to which a constant potential is supplied. B) shows an example in which a back gate is provided to a transistor in the circuit shown in FIG. The same configuration is also applicable to the circuits shown in Figs. 5(A), (B), 7(B), 8(A), and (B). In addition, a front gate can be used for the transistors included in one circuit. a structure in which the same potential as that of the back gate is applied to the back gate, a structure in which a constant potential is applied to the back gate, or Alternatively, a circuit configuration may be used in which a back gate is not provided or a configuration in which a back gate is not provided is combined as necessary. stomach.

[0138] In the above-described circuit example, the wiring 315 (OUT) is An integrating circuit as shown in C) may be connected. The S / N ratio can be increased, and weaker light can be detected. This can increase the sensitivity of the device.

[0139] FIG. 10(A) is an integrating circuit using an operational amplifier circuit (also referred to as an OP amplifier). The inverting input terminal of the operational amplifier circuit is connected to wiring 315 (OUT) via a resistor element R. The non-inverting input terminal of the operational amplifier circuit is connected to the ground potential. The output terminal of the operational amplifier circuit is connected to the inverting input terminal of the operational amplifier circuit via a capacitor element C. The inverting input terminal of the operational amplifier circuit is connected to wiring 315 (OUT) via a resistor element R. The non-inverting input terminal of the operational amplifier circuit is connected to the ground potential. The output terminal of the operational amplifier circuit is connected to the inverting input terminal of the operational amplifier circuit via a capacitor element C.

[0140] FIG. 10(B) is an integrating circuit using an operational amplifier circuit having a configuration different from that of FIG. 10(A). The inverting input terminal of the operational amplifier circuit is connected to wiring 315 (OUT) via a resistor element R and a capacitor element C1. The non-inverting input terminal of the operational amplifier circuit is connected to the ground potential. The output terminal of the operational amplifier circuit is connected to the inverting input terminal of the operational amplifier circuit via a capacitor element C2. The inverting input terminal of the operational amplifier circuit is connected to wiring 315 (OUT) via a resistor element R and a capacitor element C1. The non-inverting input terminal of the operational amplifier circuit is connected to the ground potential. The output terminal of the operational amplifier circuit is connected to the inverting input terminal of the operational amplifier circuit via a capacitor element C2.

[0141] FIG. 10(C) is an integrating circuit using an operational amplifier circuit having a configuration different from those of FIGS. 10(A) and 10(B). The non-inverting input terminal of the operational amplifier circuit is connected to wiring 315 (OUT) via a resistor element R. The output terminal of the operational amplifier circuit is connected to the inverting input terminal of the operational amplifier circuit. Note that the resistor element R and the capacitor element C constitute a CR integrating circuit. Also, the operational amplifier circuit constitutes a unity gain buffer. The non-inverting input terminal of the operational amplifier circuit is connected to wiring 315 (OUT) via a resistor element R. The output terminal of the operational amplifier circuit is connected to the inverting input terminal of the operational amplifier circuit. Note that the resistor element R and the capacitor element C constitute a CR integrating circuit. Also, the operational amplifier circuit constitutes a unity gain buffer.

[0142] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0143] (Embodiment 3) In this embodiment, a transistor for initializing the potential of the charge storage unit (FD), a transistor for outputting a signal according to the potential of the charge storage unit (FD), and each wiring (signal line) are provided between pixels. A transistor for outputting a signal according to the potential of the charge storage unit (FD), and each wiring (signal line) are provided between pixels. ​​​​​The circuit configuration in the case of sharing among the circuits 91 will be described.

[0144] The pixel circuit shown in FIG. 11 has, for each pixel, one transistor 52 (functioning as a transfer transistor), one transistor 54 (functioning as an amplification transistor), one transistor 55 (functioning as a reset transistor), one transistor 56 (functioning as a selection transistor), and one photodiode 60, similar to the circuit shown in FIG. 5(A). Also, wiring 311 (functioning as a signal line for controlling transistor 55), wiring 312 (functioning as a signal line for controlling transistor 52), wiring 313 (functioning as a signal line for controlling transistor 56), wiring 314 (functioning as a high potential line), wiring 315 (functioning as a signal line for reading out the signal output from transistor 54), and wiring 316 (functioning as a reference potential line (GND)) are electrically connected to the pixel circuit.

[0145] In the circuit shown in FIG. 5(A), an example was shown with wiring 314 as GND and wiring 317 as the high potential line. However, in this pixel circuit, wiring 314 is used as the high potential line (e.g., VDD), and by connecting the other of the source or drain of transistor 56 to wiring 314, wiring 317 is omitted. Also, wiring 315 (OUT) is reset to a low potential.

[0146] Between the pixel circuits of the first line and the pixel circuits of the second line, as shown below, wiring 314, wiring 315, and wiring 316 can be shared, and depending on the operation method, wiring 311 can also be shared.

[0147] FIG. 12 shows, for four pixels of the first to fourth lines adjacent in the vertical direction, transistor 5 ​​​​​​​​​​​​4. Vertical 4-pixel sharing that doubles as transistor 55, transistor 56, and wiring 311 The structure is shown. By reducing transistors and wiring, miniaturization due to reduced pixel area and yield can be improved. In each of four vertically adjacent pixels, either the source or drain of transistor 52, either the source or drain of transistor 55, and the gate of transistor 54 are electrically connected to the charge storage part (FD). By sequentially operating transistor 52 of each pixel and repeating the accumulation operation and the readout operation, data can be acquired from all pixels.

[0148] Figure 13 shows a vertical-horizontal 4-pixel sharing structure that doubles as transistor 54, transistor 55, transistor 56, wiring 313, and wiring 311 for four pixels adjacent in the horizontal and vertical directions. Similar to the vertical 4-pixel sharing type, by reducing transistors and wiring, miniaturization due to reduced pixel area and yield can be improved. In four pixels adjacent in the horizontal and vertical directions, either the source or drain of transistor 52, either the source or drain of transistor 55, and the gate of transistor 54 are electrically connected to the charge storage part (FD). By sequentially operating transistor 52 of each pixel and repeating the accumulation operation and the readout operation, data can be acquired from all pixels.

[0149] Figure 14 shows a structure that doubles as transistor 54, transistor 55, transistor 56, wiring 311, and wiring 312 and 314 for four pixels adjacent in the horizontal and vertical directions. It is a circuit that further shares wiring 312 in the above-described vertical-horizontal 4-pixel sharing type. ​​ It is. Four adjacent pixels in the horizontal and vertical directions (the first row has two adjacent pixels in the horizontal direction ), the other of the source or drain of the transistor 52, the source of the transistor 55 or one of the drains, and the gate of the transistor 54 are electrically connected to the charge storage section (FD). Also, in this circuit configuration, two transfer transistors located in the vertical direction (transistor 52) share the wiring 312, so that there are transistors that can move simultaneously not only in the horizontal direction but also in the vertical direction direction.

[0150] Note that although it is different from the form of sharing the transistors and signal lines described above, it is also possible to adopt a configuration of a pixel circuit having a plurality of photodiodes .

[0151] For example, as in the pixel circuit shown in FIG. 15(A), between the wiring 316 and one of the source or drain of the transistor 52 , photodiodes 60a, 60b, 60c and transistors 58a, 58b, 58c, etc. are provided. The transistors 58a, 58b, 58c are respectively used as switches for selecting the photodiodes 60a, 60b, 60c connected thereto . Note that in FIG. 15, the number of combinations of photodiodes and transistors having the function as switches is exemplified as three, but it is not limited thereto. For example , as shown in FIG. 15(B), it can also be configured with two. Of course, it can also be four or more . , as shown in FIG. 15(B), it can also be configured with two. Of course, it can also be four or more .

[0152] As an example, for the photodiodes 60a, 60b, 60c, those having different characteristics of sensitivity to illuminance can be used respectively, and for each environment from low illuminance to high illuminance , Those suitable for imaging are selected. For example, for a high illuminance photodiode, one combined with a dimming filter can be used so that the output with respect to the illuminance has linearity. Note that a plurality of photodiodes may be selected and operated.

[0153] Also, for the photodiodes 60a, 60b, and 60c, those having different sensitivities with respect to wavelengths can be used, and those suitable for imaging at respective wavelengths from ultraviolet to far infrared are selected. For example, by combining a filter that transmits the wavelength range to be detected and a photodiode, imaging using ultraviolet light, imaging using visible light, imaging using infrared light, etc. can be switched and performed.

[0154] Also, for the photodiodes included in the pixel circuit, a plurality of those having different light receiving areas may be used. In a configuration having two photodiodes, for example, those having different ratios such as 1:10 or 1:100 in the light receiving area can be used. In a photodiode, the current value output may saturate due to the influence of the series resistance, etc. In this case, from Ohm's law, the smaller the current value, the better the linearity with respect to the illuminance. Therefore, usually, imaging is performed using a photodiode with a large light receiving area so as to have high sensitivity, and in an environment with high illuminance, imaging is performed using a photodiode with a small light receiving area. By doing so, an imaging device with high sensitivity and a wide dynamic range can be obtained.

[0155] Note that in the configuration of a pixel having photodiodes with different light receiving areas, as shown in FIG. 15(C), one pixel 90 has photodiodes 60a and 60b with different areas. ​​​​​​​​​​​​​In addition to the configuration described above, as shown in FIG. 15(D), photodiodes 6 0a and 60b with different areas may be alternately arranged for each pixel 90.

[0156] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0157] (Embodiment 4) In this embodiment, an example of a method for driving a pixel circuit will be described.

[0158] As described in Embodiment 2, the operation of the pixel circuit is a repetition of a reset operation, an accumulation operation, and a selection operation. As an imaging method for controlling the entire pixel matrix, a global shutter method and a rolling shutter method are known.

[0159] FIG. 16(A) is a timing chart in the global shutter method. Note that FIG. 16(A) shows an imaging device having a plurality of pixel circuits in a matrix form, and the circuit of FIG. 5(A) is provided in the pixel circuit. Taking this as an example, the operation of the pixel circuits from the first row to the nth row (n is a natural number of 3 or more) will be described. The following operation description can also be applied to the circuits shown in FIGS. 5(B), 7(A), (B), and FIGS. 8(A), (B).

[0160] In FIG. 16(A), signals 501, 502, and 503 are signals input to wiring 311(RS) connected to each pixel circuit in the first row, the second row, and the nth row. Also, signals 504, 505, and 506 are signals input to wiring 312(TX) connected to each pixel circuit in the first row, the second row, and the nth row. Further, signals 507 and 508 , the signal 509 is a signal input to the wiring 313 ( SE) connected to each pixel circuit in the first row, second row, and nth row.

[0161] Also, the period 510 is the period required for one imaging. Also, the period 511 is the period during which the pixel circuits in each row are simultaneously performing a reset operation. Also, the period 520 is the period during which the pixel circuits in each row are simultaneously performing an accumulation operation. Note that the selection operation is sequentially performed by the pixel circuits in each row. As an example, the period 531 is the period during which the pixel circuit in the first row is performing a selection operation. Thus, in the global shutter method, after the reset operation is performed almost simultaneously by all the pixel circuits, the accumulation operation is performed almost simultaneously by all the pixel circuits, and the readout operation is sequentially performed for each row. That is, in the global shutter method, since the accumulation operation is performed almost simultaneously in all the pixel circuits,

[0162] the simultaneity of imaging in the pixel circuits of each row is ensured. Therefore, even if the subject is a moving object, an image with little distortion can be obtained.

[0163] On the other hand, FIG. 16(B) is a timing chart when the rolling shutter method is used. Note that the signals 501 to 509 can be referred to for the description of FIG. 16(A). The period 6 10 is the period required for one imaging. The periods 611, 612, and 613 are respectively the reset periods for the first row, second row, and nth row. Also, the periods 621, 622 and 623 are respectively the accumulation operation periods for the first row, second row, and nth row. Also, the period 631 is the period during which the pixel circuit in the first row is performing a selection operation. Thus, in the rolling shutter method, the accumulation operation is not performed simultaneously in all the pixel circuits, but is sequentially performed for each row.​ Therefore, the simultaneity of imaging in the pixel circuits of each row is not ensured. Thus, in the first row and the last row, since the imaging timings are different, when a moving object is the subject, an image with a large distortion will be obtained.

[0164] In order to realize the global shutter method, it is necessary to keep the potential of the charge storage section (FD) for a long time until the signal readout from each pixel is sequentially completed. The long-time holding of the potential of the charge storage section (FD) can be realized by using a transistor with an extremely low off-current, such as transistor 52, in which the channel formation region is formed of an oxide semiconductor. On the other hand, when a transistor in which the channel formation region is formed of silicon or the like is applied to transistor 52 or the like, since the off-current is high, the potential of the charge storage section (FD) cannot be held for a long time, and it becomes difficult to use the global shutter method. As described above, by using a transistor in which the channel formation region in the pixel circuit is formed of an oxide semiconductor, the global shutter method can be easily realized. The global shutter method can be easily realized. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0165] As described above, by using a transistor in which the channel formation region in the pixel circuit is formed of an oxide semiconductor, the global shutter method can be easily realized.

[0166] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0167] (Embodiment 5) In this embodiment, a transistor having an oxide semiconductor that can be used in one aspect of the present invention will be described with reference to the drawings. Note that in the drawings of this embodiment, for clarity, some elements are enlarged, reduced, or omitted. For clarity, some elements are enlarged, reduced, or omitted.

[0168] Figs. 17(A) and (B) are a top view and a cross-sectional view of a transistor 101 according to one aspect of the present invention. Yes. The cross-section in the direction of the dashed line B1 - B2 shown in Fig. 17(A) corresponds to Fig. 17(B). Also, the cross-section in the direction of the dashed line B3 - B4 shown in Fig. 17(A) corresponds to Fig. 23(A). Also, the direction of the dashed line B1 - B2 may be referred to as the channel length direction, and the direction of the dashed line B3 - B4 may be referred to as the channel width direction.

[0169] The transistor 101 has an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 140 and a conductive layer 150 electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. Also, an insulating layer 190 (planarization film) etc. in contact with the insulating layer 180 may be provided as necessary.

[0170] Here, the conductive layer 140 can function as a source electrode layer, the conductive layer 150 can function as a drain electrode layer, the insulating layer 160 can function as a gate insulating film, and the conductive layer 170 can function as a gate electrode layer, respectively.

[0171] Also, the region 231 shown in Fig. 17(B) can function as a source region, the region 232 can function as a drain region, and the region 233 can function as a channel formation region. The regions 231 and 232 are in contact with the conductive layer 140 and the conductive layer 150, respectively. If a conductive material that easily binds with oxygen is used for the conductive layer 140 and the conductive layer 150, the regions 231 and 232 can be made to have a lower resistance.

[0172] ​​​​​​​​​​​​Specifically, when the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150, oxygen deficiency occurs in the oxide semiconductor layer 130, and due to the interaction between the oxygen deficiency and hydrogen remaining in or diffusing from the outside into the oxide semiconductor layer 130, regions 231 and 232 become n-type with low resistance.

[0173] Note that the functions of the "source" and "drain" of a transistor may be interchanged when transistors with different polarities are employed or when the direction of current changes in circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable. Also, the "electrode layer" can be rephrased as "wiring".

[0174] Further, although an example in which the conductive layer 170 is formed of two layers, i.e., the conductive layer 171 and the conductive layer 172, is illustrated, it may be a single layer or a laminate of three or more layers. This configuration can also be applied to other transistors described in this embodiment mode.

[0175] Also, although an example in which the conductive layer 140 and the conductive layer 150 are formed as single layers is illustrated, they may be a laminate of two or more layers. This configuration can also be applied to other transistors described in this embodiment mode.

[0176] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 18(A) and 18(B). FIG. 18(A) is a top view of the transistor 102, and the cross section in the one-dot chain line C1-C2 direction shown in FIG. 18(A) corresponds to FIG. 18(B). Also, the cross section in the one-dot chain line C3-C4 direction shown in FIG. 18(A) corresponds to FIG. 23(B). Also, the one-dot chain line C1-C2 direction is the channel ​​​​​​The direction of the dashed dotted line C3-C4 may be referred to as the channel length direction, and the direction of the dashed dotted line C3-C4 may be referred to as the channel width direction.

[0177] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0178] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. On the other hand, since no offset region is formed in the oxide semiconductor layer 130, a transistor with a high on-current is formed. It is easy to form a transistor.

[0179] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 19A is a top view of the transistor 103. The cross section in the 1-D2 direction corresponds to FIG. 19(B). The cross section in the -D4 direction corresponds to FIG. 23(A). The direction of the dashed dotted line D3-D4 may be referred to as the channel length direction, and the direction of the dashed dotted line D3-D4 may be referred to as the channel width direction.

[0180] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer 190 (planarizing film) in contact with 150 may also be provided.

[0181] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0182] In addition, a region 231 shown in FIG. 19B is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are insulators. If an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0183] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, a silicon nitride film or an aluminum nitride film can be used.

[0184] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 20A is a top view of the transistor 104. The cross-section in the 1-E2 direction corresponds to Fig. 20(B). Also, the dashed-dotted line E3 shown in Fig. 20(A) - The cross-section in the E4 direction corresponds to Fig. 23(A). Also, the dashed-dotted line in the E1-E2 direction is sometimes referred to as the channel length direction, and the dashed-dotted line in the E3-E4 direction is sometimes referred to as the channel width direction.

[0185] The transistor 104 has the same configuration as the transistor 103, except that the conductive layer 140 and the conductive layer 150 are in contact with the end of the oxide semiconductor layer 130 so as to cover it.

[0186] Also, the regions 331 and 334 shown in Fig. 20(B) can function as source regions, the regions 332 and 335 can function as drain regions, and the region 333 can function as a channel formation region. The regions 331 and 332 can be made to have low resistance in the same manner as the regions 231 and 23 2 in the transistor 101. Also, the regions 334 and 335 can be made to have low resistance in the same manner as the regions 231 and 232 in the transistor 103. Note that when the lengths of the regions 334 and 335 in the channel length direction are 100 nm or less, preferably 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field, so it is also possible to adopt a configuration in which the above-described low resistance is not achieved.

[0187] The transistors 103 and 104 have a self-aligned structure in which the conductive layer 170 does not overlap with the conductive layer 140 and the conductive layer 150. The self-aligned transistor has an extremely small parasitic capacitance between the gate electrode layer and the source electrode layer and the drain electrode layer, so it is suitable for high-speed operation applications.

[0188] ​Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 21A is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 21(B). Also, the dashed line F3 shown in FIG. The cross section in the -F4 direction corresponds to FIG. 23(A). The dashed line F1-F2 direction corresponds to the channel length The direction indicated by the dashed dotted line F3-F4 may be referred to as the channel width direction.

[0189] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer 190 (planarizing film) may be provided.

[0190] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0191] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and has a conductive layer 142 and a conductive layer 152 that are electrically connected to the conductive layer 151 respectively Except for this point, it has the same configuration as the transistor 101. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can act as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 152) can act as a drain electrode layer.

[0192] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 22(A) and (B). FIG. 22(A) is a top view of the transistor 106, and the cross-section in the direction of the dashed-dotted line G 1-G2 shown in FIG. 22(A) corresponds to FIG. 22(B). Also, the cross-section in the direction of the dashed-dotted line G3 -G4 shown in FIG. 22(A) corresponds to FIG. 23(A). Also, the direction of the dashed-dotted line G1-G2 may be referred to as the channel length direction, and the direction of the dashed-dotted line G3-G4 may be referred to as the channel width direction.

[0193] The transistor 106 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 141 and a conductive layer 151 that are electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the insulating layer 120, the oxide semiconductor layer 130, the conductive layer 141, the conductive layer 151, the insulating layer 160, and the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175, and has a conductive layer 142 and a conductive layer 152 that are electrically connected to the conductive layer 141 and the conductive layer 151 respectively through openings provided in the insulating layer 175 and the insulating layer 180. Also, if necessary, it may have an insulating layer 190 (a planarization film) in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152.

[0194] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and not in contact with the side surfaces in a non-contact configuration.

[0195] The transistor 106 has the same configuration as the transistor 103, except that it has the conductive layer 141 and the conductive layer 151. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can act as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 15 2) can act as a drain electrode layer. In the configurations of the transistor 105 and the transistor 106, since the conductive layer 140 and the conductive layer 1 50 are not in contact with the insulating layer 120, oxygen in the insulating layer 120 is less likely to be taken away by the conductive layer 140 and the conductive layer 150, and the supply of oxygen from the insulating layer 120 into the oxide semiconductor layer 130 can be facilitated.

[0196] In addition, in the regions 231 and 232 in the transistor 103, and the regions 334 and 335 in the transistor 104 and the transistor 106, impurities for forming oxygen vacancies and increasing the conductivity may be added. As impurities for forming oxygen vacancies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium zinc, and carbon can be used. As a method for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used.

[0197]

[0198] When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen vacancies are formed. Due to the interaction between the oxygen vacancies contained in the oxide semiconductor layer and hydrogen remaining in or later added to the oxide semiconductor layer, the conductivity of the oxide semiconductor layer can be increased. When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of impurity elements, hydrogen enters the oxygen vacancy sites and donor levels are formed in the vicinity of the conduction band. As a result, an oxide conductor can be formed. Here, the oxide semiconductor that has been made conductive is referred to as an oxide conductor. The oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide or substantially coincide. For this reason, the contact between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer is an ohmic contact, and the contact resistance between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer can be reduced. In addition, the transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as shown in the cross-sectional views in the channel length direction shown in FIGS. 24(A), (B), (C) and FIGS. 25(A), (B), (C), and the cross-sectional views in the channel width direction shown in FIGS. 26(A), (B). By using the conductive layer 173 as a second gate electrode layer (back gate), further increase in the on-current and control of the threshold voltage can be achieved.

[0199] When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen vacancies are formed. Due to the interaction between the oxygen vacancies contained in the oxide semiconductor layer and hydrogen remaining in or later added to the oxide semiconductor layer, the conductivity of the oxide semiconductor layer can be increased. When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of impurity elements, hydrogen enters the oxygen vacancy sites and donor levels are formed in the vicinity of the conduction band. As a result, an oxide conductor can be formed. Here, the oxide semiconductor that has been made conductive is referred to as an oxide conductor. The oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide or substantially coincide. For this reason, the contact between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer is an ohmic contact, and the contact resistance between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer can be reduced. In addition, the transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as shown in the cross-sectional views in the channel length direction shown in FIGS. 24(A), (B), (C) and FIGS. 25(A), (B), (C), and the cross-sectional views in the channel width direction shown in FIGS. 26(A), (B). By using the conductive layer 173 as a second gate electrode layer (back gate), further increase in the on-current and control of the threshold voltage can be achieved.

[0200] The oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide or substantially coincide. For this reason, the contact between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer is an ohmic contact, and the contact resistance between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer can be reduced. In addition, the transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as shown in the cross-sectional views in the channel length direction shown in FIGS. 24(A), (B), (C) and FIGS. 25(A), (B), (C), and the cross-sectional views in the channel width direction shown in FIGS. 26(A), (B). By using the conductive layer 173 as a second gate electrode layer (back gate), further increase in the on-current and control of the threshold voltage can be achieved. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen vacancies are formed. Due to the interaction between the oxygen vacancies contained in the oxide semiconductor layer and hydrogen remaining in or later added to the oxide semiconductor layer, the conductivity of the oxide semiconductor layer can be increased. When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of impurity elements, hydrogen enters the oxygen vacancy sites and donor levels are formed in the vicinity of the conduction band. As a result, an oxide conductor can be formed. Here, the oxide semiconductor that has been made conductive is referred to as an oxide conductor.

[0201] In addition, the transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as shown in the cross-sectional views in the channel length direction shown in FIGS. 24(A), (B), (C) and FIGS. 25(A), (B), (C), and the cross-sectional views in the channel width direction shown in FIGS. 26(A), (B). By using the conductive layer 173 as a second gate electrode layer (back gate), further increase in the on-current and control of the threshold voltage can be achieved. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen vacancies are formed. Due to the interaction between the oxygen vacancies contained in the oxide semiconductor layer and hydrogen remaining in or later added to the oxide semiconductor layer, the conductivity of the oxide semiconductor layer can be increased. When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of impurity elements, hydrogen enters the oxygen vacancy sites and donor levels are formed in the vicinity of the conduction band. As a result, an oxide conductor can be formed. Here, the oxide semiconductor that has been made conductive is referred to as an oxide conductor. The oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide or substantially coincide. For this reason, the contact between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer is an ohmic contact, and the contact resistance between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer can be reduced. In addition, the transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as shown in the cross-sectional views in the channel length direction shown in FIGS. 24(A), (B), (C) and FIGS. 25(A), (B), (C), and the cross-sectional views in the channel width direction shown in FIGS. 26(A), (B). By using the conductive layer 173 as a second gate electrode layer (back gate), further increase in the on-current and control of the threshold voltage can be achieved. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen vacancies are formed. Due to the interaction between the oxygen vacancies contained in the oxide semiconductor layer and hydrogen remaining in or later added to the oxide semiconductor layer, the conductivity of the oxide semiconductor layer can be increased. In the figure, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Further, the width of the conductive layer 173 may be shorter than that of the conductive layer 170.

[0202] To increase the on-current, for example, the conductive layer 170 and the conductive layer 173 may be set to the same potential and driven as a double gate transistor. To control the threshold voltage, a fixed potential different from that of the conductive layer 170 may be supplied to the conductive layer 173. To set the conductive layer 170 and the conductive layer 1 73 to the same potential, for example, as shown in FIG. 26(B), the conductive layer 170 and the conductive layer 1 73 may be electrically connected via a contact hole.

[0203] In the transistors 101 to 106 in FIGS. 17 to 22, an example in which the oxide semiconductor layer 130 is a single layer is illustrated, but the oxide semiconductor layer 130 may be laminated. The oxide semiconductor layers 130 of the transistors 101 to 106 can be replaced with the oxide semiconductor layer 130 shown in FIG. 27 or FIG. 28.

[0204] FIGS. 27(A), (B), and (C) are a top view and a cross-sectional view of the oxide semiconductor layer 130 having a two-layer structure. The cross-section in the direction of the dashed-dotted line A1 - A2 shown in FIG. 27(A) corresponds to FIG. 27(B). Also, the cross-section in the direction of the dashed-dotted line A3 - A4 shown in FIG. 27(A) corresponds to FIG. 27(C).

[0205] FIGS. 28(A), (B), and (C) are a top view and a cross-sectional view of the oxide semiconductor layer 130 having a three-layer structure. The cross-section in the direction of the dashed-dotted line A1 - A2 shown in FIG. 28(A) corresponds to FIG. 28(B). Also, the cross-section in the direction of the dashed-dotted line A3 - A4 shown in FIG. 28(A) corresponds to FIG. 28(C). ​​​​​​​​​​

[0206] For the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, oxide semiconductor layers having different compositions or the like can be used respectively.

[0207] Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 29(A) and (B). FIG. 29(A) is a top view of the transistor 107, and a cross section in the dash-dotted line H1-H2 direction shown in FIG. 29(A) corresponds to FIG. 29(B). Also, a cross section in the dash-dotted line H3-H4 direction shown in FIG. 29(A) corresponds to FIG. 35(A). Further, the dash-dotted line H1-H2 direction may be referred to as the channel length direction, and the dash-dotted line H3-H4 direction may be referred to as the channel width direction.

[0208] The transistor 107 includes an insulating layer 120 in contact with the substrate 115, a stack including an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, conductive layers 140 and 150 electrically connected to the stack, an oxide semiconductor layer 130c in contact with the stack, the conductive layers 140 and 150, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the conductive layers 140, 150, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. Further, an insulating layer 190 (planarization film) or the like in contact with the insulating layer 180 may be provided as necessary.

[0209] The transistor 107 is characterized in that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in regions 231 and 232, and The oxide semiconductor layer 130 is three-layered (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c), and has a configuration similar to that of the transistor 101 except that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layer 140 and the conductive layer 150 and the insulating layer 160. Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 30(A) and (B). FIG. 30(A) is a top view of the transistor 108, and a cross section in the one-dot chain line I1-I2 direction shown in FIG. 30(A) corresponds to FIG. 30(B). Further, a cross section in the one-dot chain line I3-I4 direction shown in FIG. 30(A) corresponds to FIG. 35(B). Also, the one-dot chain line I1-I2 direction may be referred to as the channel length direction, and the one-dot chain line I3-I4 direction may be referred to as the channel width direction. The transistor 108 is different from the transistor 107 in that the ends of the insulating layer 160 and the oxide semiconductor layer 130c do not coincide with the ends of the conductive layer 170. Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 31(A) and (B). FIG. 31(A) is a top view of the transistor 109, and a cross section in the one-dot chain line J1-J2 direction shown in FIG. 31(A) corresponds to FIG. 31(B). Further, a cross section in the one-dot chain line J3-J4 direction shown in FIG. 31(A) corresponds to FIG. 35(A). Also, the one-dot chain line J1-J2 direction may be referred to as the channel length direction, and the one-dot chain line J3-J4 direction may be referred to as the channel width direction.

[0210] The transistor 109 includes an insulating layer 120 in contact with the substrate 115, a stack including an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, and an acid in contact with the stack. FIG. 30(A) is a top view of the transistor 108, and a cross section in the one-dot chain line I1-I2 direction shown in FIG. 30(A) corresponds to FIG. 30(B). Further, a cross section in the one-dot chain line I3-I4 direction shown in FIG. 30(A) corresponds to FIG. 35(B). Also, the one-dot chain line I1-I2 direction may be referred to as the channel length direction, and the one-dot chain line I3-I4 direction may be referred to as the channel width direction.

[0211] The transistor 108 is different from the transistor 107 in that the ends of the insulating layer 160 and the oxide semiconductor layer 130c do not coincide with the ends of the conductive layer 170.

[0212] Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 31(A) and (B). FIG. 31(A) is a top view of the transistor 109, and a cross section in the one-dot chain line J1-J2 direction shown in FIG. 31(A) corresponds to FIG. 31(B). Further, a cross section in the one-dot chain line J3-J4 direction shown in FIG. 31(A) corresponds to FIG. 35(A). Also, the one-dot chain line J1-J2 direction may be referred to as the channel length direction, and the one-dot chain line J3-J4 direction may be referred to as the channel width direction.

[0213] The transistor 109 includes an insulating layer 120 in contact with the substrate 115, a stack including an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, and an acid in contact with the stack. ​​​​ The oxide semiconductor layer 130c, the insulating layer 160 in contact with the oxide semiconductor layer 130c, the conductive layer 170 in contact with the insulating layer 16 0, the insulating layer 175 covering the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, the insulating layer 180 in contact with the insulating layer 175, and the conductive layer 14 that is electrically connected to the stack through an opening provided in the insulating layer 175 and the insulating layer 180 has a conductive layer 14 0 and a conductive layer 150. Further, if necessary, it may have an insulating layer 180, a conductive layer 140, and an insulating layer 190 (planarization film) in contact with the conductive layer 150, etc.

[0214] The transistor 109 has the same configuration as the transistor 103 except that the oxide semiconductor layer 130 is two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, and the oxide semiconductor layer 130 is three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233. point.

[0215] Further, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 32(A) and (B). FIG. 32(A) is a top view of the transistor 110, and the cross-section in the direction of the dashed-dotted line K 1-K2 shown in FIG. 32(A) corresponds to FIG. 32(B). Also, the cross-section in the direction of the dashed-dotted line K3 -K4 shown in FIG. 32(A) corresponds to FIG. 35(A). Further, the direction of the dashed-dotted line K1-K2 may be referred to as the channel length direction, and the direction of the dashed-dotted line K3-K4 may be referred to as the channel width direction.

[0216] The transistor 110 has the same configuration as the transistor 103 except that the oxide semiconductor layer 130 is two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 331 and 332, and the oxide semiconductor layer 130 is three The transistor has the same configuration as transistor 104, except that the oxide semiconductor layer 130 has three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c).

[0217] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 33(A) and (B). FIG. 33(A) is a top view of transistor 111, and the cross-section in the dash-dotted line L1-L2 direction shown in FIG. 33(A) corresponds to FIG. 33(B). Also, the cross-section in the dash-dotted line L3-L4 direction shown in FIG. 33(A) corresponds to FIG. 35(A). Further, the dash-dotted line L1-L2 direction may be referred to as the channel length direction, and the dash-dotted line L3-L4 direction may be referred to as the channel width direction.

[0218] Transistor 111 includes an insulating layer 120 in contact with substrate 115, a stack composed of an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with insulating layer 120, conductive layers 141 and 151 electrically connected to the stack, an oxide semiconductor layer 130c in contact with the stack, conductive layers 141, 151, and oxide semiconductor layer 130c, an insulating layer 160 in contact with oxide semiconductor layer 130c, a conductive layer 170 in contact with insulating layer 160, an insulating layer 175 in contact with the stack, conductive layers 141, 151, oxide semiconductor layer 130c, insulating layer 160, and conductive layer 170, an insulating layer 180 in contact with insulating layer 175, and conductive layers 142 and 152 that are electrically connected to conductive layers 141 and 151 respectively through openings provided in insulating layer 175 and insulating layer 180. Further, if necessary, it may have an insulating layer 190 (planarization film) in contact with insulating layer 180, conductive layer 142, and conductive layer 152, etc.

[0219] In transistor 111, the oxide semiconductor layer 130 is two-layered in regions 231 and 232​​​​​​​​​​​​​ in that it is a layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b), in region 233 in that the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c), and in that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layer 141 and the conductive layer 151 and the insulating layer 160 except for these points, it has the same configuration as the transistor 105.

[0220] Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 34(A) and (B). FIG. 34(A) is a top view of the transistor 112, and the cross-section in the direction of the dashed line M1 - M2 shown in FIG. 34(A) corresponds to FIG. 34(B). Also, the cross-section in the direction of the dashed line M3 - M4 shown in FIG. 34(A) corresponds to FIG. 35(A). Also, the direction of the dashed line M1 - M2 may be referred to as the channel length direction, and the direction of the dashed line M3 - M4 may be referred to as the channel width direction.

[0221] The transistor 112 has the same configuration as the transistor 106, except that in regions 331, 332, 334, and 335, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b), and in region 333, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c).

[0222] Also, the transistor according to one aspect of the present invention may have a cross-sectional view in the channel length direction shown in FIGS. 36(A), (B), (C) and FIGS. 37(A), (B), (C), and a cross-sectional view in the channel width direction shown in FIGS. 38(A), (B), such that a conductive layer is provided between the oxide semiconductor layer 130 and the substrate 115. It may include a layer 173. By using this conductive layer as a second gate electrode layer (back gate), it is possible to further increase the on-current and control the threshold voltage. Note that in the cross-sectional views shown in FIGS. 36(A), (B), (C) and FIGS. 37(A), (B), (C), the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Further, the width of the conductive layer 173 may be shorter than that of the conductive layer 170.

[0223] Also, the conductive layer 140 (source electrode layer) and the conductive layer 150 (drain electrode layer) in the transistor of one aspect of the present invention may have a configuration as shown in the top views of FIGS. 39(A) and (B). Note that in FIGS. 39(A) and (B), only the oxide semiconductor layer 130, the conductive layer 140 and the conductive layer 150 are illustrated. As shown in FIG. 39(A), the widths (W ) of the conductive layer 140 and the conductive layer 150 may be formed longer than the width (W SD ) of the oxide semiconductor layer. Also, as shown in FIG. 39(B), W OS ) may be formed shorter than W . By setting W SD ≧W OS (W is less than or equal to W OS ), the gate electric field is likely to be applied to the entire oxide semiconductor layer 130, SD and the electrical characteristics of the transistor can be improved. SD is W OS ), the gate electric field is likely to be applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor can be improved.

[0224] In the transistor (transistors 101 to 112) of one aspect of the present invention, in any configuration, the conductive layer 170, which is the gate electrode layer, electrically surrounds the channel width direction of the oxide semiconductor layer 130 via the insulating layer 160, which is the gate insulating film, and the on-current is can be enhanced. Such a transistor structure is called a surrounded channel (s-channel) structure.

[0225] In addition, in a transistor having the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, as well as in a transistor having the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, by appropriately selecting two or three materials constituting the oxide semiconductor layer 130, current can be made to flow through the oxide semiconductor layer 130b. When current flows through the oxide semiconductor layer 130b, it is less affected by interface scattering and a high on-current can be obtained. Note that increasing the thickness of the oxide semiconductor layer 130b can improve the on-current. For example, the film thickness of the oxide semiconductor layer 130b may be set to 100 nm to 200 nm. By using a transistor having the above configuration, good electrical characteristics can be imparted to the semiconductor device. In the present specification, the channel length refers to, for example, in the top view of the transistor, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by a single value. Therefore, in the present specification, the channel length is any one in the region where the channel is formed. When current flows through the oxide semiconductor layer 130b, it is less affected by interface scattering and a high on-current can be obtained. Note that increasing the thickness of the oxide semiconductor layer 130b can improve the on-current. For example, the film thickness of the oxide semiconductor layer 130b may be set to 100 nm to 200 nm. This is also good.

[0226] By using a transistor having the above configuration, good electrical characteristics can be imparted to the semiconductor device. This is possible.

[0227] In the present specification, the channel length refers to, for example, in the top view of the transistor, the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap in the region, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by a single value. Therefore, in the present specification, the channel length is any one in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by a single value. Therefore, in the present specification, the channel length is any one in the region where the channel is formed. It is taken as a value, maximum value, minimum value, or average value.

[0228] Also, the channel width is, for example, the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, maximum value, minimum value, or average value in the region where the channel is formed. Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may differ from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may become non-negligible. For example, in a fine transistor where the gate electrode covers the side surface of the semiconductor, the ratio of the channel region formed on the upper surface of the semiconductor may be smaller than the ratio of the channel region formed on the side surface of the semiconductor. In such a case, the effective channel width is larger than the apparent channel width. In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design values, the shape of the semiconductor needs to be known.

[0229] Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may differ from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may become non-negligible. For example, in a fine transistor where the gate electrode covers the side surface of the semiconductor, the ratio of the channel region formed on the upper surface of the semiconductor to the ratio of the channel region formed on the side surface of the semiconductor may increase. In such a case, the effective channel width is larger than the apparent channel width. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width becomes larger than the apparent channel width, and the influence may become non-negligible. For example, in a fine transistor where the gate electrode covers the side surface of the semiconductor, the ratio of the channel region formed on the side surface of the semiconductor to the ratio of the channel region formed on the upper surface of the semiconductor may increase. In such a case, the effective channel width is larger than the apparent channel width. In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design values, the shape of the semiconductor needs to be known. In such a case, the effective channel width is larger than the apparent channel width.

[0230] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design values, the shape of the semiconductor needs to be known. Assumptions are necessary. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0231] Therefore, in this specification, the apparent channel width may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by analyzing the cross-sectional TEM image.

[0232] Note that when calculating the field-effect mobility of the transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case of calculating using the effective channel width.

[0233] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0234] (Embodiment 6) In this embodiment, the components of the transistor shown in Embodiment 5 will be described in detail.

[0235] The substrate 115 is a silicon substrate on which a transistor and a photodiode are formed, and an insulator, wiring, and a conductor having a function as a contact plug are formed on the silicon substrate. It corresponds to the first layer 1100 and the second layer 1200 in FIG. 1(A). When forming a p-ch type transistor on a silicon substrate, it is - preferred to use a silicon substrate having an n type conductivity type. Or, an SOI substrate having an n - type or i-type silicon layer may be used. Also, the surface orientation of the surface on which the transistor is formed on the silicon substrate is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115 and can also play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method performed by heat treatment at a surface temperature of the film of 100 °C or higher and 700 °C or lower, preferably 100 °C or higher and 500 °C or lower, the insulating layer 120 is made into a film having an oxygen release amount in terms of oxygen atoms of 1.0×10 atoms / cm

[0236] or more. The insulating layer 120 also has a function as an interlayer insulating film, and may be planarized by a method such as CMP (Chemical Mechanical Polishing) so that the surface becomes flat. For example, the insulating layer 120 includes oxide insulating films such as aluminum oxide, magnesium oxide, silicon oxide, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. 19 3

[0237] ​​​​​​​​​​​, nitrides such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride oxide insulating films, or mixed materials thereof can be used. Further, a laminate of the above materials may be used.

[0238] In this embodiment, the oxide semiconductor layer 130 of the transistor is mainly described in detail when it has a three-layer structure in which the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are stacked in order from the insulating layer 120 side.

[0239] When the oxide semiconductor layer 130 is a single layer, a layer corresponding to the oxide semiconductor layer 13 0b shown in this embodiment may be used.

[0240] When the oxide semiconductor layer 130 is a two-layer structure, a laminate in which a layer corresponding to the oxide semiconductor layer 13 0b and a layer corresponding to the oxide semiconductor layer 130c shown in this embodiment are stacked in order from the insulating layer 120 side may be used. In this configuration, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c can be interchanged.

[0241] When the oxide semiconductor layer 130 has four or more layers, for example, a configuration can be adopted in which another oxide semiconductor layer is added to the three-layer oxide semiconductor layer 130 described in this embodiment can be used.

[0242] As an example, for the oxide semiconductor layer 130b, an oxide semiconductor having a larger electron affinity (energy from the vacuum level to the lower end of the conduction band) than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is used. The electron affinity is the energy difference between the vacuum level and the upper end of the valence band (ionization potential) minus the energy difference between the lower end of the conduction band and the upper end of the valence band (energy gap) ​ It can be obtained as a value obtained by subtracting (p).

[0243] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c contain one or more metal elements constituting the oxide semiconductor layer 130b. For example, the energy at the lower end of the conduction band is any one of 0.05 eV, 0.07 eV, 0.1 eV, and 0.15 eV or more higher than that of the oxide semiconductor layer 13 0b, and it is preferably formed of an oxide semiconductor close to the vacuum level within a range of any one of 2 eV, 1 eV, 0.5 eV, and 0.4 eV or less.

[0244] In such a structure, when an electric field is applied to the conductive layer 170, a channel is formed in the oxide semiconductor layer 130, specifically, in the oxide semiconductor layer 130b having the smallest energy at the lower end of the conduction band.

[0245] In addition, since the oxide semiconductor layer 130a is formed by containing one or more metal elements constituting the oxide semiconductor layer 130b, compared with the interface when the oxide semiconductor layer 130b and the insulating layer 120 are in contact, interface levels are less likely to be formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. Since the interface levels may form a channel, the threshold voltage of the transistor may vary. Therefore, by providing the oxide semiconductor layer 130a, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0246] In addition, since the oxide semiconductor layer 130c is formed by containing one or more metal elements constituting the oxide semiconductor layer 130b, when the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact ​​​​​​​​​​​The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0247] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf is a material having a higher atomic number than the oxide semiconductor layer 130b. Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably at least two times, and more preferably at least three times. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0248] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also installed. It is preferred that it includes

[0249] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and Gd. , Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0250] For example, as the oxide semiconductor, indium oxide, tin oxide, gallium oxide, zinc oxide, I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide , Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn

[0251] Here, for example, the In-Ga-Zn oxide means an oxide containing In, Ga, and Zn as main components. Also, even if there are metal elements other than In, Ga, and Zn it is okay. Also, in this specification, a film composed of In-Ga-Zn oxide is also called an IGZO film .

[0252] Also, a material represented by InMO3(ZnO) m (m > 0 and m is not an integer) may be used . Here, M represents one metal element or a plurality of metal elements selected from Ga, Y, Zr, La, Ce, or Nd. Also, In2SnO5(ZnO) n ​​(n > 0 and you may use a material represented by (n is an integer).

[0253] Note that when the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are In-M-Zn oxide containing at least indium, zinc, and M (a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La , Ce, or Hf), if the oxide semiconductor layer 1 30a is In:M:Zn = x1:y1:z1 [atomic ratio], the oxide semiconductor layer 130b is I n:M:Zn = x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Z n = x3:y3:z3 [atomic ratio], it is preferable that y1 / x1 and y3 / x3 are larger than y2 / x2 . y1 / x1 and y3 / x3 are preferably 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more than y2 / x2. At this time, in the oxide semiconductor layer 1 30b, when y2 is equal to or more than x2, the electrical characteristics of the transistor can be stabilized . However, when y2 becomes 3 times or more of x2, the field-effect mobility of the transistor decreases, so it is preferable that y2 is less than 3 times of x2.

[0254] In the case excluding Zn and O in the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, the atomic ratio of In and M is preferably In less than 50 atomic%, M 50 atomic% or more, more preferably In less than 25 atomic%, M 7 5 atomic% or more. Also, for the oxide semiconductor layer 130b excluding Zn and O, the atomic ratio of In and M is preferably In 25 atomic% or more, M 75 at omic% or less, more preferably In 34 atomic% or more, M 66 atomi Set it to less than c%.

[0255] Further, the oxide semiconductor layer 130b has a higher indium content than the oxide semiconductor layer 130a and the oxide semiconductor layer 130 It is preferable to increase the indium content. In an oxide semiconductor, mainly the s-orbitals of heavy metals paths contribute to carrier conduction. By increasing the In content rate, more s-orbitals paths overlap. Therefore, an oxide with more In than M has a higher mobility compared to an oxide with In equal to or less than M when compared. Thus, by using an oxide with a high indium content for the oxide semiconductor layer 130b, a transistor with high field-effect mobility can be realized.

[0256] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 5 0 nm or less, more preferably 5 nm or more and 25 nm or less. Also, the thickness of the oxide semiconductor layer 1 30b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less, more preferably 15 nm or more and 100 nm or less. Also, the thickness of the oxide semiconductor layer 130c is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, more preferably 3 nm or more and 15 nm or less. Also, the oxide semiconductor layer 130b is preferably thicker than the oxide semiconductor layer 1 30a and the oxide semiconductor layer 130c.

[0257] Note that in order to impart stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel it is effective to reduce the impurity concentration in the oxide semiconductor layer and make the oxide semiconductor layer intrinsic (i-type) or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is less than 1×10 / cm 15 / cm 3 less than 1×10 13 / cm​3 less than this and 8×10 11 / cm 3 less than this, or 1×10 8 / cm 3 less than this, and furthermore 1×10 -9 / cm 3 it is assumed to be greater than or equal to this.

[0258] Also, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metals other than the main components become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Also, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels become traps and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the layers of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, and at their respective interfaces.

[0259] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, the silicon concentration estimated by SIMS (Secondary Ion Mass Spectrometry) analysis is 1×10 19 atoms / cm 3 less than, preferably 5×10 18 atoms / cm 3 less than and more preferably 1×10 18 atoms / cm 3 and it is controlled to have a region less than this. Also, the hydrogen concentration is 2×10 20 atoms / cm 3 or less, preferably 5×10 1 9 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm3 Next, further is preferably 5 × 10 18 atoms / cm 3 and control is performed so as to have a region below this value. Further, the nitrogen concentration, for example, at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer, is 5 × 10 atoms / cm 19 less than, preferably 5 × 10 3 atoms / cm 18 less than, more preferably 1 × 10 3 atoms / cm 18 less than, even further 3 preferably 5 × 10 atoms / cm 17 less than, and is made to be 3 the following.

[0260] If silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be deteriorated. In order not to deteriorate the crystallinity of the oxide semiconductor layer, for example, the silicon concentration is 1 × 10 19 atoms / cm 3 less than, preferably 5 × 10 18 atoms / cm 3 less than, even more preferably 1 × 10 18 atoms / cm 3 less than, and control is performed so as to have a region below this value. Further, the carbon concentration is 1 × 10 19 atoms / cm 3 less than, preferably 5 × 10 18 atoms / cm 3 less than, even more preferably 1 × 10 18 atoms / cm 3 less than, and control is performed so as to have a region below this value.

[0261] Further, a transistor using the oxide semiconductor film purified as described above for the channel formation region The off-current of the transistor is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current per channel width of the transistor can be reduced to several y A / μm to several z A / μm.

[0262] Note that as an insulating film for the gate insulating film of the transistor, an insulating film containing silicon is often used. Therefore, due to the above reasons, the region that becomes the channel of the oxide semiconductor layer preferably has a structure that does not contact the gate insulating film like the transistor of one aspect of the present invention. Further, when a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface, and the field-effect mobility of the transistor decreases. From this point of view as well, it can be said that the region that becomes the channel of the oxide semiconductor layer is preferably separated from the gate insulating film.

[0263] Therefore, by forming the oxide semiconductor layer 130 into a stacked structure of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b , and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b, and a transistor having high field-effect mobility and stable electrical characteristics can be formed.

[0264] In the band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, the energy at the lower end of the conduction band changes continuously. This is understood from the fact that the compositions of the oxide semiconductor layer 1 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are approximated, and oxygen diffuses easily among them. Therefore, the oxide semiconductor layer 130a , the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are a laminate of layers having different compositions. It can also be said that they are physically continuous, and in the drawing, each interface of the laminate is represented by a dotted line.

[0265] The oxide semiconductor layers 130 laminated with a common main component are not simply laminated layer by layer but are fabricated so that a continuous junction (here, a U-shaped well structure (U Shape Well) in which the energy at the lower end of the conduction band changes continuously between layers) is formed. That is, no impurities that form defect levels such as trap centers or recombination centers are present at the interfaces of the respective layers so as to form a laminated structure. If impurities are mixed between the laminated oxide semiconductor layers the continuity of the energy band is lost, and carriers are trapped or recombined at the interface and disappear.

[0266] For example, for the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In:Ga:Zn = 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: 9:6 (atomic ratio), etc., of In-Ga-Zn oxide can be used. Also, for the oxide semiconductor layer 130b, In:Ga:Zn = 1:1:1, 2:1:3, 5:5:6, or 3:1:2 (atomic ratio), etc., of In-Ga-Zn oxide can be used. Note that the atomic ratios of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 c each include fluctuations of plus or minus 20% of the above atomic ratios as an error.

[0267] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 becomes a well, and the channel is formed in the oxide semiconductor layer 130b. Note that the oxide semiconductor layer 130 has the lower end of the conduction band Since the energy changes continuously, it can also be called a U-shaped well. Also, the channel formed in such a configuration can also be referred to as an embedded channel.

[0268] In addition, near the interfaces of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c with an insulating layer such as a silicon oxide film, trap levels can be formed due to impurities and defects. Because of the existence of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, the oxide semiconductor layer 13 0b can be kept away from the trap levels. However, when the difference between the energy at the lower end of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c and the energy at the lower end of the conduction band of the oxide semiconductor layer 130b is small, electrons in the oxide semiconductor layer 13

[0269] 0b may reach the trap levels across the energy difference. When electrons are captured by the trap levels, negative charges are generated at the insulating layer interface, and the threshold voltage of the transistor shifts in the positive direction. It is preferable that the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c contain crystal parts. In particular, by using crystals oriented along the c-axis, stable electrical characteristics can be imparted to the transistor . Also, crystals oriented along the c-axis are resistant to distortion and can improve the reliability of semiconductor devices using flexible substrates. For the conductive layer 140 acting as the source electrode layer and the conductive layer 1

[0270] 50 acting as the drain electrode layer, for example, a single layer or a stack of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc , and alloys of these metal materials can be used. Moreover, crystals oriented along the c-axis are resistant to distortion and can improve the reliability of semiconductor devices using flexible substrates. For the conductive layer 140 acting as the source electrode layer and the conductive layer 150 acting as the drain electrode layer, for example, a single layer or a stack of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of these metal materials can be used.

[0271] For the conductive layer 140 acting as the source electrode layer and the conductive layer 1 50 acting as the drain electrode layer, for example, a single layer or a stack of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc , and alloys of these metal materials can be used. Typically, it is more preferable to use W with a high melting point, such as Ti which easily binds to oxygen and can have a relatively high subsequent process temperature. In addition, a laminate of an alloy such as low-resistance Cu or Cu-Mn and the above material may be used. Note that, in transistors 105, 106, 111, and 112, for example, W can be used for conductive layers 141 and 151, and a laminate film of Ti and Al can be used for conductive layers 142 and 152.

[0272] The above material has the property of extracting oxygen from the oxide semiconductor layer. Therefore, in a part of the region of the oxide semiconductor layer in contact with the above material, oxygen in the oxide semiconductor layer desorbs, forming oxygen vacancies. The region becomes n-type by the bonding of the slightly contained hydrogen in the layer with the oxygen vacancies. Therefore, the n-type region can be used as the source or drain of the transistor.

[0273] As the insulating layer 160 acting as a gate insulating film, an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used. In addition, the insulating layer 160 may be a laminate of the above materials. Note that the insulating layer 160 may contain La, nitrogen, Zr, etc. as impurities.

[0274] Next, an example of the laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, oxygen , and has nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide, and oxidation Preferably, it contains silicon oxide or silicon oxynitride.

[0275] Hafnium oxide and aluminum oxide have a higher relative dielectric constant compared to silicon oxide or silicon oxynitride. Therefore, since the film thickness can be increased with respect to silicon oxide, the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant compared to hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these. By the way, the surface to be formed of hafnium oxide having a crystal structure may have interface levels due to defects. The interface levels function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it is preferable to separate them from each other by disposing another film between the channel region of the transistor and hafnium oxide. This film has a buffering function. The film having a buffering function may be a film included in the insulating layer 160, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, oxide semiconductor, etc. can be used. Note that the film having a buffering function includes, for example, the channel region

[0276] Incidentally, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it is preferable to separate them from each other by disposing another film between the channel region of the transistor and hafnium oxide. This film has a buffering function. The film having a buffering function may be a film included in the insulating layer or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, oxide semiconductor, etc. can be used. Note that the film having a buffering function includes, for example, the channel region When hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it is preferable to separate them from each other by disposing another film between the channel region of the transistor and hafnium oxide. This film has a buffering function. The film having a buffering function may be a film included in the insulating layer 160, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, oxide semiconductor, etc. can be used. Note that the film having a buffering function includes, for example, the channel region It may be a film included in the insulating layer 160 or may be a film included in the oxide semiconductor film. That is, As the film having a buffering function, silicon oxide, silicon oxynitride, oxide semiconductor, etc. can be used. Note that the film having a buffering function includes, for example, the channel region A semiconductor or insulator having a larger energy gap than the semiconductor is used. Or, for the film having a buffer function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Or, for the film having a buffer function, for example, a semiconductor or insulator having a larger ionization energy than the semiconductor that becomes the channel region is used. On the other hand, there is a case where the threshold voltage of the transistor can be controlled by trapping charges at the interface levels (trap centers) on the formed surface of hafnium oxide having the crystal structure described above. In order to stably exist the charges, for example, a semiconductor or insulator having a larger energy gap than hafnium oxide may be disposed between the channel region and hafnium oxide. Or, a semiconductor or insulator having a smaller electron affinity than hafnium oxide may be disposed. Or, for the film having a buffer function, a semiconductor or insulator having a larger ionization energy than hafnium oxide may be disposed. By using such a semiconductor or insulator, the release of the charges trapped at the interface levels is less likely to occur, and the charges can be held for a long period of time. As such an insulator, for example, silicon oxide and silicon oxynitride can be mentioned. In order to capture charges at the interface levels in the insulating layer 160, electrons may be moved from the oxide semiconductor layer 130 toward the gate electrode layer (conductive layer 170). As a specific example, under a high temperature (for example, 125 ° C or higher and 450 ° C or lower, typically 150 ° C or higher and 300 ° C or lower), the potential of the gate electrode layer (conductive layer 170) is set higher than the potentials of the source electrode and the drain electrode.

[0277] One the other hand, there is a situation where the threshold voltage of the transistor can be controlled by trapping charges at the interface levels (trap centers) on the formed surface of hafnium oxide having the crystal structure described above. To stably hold such charges, for example, a semiconductor or insulator having a larger energy gap than hafnium oxide may be disposed between the channel region and hafnium oxide. Or, a semiconductor or insulator having a smaller electron affinity than hafnium oxide may be disposed. Or, for the film having a buffer function, a semiconductor or insulator having a larger ionization energy than hafnium oxide may be disposed. By using such a semiconductor or insulator, the release of the charges trapped at the interface levels is less likely to occur, and the charges can be held over a long period of time. As such an insulator, for example, silicon oxide and silicon oxynitride can be mentioned. To capture charges at the interface levels in the insulating layer 160, electrons may be moved from the oxide semiconductor layer 130 toward the gate electrode layer (conductive layer 170). Specifically, at a high temperature (for example, 125 °C or higher and 450 °C or lower, typically 150 °C or higher and 300 °C or lower), the potential of the gate electrode layer (conductive layer 170) is set higher than the potentials of the source electrode and the drain electrode.

[0278] As such an insulator, for example, silicon oxide, silicon oxynitride can be cited. To capture charges at the interface levels in the insulating layer 160, electrons may be moved from the oxide semiconductor layer 130 toward the gate electrode layer (conductive layer 170). As a specific example, at a high temperature (for example, 125 ° C or higher and 450 ° C or lower, typically 150 ° C or higher and 300 ° C or lower), the potential of the gate electrode layer (conductive layer 170) is set higher than the potentials of the source electrode and the drain electrode. To capture charges at the interface levels in the insulating layer 160, electrons may be moved from the oxide semiconductor layer 130 toward the gate electrode layer (conductive layer 170). Specific examples include, at a high temperature (for example, 125 °C or higher and 450 °C or lower, typically 150 °C or higher and 300 °C or lower), setting the potential of the gate electrode layer (conductive layer 170) higher than the potentials of the source electrode and the drain electrode. Under such conditions, ​It is sufficient to maintain the temperature at this temperature for at least one second, typically at least one minute.

[0279] In this way, a transistor in which a desired amount of electrons are trapped in the interface state of the insulating layer 160, etc., The threshold voltage is shifted to the positive side. By adjusting the application time, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. If the charges can be trapped, the charges can be trapped not in the insulating layer 160 but in the A laminated film having a similar structure may be used for other insulating layers.

[0280] In addition, in the insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130, nitrogen The semiconductor device may have a region having a low density of oxide-induced states. As the oxide insulating layer, a silicon oxynitride film or a nitrogen oxide film having a low nitrogen oxide emission amount is used. An aluminum oxynitride film or the like that releases less substances can be used.

[0281] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectrometry (TDS). (Thermal Desorption Spectroscopy) This is a membrane that releases more ammonia than elemental oxide, and is typically The amount is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is ammonia. The amount of release is determined when the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released by the heat treatment below.

[0282] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0283] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. Alternatively, alloys such as Cu-Mn or laminations of the above materials with Cu or alloys such as Cu-Mn may be used. In this embodiment, tantalum nitride is used for the conductive layer 171 and tungsten is used for the conductive layer 172. This is used to form the conductive layer 170 .

[0284] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0285] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the case of the stud 107, the transistor 108, and the transistor 111, it is preferable to use an aluminum oxide film for the insulating layer 175. The aluminum oxide film has a high blocking effect of not allowing the film to permeate impurities such as hydrogen and moisture, as well as both oxygen. Therefore, the aluminum oxide film is suitable for use as a protective film that prevents the incorporation of impurities such as hydrogen and moisture into the oxide semiconductor layer 130 during and after the manufacturing process of the transistor, prevents the release of oxygen from the oxide semiconductor layer, and prevents the unnecessary release of oxygen from the insulating layer 1 20. Further, the oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer.

[0286] Also, it is preferable that an insulating layer 180 is formed on the insulating layer 175. For the insulating layer, an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used. Further, the insulating layer may be a laminate of the above materials.

[0287] Here, it is preferable that the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. Since the oxygen released from the insulating layer 180 can be diffused through the insulating layer 160 into the channel formation region of the oxide semiconductor layer 130, the oxygen deficiency formed in the channel formation region can be replenished with oxygen. Therefore, stable electrical characteristics of the transistor can be obtained.

[0288] ​​​​​​​​​​​​In order to highly integrate a semiconductor device, miniaturization of transistors is essential. On the other hand, it is known that the electrical characteristics of transistors deteriorate due to the miniaturization of transistors. When the channel width is reduced, the on-current decreases. In the transistors 107 to 112 according to one aspect of the present invention, an oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b in which a channel is formed, and the channel formation layer and the gate insulating film are not in contact with each other. Therefore, scattering of carriers generated at the interface between the channel formation layer and the gate insulating film can be suppressed, and the on-current of the transistor can be increased.

[0289] In the transistors 107 to 112 according to one aspect of the present invention, an oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b in which a channel is formed, and the channel formation layer and the gate insulating film are not in contact with each other. Therefore, scattering of carriers generated at the interface between the channel formation layer and the gate insulating film can be suppressed, and the on-current of the transistor can be increased. formation layer and the gate insulating film are not in contact with each other. Therefore, scattering of carriers generated at the interface between the channel formation layer and the gate insulating film can be suppressed, and the on-current of the transistor can be increased. Moreover, in the transistor according to one aspect of the present invention, as described above, the gate electrode layer (conductive layer 170) is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 130. Therefore, in addition to the gate electric field from the vertical direction to the upper surface with respect to the oxide semiconductor layer 130, the gate electric field from the direction perpendicular to the side surface is applied. That is, the gate electric field is applied to the channel formation layer as a whole, and the effective channel width is expanded. Therefore, the on-current can be further increased.

[0290] Moreover, in the transistor according to one aspect of the present invention, as described above, the gate electrode layer (conductive layer 170) is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 130. Therefore, in addition to the gate electric field from the vertical direction to the upper surface with respect to the oxide semiconductor layer 130, the gate electric field from the direction perpendicular to the side surface is applied. That is, the gate electric field is applied to the channel formation layer as a whole, and the effective channel width is expanded. Therefore, the on-current can be further increased. Therefore, in addition to the gate electric field from the vertical direction to the upper surface with respect to the oxide semiconductor layer 130, the gate electric field from the direction perpendicular to the side surface is applied. That is, the gate electric field is applied to the channel formation layer as a whole, and the effective channel width is expanded. Therefore, the on-current can be further increased. Therefore, in addition to the gate electric field from the vertical direction to the upper surface with respect to the oxide semiconductor layer 130, the gate electric field from the direction perpendicular to the side surface is applied. That is, the gate electric field is applied to the channel formation layer as a whole, and the effective channel width is expanded. Therefore, the on-current can be further increased. Therefore, in addition to the gate electric field from the vertical direction to the upper surface with respect to the oxide semiconductor layer 130, the gate electric field from the direction perpendicular to the side surface is applied. That is, the gate electric field is applied to the channel formation layer as a whole, and the effective channel width is expanded. Therefore, the on-current can be further increased. Therefore, in addition to the gate electric field from the vertical direction to the upper surface with respect to the oxide semiconductor layer 130, the gate electric field from the direction perpendicular to the side surface is applied. That is, the gate electric field is applied to the channel formation layer as a whole, and the effective channel width is expanded. Therefore, the on-current can be further increased.

[0291] Moreover, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has two or three layers, forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a has the effect of making it difficult to form interface levels. In addition, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has three layers, by making the oxide semiconductor layer 130b the layer located in the middle of the three-layer structure, effects such as eliminating the influence of impurity mixing from above and below can be achieved. Moreover, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has two or three layers, forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a has the effect of making it difficult to form interface levels. In addition, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has three layers, by making the oxide semiconductor layer 130b the layer located in the middle of the three-layer structure, effects such as eliminating the influence of impurity mixing from above and below can be achieved. Moreover, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has two or three layers, forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a has the effect of making it difficult to form interface levels. In addition, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has three layers, by making the oxide semiconductor layer 130b the layer located in the middle of the three-layer structure, effects such as eliminating the influence of impurity mixing from above and below can be achieved. Moreover, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has two or three layers, forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a has the effect of making it difficult to form interface levels. In addition, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has three layers, by making the oxide semiconductor layer 130b the layer located in the middle of the three-layer structure, effects such as eliminating the influence of impurity mixing from above and below can be achieved. Moreover, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has two or three layers, forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a has the effect of making it difficult to form interface levels. In addition, in the transistor in which the oxide semiconductor layer 130 according to one aspect of the present invention has three layers, by making the oxide semiconductor layer 130b the layer located in the middle of the three-layer structure, effects such as eliminating the influence of impurity mixing from above and below can be achieved. This is done. Therefore, in addition to the improvement in the on-current of the transistor described above, it is possible to achieve stabilization of the threshold voltage and reduction of the S value (subthreshold value). Thus, Icu t (the current when the gate voltage VG is 0 V) can be lowered, and power consumption can be reduced. In addition, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention is suitable for forming a highly integrated semiconductor device because deterioration of electrical characteristics accompanying miniaturization can be suppressed.

[0292] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0293] (Embodiment 7) In this embodiment, a method for manufacturing the transistor 101 and the transistor 1 07 described in Embodiment 5 will be described.

[0294] First, an example of a method for manufacturing a silicon transistor included in the substrate 115 will be described. As the silicon substrate, an n - -type single-crystalline silicon substrate is used, and an element formation region separated by an insulating layer (also referred to as a field oxide film ) is formed on the surface. The formation of the element isolation region can use the LOCOS method ( Local Oxidation of Silicon) or the STI method (Shallow Trench Isolation), etc.

[0295] Here, the substrate is not limited to a single-crystalline silicon substrate, and an SOI (Silicon on Insul ator) substrate or the like can also be used.

[0296] Next, a gate insulating film is formed so as to cover the element formation region. For example, a silicon oxide film is formed by performing a heat treatment to oxidize the surface of the element formation region. Further, after forming the silicon oxide film, the surface of the silicon oxide film may be nitrided by performing a nitriding treatment. Next, a conductive film is formed so as to cover the gate insulating film. As the conductive film, an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, Nb, etc., or an alloy material or a compound material mainly composed of these elements can be used. Further, it can also be formed of a metal nitride film obtained by nitriding these elements. In addition, it can also be formed of a semiconductor material typified by polycrystalline silicon doped with impurity elements such as phosphorus.

[0297] Next, the conductive film is selectively etched to form a gate electrode layer on the gate insulating film. Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to cover the gate electrode layer, and an etch-back is performed to form sidewalls on the side surfaces of the gate electrode layer. Next, a resist mask is selectively formed so as to cover the region other than the element formation region, and an impurity element is introduced using the resist mask and the gate electrode layer as masks to form a p-type impurity region. Here, in order to form a p-ch type transistor, as the impurity element, B, Ga, etc., which are impurity elements that impart a p-type, can be used. Next, a resist mask is selectively formed to fabricate a photodiode. Here, Next, a resist mask is selectively formed to fabricate a photodiode. Here,

[0298] Next, the conductive film is selectively etched to form a gate electrode layer on the gate insulating film. Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to cover the gate electrode layer, and an etch-back is performed to form sidewalls on the side surfaces of the gate electrode layer.

[0299] Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to cover the gate electrode layer, and an etch-back is performed to form sidewalls on the side surfaces of the gate electrode layer. Next, a resist mask is selectively formed so as to cover the region other than the element formation region, and an impurity element is introduced using the resist mask and the gate electrode layer as masks to form a p-type impurity region. Here, in order to form a p-ch type transistor, as the impurity element, B, Ga, etc., which are impurity elements that impart a p-type, can be used.

[0300] Next, a resist mask is selectively formed so as to cover the region other than the element formation region, and an impurity element is introduced using the resist mask and the gate electrode layer as masks to form a p-type impurity region. Here, in order to form a p-ch type transistor, as the impurity element, B, Ga, etc., which are impurity elements that impart a p-type, can be used. Next, a resist mask is selectively formed so as to cover the region other than the element formation region, and an impurity element is introduced using the resist mask and the gate electrode layer as masks to form a p-type impurity region. Here, in order to form a p-ch type transistor, as the impurity element, B, Ga, etc., which are impurity elements that impart a p-type, can be used. + type impurity Next, a resist mask is selectively formed so as to cover the region other than the element formation region, and an impurity element is introduced using the resist mask and the gate electrode layer as masks to form a p-type impurity region. Here, in order to form a p-ch type transistor, as the impurity element, B, Ga, etc., which are impurity elements that impart a p-type, can be used. Next, a resist mask is selectively formed so as to cover the region other than the element formation region, and an impurity element is introduced using the resist mask and the gate electrode layer as masks to form a p-type impurity region. Here, in order to form a p-ch type transistor, as the impurity element, B, Ga, etc., which are impurity elements that impart a p-type, can be used.

[0301] Next, a resist mask is selectively formed to fabricate a photodiode. Here, , on the same surface of the single-crystal silicon substrate as the surface on which the transistor is formed, a photodiode To form the cathode of the photodiode, phosphorus (P), an impurity element that imparts an n-type, or arsenic ( As) is introduced to form an n + -type shallow impurity region. Also, a p -type deep impurity region for making an electrical connection between the anode of the photodiode and the wiring may be formed + . Note that the anode of the photodiode (p -type shallow impurity region) is formed on the surface of the single-crystal silicon substrate opposite to the surface on which the cathode of the photodiode is formed in a later process + .

[0302] Here, as shown in Fig. 1(A), the region in contact with the side surface of the photodiode is opened by etching, and an insulating layer is provided in the opening. As the insulating layer, a silicon oxide layer, a silicon nitride layer, etc. can be used, and it can be formed by a film formation method such as CVD (Chemical Vapor Deposi tion) method or a thermal oxidation method.

[0303] Thus, a p-ch type transistor having an active region on the silicon substrate and a photodiode are completed. Note that it is preferable to form a passivation film such as a silicon nitride film on the transistor.

[0304] Next, an interlayer insulating film is formed on the silicon substrate on which the transistor is formed, using a silicon oxide film or the like, and various conductors and various wiring layers are formed. Also, as described in Embodiment 1, an insulating layer such as aluminum oxide that prevents hydrogen diffusion is formed. On the substrate 115, the silicon substrate on which the above-described tra nsistor and photodiode are formed, and formed on the silicon substrate It includes a formed interlayer insulating layer, wiring layer, conductor, etc.

[0305] Subsequently, a method for manufacturing the transistor 102 will be described with reference to FIGS. 40 and 41. Note that the left side of the drawing shows a cross-section in the channel length direction of the transistor, and the right side shows the cross-section in the channel width direction. Also, since the drawing in the channel width direction is an enlarged view, the apparent film thickness of each element is different in the left and right drawings.

[0306] The oxide semiconductor layer 130 exemplifies a case where it has a three-layer structure of an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. When the oxide semiconductor layer 130 has a two-layer structure it may be composed of two layers, namely, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. Also, when the oxide semiconductor layer 130 has a single-layer structure, it may be a single layer of the oxide semiconductor layer 130b only.

[0307] First, an insulating layer 120 is formed on the substrate 115. The type of the substrate 115 and the material of the insulating layer 120 can be referred to the description in Embodiment 6. Note that the insulating layer 120 can be formed by using sputtering, CVD (Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), etc.

[0308] Also, oxygen may be added to the insulating layer 120 by using ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, etc. By adding oxygen, the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130 can be made more facilitated.

[0309] Note that the surface of the substrate 115 is an insulator, and the impurity diffusion ​​When there is no influence of scattering, the configuration can be such that the insulating layer 120 is not provided.

[0310] Next, an oxide semiconductor film 130A that becomes the oxide semiconductor layer 130a, an oxide semiconductor film 130B that becomes the oxide semiconductor layer 130b, and an oxide semiconductor film 130C that becomes the oxide semiconductor layer 130c are formed using a sputtering method, a CVD method, an MBE method, etc. (refer to Fig. 4 0(A)).

[0311] When the oxide semiconductor layer 130 has a laminated structure, the oxide semiconductor films are preferably laminated continuously without being exposed to the atmosphere using a multi-chamber type film forming apparatus (for example, a sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus should be evacuated to a high vacuum (up to about 5×10 Pa to 1×10 Pa) using an adsorption type vacuum exhaust pump such as a cryopump to remove impurities such as water as much as possible for the oxide semiconductor, and the substrate should be heated to 100°C or higher, preferably 500°C or higher. It is preferable to use a combination of a turbo molecular pump and a cold trap to prevent gas containing carbon components and moisture from flowing back into the chamber from the exhaust system. A combination of a turbo molecular pump and a cryopump for the exhaust system may also be used. -7 -4 In order to obtain a high-purity intrinsic oxide semiconductor, it is preferable not only to evacuate the chamber to a high vacuum but also to purify the sputtering gas to a high purity. The oxygen gas and argon gas used as the sputtering gas should be purified to a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower to prevent moisture and the like from being incorporated into the oxide semiconductor film as much as possible.

[0312] ​​​​​​​​​​​ can be done.

[0313] For the oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C, the materials described in Embodiment 6 can be used. When the sputtering method is used as the film formation method films can be formed using the materials described in Embodiment 6 as targets.

[0314] However, as described in detail in Embodiment 6, for the oxide semiconductor film 130B, a material with a larger electron affinity than that of the oxide semiconductor film 130A and the oxide semiconductor film 130C is used.

[0315] In addition, it is preferable to use the sputtering method for forming the oxide semiconductor film. As the sputtering method the RF sputtering method, the DC sputtering method, the AC sputtering method, etc. can be used.

[0316] After the formation of the oxide semiconductor film 130C, a first heat treatment may be performed. The first heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. Also, the atmosphere of the first heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere. By the first heat treatment, the crystallinity of the oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C is enhanced, and furthermore, impurities such as hydrogen and water can be removed from the insulating layer 120, the oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C. Note that the first heat treatment is for the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the like described later. and the oxide semiconductor film 130C. In addition, the first heat treatment can remove impurities such as hydrogen and water from the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the like described later. It may be performed after the etching for forming the oxide semiconductor layer 130c.

[0317] Next, a first conductive layer is formed on the oxide semiconductor film 130A. The first conductive layer can be formed, for example, using the following method.

[0318] First, a first conductive film is formed on the oxide semiconductor film 130A. As the first conductive film, A l, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and a single layer or laminate of a material selected from alloys of the metal materials can be used.

[0319] Next, a resist film is formed on the first conductive film, and the resist film is exposed using a method such as electron beam exposure, immersion exposure, EUV exposure, etc., and a first resist mask is formed by performing development processing. Note that an organic coating film is preferably formed as an adhesive layer between the first conductive film and the resist film. Alternatively, the first resist mask may be formed using a nanoimprint lithography method.

[0320] Next, using the first resist mask, the first conductive film is selectively etched, and the first resist mask is ashed to form a conductive layer.

[0321] Next, using the above conductive layer as a hard mask, the oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C are selectively etched to remove the above conductive layer, and an oxide semiconductor layer 130 composed of a laminate of the oxide semiconductor layers 130a, 130b, and 130c is formed (see FIG. 40(B)). Note that the oxide semiconductor layer 130 may be formed using the first resist mask without forming the above conductive layer. ​ Here, oxygen ions may be implanted into the oxide semiconductor layer 130.

[0322] Next, a second conductive film is formed so as to cover the oxide semiconductor layer 130. As the second conductive film the materials that can be used for the conductive layer 140 and the conductive layer 150 described in Embodiment 6 may be used for formation. For the formation of the second conductive film, sputtering, CVD, MBE, etc. can be used.

[0323] Next, a second resist mask is formed on the portions that will become the source region and the drain region . Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150 (see Fig. 40(C)).

[0324] Next, an insulating film 160A that will become a gate insulating film is formed on the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150 . The insulating film 160A may be formed of a material that can be used for the insulating layer 160 described in Embodiment 6 . For the formation of the insulating film 160A, sputtering, C VD, MBE, etc. can be used.

[0325] Next, a second heat treatment may be performed. The second heat treatment can be performed under the same conditions as the first heat treatment . By the second heat treatment, the oxygen implanted into the oxide semiconductor layer 130 can be diffused throughout the oxide semiconductor layer 130 . Note that the above effect may be obtained by a third heat treatment without performing the second heat treatment .

[0326] Next, a third conductive film 171A and a fourth conductive film 172A that will become the conductive layer 170 are formed on the insulating film 160A. The third conductive film 171A and the fourth conductive film 172A are in Embodiment It may be formed of a material that can be used for the conductive layer 171 and the conductive layer 172 described in 6. For the formation of the third conductive film 171A and the fourth conductive film 172A, a sputtering method, CVD method, MBE method, or the like can be used.

[0327] Next, a third resist mask 156 is formed on the fourth conductive film 172A (see Fig. 41(A)) Reference). Then, using the third resist mask 156, the third conductive film 171A, the fourth conductive film 172A, and the insulating film 160A are selectively etched to form a conductive layer 170 composed of the conductive layer 171 and the conductive layer 172, and an insulating layer 160 (see Fig. 41(B)).

[0328] Next, an insulating layer 175 is formed on the oxide semiconductor layer 130, the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170. For the material of the insulating layer 175, reference can be made to the description of Embodiment 6. In the case of the transistor 101, it is preferable to use an aluminum oxide film. The insulating layer 175 can be formed by a sputtering method, a CVD method, an MBE method, or the like.

[0329] Next, an insulating layer 180 is formed on the insulating layer 175 (see Fig. 41(C)). For the material of the insulating layer 180, reference can be made to the description of Embodiment 6. Also, the insulating layer 180 can be formed by a sputtering method, a CVD method, an MBE method, or the like.

[0330] In addition, oxygen may be added to the insulating layer 175 and / or the insulating layer 180 by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment method, or the like. By adding oxygen, the insulating layer 175 and / or the insulating layer 1 80 The supply of oxygen from the 80 to the oxide semiconductor layer 130 can be further facilitated.

[0331] Next, a third heat treatment may be performed. The third heat treatment can be performed under the same conditions as the first heat treatment. Excess oxygen is likely to be released from the insulating layer 120, the insulating layer 175, and the insulating layer 180, and the oxygen deficiency in the oxide semiconductor layer 130 can be reduced.

[0332] Next, a method for manufacturing the transistor 107 will be described. Note that detailed descriptions of steps overlapping with the method for manufacturing the transistor 101 described above will be omitted.

[0333] An insulating layer 120 is formed on the substrate 115, and an oxide semiconductor film 130A that becomes the oxide semiconductor layer 130a and an oxide semiconductor film 130B that becomes the oxide semiconductor layer 130b are formed on the insulating layer using a sputtering method, a CVD method, an MBE method, or the like (see FIG. 42(A)).

[0334] Next, a first conductive film is formed on the oxide semiconductor film 130B, and a conductive layer is formed using the first resist mask in the same manner as described above. Then, the oxide semiconductor film 130A and the oxide semiconductor film 130B are selectively etched using the conductive layer as a hard mask, and the conductive layer is removed to form a stack composed of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b (see FIG. 42(B)). Note that the stack may be formed using the first resist mask without forming a hard mask. Here, oxygen ions may be implanted into the oxide semiconductor layer 130.

[0335] Next, a second conductive film is formed so as to cover the stack. Then, a source region and a drain ​​​​​​​​​​​A second resist mask is formed over a portion that becomes the N region, and using the second resist mask, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150 ( see Fig. 42(C)).

[0336] Next, an oxide semiconductor film 130C that becomes the oxide semiconductor layer 130c is formed over the stacked oxide semiconductor layer 130a and the oxide semiconductor layer 130b, and over the conductive layer 140 and the conductive layer 150. Further, an insulating film 160A that becomes a gate insulating film, and a third conductive film 171A and a fourth conductive film 172A that become the conductive layer 170 are formed over the oxide semiconductor film 130C.

[0337] Next, a third resist mask 156 is formed over the fourth conductive film 172A (see Fig. 43(A)). Then, using the resist mask, the third conductive film 171A, the fourth conductive film 172A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched to form a conductive layer 170 composed of the conductive layer 171 and the conductive layer 172, an insulating layer 160, and an oxide semiconductor layer 130c (see Fig. 43(B)). Note that the transistor 108 can be fabricated by etching the insulating film 160A and the oxide semiconductor film 130C using a fourth resist mask.

[0338] Next, an insulating layer 175 and an insulating layer 180 are formed over the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, the oxide semiconductor layer 130c), the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170 (see Fig. 43(C)).

[0339] In the above steps, the transistor 107 can be fabricated. ​​​​​​

[0340] Note that various films such as the metal film, semiconductor film, and inorganic insulating film described in this embodiment can typically be formed by sputtering or plasma CVD methods, but other methods, such as thermal CVD methods, may also be used. Examples of thermal CVD methods include MOCVD (Metal O rganic Chemical Vapor Deposition) and ALD (A tomic Layer Deposition).

[0341] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0342] Also, in the thermal CVD method, the source gas and the oxidizing agent are simultaneously introduced into the chamber, and the chamber is under atmospheric pressure or reduced pressure, and reacted near or on the substrate to deposit on the substrate, thereby forming a film.

[0343] In the ALD method, the chamber is under atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber and reacted, and this is repeated to form a film. An inert gas ( argon, nitrogen, etc.) may be introduced as a carrier gas together with the source gas. For example, two or more types of source gases may be supplied to the chamber in sequence. At that time, after the reaction of the first source gas so that the plurality of types of source gases do not mix, an inert gas is introduced, and the second source gas is introduced. Or, instead of introducing an inert gas, after discharging the first source gas by evacuation, the second source gas may be introduced. The first source gas adsorbs and reacts on the surface of the substrate to form the first layer , and the second source gas introduced later adsorbs and reacts, and the second layer is formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0344] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used instead of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0345] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0346] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Raw material gas obtained by vaporizing (such as) and two types of gases, H2O as an oxidant, are used. Other materials include tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There are.

[0347] For example, when forming a silicon oxide film by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film forming surface, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied and reacted with the adsorbed substance.

[0348] For example, when forming a tungsten film by a film forming apparatus using ALD, WF6 gas and B2H6 gas are sequentially introduced to form an initial tungsten film, and then WF6 gas and H 2 gas are sequentially introduced to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0349] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, by a film forming apparatus using ALD, In(CH3)3 gas and O3 gas are sequentially introduced to form an In-O layer and then Ga(CH3)3 gas and O3 gas are sequentially introduced to form a GaO layer, and further Zn(CH3)2 and O3 gas are sequentially introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed using these gases. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H.

[0350] ​​​​​Note that the present embodiment can be appropriately combined with other embodiments described in this specification. 。

[0351] (Embodiment 8) Hereinafter, the structure of an oxide semiconductor film that can be used in one aspect of the present invention will be described. 。

[0352] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0353] Also, in this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system. 。

[0354] Oxide semiconductor films are roughly classified into non-single crystal oxide semiconductor films and single crystal oxide semiconductor films. Non single crystal oxide semiconductor films refer to CAAC-OS (C Axis Aligned Crys talline Oxide Semiconductor) films, polycrystalline oxide semiconductor films , microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, and the like.

[0355] First, the CAAC-OS film will be described.

[0356] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented along the c-axis.

[0357] By a transmission electron microscope (TEM: Transmission Electron Micro scope), a composite analysis image of the bright field image and diffraction pattern of the CAAC-OS film ( It is also called a high-resolution TEM image. By observing (), a plurality of crystal parts can be confirmed. On the other hand, even with a high-resolution TEM image, the boundary between distinct crystal parts, that is, the grain boundary (also called grain boundary underlay) cannot be confirmed. Therefore, it can be said that in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is unlikely to occur.

[0358] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction substantially parallel to the sample surface, it can be confirmed that in the crystal part, metal atoms are arranged in layers. Each layer of metal atoms reflects the unevenness of the surface (also called the formed surface) or the upper surface of the CAAC-OS film and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0359] On the other hand, when observing a high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample surface it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0360] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) device for example, in the out-of-plane method analysis of a CAAC-OS film having InGaZnO4 crystals a peak may appear near a diffraction angle (2θ) of 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal and thus it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0361] ​​Note: Out-of-plane method of CAAC-OS film having InGaZnO4 crystal In the analysis by the , in addition to the peak with 2θ around 31°, a peak may also appear at around 2θ = 36° . The peak at around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation . The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36° .

[0362] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon , silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, take oxygen from the oxide semiconductor film to disrupt the atomic arrangement of the oxide semiconductor film and reduce its crystallinity . Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc. have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they disrupt the atomic arrangement of the oxide semiconductor film and become a factor in reducing its crystallinity. Note that impurities contained in the oxide semiconductor film may be carrier traps or carrier generation sources .

[0363] Also, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen vacancies in the oxide semiconductor film may become carrier traps or carrier generation sources by capturing hydrogen .

[0364] A low impurity concentration and a low defect level density (few oxygen vacancies) are called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film with high-purity intrinsic or substantially high-purity intrinsic Since there are few carrier generation sources, the carrier density can be lowered. Therefore, a transistor using the oxide semiconductor film rarely has an electrical characteristic in which the threshold voltage becomes negative ( also referred to as normally-on).). Also, an oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using the oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high defect level density may have unstable electrical characteristics. Moreover, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Moreover, a transistor using an oxide semiconductor film with a high impurity concentration and a high defect level density may have unstable electrical characteristics.

[0365] Next, the microcrystalline oxide semiconductor film will be described.

[0366] Next, the microcrystalline oxide semiconductor film will be described.

[0367] In a high-resolution TEM image, the microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called an nc -OS (nanocrystalline Oxide Semiconductor) film. Also, in a high-resolution TEM image, for example, the nc-OS film clearly shows grain boundaries. In a high-resolution TEM image, the microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called an nc -OS (nanocrystalline Oxide Semiconductor) film. Also, in a high-resolution TEM image, for example, the nc-OS film clearly shows grain boundaries. -OS (nanocrystalline Oxide Semiconductor) film. Also, in a high-resolution TEM image, for example, the nc-OS film clearly shows grain boundaries. -OS (nanocrystalline Oxide Semiconductor) film. Also, the nc-OS film, for example, clearly shows grain boundaries in a high-resolution TEM image. ​​There may be cases where it cannot be recognized.

[0368] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, the nc-OS film has no regularity in the crystal orientation between different crystalline parts. Therefore, no orientation is observed in the whole film. Thus, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus using X-rays with a diameter larger than that of the crystalline part, in the analysis by the out-of-plane method, no peak indicating a crystal plane is detected. Further, for the nc-OS film, electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter larger than that of the crystalline part (for example, 50 nm or more) is performed, and a diffraction pattern such as a halo pattern is observed. On the other hand, for the nc-OS film, nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than that of the crystalline part is performed, and spots are observed. Further, when performing nanobeam electron diffraction on the nc-OS film, spots distributed in a circular shape may be observed. Further, when performing nanobeam electron diffraction on the nc-OS film, a plurality of spots may be observed within a ring-shaped region.

[0369] The nc-OS film is an oxide semiconductor film having higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystalline parts. Therefore, the nc-O S film has a higher density of defect levels than the CAAC-OS film.

[0370] Next, the amorphous oxide semiconductor film will be described.

[0371] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

[0372] In the high-resolution TEM image, no crystal part can be confirmed in the amorphous oxide semiconductor film.

[0373] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

[0374] Note that the oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (amorphous-like OS: amorphous-like Oxide Semiconductor) film. ide Semiconductor) film.

[0375] In the high-resolution TEM image of the amorphous-like OS film, voids (also referred to as voids) may be observed. Also, in the high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The amorphous-like OS film is crystallized by a very small amount of electron irradiation to the extent observable by TEM. ​​​​​​​​​Crystallization may occur and growth of the crystalline portion may be observed. On the other hand, in the case of a high-quality nc-OS film , crystallization due to a minute amount of electron irradiation to the extent observable by TEM is hardly seen.

[0376] In addition, measurement of the size of the crystalline portion of the amorphous-like OS film and the nc-OS film can be performed using a high-resolution TEM image. For example, the crystal of InGaZnO4 has a layered structure and has two Ga-Zn-O layers between In-O layers. The unit lattice of the crystal of InGaZnO4 has three In-O layers and six Ga-Zn-O layers, and a total of nine layers are stacked in a layered manner in the c-axis direction. Therefore, the distance between these adjacent layers is , about the same as the lattice plane spacing of the (009) plane (also referred to as the d value). From crystal structure analysis, its value is determined to be 0.29 nm. Therefore, paying attention to the lattice fringes in the high-resolution TEM image , at locations where the distance between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each of the lattice fringes corresponds to the a-b plane of the crystal of InGaZnO4.

[0377] In addition, the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, an amorphous-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. It may be.

[0378] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments. It can be.

[0379] (Embodiment 9) Hereinafter, the band structure of the transistor according to one aspect of the present invention will be described.

[0380] FIG. 44(A) is a cross-sectional view of a transistor having an oxide semiconductor layer according to one aspect of the present invention Yes.

[0381] The transistor shown in Fig. 44(A) includes an insulating layer 401 on a substrate 400, a conductive layer 404a on the insulating layer 401, a conductive layer 404b on the conductive layer 404a, an insulating layer 402a on the insulating layer 401, on the conductive layer 40 4a and on the conductive layer 404b, an insulating layer 402b on the insulating layer 402a and a semiconductor layer 406a on the insulating layer 402b, a semiconductor layer 406b on the semiconductor layer 406a , an insulating layer 412 on the semiconductor layer 406b, a conductive layer 414a on the insulating layer 412, and a conductive layer 4 14a, a conductive layer 414b on the conductive layer 414a, an insulating layer 408 on the insulating layer 402b, on the semiconductor layer 406a, on the semiconductor layer 406 b, on the insulating layer 412, on the conductive layer 414a, and on the conductive layer 414b, an insulating layer 418 on the insulating layer 408, a conductive layer 416a1 and a conductive layer 416 b1 on the insulating layer 418, and conductive layers 416a2 and respectively conductive layers 416b2 on the conductive layers 416a1 and 416b1, and an insulating layer 428 on the insulating layer 418, on the conductive layer 416a2, and on the conductive layer 416b2. It has.

[0382] The insulating layer 401 may have a function of suppressing the mixing of impurities such as copper into the channel formation region of the transistor. It may have.

[0383] The stack of the conductive layer 404a and the conductive layer 404b is collectively referred to as the conductive layer 404. The conductive layer 404 has a function as the gate electrode of the transistor. Also, the conductive layer 404 may have a function of shielding light from the channel formation region of the transistor, etc. It may have.

[0384] The insulating layer 402a and the insulating layer 402b are collectively referred to as the insulating layer 402. The insulating layer 402 is the It has a function as a gate insulating layer of a transistor. Further, the insulating layer 402a may have a function of suppressing the mixing of impurities such as copper into the channel formation region of the transistor.

[0385] The semiconductor layer 406a and the semiconductor layer 406b are collectively referred to as the semiconductor layer 406. The semiconductor layer 406 has a function as a channel formation region of a transistor. For example, the semiconductor layer 406a corresponds to the oxide semiconductor layer 130b shown in the previous embodiment, and the semiconductor layer 406b corresponds to the oxide semiconductor layer 130c shown in the previous embodiment.

[0386] Note that the semiconductor layer 406a has regions 407a1 and 407b1 that do not overlap with the insulating layer 412, the conductive layer 414a, and the conductive layer 414b. Further, the semiconductor layer 406b has regions 407a2 and 407b2 that do not overlap with the insulating layer 412, the conductive layer 414a, and the conductive layer 414b. The regions 407a1 and 407b1 are regions with lower resistance than the regions of the semiconductor layer 406a that overlap with the insulating layer 412, the conductive layer 414a, and the conductive layer 414b. Also, the regions 407a2 and 407b2 are regions with lower resistance than the regions of the semiconductor layer 406b that overlap with the insulating layer 412, the conductive layer 414a, and the conductive layer 414b. Note that the region with lower resistance can also be referred to as a region with a high carrier density.

[0387] Also, the regions 407a1 and 407a2 are collectively referred to as the region 407a. Also, the regions 407b1 and 407b2 are collectively referred to as the region 407b. The regions 407a and 407b have functions as source regions and drain regions of a transistor.

[0388] The conductive layer 414a and the conductive layer 414b are collectively referred to as the conductive layer 414. The conductive layer 414 functions as the gate electrode of the transistor. Alternatively, the conductive layer 414 may have a function of shielding light from the channel formation region of the transistor or the like.

[0389] The insulating layer 412 functions as the gate insulating layer of the transistor.

[0390] The insulating layer 408 may have a function of suppressing impurities such as copper contained in the conductive layer 416a2 and the conductive layer 416b2 from mixing into the channel formation region of the transistor.

[0391] The insulating layer 418 may function as an interlayer insulating layer of the transistor, thereby reducing the parasitic capacitance between the wirings of the transistor.

[0392] The conductive layer 416a1 and the conductive layer 416a2 are collectively referred to as the conductive layer 416a. Also, the conductive layer 416b1 and the conductive layer 416b2 are collectively referred to as the conductive layer 416b. The conductive layer 416a and the conductive layer 416b function as the source electrode and the drain electrode of the transistor.

[0393] The insulating layer 428 may have a function of suppressing impurities from mixing into the channel formation region of the transistor.

[0394] Here, FIG. 44(B) shows the band structure in the P1-P2 cross section including the channel formation region of the transistor. Note that it is assumed that the energy gap of the semiconductor layer 406a is slightly smaller than that of the semiconductor layer 406b. Also, the insulating layer 402a, the insulating layer 402b, and the insulating layer 412 have an energy gap sufficiently larger than that of the semiconductor layer 406a and the semiconductor layer 406b. Do so. Also, the Fermi levels (denoted as Ef) of the semiconductor layer 406a, the semiconductor layer 406b, the insulating layer 402a, the insulating layer 402b, and the insulating layer 412 are set to the positions of their respective intrinsic Fermi levels (denoted as Ei). Also, the work functions of the conductive layer 404 and the conductive layer 414 are set to the same positions as the Fermi levels.

[0395] When the gate voltage is set to be equal to or higher than the threshold voltage of the transistor, due to the energy difference between the lower ends of the conduction bands between the semiconductor layer 406a and the semiconductor layer 406b, electrons preferentially flow through the semiconductor layer 406a. That is, it can be estimated that electrons are embedded in the semiconductor layer 406a. Note that the energy of the lower end of the conduction band is denoted as Ec, and the energy of the upper end of the valence band is denoted as Ev. .

[0396] Therefore, in the transistor according to one aspect of the present invention, the influence of interface scattering is reduced by the embedding of electrons. Therefore, the transistor according to one aspect of the present invention has a small channel resistance.

[0397] Next, FIG. 44(C) shows the band structure in the cross-section of Q1-Q2 including the source region or the drain region of the transistor. Note that the regions 407a1, 407b1, 407a 2, and 407b2 are in a degenerate state. Also, in the region 407b1, the Fermi level of the semiconductor layer 406a is set to be approximately the same as the energy of the lower end of the conduction band. Also, in the region 407b 2, the Fermi level of the semiconductor layer 406b is set to be approximately the same as the energy of the lower end of the conduction band. . The same applies to the regions 407a1 and 407a2.

[0398] At this time, the conductive layer 416b having the function of a source electrode or a drain electrode, and the region Since the energy barrier between 407b2 and [the relevant part] is small enough, an ohmic contact is formed. Also, the region between 407b2 and the region 407b1 forms an ohmic contact. Similarly, the conductive layer 416a having the function of a source electrode or a drain electrode and the region 407a2 form an ohmic contact because the energy barrier is small enough. Also, the region 407a2 and the region 407a 1 form an ohmic contact. Therefore, it can be seen that the transfer of electrons between the conductive layer 416a and the conductive layer 416b and the semiconductor layer 406a and the semiconductor layer 406b occurs smoothly.

[0399] As described above, the transistor according to one aspect of the present invention enables smooth transfer of electrons between the source electrode and the drain electrode and the channel formation region, has a low channel resistance, and has an extremely small off-current. That is, it can be seen that the transistor has excellent switching characteristics.

[0400] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0401] (Embodiment 10) In this embodiment, the effects of oxygen vacancies in the oxide semiconductor layer and hydrogen bonded to the oxygen vacancies will be described.

[0402] <(1). Formation and stability of VH o > When the oxide semiconductor film (hereinafter referred to as IGZO) is a perfect crystal, at room temperature, H preferentially diffuses along the ab plane. Also, during heat treatment at 450 °C, H diffuses in the ab plane and the c-axis direction, respectively. Therefore, here, in the presence of oxygen vacancies V o in IGZO​ Combination, H is oxygen deficiency V o It will be explained whether it is easy to enter or not. Here, oxygen deficiency V o Inside The state where there is H in is denoted as V o H

[0403] For the calculation, the InGaZnO4 crystal model shown in Fig. 45 was used. Here, V o The H in H V o comes out from and the activation barrier (E a ) of the reaction path where it combines with oxygen was calculated using the NEB (Nudg ed Elastic Band) method. The calculation conditions are shown in Table 1

[0404]

Table 1

[0405] Also, in the InGaZnO4 crystal model, due to the difference in the metal element to which the oxygen atom binds and its number , there are four types of oxygen atoms 1 to oxygen atom 4 as shown in Fig. 45. Here Oxygen deficiency V o Calculations were performed for oxygen atoms 1 and 2 that are likely to form

[0406] First, calculations were performed for oxygen atom 1 bonded to 3 In and 1 Zn

[0407] The model in the initial state is shown in Fig. 46(A), and the model in the final state is shown in Fig. 46(B). Also , in the initial state and the final state, the calculated activation barrier (E a ) is shown in Fig. 47. Note , the initial state here refers to the state where a hydrogen atom exists in the oxygen deficiency V o generated by the desorption of oxygen atom 1 (V H), and the final state refers to the state where a hydrogen atom moves from the oxygen deficiency V o and one o from It is in a state (H-O) where it is bonded to an oxygen atom bonded to Ga and two Zn atoms.

[0408] As a result of the calculation, for the hydrogen atom in the oxygen deficiency V o to move and bond with another oxygen atom, approximately 1.5 eV of energy is required, while for the hydrogen atom bonded to the oxygen atom to move into the oxygen deficiency V o it was found that approximately 0.46 eV of energy is required.

[0409] Here, from the activation barrier (E a ) obtained by the calculation and Equation 1, the reaction frequency (Γ) was calculated using Equation 1, where k B is the Boltzmann constant and T is the absolute temperature.

[0410]

Equation

[0411] Assuming a frequency factor ν = 10 13 [1 / sec], the reaction frequency at 350 °C was calculated. The frequency of hydrogen atoms moving from the model shown in Fig. 46(A) to the model shown in Fig. 46(B) was 5 .52×10 0 [1 / sec]. Also, the frequency of hydrogen atoms moving from the model shown in Fig. 46(B) to the model shown in Fig. 46( A) was 1.82×10 9 [1 / sec] . From this, it can be said that hydrogen atoms diffusing in IGZO are likely to form VH o and once VH o H is formed, it is difficult to desorb from the oxygen deficiency V o .

[0412] Next, calculations were performed for two oxygen atoms bonded to one Ga and two Zn atoms.

[0413] The model in the initial state is shown in Fig. 48(A), and the model in the final state is shown in Fig. 48(B). Also , in the initial state and the final state, the calculated activation barrier (E a ) is shown in Fig. 49. Note that , the initial state here refers to the state (V o H) where there is a hydrogen atom in the oxygen vacancy V generated by the desorption of oxygen atom 2 , and the final state refers to the state (H - O) where a hydrogen atom moves from the oxygen vacancy V o and binds to an oxygen atom that binds to one Ga o and two Zn.

[0414] As a result of the calculation, about 1.7 o 5 eV of energy is required for the hydrogen atom in the oxygen vacancy V to move and bind to another oxygen atom, whereas about 0.35 eV of energy is required for the hydrogen atom bound to an oxygen atom to move into the oxygen vacancy V o .

[0415] Also, from the activation barrier (E a ) obtained by the calculation and the above formula 1, the reaction frequency (Γ) was calculated .

[0416] Assuming the frequency factor ν = 10 13 [1 / sec], the reaction frequency at 350 °C was calculated. The frequency of the hydrogen atom moving from the model shown in Fig. 48(A) to the model shown in Fig. 48(B) was 7 .53 × 10 -2 [1 / sec]. Also, the frequency of the hydrogen atom moving from the model shown in Fig. 48(B) to the model shown in Fig. 48 (A) was 1.44 × 10 10 [1 / sec] . From this, it can be said that once V o H is formed, it is difficult for the hydrogen atom to desorb from the oxygen vacancy V o .

[0417] From the above, hydrogen atoms in IGZO are likely to diffuse during annealing, and oxygen vacancies V o exist In the case where there is an oxygen vacancy V o it was found that they are likely to be trapped in V o and become VH

[0418] <(2). V o H transition level> In IGZO, when there is an oxygen vacancy V o from the calculations using the above NEB method, hydrogen atoms are likely to form stable VH o . Therefore, to investigate whether VH o is involved in carrier trapping the transition level of VH o was calculated

[0419] An InGaZnO4 crystal model (112 atoms) was used for the calculation. For oxygen sites 1 and 2 shown in Fig. 45 VH models were created and the transition levels were calculated o . The calculation conditions are shown in Table 2

[0420]

Table 2

[0421] By adjusting the mixing ratio of the exchange term so that a band gap close to the experimental value is obtained, the band gap of the defect-free InGaZnO4 crystal model became 3.08 eV, which is close to the experimental value of 3.15 eV

[0422] The transition level (ε(q / q’)) of the model with defect D is calculated by the following equation 2 . Here, ΔE(D q ) is the formation energy at the charge q of defect D and is calculated from equation 3 .

[0423]

Number

[0424]

Number

[0425] In equations 2 and 3, E tot (D q ) is the total energy in the charge q of the model containing defect D, E (bulk) is the total energy of the defect-free model (perfect crystal), tot Δn is the increase or decrease number of atom i related to the defect, μ i is the chemical potential of atom i, ε i is the energy at the upper end of the valence band in the defect-free model, ΔV VBM is the correction term related to the electrostatic potential, E is the Fermi energy. q

[0426] F The calculated transition levels of V

[0426] o H are shown in Fig. 50. The numerical values in Fig. 50 are the depths from the lower end of the conduction band There are. From Fig. 50, the transition level of V o H for oxygen atom 1 exists 0.05 eV below the lower end of the conduction band in V, and the transition level of V o H for oxygen atom 2 exists 0.11 eV below the lower end of the conduction band Therefore, each V o H will be involved in the electron trap. That is, V o H has been shown to act as a donor. Also, IGZO with V o H has been shown to have conductivity It has become clear that it has.

[0427] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0428] (Embodiment 11)

[0429] An imaging device according to an aspect of the present invention and a semiconductor device including the imaging device can be used in a display device, a personal computer, an image playback device equipped with a recording medium (typically a device having a function of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying its image). In addition, as an electronic device in which an imaging device according to an aspect of the present invention and a semiconductor device including the imaging device can be used, there are a mobile phone, a game machine including a portable type, a portable data terminal, an e-book terminal, a video camera, a digital still camera, etc., a camera such as a digital still camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction machine, an automated teller machine (ATM) , a vending machine, and the like. Specific examples of these electronic devices are shown in FIG. 51. FIG. 51(A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit

[0430] 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, a camera 909, etc. Note that the portable game machine shown in FIG. 51(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this. The imaging device according to an aspect of the present invention can be used for the camera 909. FIG. 51(B) is a portable data terminal, which has a first housing 911, a display unit 912, a camera 919, etc.

[0431] ​​It has. Information can be input and output by the touch panel function of the display unit 912. It is possible. The imaging device of one aspect of the present invention can be used for the camera 919.

[0432] FIG. 51(C) is a digital camera, which has a housing 921, a shutter button 922, a microphone 9 23, a light emitting unit 927, a lens 925, etc. An imaging device of one aspect of the present invention can be provided at the position that becomes the focus of the lens 925. It is possible to provide an imaging device of one aspect of the present invention.

[0433] FIG. 51(D) is a wristwatch-type information terminal, which has a housing 931, a display unit 932, a list band 9 33, a camera 939, etc. The display unit 932 may be a touch panel. The imaging device of one aspect of the present invention can be used for the camera 939.

[0434] FIG. 51(E) is a video camera, which has a first housing 941, a second housing 942, a display unit 943, operation keys 944, a lens 945, a connection part 946, etc. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display unit 943 is provided on the second housing 942. And the first housing 941 and the second housing 942 are connected by the connection part 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. It is also possible to adopt a configuration in which the video on the display unit 943 is switched according to the angle between the first housing 941 and the second housing 94 2 at the connection part 946. An imaging device of one aspect of the present invention can be provided at the position that becomes the focus of the lens 945. It is possible to provide an imaging device of one aspect of the present invention.

[0435] FIG. 51(F) is a mobile phone, and the housing 951 has a display unit 952, a microphone 957, a speaker 954, a camera 959, an input / output terminal 956, operation buttons 955, etc. The camera The imaging device of one embodiment of the present invention can be used for 959.

[0436] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0437] (Embodiment 12) Here, modifications of the transistor described in the above embodiment will be described with reference to FIGS. The transistor shown in FIG. 52 is formed on an insulating layer 824 on a substrate 821. The oxide semiconductor layer 828 is connected to an insulating layer 837. and a conductive layer 840 which is in contact with the insulating layer 7 and overlaps with the oxide semiconductor layer 828. The conductive layer 837 functions as a gate insulating film. The conductive layer 840 functions as a gate electrode layer. It has the function of

[0438] In addition, the insulating layer 846 in contact with the oxide semiconductor layer 828 and the insulating layer The transistor is provided with an insulating layer 847. At the end, the conductive layers 856 and 857 in contact with the oxide semiconductor layer 828 are Note that the conductive layers 856 and 857 are formed as a source electrode layer and a drain electrode layer. It has the function of

[0439] Note that the conductive layer, the oxide semiconductor layer, and the insulating For the layer, those shown in the above embodiment can be used as appropriate.

[0440] In the transistor illustrated in FIG. 52A, the oxide semiconductor layer 828 overlaps with the conductive layer 840. and a region 828a formed in the region including the impurity element and sandwiching the region 828a. The conductive layers 856 and 857 have regions 828b and 828c. The region 828a functions as a channel region. The regions 828b and 828c are Regions 828b and 828c have a lower resistivity than region 828a. It functions as a rain area.

[0441] Alternatively, as in the transistor illustrated in FIG. 52B, The regions 828d and 828e in contact with the conductive layers 856 and 857 are not doped with impurity elements. In this case, the regions 828d and 828e in contact with the conductive layers 856 and 857 and the region 82 Between the region 828 and the region 828a, there are regions 828b and 828c having an impurity element. d and 828e become conductive when a voltage is applied to the conductive layers 856 and 857. It functions as a source region and a drain region.

[0442] In the transistor shown in FIG. 52B, after the conductive layers 856 and 857 are formed, An impurity element is added to the oxide semiconductor layer by using the conductive layers 856 and 857 as a mask. By doing so, it can be formed.

[0443] The conductive layer 840 may have a tapered end. The angle θ1 between the surface where the conductive layer 840 and the conductive layer 840 are in contact with each other is 90°. or 10° to 85° or 15° to 85° or 30° to 8 It may be 5° or less, or between 45° and 85°, or between 60° and 85°. This improves the coverage of the insulating layer 846 on the side surfaces of the insulating layer 837 and the conductive layer 840. It is possible to do so.

[0444] Next, a modified example of regions 828b and 828c will be described. Note that FIGS. 52(C) to 5 2(F) are enlarged views of the oxide semiconductor layer 828 shown in FIG. 52(A) and its vicinity. Here the channel length L is the interval between regions containing a pair of impurity elements.

[0445] As shown in FIG. 52(C), in the cross-sectional shape in the channel length direction, the boundaries of regions 828a and regions 828b, 828c coincide or substantially coincide with the ends of the conductive layer 840 via the insulating layer 837. That is, in the top surface shape, the boundaries of regions 828a and regions 828b, 82 8c coincide or substantially coincide with the ends of the conductive layer 840. Or, as shown in FIG. 52(D), in the cross-sectional shape in the channel length direction, region 828a

[0446] has a region that does not overlap with the ends of the conductive layer 840. This region functions as an offset region. The length of the offset region in the channel length direction is denoted as L off off off off When there are a plurality of offset regions, the length of one offset region is denoted as L off off off off The offset region is included in the channel region. Also, L is less than 20% of the channel length L,

[0447] or less than 10%, or less than 5%, or less than 2%. Or, as shown in FIG. 52(E), in the cross-sectional shape in the channel length direction, regions 828b ov ov ov ov ov ov 828c have a region that overlaps with the conductive layer 840 via the insulating layer 837. This region functions as an overlap region. The length of the overlap region in the channel length direction is denoted as L ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov ov [[ID=1 Less than 5% or less than 2%.

[0448] Or, as shown in FIG. 52(F), in the cross-sectional shape in the channel length direction, region 828a has region 828f between region 828b, and has region 82 8g between region 828a and region 828c. Regions 828f and 828g have a lower concentration of impurity elements than regions 828b and 828c and have a higher resistivity. Here, regions 828f and 828g overlap with the insulating layer 837 but may also overlap with the insulating layer 837 and the conductive layer 840.

[0449] In FIGS. 52(C) to 52(F), although the transistor shown in FIG. 52(A) has been described, in the transistor shown in FIG. 52(B) as well, the structure of FIGS. 52(C) to 52(F ) can be appropriately applied.

[0450] In the transistor shown in FIG. 53(A), the end of the insulating layer 837 is located outside the end of the conductive layer 840 . That is, the insulating layer 837 has a shape protruding from the conductive layer 840. Since it is possible to keep the insulating layer 846 away from region 828a , it is possible to suppress nitrogen, hydrogen, etc. contained in the insulating layer 846 from entering the region 828a that functions as the channel region .

[0451] In the transistor shown in FIG. 53(B), the insulating layer 837 and the conductive layer 840 are tapered , and the angles of the respective tapered portions are different. That is, the angle formed by the surface where the insulating layer 837 and the conductive layer 840 contact, the angle θ1 formed by the side surface of the conductive layer 840, the angle formed by the surface where the oxide semiconductor layer 828 and the insulating layer 837 contact, and the angle θ2 formed by the side surface of the insulating layer 837 are different. Angle θ2 is ​​​, less than 90°, or 30° or more and 85° or less, or 45° or more and 70° or less may be acceptable. For example, when the angle θ2 is smaller than the angle θ1, the coverage of the insulating layer 846 is enhanced. Also, when the angle θ2 is larger than the angle θ1, it is possible to move the insulating layer 846 away from the region 828a. Therefore, it is possible to suppress nitrogen, hydrogen, etc. contained in the insulating layer 846 from entering the region 828a that functions as a channel region.

[0452] Next, a modified example of the regions 828b and 828c will be described with reference to FIGS. 53(C) to 53(F). FIGS. 53(C) to 53(F) are enlarged views of the oxide semiconductor layer 828 shown in FIG. 53(A) and its vicinity.

[0453] As shown in FIG. 53(C), in the cross-sectional shape in the channel length direction, the boundaries of the regions 828a and the regions 828b and 828c coincide or substantially coincide with the end of the conductive layer 840 via the insulating layer 837. That is, in the top surface shape, the boundaries of the regions 828a and the regions 828b and 8 28c coincide or substantially coincide with the end of the conductive layer 840.

[0454] Alternatively, as shown in FIG. 53(D), in the cross-sectional shape in the channel length direction, the region 828a has a region that does not overlap with the conductive layer 840. This region functions as an offset region. That is, in the top surface shape, the ends of the regions 828b and 828c coincide or substantially coincide with the end of the insulating layer 837 and do not overlap with the end of the conductive layer 840.

[0455] Alternatively, as shown in FIG. 53(E), in the cross-sectional shape in the channel length direction, the regions 828b and 828c have a region that overlaps with the conductive layer 840 via the insulating layer 837. This region is an o ​​​is called an overlap region. That is, in the top surface shape, the ends of regions 828b and 828c overlap with the conductive layer 840.

[0456] Alternatively, as shown in FIG. 53(F), in the cross-sectional shape in the channel length direction, there is a region 828f between region 828a and region 828b, and a region 82 8g between region 828a and region 828c. Regions 828f and 828g have a lower concentration of impurity elements than regions 828b and 828c and a higher resistivity. Here, regions 828f and 828g overlap with the insulating layer 837 but may also overlap with the insulating layer 837 and the conductive layer 840.

[0457] Note that in FIGS. 53(C) to 53(F), although the transistor shown in FIG. 53(A) has been described, in the transistor shown in FIG. 53(B) as well, the structures of FIGS. 53(C) to 53(F ) can be appropriately applied.

[0458] The transistor shown in FIG. 54(A) has a laminated structure for the conductive layer 840 and has a conductive layer 840a in contact with the insulating layer 837 and a conductive layer 840b in contact with the conductive layer 840a. Also, the end of the conductive layer 840a is located outside the end of the conductive layer 840b. That is, the conductive layer 840 a has a shape that protrudes from the conductive layer 840b.

[0459] Next, a modified example of regions 828b and 828c will be described. Note that FIGS. 54(B) to 5 4(E) are enlarged views of the oxide semiconductor layer 828 shown in FIG. 54(A) and its vicinity.

[0460] As shown in FIG. 54(B), in the cross-sectional shape in the channel length direction, the boundaries of region 828a and regions 828b and 828c are the end of the conductive layer 840a included in the conductive layer 840 and the insulating Through layer 837, they match or substantially match. That is, in the top surface shape, region 828a and the boundaries of regions 828b and 828c match or substantially match with the ends of conductive layer 840 .

[0461] Or, as shown in FIG. 54(C), in the cross-sectional shape in the channel length direction, region 828a has a region that does not overlap with conductive layer 840. This region functions as an offset region . That is, in the top surface shape, the ends of regions 828b and 828c do not overlap with the ends of conductive layer 840 .

[0462] Or, as shown in FIG. 54(D), in the cross-sectional shape in the channel length direction, regions 828b , 828c have a region that overlaps with conductive layer 840, here conductive layer 840a. This region is referred to as an overlap region. That is, in the top surface shape, the ends of regions 828b and 828c overlap with conductive layer 840a

[0463] Or, as shown in FIG. 54(E), in the cross-sectional shape in the channel length direction, there is region 828f between region 828a and region 828b, and there is region 82 8g between region 828a and region 828c. Since impurity elements pass through conductive layer 840a and are added to regions 828f and 828g , the impurity element concentration in regions 828f and 828g is lower than that in regions 828b and 828c , and the resistivity is higher. Here, regions 828f and 828g overlap with conductive layer 840a , but they may also overlap with conductive layer 840a and conductive layer 840b

[0464] Note that the ends of insulating layer 837 may be located outside the ends of conductive layer 840a

[0465] Or, the side surface of insulating layer 837 may be curved

[0466] Alternatively, the insulating layer 837 may be in a tapered shape. That is, the angle formed by the surface where the oxide semiconductor layer 828 and the insulating layer 837 are in contact and the side surface of the insulating layer 837 may be less than 90°, preferably 3 0° or more and less than 90°.

[0467] As shown in FIG. 54(E), the oxide semiconductor layer 828 has regions 828f and 828g where the concentration of impurity elements is lower and the resistivity is higher than those in regions 828b and 828c, so that the electric field relaxation in the drain region is possible. Therefore, it is possible to reduce deterioration such as fluctuations in the threshold voltage of the transistor due to the electric field in the drain region.

[0468] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0469] (Embodiment 13) In this embodiment, an example of an image processing engine of an imaging device (image sensor) will be described with reference to FIG 55.

[0470] The imaging device includes an imaging unit 4000, an analog memory unit 4010, an image processing engine unit 4020, and an A / D conversion unit 4030. The imaging unit 4000 includes a plurality of pixels arranged in a matrix, a driver circuit 4001, and a readout circuit 4002. Each pixel is composed of a photodiode and a transistor. The analog memory unit 4010 includes a plurality of analog memories 4011. Here, each analog memory 4011 is configured to have memory cells equal to or more than the number of pixels in the imaging unit 40 00. That is, each analog memory ​​​​​​The memory 4011 can store one frame of the imaging data 4005 acquired by the imaging unit 4000. do.

[0471] The operation of the imaging device will be described below. In the first step, each pixel captures one frame. The first image data 4005 is acquired as the first image data. The first imaging data 4005 is read out. A so-called rolling shutter method may be used. A so-called global shutter method may be used in which the image data 4005 is sequentially read out by exposing the image data 4005 at once. .

[0472] By using the rolling shutter method, the image data 4005 of a certain row of pixels is read out. When the pixel is being illuminated, other rows of pixels can be exposed, allowing the frame rate of the image to be increased. In addition, by using the global shutter method, it is possible to capture images with a moving subject without any problems. Even if the object is not photographed, it is possible to obtain a captured image with little distortion.

[0473] In the second step, the first imaging data 4005 acquired by each pixel is read out and output to the read circuit 40. The image is stored in the first analog memory 4011 via the image sensor 402. The first image pickup data 4005 is stored as analog data in the first analog memory 4011. In other words, since analog-to-digital conversion processing is not required, It is easy to increase the frame frequency of imaging.

[0474] After that, the first step and the second step are repeated n times. However, in the nth repetition, In this case, the n-th image data 4005 acquired by each pixel is read out via a circuit 4002. The signal is stored in the nth analog memory 4011 .

[0475] As a third step, in the image processing engine unit 4020, using the first imaging data 4005 to the nth imaging data 4005 stored in the plurality of analog memories 4 011, perform desired image processing to obtain post-image processing imaging data 4025.

[0476] As a fourth step, in the A / D conversion unit 4030, perform analog-to-digital conversion on the post-image processing imaging data 4025 to obtain image data 4035.

[0477] As one of the above image processes, obtain post-image processing imaging data 4025 without out-of-focus blur from the plurality of imaging data 4005. In order to obtain the post-image processing imaging data 4025, calculate the sharpness of each imaging data 4005, and it is possible to obtain the imaging data 4005 with the highest sharpness as the post-image processing imaging data 4025. Also, from each imaging data 400 5, extract regions with high sharpness, connect them together, and it is possible to configure them as post-image processing imaging data 4 025. 5

[0478] Also, as a different one of the above image processes, obtain post-image processing imaging data 4025 with optimal brightness from the plurality of imaging data 4005. In order to obtain the post-image processing imaging data 4025, calculate the maximum brightness of each imaging data 4005, and obtain the post-image processing imaging data 4025 from the imaging data 4005 excluding the imaging data 4005 whose maximum brightness has reached the saturation value

[0479] Also, calculate the minimum brightness of each imaging data 4005, and obtain the post-image processing imaging data 4025 from the imaging data 4005 excluding the imaging data 4005 whose minimum brightness has reached the saturation value A configuration is possible.

[0480] In addition, in accordance with the lighting of the flash for imaging, when the above first step and second step are executed, imaging data 4005 corresponding to the timing at which the optimal light amount is irradiated can be obtained. In addition, in accordance with the lighting of the flash for imaging, when the above first step and second step are executed, imaging data 4005 corresponding to the timing at which the optimal light amount is irradiated can be obtained. A configuration is possible.

[0481] In addition, this embodiment can be appropriately combined with other embodiments shown in this specification. .

Explanation of Reference Numerals

[0482] 40 Silicon substrate 50 Transistor 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 58a Transistor 58b Transistor 58c Transistor 60 Photodiode 60a Photodiode 60b Photodiode 60c Photodiode 60p Light-receiving section 61 Anode 62 Cathode 63 Low-resistance region 64 Light control layer 66 Region 70 Conductor 71 Wiring layer 72 Wiring layer 73 Wiring layer 80 Insulating layer 81 Insulating layer 82 Insulating layer 83 Insulating layer 84 Insulating layer 85 Insulating layer 90 Pixel 91 Circuit 91a Region 91b Region 91c Region 92 Circuit 92a Region 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 115 Substrate 120 Insulating Layer 130 Oxide Semiconductor Layer 130a Oxide Semiconductor Layer 130A Oxide Semiconductor Film 130b Oxide Semiconductor Layer 130B Oxide Semiconductor Film 130c Oxide Semiconductor Layer 130C Oxide Semiconductor Film 140 Conductive Layer 141 Conductive Layer 142 Conductive Layer 150 Conductive Layer 151 Conductive Layer 152 Conductive Layer 156 Resist Mask 160 Insulating Layer 160A Insulating Film 170 Conductive Layer 171 Conductive Layer 171A Conductive Film 172 Conductive Layer 172A Conductive Film 173 Conductive Layer 175 Insulating Layer 180 Insulating Layer 190 Insulating Layer 231 Region 232 Region 233 Region 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 316 Wiring 317 Wiring 331 Region 332 Region 333 Region 334 Region 335 Region 400 Substrate 401 Insulating Layer 402 Insulating Layer 402a Insulating Layer 402b Insulating Layer 404 Conductive Layer 404a Conductive Layer 404b Conductive Layer 406 Semiconductor Layer 406a Semiconductor Layer 406b Semiconductor Layer 407a Region 407a1 Region 407a2 Region 407b Region 407b1 Region 407b2 Region 408 Insulating Layer 408a Insulating Layer 412 Insulating Layer 414 Conductive Layer 414a Conductive Layer 414b Conductive Layer 416a Conductive Layer 416a1 Conductive Layer 416a2 Conductive Layer 416b Conductive Layer 416b1 Conductive Layer 416b2 Conductive Layer 418 Insulating Layer 428 Insulating Layer 501 Signal 502 Signal 503 Signal 504 Signal 505 Signal 506 signal 507 signal 508 signal 509 signal 510 period 511 period 520 period 531 period 610 period 611 period 612 period 621 period 622 period 623 period 631 period 701 signal 702 signal 703 signal 704 signal 705 signal 821 substrate 824 insulating layer 828 oxide semiconductor layer 828a region 828b region 828c region 828d region 828e region 828f region 828g region 828h region 828i region 837 insulating layer 840 conductive layer 840a conductive layer 840b conductive layer 846 insulating layer 847 insulating layer 856 conductive layer 857 conductive layer 901 housing 902 housing 903 display unit 904 display unit 905 microphone 906 speaker 907 operation key 908 stylus 909 camera 911 housing 912 Display unit 919 Camera 921 Housing 922 Shutter button 923 Microphone 925 Lens 927 Light emitting unit 931 Housing 932 Display unit 933 List band 939 Camera 941 Housing 942 Housing 943 Display unit 944 Operation key 945 Lens 946 Connection part 951 Housing 952 Display unit 954 Speaker 955 Button 956 Input / output terminal 957 Microphone 959 Camera 1100 Layer 1200 Layer 1300 Layer 1400 Layer 1500 Insulating layer 1510 Light shielding layer 1520 Organic resin layer 1530 Color filter 1530a Color filter 1530b Color filter 1530c Color filter 1540 Microlens array 1550 Optical conversion layer 1600 Support substrate 1700 Pixel matrix 1730 Circuit 1740 Circuit 1750 Circuit 1760 Circuit 1770 Terminal 1800 Shift register 1810 Shift register 1900 Buffer circuit 1910 Buffer Circuit 2100 Analog Switch 2110 Vertical Output Line 2200 Output Line 4000 Imaging Unit 4002 Circuit 4005 Imaging Data 4010 Analog Memory Unit 4011 Analog Memory 4020 Image Processing Engine Unit 4025 Post-Image-Processing Imaging Data 4030 A / D Conversion Unit 4035 Image Data

Claims

[Claim 1] An imaging device having a first circuit and a second circuit, the first circuit includes a first transistor and a second transistor; the second circuit includes a third transistor and a photodiode; the first transistor is provided on a first surface of a silicon substrate; The photodiode is provided on the silicon substrate, the second transistor is disposed on the first transistor, the silicon substrate having a first insulating layer; the first insulating layer is provided to surround a side surface of the photodiode, the first transistor is a p-channel transistor, the first transistor has an active region in the silicon substrate; the second transistor and the third transistor are n-ch transistors, active layers of the second transistor and the third transistor include an oxide semiconductor; 2. An imaging device according to claim 1, wherein the light receiving surface of the photodiode is provided on a surface of the silicon substrate opposite to the first surface.

Images