Display device

Abstract

To provide a display device that can improve a yield.SOLUTION: A display device in one embodiment includes a first lower electrode, a rib including a plurality of first pixel openings overlapping with the first lower electrode, a partition wall, a plurality of first organic layers in contact with the first lower electrode through each of the first pixel openings and emitting light in accordance with the voltage application, and a plurality of first upper electrodes covering the first organic layers. The partition wall includes a lower part disposed over the rib, and an upper part having an end part projecting from the side surface of the lower part. The partition wall includes a plurality of first openings overlapping with the first pixel openings, and a first partition wall disposed between the first pixel openings.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies enabling improvement of the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of improving the yield.

Means for Solving the Problems

[0005] The display device according to one embodiment includes a first lower electrode, a rib having a plurality of first pixel openings overlapping the first lower electrode, a partition wall, a plurality of first organic layers that are in contact with the first lower electrode through the plurality of first pixel openings and emit light in response to the application of a voltage, and a plurality of first upper electrodes that respectively cover the plurality of first organic layers. The partition wall includes a lower portion disposed above the rib and an upper portion having an end portion protruding from a side surface of the lower portion. Further, the partition wall includes a plurality of first openings respectively overlapping the plurality of first pixel openings and a first partition wall disposed between the plurality of first pixel openings.

[0006] The display device according to one embodiment includes a first lower electrode, a rib having a first pixel opening overlapping the first lower electrode, a partition wall, a first organic layer that is in contact with the first lower electrode through the first pixel opening and emits light in response to the application of a voltage, and a first upper electrode that covers the first organic layer. The partition wall includes a lower portion disposed above the rib and an upper portion having an end portion protruding from a side surface of the lower portion. Further, the partition wall includes a first opening overlapping the first pixel opening and a first partition wall overlapping the first pixel opening and spaced apart from an edge portion of the first opening.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

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[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, components that exhibit the same or similar functions as those described above with respect to the previously shown drawings may be assigned the same reference numerals, and detailed descriptions that are repeated may be omitted as appropriate.

[0009] Note that in the drawings, for the purpose of facilitating understanding as necessary, the X-axis, Y-axis, and Z-axis that are perpendicular to each other are described. The direction along the X-axis is referred to as the X direction (second direction), the direction along the Y-axis is referred to as the Y direction (first direction), and the direction along the Z-axis is referred to as the Z direction. The Z direction is the normal direction of the plane including the X direction and the Y direction. Also, viewing various elements parallel to the Z direction is referred to as a plan view.

[0010] The display device according to each embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, and a wearable terminal.

[0011] [First Embodiment] FIG. 1 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a resin film having flexibility.

[0012] In the present embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, a case where the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3 is assumed. However, the pixel PX may include sub-pixels SP of other colors such as white, together with or instead of the sub-pixels SP1, SP2, and SP3.

[0014] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements constituted by, for example, thin film transistors.

[0015] In the display area DA, a plurality of scan lines GL for supplying a scan signal to the pixel circuit 1 of each sub-pixel SP, a plurality of signal lines SL for supplying a video signal to the pixel circuit 1 of each sub-pixel SP, and a plurality of power supply lines PL are arranged. In the example of FIG. 1, the scan lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0016] The gate electrode of the pixel switch 2 is connected to the scan line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the driving transistor 3 and the capacitor 4. The source electrode of the driving transistor 3 is connected to the power supply line PL and the capacitor 4. The drain electrode of the driving transistor 3 is connected to the display element DE.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] FIG. 2 is a schematic plan view showing an example of the layout of the sub-pixels SP1, SP2, and SP3 according to the first embodiment. In the example shown in FIG. 2, the sub-pixels SP2 and SP3 are arranged side by side with the sub-pixel SP1 in the X direction. Further, the sub-pixel SP2 and the sub-pixel SP3 are arranged side by side in the Y direction.

[0019] When the sub-pixels SP1, SP2, and SP3 have such a layout, in the display area DA, a column in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and a column in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed.

[0020] Note that the layout of the sub-pixels SP1, SP2, and SP3 and the sizes of the sub-pixels SP1, SP2, and SP3 are not limited to the example of FIG. 2. As another example, the sub-pixels SP1, SP2, and SP3 may be arranged side by side in the X direction. Also, at least two of the sub-pixels SP1, SP2, and SP3 may have the same size.

[0021] In the display area DA, ribs 5 are arranged. The ribs 5 each have pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3. The pixel opening AP1 includes pixel openings AP11 and AP12. The pixel openings AP11 and AP12 are each an example of a first pixel opening. The pixel opening AP2 is an example of a second pixel opening.

[0022] In the example of FIG. 2, the pixel openings AP11 and AP12 are arranged side by side in the Y direction. Also, the pixel opening AP11 is adjacent to the pixel opening AP3 in the X direction, and the pixel opening AP12 is adjacent to the pixel opening AP2 in the X direction.

[0023] In the example of FIG. 2, the area of the pixel opening AP11 is equal to the area of the pixel opening AP12. Also, the area of each of the pixel openings AP11 and AP12 is smaller than the area of the pixel opening AP2 and larger than the area of the pixel opening AP3. Furthermore, the total area of each of the pixel openings AP11 and AP12 (the total area of the pixel opening AP1) is larger than the pixel openings AP2 and AP3.

[0024] Note that the area of the pixel opening AP11 may be different from the area of the pixel opening AP12. Also, the area of each of the pixel openings AP11 and AP12 may be larger or smaller than the area of each of the pixel openings AP2 and AP3.

[0025] In the display area DA, a partition wall 6 is arranged. The partition wall 6 is located above the ribs 5 and entirely overlaps the ribs 5. In the example of FIG. 2, the partition wall 6 has the same planar shape as the ribs 5. That is, the partition wall 6 includes openings A1, A2, and A3 in the sub-pixels SP1, SP2, and SP3, respectively. The opening A1 includes openings A11 and A12. The openings A11, A12, A2, and A3 overlap the pixel openings AP11, AP12, AP2, and AP3, respectively. The openings A11 and A12 are each an example of a first opening. The opening A2 is an example of a second opening.

[0026] In the example of FIG. 2, the area of the opening A11 is equal to the area of the opening A12. Also, the area of each of the openings A11 and A12 is smaller than the area of the opening A2 and larger than the area of the opening A3. Further, the total area of each of the openings A11 and A12 (the total area of the opening A1) is larger than the openings A2 and A3.

[0027] Note that the area of the opening A11 may be different from the area of the opening A12. Also, the area of each of the openings A11 and A12 may be larger or smaller than the area of each of the openings A2 and A3.

[0028] The partition wall 6 includes a partition wall 6A (first partition wall) and a partition wall 6B (second partition wall). The partition wall 6A is disposed between the pixel openings AP11 and AP12. In the example of FIG. 2, the partition wall 6A is constituted by a first portion 6Aa extending in the X direction between the openings A11 and A12.

[0029] The partition wall 6B is disposed between the pixel openings AP1 and AP2. In the example of FIG. 2, the partition wall 6B is disposed between the pixel opening AP12 and the pixel opening AP2. The partition wall 6B extends in the Y direction and intersects the partition wall 6A. Note that, in the example of FIG. 2, the partition wall 6B is orthogonal to the first portion 6Aa of the partition wall 6A, but the present invention is not limited to this example.

[0030] The sub-pixel SP1 includes a lower electrode LE1 (first lower electrode), an upper electrode UE1 (first upper electrode), and an organic layer OR1 (first organic layer) that respectively overlap the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2 (second lower electrode), an upper electrode UE2 (second upper electrode), and an organic layer OR2 (second organic layer) that respectively overlap the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively overlap the pixel opening AP3.

[0031] The portions of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the sub-pixel SP1. The portions of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the sub-pixel SP2. The portions of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer described later.

[0032] The pixel circuits 1 (see FIG. 1) of the sub-pixels SP1, SP2, and SP3 are respectively disposed below the lower electrodes LE1, LE2, and LE3. The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3. In the example of FIG. 2, the contact holes CH1, CH2, and CH3 are entirely overlapped with the rib 5 and the partition wall 6, but this is not limited to this example.

[0033] FIG. 3 is a schematic cross-sectional view of the display device DSP along the line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuit 1, the scanning line GL, the signal line SL, and the power supply line PL shown in FIG. 1. The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film that planarizes the unevenness caused by the circuit layer 11.

[0034] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. Although not shown in the cross-section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit 1 of the circuit layer 11 through the contact holes CH1, CH2, and CH3 (see FIG. 2) provided in the organic insulating layer 12.

[0035] The partition wall 6 includes a lower portion 61 having conductivity disposed on the rib 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width larger than that of the lower portion 61. As a result, both end portions of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhang shape.

[0036] In the example of FIG. 3, the lower portion 61 has a bottom layer 63 disposed on the rib 5, and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Also, in the example of FIG. 3, both end portions of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0037] Also, in the example of FIG. 3, the upper portion 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the shaft layer 64. The second top layer 66 is disposed on the first top layer 65. The second top layer 66 may be formed thinner than the first top layer 65 as shown. Also, the second top layer 66 may have a width smaller than that of the first top layer 65. When the partition wall 6 has the configuration shown in FIG. 3, the openings A11, A12, A2, A3 shown in FIG. 2 correspond to regions surrounded by the end portions of the first top layer 65, respectively.

[0038] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrodes UE1, UE2, UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0039] The display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. The display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. The display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as an optical adjustment layer that improves the light extraction efficiency of the light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0040] In the following description, a multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is referred to as a stacked film FL1, a multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is referred to as a stacked film FL2, and a multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is referred to as a stacked film FL3.

[0041] A part of the stacked film FL1 is located above the upper part 62. The part is separated from a part of the stacked film FL1 that is located around the partition wall 6 (the part constituting the display element DE1). Similarly, a part of the stacked film FL2 is located above the upper part 62, and the part is separated from a part of the stacked film FL2 that is located around the partition wall 6 (the part constituting the display element DE2). Further, a part of the stacked film FL3 is located above the upper part 62, and the part is separated from a part of the stacked film FL3 that is located around the partition wall 6 (the part constituting the display element DE3).

[0042] Sealing layers SE11, SE12, and SE13 are respectively disposed in the sub-pixels SP1, SP2, and SP3. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the sub-pixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the sub-pixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the sub-pixel SP3.

[0043] In the example of FIG. 3, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE12 on the partition wall 6. Also, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE13 on the partition wall 6.

[0044] The sealing layers SE11, SE12, and SE13 are covered by a resin layer RS1. The resin layer RS1 is covered by a sealing layer SE2. The sealing layer SE2 is covered by a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are continuously provided at least over the entire display area DA, and a part thereof also extends to the peripheral area SA.

[0045] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0046] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The ribs 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the ribs 5 are formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as an epoxy resin or an acrylic resin.

[0047] The lower electrodes LE1, LE2, and LE3 have, for example, a reflective layer formed of silver and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0048] FIG. 4 is a diagram showing an example of a layer structure applicable to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer EML. In the present embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in the Z direction in this order. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of light-emitting layers EML.

[0049] The cap layers CP1, CP2, and CP3 have, for example, a laminated structure in which a plurality of transparent layers are stacked. These transparent layers may include a layer formed of an inorganic material and a layer formed of an organic material. Further, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13. The cap layers CP1, CP2, and CP3 each have a role as an optical adjustment layer for improving the light extraction efficiency of the light emitted by the organic layers OR1, OR2, and OR3. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0050] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of, for example, different metal materials from each other. As the metal material of the bottom layer 63, for example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used. Note that at least one of the bottom layer 63 and the shaft layer 64 may have a laminated structure of a plurality of layers. Further, the shaft layer 64 may include a layer formed of an insulating material.

[0051] For example, the first top layer 65 of the partition wall 6 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. As the metal material of the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. As the conductive oxide of the second top layer 66, for example, ITO or IZO can be used. Note that the upper portion 62 may have a single-layer structure formed of a specific material. Further, the upper portion 62 may include a layer formed of an insulating material.

[0052] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61, respectively. That is, the partition wall 6 serves as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3. Pixel voltages corresponding to the video signals of the signal line SL are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0053] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in the red wavelength range. As another example, the light-emitting layer EML of the organic layer OR2 may emit light in the red wavelength range, and the light-emitting layer EML of the organic layer OR3 may emit light in the green wavelength range.

[0054] As still another example, the light-emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (for example, white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer EML into light of colors corresponding to the sub-pixels SP1, SP2, and SP3. Further, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layer EML to generate light of colors corresponding to the sub-pixels SP1, SP2, and SP3.

[0055] FIG. 5 is a schematic plan view of the partition wall 6 shown in FIG. 2. Here, as shown in FIG. 5, the widths along the X direction and Y direction of the opening A11 are defined as widths W1x and W1y, respectively, and the widths along the X direction and Y direction of the opening A12 are defined as widths W2x and W2y, respectively. Further, the width along the Y direction of the first portion 6Aa is defined as width WAa, and the width along the X direction of the partition wall 6B is defined as width WB.

[0056] In the present embodiment, the width W1x is equal to the width W2x (W1x = W2x), and the width W1y is equal to the width W2y (W1y = W2y). That is, in the example of FIG. 5, the areas of the openings A11 and A12 are equal. Note that the magnitude relationship between the width W1x and the width W2x, and the magnitude relationship between the width W1y and the width W2y are not limited to this example. The width W1x may be different from the width W2x, or the width W1y may be different from the width W2y.

[0057] In the present embodiment, the total width (W1y + W2y + WAa) of the widths W1y, W2y, and WAa is larger than at least one of the widths W1x and W2x (both widths W1x and W2x in the example of FIG. 5). The width WAa is smaller than the width WB (WAa < WB).

[0058] FIG. 6 is a schematic cross-sectional view of the display device DSP taken along line IV-IV in FIG. 2. Note that the substrate 10, the circuit layer 11, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are not shown.

[0059] In the following description, the portion of the rib 5 that overlaps with the partition wall 6A is referred to as the rib 5A. The rib 5A is disposed on the lower electrode LE1. The first portion 6Aa is disposed on the rib 5A. The first portion 6Aa is disposed between the pixel opening AP11 and the pixel opening AP12. The partition wall 6A (the first portion 6Aa) is in an overhanging shape like the other portions of the partition wall 6. In the sub-pixel SP1, the laminated film FL1 is divided by the first portion 6Aa.

[0060] The two organic layers OR1 divided by the first part 6Aa are in contact with the lower electrode LE1 through the pixel apertures AP11 and AP12, respectively. The two upper electrodes UE1 divided by the first part 6Aa cover the two organic layers OR1, respectively. The two cap layers CP1 divided by the first part 6Aa cover the two upper electrodes UE1, respectively. A part of the stacked film FL1 is located on the upper part 62 of the partition wall 6A. The part is separated from the part of the stacked film FL1 located around the partition wall 6A (the part constituting the display element DE1). The sealing layer SE11 continuously covers the partition wall 6A and the cap layer CP1.

[0061] Here, some effects achieved by this embodiment will be described. In the manufacturing process of the display device DSP, the stacked film FL1 is formed by vapor deposition over the entire display area DA. Further, a sealing layer SE11 covering the stacked film FL1 is formed. Subsequently, patterning of these stacked film FL1 and sealing layer SE11 is performed. Specifically, the portions of the stacked film FL1 and the sealing layer SE11 disposed in the sub-pixel SP1 are left, and the portions disposed in the sub-pixels SP2 and SP3 are removed. Thereafter, the stacked film FL2 and the sealing layer SE12 are formed in the sub-pixel SP2 by the same procedure. Further, the stacked film FL3 and the sealing layer SE13 are also formed in the sub-pixel SP3 by the same procedure.

[0062] The stacked film FL1 formed by vapor deposition has weak adhesion to the lower electrode LE1 and may peel off during the manufacturing process of the display device DSP. Due to this peeling, the yield of the display device DSP may deteriorate.

[0063] The peeling of the stacked film FL1 is likely to occur in a region where the stacked film FL1 is continuously formed over a wide area. In this regard, in the display device DSP according to this embodiment, the opening A1 is divided into openings A11 and A12 by the first portion 6Aa of the partition wall 6A. As a result, the stacked film FL1 formed on the sub-pixel SP1 is divided by the first portion 6Aa. Therefore, compared with the case where the partition wall 6A is not provided, the range in which the stacked film FL1 is continuously formed in the sub-pixel SP1 becomes smaller, and the stacked film FL1 is less likely to peel off. Accordingly, the yield of the display device DSP can be improved.

[0064] In this embodiment, the area of the opening A1 (the total area of the openings A11 and A12) is larger than the areas of the openings A2 and A3. Therefore, among the openings A1, A2, and A3, the peeling is likely to occur at the opening A1. Therefore, by dividing the opening A1 by the partition wall 6A, it is possible to effectively suppress the risk of the peeling. However, the present invention is not limited to this example, and at least one of the openings A2 and A3 may also be divided by a partition wall. Thereby, the effect of suppressing the peeling is further improved.

[0065] Also, in this embodiment, the width WAa of the first portion 6Aa that divides the stacked film FL1 is smaller than the width WB of the partition wall 6B disposed between the pixel opening AP1 and the pixel opening AP2. As the width WAa of the first portion 6Aa increases, the width of the rib 5A also increases, so that the pixel opening AP1 becomes smaller and the aperture ratio of the sub-pixel SP1 decreases. Therefore, by reducing the width WAa of the first portion 6Aa, it is possible to suppress a decrease in the aperture ratio of the sub-pixel SP1.

[0066] Note that, in this embodiment, the lower electrode LE1 and the opening A1 have a shape that is long in the Y direction. Also, the first portion 6Aa extends in the X direction. Further, the opening A1 is divided by the first portion 6Aa such that the openings A11 and A12 are arranged in the Y direction. The present invention is not limited to this example, and the first portion 6Aa may extend in the Y direction. That is, the opening A1 may be divided by the first portion 6Aa such that the openings A11 and A12 are arranged in the X direction.

[0067] Also, in this embodiment, although the opening A1 is divided into two by the partition wall 6A, it may be divided into three or more. In this case, the opening may be divided by a plurality of partition walls parallel to each other, or may be divided by partition walls intersecting each other as described later.

[0068] FIG. 7 is a schematic plan view showing another example of the layout of the sub-pixels SP1, SP2, and SP3 according to the first embodiment. The same or similar elements as those of the above-described display device DSP are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate.

[0069] The pixel opening AP1 includes pixel openings AP11, AP12, AP13, and AP14. In the example of FIG. 7, the pixel openings AP11 and AP13 are arranged in the X direction, the pixel openings AP12 and AP14 are arranged in the X direction, the pixel openings AP11 and AP12 are arranged in the Y direction, and the pixel openings AP13 and AP14 are arranged in the Y direction. Also, in the example of FIG. 7, the areas of the pixel openings AP11, AP12, AP13, and AP14 are equal. Note that the areas of the pixel openings AP11, AP12, AP13, and AP14 may be different.

[0070] The opening A1 includes openings A11, A12, A13, and A14. The openings A11, A12, A13, and A14 overlap the pixel openings AP11, AP12, AP13, and AP14, respectively. Also, in the example of FIG. 7, the areas of the openings A11, A12, A13, and A14 are equal. Note that the areas of the openings A11, A12, A13, and A14 may be different.

[0071] The partition wall 6A has a first portion 6Aa as in the example of FIG. 2. The first portion 6Aa is disposed between the pixel opening AP11 and the pixel opening AP12, and between the pixel opening AP13 and the pixel opening AP14. The partition wall 6A further has a second portion 6Ab. The second portion 6Ab is disposed between the pixel opening AP11 and the pixel opening AP13, and between the pixel opening AP12 and the pixel opening AP14. In the example of FIG. 7, the first portion 6Aa extends in the X direction. Also, the second portion 6Ab extends in the Y direction and intersects the first portion 6Aa.

[0072] Figure 8 is a schematic plan view of the partition wall 6 shown in Figure 7. Here, as shown in Figure 8, the width along the X direction of the second portion 6Ab is defined as width WAb. In the example of Figure 8, the width WAb is smaller than the width WB (WAb < WB). Similar to the width WAa of the first portion 6Aa, by making the width WAb of the second portion 6Ab smaller, it is possible to suppress a decrease in the aperture ratio of the sub-pixel SP1.

[0073] In the examples of Figures 7 and 8, the aperture A1 is divided into four by the first portion 6Aa and the second portion 6Ab. That is, since the number of divided apertures is larger than that in the example of Figure 2, the laminated film FL1 formed on the sub-pixel SP1 in the manufacturing process of the display device DSP becomes even more difficult to peel off. Note that the configuration of the partition wall 6A shown in Figures 7 and 8 can also be applied to the sub-pixels SP2 and SP3.

[0074] [Second Embodiment] Figure 9 is a schematic plan view showing an example of the layout of the sub-pixels SP1, SP2, and SP3 according to the second embodiment. The same or similar elements as those in the display device DSP according to the first embodiment are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate.

[0075] In the present embodiment, the rib 5 includes an island-shaped rib 5A spaced apart from the edge E1 of the pixel aperture AP1. The rib 5A is disposed on the lower electrode LE1. The partition wall 6 overlaps the pixel aperture AP1 and includes an island-shaped partition wall 6A spaced apart from the edge E2 of the aperture A1. The partition wall 6A is disposed on the rib 5A. The rib 5A and the partition wall 6A have a shape in which the corners of the rectangular shape in plan view are formed in a round shape. Note that each corner of the rib 5A and the partition wall 6A may be formed at a right angle. Also, the rib 5A and the partition wall 6A may be formed in a circular shape or an elliptical shape. In the example of Figure 9, the area of the aperture A1 is larger than the area of the aperture A2. The pixel aperture AP1 is an example of a first pixel aperture. The aperture A1 is an example of a first aperture. The partition wall 6A is an example of a first partition wall.

[0076] FIG. 10 is a schematic plan view of the partition wall 6 shown in FIG. 9. Here, as shown in FIG. 10, of the edge E2 of the opening A1, two sides E2y arranged parallel to the Y direction and sandwiching the partition wall 6A are defined as distances Dx1 and Dx2 from the center O of the partition wall 6A, respectively. Also, of the edge E2 of the opening A1, two sides E2x arranged parallel to the X direction and sandwiching the partition wall 6A are defined as distances Dy1 and Dy2 from the center O of the partition wall 6A, respectively. Further, the widths of the partition wall 6A along the X direction and the Y direction are defined as widths WAx and WAy, respectively.

[0077] In this embodiment, the distance Dx1 is equal to the distance Dx2 (Dx1 = Dx2), and the distance Dy1 is equal to the distance Dy2 (Dy1 = Dy2). That is, the partition wall 6A is arranged at the center of the opening A11 in the X direction and the Y direction. Note that the present invention is not limited to the above example, and the partition wall 6A may be arranged at a position deviated from the center of the opening A11. The sum of the distance Dy1 and the distance Dy2 is larger than the sum of the distance Dx1 and the distance Dx2 (Dy1 + Dy2 > Dx1 + Dx2). The widths WAx and WAy are smaller than the width WB (WAx, WAy < WB).

[0078] Also in the second embodiment, similar to the first embodiment, peeling of the laminated film can be suppressed, and the yield of the display device DSP can be improved.

[0079] Further, in the second embodiment, by separating the partition wall 6A from the edge of the opening A1, it is possible to increase the aperture ratio of the sub-pixel SP1 compared to the first embodiment.

[0080] FIG. 11 is a schematic plan view showing another example of the layout of the sub-pixels SP1, SP2, and SP3 according to the second embodiment. The rib 5 includes a plurality of ribs 5A. The partition wall 6 includes a plurality of partition walls 6A. In the example of FIG. 11, the rib 5 and the partition wall 6 each include three ribs 5A and partition walls 6A. Note that the number of each of the plurality of ribs 5A and the plurality of partition walls 6A is not limited to three, and may be two or four or more.

[0081] In the example of FIG. 11, the plurality of ribs 5A and the plurality of partition walls 6A are arranged along the Y direction. Note that the plurality of ribs 5A and the plurality of partition walls 6A may be arranged along the X direction, or may not be arranged along each of the X direction and the Y direction.

[0082] FIG. 12 is a schematic plan view of the partition wall 6 shown in FIG. 11. Among the three partition walls 6A arranged along the Y direction, the distances between the centers O of the adjacent partition walls 6A along the Y direction are defined as distances D1 and D2, respectively. In the present embodiment, the distance D1 is equal to the distance D2 (D1 = D2). That is, the plurality of partition walls 6A are arranged at equal intervals along the Y direction.

[0083] Also in the present embodiment, similar to the above-described embodiment, peeling of the laminated film can be suppressed, and the yield of the display device DSP can be improved. Further, in the present embodiment, the plurality of partition walls 6A are arranged along the direction (Y direction) in which the opening A1 extends in a long shape. As a result, the partition walls 6A are appropriately dispersed in the opening A1, and the effect of suppressing the peeling is improved.

[0084] Based on the display devices disclosed in the above embodiments, all display devices that can be appropriately designed and modified by those skilled in the art also belong to the scope of the present invention as long as they include the gist of the present invention.

[0085] Within the scope of the idea of the present invention, those skilled in the art can conceive various modifications, and those modifications are also understood to belong to the scope of the present invention. For example, those obtained by appropriately adding, deleting, or modifying components, or adding, omitting, or changing conditions in the above-described embodiments by those skilled in the art also belong to the scope of the present invention as long as they have the gist of the present invention.

[0086] In addition, with regard to other operational effects brought about by the aspects described in the above embodiments, those that are obvious from the description of this specification or can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0087] DSP... indicates a device, DA... indicates a region, SA... indicates a peripheral region, PX... indicates a pixel, SP1, SP2, SP3... indicate sub-pixels, LE1, LE2, LE3... indicate lower electrodes, OR1, OR2, OR3... indicate organic layers, UE1, UE2, UE3... indicate upper electrodes, SE11, SE12, SE13... indicate sealing layers, 5, 5A... indicate ribs, 6, 6A, 6B... indicate partition walls, 61... indicates a lower part, 62... indicates an upper part, 6Aa... indicates a first part, 6Ab... indicates a second part.

Claims

1. a first lower electrode; a rib having a plurality of first pixel openings overlapping the first lower electrode; a partition wall including a lower portion disposed above the rib and an upper portion having an end protruding from a side surface of the lower portion; a plurality of first organic layers each contacting the first lower electrode through one of the plurality of first pixel openings and emitting light in response to an applied voltage; a plurality of first upper electrodes each covering one of the plurality of first organic layers; comprising; wherein the partition wall includes a plurality of first openings respectively overlapping the plurality of first pixel openings; a first partition wall disposed between the plurality of first pixel openings; a display device.

2. the first lower electrode has a shape elongated in a first direction; two of the plurality of first openings are arranged in the first direction; the first partition wall has a first portion extending in a second direction intersecting the first direction between the two first openings; The display device according to claim 1.

3. a total width along the first direction of the two first openings and the first portion is greater than a width along the second direction of at least one of the two first openings; The display device according to claim 2.

4. further, a second lower electrode adjacent to the first lower electrode in the second direction; a second organic layer emitting light of a color different from that of the first organic layer in response to an applied voltage; a second upper electrode covering the second organic layer; the rib has a second pixel opening overlapping the second lower electrode; the second organic layer contacts the second lower electrode through the second pixel opening; wherein the partition wall further includes a second opening overlapping the second pixel opening; a second partition wall disposed between the first pixel opening and the second pixel opening; including; The display device according to claim 2.

5. a width along the first direction of the first portion is smaller than a width along the second direction of the second partition wall; The display device according to claim 4.

6. the first portion is orthogonal to the second partition wall; The display device according to claim 4.

7. an area of the first opening is smaller than an area of the second opening; The display device according to claim 4.

8. a total area of the plurality of first openings is greater than an area of the second opening; The display device according to claim 4.

9. two of the plurality of first openings are arranged in the second direction; the first partition wall has a second portion disposed between the two first openings arranged in the second direction; the second portion intersects the first portion; The display device according to claim 2.

10. a first lower electrode; A rib having a first pixel opening overlapping the first lower electrode, A partition wall including a lower portion disposed above the rib and an upper portion having an end protruding from a side surface of the lower portion, A first organic layer that contacts the first lower electrode through the first pixel opening and emits light in response to an applied voltage, A first upper electrode covering the first organic layer, Comprising, The partition wall, A first opening overlapping the first pixel opening, A first partition wall overlapping the first pixel opening and spaced apart from an edge of the first opening, A display device including.

11. The width of the first opening along the first direction is larger than the width of the first opening along a second direction intersecting the first direction, The first partition wall is disposed at the center of the first opening in the first direction, The display device according to claim 10.

12. The first partition wall is disposed at the center of the first opening in the second direction, The display device according to claim 11.

13. Furthermore, a second lower electrode adjacent to the first lower electrode, A second organic layer that emits light of a color different from that of the first organic layer in response to an applied voltage, A second upper electrode covering the second organic layer, The rib has a second pixel opening overlapping the second lower electrode, The second organic layer contacts the second lower electrode through the second pixel opening, The partition wall further, A second opening overlapping the second pixel opening, A second partition wall disposed between the first pixel opening and the second pixel opening, Including, The display device according to claim 10.

14. The width of the first partition wall is smaller than the width of the second partition wall, The display device according to claim 13.

15. The area of the first opening is larger than the area of the second opening, The display device according to claim 13.

16. The partition wall includes a plurality of the first partition walls, The display device according to claim 10.

17. The width of the first opening along the first direction is larger than the width of the first opening along a second direction intersecting the first direction, The plurality of first partition walls are arranged side by side along the first direction, The display device according to claim 16.

18. The plurality of first partition walls are arranged at equal intervals, The display device according to claim 17.

19. The first organic layer includes a light-emitting layer that emits blue light, The display device according to claim 1 or 10.

20. The first organic layer includes a light-emitting layer that emits blue light, The second organic layer includes a light-emitting layer that emits green or red light, The display device according to claim 4 or 13.

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