Display device and manufacturing method for display device

Abstract

To provide a display device and a manufacturing method for a display device.SOLUTION: A display device in an embodiment includes a pixel circuit layer including a base layer and a pixel circuit disposed thereon, and a light-emitting element layer disposed on the pixel circuit layer and including a light-emitting element, a pixel defining layer, a capping layer, and a wire electrically connected to the pixel circuit. The light-emitting element includes an anode electrode, a cathode electrode, and a light-emitting part, at least a part of which is disposed between the anode electrode and the cathode electrode. The pixel defining layer covers at least a part of the anode electrode. At least a part of the capping layer is in contact with the pixel defining layer. The wire is disposed on the pixel defining layer and includes a first wire and a second wire that are separated from each other, each forming a closed loop. The first wire surrounds a subpixel region in a plan view and the second wire surrounds the first wire in the plan view. The light-emitting part is disposed in a region surrounded by the first wire.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device.

Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has been increasing. A display device can include a light-emitting element, and sub-pixels adjacent to each other can be formed using the light-emitting element.

[0003] As the demand for high-quality display devices increases, the structure of sub-pixels has been miniaturized, and a structure in which leakage current does not occur between sub-pixels is required.

[0004] In addition, in order to improve the reliability of electrical signals supplied to sub-pixels, it is necessary to reduce the risk of voltage drop due to an increase in resistance in a conductive structure to which the electrical signals are supplied.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] One aspect of the present disclosure is to provide a display device and a method of manufacturing the display device in which the risk of voltage drop with respect to a cathode electrode is reduced.

[0007] One aspect of the present disclosure is to provide a display device and a method of manufacturing the display device in which the risk of leakage current is reduced.

[0008] One aspect of the present disclosure is to provide a display device having excellent display quality capable of providing a high-resolution image and a method of manufacturing the display device.

[0009] One aspect of the present disclosure is to provide a display device and a method of manufacturing the display device with improved convenience in the manufacturing process.

Means for Solving the Problems

[0010] The display device according to an embodiment of the present disclosure may include a sub-pixel region. The display device may include a pixel circuit layer including a base layer and a pixel circuit disposed on the base layer, and a light-emitting element layer disposed on the pixel circuit layer and electrically connected to the pixel circuit, the light-emitting element layer including a light-emitting element, a pixel defining layer, a capping layer, and wirings. The light-emitting element may include an anode electrode, a cathode electrode, and a light-emitting portion at least partially disposed between the anode electrodes. The pixel defining layer may cover at least a part of the anode electrode. At least a part of the capping layer may be in contact with the pixel defining layer. The wirings may include a first wiring and a second wiring spaced apart from each other and disposed on the pixel defining layer and forming a closed loop respectively. The first wiring may surround the sub-pixel region in plan view, and the second wiring may surround the first wiring in plan view. The light-emitting portion may be disposed within a region surrounded by the first wiring.

[0011] According to an embodiment, the wiring may include a conductive material having an electrical conductivity smaller than 4.0×10 7 (S / m) at 20°C.

[0012] According to an embodiment, the wiring may include aluminum (Al) or molybdenum (Mo).

[0013] According to an embodiment, the first wiring and the second wiring may include the same material as each other and may be respectively disposed on one surface of the pixel defining layer.

[0014] According to an embodiment, the first wiring may be disposed in a peripheral portion of the sub-pixel region. The second wiring may be disposed in a peripheral portion of the first wiring. The sub-pixel region may include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first wiring may include a first wiring portion surrounding the first sub-pixel region, a second wiring portion surrounding the second sub-pixel region, and a third wiring portion surrounding the third sub-pixel region.

[0015] According to an embodiment, the cathode electrode may include a first cathode electrode overlapping with the first sub-pixel region, a second cathode electrode overlapping with the second sub-pixel region, and a third cathode electrode overlapping with the third sub-pixel region. The first cathode electrode, the second cathode electrode, and the third cathode electrode may be physically separated from each other.

[0016] According to an embodiment, the pixel circuit layer may include a first power line and a second power line having different potentials from each other. The first power line may be electrically connected to the pixel circuit. The second power line may be electrically connected to the cathode electrode via the first wiring.

[0017] According to an embodiment, the display device may include a display region and a non-display region surrounding at least a part of the display region. At least a part of the first wiring may be electrically connected to the second power line via a contact portion penetrating the pixel defining layer. The second power line may have a thickness thicker than that of the cathode electrode. The contact portion may be disposed within the display region.

[0018] According to an embodiment, the capping layer may include a first capping layer and a second capping layer on the first capping layer. The first capping layer may cover the first wiring and may not cover the second wiring. The second capping layer may cover the second wiring.

[0019] According to the embodiment, the second capping layer and the pixel defining layer may each contain an inorganic material, and may be in contact with each other in a region adjacent to the second wiring.

[0020] The display device according to an embodiment of the present disclosure may include a display region, a non-display region surrounding at least a part of the display region, a base layer, a pixel circuit and a power line disposed on the base layer, and a pixel circuit layer including a via layer covering the power line, and a light emitting element layer disposed on the pixel circuit layer and electrically connected to the pixel circuit, including a light emitting element, a pixel defining layer, and a wiring. The light emitting element may include an anode electrode, a cathode electrode, and a light emitting portion at least a part of which is disposed between the anode electrodes. The pixel defining layer may overlap the anode electrode in plan view. The wiring may be directly disposed on the pixel defining layer and include a first wiring and a second wiring spaced apart from each other. The power line may be disposed across the display region and the non-display region. The cathode electrode and the power line may be electrically connected in the display region via a contact member penetrating the via layer. The power line may have a thickness thicker than that of the cathode electrode.

[0021] The manufacturing method of a display device according to an embodiment of the present disclosure may include a step of manufacturing a pixel circuit layer and a step of manufacturing a light-emitting element layer including a light-emitting element disposed on the pixel circuit layer. The step of manufacturing the light-emitting element layer may include a step of forming an anode electrode, a pixel defining layer, and wirings on the pixel circuit layer, and a step of patterning a layer for defining sub-pixels. The wirings may be disposed on the pixel defining layer and include a first wiring and a second wiring spaced apart from each other, and the first wiring may be closer to the anode electrode than the second wiring. The patterning step may include a step of forming a base light-emitting portion, a step of removing at least a part of a layer adjacent to the first wiring (the layer adjacent to the first wiring includes the base light-emitting portion) by supplying a first voltage to the first wiring, a step of forming a base cathode electrode and a first base capping layer, and a step of removing at least a part of a layer adjacent to the second wiring (the layer adjacent to the second wiring includes the base light-emitting portion, the base cathode electrode, and the first base capping layer) by supplying a second voltage to the second wiring.

[0022] According to an embodiment, the pixel circuit layer may include a pixel circuit, a first power supply line electrically connected to the pixel circuit, and a second power supply line having a potential different from that of the first power supply line. The step of forming the wirings may include a step of electrically connecting the first wiring and the second power supply line.

[0023] According to an embodiment, the step of forming the base light-emitting portion may include a step of entirely depositing the base light-emitting portion on the pixel circuit layer.

[0024] According to an embodiment, the step of removing at least a part of the layer adjacent to the first wiring may include a step of providing a first light-emitting portion disposed within a region surrounded by the first wiring.

[0025] According to an embodiment, the step of forming the base cathode electrode may include a step of electrically connecting the base cathode electrode and the first wiring, and a step of the base cathode electrode contacting the pixel defining layer in a region adjacent to the first wiring.

[0026] According to an embodiment, the step of removing at least a part of the layer adjacent to the first wiring may include a step of forming a first opening exposing at least a part of the pixel defining layer. The step of removing at least a part of the layer adjacent to the second wiring may include a step of forming a second opening exposing at least a part of the pixel defining layer.

[0027] According to an embodiment, the manufacturing method may further include a step of forming a second base capping layer, and a step of removing at least a part of the layer formed on the outer periphery of the second wiring (the layer formed on the outer periphery of the second wiring includes the base light emitting portion, the base cathode electrode, and the first base capping layer).

[0028] According to an embodiment, the second base capping layer may contact the pixel defining layer in a region adjacent to the second wiring. The second base capping layer and the pixel defining layer may each include an inorganic material.

[0029] According to an embodiment, the manufacturing method may further include a step of entirely depositing a sealing layer on the pixel circuit layer.

Effects of the Invention

[0030] According to an embodiment of the present disclosure, it is possible to provide a display device with a reduced risk of voltage drop with respect to a cathode electrode and a method of manufacturing the display device.

[0031] According to an embodiment of the present disclosure, it is possible to provide a display device with a reduced risk of leakage current and a method of manufacturing the display device.

[0032] According to an embodiment of the present disclosure, a display device having excellent display quality capable of providing a high-resolution image and a method of manufacturing the display device can be provided.

[0033] According to an embodiment of the present disclosure, a display device with improved convenience in the manufacturing process and a method of manufacturing the display device can be provided.

Brief Description of the Drawings

[0034]

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Mode for Carrying Out the Invention

[0035] Since the present disclosure can be modified in various ways and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present disclosure to a specific disclosed form, and it should be understood that it includes all modifications, equivalents, and alternatives included in the spirit and technical scope of the present disclosure.

[0036] Terms such as "first", "second", etc. may be used to describe various components, but the above components should not be limited by the above terms. The above terms are used only for the purpose of distinguishing one component from another. For example, within the scope not departing from the scope of the present disclosure, the first component may be referred to as the second component, and similarly the second component may be referred to as the first component. Singular expressions include plural expressions unless the context clearly has a different meaning.

[0037] In the present disclosure, terms such as "including" or "having" are intended to specify that there are features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and it should be understood that the existence or addition possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof are not precluded in advance. Also, when a part such as a layer, film, region, plate, etc. is "on" another part, it includes not only the case where it is directly on the other part, but also the case where there are other parts in between. Note that in this specification, when a part such as a certain layer, film, region, plate, etc. is formed "on" another part, the forming direction is not limited to the upper direction only, and those formed in the side or lower direction are also included. Conversely, when a part such as a layer, film, region, plate, etc. is "under" another part, it includes not only the case where it is directly under the other part, but also the case where there are other parts in between.

[0038] The present disclosure relates to a display device and a method for manufacturing a display device. Hereinafter, a display device and a method for manufacturing a display device according to an embodiment will be described with reference to the accompanying drawings.

[0039] FIG. 1 is a schematic plan view showing a display device according to an embodiment.

[0040] Referring to FIG. 1, the display device DD may include a base layer BSL and pixels PXL disposed on the base layer BSL. Although not shown in the figure, the display device DD may further include a drive circuit unit (for example, a scan drive unit and a data drive unit), wirings, and pads for driving the pixels PXL.

[0041] The display device DD (or the base layer BSL) may include a display area DA and a non-display area NDA. The non-display area NDA can mean an area other than the display area DA. The non-display area NDA can surround at least a part of the display area DA.

[0042] The base layer BSL can form the base surface of the display device DD. The base layer BSL may be a rigid or flexible substrate or film. For example, the base layer BSL may include a glass material. Or, the base layer BSL may include a silicon material. Or, the base layer BSL may include polyimide, but the present disclosure is not limited thereto.

[0043] The display area DA can mean an area where pixels PXL are arranged. The non-display area NDA can mean an area where no pixels PXL are arranged. In the non-display area NDA, a drive circuit section, wiring, and pads connected to the pixels PXL in the display area DA may be arranged.

[0044] According to an embodiment, the pixel PXL (or sub-pixel SPX) may be arranged according to a stripe or PENTILE TM ) array structure or the like, but is not limited thereto, and various embodiments may be applied to the present disclosure.

[0045] According to an embodiment, the pixel PXL (or sub-pixel SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may each be a sub-pixel of one pixel PXL. At least one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can form one pixel unit that can emit lights of various colors.

[0046] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can emit light of one color.

[0047] For example, the first sub-pixel SPX1 may be a red pixel that emits red (e.g., the first color) light, the second sub-pixel SPX2 may be a green pixel that emits green (e.g., the second color) light, and the third sub-pixel SPX3 may be a blue pixel that emits blue (e.g., the third color) light. The red pixel can provide light in a wavelength band of 600 nm to 750 nm. The green pixel can provide light in a wavelength band of 480 nm to 560 nm. The blue pixel can provide light in a wavelength band of 370 nm to 460 nm.

[0048] According to an embodiment, the number of the second sub-pixels SPX2 may be larger than the number of the first sub-pixels SPX1 and the number of the third sub-pixels SPX3. However, the color, type, and / or number of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 that constitute each pixel unit are not limited to specific examples.

[0049] FIG. 2 is a schematic plan view showing a display area according to an embodiment. In FIG. 2, for convenience of explanation, a structure in which the first to third sub-pixels SPX1 to SPX3 are sequentially arranged in the first direction DR1 is shown. However, the present disclosure is not limited thereto.

[0050] Referring to FIG. 2, the display device DD may further include a wiring L arranged adjacent to the sub-pixel SPX.

[0051] According to an embodiment, the sub-pixel SPX can form a sub-pixel region SPXA. The sub-pixel region SPXA may be a region where light of one color is visible. For example, the sub-pixel region SPXA may include a first sub-pixel region SPXA1 in which the first sub-pixel SPX1 is formed and the first color light is provided, a second sub-pixel region SPXA2 in which the second sub-pixel SPX2 is formed and the second color light is provided, and a third sub-pixel region SPXA3 in which the third sub-pixel SPX3 is formed and the third color light is provided.

[0052] The wiring L may include wiring L corresponding to each of the sub-pixels SPX. For example, the wiring L may include a first wiring portion surrounding the first sub-pixel region SPXA1, a second wiring portion surrounding the second sub-pixel region SPXA2, and a third wiring portion surrounding the third sub-pixel region SPXA3. The shape of the wiring L may be determined according to the shape of each sub-pixel SPX. For example, the shape of the wiring L can correspond to the shape of the edge of the sub-pixel region SPXA.

[0053] The wiring L may include a first wiring L1 and a second wiring L2. The first wiring L1 and the second wiring L2 may be separated from each other, and in a plan view, they may not overlap with each other. The first wiring L1 and the second wiring L2 may be physically separated from each other. The first wiring L1 and the second wiring L2 may be electrically separated from each other.

[0054] The first wiring L1 may be disposed in the peripheral portion of the sub-pixel region SPXA. The first wiring L1 may be disposed between the sub-pixel region SPXA and the second wiring L2. The first wiring L1 can form a closed loop and can surround the sub-pixel region SPXA1 in a plan view.

[0055] The second wiring L2 may be disposed in the peripheral portion of the first wiring L1. The second wiring L2 may be disposed on the outer contour of the closed loop formed by the first wiring L1. The second wiring L2 can form a closed loop and can surround the first wiring L1 in a plan view.

[0056] According to an embodiment, the first wiring L1 and the second wiring L2 may be formed in the same process. Thereby, the first wiring L1 and the second wiring L2 can include the same material and can be disposed in the same layer. The first wiring L1 and the second wiring L2 may be disposed on the same layer (for example, the pixel defining layer PDL (see FIG. 3)). The first wiring L1 and the second wiring L2 may be respectively disposed on one surface of the pixel defining layer PDL.

[0057] Hereinafter, with reference to FIGS. 3 to 8, a display device DD including the wiring L will be described.

[0058] FIGS. 3 and 4 are schematic cross-sectional views showing a display device according to an embodiment. FIGS. 3 and 4 schematically show a display area DA including first to third sub-pixel areas SPXA1 to SPXA3. FIGS. 3 and 4 are schematic cross-sectional views taken along line A - A' of FIG. 2. FIG. 5 is a schematic block diagram showing a connection structure for a sub-pixel including a light-emitting element according to an embodiment. For example, FIG. 5 may show an electrical connection structure including a pixel circuit PXC corresponding to each of the sub-pixels SPX. FIG. 6 is a schematic cross-sectional view showing a light-emitting element and a capping layer according to an embodiment. FIG. 7 is a schematic block diagram showing an electrical path to which a cathode signal is supplied according to an embodiment. For example, FIG. 7 may schematically show the positional relationship of components and the electrical connection relationship between the components based on the display area DA and the non-display area NDA. FIG. 8 is a schematic cross-sectional view for explaining the thickness relationship between a second power line and a cathode electrode according to an embodiment.

[0059] Referring to FIGS. 3 and 4, the display device DD may include a pixel circuit layer PCL and a light-emitting element layer LEL.

[0060] The pixel circuit layer PCL may include a base layer BSL, a pixel circuit PXC, a first power line PL1, a second power line PL2, and a via layer VIA.

[0061] The base layer BSL can form a base on which a pixel circuit PXC configured to drive the light-emitting element LD, a first power line PL1, and a second power line PL2 are arranged. The pixel circuit PXC may be arranged on the base layer BSL and may be configured to drive the light-emitting element LD. The pixel circuit layer PCL may include a conductive layer and an insulating layer, and the conductive layer can form the pixel circuit PXC, the first power line PL1, and the second power line PL2. The pixel circuit PXC may be included in the corresponding sub-pixel SPX.

[0062] The pixel circuit PXC may include one or more circuit elements. For example, the pixel circuit PXC may include three transistors and a storage capacitor. For example, the pixel circuit PXC may include a driving transistor, a switching transistor, and a storage capacitor, but the present disclosure is not necessarily limited thereto.

[0063] The pixel circuit PXC may include a first pixel circuit PXC1 configured to drive a first sub-pixel SPX1 and electrically connected to a light-emitting element LD of the first sub-pixel SPX1, a second pixel circuit PXC2 configured to drive a second sub-pixel SPX2 and electrically connected to a light-emitting element LD of the second sub-pixel SPX2, and a third pixel circuit PXC3 configured to drive a third sub-pixel SPX3 and electrically connected to a light-emitting element LD of the third sub-pixel SPX3.

[0064] On the other hand, referring to FIG. 5, the pixel circuit PXC may be electrically connected to a scanning line SL and a data line DL. The scanning line SL can supply a scanning signal to the pixel circuit PXC and may be electrically connected to the gate electrode of the switching transistor of the pixel circuit PXC according to the embodiment. The light-emitting element LD can be configured to emit light corresponding to a data signal provided from the data line DL.

[0065] The pixel circuit PXC may be electrically connected to a first power line PL1 and a second power line PL2. For example, the anode electrode AE of the light-emitting element LD may be electrically connected to the pixel circuit PXC and the first power line PL1, and the cathode electrode CE of the light-emitting element LD may be electrically connected to the second power line PL2. The first power line PL1 and the second power line PL2 may be disposed on the base layer BSL.

[0066] The power supply of the first power line PL1 and the power supply of the second power line PL2 can have different potentials. For example, the power supply of the first power line PL1 may be a high-potential pixel power supply supplied with power from the first voltage potential VDD, and the power supply of the second power line PL2 may be a low-potential pixel power supply supplied with power from the second voltage potential VSS. The potential difference between the power supply of the first power line PL1 and the power supply of the second power line PL2 can be set to be equal to or higher than the threshold voltage of the light-emitting element LD.

[0067] The first power line PL1 may be electrically connected to a pixel circuit PXC (for example, a driving transistor). The second power line PL2 may be electrically connected to the cathode electrode CE of the light-emitting element LD.

[0068] Each light-emitting element LD can be connected in the forward direction between the first power line PL1 and the second power line PL2 to form each effective light source. The effective light sources can be aggregated to form the light-emitting elements LD of the sub-pixel SPX.

[0069] The light-emitting element LD can emit light with a luminance corresponding to the driving current supplied through the pixel circuit PXC. During each frame period, the pixel circuit PXC can supply a driving current corresponding to the data signal to the light-emitting element LD. The light-emitting element LD can emit light with a luminance corresponding to the current flowing through it.

[0070] The first power line PL1 and the second power line PL2 may be patterned on the base layer BSL. According to an embodiment, the first power line PL1 may be patterned within the sub-pixel region SPXA and the region adjacent thereto. The second power line PL2 may be patterned within the sub-pixel region SPXA and the region adjacent thereto. For convenience of explanation, the first and second power lines PL1 and PL2 corresponding to each of the first to third sub-pixels SPX1 to SPX3 are shown separately, but according to an embodiment, the first power lines PL1 corresponding to each of the first to third sub-pixels SPX1 to SPX3 may be connected to each other or may be integrally formed. The second power lines PL2 corresponding to each of the first to third sub-pixels SPX1 to SPX3 may be connected to each other or may be integrally formed.

[0071] According to an embodiment, the first power line PL1 and the second power line PL2 may include a conductive material. For example, the first power line PL1 and the second power line PL2 may include one or more of the group consisting of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt), but the present disclosure is not limited thereto.

[0072] The first power line PL1 may be electrically connected to the pixel circuit PXC. The second power line PL2 may be electrically connected to the first wiring L1.

[0073] The via layer VIA can form an upper structure of the pixel circuit layer PCL. The via layer VIA may be a planarization layer. The via layer VIA can cover the pixel circuit PXC, the first power line PL1, and the second power line PL2.

[0074] At least a part of the contact member CNP that electrically connects the second power line PL2 and the cathode electrode CE may be formed in the via layer VIA. At least a part of the contact portion CNT that electrically connects the pixel circuit PXC and the anode electrode AE may be formed in the via layer VIA.

[0075] The via layer VIA may contain an organic material. For example, the organic material may include one or more of the group consisting of acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin, but the present disclosure is not limited thereto.

[0076] The light-emitting element layer LEL may be disposed on the pixel circuit layer PCL. According to an embodiment, the light-emitting element layer LEL may include a light-emitting element LD, a pixel defining layer PDL, a capping layer CPL, a wiring L, and a sealing layer TFE. According to an embodiment (see FIG. 4), the light-emitting element layer LEL may further include a void VO.

[0077] The light-emitting element LD may include an organic light-emitting diode (OLED) containing an organic material, but the present disclosure is not limited thereto. According to an embodiment, the light-emitting element LD may be a quantum dot light-emitting element containing an inorganic material.

[0078] Referring also to FIG. 6, the light-emitting element LD may include an anode electrode AE, a light-emitting portion EL, and a cathode electrode CE. The light-emitting element LD may include a first light-emitting element LD1 for forming a first sub-pixel SPX1, a second light-emitting element LD2 for forming a second sub-pixel SPX2, and a third light-emitting element LD3 for forming a third sub-pixel SPX3.

[0079] According to an embodiment, the first to third light-emitting elements LD1 to LD3 can emit light of different colors. For example, the first light-emitting element LD1 can emit light of a first color. The second light-emitting element LD2 can emit light of a second color. The third light-emitting element LD3 can emit light of a third color.

[0080] The anode electrode AE may be disposed on the pixel circuit layer PCL (e.g., via layer VIA). The anode electrode AE may be electrically connected to the pixel circuit PXC through the contact portion CNT. The anode electrode AE may include a first anode electrode AE1 electrically connected to the first pixel circuit PXC1, a second anode electrode AE2 electrically connected to the second pixel circuit PXC2, and a third anode electrode AE3 electrically connected to the third pixel circuit PXC3.

[0081] The anode electrode AE may include various conductive materials. For example, the anode electrode AE may include a transparent conductive material. For example, the anode electrode AE may include at least one of transparent conductive substances such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). The anode electrode AE may include an opaque conductive material capable of reflecting light. For example, the anode electrode AE may include one or more of the group of titanium nitride (TiN), silver (Ag), and aluminum (Al).

[0082] The light emitting portion EL may be disposed on the anode electrode AE. The light emitting portion EL may include a first light emitting portion EL1 disposed on the first anode electrode AE1 to form a first sub-pixel SPX1, a second light emitting portion EL2 disposed on the second anode electrode AE2 to form a second sub-pixel SPX2, and a third light emitting portion EL3 disposed on the third anode electrode AE3 to form a third sub-pixel SPX3.

[0083] The light-emitting part EL may include a multilayer structure. The light-emitting part EL may include a light-emitting layer EML configured to generate light, an electron transport part ETU configured to transport electrons, a hole transport part HTU configured to transport holes, and the like. The light-emitting layer EL may include various organic materials, and according to an embodiment, may further include inorganic substances such as metal-containing compounds or quantum dots.

[0084] The hole transport part HTU may include a multilayer structure having a plurality of layers each including different materials. For example, the hole transport part HTU may include at least one of a hole injection layer and a hole transport layer, and according to an embodiment, may further include a light-emission assisting layer, an electron blocking layer, and the like.

[0085] The hole injection layer may be a layer that performs or improves the function of injecting holes from the anode electrode AE to another adjacent organic layer. The hole transport layer may be a layer that provides the provided holes to the light-emitting layer EML. The light-emission assisting layer may be a layer that compensates for the resonance distance based on the wavelength of the light provided by the light-emitting layer EML. The electron blocking layer may be a layer that can prevent the injection of electrons from the electron transport part ETU and reduce the number of carriers (e.g., holes or electrons) that leave the light-emitting layer EML. For example, the hole transport part HTU may have a multilayer (laminated) structure such as a hole injection layer / hole transport layer, a hole injection layer / hole transport layer / light-emission assisting layer, a hole injection layer / light-emission assisting layer, a hole transport layer / light-emission assisting layer, an electron blocking layer / hole injection layer / hole transport layer, a hole transport layer having different materials arranged in sequence, or a hole injection layer / hole transport layer / electron blocking layer. However, the present disclosure is not limited thereto.

[0086] According to an embodiment, the hole transport part HTU may include various hole-transporting organic materials, but the present disclosure is not particularly limited.

[0087] The light-emitting layer EML may be disposed between the hole transport unit HTU and the electron transport unit ETU. The light-emitting layer EML may include a material capable of emitting light of one color. The light-emitting layer EML may include a host and a dopant. The host of the light-emitting layer EML is a luminescent substance capable of capturing carriers (electrons and holes) for light generation and can be induced to efficiently generate excitons. The dopant may include a phosphorescent dopant or a fluorescent dopant. According to an embodiment, the exemplification of the dopant is not particularly limited. Depending on the embodiment, the dopant may include an organic material and may include a metal complex or the like.

[0088] The electron transport unit ETU may include a multilayer structure having a plurality of layers each including different materials. The electron transport unit ETU can include at least one of an electron injection layer and an electron transport layer, and according to an embodiment, may further include an electron buffer layer, a hole blocking layer, and the like.

[0089] The electron injection layer may be a layer that performs or improves the electron injection function from the cathode electrode CE to an adjacent other organic layer. The electron transport layer may be a layer that provides the provided electrons to the light-emitting layer EML. The hole blocking layer may be a layer that can prevent hole injection from the hole transport unit HTU and reduce the number of carriers departing from the light-emitting layer EML.

[0090] For example, the electron transport unit ETU can have a multilayer structure such as an electron transport layer / electron injection layer, a hole blocking layer / electron transport layer / electron injection layer, an electron adjustment layer / electron transport layer / electron injection layer, or a buffer layer / electron transport layer / electron injection layer, but the present disclosure is not limited thereto.

[0091] According to an embodiment, the electron transport unit ETU may include various electron transporting compounds. For example, the electron transport unit ETU may include a metal-free organic material, and may include a metal-containing organic material or various metal materials (such as alkaline earth metals and / or rare earth metals, etc.), but the present disclosure is not limited thereto.

[0092] The cathode electrode CE is disposed on the light-emitting portion EL, and at least a part of the cathode electrode CE may be disposed on the pixel defining layer PDL. According to an embodiment, the cathode electrode CE may be disposed in a region adjacent to the first wiring L1. The cathode electrode CE may cover the first wiring L1 and may not cover the second wiring L2. The cathode electrode CE may overlap the first wiring L1 in a plan view and may not overlap the second wiring L2. According to an embodiment, the cathode electrode CE can be in contact with the first wiring L1. According to an embodiment, the cathode electrode CE may not be in contact with the second wiring L2.

[0093] The cathode electrode CE can be in contact with the pixel defining layer PDL in a region adjacent to the first wiring L1. According to an embodiment, joule heating is formed by the first wiring L1, and the layer adjacent to the first wiring L1 can be removed, and then the cathode electrode CE can be formed, so that in the region adjacent to the first wiring L1, the exposed pixel defining layer PDL and the cathode electrode CE can be directly adjacent to each other.

[0094] The cathode electrode CE may be electrically connected to the first wiring L1. The first wiring L1 is electrically connected to the second power line PL2 through the contact portion CNP, and the cathode electrode CE can receive the supply of the cathode voltage through the first wiring L1. According to an embodiment, the contact portion CNP can penetrate the pixel defining layer PDL and the via layer VIA, and can also penetrate the insulating layer on the second power line PL2 according to the embodiment.

[0095] According to an embodiment, the cathode electrodes CE for the respective sub-pixels SPX may be separated from each other. The cathode electrode CE may include a first cathode electrode CE1 included in the first sub-pixel SPX1 and electrically connected to the first light-emitting unit EL1, a second cathode electrode CE2 included in the second sub-pixel SPX2 and electrically connected to the second light-emitting unit EL2, and a third cathode electrode CE3 included in the third sub-pixel SPX3 and electrically connected to the third light-emitting unit EL3. According to an embodiment, the first to third cathode electrodes CE1 to CE3 may be physically separated from each other.

[0096] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit the light emitted from the light-emitting unit EL. The cathode electrode CE may be formed of a metal material or a transparent conductive material so as to have a relatively thin thickness. In an embodiment, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In another embodiment, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof, but the material of the cathode electrode CE is not limited thereto.

[0097] In each of the sub-pixels SPX, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE are transported into the light-emitting unit EL to form excitons, and when the excitons transition from the excited state to the ground state, light can be generated. The luminance of the light may be determined according to the amount of current flowing through the light-emitting unit EL. The wavelength range of the generated light may be determined according to the configuration of the light-emitting unit EL.

[0098] On the other hand, since the cathode electrode CE has a relatively thin thickness, it can have a relatively high resistance. Experimentally, when a voltage is applied through a conductive structure with high resistance, a voltage drop risk may occur, and it may be difficult to supply the intended electrical signal to the light-emitting device LD.

[0099] Referring to FIGS. 7 and 8 together, the electrical path to which the cathode voltage is supplied according to the embodiment can be defined (defined) so that the risk of voltage drop is reduced.

[0100] According to the embodiment, the cathode voltage may be supplied substantially through the second power line PL2 having a large thickness, and may be electrically connected to the cathode electrode CE through the contact member CNP in a region adjacent to the target cathode electrode CE to which the cathode voltage is supplied.

[0101] The second power line PL2 can have a power thickness T_PL. The cathode electrode CE can have a cathode thickness T_CE. According to the embodiment, the cathode thickness T_CE may be thinner than the power thickness T_PL. For example, the power thickness T-PL may be in the range of 2000 Å to 9000 Å. The cathode thickness T_CE may be in the range of 50 Å to 200 Å, but the present disclosure is not limited thereto. According to the embodiment, since the cathode thickness T_CE may be thinner than the power thickness T_PL, the cathode electrode CE can have a larger resistance than the second power line PL2.

[0102] The second power line PL2 may be electrically connected to the second voltage potential VSS in the non-display region NDA. The second power line PL2 may be electrically connected to the cathode electrode CE in the display region DA. The first cathode electrode CE1 may be electrically connected to a part (for example, the first part) of the second power line PL2 through the contact portion CNP, and the second cathode electrode CE2 may be electrically connected to another part (for example, the second part) of the second power line PL2 through the contact portion CNP, and the third cathode electrode CE3 may be electrically connected to still another part (for example, the third part) of the second power line PL2 through the contact portion CNP. The contact portion CNP can be disposed within the display region DA. The contact portion CNP may overlap the cathode electrode CE in plan view and may not overlap the second power line PL2.

[0103] Therefore, as described above, the path through which the cathode voltage is applied can be defined substantially by the second power line PL2 having a relatively small resistance, and the path through which the cathode voltage is applied can be defined as a small portion in the cathode electrode CE having a relatively large resistance. Eventually, the risk of voltage drop with respect to the cathode voltage can be substantially reduced.

[0104] The pixel defining layer PDL can cover at least a part of the anode electrode AE. The pixel defining layer PDL may at least partially overlap with the anode electrode AE in a plan view. The pixel defining layer PDL can form an opening, and the anode electrode AE can be exposed through the opening.

[0105] The pixel defining layer PDL can form a base on which the wiring L is arranged. For example, the pixel defining layer PDL can be in contact with the wiring L.

[0106] The pixel defining layer PDL may contain an inorganic material. For example, the pixel defining layer PDL may contain silicon oxide (SiOx) and silicon nitride (SiNx), but the present disclosure is not limited thereto.

[0107] The pixel defining layer PDL may include a multilayer (laminated) structure. For example, the pixel defining layer PDL may include a multilayer structure in which silicon oxide (SiOx) and silicon nitride (SiNx) are alternately arranged.

[0108] The capping layer CPL may be arranged on the light emitting element LD (for example, the cathode electrode CE). The capping layer CPL can passivate the first to third light emitting elements LD1 to LD3.

[0109] The capping layer CPL may include a first capping layer CPL1 and a second capping layer CPL2. The first capping layer CPL1 and the second capping layer CPL2 may include an inorganic material. For example, the first capping layer CPL1 and the second capping layer CPL2 may independently include one or more of the group consisting of silicon nitride (SiNx), aluminum nitride (AlNx), titanium nitride (TiNx), silicon oxide (SiOx), aluminum oxide (AlxOy), titanium oxide (TiOx), silicon oxycarbide (SiOxCy), and silicon oxynitride (SiOxNy). However, the present disclosure is not limited thereto.

[0110] The first capping layer CPL1 may be disposed on each of the first to third light-emitting elements LD1 to LD3. The first capping layer CPL1 can passivate each of the first to third light-emitting elements LD1 to LD3 during the process of sequentially manufacturing the first to third light-emitting elements LD1 to LD3, and can reduce the risk of defects occurring during manufacturing. The first capping layer CPL1 can cover the first wiring L1 and may not cover the second wiring L2. The first capping layer CPL1 may overlap the first wiring L1 in a plan view and may not overlap the second wiring L2.

[0111] The second capping layer CPL2 may be disposed on each of the first to third light-emitting elements LD1 to LD3, and may also be disposed on the outer contours of each of the first to third light-emitting elements LD1 to LD3. The second capping layer CPL2 can cover the first wiring L1 and can cover the second wiring L2. According to an embodiment, the second capping layer CPL2 may be directly adjacent to the second wiring L2. The second capping layer CPL2 can cover the side surfaces of the light-emitting portion EL, the cathode electrode CE, and the first capping layer CPL1.

[0112] The second capping layer CPL2 can encapsulate the light-emitting element LD to reduce risks such as moisture. The second capping layer CPL2 can physically contact the pixel definition layer PDL in the region adjacent to the second wiring L2. When Joule heat is formed through the second wiring L2, the layer adjacent to the second wiring L2 can be removed, and then the second capping layer CPL2 can be formed. As a result, in the region adjacent to the second wiring L2, the exposed pixel definition layer PDL and the second capping layer CPL2 can be directly adjacent to each other.

[0113] As described above, the second capping layer CPL2 may contain an inorganic material, and the pixel definition layer PDL may also contain an inorganic material. Therefore, since the inorganic materials can be directly adjacent to each other, an inorganic encapsulation structure can be formed in the peripheral portion of the light-emitting element LD. The inorganic encapsulation structure can prevent the problem of moisture permeability (issue) that may occur in the light-emitting element LD, so the lifespan and element characteristics of the light-emitting element LD can be improved.

[0114] The wiring L may be disposed on the pixel definition layer PDL. According to an embodiment, the wiring L can be directly adjacent to the pixel definition layer PDL. Each of the first wiring L1 and the second wiring L2 may be disposed adjacent to the first to third sub-pixel regions SPXA1 to SPXA3.

[0115] The wiring L may be a resistive conductive structure for forming Joule heat. According to an embodiment, when a pulse voltage is supplied to the wiring L, heat can be applied to the region adjacent to the wiring L. The applied heat can remove at least a part of the layer (for example, a layer containing an organic material) disposed in the peripheral portion of the wiring L. According to an embodiment, by adjusting the magnitude of the voltage supplied to the wiring L and the time during which the voltage is supplied, the amount of the layer disposed in the peripheral portion removed can be determined.

[0116] According to an embodiment, the wiring L may contain a conductive material having a certain resistance. The wiring L may contain a metal material suitable for forming Joule heat. For example, the wiring L has a resistance of 4.0×10 at 20°C 7It may include a conductive material having an electrical conductivity smaller than (S / m) (siemens per meter). Therefore, the wiring L can have characteristics suitable for forming Joule heat. For example, the wiring L may include aluminum (Al), and the wiring L may include molybdenum (Mo). According to an embodiment, based on the intensity of the voltage supplied to the wiring L and the supply time of the voltage, the range in which the Joule heat diffuses can be adjusted. Therefore, even when the structure of the display device DD (for example, the sub-pixel SPX) is miniaturized, a display device DD having a high-resolution display quality can be provided.

[0117] Since the wiring L can form Joule heat during the manufacturing process of the display device DD, the wiring L can expose the pixel defining layer PDL in the region adjacent to the wiring L. A cathode electrode CE may be disposed on the first wiring L1. A second capping layer CPL2 may be disposed on the second wiring L2.

[0118] As described above, since the first wiring L1 can form a closed-loop structure, the light-emitting portion EL may be disposed within the region surrounded by the first wiring L1 and may include an edge inside the first wiring L1. Also, since the second wiring L2 can form a closed-loop structure, the light-emitting element LD may be disposed within the region surrounded by the second wiring L2 and may include an edge inside the second wiring L2.

[0119] The first wiring L1 may include a first-1 wiring portion L1-1 and a first-2 wiring portion L1-2. The second wiring L2 may include a second-1 wiring portion L2-1 and a second-2 wiring portion L2-2. The first-1 wiring portion L1-1 is disposed on the first side of the light-emitting portion EL and may be disposed between the second-1 wiring portion L2-1 and the light-emitting portion EL. The first-2 wiring portion L1-2 is disposed on the second side of the light-emitting portion EL and may be disposed between the second-2 wiring portion L2-2 and the light-emitting portion EL.

[0120] According to an embodiment (see FIG. 4), voids VO may be further formed in a region adjacent to the second wiring L2. The voids VO may be disposed between the first wiring L1 and the second wiring L2. The voids VO may be formed directly on the pixel defining layer PDL. The voids VO may be surrounded by a layer formed in the same process as the cathode electrode CE, the first capping layer CPL1, and the light emitting portion EL. The voids VO may be voids.

[0121] The encapsulation layer TFE may be disposed on the light emitting element LD and the capping layer CPL. The encapsulation layer TFE can remove a step formed by the light emitting element LD. The encapsulation layer TFE can form an outer layer of the light emitting element layer LEL.

[0122] The encapsulation layer TFE may include a multilayer structure. For example, the encapsulation layer TFE may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. According to an embodiment, the first encapsulation layer TFE1 may include an inorganic material, the second encapsulation layer TFE2 may include an organic material, and the third encapsulation layer TFE3 may include an inorganic material, but the present disclosure is not limited thereto.

[0123] With reference to FIGS. 9 to 25, a method for manufacturing the display device DD according to an embodiment will be described. Contents overlapping with the above description will be briefly described or not refuted.

[0124] FIG. 9 is a flowchart showing a method for manufacturing a display device according to an embodiment. FIG. 10 is a flowchart showing a step of manufacturing a light emitting element layer according to an embodiment. FIG. 11 is a flowchart showing a step of patterning sub-pixels.

[0125] Figs. 12 to 25 are schematic cross-sectional views at different process stages showing a method for manufacturing a display device according to an embodiment. For convenience of explanation, Figs. 12, 13, 24, and 25 show a cross-sectional structure based on Fig. 3 (for example, a cross-sectional structure of a part of the display area DA), and Figs. 14 to 23 show a cross-sectional structure with reference to the first sub-pixel SPX1 among the sub-pixels SPX. According to the embodiment, Figs. 19, 21, and 23 show embodiments in which the display device DD described above with reference to Fig. 4 includes voids VO.

[0126] Referring to Fig. 9, a method for manufacturing a display device according to an embodiment may include a step S100 of manufacturing a pixel circuit layer and a step S200 of manufacturing a light-emitting element layer.

[0127] Referring to Fig. 10, the step S200 of manufacturing a light-emitting element layer may include a step S220 of forming an anode electrode, a pixel defining layer, and wirings, a step S240 of patterning a layer for defining (defining) a first sub-pixel, a step S260 of patterning a layer for defining (defining) a second sub-pixel, a step S280 of patterning a layer for defining (defining) a third sub-pixel, and a step S290 of forming a sealing layer.

[0128] Referring to Fig. 11, the step S240 of patterning a layer for defining a first sub-pixel may include a step S2410 of forming a base light-emitting portion, a step S2420 of removing at least a part of a layer adjacent to the first wiring, a step S2430 of forming a base cathode electrode and a first base capping layer, a step S2440 of removing at least a part of a layer adjacent to the second wiring, a step S2450 of forming a second base capping layer, and a step S2460 of removing at least a part of a layer disposed on the outer contour of the second wiring.

[0129] Referring to Figs. 9 and 12, in the step S100 of manufacturing a pixel circuit layer, a layer for forming a pixel circuit layer PCL on a base layer BSL may be patterned.

[0130] In this step S100, the pixel circuit PXC, the first power line PL1, and the second power line PL2 may be patterned on the base layer BSL, and the via layer VIA may be formed on the pixel circuit PXC, the first power line PL1, and the second power line PL2.

[0131] In this step S100, the first power line PL1 and the pixel circuit PXC may be electrically connected. According to the embodiment, the second power line PL2 can be exposed, and a contact hole for forming the contact member CNP in a subsequent process can be formed.

[0132] According to the embodiment, the conductive layer or the insulating layer on the base layer BSL can be formed based on the normal processes for manufacturing semiconductor devices. For example, the conductive layer or the insulating layer on the base layer BSL may be formed by a photolithography process, may be etched by various methods (such as wet etching, dry etching, etc.), and may be deposited by various methods (such as sputtering, chemical vapor deposition, etc.). The present disclosure is not necessarily limited to special examples.

[0133] Referring to FIGS. 9, 10, 13, and 14, in step S220 of forming the anode electrode, the pixel defining layer, and the wiring, the anode electrode AE may be patterned on the pixel circuit layer PCL (for example, the base layer BSL) and the via layer VIA, the pixel defining layer PDL may be patterned adjacent to the anode electrode AE, and the wiring L may be patterned on the pixel defining layer PDL.

[0134] In this step S220, it may be patterned in the regions corresponding to the first to third sub-pixel regions SPXA1 to SPXA3 where the first to third anode electrodes AE1 to AE3 are to be formed. Also, each of the first to third anode electrodes AE1 to AE3 may be electrically connected to the first to third pixel circuits PXC1 to PXC3 through the contact portions CNT penetrating the via layer VIA.

[0135] In this step S220, the pixel defining layer PDL may be patterned to overlap with an area adjacent to the first to third sub-pixel regions SPXA1 to SPXA3, may be patterned to cover the first to third anode electrodes AE1 to AE3, or may be patterned to expose at least a part of the first to third anode electrodes AE1 to AE3.

[0136] In this step S220, the wiring L is patterned on the pixel defining layer PDL, and first and second wirings L1 and L2 spaced apart from each other may be provided. For example, first-1 wiring L1-1, first-2 wiring L1-2, second-1 wiring L2-1, and second-2 wiring L2-2 may be formed in an area adjacent to the first sub-pixel SPXA1, first-1 wiring L1-1, first-2 wiring L1-2, second-1 wiring L2-1, and second-2 wiring L2-2 may be formed in an area adjacent to the second sub-pixel SPXA2, and first-1 wiring L1-1, first-2 wiring L1-2, second-1 wiring L2-1, and second-2 wiring L2-2 may be formed in an area adjacent to the third sub-pixel SPXA3.

[0137] In this step S220, a contact member CNP at least partially penetrating the pixel defining layer PDL may be formed, and at least a part of the first wiring L1 may be electrically connected to the second power line PL2. For example, the first-2 wiring L1-2 adjacent to one side of each of the sub-pixel regions SPXA may be electrically connected to the second power line PL2 via the contact portion CNP. However, a part of the first wiring L1 electrically connected to the contact member CNP is not limited to the first-2 wiring L1-2, and according to the embodiment, at least a part of the other first wiring L1 may be electrically connected.

[0138] The first to third light-emitting parts EL1 to EL3 according to the embodiment can be manufactured without using an FMM (Fine Metal Mask). According to the embodiment, the first to third light-emitting parts EL1 to EL3 are structures included in each of the sub-pixels SPX for emitting light of different colors, and the first to third light-emitting parts EL1 to EL3 adjacent to each other need to be separated from each other. According to the implementation, the first to third light-emitting parts EL1 to EL3 may be separately provided from each other using the Joule heat generated by the wiring L.

[0139] According to the embodiment, after the steps S220 of forming the anode electrode, the pixel defining layer, and the wiring, layers for forming the sub-pixel SPX may be sequentially formed. Hereinafter, for convenience of explanation, the process of forming the layers for forming the sub-pixel SPX in the order of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 will be described. However, the present disclosure is not limited thereto.

[0140] Referring to FIGS. 9 to 11 and FIG. 15, in the step S240 of patterning the layer for defining the first sub-pixel, the step S2410 of forming the base light-emitting part may be performed.

[0141] In this step S2410, the base light-emitting part EL1_B may be formed in the display area DA. The base light-emitting part EL1_B can be formed without using an FMM. For example, the base light-emitting part EL1_B may be entirely vapor-deposited on the pixel circuit layer PCL. The base light-emitting part EL1_B can cover the exposed anode electrode AE (for example, the first anode electrode AE1) and can cover the wiring L. For example, the base light-emitting part EL1_B can cover the first wiring L1 and the second wiring L2. Since the base light-emitting part EL1_B covers the pixel defining layer PDL, the pixel defining layer PDL may not be exposed.

[0142] Referring to FIGS. 9 to 11 and FIG. 16, in step S240 of patterning a layer for defining the first sub-pixel, step S2420 of removing at least a part of the layer adjacent to the first wiring may be performed. The layer adjacent to the first wiring L1 removed in this step S2420 may include the base light-emitting portion EL1_B, and after this step S2420 is performed, the layer adjacent to the first wiring L1 may include the remaining light-emitting portion EL1_R.

[0143] This step S2420 may be a step of separating the light-emitting portion EL for emitting light of one color from the light-emitting portion EL for emitting light of another color. By performing this step S2420, the light-emitting portion EL can be divided for each sub-pixel SPX, leakage current can be prevented, and the risk that light of one color is emitted in a color other than the intended color can be prevented. Also, since the light-emitting portion EL can be divided for each sub-pixel SPX using Joule heat, a separate structure is not additionally required, and the convenience of the manufacturing process can be improved.

[0144] In this step S2420, a first voltage can be supplied to the first wiring L1 (for example, the first-1 wiring L1-1 and the first-2 wiring L1-2), and the first wiring L1 can form Joule heat. For example, a pulsed input voltage can be provided to the first wiring L1, and thermal energy can be applied to the region adjacent to the first wiring L1. The numerical range of the first voltage and the input method by which the first voltage is provided are not limited to specific examples.

[0145] In this step S2420, a part of the pixel definition layer PDL adjacent to the first wiring L1 may be exposed. For example, a first opening OP1 exposing the pixel definition layer PDL may be formed by removing a part of the base light-emitting portion EL1_B by the heat generated by the first wiring L1.

[0146] Referring to FIG. 2 in combination, since the first wiring L1 can be in a closed-loop shape surrounding an area, the first opening OP1 can also be in a closed-loop shape surrounding an area.

[0147] In this step S2420, at least a part of the base light-emitting part EL1_B can be removed to provide (or pattern) the first light-emitting part EL1 and the remaining light-emitting part EL1_R. For example, a part of the base light-emitting part EL1_B adjacent to the first wiring L1 can be removed to form the first light-emitting part EL1 and the remaining light-emitting part EL1_R separated from each other. Thereby, the first light-emitting part EL1 can be arranged within the region surrounded by the first wiring L1, and the remaining light-emitting part EL1_R can be arranged on the outer contour of the first wiring L1. That is, by performing this step S2420, the first light-emitting part EL1 provided separately can be manufactured in the region where the first sub-pixel region SPXA1 is to be formed.

[0148] When this step S2420 is performed, the second wiring L2 can be covered by the remaining light-emitting part EL1_R and may not be exposed.

[0149] Referring to FIGS. 9 to 11 and FIG. 17, in step S240 of patterning the layer for defining the first sub-pixel, step S2430 of forming the base cathode electrode and the first base capping layer may be performed.

[0150] In this step S2430, the base cathode electrode CE_B and the first base capping layer CPL1_B may be formed in the display area DA. For example, the base cathode electrode CE_B and the first base capping layer CPL1_B may be deposited over the entire surface.

[0151] In this step S2430, the base cathode electrode CE_B can cover the first wiring L1 and can be electrically connected to the first wiring L1. The base cathode electrode CE_B may be physically in contact with the first wiring L1. Thereby, the base cathode electrode CE_B can be electrically connected to the second power line PL2 via the first wiring L1 and the contact member CNP. At least a part of the base cathode electrode CE_B can fill the first opening OP1, can contact the pixel defining layer PDL in the region corresponding to the first opening OP1, and can cover the first light-emitting part EL1 and the remaining light-emitting part EL1_B.

[0152] In this step S2430, the first base capping layer CPL1_B can cover the base cathode electrode CE_B. The first base capping layer CPL1_B can passivate the base cathode electrode CE_B and the layer thereunder.

[0153] Referring to FIGS. 9 to 11, FIG. 18, and FIG. 19, in step S240 of patterning the layer for defining the first sub-pixel, step S2440 of removing at least a part of the layer adjacent to the second wiring may be performed. The layer adjacent to the second wiring L2 removed in this step S2440 may include a remaining light-emitting portion EL1_R, a part of the base cathode electrode CE_B, and a part of the first base capping layer CPL1_B.

[0154] In this step S2440, a second voltage can be supplied to the second wiring L2 (for example, the second-1 wiring L2-1 and the second-2 wiring L2-2), and the second wiring L2 can form Joule heat. For example, a pulsed input voltage can be provided to the second wiring L2, and thermal energy can be applied to the region adjacent to the second wiring L2. The numerical range of the second voltage and the input method for providing the second voltage are not limited to specific examples.

[0155] According to an embodiment, the second voltage may be different from the first voltage supplied to the first wiring L1 described above. For example, as the second voltage increases, the size of the second opening OP2 can increase. The size of the second opening OP2 can correspond to the range where the inorganic encapsulation structure is formed. Therefore, based on the size of the second voltage, the range where the inorganic encapsulation structure is formed can be controlled.

[0156] In this step S2440, a part of the pixel defining layer PDL adjacent to the second wiring L2 may be exposed. For example, due to the heat generated by the formation of the second wiring L2, a part of the residual light emitting portion EL1_R, a part of the base cathode electrode CE_B, and a part of the first base capping layer CPL1_B may be removed, and a second opening OP2 exposing the pixel defining layer PDL may be formed. The size of the second opening OP2 may be determined based on the intensity of the voltage applied to the second wiring L2, the time for which the voltage is applied, and the like.

[0157] Referring to FIG. 2, since the second wiring L2 may be in a closed loop surrounding an area, the second opening OP2 may also be in a closed loop surrounding an area.

[0158] In this step S2440, at least a part of the base cathode electrode CE_B may be removed, and the first cathode electrode CE1 and the residual cathode electrode CE1_R may be provided. For example, a part of the base cathode electrode CE_B adjacent to the second wiring L2 is removed, the first cathode electrode CE1 is disposed within the area surrounded by the second wiring L2, and the residual cathode electrode CE1_R may be disposed on the outer periphery of the second wiring L2. That is, by performing this step S2440, the first cathode electrode CE1 for forming the first sub-pixel SPX1 can be manufactured. Further, as described above, since the base cathode electrode CE_B can be electrically connected to the first wiring L1, a first cathode electrode CE1 electrically connected to the second power line PL2 via the contact member CNP can be provided in the display area DA.

[0159] In this step S2440, at least a part of the first base capping layer CPL1_B may be removed, and the first capping layer CPL1 and the residual capping layer CPL1_R may be provided. For example, a part of the first base capping layer CPL1_B adjacent to the second wiring L2 is removed, the first capping layer CPL1 is disposed within the area surrounded by the second wiring L2, and the residual capping layer CPL1_R may be disposed on the outer periphery of the second wiring L2.

[0160] In this step S2440, according to the embodiment (see FIG. 19), the remaining light-emitting portion EL1_R can be etched more than the base cathode electrode CE_B and the first base capping layer CPL1_B, and the first light-emitting portion EL1 can be etched more than the cathode electrode CE and the first base capping layer CPL1_B. As a result, voids VO can be formed. For example, the remaining light-emitting portion EL1_R can be formed so as to be more recessed than the base cathode electrode CE_B and the first base capping layer CPL1_B, and voids VO can be formed below the remaining cathode electrode CE1_R and the remaining capping layer CPL1_R. The first light-emitting portion EL1 can be formed so as to be more recessed than the cathode electrode CE and the first base capping layer CPL1_B, and voids VO can be formed below the cathode electrode CE and the first capping layer CPL1. As a result, the voids VO can overlap with the remaining cathode electrode CE1_R and the remaining capping layer CPL1_R in plan view, and the voids VO can overlap with the cathode electrode CE and the first capping layer CPL1 in plan view.

[0161] Referring to FIGS. 9 to 11, FIG. 20, and FIG. 21, in step S240 of patterning the layer for defining the first sub-pixel, step S2450 of forming the second base capping layer may be performed.

[0162] In this step S2450, the second base capping layer CPL2_B can be formed in the display area DA. The second base capping layer CPL2_B may be deposited over the entire surface.

[0163] In this step S2450, the second base capping layer CPL2_B can cover the remaining capping layer CPL1_R, the second wiring L2, and the first capping layer CPL1. The second base capping layer CPL2_B can passivate the layer disposed below the second base capping layer CPL2_B.

[0164] In this step S2450, according to the embodiment (see FIG. 21), the second base capping layer CPL2_B may be formed so as to be directly adjacent to the void VO. For example, the second base capping layer CPL2_B can cover one side portion of the opened void VO. Therefore, the void VO can be surrounded by one or more layers.

[0165] In this step S2450, the second base capping layer CPL2_B can contact the pixel defining layer PDL in the region corresponding to the second opening OP2, whereby an inorganic encapsulation structure can be formed.

[0166] Referring to FIGS. 9 to 11, FIG. 22, and FIG. 23, in step S240 of patterning the layer for defining the first sub-pixel, step S2460 of removing at least a part of the layer disposed on the outer contour of the second wiring may be performed, whereby the first sub-pixel SPX1 can be provided. The layer disposed on the outer contour of the second wiring L2 removed in this step S2460 may include a part of the remaining light emitting portion EL1_R, a part of the remaining cathode electrode CE_R, and a part of the remaining capping layer CPL_R.

[0167] In this step S2460, an outer contour region RA for exposing a part of the pixel defining layer PDL may be formed on the outer contour of the second wiring L2. For example, since the layer disposed on the outer contour of the second wiring L2 can be etched, the first capping layer CPL1 and the second capping layer CPL2 can passivate the layer (for example, the first light emitting element LD1) disposed below the first capping layer CPL1. According to the embodiment, the second capping layer CPL2 can cover the outer surface of the second wiring L2.

[0168] In this step S2460, at least a part of the second capping layer CPL2 adjacent to the second wiring L2 may not be removed. As described above, the second capping layer CPL2 and the pixel defining layer PDL can contact each other to form an inorganic encapsulation structure. In this step S2460, by adjusting the range in which the second base capping layer CPL2_B is removed, the inorganic encapsulation structure can be retained.

[0169] In this step S2460, a part formed in the second sub-pixel region SPXA2, the third sub-pixel region SPXA3, etc. among the layers for forming the first sub-pixel SPX1 can be removed.

[0170] In this step S2460, according to the embodiment (see FIG. 23), a part of the void VO adjacent to the remaining cathode electrode CE1_R and the remaining capping layer CPL1_R may be removed, and the other part of the void VO adjacent to the cathode electrode CE and the first capping layer CPL1 may not be removed.

[0171] Referring to FIGS. 9, 10, and 24, a step S260 of patterning the layer for defining the second sub-pixel and a step S280 of patterning the layer for defining the third sub-pixel may be performed, and the second and third sub-pixels SPX2, SPX3 may be provided. FIG. 24 also shows the layer for the first sub-pixel SPX1 provided by performing the step S240 of patterning the layer for defining the above-mentioned first sub-pixel.

[0172] According to the embodiment, the step S260 of patterning the layer for defining the second sub-pixel may be performed in a manner similar to (for example, substantially the same as) the step S240 of patterning the layer for defining the above-mentioned first sub-pixel. For example, a cathode connection structure for the second sub-pixel SPX2 can be formed using the first wiring L1, the second light-emitting part EL2 can be separated from the different light-emitting part EL using the first wiring L1, and an inorganic-inorganic bonding structure can be formed using the second wiring L2.

[0173] According to an embodiment, the step S280 of patterning the layer for defining the third sub-pixel may be performed in a manner similar to (e.g., substantially the same as) the step S240 of patterning the layer for defining the first sub-pixel described above. For example, by using the first wiring L1, a cathode connection structure for the third sub-pixel SPX3 can be formed, and by using the first wiring L1, the third light-emitting portion EL3 can be separated from other light-emitting portions EL, and an inorganic-inorganic bonding structure can be formed by using the second wiring L2.

[0174] Referring to FIGS. 9, 10, and 25, in the step S290 of forming the encapsulation layer, the encapsulation layer TFE may be formed to cover the first to third sub-pixel regions SPXA1 to SPXA3.

[0175] In this step S290, the encapsulation layer TFE can be deposited over the entire surface, can cover the first to third light-emitting elements LD1 to LD3, and can cover the capping layer CPL.

[0176] According to an embodiment, the first to third encapsulation layers TFE1 to TFE3 can be sequentially formed (e.g., deposited) such that the encapsulation layer TFE is formed.

[0177] According to an embodiment, the light-emitting element LD can be protected by the pixel definition layer PDL forming the inorganic encapsulation structure and the second capping layer CPL2, and can be further protected by the encapsulation layer TFE.

[0178] Thereafter, according to the embodiment, an additional structure (e.g., a window, etc.) may be further formed on the encapsulation layer TFE, and a display device DD may be provided according to the embodiment.

[0179] As described above, the preferred embodiments of the present disclosure have been described with reference thereto. However, those skilled in the art or those having ordinary knowledge in the art will understand that the present disclosure can be variously modified and changed within the scope not departing from the spirit and technical scope of the present disclosure described in the appended claims.

[0180] Therefore, the technical scope of the present disclosure should not be limited to the content described in the detailed description of the specification, but should be determined by the scope of the claims.

[0181] According to a preferred embodiment, it is as follows.

[0182] The background and problems of this case are as follows (i) to (vi).

[0183] (i) In a display panel or the like in which organic light-emitting elements (OLEDs) are arranged, for each sub-pixel, a lower electrode (typically a pixel electrode) and an upper electrode (typically a common electrode) are arranged, and a light-emitting layer or the like is arranged therebetween. And the pixel electrode of the organic light-emitting element (OLED) is connected to the lower pixel electrode formed for each sub-pixel.

[0184] (ii) The common electrode can be arranged over a plurality of sub-pixels. However, for improving display performance, it is desirable to supply a common voltage from a large number of locations over the entire display area. Also, depending on the driving method or the like, it often occurs that it is desirable to separate the common electrodes between sub-pixels of different colors.

[0185] (iii) Power supply to the common electrode is performed through contact holes. However, in order to supply sufficient power, it is necessary to increase the area of the contact holes.

[0186] (iv) Also, in order to separate the common electrode, for example, horizontally or vertically, it is necessary to perform a patterning process, which imposes a process burden.

[0187] (v) When the common electrode is used as the upper electrode, in the contact region with the lower electrode, if the light-emitting layer is not sufficiently removed, the contact resistance may increase.

[0188] (vi) Referring to FIGS. 7 to 8 of Patent Document 1 and

[0096] -

[0100] , etc., for the pixel electrodes of each sub-pixel, they are composed of a plurality of divided electrodes (125a, 125b, 125c), and the divided electrodes (125a, 125b, 125c) are connected to each other by narrow bridge electrodes (BEa, BEb). As shown in FIG. 7, when a short circuit occurs due to a foreign object (P) in one divided electrode (125b), the short-circuit current concentrates, causing disconnection and blackening the location of this divided electrode (125b). However, Patent Document 1 does not provide any separate disclosure or suggestion related to the problems of this case.

[0189] Therefore, according to a particularly preferred embodiment, it is set as follows in A1 to A4 or A1 to A5 below.

[0190] A1. Near the opening of the sub-pixel, preferably so as to surround the opening of the sub-pixel, a "first wiring L1" (including the left and right first-1 wiring portions L1-1 and first-2 wiring portions L1-2) for supplying a common voltage is formed on the pixel defining film (PDL). At this time, the "first wiring L1" is connected to the "second power line PL2" on the lower layer side through a contact hole (such as a contact member CNP) that penetrates the pixel defining film (PDL) and the insulating layer below it.

[0191] A2. After forming the light-emitting layer (base light-emitting portion EL1), by applying a strong pulse voltage to the "first wiring L1", the light-emitting layer is evaporated and removed at the location covering the "first wiring L1" and its vicinity.

[0192] A3. On the other hand, when viewed from the opening of the sub-pixel, a "second wiring L2" (including the left and right second-1 wiring portions L1-1 and second-2 wiring portions L1-2) is formed on the pixel defining film (PDL) outside the "first wiring L1", etc., preferably so as to surround the vicinity of the opening of the sub-pixel.

[0193] After forming the A4 common electrode layer (CE1) and the capping layer (the first base capping layer CPL1_B), a pulse voltage is applied to the "second wiring L2" to evaporate and remove the common electrode layer (CE1) and the like at the location covering the "second wiring L2" and in its vicinity. As a result, the common electrode layer (CE1) is separated between sub-pixels of different colors and the like.

[0194] In many cases, the light-emitting layer is more likely to evaporate than the metal layer or conductive layer constituting the common electrode layer (CE1). Therefore, voids (void VO) can be formed below the location sandwiching the "second wiring L2" where the common electrode layer (CE1) protrudes in a eaves shape or chip shape. This void (void VO) can be completely hollow or can have a partially remaining light-emitting layer.

Explanation of symbols

[0195] DD Display device PXL, SPX Pixel, sub-pixel DA, NDA Display area, non-display area PCL Pixel circuit layer LEL Light-emitting element layer L Wiring CNP Contact member LD Light-emitting element AE Anode electrode CE Cathode electrode CPL Capping layer EL Light-emitting part PDL Pixel definition layer PXC Pixel circuit PL1, PL2 First power line, second power line TFE Encapsulation layer VIA Via layer VO Void

Claims

1. A display device including a sub-pixel region, a pixel circuit layer including a base layer and a pixel circuit disposed on the base layer; a light emitting element layer disposed on the pixel circuit layer and including a light emitting element, a pixel defining layer, a capping layer, and wiring electrically connected to the pixel circuit; The light-emitting element includes an anode electrode, a cathode electrode, and a light-emitting portion at least a part of which is disposed between the anode electrode and the cathode electrode; the pixel definition layer covers at least a portion of the anode electrode; at least a portion of said capping layer contacts said pixel definition layer; the wiring includes a first wiring and a second wiring that are spaced apart from each other and that are disposed on the pixel definition layer and each of the first wiring and the second wiring forms a closed loop; the first wiring surrounds the sub-pixel region in a plan view, and the second wiring surrounds the first wiring in a plan view; The light-emitting portion is disposed within a region surrounded by the first wiring.

2. The wiring has a resistance of 4.0×10 at 20° C. ７ The display of claim 1 , comprising a conductive material having an electrical conductivity of less than (S / m).

3. The display device according to claim 2 , wherein the wiring contains aluminum (Al) or molybdenum (Mo).

4. The first wiring and the second wiring are Each contains the same material, The display device of claim 1 , wherein each of the pixel defining layers is disposed on one side of the pixel defining layer.

5. the first wiring is disposed in a peripheral portion of the sub-pixel region, the second wiring is disposed in a peripheral portion of the first wiring, the sub-pixel region includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region; The display device of claim 1 , wherein the first wiring includes a first wiring portion surrounding the first sub-pixel region, a second wiring portion surrounding the second sub-pixel region, and a third wiring portion surrounding the third sub-pixel region.

6. the cathode electrode includes a first cathode electrode overlapping the first sub-pixel region, a second cathode electrode overlapping the second sub-pixel region, and a third cathode electrode overlapping the third sub-pixel region; The display device of claim 5 , wherein the first cathode electrode, the second cathode electrode, and the third cathode electrode are physically separated from each other.

7. the pixel circuit layer includes a first power line and a second power line having different potentials; the first power supply line is electrically connected to the pixel circuit, The display device according to claim 1 , wherein the second power supply line is electrically connected to a cathode electrode via the first wiring.

8. a display area and a non-display area surrounding at least a portion of the display area; At least a portion of the first wiring is electrically connected to the second power supply line via a contact portion that penetrates the pixel definition layer; the second power line has a thickness greater than that of the cathode electrode; The display device according to claim 7 , wherein the contact portion is disposed within the display area.

9. the capping layer includes a first capping layer and a second capping layer on the first capping layer; the first capping layer covers the first wiring and does not cover the second wiring; The display device according to claim 1 , wherein the second capping layer covers the second wiring.

10. The display device of claim 9 , wherein the second capping layer and the pixel defining layer each include an inorganic material and are in contact with each other in a region adjacent to the second wiring.

11. a display area and a non-display area surrounding at least a portion of the display area; a pixel circuit layer including a base layer, a pixel circuit and a power line disposed on the base layer, and a via layer covering the power line; a light emitting element layer disposed on the pixel circuit layer and including a light emitting element, a pixel definition layer, and wiring electrically connected to the pixel circuit; The light-emitting element includes an anode electrode, a cathode electrode, and a light-emitting portion at least a part of which is disposed between the anode electrode and the cathode electrode; the pixel definition layer overlaps with the anode electrode in a plan view, the wiring includes a first wiring and a second wiring disposed directly on the pixel definition layer and spaced apart from each other; the power supply line is arranged across the display area and the non-display area, the cathode electrode and the power supply line are electrically connected in the display area through a contact member that penetrates the via layer; The power supply line has a thickness greater than that of the cathode electrode.

12. fabricating a pixel circuit layer; manufacturing a light emitting device layer including a light emitting device disposed on the pixel circuit layer; The step of manufacturing the light emitting device layer includes: forming an anode electrode, a pixel defining layer, and wiring on the pixel circuit layer; patterning the layer to define subpixels; the wiring includes a first wiring and a second wiring spaced apart from each other and disposed on the pixel definition layer, the first wiring being closer to the anode electrode than the second wiring; The patterning step includes: forming a base light emitting portion; removing at least a portion of a layer adjacent to the first wiring by supplying a first voltage to the first wiring, the layer adjacent to the first wiring including the base light-emitting portion; forming a base cathode electrode and a first base capping layer; A step of removing at least a portion of a layer adjacent to the second wiring by supplying a second voltage to the second wiring. the layer adjacent to the second wiring includes the base light emitting portion, the base cathode electrode, and the first base capping layer.

13. the pixel circuit layer includes a pixel circuit, a first power supply line electrically connected to the pixel circuit, and a second power supply line having a potential different from that of the first power supply line; The method of claim 12, wherein the forming of the wiring includes electrically connecting the first wiring and the second power supply line.

14. The method of claim 13, wherein the forming the base emitter comprises depositing the base emitter over the entire surface of the pixel circuit layer.

15. The method of claim 12 , wherein removing at least a portion of the layer adjacent to the first wiring includes providing a first light-emitting portion disposed within a region surrounded by the first wiring.

16. The step of forming the base cathode electrode comprises: electrically connecting the base cathode electrode and the first wiring; The method of claim 12 , further comprising: contacting the base cathode electrode with the pixel definition layer in an area adjacent to the first wiring.

17. removing at least a portion of the layer adjacent to the first wiring includes forming a first opening exposing at least a portion of the pixel definition layer; The method of claim 12 , wherein removing at least a portion of the layer adjacent to the second wiring includes forming a second opening that exposes at least a portion of the pixel defining layer.

18. forming a second base capping layer; 13. The method of claim 12, further comprising: removing at least a portion of a layer formed on an outer periphery of the second wiring, the layer formed on the outer periphery of the second wiring including the base light emitting portion, the base cathode electrode, and the first base capping layer.

19. the second base capping layer contacts the pixel definition layer in an area adjacent to the second wiring; 20. The method of claim 18, wherein the second base capping layer and the pixel defining layer each comprise an inorganic material.

20. The method of claim 12, further comprising: blanket depositing an encapsulation layer on the pixel circuit layer.

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