High-frequency module and communication device

Abstract

To provide a high-frequency module that is equipped with an IC chip including low-noise amplifiers and can reduce signal interference.SOLUTION: A high-frequency module includes a mounting board and an IC chip. The IC chip includes a plurality of switches and a plurality of low-noise amplifiers. The mounting board includes a first ground layer 23, a second ground layer, a first via conductor group, and a second via conductor group. The first ground layer 23 has a plurality of slits 27. The plurality of slits 27 include a first slit 271 and a second slit 272. The first slit 271 is disposed between a first via conductor V11 and a third via conductor V21 in a plan view from a thickness direction D1 of the mounting board 2. The second slit 272 is disposed between a second via conductor V12 and a fourth via conductor V22 in a plan view from the thickness direction D1 of the mounting board 2.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a high-frequency module and a communication device, and more particularly to a high-frequency module including an IC chip having a low-noise amplifier and a communication device including the high-frequency module.

Background Art

[0002] Patent Document 1 describes a high-frequency module including a semiconductor element (IC chip) including a transmission power amplifier (power amplifier). In the high-frequency module described in Patent Document 1, an interference-preventing ground pattern is disposed between two voltage supply lines that supply voltage to one transmission power amplifier. Further, in the high-frequency module described in Patent Document 1, a slit is provided between two regions facing the two voltage supply lines in the interference-preventing ground pattern.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the high-frequency module described in Patent Document 1, when the IC chip includes a low-noise amplifier, signal interference may occur not only between the voltage supply lines but also between the paths of the received signals.

[0005] An object of the present invention is to reduce signal interference in a high-frequency module including an IC chip having a low-noise amplifier and a communication device including the high-frequency module.

Means for Solving the Problems

[0006] A high-frequency module according to one aspect of the present invention includes a mounting substrate and an IC chip. The mounting substrate is a multilayer substrate and has a first main surface and a second main surface facing each other. The IC chip is disposed on the first main surface of the mounting substrate. The IC chip includes a plurality of switches and a plurality of low-noise amplifiers. The plurality of low-noise amplifiers are connected to the plurality of switches one-to-one. The plurality of switches include a first switch and a second switch. The plurality of low-noise amplifiers include a first low-noise amplifier and a second low-noise amplifier. The first low-noise amplifier is connected to the first switch. The second low-noise amplifier is connected to the second switch. The mounting substrate includes a first ground layer, a second ground layer, a first via conductor group, a second via conductor group, and a third via conductor group. The first ground layer is disposed between the first main surface and the second main surface. The second ground layer is disposed between the first ground layer and the second main surface. The first via conductor group connects the plurality of switches and the first ground layer. The second via conductor group connects the plurality of low-noise amplifiers and the first ground layer. The third via conductor group connects the first ground layer and the second ground layer. The first ground layer has a plurality of slits. The third via conductor group is disposed around the first via conductor group and the second via conductor group in a plan view from the thickness direction of the mounting substrate. The first via conductor group includes a first via conductor and a second via conductor. The first via conductor is connected to the first switch. The second via conductor is connected to the second switch. The second via conductor group includes a third via conductor and a fourth via conductor. The third via conductor is connected to the first low-noise amplifier. The fourth via conductor is connected to the second low-noise amplifier. The plurality of slits include a first slit and a second slit. The first slit is disposed between the first via conductor and the third via conductor in a plan view from the thickness direction of the mounting substrate. The second slit is disposed between the second via conductor and the fourth via conductor in a plan view from the thickness direction of the mounting substrate.The first via conductor, the first slit, and the third via conductor, and the second via conductor, the second slit, and the fourth via conductor are arranged adjacent to each other.

[0007] A communication device according to one aspect of the present invention includes the high-frequency module and a signal processing circuit connected to the high-frequency module.

Advantages of the Invention

[0008] According to the high-frequency module and the communication device according to one aspect of the present invention, it is possible to reduce signal interference.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0010] Hereinafter, the high-frequency module and the communication device according to the embodiments will be described with reference to the drawings. Each of the drawings referred to in the following embodiments is a schematic diagram, and the ratio of the size and thickness of each component in the drawings does not necessarily reflect the actual dimensional ratio.

[0011] (Embodiment 1) (1) High-Frequency Module As shown in FIG. 7, for example, the high-frequency module 1 is used in the communication device 100. The communication device 100 is, for example, a mobile phone such as a smartphone. Note that the communication device 100 is not limited to being a mobile phone, and may be, for example, a wearable terminal such as a smartwatch. The high-frequency module 1 is, for example, a high-frequency module capable of supporting 4G (Fourth Generation Mobile Communication) standards, 5G (Fifth Generation Mobile Communication) standards, etc. The 4G standard is, for example, the 3GPP (Registered Trademark, Third Generation Partnership Project) LTE (Registered Trademark, Long Term Evolution) standard. The 5G standard is, for example, 5G NR (New Radio). The high-frequency module 1 is, for example, capable of supporting carrier aggregation and dual connectivity.

[0012] The high-frequency module 1 is provided, for example, in a communication device 100 that supports multi-band and conforms to communication standards such as LTE. The high-frequency module 1 can, for example, assign different frequencies to a transmission signal (a high-frequency signal for transmission) and a reception signal (a high-frequency signal for reception) by FDD (Frequency Division Duplex) to realize two-way transmission of full-duplex communication.

[0013] (2) Circuit Configuration of High-Frequency Module Hereinafter, the circuit configuration of the high-frequency module 1 according to Embodiment 1 will be described with reference to FIG. 7.

[0014] As shown in FIG. 7, the high-frequency module 1 according to Embodiment 1 includes, for example, a plurality of external connection terminals 18, a switch 11, a plurality (four in FIG. 7) of reception filters 121 to 124, a plurality (two in FIG. 7) of switches 13, a plurality (two in FIG. 7) of matching circuits 14, a plurality (two in FIG. 7) of low-noise amplifiers 15, a plurality (two in FIG. 7) of inductors 16, and a switch 17. The plurality of external connection terminals 18 include an antenna terminal 181, a first signal output terminal 182, and a second signal output terminal 183.

[0015] Here, the plurality of switches 13, the plurality of matching circuits 14, the plurality of low-noise amplifiers 15, and the plurality of inductors 16 are connected one-to-one. That is, the switch 131, the matching circuit 141, the low-noise amplifier 151, and the inductor 161 are connected to each other. Also, the switch 132, the matching circuit 142, the low-noise amplifier 152, and the inductor 162 are connected to each other.

[0016] (2.1) Low-Noise Amplifier Each of the plurality of low-noise amplifiers 15 is an amplifier that amplifies a reception signal. Each of the plurality of low-noise amplifiers 15 has an input terminal (not shown) and an output terminal (not shown).

[0017] The input terminal of the low-noise amplifier 151 is connected to the signal processing circuit 19 via the switch 17. The output terminal of the low-noise amplifier 151 is connected to the switch 131 via the matching circuit 141.

[0018] The input terminal of the low-noise amplifier 152 is connected to the signal processing circuit 19 via the switch 17. The output terminal of the low-noise amplifier 152 is connected to the switch 132 via the matching circuit 142.

[0019] (2.2) Reception Filter Each of the plurality of receiving filters 121 to 124 is a filter that allows a received signal to pass through. Each of the plurality of receiving filters 121 to 124 is, for example, an elastic wave filter including a plurality of series arm resonators and a plurality of parallel arm resonators. The elastic wave filter is, for example, a SAW (Surface Acoustic Wave) filter that utilizes elastic surface waves. Each of the receiving filters 121 to 124 has an input terminal (not shown) and an output terminal (not shown).

[0020] The input terminal of the receiving filter 121 is connected to the antenna terminal 181 via the switch 11. The output terminal of the receiving filter 121 is connected to the low-noise amplifier 151 via the switch 131.

[0021] The input terminal of the receiving filter 122 is connected to the antenna terminal 181 via the switch 11. The output terminal of the receiving filter 122 is connected to the low-noise amplifier 151 via the switch 131.

[0022] The input terminal of the receiving filter 123 is connected to the antenna terminal 181 via the switch 11. The output terminal of the receiving filter 123 is connected to the low-noise amplifier 152 via the switch 132.

[0023] The input terminal of the receiving filter 124 is connected to the antenna terminal 181 via the switch 11. The output terminal of the receiving filter 124 is connected to the low-noise amplifier 152 via the switch 132.

[0024] (2.3) Switch Switch 11 switches the filter connected to the antenna terminal 181 from among the plurality of receiving filters 121 to 124. Switch 11 has a common terminal 110 and selection terminals 111 to 114. The common terminal 110 is connected to the antenna terminal 181. The selection terminal 111 is connected to the receiving filter 121. The selection terminal 112 is connected to the receiving filter 122. The selection terminal 113 is connected to the receiving filter 123. The selection terminal 114 is connected to the receiving filter 124.

[0025] (2.4) Switch The plurality of switches 13 switches the filter connected to each of the plurality of low-noise amplifiers 15. The plurality of low-noise amplifiers 15 are connected to the plurality of switches 13 one-to-one. More specifically, switch 131 is connected to low-noise amplifier 151. Switch 132 is connected to low-noise amplifier 152.

[0026] Switch 131 switches the filter connected to low-noise amplifier 151 from among the plurality of receiving filters 121 to 122. Switch 131 has a common terminal 1310 and selection terminals 1311, 1312. The common terminal 1310 is connected to low-noise amplifier 151 via matching circuit 141. The selection terminal 1311 is connected to the receiving filter 121. The selection terminal 1312 is connected to the receiving filter 122.

[0027] Switch 132 switches the filter connected to low-noise amplifier 152 from among the plurality of receiving filters 123 to 124. Switch 132 has a common terminal 1320 and selection terminals 1321, 1322. The common terminal 1320 is connected to low-noise amplifier 152 via matching circuit 142. The selection terminal 1321 is connected to the receiving filter 123. The selection terminal 1322 is connected to the receiving filter 124.

[0028] Each of the plurality of switches 13 has a ground terminal (not shown).

[0029] (2.5) Switch The switch 17 switches the low-noise amplifier connected to each of the first signal output terminal 182 and the second signal output terminal 183 from among the plurality of low-noise amplifiers 15. The switch has common terminals 173, 174 and selection terminals 171, 172. The common terminal 173 is connected to the first signal output terminal 182. The common terminal 174 is connected to the second signal output terminal 183. The selection terminal 171 is connected to the low-noise amplifier 151. The selection terminal 172 is connected to the low-noise amplifier 152.

[0030] (2.6) Matching Circuit The matching circuit 141 is a circuit for impedance matching between the output terminal of the low-noise amplifier 151 and the common terminal 1310 of the switch 131. The matching circuit 141 includes at least one of one or more capacitors and one or more inductors.

[0031] The matching circuit 142 is a circuit for impedance matching between the output terminal of the low-noise amplifier 152 and the common terminal 1320 of the switch 132. The matching circuit 142 includes at least one of one or more capacitors and one or more inductors.

[0032] (2.7) Inductor The plurality of inductors 16 correspond one-to-one to the plurality of low-noise amplifiers 15.

[0033] The inductor 161 is an inductor connected between the ground terminal of the low-noise amplifier 151 and the matching circuit 141 and the ground.

[0034] The inductor 162 is an inductor connected between the ground terminal of the low-noise amplifier 152 and the ground terminal of the matching circuit 142 and the ground.

[0035] (3) Structure of High-Frequency Module Hereinafter, the structure of the high-frequency module 1 according to Embodiment 1 will be described with reference to the drawings.

[0036] The high-frequency module 1 according to Embodiment 1 includes, for example, as shown in FIG. 1, a mounting substrate 2 and an IC chip 10.

[0037] (3.1) Mounting Substrate As shown in FIG. 1, the mounting substrate 2 has a first main surface 21 and a second main surface 22. The first main surface 21 and the second main surface 22 face each other in the first direction D1.

[0038] The IC chip 10 is disposed on the first main surface 21 of the mounting substrate 2.

[0039] The mounting substrate 2 is, for example, a multilayer substrate including a plurality of dielectric layers and a plurality of conductive layers. The plurality of dielectric layers and the plurality of conductive layers are laminated in the first direction D1. The plurality of conductive layers are formed in a predetermined pattern defined for each layer. Each of the plurality of conductive layers includes one or more conductor portions in a plane orthogonal to the first direction D1. The material of each conductive layer is, for example, copper. The plurality of conductive layers include a plurality of ground layers to which a ground potential is applied. The plurality of ground layers include a first ground layer 23 and a second ground layer 24. That is, the mounting substrate 2 includes the first ground layer 23 and the second ground layer 24. The first ground layer 23 is disposed between the first main surface 21 and the second main surface 22. The second ground layer 24 is disposed between the first ground layer 23 and the second main surface 22. That is, in the first direction D1, the first main surface 21, the first ground layer 23, the second ground layer 24, and the second main surface 22 are arranged in this order. In each of the first ground layer 23 and the second ground layer 24, in a plan view from the first direction D1, the area of the conductor portion having a ground potential is 50% or more. In the high-frequency module 1, a plurality of ground terminals and the ground layer are electrically connected via via conductors or the like of the mounting substrate 2.

[0040] The mounting substrate 2 is, for example, an LTCC (Low Temperature Co-fired Ceramics) substrate. The mounting substrate 2 is not limited to the LTCC substrate, and may be, for example, an HTCC (High Temperature Co-fired Ceramics) substrate, a printed wiring board, or a resin multilayer substrate.

[0041] Also, the mounting substrate 2 is not limited to the LTCC substrate, and may be, for example, a wiring structure. The wiring structure is, for example, a multilayer structure. The multilayer structure includes at least one insulating layer and at least one conductive layer. The insulating layer is formed in a predetermined pattern. When there are a plurality of insulating layers, the plurality of insulating layers are formed in a predetermined pattern defined for each layer. The conductive layer is formed in a predetermined pattern different from the predetermined pattern of the insulating layer. When there are a plurality of conductive layers, the plurality of conductive layers are formed in a predetermined pattern defined for each layer. The conductive layer may include one or more rewiring portions. In the wiring structure, of the two surfaces facing each other in the thickness direction of the multilayer structure, the first surface is the first main surface 21 of the mounting substrate 2, and the second surface is the second main surface 22 of the mounting substrate 2. The wiring structure may be, for example, an interposer. The interposer may be an interposer using a silicon substrate, or may be a substrate composed of multiple layers.

[0042] (3.2) IC Chip The IC chip 10 is disposed on the first main surface 21 of the mounting substrate 2. The IC chip 10 is, for example, rectangular in shape and elongated in the third direction D3 in a plan view from the first direction D1. Here, the second direction D2 and the third direction D3 are orthogonal to each other and both are orthogonal to the first direction D1.

[0043] The IC chip 10 includes, for example, elements provided in each of a plurality of reception paths in a high-frequency module. More specifically, as shown in FIG. 2, the IC chip 10 includes a plurality (four in FIG. 3) of switches 13 and a plurality (four in FIG. 3) of low-noise amplifiers 15. The IC chip 10 further includes a plurality (four in FIG. 3) of inductors 16, a switch 17, and a control circuit 193.

[0044] The plurality of switches 13 and the plurality of low-noise amplifiers 15 correspond to each other one-to-one as described above. The plurality of switches 13 includes switches 131 to 134. The plurality of low-noise amplifiers 15 includes low-noise amplifiers 151 to 154. The low-noise amplifier 151 is connected to the switch 131. The low-noise amplifier 152 is connected to the switch 132. The low-noise amplifier 153 is connected to the switch 133. The low-noise amplifier 154 is connected to the switch 134. The switch 131 corresponds to the first switch of the present disclosure, and the switch 132 corresponds to the second switch of the present disclosure. The low-noise amplifier 151 corresponds to the first low-noise amplifier of the present disclosure, and the low-noise amplifier 152 corresponds to the second low-noise amplifier of the present disclosure.

[0045] The inductor 16 is constituted by, for example, a plurality of pattern conductors arranged along the first direction D1 and via conductors connecting two adjacent pattern conductors in the first direction D1. Each of the plurality of pattern conductors is, for example, L-shaped, linear, arc-shaped, or the like. The winding axis of the inductor 16 is, for example, a direction along the first direction D1. The control circuit 193 is, for example, a circuit that supplies power to the low-noise amplifier 15 and controls the switches 13 and 17.

[0046] The IC chip 10 is, for example, flip-mounted on the first main surface 21 of the mounting substrate 2. The IC chip 10 is connected to the mounting substrate 2 by, for example, a plurality of conductive bumps. The material of the conductive bumps is, for example, solder, gold, or copper.

[0047] (4) Details of the mounting substrate (4.1) Arrangement of via conductors Hereinafter, the structure of the high-frequency module 1 will be described in detail with reference to FIGS. 1 to 5. Here, FIGS. 2 to 5 show regions overlapping each other in a plan view from the first direction D1. Also, each of the X1-X1 cross-sections of FIGS. 2 to 5 corresponds to FIG. 1. Note that the dotted region in FIG. 3 indicates the existing region of the first ground layer 23. Also, the dotted region in FIG. 4 indicates the existing region of the second ground layer 24. That is, the dotted regions in FIGS. 3 and 4 indicate the surfaces rather than the cross-sections of the first ground layer 23 and the second ground layer 24.

[0048] A plurality of conductor portions 25 are arranged on the first main surface 21 of the mounting substrate 2. Also, the mounting substrate 2 has a plurality of via conductors V1 to V5. The plurality of via conductors V1 to V5 include a plurality of via conductors V1, a plurality of via conductors V2, a plurality of via conductors V3, a plurality of via conductors V4, and a plurality of via conductors V5. The plurality of via conductors V1 constitute the first via conductor group. The plurality of via conductors V2 constitute the second via conductor group. The plurality of via conductors V3 constitute the third via conductor group.

[0049] The plurality of conductor portions 25 are arranged on the first main surface 21 of the mounting substrate 2. Each of the plurality of conductor portions 25 has a first end and a second end. Each of the first ends of the plurality of conductor portions 25 is connected to the IC chip 10. Each of the second ends of the plurality of conductor portions 25 is connected to other electronic components (not shown) arranged on the first main surface 21 of the mounting substrate 2. The plurality of conductor portions 25 include, for example, a signal wiring portion that inputs signals from the reception filters 121 to 124 to the plurality of switches 13. Also, the plurality of conductor portions 25 include, for example, a voltage wiring portion that supplies a voltage for driving the IC chip 10.

[0050] Each of the plurality of via conductors V1 included in the first via conductor group connects the first main surface 21 and the first ground layer 23 in the first direction D1, which is the thickness direction of the mounting substrate 2, as shown in FIGS. 1 and 3 to 5. Each of the plurality of via conductors V1 is, for example, columnar. The first end of each of the plurality of via conductors V1 is disposed on the first main surface 21 of the mounting substrate 2 and is connected one-to-one to a plurality of switches 13 included in the IC chip 10. The second end of each of the plurality of via conductors V1 is connected to the first ground layer 23. That is, the first via conductor group connects the plurality of switches 13 and the first ground layer 23. More specifically, the via conductor V11 is connected to the switch 131. The via conductor V12 is connected to the switch 132. The via conductor V13 is connected to the switch 133. The via conductor V14 is connected to the switch 134. The via conductor V11 corresponds to the first via conductor of the present disclosure. The via conductor V12 corresponds to the second via conductor of the present disclosure.

[0051] Each of the plurality of via conductors V2 included in the second via conductor group connects the first main surface 21 and the first ground layer 23 in the first direction D1, which is the thickness direction of the mounting substrate 2, as shown in FIGS. 3 to 5. Each of the plurality of via conductors V2 is, for example, columnar. The first end of each of the plurality of via conductors V2 is disposed on the first main surface 21 of the mounting substrate 2 and is connected one-to-one to a plurality of low-noise amplifiers 15 included in the IC chip 10. More specifically, the plurality of via conductors V2 are connected to a plurality of inductors 16 connected to the plurality of low-noise amplifiers 15. The second end of each of the plurality of via conductors V4 is connected to the first ground layer 23. That is, the second via conductor group connects the plurality of low-noise amplifiers 15 and the first ground layer 23. More specifically, the via conductor V21 is connected to the low-noise amplifier 151. The via conductor V22 is connected to the low-noise amplifier 152. The via conductor V23 is connected to the low-noise amplifier 153. The via conductor V24 is connected to the low-noise amplifier 154. The via conductor V21 corresponds to the third via conductor of the present disclosure. The via conductor V22 corresponds to the fourth via conductor of the present disclosure.

[0052] The plurality of via conductors V1 included in the first via conductor group correspond one-to-one with the plurality of via conductors V2 included in the second via conductor group. Here, the correspondence between one via conductor V1 and one via conductor V2 means that the switch 13 connected to one via conductor V1 and the low-noise amplifier 15 connected to one via conductor V2 are connected to each other. More specifically, the via conductor V11 corresponds to the via conductor V21. The via conductor V12 corresponds to the via conductor V22. The via conductor V13 corresponds to the via conductor V23. The via conductor V14 corresponds to the via conductor V24.

[0053] Here, each of the first via conductor group and the second via conductor group is arranged at an end of the IC chip 10 in a plan view from the first direction D1. "Each of the first via conductor group and the second via conductor group is arranged at an end of the IC chip 10 in a plan view from the first direction D1" means that the distance between each of the plurality of via conductors V1 and each of the plurality of via conductors V2 and the outer edge of the IC chip 10 is equal to or less than 1 / 2 of the short side of the IC chip 10. More specifically, as shown in FIGS. 3 and 4, each of the plurality of via conductors V1 and each of the plurality of via conductors V2 are arranged along one end (upper side on the paper surface) of the IC chip 10 in the second direction D2.

[0054] Also, each of the plurality of via conductors V1 and each of the plurality of via conductors V2 are arranged alternately in a plan view from the first direction D1. More specifically, in the third direction D3, the via conductors V11, V21, V12, V22, V13, V23, V14, and V24 are arranged in this order.

[0055] The third via conductor group connects the first ground layer 23 and the second ground layer 24 in the first direction D1, which is the thickness direction of the mounting substrate 2. More specifically, each of the plurality of via conductors V3 included in the third via conductor group connects the first ground layer 23 and the second ground layer 24 in the first direction D1, as shown in FIGS. 1, 4, and 5. Each of the plurality of via conductors V3 is, for example, cylindrical. The first end of each of the plurality of via conductors V3 is connected to the first ground layer 23. The second end of each of the plurality of via conductors V3 is connected to the second ground layer 24. The third via conductor group is disposed around the first via conductor group and the second via conductor group. More specifically, as shown in FIG. 4, the density of the plurality of via conductors V3 is greater around the via conductor V1 or the via conductor V2 than outside the periphery of the via conductor V1 or the via conductor V2. This makes it possible to reduce the potential difference in the first ground layer 23 and to bring the potential of the first ground layer 23 closer to the ground potential.

[0056] Each of the plurality of via conductors V4 penetrates the mounting substrate 2 in the first direction D1 from at least the first main surface 21 to the second ground layer 24, as shown in FIGS. 3 to 5. Each of the plurality of via conductors V4 is, for example, cylindrical. The first end of each of the plurality of via conductors V4 is disposed on the first main surface 21 of the mounting substrate 2 and is connected to the IC chip 10. The second end of each of the plurality of via conductors V4 is connected to a conductor portion 26 on the same plane as the second ground layer 24 or a conductor portion (not shown) on the second main surface 22 side of the second ground layer 24, as shown in FIG. 6. Note that each of the plurality of via conductors V4 does not contact the first ground layer 23 and the second ground layer 24. The plurality of via conductors V4 includes, for example, a wiring portion that inputs a signal from the switch 17 to the external connection terminal 18. The plurality of via conductors V4 also includes, for example, a power supply circuit that supplies a voltage for driving the IC chip 10.

[0057] As shown in FIGS. 3 to 5, each of the plurality of via conductors V5 connects the first main surface 21 and the second ground layer 24 in the first direction D1. Each of the plurality of via conductors V5 is, for example, cylindrical. The first end of each of the plurality of via conductors V5 is connected to a land electrode (not shown) at ground potential disposed on the first main surface 21, for example. The second end of each of the plurality of via conductors V5 is connected to the second ground layer 24.

[0058] (4.2) Relationship between the via conductor and the first ground layer As shown in FIGS. 1, 4, and 6, the first ground layer 23 has a plurality of slits 27.

[0059] Each of the plurality of slits 27 is provided between one of the plurality of via conductors V1 included in the first via conductor group and the via conductor V2 corresponding to the via conductor V1 among the plurality of via conductors V2 included in the second via conductor group in a plan view from the first direction D1. That is, the switch 13 connected to one of the via conductors V1 in the first via conductor group and the low-noise amplifier 15 connected to one of the via conductors V2 in the second via conductor group are connected to each other.

[0060] More specifically, a slit 271 is disposed between the via conductor V11 and the via conductor V21. The via conductor V11 is connected to the switch 131. The via conductor V21 is connected to the low-noise amplifier 151. The low-noise amplifier 151 is connected to the switch 131. The slit 271 corresponds to the first slit of the present disclosure. Thereby, it is possible to reduce signal interference due to connection via the first ground layer 23 between the ground terminal of the switch 131 and the ground terminal of the low-noise amplifier 151. That is, the isolation between the switch 131 and the low-noise amplifier 151 is improved.

[0061] Similarly, a slit 272 is disposed between via conductor V12 and via conductor V22. Via conductor V12 is connected to switch 132. Via conductor V22 is connected to low-noise amplifier 152. Low-noise amplifier 152 is connected to switch 132. Slit 272 corresponds to the second slit of the present disclosure. Thereby, it becomes possible to reduce signal interference due to connection via the first ground layer 23 between the ground terminal of switch 132 and the ground terminal of low-noise amplifier 152. That is, the isolation between switch 132 and low-noise amplifier 152 is improved.

[0062] Similarly, a slit 273 is disposed between via conductor V13 and via conductor V23. Via conductor V13 is connected to switch 133. Via conductor V23 is connected to low-noise amplifier 153. Low-noise amplifier 153 is connected to switch 133. Thereby, it becomes possible to reduce signal interference due to connection via the first ground layer 23 between the ground terminal of switch 133 and the ground terminal of low-noise amplifier 153. That is, the isolation between switch 133 and low-noise amplifier 153 is improved.

[0063] Similarly, a slit 274 is disposed between via conductor V14 and via conductor V24. Via conductor V14 is connected to switch 134. Via conductor V24 is connected to low-noise amplifier 154. Low-noise amplifier 154 is connected to switch 134. Thereby, it becomes possible to reduce signal interference due to connection via the first ground layer 23 between the ground terminal of switch 134 and the ground terminal of low-noise amplifier 154. That is, the isolation between switch 134 and low-noise amplifier 154 is improved.

[0064] Also, as shown in FIG. 3, in the high-frequency module 1, in all via conductors V1, there is a slit 27 between the via conductor V1 and the via conductor V2. That is, one of the plurality of slit 27s is disposed between each of the plurality of via conductors V1 included in the first via conductor group and the corresponding via conductor V2 in the second via conductor group. Therefore, in the high-frequency module 1, the isolation between all of the plurality of switches 13 and the connected low-noise amplifier 15 is improved.

[0065] Also, each of the plurality of via conductors V1 and each of the plurality of via conductors V2 are alternately arranged in a plan view from the first direction D1. Therefore, as shown in FIG. 3, in the plan view from the first direction D1, a combination of one of the plurality of via conductors V1, one of the plurality of slits 27, and one of the plurality of via conductors V2 are arranged adjacent to each other. Here, "a combination of one of the plurality of via conductors V1, one of the plurality of slits 27, and one of the plurality of via conductors V2 are arranged adjacent to each other" means that there are no via conductors V1, via conductors V2, and slits 27 between one combination of via conductor V1, slit 27, and via conductor V2 and one combination of via conductor V1, slit 27, and via conductor V2.

[0066] More specifically, in the third direction D3, the via conductor V11, the slit 271, the via conductor V21, the via conductor V12, the slit 272, the via conductor V22, the via conductor V13, the slit 273, the via conductor V23, the via conductor V14, the slit 274, and the via conductor V24 are arranged in this order. Therefore, the via conductor V11, the slit 271, and the via conductor V21 and the via conductor V21, the slit 272, and the via conductor V22 are arranged adjacent to each other. Thereby, it becomes possible to reduce signal interference due to connection via the first ground layer 23 between the plurality of via conductors V1. Also, it becomes possible to reduce signal interference due to connection via the first ground layer 23 between the plurality of via conductors V2. Therefore, it becomes easy to improve the isolation between the plurality of switches 13 and the plurality of low-noise amplifiers 15.

[0067] Also, each of the plurality of via conductors V1 and each of the plurality of via conductors V2 are arranged at the end of the IC chip 10 in a plan view from the first direction D1. Therefore, as shown in FIG. 3, in the plan view from the first direction D1, the first via conductor group, the plurality of slits 27, and the second via conductor group are arranged at the end of the IC chip 10 in a plan view from the first direction D1. Thereby, in the mounting substrate 2, it becomes easy to regularly arrange the plurality of via conductors V1, the plurality of via conductors V2, and the plurality of slits 27. Therefore, it becomes easy to make the degree of improvement in isolation equal for any combination of the plurality of switches 13 and the plurality of low-noise amplifiers 15.

[0068] (4.3) Shape of slit As shown in FIGS. 4 and 6, each of the plurality of slits 27 is long in a direction intersecting the direction connecting one via conductor V1 and one via conductor V2 sandwiching the slit 27 in a plan view from the first direction D1. More specifically, the slit 271 is long in a direction intersecting the direction connecting the via conductor V11 and the via conductor V21. Similarly, the slit 272 is long in a direction intersecting the direction connecting the via conductor V12 and the via conductor V22. Similarly, the slit 273 is long in a direction intersecting the direction connecting the via conductor V13 and the via conductor V23. Similarly, the slit 274 is long in a direction intersecting the direction connecting the via conductor V14 and the via conductor V24.

[0069] More specifically, the width W1 of the slit 27 is equal to or less than the distance d1 between the via conductor V1 and the via conductor V2. Specifically, as shown in FIG. 6, the width W1 of the slit 274 is equal to or less than the distance d1 between the via conductor V14 and the via conductor V24. Similarly, the width W1 of the slit 271 is equal to or less than the distance d1 between the via conductor V11 and the via conductor V21.

[0070] Also, the length W2 of the slit 27 is equal to or more than twice the width W1 of the slit 27.

[0071] As a result, the length of the path in the first ground layer 23 that electrically connects via conductor V1 and via conductor V2 becomes sufficiently long with respect to the distance d1 between via conductor V1 and via conductor V2. Therefore, it becomes possible to further reduce the interference between the plurality of switches 13 and the plurality of low-noise amplifiers 15 via via conductor V1, via conductor V2, and the first ground layer 23.

[0072] (5) Communication device As shown in FIG. 7, the communication device 100 includes a high-frequency module 1, a signal processing circuit 19, and an antenna 101.

[0073] The antenna 101 is connected to the antenna terminal 181 of the high-frequency module 1. The antenna 101 has a transmission function of radiating the transmission signal output from the high-frequency module 1 as radio waves, and a reception function of receiving the reception signal as radio waves from the outside and outputting it to the high-frequency module 1.

[0074] The signal processing circuit 19 includes an RF signal processing circuit 191 and a baseband signal processing circuit 192. The signal processing circuit 19 processes the signal passing through the high-frequency module 1. More specifically, the signal processing circuit 19 processes the transmission signal and the reception signal.

[0075] The RF signal processing circuit 191 is, for example, an RFIC (Radio Frequency Integrated Circuit). The RF signal processing circuit 191 performs signal processing on high-frequency signals.

[0076] The RF signal processing circuit 191 performs signal processing such as up-conversion and amplification on the transmission signal transmitted from the baseband signal processing circuit 192, and outputs the transmission signal subjected to signal processing to the high-frequency module 1. Also, the RF signal processing circuit 191 performs signal processing such as amplification and down-conversion on the reception signal output from the high-frequency module 1, and outputs the reception signal subjected to signal processing to the baseband signal processing circuit 192.

[0077] The baseband signal processing circuit 192 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 192 performs predetermined signal processing on a transmission signal from outside the signal processing circuit 19. The received signal processed by the baseband signal processing circuit 192 is used, for example, as an image signal for image display or as an audio signal for a call.

[0078] In addition, the RF signal processing circuit 191 also has a function as a control unit that controls the connection of the switches 11, 13, and 17 of the high-frequency module 1 based on the transmission and reception of high-frequency signals (transmission signals, reception signals). Specifically, the RF signal processing circuit 191 switches the connection of the switches 11, 13, and 17 of the high-frequency module 1 by a control signal (not shown). Note that the control unit may be provided outside the RF signal processing circuit 191, and may be provided, for example, in the high-frequency module 1 or the baseband signal processing circuit 192.

[0079] (6) Effects The high-frequency module 1 according to Embodiment 1 includes a mounting substrate 2 and an IC chip 10. The mounting substrate 2 is a multilayer substrate and has a first main surface 21 and a second main surface 22 facing each other. The IC chip 10 is disposed on the first main surface 21 of the mounting substrate 2. The IC chip 10 includes a plurality of switches 13 and a plurality of low-noise amplifiers 15. The plurality of low-noise amplifiers 15 are connected to the plurality of switches 13 one-to-one. The plurality of switches 13 include a switch 131 and a switch 132. The plurality of low-noise amplifiers 15 include a low-noise amplifier 151 connected to the switch 131 and a low-noise amplifier 152 connected to the switch 132. The mounting substrate 2 includes a first ground layer 23, a second ground layer 24, a first via conductor group, a second via conductor group, and a third via conductor group. The first ground layer 23 is disposed between the first main surface 21 and the second main surface 22. The second ground layer 24 is disposed between the first ground layer 23 and the second main surface 22. The first via conductor group connects the plurality of switches 13 and the first ground layer 23. The second via conductor group connects the plurality of low-noise amplifiers 15 and the first ground layer 23. The third via conductor group connects the first ground layer 23 and the second ground layer 24. The first ground layer 23 has a plurality of slits 27. The third via conductor group is disposed around the first via conductor group and the second via conductor group in a plan view from the thickness direction D1 of the mounting substrate 2. The first via conductor group includes a via conductor V11 connected to the switch 131 and a via conductor V12 connected to the switch 132. The second via conductor group includes a via conductor V21 connected to the low-noise amplifier 151 and a via conductor V22 connected to the low-noise amplifier 152. The plurality of slits 27 include a slit 271 disposed between the via conductor V11 and the via conductor V21 and a slit 272 connected between the via conductor V12 and the via conductor V22 in a plan view from the thickness direction D1 of the mounting substrate 2. The via conductor V11, the slit 271, and the via conductor V21, and the via conductor V12, the slit 272, and the via conductor V21 are disposed adjacent to each other. Thereby, it is possible to reduce the crosstalk of signals via the first ground layer 23 between the plurality of switches 13 and the plurality of low-noise amplifiers 15.Therefore, it becomes possible to improve the isolation between each of the plurality of switches 13 and each of the plurality of low-noise amplifiers 15.

[0080] Further, in the high-frequency module 1 according to Embodiment 1, the plurality of slits 27 of the first via conductor group, the second via conductor group, and the first ground layer 23 are arranged at the end of the IC chip 10 in a plan view from the first direction D1. Therefore, in the mounting substrate 2, it becomes easy to regularly arrange the plurality of via conductors V1, the plurality of via conductors V2, and the plurality of slits 27. Therefore, it becomes easy to make the degree of improvement in isolation equal for any combination of the plurality of switches 13 and the plurality of low-noise amplifiers 15.

[0081] Further, in the high-frequency module 1 according to Embodiment 1, in a plan view from the first direction D1, the slit 27 is long in a direction intersecting the direction connecting the via conductor V11 and the via conductor V21. In a plan view from the first direction D1, the width W1 of the slit 27 is equal to or less than the distance d1 between the via conductor V11 and the via conductor V21. Thereby, the length of the path in the first ground layer 23 that electrically connects the via conductor V11 and the via conductor V21 becomes sufficiently long with respect to the distance d1 between the via conductor V11 and the via conductor V21. Therefore, it becomes possible to further reduce the interference between the switch 131 and the low-noise amplifier 151.

[0082] Further, in the high-frequency module 1 according to Embodiment 1, in a plan view from the first direction D1, the length W2 of the slit 271 is two times or more the width W1 of the slit 271. Thereby, the length of the path in the first ground layer 23 that electrically connects the via conductor V11 and the via conductor V21 becomes sufficiently long with respect to the distance d1 between the via conductor V11 and the via conductor V21. Therefore, it becomes possible to further reduce the interference between the switch 131 and the low-noise amplifier 151.

[0083] In addition, in the high-frequency module 1 according to Embodiment 1, the plurality of via conductors V1 included in the first via conductor group correspond one-to-one with the plurality of via conductors V2 included in the second via conductor group. One of the plurality of slits 27 is disposed between each of the plurality of via conductors V1 included in the first via conductor group and the corresponding via conductor V2 in the second via conductor group. Therefore, in the high-frequency module 1, the isolation between all of the plurality of switches 13 and the connected low-noise amplifiers 15 is improved.

[0084] In addition, the communication device 100 according to Embodiment 1 includes the high-frequency module 1 and a signal processing circuit 19 connected to the high-frequency module 1. Thereby, in the communication device 100 according to Embodiment 1, it is possible to improve the isolation between each of the plurality of switches 13 and each of the plurality of low-noise amplifiers 15 in the high-frequency module 1.

[0085] (Embodiment 2) (1) Configuration In the high-frequency module 1 according to Embodiment 2, the first ground layer 23 has a plurality of slits 27a.

[0086] As shown in FIG. 8, the first ground layer 23 has a plurality of slits 27a. Each of the plurality of slits 27a includes a first portion 28. In a plan view from the first direction D1, the first portion 28 overlaps with the inductor 16 (see FIG. 2). Here, "in a plan view from the first direction D1, the first portion 28 overlaps with the inductor 16" means that at least a part of the existence region of the inductor 16 is located inside the first portion 28 in a plan view from the first direction D1.

[0087] Specifically, in a plan view from the first direction D1, the first portion 281 overlaps with the inductor 161 (see FIG. 2). Also, the first portion 282 overlaps with the inductor 162 (see FIG. 2). The first portion 283 overlaps with the inductor 163 (see FIG. 2). The first portion 284 overlaps with the inductor 164 (see FIG. 2).

[0088] Therefore, in the high-frequency module 1 according to Embodiment 2, each of the plurality of inductors 16 overlaps with any one of the plurality of slits 27a in a plan view from the first direction D1. Thereby, it becomes possible to reduce the electromagnetic coupling between each of the plurality of inductors 16 and the first ground layer 23, and in particular, it becomes possible to reduce the parasitic capacitance of the plurality of inductors 16. Therefore, it becomes possible to reduce the inflow of noise into the plurality of low-noise amplifiers 15.

[0089] Further, in the high-frequency module 1 according to Embodiment 2, since the plurality of slits 27a have the first portion 28, the area is larger than that of the plurality of slits 27 in the high-frequency module 1 according to Embodiment 1. Therefore, since the length of the path in the first ground layer 23 that electrically connects the via conductor V1 and the via conductor V2 becomes longer, it becomes possible to further reduce the interference between the switch 13 and the low-noise amplifier 15.

[0090] (2) Effects In the high-frequency module 1 according to Embodiment 2, the IC chip 10 further includes a plurality of inductors 16 that correspond one-to-one to the plurality of low-noise amplifiers 15. Each of the plurality of inductors 16 is connected between the corresponding low-noise amplifier 15 among the plurality of low-noise amplifiers 15 and the via conductor V2 connected to the corresponding low-noise amplifier 15 in the second via conductor group. In a plan view from the first direction D1, one inductor among the plurality of inductors 16 overlaps with the slit 27a. Thereby, it becomes possible to reduce the electromagnetic coupling between each of the plurality of inductors 16 and the first ground layer 23, and it becomes possible to reduce the inflow of noise into the plurality of low-noise amplifiers 15. Further, since the length of the path in the first ground layer 23 that electrically connects the via conductor V1 and the via conductor V2 becomes longer, it becomes possible to further reduce the interference between the switch 13 and the low-noise amplifier 15.

[0091] (Embodiment 3) In the high-frequency module 1 according to Embodiment 3, in a plan view from the first direction D1, the combination of the via conductor V1, the slit 27, and the via conductor V2 is arranged along the outer periphery of the IC chip 10. Thereby, the combination of the via conductor V1, the slit 27, and the via conductor V2 is aligned not only in the third direction D3 but also in the second direction D2.

[0092] More specifically, as shown in FIG. 9, the via conductor V1 and the via conductor V2 are arranged in a U shape along the outer periphery of the IC chip 10. More specifically, the via conductor V15 and the via conductor V25 are aligned with the via conductor V11 and the via conductor V21 in the second direction D2. Similarly, the via conductor V16 and the via conductor V26 are aligned with the via conductor V14 and the via conductor V24 in the second direction D2. A slit 275 is arranged between the via conductor V15 and the via conductor V25. A slit 276 is arranged between the via conductor V16 and the via conductor V26.

[0093] Also in the high-frequency module 1 according to Embodiment 3, it is possible to reduce the interference between the switch 13 and the low-noise amplifier 15. In addition, since the switch 13 and the low-noise amplifier 15 do not need to be arranged on one side of the IC chip 10, it is possible to miniaturize the IC chip 10.

[0094] (Embodiment 4) (1) Configuration In the high-frequency module 1 according to Embodiment 4, the via conductors included in each of the first via conductor group and the second via conductor group reach the second ground layer 24 through the first ground layer 23 as shown in FIGS. 10 and 11.

[0095] Specifically, as shown in FIGS. 10 and 11, the first via conductor group and the second via conductor group connect the first main surface 21 of the mounting substrate 2 and the second ground layer 24 through the first ground layer 23. Here, the first via conductor group and the second via conductor group are connected to the first ground layer 23. In other words, the first via conductor group and the second via conductor group connect the first ground layer 23 and the second ground layer 24. Thereby, the uniformity of the potential of the first ground layer 23 is improved. Here, it is not necessary for all of the via conductors V1 and V2 included in each of the first via conductor group and the second via conductor group to be connected to the second ground layer 24. It is sufficient that at least one via conductor V1 and the via conductor V2 corresponding to the via conductor V1 are connected to the second ground layer 24.

[0096] Further, in the high-frequency module 1 according to Embodiment 4, the second ground layer 24 has a plurality of slits 29. In a plan view from the first direction D1, the plurality of slits 29 overlap the plurality of slits 27. Here, "in a plan view from the first direction D1, the plurality of slits 29 overlap the plurality of slits 27" means that in a plan view from the first direction D1, a part of each of the plurality of slits 29 overlaps a part of any of the plurality of slits 27. Specifically, in a plan view from the first direction D1, the slit 291 overlaps the slit 271. Also, in a plan view from the first direction D1, the slit 292 overlaps the slit 272. Also, in a plan view from the first direction D1, the slit 293 overlaps the slit 273. Also, in a plan view from the first direction D1, the slit 294 overlaps the slit 274.

[0097] Thereby, interference via the second ground layer 24 between the switch 13 connected to the via conductor V1 and the low-noise amplifier 15 connected to the via conductor V2 can be reduced.

[0098] (2) Effects In the high-frequency module 1 according to Embodiment 4, the first via conductor group and the second via conductor group further connect the first ground layer 23 and the second ground layer 24. As a result, the first ground layer 23 is connected to the second ground layer 24 not only by the third via conductor group but also by the first via conductor group and the second via conductor group. Therefore, the potential of the first ground layer 23 becomes more stable.

[0099] Also, in the high-frequency module 1 according to Embodiment 4, the second ground layer 24 has a plurality of slits 29. In a plan view from the first direction D1, the plurality of slits 27 in the first ground layer 23 overlap with the plurality of slits 29 in the second ground layer 24. Thereby, it becomes possible to reduce the signal crosstalk through the second ground layer 24 between the plurality of switches 13 and the plurality of low-noise amplifiers 15.

[0100] (Modification example) The high-frequency module 1 according to Embodiments 1 to 4 includes one IC chip 10 including a plurality of low-noise amplifiers 15, but the high-frequency module 1 may include a plurality of IC chips 10. At this time, each of the plurality of IC chips 10 may include a plurality of low-noise amplifiers 15 or may include one low-noise amplifier 15. In this case, in a plan view from the first direction D1, it is preferable that the plurality of low-noise amplifiers 15 are arranged along the outer edge of the region including the plurality of IC chips 10.

[0101] Also, in the high-frequency module 1 according to Embodiments 1 to 3, either one of the plurality of via conductors V1 and the plurality of via conductors V2 may further connect the first ground layer 23 and the second ground layer 24. As a result, the potential of the first ground layer 23 becomes more stable, and crosstalk of signals through the first ground layer 23 hardly occurs between the plurality of switches 13 and the plurality of low-noise amplifiers 15.

[0102] Also, in the high-frequency module 1 according to Embodiments 1 to 4, the mounting substrate 2 may further include a ground layer in addition to the first ground layer 23 and the second ground layer 24.

[0103] In addition, in the high-frequency module 1 according to Embodiments 1 to 4, the switch 131 is connected to the reception filters 121 and 122, and the switch 132 is connected to the reception filters 123 and 124. However, the connection relationship between the switch 13 and the reception filters 121 to 124 is not limited to this. As long as each of the plurality of switches 13 is configured to select a reception filter connected from the plurality of reception filters to the low-noise amplifier 15, the connection relationship between the switch 13 and the reception filter may be any configuration.

[0104] (Aspect) The high-frequency module (1) according to the first aspect includes a mounting substrate (2) and an IC chip (10). The mounting substrate (2) is a multilayer substrate and has a first main surface (21) and a second main surface (22) facing each other. The IC chip (10) is disposed on the first main surface (21) of the mounting substrate (2). The IC chip (10) includes a plurality of switches (13) and a plurality of low-noise amplifiers (15). The plurality of low-noise amplifiers (15) are connected to the plurality of switches (13) one-to-one. The plurality of switches (13) include a first switch (131) and a second switch (132). The plurality of low-noise amplifiers (15) include a first low-noise amplifier (151) and a second low-noise amplifier (152). The first low-noise amplifier (151) is connected to the first switch (131). The second low-noise amplifier (152) is connected to the second switch (132). The mounting substrate (2) includes a first ground layer (23), a second ground layer (24), a first via conductor group, a second via conductor group, and a third via conductor group. The first ground layer (23) is disposed between the first main surface (21) and the second main surface (22). The second ground layer (24) is disposed between the first ground layer (23) and the second main surface (22). The first via conductor group connects the plurality of switches (13) and the first ground layer (23). The second via conductor group connects the plurality of low-noise amplifiers (15) and the first ground layer (23). The third via conductor group connects the first ground layer (23) and the second ground layer (24). The first ground layer (23) has a plurality of slits (27; 27a). The third via conductor group is disposed around the first via conductor group and the second via conductor group in a plan view from the thickness direction (D1) of the mounting substrate (2). The first via conductor group includes a first via conductor (V11) and a second via conductor (V12). The first via conductor (V11) is connected to the first switch (131). The second via conductor (V12) is connected to the second switch (132). The second via conductor group includes a third via conductor (V21) and a fourth via conductor (V22). The third via conductor (V21) is connected to the first low-noise amplifier (151). The fourth via conductor (V22) is connected to the second low-noise amplifier (152).The plurality of slits (27; 27a) includes a first slit (271) and a second slit (272). The first slit (271) is disposed between the first via conductor (V11) and the third via conductor (V21) in a plan view from the thickness direction (D1) of the mounting substrate (2). The second slit (272) is disposed between the second via conductor (V12) and the fourth via conductor (V22) in a plan view from the thickness direction (D1) of the mounting substrate (2). The first via conductor (V11), the first slit (271), and the third via conductor (V21), and the second via conductor (V12), the second slit (272), and the fourth via conductor (V22) are disposed adjacent to each other.

[0105] According to the high-frequency module (1) according to the above aspect, it is possible to reduce the crosstalk through the first ground layer (23) of the signal between the plurality of switches (13) and the plurality of low-noise amplifiers (15). Therefore, it is possible to improve the isolation between each of the plurality of switches (13) and each of the plurality of low-noise amplifiers (15).

[0106] In the high-frequency module (1) according to the second aspect, in the first aspect, the first via conductor group and the second via conductor group connect the first ground layer (23) and the second ground layer (24).

[0107] According to the high-frequency module (1) according to the above aspect, since the potential of the first ground layer (23) is stabilized, it is possible to improve the isolation between each of the plurality of switches (13) and each of the plurality of low-noise amplifiers (15).

[0108] In the high-frequency module (1) according to the third aspect, in the second aspect, the second ground layer (24) has a plurality of slits (29). In a plan view from the thickness direction (D1) of the mounting substrate (2), the plurality of slits (27; 27a) of the first ground layer (23) and the plurality of slits (29) of the second ground layer (24) overlap.

[0109] According to the high-frequency module (1) according to the above aspect, it is possible to reduce the crosstalk via the second ground layer (24) of the signal between the plurality of switches (13) and the plurality of low-noise amplifiers (15). Therefore, it is possible to improve the isolation between each of the plurality of switches (13) and each of the plurality of low-noise amplifiers (15).

[0110] In the high-frequency module (1) according to the fourth aspect, in any of the first to third aspects, the plurality of slits (27) of the first via conductor group, the second via conductor group, and the first ground layer (23) are arranged at the end of the IC chip (10) in a plan view from the thickness direction (D1) of the mounting substrate (2).

[0111] According to the high-frequency module (1) according to the above aspect, it is easy to regularly arrange the first via conductor group, the second via conductor group, and the plurality of slits (27). Therefore, it is easy to make the degree of improvement in isolation equal for any combination of the plurality of switches (13) and the plurality of low-noise amplifiers (15).

[0112] In the high-frequency module (1) according to the fifth aspect, in any of the first to fourth aspects, in a plan view from the thickness direction (D1) of the mounting substrate (2), the first slit (271) is long in a direction intersecting the direction connecting the first via conductor (V11) and the third via conductor (V21). In a plan view from the thickness direction (D1) of the mounting substrate (2), the width of the first slit (271) is equal to or less than the distance between the first via conductor (V11) and the third via conductor (V21).

[0113] According to the high-frequency module (1) according to the above aspect, the length of the path in the first ground layer (23) that electrically connects the first via conductor (V11) and the third via conductor (V21) becomes sufficiently long with respect to the distance (d1) between the first via conductor (V11) and the third via conductor (V21). Therefore, it is possible to further reduce the interference between the first switch (131) and the first low-noise amplifier (151).

[0114] In the high-frequency module (1) according to the sixth aspect, in the fifth aspect, in a plan view from the thickness direction (D1) of the mounting substrate (2), the length (W2) of the first slit (271) is 2 times or more the width (W1) of the first slit (271).

[0115] According to the high-frequency module (1) according to the above aspect, the length of the path in the first ground layer (23) that electrically connects the first via conductor (V11) and the third via conductor (V21) becomes sufficiently long with respect to the distance (d1) between the first via conductor (V11) and the third via conductor (V21). Therefore, it becomes possible to further reduce the interference between the first switch (131) and the first low-noise amplifier (151).

[0116] In the high-frequency module (1) according to the seventh aspect, in any of the first to fourth aspects, the IC chip (10) further includes a plurality of inductors (16) that correspond one-to-one to the plurality of low-noise amplifiers (15). Each of the plurality of inductors (16) is connected between the corresponding low-noise amplifier (15) among the plurality of low-noise amplifiers (15) and the via conductor (V2) connected to the corresponding low-noise amplifier (15) in the second via conductor group. In a plan view from the thickness direction (D1) of the mounting substrate (2), one inductor (16) among the plurality of inductors (16) overlaps with the first slit (27a).

[0117] According to the high-frequency module (1) according to the above aspect, it becomes possible to reduce the electromagnetic coupling between each of the plurality of inductors (16) and the first ground layer (23), and it becomes possible to reduce the inflow of noise into the plurality of low-noise amplifiers (15). Further, since the length of the path in the first ground layer (23) that electrically connects the via conductor (V1) and the via conductor (V2) becomes longer, it becomes possible to further reduce the interference between the switch (13) and the low-noise amplifier (15).

[0118] In the high-frequency module (1) according to the eighth aspect, in any one of the first to seventh aspects, the plurality of via conductors (V1) included in the first via conductor group correspond one-to-one with the plurality of via conductors (V2) included in the second via conductor group. One of the plurality of slits (27; 27a) is disposed between each of the plurality of via conductors (V1) included in the first via conductor group and the corresponding via conductor (V2) in the second via conductor group.

[0119] According to the high-frequency module (1) according to the above aspect, for all of the plurality of switches (13), the isolation between the connected low-noise amplifier (15) is improved.

[0120] The communication device (100) according to the ninth aspect includes the high-frequency module (1) according to any one of the first to eighth aspects and a signal processing circuit (19) connected to the high-frequency module (1).

[0121] According to the communication device (100) according to the above aspect, in the high-frequency module (1), it is possible to reduce the signal crosstalk through the first ground layer (23) between the plurality of switches (13) and the plurality of low-noise amplifiers (15). Therefore, it is possible to improve the isolation between each of the plurality of switches (13) and each of the plurality of low-noise amplifiers (15).

Description of Reference Numerals

[0122] 1 High-frequency module 2 Mounting substrate 21 First main surface 22 Second main surface 23 First ground layer 24 Second ground layer 25, 26 Conductor portions 27 Slit 27a Slit (slit, first slit) 271 Slit (first slit) 272 Slit (second slit) 273, 274, 275, 276 Slits 28 First part 281, 282, 283, 284 First part 29 Slit 291, 292, 293, 294 Slits 10 IC chip 193 Control circuit 11 Switch 110 Common terminal 111, 112, 113, 114 Selection terminals 121, 122, 123, 124 Receiving filters 13 Switch 131 Switch (First switch) 1310 Common terminal 1311, 1312 Selection terminals 132 Switch (Second switch) 1320 Common terminal 1321, 1322 Selection terminals 133, 134 Switches 14 Integrating circuit 141, 142 Integrating circuits 15 Low-noise amplifier 151 Low-noise amplifier (First low-noise amplifier) 152 Low-noise amplifier (Second low-noise amplifier) 153, 154 Low-noise amplifiers 16 Inductor 161, 162, 163, 164 Inductors 17 Switch 171, 172 Selection terminals 173, 174 Common terminals 18 External connection terminal 181 Antenna terminal 182 First signal output terminal 183 Second signal output terminal 100 Communication device 101 Antenna 19 Signal processing circuit 191 RF signal processing circuit 192 Baseband signal processing circuit d1 distance D1 First direction D2 Second direction D3 Third direction V1 Via conductor V11 Via conductor (First via conductor) V12 Via conductor (Second via conductor) V13, V14, V15, V16 Via conductors V2 Via conductor V21 Via conductor (Third via conductor) V22 Via conductor (Fourth via conductor) V23, V24, V25, V26 Via conductors V3 Via conductor V4 Via conductor V5 Via conductor W1 Width W2 Length

Claims

1. A multilayer substrate including a mounting substrate having a first main surface and a second main surface facing each other, and an IC chip disposed on the first main surface of the mounting substrate. The IC chip includes a plurality of switches, and a plurality of low-noise amplifiers connected one-to-one to the plurality of switches. The plurality of switches include a first switch and a second switch. The plurality of low-noise amplifiers include a first low-noise amplifier connected to the first switch, and a second low-noise amplifier connected to the second switch. The mounting substrate includes a first ground layer disposed between the first main surface and the second main surface, a second ground layer disposed between the first ground layer and the second main surface, a first via conductor group connecting the plurality of switches and the first ground layer, a second via conductor group connecting the plurality of low-noise amplifiers and the first ground layer, and a third via conductor group connecting the first ground layer and the second ground layer. The first ground layer has a plurality of slits. The third via conductor group is disposed around the first via conductor group and the second via conductor group in a plan view from the thickness direction of the mounting substrate. The first via conductor group includes a first via conductor connected to the first switch, and a second via conductor connected to the second switch. The second via conductor group includes a third via conductor connected to the first low-noise amplifier, and a fourth via conductor connected to the second low-noise amplifier. The plurality of slits include a first slit disposed between the first via conductor and the third via conductor in a plan view from the thickness direction of the mounting substrate, and a second slit disposed between the second via conductor and the fourth via conductor in a plan view from the thickness direction of the mounting substrate. The first via conductor, the first slit, and the third via conductor, and the second via conductor, the second slit, and the fourth via conductor are disposed adjacent to each other. A high-frequency module.

2. The first via conductor group and the second via conductor group connect the first ground layer and the second ground layer. The high-frequency module according to Claim 1.

3. The second ground layer has a plurality of slits. In a plan view from the thickness direction of the mounting substrate, the plurality of slits of the first ground layer and the plurality of slits of the second ground layer overlap. The high-frequency module according to claim 2.

4. The first via conductor group, the second via conductor group, and the plurality of slits of the first ground layer are arranged at an end portion of the IC chip in a plan view from the thickness direction of the mounting substrate. The high-frequency module according to any one of claims 1 to 3.

5. In a plan view from the thickness direction of the mounting substrate, The first slit is long in a direction intersecting the direction connecting the first via conductor and the third via conductor. The width of the first slit is equal to or less than the distance between the first via conductor and the third via conductor. The high-frequency module according to any one of claims 1 to 3.

6. In a plan view from the thickness direction of the mounting substrate, the length of the first slit is two times or more the width of the first slit. The high-frequency module according to claim 5.

7. The IC chip further includes a plurality of inductors corresponding one-to-one to the plurality of low-noise amplifiers, Each of the plurality of inductors is connected between a corresponding low-noise amplifier among the plurality of low-noise amplifiers and a via conductor connected to the corresponding low-noise amplifier among the second via conductor group. In a plan view from the thickness direction of the mounting substrate, one inductor among the plurality of inductors overlaps the first slit. The high-frequency module according to any one of claims 1 to 3.

8. The plurality of via conductors included in the first via conductor group correspond one-to-one to the plurality of via conductors included in the second via conductor group, One of the plurality of slits is arranged between each of the plurality of via conductors included in the first via conductor group and the corresponding via conductor among the second via conductor group. The high-frequency module according to any one of claims 1 to 3.

9. The high-frequency module according to claim 1, A signal processing circuit connected to the high-frequency module, A communication device comprising the same.

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