Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor that has improved strength of side-margin sections even when the dimensions in the width direction of the side-margin sections are small.SOLUTION: A laminated ceramic capacitor 10 includes: a laminate 12; and a first external electrode 40 and a second external electrode 42 respectively formed on both end surfaces of the laminate 12. The laminate 12 has: an inner layer part 26; outer layer parts 28, 30; and side-margin parts 32, 34 that are arranged to sandwich the inner layer part 26 and the outer layer parts 28, 30 in a width direction. The laminate 12 further includes: a first internal electrode 22 connected to the first external electrode 40; and a second internal electrode 24 connected to the second external electrode 42. The first internal electrode 22 and the second internal electrode 24 each have an Si segregation part on the side-margin part side. The side-margin parts 32, 34 contain ceramic particles and Si. and Si is segregated between the ceramic particles.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This invention relates to a multilayer ceramic capacitor.

Background Art

[0002] In recent years, there has been a demand for multilayer ceramic capacitors with large capacitance and small size. Such a multilayer ceramic capacitor has, for example, a laminate formed in a rectangular parallelepiped shape, in which a dielectric layer for an inner layer on which an internal electrode is printed and the internal electrode are alternately laminated, and further, an outer layer ceramic layer is laminated on the upper and lower surfaces thereof. And it has external electrodes formed on both end faces of the laminate. In such a multilayer ceramic capacitor, in order to prevent the internal electrode from connecting to the external electrode on the side surface of the laminate, there is one in which a dielectric layer called a side margin portion is formed on the side surface.

[0003] Patent Document 1 discloses a method for manufacturing a multilayer ceramic capacitor having the side margin portion as described above. In the method for manufacturing a multilayer ceramic capacitor described in Patent Document 1, first, a conductive film serving as an internal electrode is laminated on a ceramic green sheet formed on the surface. Next, a mother laminate is formed, and when cutting the mother laminate, it is cut so that the conductive film is exposed on the side surface where the external electrode is not formed. As a result, a laminate chip is obtained. Then, a ceramic slurry serving as a side margin portion is applied to the internal electrodes exposed on both sides of the cut laminate chip. Thereby, since it becomes possible to form the internal electrode over the entire width of the laminate chip, it is possible to improve the acquisition efficiency of capacitance and reduce the variation in capacitance.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the multilayer ceramic capacitor of Patent Document 1, for example, when the thickness of the side margin portion, that is, the dimension along the width direction of the laminate is reduced for the purpose of obtaining a larger capacitance with a smaller size of the multilayer ceramic capacitor, sufficient strength of the side margin portion cannot be obtained. As a result, the multilayer ceramic capacitor of Patent Document 1 has a problem that sufficient flexural strength cannot be obtained. Further, cracks and chips are likely to occur in the side margin portion, and moisture enters through the cracks and chips. As a result, there is a problem that the insulation of the multilayer ceramic capacitor of Patent Document 1 deteriorates.

[0006] The main object of the present invention is to provide a multilayer ceramic capacitor with improved reliability, which can improve the strength of the side margin portion even when the dimension in the width direction of the side margin portion is small.

Means for Solving the Problems

[0007] The multilayer ceramic capacitor according to the present invention includes a dielectric layer and an internal electrode laminated in the lamination direction, and has a first main surface and a second main surface opposing in the lamination direction, a first end surface and a second end surface opposing in the length direction, and a first side surface and a second side surface opposing in the width direction. The multilayer ceramic capacitor includes a laminate, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface. The laminate includes an inner layer portion, an outer layer portion, and a side margin portion disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction. The internal electrode has a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode. The thickness in the width direction between the first internal electrode and the second internal electrode and the first side surface is 5 μm or more and 40 μm or less. The first internal electrode and the second internal electrode include a Si segregation portion on the side margin portion side. The side margin portion includes ceramic particles and Si, and Si is segregated between the ceramic particles. The multilayer ceramic capacitor is provided. In addition, in the multilayer ceramic capacitor according to the present invention, it is preferable that the segregation portion of Si is located within a range of 0.5 μm or less from the surface exposed on the side margin portion side of the first internal electrode and the second internal electrode toward the center in the width direction. Furthermore, in the multilayer ceramic capacitor according to the present invention, it is preferable that the Si contained in the end portions in the width direction of the first internal electrode and the second internal electrode is more than the Si contained in the central portion in the width direction of the first internal electrode and the second internal electrode. Moreover, in the multilayer ceramic capacitor according to the present invention, it is preferable that the segregation portion of Si is arranged along the stacking direction. In addition, in the multilayer ceramic capacitor according to the present invention, the side margin portion further contains Mg, and it is preferable that the first internal electrode and the second internal electrode further include a segregation portion of Mg on the side margin portion side. The multilayer ceramic capacitor according to the present invention includes a dielectric layer and an internal electrode stacked in the stacking direction, and includes a first main surface and a second main surface opposed in the stacking direction, a first end surface and a second end surface opposed in the length direction, and a first side surface and a second side surface opposed in the width direction. A multilayer body, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, the multilayer body includes an inner layer portion, an outer layer portion, and a side margin portion disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction. The internal electrode has a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode. The thickness in the width direction of the first internal electrode, the second internal electrode, and the first side surface is about 20 μm. Among the side margin portions, when a region of 4 μm in the width direction from the end portions in the width direction of the first internal electrode and the second internal electrode is defined as the inner layer and the other regions are defined as the outer layer, the amount of Si contained in the inner layer is less than the amount of Si contained in the outer layer. It is a multilayer ceramic capacitor. In addition, in the multilayer ceramic capacitor according to the present invention, it is preferable that the amount of Ba contained in the inner layer is more than the amount of Ba contained in the outer layer. Furthermore, in the multilayer ceramic capacitor according to the present invention, it is preferable that the voids included in the inner layer are more numerous than the voids included in the outer layer.

[0008] In the multilayer ceramic capacitor according to the present invention, the laminate includes an inner layer portion, an outer layer portion, and a side margin portion disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction. The internal electrodes have a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode. The thicknesses in the width direction of the first internal electrode and the second internal electrode and the first side surface are 5 μm or more and 40 μm or less. The first internal electrode and the second internal electrode are provided with a segregation portion of Si on the side margin portion side. In addition, the side margin portion contains ceramic particles and Si, and Si is segregated between the ceramic particles, so that the flexural strength of the multilayer ceramic capacitor can be improved. Also, in the multilayer ceramic capacitor according to the present invention, when a region of 4 μm in the width direction from the widthwise ends of the first internal electrode and the second internal electrode in the side margin portion is defined as the inner layer and the other regions are defined as the outer layer, the amount of Si contained in the inner layer is less than the amount of Si contained in the outer layer. Therefore, cracks and chips in the side margin portion are less likely to occur, and the entry of moisture can be prevented, so that the insulation of the multilayer ceramic capacitor can be ensured. As a result, a multilayer ceramic capacitor with improved reliability can be provided.

Advantages of the Invention

[0009] According to the present invention, even if the dimension in the width direction of the side margin portion is small, the strength of the side margin portion can be improved, and a multilayer ceramic capacitor with improved reliability can be provided.

[0010] The above objects, other objects, features, and advantages of the present invention will become more apparent from the following description of the embodiments for carrying out the invention with reference to the drawings.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0012] 1. Multilayer Ceramic Capacitor An embodiment of the multilayer ceramic capacitor according to the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is an external perspective view showing the multilayer ceramic capacitor of the embodiment. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1 showing the multilayer ceramic capacitor of the embodiment. FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1 showing the multilayer ceramic capacitor of the embodiment. FIG. 4 is an enlarged view of a portion C of FIG. 3 showing the multilayer ceramic capacitor of the embodiment.

[0013] As shown in FIG. 1, the multilayer ceramic capacitor 10 of this embodiment is generally composed of a laminate 12 and first and second external electrodes 40 and 42 formed on both end faces of the laminate 12, respectively.

[0014] When the size of the multilayer ceramic capacitor 10 according to the present invention is described as "dimension in the length (L) direction × dimension in the width (W) direction × dimension in the stacking (T) direction", for example, it is usually assumed to be sizes such as "1.6 mm × 0.8 mm × 0.8 mm", "1.0 mm × 0.5 mm × 0.5 mm", "0.6 mm × 0.3 mm × 0.3 mm", "0.4 mm × 0.2 mm × 0.2 mm", "0.2 mm × 0.1 mm × 0.1 mm".

[0015] As shown in FIG. 1, the laminate 12 is formed in a substantially rectangular parallelepiped shape. The laminate 12 has a first end face 13 and a second end face 14 extending along the width (W) direction and the stacking (T) direction, a first side face 15 and a second side face 16 extending along the length (L) direction and the stacking (T) direction, and a first main face 17 and a second main face 18 extending along the length (L) direction and the width (W) direction. The first end face 13 and the second end face 14 face each other, the first side face 15 and the second side face 16 face each other, and the first main face 17 and the second main face 18 face each other. Also, the first side face 15 and the second side face 16 are orthogonal to the first end face 13 and the second end face 14, and the first main face 17 and the second main face 18 are orthogonal to the first end face 13 and the first side face 15. Note that if the laminate 12 has a substantially rectangular parallelepiped shape, it is preferable that rounded portions or the like are formed at the corners and edges.

[0016] As shown in FIG. 2, in the laminate 12, a first internal electrode 22 is disposed at the interface between the inner-layer ceramic layers 20, and a second internal electrode 24 is disposed so as to sandwich the inner-layer ceramic layer 20 so as to face the first internal electrode 22. The inner layer portion 26 is constituted by laminating a plurality of such combinations of the inner-layer ceramic layer 20, the first internal electrode 22, and the second internal electrode 24. An outer layer portion 28 and an outer layer portion 30 are provided so as to sandwich the inner layer portion 26 in the lamination (T) direction. The outer layer portion 28 has a plurality of outer-layer ceramic layers 46, and the outer layer portion 30 has a plurality of outer-layer ceramic layers 48. Side margin portions 32 and 34 are provided so as to sandwich the inner layer portion 26 and the outer layer portions 28 and 30 in the width (W) direction. These side margin portions 32 and 34 are constituted by a plurality of side-margin ceramic layers. In other words, the inner layer portion 26 is a region sandwiched between a first internal electrode 22b closest to the first main surface 17 and a second internal electrode 24b closest to the second main surface 18 along the lamination (T) direction. Further, the side margin portions 32 and 34 are regions where the first internal electrode 22 and the second internal electrode 24 do not exist in a cross section of the laminate 12 viewed from the lamination (T) direction.

[0017] Each of the plurality of inner-layer ceramic layers 20 is formed so as to be sandwiched between the first internal electrode 22 and the second internal electrode 24. The inner-layer ceramic layer 20 is made of, for example, dielectric ceramic particles containing a perovskite-type compound containing Ba and Ti as a main component and having a perovskite structure. Further, at least one of Si, Mg, and Ba may be added as an additive to these main components. The additive exists between the ceramic particles. The thickness of the inner-layer ceramic layer 20 after firing is 0.2 μm or more and 10 μm or less.

[0018] In the laminate 12, the outer ceramic layers 46 and 48 that constitute the upper and lower outer layer portions 28 and 30 are formed of the same dielectric ceramic material as the inner ceramic layer 20. Note that the outer ceramic layers 46 and 48 may be formed of a material different from that of the inner ceramic layer 20. Further, when the outer ceramic layers 46 and 48 each have a multilayer structure, it is preferable that the segregation portions of the other outer ceramic layers 46 and 48 are more than the segregation portions of the Si of the outer ceramic layers 46 and 48 located closest to the first and second internal electrodes 22b and 24b. Thereby, the flexural strength from the lamination (T) direction side of the multilayer ceramic capacitor 10 can be improved. Note that the thickness of the outer layer portions 28 and 30 after firing is 15 μm or more and 40 μm or less. Note that each of the outer ceramic layers 46 and 48 may have a single-layer structure instead of a multilayer structure.

[0019] The first internal electrode 22 and the second internal electrode 24 face each other in the lamination (T) direction with the inner ceramic layer 20 therebetween. Capacitance is generated by the portion where the first internal electrode 22 and the second internal electrode 24 face each other with the inner ceramic layer 20 therebetween.

[0020] The inner ceramic layer 20 extends along the width (W) direction and the length (L) direction, and each of the plurality of first internal electrodes 22 extends in a flat plate shape along the inner ceramic layer 20. Each of the plurality of first internal electrodes 22 is drawn out to the first end face 13 of the laminate 12 and electrically connected to the first external electrode 40. Further, each of the plurality of second internal electrodes 24 extends in a flat plate shape so as to face the first internal electrode 22 with the inner ceramic layer 20 therebetween. Each of the plurality of second internal electrodes 24 is drawn out to the second end face 14 of the laminate 12 and electrically connected to the second external electrode 42.

[0021] The thickness of each of the first and second internal electrodes 22 and 24 is, for example, 0.3 μm or more and 2.0 μm or less. The first and second internal electrodes 22 and 24 preferably contain Ni. In addition to Ni, metals such as Cu, Ag, Pd, Ag-Pd alloy, and Au can be contained, for example. Note that the first and second internal electrodes 22 and 24 may contain the same dielectric particles as the inner layer ceramic layer 20.

[0022] As shown in FIG. 4, Si is segregated in the region including the surfaces exposed on the sides of the most side margin portions 32 and 34 of the first and second internal electrodes 22 and 24. Si has a segregation region in the internal electrodes within at least a range of 0.5 μm or less from the side margin portions toward the central portion in the width (W) direction, forming segregation portions 22a and 24a. In other words, the segregation portion 22a is formed on the sides of the side margin portions 32 and 34 of the first internal electrode 22, and the segregation portion 24a is formed on the sides of the side margin portions 32 and 34 of the second internal electrode 24. The flexural strength of the multilayer ceramic capacitor 10 is improved by these segregation portions 22a and 24a.

[0023] When the regions where the first internal electrode 22 and the second internal electrode 24 do not exist are defined as the side margin portions 32 and 34 in the cross section of the laminate 12 in the lamination (T) direction, the side margin portions 32 and 34 have a plurality of side margin layers, and the Si content in the other side margin layers is higher than that in the side margin layer closest to the internal electrodes 22 and 24. Therefore, the strength of the side margin portions 32 and 34 can be increased. Thereby, the flexural strength of the multilayer ceramic capacitor 10 can be improved. Further, cracks and chips are less likely to occur in the side margin portions 32 and 34, and the intrusion of moisture can be prevented. Thereby, the insulation of the multilayer ceramic capacitor 10 can be ensured. As a result, a highly reliable multilayer ceramic capacitor 10 can be obtained.

[0024] Further, in the laminate 12, the first internal electrode 22 and the second internal electrode 24 include segregation portions 22a and 24a on the side of the side margin portions 32 and 34. When the segregation portions 22a and 24a contain Si, the flexural strength of the multilayer ceramic capacitor can be further improved. Each of the side margin portions 32 and 34 has a multilayer structure including outer layers 32a and 34a located on the first and second side surfaces 15 and 16 sides of the laminate 12 and inner layers 32b and 34b located on the first and second internal electrodes 22 and 24 sides. It should be noted that the fact that the side margin portions 32 and 34 have a multilayer structure can be easily confirmed by observing with an optical microscope due to the difference in sinterability between the outer layers 32a and 34a and the inner layers 32b and 34b.

[0025] The dimensions in the width (W) direction of the side margin portions 32 and 34 after firing are, for example, 5 μm or more and 40 μm or less. More preferably, they are 20 μm or less. Also, the dimensions in the width (W) direction of the outer layers 32a and 34a are larger than the dimensions in the width (W) direction of the inner layers 32b and 34b. Specifically, the dimensions in the width (W) direction of the outer layers 32a and 34a are 5 μm or more and 20 μm or less. The dimensions in the width (W) direction of the inner layers 32b and 34b are 0.1 μm or more and 20 μm or less.

[0026] Note that the dimension in the width (W) direction of the side margin portions 32 and 34 in the present invention means the average dimension calculated based on the measurement results by measuring the dimensions of the side margin portions 32 and 34 at a plurality of positions along the lamination (T) direction. The measurement method is as follows. First, expose the surface including the width (W) direction and the lamination (T) direction of the multilayer ceramic capacitor 10 (hereinafter referred to as the "WT cross-section"). Next, image with an optical microscope so that the end portions in the width (W) direction of the first and second internal electrodes 22 and 24 and one of the side margin portions 32 and 34 in the WT cross-section are within the same visual field. The imaging positions are imaged at three positions: the upper part, the central part, and the lower part in the lamination (T) direction. Then, at the upper part, the central part, and the lower part, draw a plurality of line segments parallel to the width (W) direction from the end portions in the width (W) direction of the first and second internal electrodes 22 and 24 toward the first and second side surfaces 15 and 16, and measure the lengths of the respective line segments. For the lengths of the line segments measured in this way, calculate the average value for each of the upper part, the central part, and the lower part. Further, by averaging the respective average values, the thickness dimension of the side margin portions 32 and 34 is obtained.

[0027] The side margin portions 32 and 34 are made of a dielectric ceramic material having a perovskite structure composed of a main component such as BaTiO3. Si is added as an additive to these main components, and there are portions where these additives are segregated between the ceramic particles. Due to the presence of the segregated portions of Si, the flexural strength of the side margin portions 32 and 34 is improved. In the outer layers 32a and 34a, Si is added in an amount such that the mole number of Si / mole number of Ti is 3.0 or more and 7.0 or less, and in the inner layers 32b and 34b, Si is added in an amount such that the mole number of Si / mole number of Ti is 1.0 or more and 4.0 or less. In particular, the segregated portions of Si in the outer layers 32a and 34a are present in a larger amount than the segregated portions of Si in the inner layers 32b and 34b.

[0028] FIG. 5 is a view obtained by imaging a segregation portion of Si in a side margin portion included in the multilayer ceramic capacitor 10 with a wavelength dispersive X-ray analyzer (hereinafter referred to as WDX). The segregation portions of Si in the side margin portions 32 and 34 can be confirmed by observing with WDX after exposing the WT cross section at substantially the center in the length (L) direction of the laminate 12. Further, it can be confirmed that segregation portions 22a and 24a of Si are formed on the sides of the first and second internal electrodes 22 and 24 closest to the side margin portions 32 and 34. Note that segregation of not only Si but also Mg has been confirmed. FIGS. 6 to 8 are views obtained by imaging the same location (near the surface of the side margin portion) of the multilayer ceramic capacitor 10 with WDS, FIG. 6 is a view imaging the segregation portion of Mg, FIG. 7 is a view imaging the segregation portion of Ni, and FIG. 8 is a view imaging the segregation portion of Si.

[0029] The amount of Ba, which is an additive, between the ceramic particles of each of the inner layer ceramic layer 20, the outer layers 32a and 34a, and the inner layers 32b and 34b is inner layer ceramic layer 20 < outer layers 32a and 34a < inner layers 32b and 34b, is. Thus, the Ba content between the ceramic particles of each of the inner layer ceramic layer 20, the outer layers 32a and 34a, and the inner layers 32b and 34b is different. Note that the difference in the Ba content can be found by TEM analysis.

[0030] Also, the Ba content in the inner layer portion 26, the outer layers 32a and 34a, and the inner layers 32b and 34b of the side margin portions 32 and 34 is such that the molar ratio of Ti to 1 mol is, at the center value, for the outer layers 32a and 34a, greater than 1.01 and 1.020 or less, for the inner layers 32b and 34b, greater than 1.020 and less than 1.040, for the inner layer portion 26, greater than 0.99 and less than 1.01, is formulated as.

[0031] The method for confirming the above-mentioned molar ratio is as follows. First, polish the outer layers 32a, 34a and the inner layers 32b, 34b in the side margin portions 32, 34 of the laminate 12 from the side margin portions 32, 34 sides. Next, dissolve the powders of the outer layers 32a, 34a and the inner layers 32b, 34b obtained by polishing with an acid. Then, by performing ICP emission spectroscopic analysis, it is possible to confirm whether each of the outer layers 32a, 34a and the inner layers 32b, 34b has the above-mentioned molar ratio.

[0032] The content of Ba between the ceramic particles in the inner layers 32b, 34b is added in a range exceeding 100% and less than 140% with respect to the content of Ba between the ceramic particles in the outer layers 32a, 34a.

[0033] In addition, the side margin portions 32, 34 are formed such that the void portions decrease from the inner electrode side toward the side surface side. That is, the void portions in the outer layers 32a, 34a are less than the void portions in the inner layers 32b, 34b. Thereby, the intrusion of moisture from the side margin portions 32, 34 into the inside of the laminate 12 is suppressed, so that the moisture resistance of the multilayer ceramic capacitor 10 can be improved. Furthermore, the insulation of the multilayer ceramic capacitor 10 can be ensured.

[0034] (First and Second External Electrodes 40, 42) The first external electrode 40 is formed so as to cover the first end face 13 of the laminate 12 and is electrically connected to the first internal electrode 22 drawn out to the first end face 13 of the laminate 12. The second external electrode 42 is formed so as to cover the second end face 14 of the laminate 12 and is electrically connected to the second internal electrode 24 drawn out to the second end face 14 of the laminate 12.

[0035] As shown in FIGS. 1 and 2, the first external electrode 40 has a three-layer structure including a base electrode layer 40a, an underlying plating 40b formed on the surface of the base electrode layer 40a, and an upper plating 40c formed on the surface of the underlying plating 40b. The base electrode layer 40a is provided so as to cover the entire first end face 13 of the laminate 12, and from the portion covering the end face 13, it is provided so as to cover a part of each of the first side face 15 and the second side face 16 and a part of each of the first main face 17 and the second main face 18.

[0036] As shown in FIGS. 1 and 2, the second external electrode 42 has a three-layer structure including a base electrode layer 42a, an underlying plating 42b formed on the surface of the base electrode layer 42a, and an upper plating 42c formed on the surface of the underlying plating 42b. The base electrode layer 42a is provided so as to cover the entire second end face 14 of the laminate 12, and from the portion covering the end face 14, it is provided so as to cover a part of each of the first side face 15 and the second side face 16 and a part of each of the first main face 17 and the second main face 18.

[0037] The base electrode layers 40a and 42a preferably contain Cu formed by baking. In addition to Cu, for example, Ni, Ag, Pd, an Ag-Pd alloy, or Au can be included. Also, the base electrode layers 40a and 42a may be multiple layers. Note that the base electrode layers 40a and 42a may be formed by so-called co-firing simultaneously with the first internal electrode 22 and the second internal electrode 24, or may be formed by so-called post-firing by applying a conductive paste and baking. Also, the base electrode layers 40a and 42a may be formed by direct plating or may be formed by curing a resin layer containing conductive particles and a thermosetting resin.

[0038] The lower coatings 40b and 42b preferably contain Ni to prevent solder erosion. Also, the upper coatings 40c and 42c preferably contain Sn to enhance mountability. Note that the lower coatings 40b and 42b can contain, in addition to Ni, or the upper coatings 40c and 42c can contain, in addition to Sn, for example, Cu, Ag, Pd, Ag-Pd alloy, or Au. A conductive resin layer for stress relaxation may be formed between the base electrode layer 40a and the lower coating 40b, and between the base electrode layer 42a and the lower coating 42b. Also, the first and second external electrodes 40 and 42 may be formed by directly plating on the laminate 12.

[0039] Note that when directly plating as the external electrodes 40 and 42, and using Ni as the first and second internal electrodes 22 and 24, it is preferable to use Cu, which has good joinability with Ni, as the lower coatings 40b and 42b. Further, the upper coatings 40c and 42c preferably have a two-layer structure including an upper coating first layer formed on the surface of the lower coatings 40b and 42b, and an upper coating second layer formed on the surface of the upper coating first layer. The upper coating first layer preferably contains Ni having a function of preventing solder erosion. The upper coating second layer preferably contains Sn or Au having good solder wettability.

[0040] As shown in FIG. 3, in the multilayer ceramic capacitor 10 of this embodiment, its side margin portions 32 and 34 are composed of a plurality of layers. The side margin portion 32 has an outer layer 32a and an inner layer 32b. The inner layer 32b is disposed between the first and second internal electrodes 22 and 24 and the outer layer 32a. The Si content of the outer layer 32a, which is a side margin layer other than the inner layer 32b, is higher than that of the inner layer 32b disposed closest to the first and second internal electrodes 22 and 24. The side margin portion 34 has an outer layer 34a and an inner layer 34b. The inner layer 34b is disposed between the first and second internal electrodes 22 and 24 and the outer layer. The Si content of the outer layer 34a, which is a side margin layer other than the inner layer 34b, is higher than that of the inner layer 34b disposed closest to the first and second internal electrodes 22 and 24. Thereby, since the strength of the side margin portions 32 and 34 can be improved, the flexural strength of the multilayer ceramic capacitor 10 is improved. Further, cracks and chips are less likely to occur in the side margin portions 32 and 34, and moisture intrusion can be prevented, so that the insulation of the multilayer ceramic capacitor 10 can be ensured. As a result, a multilayer ceramic capacitor 10 with improved reliability can be provided. Also, an interface exists between the outer layers 32a and 34a and the inner layers 32b and 34b, and the stress applied to the multilayer ceramic capacitor 10 can be relaxed by this interface.

[0041] Also, in the multilayer ceramic capacitor 10 of this embodiment, the surface of the first and second internal electrodes 22 and 24 closest to the side margin portions 32 and 34 contains more Si than the central portions. As a result, the strength of the side margin portions 32 and 34 can be further improved.

[0042] Furthermore, in the multilayer ceramic capacitor 10 of this embodiment, when the Si content in the side margin portions 32 and 34 is calculated as the number of moles of Si / the number of moles of Ti, it is 1.0 or more and 7.0 or less. When the number of moles of Si / the number of moles of Ti is less than 1.0, the sintering of the side margin portions 32 and 34 becomes insufficient, the porosity increases, and sufficient improvement in flexural strength cannot be expected. On the other hand, when the number of moles of Si / the number of moles of Ti exceeds 7.0, Si diffuses excessively into the internal electrode, resulting in over-sintering and a decrease in reliability such as the insulation resistance value.

[0043] Moreover, in the multilayer ceramic capacitor 10 of this embodiment, in the width direction of the laminate 10, the dimensions of the side margin portions 32 and 34 are 5 μm or more and 40 μm or less. If the side margin portions 32 and 34 exceed 40 μm, the required capacitance cannot be ensured. If it is less than 5 μm, the sintering of the side margin portions 32 and 34 does not proceed sufficiently, and a dense side margin portion 32 and 34 cannot be obtained. If the side margin portion is not dense, moisture intrusion from the outside becomes easy.

[0044] 2. Manufacturing method of multilayer ceramic capacitor Next, the manufacturing method of the multilayer ceramic capacitor will be described. FIG. 9 is a diagram for explaining the manufacturing method of the multilayer ceramic capacitor of this embodiment, where (a) is a schematic diagram showing a ceramic green sheet on which a conductive film is formed, and (b) is a schematic diagram showing the state of laminating the ceramic green sheets on which the conductive films are formed. FIG. 10 is a perspective view showing an example of the appearance of a laminate chip obtained in the manufacturing method of the multilayer ceramic capacitor of this embodiment.

[0045] (1) Formation of laminate chip First, as a dielectric ceramic material, a perovskite compound containing Ba and Ti is prepared. At least one of Si, Mg, and Ba, as well as an organic binder, an organic solvent, a plasticizer, and a dispersant, are mixed with the dielectric powder obtained from this dielectric ceramic material at a predetermined ratio to produce a ceramic slurry. The ceramic slurry is formed into ceramic green sheets 50a and 50b on the surfaces of a plurality of resin films (not shown). The ceramic green sheet 50b is laminated alternately with the ceramic green sheet 50a, and the forming of the ceramic green sheet 50a (50b) is performed using, for example, a die coater, a gravure coater, and a microgravure coater.

[0046] Next, as shown in FIG. 9(a), a conductive paste for an internal electrode is printed in a stripe shape in the X direction on the surface of the ceramic green sheet 50a (50b) and dried. Hereinafter, the direction in which the conductive paste for the internal electrode extends in a stripe shape is defined as the X direction. Also, the width direction of the conductive films 52a and 52b is defined as the Y direction. In this way, the conductive films 52a (52b) that become the first internal electrode 22 (the second internal electrode 24) are formed. As the printing method, various methods such as screen printing, inkjet printing, and gravure printing can be used. The thickness of the conductive films 52a and 52b is, for example, 1.5 μm or less.

[0047] First, a predetermined number of ceramic green sheets without a formed conductive film that will become the outer layer portion 28 are stacked, and then, as shown in FIG. 9(b), a plurality of ceramic green sheets 50a and 50b printed with the conductive films 52a and 52b are shifted in the Y direction and laminated to form the inner layer portion 26. Further, a predetermined number of ceramic green sheets without a formed conductive film that will become the outer layer portion 30 are stacked on the inner layer portion 26 to obtain a mother laminate.

[0048] Next, the obtained mother laminate is pressed. As the method for pressing the mother laminate, methods such as rigid pressing and hydrostatic pressing can be used.

[0049] Next, the pressed mother laminate is cut into chip shapes to obtain laminate chips 60 shown in FIG. 10. As methods for cutting the mother laminate, various methods such as die cutting, dicing, and laser can be used.

[0050] As shown in FIG. 10, on one end face of the laminate chip 60 obtained through the above steps, only the conductive film 52a of the ceramic green sheet 50a is exposed. On the other end face, only the conductive film 52b of the ceramic green sheet 50b is exposed. On both side surfaces of the laminate chip 60, the conductive film 52a of the ceramic green sheet 50a and the conductive film 52b of the ceramic green sheet 50b are respectively exposed.

[0051] (2) Formation of Side Margin Portions Next, the procedure for producing ceramic green sheets for side margins that will become side margins 32 and 34 will be described.

[0052] First, a perovskite-type compound containing Ba and Ti is prepared as the dielectric ceramic material. At least one of Si, Mg, and Ba, as well as a binder resin, an organic solvent, a plasticizer, and a dispersant, are mixed with the dielectric powder obtained from this dielectric ceramic material at a predetermined ratio to produce a ceramic slurry.

[0053] Here, Si is added to the ceramic slurry that will become the outer layer 32a of the side margin 32 (and the outer layer 34a of the side margin 34). Specifically, Si is added such that the mole number of Si / the mole number of Ti is 1.0 or more and 7.0 or less. Also, Si is added to the ceramic slurry that will become the inner layer 32b of the side margin 32 (and the outer layer 34b of the side margin 34). Specifically, Si is added such that the mole number of Si / the mole number of Ti is 1.0 or more and 4.0 or less.

[0054] In addition, Ba is added to the ceramic slurry that forms the outer layer 32a of the side margin portion 32 (and the outer layer 34a of the side margin portion 34). Specifically, Ba is added such that the mole number of Ba / the mole number of Ti is 0.00 or more and less than 0.02. Also, Ba is added to the ceramic slurry that forms the inner layer 32b of the side margin portion 32 (and the outer layer 34b of the side margin portion 34). Specifically, Ba is added such that the mole number of Ba / the mole number of Ti is 0.02 or more and less than 0.04.

[0055] Furthermore, the amount of polyvinyl chloride (PVC) contained in the ceramic slurry that forms the outer layers 32a and 34a of the side margin portions 32 and 34 is greater than the amount of polyvinyl chloride (PVC) contained in the ceramic slurry that forms the inner portions 32b and 34b of the side margin portions 32 and 34.

[0056] Moreover, for the solvent contained in the ceramic slurry that forms the inner layers 32b and 34b of the side margin portions 32 and 34, an appropriate and optimal solvent is selected to prevent dissolution of the outer layer ceramic green sheet. Also, this inner layer ceramic green sheet has the role of adhering to the laminate chip 60.

[0057] Then, the ceramic slurry that forms the outer layers 32a and 34a is applied to the surface of the resin film and dried, thereby obtaining a ceramic green sheet for the outer layer.

[0058] Next, the ceramic slurry that forms the inner layers 32b and 34b is applied to the surface of the ceramic green sheet for the outer layer and dried, forming a ceramic green sheet for the inner layer. In this way, a ceramic green sheet for the side margin having a two-layer structure is obtained.

[0059] Here, the dimension along the width direction of the ceramic green sheet for the inner layer is preferably smaller than the dimension along the width direction of the ceramic green sheet for the outer layer. Specifically, for example, regarding the thickness after firing, the ceramic green sheet for the outer layer is formed to be 5 μm or more and 20 μm or less, and the ceramic green sheet for the inner layer is formed to be 0.1 μm or more and 20 μm or less.

[0060] In the above description, the case where the ceramic green sheet for the side margin having a two-layer structure is obtained by applying and drying the ceramic green sheet for the inner layer on the surface of the ceramic green sheet for the outer layer has been described. However, it is not limited to this case, and each of the ceramic green sheet for the outer layer and the ceramic green sheet for the inner layer may be formed in advance, and then a ceramic green sheet for the side margin having a two-layer structure may be obtained by laminating them. Note that the ceramic green sheet for the side margin is not limited to two layers, and may have a plurality of layers of three or more layers.

[0061] Next, the ceramic green sheet for the side margin is peeled off from the resin film.

[0062] Subsequently, the side surface where the conductive films 52a and 52b of the inner layer ceramic green sheet and the laminate chip 60 are exposed in the peeled ceramic green sheet for the side margin is opposed, pressed, and punched to form a layer that becomes the side margin portion 32. Further, for the side surface of the laminate chip 60 where the layer that becomes the side margin portion 32 is not formed, the side surface where the conductive films 52a and 52b of the laminate chip 60 are exposed and the inner layer ceramic green sheet are opposed, pressed, and punched to form a layer that becomes the side margin portion 34. At this time, it is preferable to previously apply an organic solvent serving as an adhesive to the side surface of the laminate chip 60.

[0063] Next, the laminated body chip 60 in which the layers that will become the side margin portions 32 and 34 are formed is degreased under predetermined conditions in a nitrogen atmosphere, and then fired at a predetermined temperature in a nitrogen-hydrogen-steam mixed atmosphere to obtain a sintered laminated body 12.

[0064] Next, an external electrode paste mainly composed of Cu is applied and baked on each of the two end faces of the sintered laminated body 12 to form a base electrode 40a connected to the first internal electrode 22 and a base electrode 42a connected to the second internal electrode. Further, lower layer plating 40b and 42b by Ni plating are formed on the surfaces of the base electrode layers 40a and 42a, and upper layer plating 40c and 42c by Sn plating are formed on the surfaces of the lower layer plating 40b and 42b, thereby forming the first and second external electrodes 40 and 42.

[0065] In the above manner, the multilayer ceramic capacitor 10 shown in FIG. 1 is manufactured.

[0066] Note that the side margin portions 32 and 34 may be formed by applying a ceramic slurry for side margin on both side surfaces where the conductive films 52a and 52b of the laminated body chip 60 are exposed.

[0067] That is, a ceramic slurry that will become the inner layers 32b and 34b is applied and dried on both side surfaces where the conductive films 52a and 52b of the laminated body chip 60 are exposed. Further, a ceramic slurry that will become the outer layers 32a and 34a is applied on the surfaces of the inner layers 32b and 34b.

[0068] In this case, the thicknesses of the ceramic slurries that will become the outer layers 32a and 34a and the inner layers 32b and 34b can be adjusted by changing the amount of resin contained in each ceramic slurry.

[0069] Further, the side margin portions 32 and 34 can be formed by masking both end faces of the laminate chip 60 with resin or the like, dipping the entire laminate chip 60 into a ceramic slurry that will become the inner layers 32b and 34b, drying it, and then dipping it into a ceramic slurry that will become the outer layers 32a and 34a. In this case, an inner layer and an outer layer are formed on the outer layer portions 28 and 30, resulting in a three-layer structure.

[0070] 3. Experimental Examples Hereinafter, experimental examples conducted by the inventors to confirm the effects of this invention will be described. In the experimental examples, each sample of the multilayer ceramic capacitor of the following-described examples and comparative examples was manufactured, and the hardness of the surface of the side margin portion of the multilayer ceramic capacitor was evaluated by measuring it with a Vickers hardness tester.

[0071] (Examples) First, in the examples, samples of the multilayer ceramic capacitor shown in FIG. 1 were manufactured by the method described above. In this case, the outer dimensions of the multilayer ceramic capacitor were 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height. In the examples, a multilayer ceramic capacitor having a side margin portion with a two-layer structure composed of an inner layer containing Si such that the mole number of Si / mole number of Ti is 3.5 with respect to Ti and an outer layer containing Si such that the mole number of Si / mole number of Ti is 5 with respect to Ti was prepared. Also, the thickness of the side margin portion was 20 μm. Regarding the side margin portion of the examples, the thickness of the outer layer was 16 μm and the thickness of the inner layer was 4 μm.

[0072] (Comparative Examples) In the comparative examples, a multilayer ceramic capacitor was manufactured under the same conditions as in the examples, except that a side margin portion with a single-layer structure containing Si such that the mole number of Si / mole number of Ti is 3.5 with respect to Ti was provided without providing a side margin portion composed of two layers of an inner layer and an outer layer.

[0073] (Evaluation Method) Five samples of each of the multilayer ceramic capacitors of the above-described examples and comparative examples were prepared, and the hardness of the surface of the side margin portion on both side surfaces of the multilayer ceramic capacitor was measured with a Vickers hardness tester. The measurement conditions for the Vickers hardness were a measurement load of 200 gf and a dwell time at the bottom dead center of 10 s. Further, the pore area ratio in the vicinity of the surface of the side margin portion of each sample of the multilayer ceramic capacitors of the examples and comparative examples was calculated. This pore area ratio is obtained by exposing the surface including the side margin portion and imaging it with an SEM. Image processing is performed on the captured image to measure the area of the pores. The ratio of the area of the pores to the area of the multilayer ceramic capacitor shown in the captured image is calculated as the pore area ratio.

[0074] FIG. 11 is a diagram showing the relationship between the pore area ratio in the vicinity of the surface of the side margin portion and the Vickers hardness of the surface of the side margin portion. As a result of the experiment, as shown in FIG. 11, in the multilayer ceramic capacitor of the example, the pore area ratio in the vicinity of the surface of the side margin portion was 0.3%, and the Vickers hardness of the surface of the side margin portion was 1470 MPa or more and 1680 MPa or less. On the other hand, as shown in FIG. 11, in the multilayer ceramic capacitor of the comparative example, the pore area ratio in the vicinity of the surface of the side margin portion was 1.9%, and the Vickers hardness of the surface of the side margin portion was 1140 MPa or more and 1270 MPa or less. From the above, it became clear that the flexural strength of the multilayer ceramic capacitor of the example was improved compared to that of the multilayer ceramic capacitor of the comparative example.

[0075] Note that the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist thereof.

Explanation of Reference Numerals

[0076] 10 Multilayer ceramic capacitor 12 Laminate 13 First end face 14 Second end face 15 First side face 16 Second side face 17 First main face 18 Second main surface 20 Ceramic layer for inner layer 22 First internal electrode 22a, 24a Segregation part 22b First internal electrode closest to the first main surface 24 Second internal electrode 24b Second internal electrode closest to the second main surface 26 Inner layer part 28, 30 Outer layer part 32, 34 Side margin part 32a, 34a Outer layer 32b, 34b Inner layer 40 First external electrode 42 Second external electrode 40a, 42a Base electrode layer 40b, 42b Lower plating 40c, 42c Upper plating 46, 48 Ceramic layer for outer layer 50a, 50b Ceramic green sheet 52a, 52b Conductive film 60 Multilayer chip

Claims

1. A laminate including dielectric layers and internal electrodes laminated in a stacking direction, having a first main surface and a second main surface opposing each other in the stacking direction, a first end surface and a second end surface opposing each other in a length direction, and a first side surface and a second side surface opposing each other in a width direction; A first external electrode disposed on the first end surface; A second external electrode disposed on the second end surface and comprising: wherein the laminate has an inner layer portion; an outer layer portion; and a side margin portion disposed so as to sandwich the inner layer portion and the outer layer portion from the width direction, and comprising: wherein the internal electrodes have a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode; wherein the thicknesses in the width direction of the first internal electrode and the second internal electrode and the first side surface are 5 μm or more and 40 μm or less; wherein the first internal electrode and the second internal electrode have a segregation portion of Si on the side of the side margin portion; wherein the side margin portion contains ceramic particles and Si; a multilayer ceramic capacitor in which Si is segregated between the ceramic particles.

2. The multilayer ceramic capacitor according to claim 1, wherein the segregation portion of Si is located within a range of 0.5 μm or less from the surface exposed on the side of the side margin portion of the first internal electrode and the second internal electrode toward the center in the width direction.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein Si contained in the end portions in the width direction of the first internal electrode and the second internal electrode is more than Si contained in the central portion in the width direction of the first internal electrode and the second internal electrode.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the segregation portion of Si is arranged along the stacking direction.

5. wherein the side margin portion further contains Mg; The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the first internal electrode and the second internal electrode further have a segregation portion of Mg on the side of the side margin portion.

6. A laminate including dielectric layers and internal electrodes laminated in a stacking direction, having a first main surface and a second main surface opposing each other in the stacking direction, a first end surface and a second end surface opposing each other in a length direction, and a first side surface and a second side surface opposing each other in a width direction; A first external electrode disposed on the first end surface; A second external electrode disposed on the second end surface and comprising: The laminate includes: an inner layer portion; an outer layer portion; and a side margin portion disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction. The internal electrodes include a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode. The thickness in the width direction between the first internal electrode and the second internal electrode and the first side surface is about 20 μm. When a region of 4 μm in the width direction from the end portions in the width direction of the first internal electrode and the second internal electrode is defined as an inner layer and the other regions are defined as outer layers in the side margin portion, a multilayer ceramic capacitor in which the amount of Si contained in the inner layer is less than the amount of Si contained in the outer layer.

7. The multilayer ceramic capacitor according to claim 6, wherein the amount of Ba contained in the inner layer is greater than the amount of Ba contained in the outer layer.

8. The multilayer ceramic capacitor according to claim 6 or claim 7, wherein the inner layer contains more voids than the outer layer. ​

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