Display device

Abstract

To improve the opening ratio of a semiconductor device.SOLUTION: A display device includes a driving circuit including a first thin film transistor and a pixel including a second thin film transistor on the same substrate. The first thin film transistor includes a first gate electrode layer, a gate insulating layer, a first oxide semiconductor layer, a first oxide conductive layer and a second oxide conductive layer, an oxide insulating layer in contact with a part of the first oxide semiconductor layer and in contact with a periphery and a side surface of the first oxide conductive layer and the second oxide conductive layer, a first source electrode layer, and a first drain electrode layer. The second thin film transistor includes a second gate electrode layer, a second oxide semiconductor layer, and a second source electrode layer and a second drain electrode layer formed of a material with a light-transmitting property.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices such as display devices, semiconductor circuits, and electronic devices are all semiconductor devices. There is.

Background Art

[0003] In recent years, a technique for forming a thin film transistor (also referred to as a TFT: Thin Film Transistor) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. The thin film transistor is widely applied to electronic devices such as ICs and electro-optical devices, and in particular, development as a switching element for an image display device has been urgently required.

[0004] Among metal oxides, some exhibit semiconductor characteristics. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. A thin film transistor having such a metal oxide exhibiting semiconductor characteristics as a channel formation region is already known (Patent Document 1 and Patent Document 2).

[0005]

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] When manufacturing a plurality of thin film transistors on an insulating surface, for example, there is a portion where a gate wiring and a source wiring intersect. An insulating layer is provided between the gate wiring and the source wiring having a different potential from the gate wiring at the intersecting portion, and the insulating layer becomes a dielectric to generate a capacitance. This capacitance is also called a parasitic capacitance between wirings, and there is a risk of signal waveform distortion. In addition, if the parasitic capacitance is large, there is a risk that signal transmission will be slow.

[0007] Moreover, an increase in parasitic capacitance leads to a crosstalk phenomenon in which an electrical signal leaks between wirings and an increase in power consumption.

[0008] In an active matrix type display device, in particular, if a large parasitic capacitance is formed between a signal wiring for supplying a video signal and another wiring or electrode, there is a risk that the display quality will deteriorate.

[0009] Also, even when miniaturizing a circuit, the wiring pitch becomes narrow, and there is a risk that the parasitic capacitance between wirings will increase.

[0010] One aspect of the present invention is to provide a semiconductor device having a configuration capable of sufficiently reducing the parasitic capacitance between wirings.

[0011] When forming a drive circuit on an insulating surface, the operating speed of the thin film transistor used in the drive circuit is preferably fast.

[0012] ​​​​​​ For example, shortening the channel length (also referred to as L) of a thin-film transistor or widening the channel width (also referred to as W) increases the operating speed. However, when the channel length is shortened, there is a problem that the etching characteristics, such as the on-off ratio, become small. Also, when the channel width W is widened, there is a problem of increasing the capacitance load of the thin-film transistor itself. In addition, it is also an object to provide a semiconductor device including a thin-film transistor having stable electrical characteristics even when the channel length is short. When forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a driving circuit on the same substrate, the thin-film transistor used for the pixel portion is required to have excellent switching characteristics, such as a large on-off ratio, and the thin-film transistor used for the driving circuit is required to have a high operating speed. In particular, the higher the definition of the display device, the shorter the writing time of the display image is required. Therefore, it is preferable that the thin-film transistor used for the driving circuit has a high operating speed. In addition, one aspect of the present invention is to provide a semiconductor device that prevents a complicated process and an increase in manufacturing cost, forms a plurality of types of circuits on the same substrate, and includes a plurality of types of thin-film transistors adapted to the characteristics of the plurality of types of circuits.

[0013] One aspect of the present invention has a driving circuit and a pixel portion on the same substrate, and each of the driving circuit and the pixel portion has a thin-film transistor. The driving circuit and the pixel portion are fabricated on the same substrate.

[0014] When forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a driving circuit on the same substrate, the thin-film transistor used for the pixel portion is required to have excellent switching characteristics, such as a large on-off ratio, and the thin-film transistor used for the driving circuit is required to have a high operating speed. In particular, the higher the definition of the display device, the shorter the writing time of the display image is required. Therefore, it is preferable that the thin-film transistor used for the driving circuit has a high operating speed. When forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a driving circuit on the same substrate, the thin-film transistor used for the pixel portion is required to have excellent switching characteristics, such as a large on-off ratio, and the thin-film transistor used for the driving circuit is required to have a high operating speed. In particular, the higher the definition of the display device, the shorter the writing time of the display image is required. Therefore, it is preferable that the thin-film transistor used for the driving circuit has a high operating speed.

[0015] One aspect of the present invention is to provide a semiconductor device that prevents a complicated process and an increase in manufacturing cost, forms a plurality of types of circuits on the same substrate, and includes a plurality of types of thin-film transistors adapted to the characteristics of the plurality of types of circuits. Means for Solving the Problems

[0016] One aspect of the present invention has a driving circuit and a pixel portion on the same substrate, and each of the driving circuit and the pixel portion has a thin-film transistor. The driving circuit and the pixel portion are fabricated on the same substrate. Thereby, the manufacturing cost is reduced.

[0017] In one aspect of the present invention, the thin film transistor of the driving circuit (also referred to as the first thin film transistor) and the thin film transistor of the pixel portion (also referred to as the second thin film transistor) are bottom gate type thin film transistors, each having a gate electrode (also referred to as a gate electrode layer), a source electrode (also referred to as a source electrode layer), and a drain electrode (also referred to as a drain electrode layer), and a semiconductor layer having a channel formation region.

[0018] In one aspect of the present invention, the gate electrode, source electrode, and drain electrode of the thin film transistor in the pixel portion are formed of a conductive layer having translucency, and the semiconductor layer is formed of a translucent semiconductor layer. That is, the thin film transistor in the pixel portion is formed of a material having translucency. Thereby, the aperture ratio of the pixel portion is improved.

[0019] Also, in one aspect of the present invention, the gate electrode of the thin film transistor in the driving circuit is formed of the same material as the gate electrode of the thin film transistor in the pixel portion or a material having a lower resistance value than the material used for the gate electrode of the thin film transistor in the pixel portion, and the source electrode and drain electrode of the thin film transistor in the driving circuit are formed of a material having a lower resistance value than the source electrode and drain electrode of the thin film transistor in the pixel portion. Therefore, the resistance values of the source electrode and drain electrode of the thin film transistor in the pixel portion are higher than the resistance values of the source electrode and drain electrode of the thin film transistor in the driving circuit.

[0020] Also, in one aspect of the present invention, the thin film transistor of the driving circuit has a semiconductor layer and a source electrode It is a structure having a conductive layer between layers and between the semiconductor layer and the drain electrode. The resistance value of the conductive layer is preferably lower than that of the semiconductor layer and higher than that of the source electrode layer and the drain electrode layer. Thereby, the operating speed of the drive circuit is improved.

[0021] Also, in one aspect of the present invention, the thin film transistor of the drive circuit is in contact with a part of the semiconductor layer and has an oxide insulating layer in contact with the periphery and side surfaces of the conductive layer between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode. By adopting the structure having the oxide insulating layer the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it is increased, thereby reducing the parasitic capacitance. By reducing the parasitic capacitance the sag of the signal waveform can be suppressed. Further, in the thin film transistor of the drive circuit the source electrode is in contact with the conductive layer provided between the semiconductor layer and the source electrode, and the drain electrode is in contact with the conductive layer provided between the semiconductor layer and the drain electrode.

[0022] One aspect of the present invention has a drive circuit having a first thin film transistor and a pixel having a second thin film transistor on the same substrate. The first thin film transistor includes a first gate electrode layer a gate insulating layer provided on the first gate electrode layer, a first oxide semiconductor layer provided on the first gate electrode layer with the gate insulating layer interposed therebetween and having a first channel formation region a first oxide conductive layer and a second oxide conductive layer provided on the first oxide semiconductor layer an oxide insulating layer in contact with a part of the oxide semiconductor layer and in contact with the periphery and side surfaces of the first oxide conductive layer and the second oxide conductive layer, a first source electrode layer in contact with the first oxide conductive layer, and a first ​​​​​It has a first drain electrode layer in contact with the oxide conductive layer of 2, and the second thin film transistor , a second gate electrode layer made of a material having translucency, and the second is provided on the second gate electrode layer with a gate insulating layer interposed therebetween, and has a second oxide semiconductor layer having a second channel formation region, and a second source electrode layer and a second drain electrode layer made of a material having translucency, which are provided on the second oxide semiconductor layer.

[0023] One aspect of the present invention is that the source electrode layer and the drain electrode layer of the first thin film transistor are a conductive layer mainly composed of an element selected from Al , Cr, Cu, Ta, Ti, Mo, and W, or a semiconductor device may be composed of a laminate combining them.

[0024] One aspect of the present invention is that the source electrode layer and the drain electrode layer of the second thin film transistor are indium oxide, indium tin oxide alloy, indium zinc oxide alloy, or zinc oxide , and a semiconductor device may be used.

[0025] One aspect of the present invention is that a capacitor portion is provided on the same substrate as the first thin film transistor and the second thin film transistor. The capacitor portion has a capacitor wiring and a capacitor electrode overlapping the capacitor wiring, and the capacitor wiring and the capacitor electrode may be a semiconductor device having translucency.

[0026] One aspect of the present invention is that a semiconductor device may have a conductive layer overlapping the channel formation region of the first oxide semiconductor layer on the oxide insulating layer of the first thin film transistor.

[0027] One aspect of the present invention is that a semiconductor device may be such that the first oxide conductive layer and the second oxide conductive layer are made of the same material as the source electrode layer and the drain electrode layer of the second thin film transistor ​​​​ 。

[0028] One aspect of the present invention is a method of manufacturing a semiconductor device having a driving circuit with a first thin film transistor and a pixel portion with a second thin film transistor on the same substrate, the method including forming a first gate electrode layer and a second gate electrode layer, forming a gate insulating layer on the first gate electrode layer and the second gate electrode layer, forming a first oxide semiconductor layer on the first gate electrode layer with the gate insulating layer therebetween, and forming a second oxide semiconductor layer on the second gate electrode layer with the gate insulating layer therebetween, dehydrating or dehydrogenating the first oxide semiconductor layer and the second oxide semiconductor layer, forming an oxide conductive film on the first oxide semiconductor layer and the second oxide semiconductor layer, removing a part of the oxide conductive film to form a first oxide conductive layer on the first oxide semiconductor layer and a second oxide conductive layer, forming a second source electrode layer and a second drain electrode layer on the second oxide semiconductor layer, forming an oxide insulating layer on the first oxide conductive layer, the second oxide conductive layer, the second source electrode layer, and the second drain electrode layer, removing a part of the oxide insulating layer to expose a part of the first oxide conductive layer and a part of the second oxide conductive layer, forming a first source electrode layer in contact with the exposed first oxide conductive layer, and forming a first drain electrode layer in contact with the exposed second oxide conductive layer. The method is characterized by the above steps and is a method of manufacturing a semiconductor device. removing a part of the oxide insulating layer to expose a part of the first oxide conductive layer and a part of the second oxide conductive layer, forming a first source electrode layer in contact with the exposed first oxide conductive layer, and forming a first drain electrode layer in contact with the exposed second oxide conductive layer. The method is characterized by the above steps and is a method of manufacturing a semiconductor device. of manufacturing a semiconductor device.

[0029] One aspect of the present invention is to form a resist mask using a multi-tone mask and perform etching using the resist mask, thereby forming a first oxide semiconductor layer, a second oxide semiconductor layer, a first oxide conductive layer, a second oxide conductive layer, a second source electrode layer, and a second drain electrode layer. A method for manufacturing a semiconductor device characterized by forming a layer may also be used.

[0030] In addition, as the oxide semiconductor used in this specification, for example, there is a metal oxide represented by InMO3(ZnO)m (m> 0). A thin film containing the metal oxide is formed, and a thin film transistor using the thin film as an oxide semiconductor layer is manufactured. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, may be included. In addition, in the above oxide semiconductor, in addition to the metal elements contained as M, as impurity elements, Fe, Ni, other transition metal elements, or oxides of the transition metals may be included. In this specification, among the oxide semiconductor layers having a structure represented by InMO3(ZnO)m (m>0 and m is not an integer), an oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also referred to as an In-Ga-Zn- O-based semiconductor film. In addition, as the metal oxide applied to the oxide semiconductor layer, in addition to the above, metal oxides of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In- O system, Sn-O system, Zn-O system can be applied. In addition, silicon oxide may be included in the oxide semiconductor layer composed of the above metal oxide.

[0031]

[0032] The oxide semiconductor is preferably an oxide semiconductor containing In, and more preferably In and

[0032] It is an oxide semiconductor containing Bi and Ga. In order to make the oxide semiconductor layer intrinsic (type I), dehydration or dehydrogenation is effective.

[0033] In the manufacturing process of the semiconductor device, when heat treatment is performed in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) , the oxide semiconductor layer becomes oxygen-deficient type by the heat treatment and has a lower resistance, that is, it becomes N-type (N -type, etc.). Then, by forming an oxide insulating layer in contact with the oxide semiconductor layer and making the oxide semiconductor layer in an oxygen-excessive state, the oxide - semiconductor layer can be made to have a higher resistance, that is, be made into type I. Thereby, it becomes possible to manufacture and provide a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability. .

[0034] Also, in the manufacturing process of the semiconductor device, as dehydration or dehydrogenation, in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), a heat treatment is performed at 350 °C or higher, preferably 40 0 °C or higher and below the distortion point of the substrate, for example, 400 °C or higher and 700 °C or lower, more preferably 420 °C or higher and 570 °C or lower to reduce impurities such as the contained moisture in the oxide semiconductor layer.

[0035] Even when the oxide semiconductor layer subjected to dehydration or dehydrogenation is measured by temperature-programmed desorption spectroscopy (also referred to as TDS) up to 4 50 °C, two peaks of water and at least one peak appearing around 300 °C are not detected. Therefore, even when the thin-film transistor using the oxide semiconductor layer subjected to dehydration or dehydrogenation is measured by TDS up to 450 °C, at least the peak of water appearing around 300 °C is not detected.

[0036] In the manufacturing process of the semiconductor device, the oxide semiconductor layer is not exposed to the air. It is important not to allow water or hydrogen to be mixed into the oxide semiconductor layer again. The oxide semiconductor layer is then siliconized to reduce its resistance, i.e., to become an N-type (N - After the hydrogen is absorbed, oxygen is supplied. By supplying the oxide semiconductor layer with a high resistance, a thin film transistor can be fabricated. In this case, the threshold voltage value of the thin film transistor can be made positive, and the so-called normally-off A switching element can be realized. The gate voltage of the thin film transistor is as close to 0V as possible. It is desirable for a channel to be formed at a positive threshold voltage. If the threshold voltage is negative, even if the gate voltage is 0V, For example, in an active matrix type In display devices, the electrical characteristics of the thin-film transistors that make up the circuits are important. The electrical characteristics of thin film transistors affect the performance of display devices. For example, thin film transistors have high field effect mobility characteristics. Even if it has a high threshold voltage, or if the threshold voltage is negative, the circuit In addition, in the case of thin film transistors with high threshold voltages, When the driving voltage is low, the TFT cannot perform its switching function and the load For example, in the case of an n-channel thin film transistor, a positive potential is applied to the gate electrode. The desired transistor is one in which a channel is formed and drain current begins to flow only when a voltage is applied. It is preferable to use transistors that do not form a channel unless the driving voltage is high, or transistors that operate under negative voltage conditions. However, a transistor in which a channel is formed and a drain current flows is not suitable as a thin-film transistor used in a circuit.

[0037] Further, the gas atmosphere for lowering the temperature from the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere heated up to the heating temperature T. For example, without exposing to the air in the same furnace where dehydration or dehydrogenation has been performed, the inside of the furnace is filled with high-purity oxygen gas or N2O gas and cooled.

[0038] After reducing the moisture content in the film by a heat treatment for dehydration or dehydrogenation, the oxide semiconductor film is slowly cooled (or cooled) in an atmosphere containing no moisture (dew point is -40°C or lower, preferably -60°C or lower) to improve the electrical characteristics of the thin-film transistor and realize a thin-film transistor having both mass productivity and high performance.

[0039] In this specification, a heat treatment under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) is referred to as a heat treatment for dehydration or dehydrogenation. In this specification, it is not only the desorption of H2 by this heat treatment that is called dehydrogenation, but for the sake of convenience, dehydration or dehydrogenation includes the desorption of H, OH, etc.

[0040] In the manufacturing process of the semiconductor device, when a heat treatment is performed under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.), the oxide semiconductor layer becomes oxygen-deficient type by the heat treatment and has a lower resistance, that is, becomes N-type (N-type conversion, etc.). As a result, in the oxide semiconductor layer, there is a high-resistance source region (HRS (High - Resistance Source) region) that is oxygen-deficient and overlaps with the source electrode layer. A high-resistance drain region (also referred to as an HRD (High Resistance Drain) region), which is oxygen-deficient and overlaps with the drain electrode layer, is formed. A high-resistance drain region (also referred to as an HRD (High Resistance Drain) region), which is oxygen-deficient and overlaps with the drain electrode layer, is formed. A high-resistance drain region (also referred to as an HRD (High Resistance Drain) region), which is oxygen-deficient and overlaps with the drain electrode layer, is formed.

[0041] Specifically, the carrier concentration of the high-resistance drain region is 1×10 18 / cm 3 or more, and is higher than at least the carrier concentration (less than 1×10 18 / cm 3 ) of the channel formation region. Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature. Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature.

[0042] Also, a low-resistance source region (also referred to as an LRS (Low Resistance Sorce) region) and a low-resistance drain region (also referred to as an LRD (Low Resistance Drain) region) may be formed between the drain electrode layer made of a metal material and the oxide semiconductor layer. Also, a low-resistance source region (also referred to as an LRS (Low Resistance Sorce) region) and a low-resistance drain region (also referred to as an LRD (Low Resistance Drain) region) may be formed between the drain electrode layer made of a metal material and the oxide semiconductor layer. Also, a low-resistance source region (also referred to as an LRS (Low Resistance Sorce) region) and a low-resistance drain region (also referred to as an LRD (Low Resistance Drain) region) may be formed between the drain electrode layer made of a metal material and the oxide semiconductor layer. Specifically, the carrier concentration of the low-resistance drain region is larger than that of the high-resistance drain region (HRD region), for example, within the range of 1×10 / cm 20 or more and 1×10 3 / cm 21 or less. 3 Note that the carrier concentration of the low-resistance drain region is larger than that of the high-resistance drain region (HRD region), for example, within the range of 1×10 or more and 1×10

[0043] Then, by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the oxide semiconductor layer is further made higher in resistance, that is, type-I, to form a channel formation region. Then, by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the oxide semiconductor layer is further made higher in resistance, that is, type-I, to form a channel formation region. Note that as a method of making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, for example, sputtering is performed so as to contact the dehydrated or dehydrogenated oxide semiconductor layer. Note that as a method of making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, for example, sputtering is performed so as to contact the dehydrated or dehydrogenated oxide semiconductor layer. Examples of methods for forming an oxide insulating layer include the G method. Further, after forming the oxide insulating layer heat treatment (for example, heat treatment in an atmosphere containing oxygen), heating in an inert gas atmosphere and then cooling in an oxygen atmosphere, or cooling with ultra-dry air (dew point of -40°C or lower, preferably -6 0°C or lower) may be performed.

[0044] Also, at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer is used as a channel formation region. By selectively making it in an oxygen-excessive state, the oxide semiconductor layer can be made highly resistive, that is, type-I. Further, a source electrode layer or a drain electrode layer made of a metal such as Ti is formed in contact with the dehydrated or dehydrogenated oxide semiconductor layer and a channel formation region can be formed by selectively making the exposed region of the oxide semiconductor layer that does not overlap with the source electrode layer or the drain electrode layer in an oxygen-excessive state. When the oxide semiconductor layer is selectively put in an oxygen-excessive state, a high-resistance source region overlapping with the source electrode layer and a high-resistance drain region overlapping with the drain electrode layer are formed, and the region between the high-resistance source region and the high-resistance drain region becomes the channel formation region. That is, the channel formation region is self-alignedly formed between the source electrode layer and the drain electrode layer. When the oxide semiconductor layer is selectively put in an oxygen-excessive state, a high-resistance source region overlapping with the source electrode layer and a high-resistance drain region overlapping with the drain electrode layer are formed, and the region between the high-resistance source region and the high-resistance drain region becomes the channel formation region. That is, the channel formation region is self-alignedly formed between the source electrode layer and the drain electrode layer. That is, the channel formation region is self-alignedly formed between the source electrode layer and the drain electrode layer.

[0045] According to one aspect of the present invention, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0046] In addition, by forming a high-resistance drain region (and a high-resistance source region) in the oxide semiconductor layer overlapping with the drain electrode layer (and the source electrode layer), the reliability of the drive circuit is improved. It can be illustrated. Specifically, by forming a high-resistance drain region, the conductivity can be gradually changed from the drain electrode layer to the high-resistance drain region and the channel formation region. Therefore, when operating by electrically connecting the drain electrode layer to a wiring that supplies a high power supply potential V DD, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high-resistance drain region serves as a buffer and local electric field concentration does not occur, and the breakdown voltage of the transistor can be improved.

[0047] Also, by forming a high-resistance drain region (and a high-resistance source region), the leakage current of the drive circuit can be reduced. Specifically, by forming a high-resistance source region and a high-resistance drain region, the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer flows through the drain electrode layer, the high-resistance drain region, the channel formation region, the high-resistance source region, and the source electrode layer. At this time, in the channel formation region, the leakage current flowing from the high-resistance drain region to the channel formation region is concentrated near the interface between the gate insulating layer, which becomes high resistance when the transistor is in the off state, and the channel formation region, and the leakage current in the back channel part ( a part of the surface of the channel formation region away from the gate electrode layer) can be reduced.

[0048] Also, the high-resistance source region overlapping the source electrode layer and the high-resistance drain region overlapping the drain electrode layer, although depending on the width of the gate electrode layer, by having a structure that overlaps a part of the gate electrode layer via the gate insulating layer, the electric field strength near the end of the drain electrode layer can be more effectively relaxed.

[0049] ​​​​​​ Note that the ordinal numbers assigned as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate specific names for matters for identifying the invention in this specification.

[0050] In addition, as a display device having a drive circuit, in addition to a liquid crystal display device, there are also a light-emitting display device using a light-emitting element and a display device also called electronic paper using an electrophoretic display element.

[0051] In a light-emitting display device using a light-emitting element, the pixel portion has a plurality of thin-film transistors, and there are portions in the pixel portion where the gate electrode of a thin-film transistor and the source wiring (also referred to as a source wiring layer) or drain wiring (also referred to as a drain wiring layer) of another transistor are connected. Also, in the drive circuit of a light-emitting display device using a light-emitting element, there are portions where the gate electrode of a thin-film transistor and the source wiring or drain wiring of that thin-film transistor are connected.

[0052] Also, in a liquid crystal display device, when forming a pixel portion and a drive circuit on the same substrate, in the drive circuit, thin-film transistors constituting logic gates such as an inverter circuit, a NAND circuit, a NOR circuit, and a latch circuit, and thin-film transistors constituting analog circuits such as a sense amplifier, a constant voltage generation circuit, and a VCO have only a positive polarity or only a negative polarity applied between the source electrode and the drain electrode. Therefore, the width of the high-resistance drain region that requires breakdown voltage may be designed to be wider than the width of the high-resistance source region. Also, the width of the high-resistance source region and the width of the high-resistance drain region overlapping the gate electrode layer may be widened.

[0053] ​​​​​​​​​​​​​​​ In addition, the thin film transistor disposed in the driving circuit is a thin film transistor having a single gate structure for explanation purposes. However, if necessary, a multi-gate structure having a plurality of channel formation regions can also be formed as a thin film transistor.

[0054] In addition, in the liquid crystal display device, in order to prevent deterioration of the liquid crystal, AC driving is performed. By this AC driving the polarity of the signal potential applied to the pixel electrode layer is inverted to positive or negative polarity every certain period. The TFT electrically connected to the pixel electrode layer has a pair of electrodes alternately serving as the source electrode layer and the drain electrode layer. In this specification, for convenience, one of the pair of electrodes of the thin film transistor of the pixel is referred to as the source electrode layer, and the other is referred to as the drain electrode layer. However, actually, during AC driving, one electrode alternately functions as the source electrode layer and the drain electrode layer. Also, in order to reduce the leakage current, the width of the gate electrode layer of the thin film transistor disposed in the pixel may be made narrower than the width of the gate electrode layer of the thin film transistor of the driving circuit. Further, in order to reduce the leakage current, the gate electrode layer of the thin film transistor disposed in the pixel may be designed so as not to overlap with the source electrode layer or the drain electrode layer.

Advantages of the Invention

[0055] According to one aspect of the present invention, a thin film transistor having stable electrical characteristics can be manufactured and provided. Therefore, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be provided.

Brief Description of the Drawings

[0056]

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Embodiments for Carrying Out the Invention

[0057] The embodiments will be described in detail with reference to the drawings. However, it is not limited to the following description, and the spirit Those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope. Therefore, it should not be construed as being limited to the description of the embodiments shown below. In the configurations described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof is omitted.

[0058] Note that the contents shown in each embodiment can be appropriately combined with or replaced by each other.

[0059] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 to 3. FIG. 1 shows an example of a cross-sectional structure of two thin-film transistors formed on the same substrate. The thin-film transistor 410 and the thin-film transistor 420 shown in FIG. 1 are transistors having a bottom-gate structure.

[0060] FIG. 1(A1) is a plan view of the thin-film transistor 410 arranged in the driving circuit, FIG. 1(A2) is a plan view of the thin-film transistor 420 arranged in the pixel, FIG. 1(B) is a cross-sectional view showing the cross-sectional structure along line C1-C2 in FIG. 1(A1) and the cross-sectional structure along line D1-D2 in FIG. 1(A2), and FIG. 1(C) is a cross-sectional view showing the cross-sectional structure along line C3-C4 in FIG. 1(A1) and the cross-sectional structure along line D3-D4 in FIG. 1(A2).

[0061] The thin-film transistor 410 arranged in the driving circuit includes a gate electrode layer 411, a gate insulating layer 402, and an oxide semiconductor layer 412 having at least a channel formation region 413, a high-resistance source region 414a, and a high-resistance drain region 414b on a substrate 400 having an insulating surface. and a low-resistance source region 408a, a low-resistance drain region 408b, a source electrode layer 415a, and a drain electrode layer 415b. Further, the thin-film transistor 410 includes a low-resistance source region 408a and the periphery and side surfaces of the low-resistance drain region 408b, and an oxide insulating layer 416 in contact with the oxide semiconductor layer 412.

[0062] Further, the high-resistance source region 414a is formed self-aligned in contact with the lower surface of the low-resistance source region 408a. Further, the high-resistance drain region 414b is formed self-aligned in contact with the lower surface of the low-resistance drain region 408b. Further, the channel formation region 413 is in contact with the oxide insulating layer 416 and is a region (type-I region) having a higher resistance than the high-resistance source region 414a and the high-resistance

[0063] drain region 414b. The source electrode layer 415a is in contact with the low-resistance source region 408a, and the

[0064] drain electrode layer 415b is in contact with the low-resistance drain region 408b. As the source electrode layer 415a and the drain electrode layer 415b, it is preferable to use a

[0065] metal material to reduce the resistance of the wiring. Further, by providing the low-resistance source region 408a and the low-resistance drain region 408b, a thermally stable operation is achieved as compared with a Schottky junction. Thus, an ohmic contact is formed by intentionally providing a low-resistance drain region having a higher

[0066] carrier concentration than the oxide semiconductor layer. It has. By electrically connecting the conductive layer 417 to the gate electrode layer 411 to make them at the same potential, a gate voltage can be applied to the oxide semiconductor layer 412 disposed between the gate electrode layer 411 and the conductive layer 417 from above and below. Also, when the gate electrode layer 411 and the conductive layer 417 are set to different potentials, for example, a fixed potential, GND potential, 0V, the electrical characteristics of the TFT, such as the threshold voltage, can be controlled. That is, by making one of the gate electrode layer 411 and the conductive layer 417 function as a first gate electrode layer and the other of the gate electrode layer 411 and the conductive layer 417 function as a second gate electrode layer, the thin film transistor 410 can be used as a four-terminal thin film transistor. Also, a planarization insulating layer 404 is provided between the conductive layer 417, the source electrode layer 415a and the drain electrode layer 415b, and the oxide insulating layer 416. The thin film transistor 420 disposed in the pixel includes a gate electrode layer 421, a gate insulating layer 402, an oxide semiconductor layer 422 having at least a channel formation region 423, a high-resistance source region 424a, and a high-resistance drain region 424b on a substrate 400 having an insulating surface, a source electrode layer 409a, and a drain electrode layer 409b. Also, the thin film transistor 420 includes an oxide insulating layer 416 in contact with the oxide semiconductor layer 422. Further, the high-resistance source region 424a is self-alignedly formed in contact with the lower surface of the source electrode layer 409a. Also, the high-resistance drain region 424b is self-alignedly formed in contact with the lower surface of the drain electrode layer 409b. Also, the channel formation region 423 is an oxide insulating layer Moreover, by electrically connecting the conductive layer 417 to the gate electrode layer 411 to make them at the same potential, a gate voltage can be applied to the oxide semiconductor layer 412 disposed between the gate electrode layer 411 and the conductive layer 417 from above and below. Also, when the gate electrode layer 411 and the conductive layer 417 are set to different potentials, for example, a fixed potential, GND potential, 0V, the electrical characteristics of the TFT, such as the threshold voltage, can be controlled. That is, by making one of the gate electrode layer 411 and the conductive layer 417 function as a first gate electrode layer and the other of the gate electrode layer 411 and the conductive layer 417 function as a second gate electrode layer, the thin film transistor 410 can be used as a four-terminal thin film transistor. One of the gate electrode layer 411 and the conductive layer 417 functions as a first gate electrode layer, and the other of the gate electrode layer 411 and the conductive layer 417 functions as a second gate electrode layer, so that the thin film transistor 410 can be used as a four-terminal thin film transistor. By making one of the gate electrode layer 411 and the conductive layer 417 function as a first gate electrode layer and the other of the gate electrode layer 411 and the conductive layer 417 function as a second gate electrode layer, the thin film transistor 410 can be used as a four-terminal thin film transistor. That is, by making one of the gate electrode layer 411 and the conductive layer 417 function as a first gate electrode layer and the other of the gate electrode layer 411 and the conductive layer 417 function as a second gate electrode layer, the thin film transistor 410 can be used as a four-terminal thin film transistor.

[0067] Also, a planarization insulating layer 404 is provided between the conductive layer 417, the source electrode layer 415a and the drain electrode layer 415b, and the oxide insulating layer 416. The thin film transistor 420 disposed in the pixel includes a gate electrode layer 421, a gate insulating layer 402, an oxide semiconductor layer 422 having at least a channel formation region 423, a high-resistance source region 424a, and a high-resistance drain region 424b on a substrate 400 having an insulating surface, a source electrode layer 409a, and a drain electrode layer 409b. Also, the thin film transistor 420 includes an oxide insulating layer 416 in contact with the oxide semiconductor layer 422.

[0068] The thin film transistor 420 disposed in the pixel includes a gate electrode layer 421, a gate insulating layer 402, an oxide semiconductor layer 422 having at least a channel formation region 423, a high-resistance source region 424a, and a high-resistance drain region 424b on a substrate 400 having an insulating surface, a source electrode layer 409a, and a drain electrode layer 409b. Also, the thin film transistor 420 includes an oxide insulating layer 416 in contact with the oxide semiconductor layer 422. The thin film transistor 420 disposed in the pixel includes a gate electrode layer 421, a gate insulating layer 402, an oxide semiconductor layer 422 having at least a channel formation region 423, a high-resistance source region 424a, and a high-resistance drain region 424b on a substrate 400 having an insulating surface, a source electrode layer 409a, and a drain electrode layer 409b. Also, the thin film transistor 420 includes an oxide insulating layer 416 in contact with the oxide semiconductor layer 422. The thin film transistor 420 disposed in the pixel includes a gate electrode layer 421, a gate insulating layer 402, an oxide semiconductor layer 422 having at least a channel formation region 423, a high-resistance source region 424a, and a high-resistance drain region 424b on a substrate 400 having an insulating surface, a source electrode layer 409a, and a drain electrode layer 409b. Also, the thin film transistor 420 includes an oxide insulating layer 416 in contact with the oxide semiconductor layer 422. The thin film transistor 420 disposed in the pixel includes a gate electrode layer 421, a gate insulating layer 402, an oxide semiconductor layer 422 having at least a channel formation region 423, a high-resistance source region 424a, and a high-resistance drain region 424b on a substrate 400 having an insulating surface, a source electrode layer 409a, and a drain electrode layer 409b. Also, the thin film transistor 420 includes an oxide insulating layer 416 in contact with the oxide semiconductor layer 422. The thin film transistor 420 disposed in the pixel includes a gate electrode layer 421, a gate insulating layer 402, an oxide semiconductor layer 422 having at least a channel formation region 423, a high-resistance source region 424a, and a high-resistance drain region 424b on a substrate 400 having an insulating surface, a source electrode layer 409a, and a drain electrode layer 409b. Also, the thin film transistor 420 includes an oxide insulating layer 416 in contact with the oxide semiconductor layer 422.

[0069] The high-resistance source region 424a is self-alignedly formed in contact with the lower surface of the source electrode layer 409a. Also, the high-resistance drain region 424b is self-alignedly formed in contact with the lower surface of the drain electrode layer 409b. Also, the channel formation region 423 is an oxide insulating layer The high-resistance source region 424a is self-alignedly formed in contact with the lower surface of the source electrode layer 409a. Also, the high-resistance drain region 424b is self-alignedly formed in contact with the lower surface of the drain electrode layer 409b. Also, the channel formation region 423 is an oxide insulating layer The high-resistance source region 424a is self-alignedly formed in contact with the lower surface of the source electrode layer 409a. Also, the high-resistance drain region 424b is self-alignedly formed in contact with the lower surface of the drain electrode layer 409b. Also, the channel formation region 423 is an oxide insulating layer Contact with 416, and form a region (type I region) that has a higher resistance than the high-resistance source region 424a and the high-resistance drain region 424b.

[0070] Note that the oxide semiconductor layer 412 partially overlaps with the source electrode layer 415a and the drain electrode layer 415b. Also, the oxide semiconductor layer 412 overlaps with the gate electrode layer 411 via the gate insulating layer 402. That is, the gate electrode layer 411 is provided under the oxide semiconductor layer 412 with the gate insulating layer 402 interposed therebetween. Further, the oxide semiconductor layer 422 partially overlaps with the source electrode layer 409a and the drain electrode layer 409b. Also, the oxide semiconductor layer 422 overlaps with the gate electrode layer 421 via the gate insulating layer 402. That is, the gate electrode layer 421 is provided under the oxide semiconductor layer 422 with the gate insulating layer 402 interposed therebetween.

[0071] Also, as the source electrode layer 409a and the drain electrode layer 409b, a material having translucency is used to realize a display device having a high aperture ratio as a thin film transistor. Note that, as the source electrode layer 415a and the drain electrode layer 415b, it is preferable to use a material having a lower resistance value than that of the source electrode layer 409a and the drain electrode layer 409b.

[0072] Also, a material having translucency is used for the gate electrode layer 421.

[0073] Also, in the pixel in which the thin film transistor 420 is disposed, as the pixel electrode layer 427, other electrode layers (such as a capacitive electrode layer) and wiring layers (such as a capacitive wiring layer), a conductive layer having translucency with respect to visible light is used to realize a display device having a high aperture ratio. Of course, the gate insulating layer 40 ​​​​​​​​​​​​​2. The oxide insulating layer 416 and the planarization insulating layer 404 are also preferably formed using a film having translucency to visible light. It is preferably formed using.

[0074] Also, a planarization insulating layer 404 is provided between the pixel electrode layer 427, the source electrode layer 409a and the drain electrode layer 409b, and the oxide insulating layer 416.

[0075] The pixel electrode layer 427 is in contact with the drain electrode layer 409b through an opening (also referred to as a contact hole) provided in the oxide insulating layer 416 and an opening provided in the planarization insulating layer 404. It touches. It is.

[0076] Note that after the formation of the oxide semiconductor layer 412 and the oxide semiconductor layer 422, a heat treatment (heat treatment for dehydration or dehydrogenation) is performed to reduce impurities such as moisture. After performing the heat treatment for dehydration or dehydrogenation and slow cooling, forming a heat treatment (heat treatment for dehydration or dehydrogenation) to reduce impurities such as moisture after the film formation of the oxide semiconductor film used for the formation of the oxide semiconductor layer 412 and the oxide semiconductor layer 422. After performing the heat treatment for dehydration or dehydrogenation and slow cooling, forming the oxide insulating layer in contact with the formed oxide semiconductor layer 412 and oxide semiconductor layer 422, etc. is performed to reduce the carrier concentration of the oxide semiconductor layer, which leads to an improvement in the electrical characteristics and reliability of the thin film transistor 410 and the thin film transistor 420. It leads to an improvement in the electrical characteristics and reliability of the thin film transistor 410 and the thin film transistor 420.

[0077] Also, in this specification, a film having translucency to visible light refers to a film having a film thickness such that the transmittance of visible light is 75 ~100%, and when the film has conductivity, it is also referred to as a transparent conductive film. Also, the gate electrode layer, the source electrode layer, the drain electrode layer, the pixel electrode layer, other electrode layers, and the wiring layer may be formed using a semi-transparent conductive film with respect to visible light. Semi-transparent with respect to visible light means that the transmittance of visible light is 50 to 75%.

[0078] In the semiconductor device shown in FIG. 1, as an example, the channel lengths of the thin film transistor 410 and the thin film transistor 420 are the same, but the present invention is not limited thereto. For example, since the thin film transistor for the drive circuit is required to operate at a higher speed than the thin film transistor for the pixel, the channel length of the thin film transistor 410 may be made narrower than the channel length of the thin film transistor 420. At this time, for example, the channel length of the thin film transistor 410 is preferably about 1 μm to 5 μm, and the channel length of the thin film transistor 420 is preferably 5 μm to 20 μm. As described above, the semiconductor device shown in FIG. 1 has a structure having a drive circuit having a first thin film transistor and a pixel having a second thin film transistor on the same substrate. The second thin film transistor is composed of a light-transmissive material, and the first thin film transistor is composed of a material having a lower resistance value than the light-transmissive material. Thereby, in the pixel, the aperture ratio can be improved, and the operating speed of the drive circuit can be improved. Further, by providing the drive circuit and the pixel on the same substrate, the number of wiring lines for electrically connecting the drive circuit and the pixel can be reduced, and the length of the entire wiring for electrically connecting the drive circuit and the pixel can be shortened. Therefore, miniaturization and cost reduction of the semiconductor device are possible. In the semiconductor device shown in FIG. 1, in the thin film transistor of the drive circuit, between the source electrode layer and the drain electrode layer and the oxide semiconductor layer in which the channel formation region is formed, there is a structure having a low resistance source region and a low resistance drain region. By providing the low resistance source region and the low resistance drain region, the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Moreover, in the semiconductor device shown in FIG. 1, the channel length of the thin film transistor 410 may be made narrower than the channel length of the thin film transistor 420. At this time, for example, the channel length of the thin film transistor 410 is preferably about 1 μm to 5 μm, and the channel length of the thin film transistor 420 is preferably 5 μm to 20 μm. In the semiconductor device shown in FIG. 1, as an example, the channel lengths of the thin film transistor 410 and the thin film transistor 420 are the same, but the present invention is not limited thereto. For example, since the thin film transistor for the drive circuit is required to operate at a higher speed than the thin film transistor for the pixel, the channel length of the thin film transistor 410 may be made narrower than the channel length of the thin film transistor 420. At this time, for example, the channel length of the thin film transistor 410 is preferably about 1 μm to 5 μm, and the channel length of the thin film transistor 420 is preferably 5 μm to 20 μm. As described above, the semiconductor device shown in FIG. 1 has a structure having a drive circuit having a first thin film transistor and a pixel having a second thin film transistor on the same substrate. The second thin film transistor is composed of a light-transmissive material, and the first thin film transistor is composed of a material having a lower resistance value than the light-transmissive material.

[0079] Thereby, in the pixel, the aperture ratio can be improved, and the operating speed of the drive circuit can be improved. Further, by providing the drive circuit and the pixel on the same substrate, the number of wiring lines for electrically connecting the drive circuit and the pixel can be reduced, and the length of the entire wiring for electrically connecting the drive circuit and the pixel can be shortened. Therefore, miniaturization and cost reduction of the semiconductor device are possible. In the semiconductor device shown in FIG. 1, in the thin film transistor of the drive circuit, between the source electrode layer and the drain electrode layer and the oxide semiconductor layer in which the channel formation region is formed, there is a structure having a low resistance source region and a low resistance drain region. By providing the low resistance source region and the low resistance drain region, the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Moreover, in the semiconductor device shown in FIG. 1, the channel length of the thin film transistor 410 may be made narrower than the channel length of the thin film transistor 420. At this time, for example, the channel length of the thin film transistor 410 is preferably about 1 μm to 5 μm, and the channel length of the thin film transistor 420 is preferably 5 μm to 20 μm. In the semiconductor device shown in FIG. 1, as an example, the channel lengths of the thin film transistor 410 and the thin film transistor 420 are the same, but the present invention is not limited thereto. For example, since the thin film transistor for the drive circuit is required to operate at a higher speed than the thin film transistor for the pixel, the channel length of the thin film transistor 410 may be made narrower than the channel length of the thin film transistor 420. At this time, for example, the channel length of the thin film transistor 410 is preferably about 1 μm to 5 μm, and the channel length of the thin film transistor 420 is preferably 5 μm to 20 μm. As described above, the semiconductor device shown in FIG. 1 has a structure having a drive circuit having a first thin film transistor and a pixel having a second thin film transistor on the same substrate. The second thin film transistor is composed of a light-transmissive material, and the first thin film transistor is composed of a material having a lower resistance value than the light-transmissive material.

[0080] Thereby, in the pixel, the aperture ratio can be improved, and the operating speed of the drive circuit can be improved. Further, by providing the drive circuit and the pixel on the same substrate, the number of wiring lines for electrically connecting the drive circuit and the pixel can be reduced, and the length of the entire wiring for electrically connecting the drive circuit and the pixel can be shortened. Therefore, miniaturization and cost reduction of the semiconductor device are possible. In the semiconductor device shown in FIG. 1, in the thin film transistor of the drive circuit, between the source electrode layer and the drain electrode layer and the oxide semiconductor layer in which the channel formation region is formed, there is a structure having a low resistance source region and a low resistance drain region. By providing the low resistance source region and the low resistance drain region, the frequency characteristics of the peripheral circuit (drive circuit) can be improved. This is because, compared with the direct contact between the metal electrode layer and the oxide semiconductor layer, the contact between the metal electrode layer and the low-resistance source region and the low-resistance drain region can reduce the contact resistance. In addition, an electrode layer using molybdenum (for example, a stack of a molybdenum layer, an aluminum layer, a molybdenum layer, etc.) has a high contact resistance with the oxide semiconductor layer. This is because, for example, molybdenum is less likely to be oxidized compared to titanium, so the effect of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between the molybdenum layer and the oxide semiconductor layer does not become n-type. However, by interposing a low-resistance source region and a low-resistance drain region between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (drive circuit) can be improved. In addition, by providing a low-resistance source region and a low-resistance drain region, the channel length of the thin-film transistor can be determined during the etching of the layer that becomes the low-resistance source region and the low-resistance drain region, so that the channel length can be made shorter.

[0081] Further, in the semiconductor device shown in FIG. 1, in the thin-film transistor of the drive circuit, an oxide insulating layer is in contact with a part of the oxide semiconductor layer, and the periphery and side surfaces of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer. By adopting this structure, when there is a portion (also referred to as an intersection portion) where wiring of the same layer as the gate electrode layer and wiring of the same layer as the source electrode layer and the drain electrode layer cross with an insulating layer interposed therebetween at the peripheral portion of the thin-film transistor, the distance between the wiring of the same layer as the gate electrode layer and the wiring of the same layer as the source electrode layer and the drain electrode layer can be increased. Therefore, the parasitic capacitance can be reduced.

[0082] In addition, in the thin-film transistor of the drive circuit in the semiconductor device shown in FIG. 1, a channel formation region overlaps with an oxide insulating layer and a planarization insulating layer therebetween, and it can have a structure including a conductive layer formed of a light-transmissive material, whereby the threshold voltage of the thin-film transistor can be controlled.

[0083] Furthermore, the transistor of the present embodiment can also have the structure shown in FIG. 6. The semiconductor device shown in FIG. 6 is different from the semiconductor device shown in FIG. 1 in that the gate insulating layer is formed by laminating a plurality of insulating layers and it has a protective insulating layer on the oxide insulating layer in contact with the semiconductor layer. That is, the semiconductor device shown in FIG. 6 has a laminate of a gate insulating layer 402a and a gate insulating layer 402b instead of the gate insulating layer 402 shown in FIG. 1, and has a protective insulating layer 403 on the oxide insulating layer 416 shown in FIG. 1. In other configurations of the semiconductor device shown in FIG. 6, parts common to the semiconductor device shown in FIG. 1 are appropriately incorporated by reference to the description of the semiconductor device shown in FIG. 1, and the description here is omitted.

[0084] As the gate insulating layer 402a and the gate insulating layer 402b, for example, materials applicable to the gate insulating layer 402 shown in FIG. 1 can be used. As the gate insulating layer 402a, for example, a nitride insulating layer can be used, and as the gate insulating layer 402b, for example, an oxide insulating layer can be used.

[0085] Hereinafter, with reference to FIGS. 2(A) to (E) and FIGS. 3(A) to (D), an example of the manufacturing process of the thin-film transistor 410 and the thin-film transistor 420 will be described.

[0086] First, after forming a light-transmissive conductive film on a substrate 400 having an insulating surface, a first photo​​​​​​​​​​​​​ A resist mask is formed on a part of the conductive film by a triso-graphy process, and the conductive film is etched using the resist mask to form gate electrode layers 411 and 421. In the pixel portion, a capacitive wiring (also referred to as a capacitive wiring layer) is formed by the same material and the same first photolithography process as the gate electrode layers 411 and 421. Also, when a capacitor is required not only in the pixel but also in the driving circuit, a capacitive wiring is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method since a photomask is not used, the manufacturing cost can be reduced.

[0087] There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance to withstand subsequent heat treatment. As the substrate 400 having an insulating surface for example, a glass substrate or the like can be used.

[0088] Also, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 °C or higher . Also, as the glass substrate, for example, glass materials such as aluminosilicate glass aluminoborosilicate glass, barium borosilicate glass, etc. are used . Note that by including more barium oxide (BaO) than boric acid, a more practical heat-resistant glass can be obtained. For this reason, it is preferable to use a glass substrate containing more BaO than B2O3 .

[0089] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate 400. In addition, as the substrate 400, a crystallized glass For example, etc. can be used.

[0090] Also, an insulating film serving as an underlayer film may be provided between the substrate 400 and the gate electrode layers 411 and 421. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 400, and can be formed by a single film or a stacked film selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed by a stacked film.

[0091] As the material of the gate electrode layers 411 and 421, a conductive material having translucency to visible light, for example, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, A l-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system , Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, Zn-O system of conductive metal oxides can be applied, and the film thickness of the gate electrode layers 411 and 421 is set within the range of 50 nm or more and 3 00 nm or less. As the film formation method of the conductive film used for the gate electrode layers 411 and 421, sputtering method, vacuum evaporation method (such as electron beam evaporation method), arc discharge ion plating method, or spraying method is used. Also, when using the sputtering method, Si O2 is contained in the target in an amount of 2% by weight or more and 10% by weight or less for film formation, and SiO (x > 0) that inhibits crystallization is included in the formed conductive film having translucency. x This can suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in the subsequent process. It can be suppressed.

[0092] Next, the resist mask is removed, and a gate insulating layer 402 is formed on the gate electrode layer 411 and the gate electrode layer 421. It is formed.

[0093] The gate insulating layer 402 can be formed by using the plasma CVD method, the sputtering method, or the like, as a single layer or a laminate of a silicon oxide layer , a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. For example, when forming a silicon oxynitride layer, a silicon oxynitride layer may be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. Further, the film thickness of the gate insulating layer 402 is set to be 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer.

[0094] In this embodiment, the gate insulating layer 402 is a silicon nitride layer with a film thickness of 200 nm or less formed by the plasma CVD method.

[0095] Next, an oxide semiconductor film 430 having a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 402 (see FIG. 2(A)). Even if a heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 430, in order to make the oxide semiconductor layer formed later amorphous, it is preferable to make the film thickness as thin as 50 nm or less. By making the film thickness of the oxide semiconductor film 430 thin, when a heat treatment is performed after the formation of the oxide semiconductor film 430, crystallization of the oxide semiconductor layer formed later can be suppressed.

[0096] Note that before forming the oxide semiconductor film 430 by the sputtering method, reverse sputtering is performed to generate plasma by introducing argon gas, and dust adhering to the surface of the gate insulating layer is preferably removed. Reverse sputtering means applying no voltage to the target side and introducing argon A method of forming plasma near a substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere to modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. As the oxide semiconductor film 430, an In-Ga-Zn-O-based non-single crystal film, an In-Sn-Zn-O-based, an In-Al-Zn-O-based, a Sn-Ga-Zn-O-based, an Al-Ga-Zn-O-based, a Sn-Al-Zn-O-based, an In-Zn-O-based, a Sn-Zn-O-based, an Al-Zn-O-based, an In-Sn-O-based, an In-O-based, a Sn-O-based, or a Zn-O-based oxide semiconductor film is used. In this embodiment,

[0097] a film is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. Also, the oxide semiconductor film 430 can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Further, when using the sputtering method, a target containing 2 wt% or more and 10 wt% or less of SiO2 is used to form the oxide semiconductor film 430, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film 430. This can suppress the crystallization of the subsequently formed oxide semiconductor layer during the heat treatment for dehydration or dehydrogenation performed in a later process. Next, a resist mask is formed on the oxide semiconductor film 430 by a second photolithography process, and selective etching is performed using the resist mask to process the oxide semiconductor film 430 into island-shaped oxide semiconductor layers. Also, the island-shaped oxide semiconductor layers are formed.

[0098] ​​​​​​​​​​​A resist mask may be formed by an inkjet method. Since no photomask is used when forming the resist mask by the inkjet method, the manufacturing cost can be reduced.

[0099] Next, the resist mask is removed, and dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 400°C or higher and lower than the strain point of the substrate, for example, 400°C or higher and 700°C or lower, preferably 425°C or higher and 700°C or lower. Note that if it is 425°C or higher and 700°C or lower, the heat treatment time may be 1 hour or less, but if it is less than 425°C, the heat treatment time shall be longer than 1 hour. Here, a substrate 400 having an oxide semiconductor layer formed on the upper part is introduced into an electric furnace, which is one of the heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere. Then, without being exposed to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented, and low-resistance oxide semiconductor layers 431 and 432 are obtained (see Fig. 2(B)). In this embodiment, from the heating temperature T for performing dehydration or dehydrogenation of the oxide semiconductor layer, the same furnace is used until a sufficient temperature is reached at which water and hydrogen do not enter again. Specifically, it is gradually cooled in a nitrogen atmosphere until the temperature drops by 100°C or more from the heating temperature T. Also, it is not limited to a nitrogen atmosphere, and dehydration or dehydrogenation may be performed in an atmosphere of a noble gas such as helium, neon, or argon.

[0100] Note that in the first heat treatment, it is preferable that nitrogen or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Also, the purity of nitrogen or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher. Preferably, it is 7N (99.99999%) or higher, that is, the impurity concentration of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 1 ppm or less, preferably 0.1 ppm or less.

[0101] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become a microcrystalline layer or a polycrystalline layer.

[0102] Also, the first heat treatment can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus, and a photolithography process is performed to form a resist mask, and the oxide semiconductor film is processed by selectively etching using the resist mask.

[0103] Also, before forming the oxide semiconductor film, heat treatment (400 °C or higher and below the strain point of the substrate) may be performed in an oxygen atmosphere under an inert gas atmosphere (nitrogen or rare gases such as helium, neon, and argon) to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0104] Next, an oxide conductive film is formed on the oxide semiconductor layers 431 and 432 and the gate insulating layer 402, and resist masks 433a and 433b are formed by a third photolithography process, and selective etching is performed to form the oxide conductive layers 406 and 407 (see Fig. 2(C)). As the material of the oxide conductive film, a conductive material having translucency to visible light, for example, In -Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga- Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Z n-O system, In-Sn-O system, Al-Zn-O-N system, In-O system, Sn-O system, Zn- O-based conductive metal oxides can be applied, and the film thickness of the oxide conductive film can be appropriately selected within the range of 50 nm or more and 30 0 nm or less. Also, as a method for forming the oxide conductive film, when using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiO that inhibits crystallization is included in the conductive film having translucency x (x>0) may be included Yes. Thereby, during the heat treatment for dehydration or dehydrogenation performed in a later process, it is possible to suppress the crystallization of the oxide conductive layers 406 and 407 formed later.

[0105] In the method for manufacturing a semiconductor device according to this embodiment, dehydration or dehydrogenation (first heat treatment) of the oxide semiconductor layer shown above can also be performed after forming the oxide conductive film or the oxide conductive layers 406 and 407.

[0106] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO = 1:1:1 [mole ratio], In:Ga:Zn = 1:1:0.5 [atom ratio]) is used, the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, and a direct current ( DC) power supply is 0.5 kW. An oxide semiconductor film 430 is formed in an atmosphere of argon and oxygen (argon:oxygen = 30 sccm:20 scc m oxygen flow ratio 40%). Note that when using a pulsed direct current (DC) power supply, dust can be reduced and the film thickness distribution becomes uniform, which is preferable. I n-Ga-Zn-O-based non-single crystal film has a film thickness of 5 nm to 200 nm. In this embodiment Yes, as the oxide semiconductor film, an In-Ga-Zn-O-based oxide semiconductor target is used for sp uttering A 20 nm thick In-Ga-Zn-O non-single crystal film is formed by sputtering. In addition, the oxide semiconductor target material may be, for example, In:Ga:ZnO=1:1:1, or A target material such as In:Ga:ZnO=1:1:4 can also be used.

[0107] In addition, the sputtering method uses RF sputtering, which uses a high-frequency power source as the sputtering power source. There are two methods: DC sputtering and DC sputtering. There is also a method called pulsed DC There is also the sputtering method. The RF sputtering method is mainly used to deposit insulating films. The DC sputtering method is mainly used for forming metal films.

[0108] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The sputtering equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form films by discharging multiple types of materials simultaneously using the bar.

[0109] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. E using a plasma generating device using microwaves instead of glow discharge. There is a sputtering device that uses the CR sputtering method.

[0110] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering method are used during film formation. Reactive sputtering is a method in which a compound thin film is formed by chemically reacting the components of the sputtering gas with the There are also sputtering methods in which a voltage is applied to the substrate during deposition, and bias sputtering methods in which a voltage is also applied to the substrate during deposition.

[0111] Next, the resist masks 433a and 433b are removed, and a fourth photolithography is performed. Form resist masks 436a and 436b by a lithography process, and selectively etch to form a low-resistance source region 408a and a low -resistance drain region 408b, as well as a source electrode layer 409a and a drain electrode layer 409b, which are composed of an oxide conductive layer (see Fig. 2(D)). Note that a resist mask for forming the low-resistance source region 408a, the low-resistance drain region 408b, the source electrode layer 409a, and the drain electrode layer 409b may be formed by an inkjet method. Since no photomask is used when forming the resist mask by the inkjet method, the manufacturing cost can be reduced. At this time, for the etching process, it is preferable to appropriately set the etching conditions so that the underlying oxide semiconductor layers 431 and 432 are not etched. For example, the etching time may be controlled. It is also preferable to use materials with a high etching selectivity as the materials constituting the oxide semiconductor layers 431 and 432, and the materials constituting the oxide conductive layers 406 and 407, respectively. For example, as the materials constituting the oxide semiconductor layers 431 and 432, a metal oxide material containing Sn (for example, SnZnO (x>0), or SnGaZnO

[0112] (x>0), etc.) can be used, and as the materials constituting the oxide conductive layers 406 and 407, an Al-Zn-O-based material, an Al -Zn-O-N-based material, a Zn-O-based material, etc. can be used. Materials mainly composed of such zinc oxide can be etched, for example, using an alkaline solution. Also, materials containing aluminum, such as an Al-Zn-O-based material and an Al-Zn-O-N-based material, can be used. For example, the etching time may be controlled.

[0113] Moreover, as the materials constituting the oxide semiconductor layers 431 and 432, and the materials constituting the oxide conductive layers 406 and 407, respectively, it is preferable to use materials with a high etching selectivity. For example, as the materials constituting the oxide semiconductor layers 431 and 432, a metal oxide material containing Sn (for example, SnZnO (x>0), or SnGaZnO (x>0), etc.) can be used, and as the materials constituting the oxide conductive layers 406 and 407, an Al-Zn-O-based material, an Al -Zn-O-N-based material, a Zn-O-based material, etc. can be used. Materials mainly composed of such zinc oxide can be etched, for example, using an alkaline solution. Also, materials containing aluminum, such as an Al-Zn-O-based material and an Al-Zn-O-N-based material, can be used. x (x>0), or SnGaZnO x (x>0), etc.) are used, and as the materials constituting the oxide conductive layers 406 and 407, an Al-Zn-O-based material, an Al -Zn-O-N-based material, a Zn-O-based material, etc. are used. Such materials mainly composed of zinc oxide can be etched, for example, using an alkaline solution. Also, materials containing aluminum, such as an Al-Zn-O-based material and an Al-Zn-O-N-based material, are used. -Zn-O-N-based material, a Zn-O-based material, etc. may be used. Such materials mainly composed of zinc oxide can be etched, for example, using an alkaline solution. Also, materials containing aluminum, such as an Al-Zn-O-based material and an Al-Zn-O-N-based material, may be used. For example, it can be etched using an alkaline solution. Also, materials containing aluminum, such as an Al-Zn-O-based material and an Al-Zn-O-N-based material, can be used. l-Zn-O-based material, an Al-Zn-O-N-based material, etc., materials containing aluminum, can be used. When removing the resist mask used for etching, it is preferable to use a method in which the oxide conductive layer is not removed together. For example, by removing the resist mask by dry etching, the resist mask can be removed without removing the oxide conductive layer. Next, an oxide insulating layer 416 in contact with the exposed surfaces of the oxide semiconductor layer 431 and the oxide semiconductor layer 432 is formed. The oxide insulating layer 416 should have a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer 416. In this embodiment, the oxide insulating layer 416 is formed by forming a silicon oxide film with a film thickness of 300 nm using the sputtering method. The substrate temperature during film formation should be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by the sputtering method in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 is formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film can be removed without removing the oxide conductive layer.

[0114] Next, an oxide insulating layer 416 in contact with the exposed surfaces of the oxide semiconductor layer 431 and the oxide semiconductor layer 432 is formed. is formed.

[0115] The oxide insulating layer 416 should have a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer 416. In this embodiment, the oxide insulating layer 416 is formed by forming a silicon oxide film with a film thickness of 300 nm using the sputtering method. The substrate temperature during film formation should be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by the sputtering method in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 is formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film such as a silicon oxynitride film can be used. In this embodiment, the oxide insulating layer 416 is formed by forming a silicon oxide film with a film thickness of 300 nm using the sputtering method. The substrate temperature during film formation should be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by the sputtering method in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 is formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film The oxide insulating layer 416 should have a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer 416. In this embodiment, the oxide insulating layer 416 is formed by forming a silicon oxide film with a film thickness of 300 nm using the sputtering method. The substrate temperature during film formation should be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by the sputtering method in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 is formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film The oxide insulating layer 416 should have a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer 416. In this embodiment, the oxide insulating layer 416 is formed by forming a silicon oxide film with a film thickness of 300 nm using the sputtering method. The substrate temperature during film formation should be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by the sputtering method in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 is formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film The oxide insulating layer 416 should have a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer 416. In this embodiment, the oxide insulating layer 416 is formed by forming a silicon oxide film with a film thickness of 300 nm using the sputtering method. The substrate temperature during film formation should be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by the sputtering method in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 is formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film such as a silicon oxynitride film can be used. The oxide insulating layer 416 should have a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer 416. In this embodiment, the oxide insulating layer 416 is formed by forming a silicon oxide film with a film thickness of 300 nm using the sputtering method. The substrate temperature during film formation should be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by the sputtering method in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 is formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film For example, a silicon oxide film can be formed by the sputtering method in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 is formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film such as a silicon oxynitride film can be used. For the oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432, an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside is used for formation. Typically, a silicon oxide film, a silicon oxynitride film - such as a silicon oxynitride film can be used. such as a silicon oxynitride film can be used. It is formed using a film, an aluminum oxide film, an aluminum oxynitride film, or the like. Also, an acid As the oxide insulating layer 416, a silicon oxide film formed using a boron-doped silicon target material is used to suppress the intrusion of impurities (such as moisture, hydrogen ions, OH - , etc.). Invasion can be suppressed.

[0116] Next, a second heat treatment (preferably 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere . When the second heat treatment is performed, a part of the oxide semiconductor layer 431 and the oxide semiconductor layer 432 is heated in contact with the oxide insulating layer 416 .

[0117] By going through the above steps, the oxide semiconductor layers 431 and 432 are made to have a lower resistance, and a part of the oxide semiconductor layers 431 and 432 is selectively made to be in an oxygen-excess state. As a result, the channel formation region 413 overlapping the gate electrode layer 411 becomes of type I, the channel formation region 423 overlapping the gate electrode layer 421 becomes of type I, a high-resistance source region 414a is self-alignedly formed in the part of the oxide semiconductor layer 431 overlapping the source electrode layer 415a, a high-resistance drain region 414b is self-alignedly formed in the part of the oxide semiconductor layer 431 overlapping the drain electrode layer 4 15b, a high-resistance source region 424a is self-alignedly formed in the part of the oxide semiconductor layer 432 overlapping the source electrode layer 409a, and a high-resistance drain region 424b is self-alignedly formed in the part of the oxide semiconductor layer 432 overlapping the drain electrode layer 4 09b (see Fig. 2(E) ).

[0118] ​​​Note that by forming an oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed, which can improve the reliability of the driving circuit. Specifically, by forming the high-resistance drain region 414b, the transistor can be structured such that the conductivity changes stepwise from the drain electrode layer 415b through the high-resistance drain region 414b to the channel formation region 413. Therefore, when the transistor is operated by electrically connecting the drain electrode layer to a wiring that supplies a high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 411 and the drain electrode layer 415b, the high-resistance drain region 414b (or the high-resistance source region 414a) serves as a buffer, preventing local electric field concentration and improving the breakdown voltage of the transistor. In the oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed to improve the reliability of the driving circuit. Specifically, by forming the high-resistance drain region 414b, the transistor can be structured such that the conductivity changes stepwise from the drain electrode layer 415b through the high-resistance drain region 414b to the channel formation region 413. Therefore, when the transistor is operated by electrically connecting the drain electrode layer to a wiring that supplies a high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 411 and the drain electrode layer 415b, the high-resistance drain region 414b (or the high-resistance source region 414a) serves as a buffer, preventing local electric field concentration and improving the breakdown voltage of the transistor. In the oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed to reduce the leakage current of the transistor in the driving circuit. Note that by forming an oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed, which can improve the reliability of the driving circuit. Specifically, by forming the high-resistance drain region 414b, the transistor can be structured such that the conductivity changes stepwise from the drain electrode layer 415b through the high-resistance drain region 414b to the channel formation region 413. Therefore, when the transistor is operated by electrically connecting the drain electrode layer to a wiring that supplies a high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 411 and the drain electrode layer 415b, the high-resistance drain region 414b (or the high-resistance source region 414a) serves as a buffer, preventing local electric field concentration and improving the breakdown voltage of the transistor. In the oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed to reduce the leakage current of the transistor in the driving circuit. In the oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed to reduce the leakage current of the transistor in the driving circuit.

[0119] Note that by forming an oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed, which can improve the reliability of the driving circuit. Specifically, by forming the high-resistance drain region 414b, the transistor can be structured such that the conductivity changes stepwise from the drain electrode layer 415b through the high-resistance drain region 414b to the channel formation region 413. Therefore, when the transistor is operated by electrically connecting the drain electrode layer to a wiring that supplies a high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 411 and the drain electrode layer 415b, the high-resistance drain region 414b (or the high-resistance source region 414a) serves as a buffer, preventing local electric field concentration and improving the breakdown voltage of the transistor. In the oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed to reduce the leakage current of the transistor in the driving circuit. Note that by forming an oxide semiconductor layer 431 that overlaps with the low-resistance drain region 408b (and the low-resistance source region 408a), a high-resistance drain region 414b (or a high-resistance source region 414a) can be formed, which can improve the reliability of the driving circuit. Specifically, by forming the high-resistance drain region 414b, the transistor can be structured such that the conductivity changes stepwise from the drain electrode layer 415b through the high-resistance drain region 414b to the channel formation region 413. Therefore, when the transistor is operated by electrically connecting the drain electrode layer to a wiring that supplies a high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 411 and the drain electrode layer 415b, the high-resistance drain region 414b (or the high-resistance source region 414a) serves as a buffer, preventing local electric field concentration and improving the breakdown voltage of the transistor.

[0120] Note that by forming a high-resistance drain region 424b (or a high-resistance source region 424a) in the oxide semiconductor layer 432 that overlaps with the drain electrode layer 409b (and the source electrode layer 409a), the reliability of the pixel can be improved. Specifically, by forming the high-resistance drain region 424b, the transistor can be structured such that the conductivity changes stepwise from the drain electrode layer 409b through the high-resistance drain region 424b to the channel formation region 423. In the oxide semiconductor layer 432 that overlaps with the drain electrode layer 409b (and the source electrode layer 409a), a high-resistance drain region 424b (or a high-resistance source region 424a) can be formed to improve the reliability of the pixel. Specifically, by forming the high-resistance drain region 424b, the transistor can be structured such that the conductivity changes stepwise from the drain electrode layer 409b through the high-resistance drain region 424b to the channel formation region 423. In the oxide semiconductor layer 432 that overlaps with the drain electrode layer 409b (and the source electrode layer 409a), a high-resistance drain region 424b (or a high-resistance source region 424a) can be formed to improve the reliability of the pixel. Specifically, by forming the high-resistance drain region 424b, the transistor can be structured such that the conductivity changes stepwise from the drain electrode layer 409b through the high-resistance drain region 424b to the channel formation region 423. It can be in a U shape. Therefore, when operating the transistor by electrically connecting the drain electrode layer 409b to the wiring that supplies the high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 421 and the drain electrode layer 409b, the high-resistance drain region 424b serves as a buffer and local electric field concentration does not occur, and the breakdown voltage of the transistor can be improved. Moreover, by forming the high-resistance drain region 424b (or the high-resistance source region 424a) in the oxide semiconductor layer 432 that overlaps with the drain electrode layer 409b (and the source electrode layer 409a), the leakage current of the transistor in the pixel can be reduced. In the semiconductor device of this embodiment, a protective insulating layer can also be provided on the oxide insulating layer 416. When providing the protective insulating layer, in this embodiment, it is preferable to form the protective insulating layer by forming a silicon nitride film using the RF sputtering method. The RF sputtering method is preferable as a film formation method for the protective insulating layer because of its good mass productivity. The protective insulating layer uses an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. For example, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. are used. Of course, the protective insulating layer is a transparent insulating film. Next, a fifth photolithography process is performed to form a resist mask, and by etching the oxide insulating layer 416, a region 418 where a part of the low-resistance source region 408a is exposed is formed.

[0121] Furthermore, in the oxide semiconductor layer 432 that overlaps with the drain electrode layer 409b (and the source electrode layer 409a), by forming the high-resistance drain region 424b (or the high-resistance source region 424a), the leakage current of the transistor in the pixel can be reduced. In addition, in the semiconductor device of this embodiment, a protective insulating layer can also be provided on the oxide insulating layer 416. When providing the protective insulating layer, in this embodiment, it is preferable to form the protective insulating layer by forming a silicon nitride film using the RF sputtering method. The RF sputtering method is preferable as a film formation method for the protective insulating layer because of its good mass productivity. The protective insulating layer uses an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. For example, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. are used. Of course, the protective insulating layer is a transparent insulating film. Next, a fifth photolithography process is performed to form a resist mask, and by etching the oxide insulating layer 416, a region 418 where a part of the low-resistance source region 408a is exposed

[0122] Moreover, when operating the transistor by electrically connecting the drain electrode layer 409b to the wiring that supplies the high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 421 and the drain electrode layer 409b, the high-resistance drain region 424b serves as a buffer and local electric field concentration does not occur, and the breakdown voltage of the transistor can be improved. It can be in a U shape. Therefore, Furthermore, in the oxide semiconductor layer 432 that overlaps with the drain electrode layer 409b (and the source electrode layer 409a), by forming the high-resistance drain region 424b (or the high-resistance source region 424a), the leakage current of the transistor in the pixel can be reduced. In addition, in the semiconductor device of this embodiment, a protective insulating layer can also be provided on the oxide insulating layer 416. When providing the protective insulating layer, in this embodiment, it is preferable to form the protective insulating layer by forming a silicon nitride film using the RF sputtering method. The RF sputtering method is preferable as a film formation method for the protective insulating layer because of its good mass productivity. The protective insulating layer uses an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. For example, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. are used. Of course, the protective insulating layer is a transparent insulating film. Next, a fifth photolithography process is performed to form a resist mask, and by etching the oxide insulating layer 416, a region 418 where a part of the low-resistance source region 408a is exposed - is formed. Moreover, when operating the transistor by electrically connecting the drain electrode layer 409b to the wiring that supplies the high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 421 and the drain electrode layer 409b, the high-resistance drain region 424b serves as a buffer and local electric field concentration does not occur, and the breakdown voltage of the transistor can be improved. It can be in a U shape. Therefore, Furthermore, in the oxide semiconductor layer 432 that overlaps with the drain electrode layer 409b (and the source electrode layer 409a), by forming the high-resistance drain region 424b (or the high-resistance source region 424a), the leakage current of the transistor in the pixel can be reduced.

[0123] Next, a fifth photolithography process is performed to form a resist mask, and by etching the oxide insulating layer 416, a region 418 where a part of the low-resistance source region 408a is exposed is formed. , a region 419 where a part of the low-resistance drain region 408b is exposed, and a drain electrode layer 409 Form a contact hole 426 reaching b, and the oxide insulating layer 416 is formed on the upper surface of the oxide semiconductor layer 43 1, as well as the peripheries and sides of the low-resistance source region 408a and the low-resistance drain region 408b (see Fig. 3(A)). Here, the resist mask may be formed by the inkjet method. When the resist mask is formed by the inkjet method, since no photomask is used, the manufacturing cost can be reduced. When the resist mask is formed by the inkjet method, since no photomask is used, the manufacturing cost can be reduced. When the resist mask is formed by the inkjet method, since no photomask is used, the manufacturing cost can be reduced.

[0124] Next, after removing the resist mask, a conductive film is formed on at least the exposed low-resistance source region 408a and the low-resistance drain region 408b and on the oxide insulating layer 416, and resist masks 438a and 438b are formed on the conductive film by a sixth photolithography process and the conductive film is selectively etched to form a source electrode layer 415a and a drain electrode layer 415b. (See Fig. 3(B)). and the conductive film is selectively etched to form a source electrode layer 415a and a drain electrode layer 415b. (See Fig. 3(B)). and the conductive film is selectively etched to form a source electrode layer 415a and a drain electrode layer 415b. (See Fig. 3(B)).

[0125] Examples of the material of the conductive film for forming the source electrode layer 415a and the drain electrode layer 415b include an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or an alloy containing the above-described elements as components, or an alloy combining the above-described elements. an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or an alloy containing the above-described elements as components, or an alloy combining the above-described elements.

[0126] As the conductive film, a three-layer laminated film of a titanium film, an aluminum film provided on the titanium film, and a titanium film provided on the aluminum film, or a molybdenum film, an aluminum film provided on the molybdenum film, and a molybdenum film provided on the aluminum film is preferably used. Of course, as the metal conductive film, a single-layer film, a two-layer laminated film, or a four-layer is preferably used. Of course, as the metal conductive film, a single-layer film, a two-layer laminated film, or a four-layer is preferably used. Of course, as the metal conductive film, a single-layer film, a two-layer laminated film, or a four-layer A laminated film of two or more layers may be used. Further, as the conductive film, when a laminated conductive film of a titanium film, an aluminum film, and a tantalum film is used, etching can be performed by a dry etching method using chlorine gas. Further, a resist mask for forming the conductive layer may be formed by an inkjet method. Since no photomask is used when the resist mask is formed by the inkjet method, the manufacturing cost can be reduced.

[0127] Next, a planarization insulating layer 404 is formed on the oxide insulating layer 416. As the planarization insulating layer 404, an organic material having heat resistance such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used as the planarization insulating layer 404. Note that the planarization insulating layer 404 may be formed by laminating a plurality of insulating films formed of these materials. The siloxane-based resin corresponds to a resin containing a Si—O—Si bond formed using a siloxane-based material as a starting material. Further, as the substituent of the siloxane-based resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used. Further, the organic group may have a fluoro group. The method for forming the planarization insulating layer 404 is not particularly limited, and depending on the material, sputtering, SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet)

[0128]

[0129]

[0130] ting, etc. can be used. ​​​​​​​​​​​​(spin coating method, screen printing, offset printing, etc.) and instruments such as doctor knives, roll coaters, curtain coaters, knife coaters, etc. can be used. Next, a seventh photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 409b is formed by etching the planarized insulating layer 404 (see Fig. 3(C)). Note that contact holes reaching the gate electrode layers 411 and 421 are also formed by the etching here. Also, a resist mask for forming the contact hole 441 reaching the drain electrode layer 409b may be formed by an inkjet method.

[0131] Next, a seventh photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 409b is formed by etching the planarized insulating layer 404 (see Fig. 3(C)). Note that contact holes reaching the gate electrode layers 411 and 421 are also formed by the etching here. Also, a resist mask for forming the contact hole 441 reaching the drain electrode layer 409b may be formed by an inkjet method. Next, a seventh photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 409b is formed by etching the planarized insulating layer 404 (see Fig. 3(C)). Note that contact holes reaching the gate electrode layers 411 and 421 are also formed by the etching here. Also, a resist mask for forming the contact hole 441 reaching the drain electrode layer 409b may be formed by an inkjet method. Next, a seventh photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 409b is formed by etching the planarized insulating layer 404 (see Fig. 3(C)). Note that contact holes reaching the gate electrode layers 411 and 421 are also formed by the etching here. Also, a resist mask for forming the contact hole 441 reaching the drain electrode layer 409b may be formed by an inkjet method. Next, a seventh photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 409b is formed by etching the planarized insulating layer 404 (see Fig. 3(C)). Note that contact holes reaching the gate electrode layers 411 and 421 are also formed by the etching here. Also, a resist mask for forming the contact hole 441 reaching the drain electrode layer 409b may be formed by an inkjet method. Next, a seventh photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 409b is formed by etching the planarized insulating layer 404 (see Fig. 3(C)). Note that contact holes reaching the gate electrode layers 411 and 421 are also formed by the etching here. Also, a resist mask for forming the contact hole 441 reaching the drain electrode layer 409b may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0132] Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. Next, after removing the resist mask, a conductive film having translucency is formed. For example, an indium oxide (In2O3) film, an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO) film, etc. are formed by a sputtering method, a vacuum evaporation method, etc. to form a conductive film having translucency. As the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-N-based non-single crystal film may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the Al-Zn-O-N-based non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al-Zn-O-N-based non-single crystal film. is large. The etching treatment of the film of such a material is performed using a hydrochloric acid-based solution. However, especially in the case of etching an ITO film, since residues are likely to occur, in order to improve the etching processability indium zinc oxide alloy (In2O3-ZnO) may be used.

[0133] Note that the unit of the composition ratio of the conductive film having translucency is atomic %, and the composition ratio of the conductive film having translucency is evaluated by analysis using an electron probe X-ray microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer ).

[0134] Next, an eighth photolithography process is performed to form a resist mask, and unnecessary portions of the conductive film having translucency are removed by etching to form the pixel electrode layer 427 and the conductive layer 417, and the resist mask is removed (see Fig. 3(D)).

[0135] By the above process, using eight masks, the thin film transistor 410 and the thin film transistor 420 can be separately fabricated in the driving circuit or the pixel portion on the same substrate, so that the manufacturing cost can be reduced as compared with the case where the pixel portion and the driving circuit are fabricated in separate processes. The thin film transistor 410, which is a transistor for the driving circuit, is a thin film transistor including an oxide semiconductor layer 412 having a high resistance source region 414a, a high resistance drain region 414b, and a channel formation region 413, and the thin film transistor 420, which is a transistor for the pixel, is a thin film transistor including an oxide semiconductor layer 422 having a high resistance source region 424a, a high resistance drain region 424b, and a channel formation region 423. The thin film transistor 410 and the thin film transistor 420 have high resistance sources even when a high electric field is applied. formation region 423. The thin film transistor 410 and the thin film transistor 420 are thin film transistors including an oxide semiconductor layer 422 having a high resistance source region 424a, a high resistance drain region 424b, and a channel formation region 423. The thin film transistor 410 and the thin film transistor 420 are such that even when a high electric field is applied, the high resistance source The regions 414a, high-resistance drain regions 414b, high-resistance source regions 424a, and high-resistance drain regions 424b serve as buffers, preventing local electric field concentration and improving the breakdown voltage of the transistor.

[0136] Also, in the method of manufacturing the semiconductor device shown in FIGS. 2 and 3, the gate insulating layer 402 is used as a dielectric, and the holding capacitor formed by the capacitance wiring and the capacitance electrode (also referred to as the capacitance electrode layer) can be formed on the same substrate as the thin film transistors 410 and 420. The thin film transistors 420 and the holding capacitors are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having the thin film transistors 410 is arranged around the pixel portion, thereby forming one substrate for manufacturing an active matrix type display device. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

[0137] Note that the pixel electrode layer 427 is electrically connected to the capacitance electrode layer through the contact hole 441 formed in the planarization insulating layer 404 and the contact hole 426 formed in the oxide insulating layer 416. By forming a plurality of contact holes to electrically connect the lower electrode layer and the upper electrode layer, contact holes can be easily formed even when the thickness of the insulating layer is increased, so contact failure can be suppressed. Note that the capacitance electrode layer can be formed from the same material and in the same process as the source electrode layer 409a and the drain electrode layer 409b.

[0138] Also, by providing the conductive layer 417 at a position overlapping the channel formation region 413 of the oxide semiconductor layer, a bias-thermal stress test (hereinafter In the BT test (or the like), the change amount of the threshold voltage of the thin film transistor 410 before and after the BT test can be reduced. Also, the conductive layer 417 may have the same potential as the gate electrode layer 41 1 or may be different, and can also function as a gate electrode layer. Also, the conductive layer 417 may be in a GND state, a state where a potential of 0 V is applied, or a floating state.

[0139] Also, a resist mask for forming the conductive layer 417 and the pixel electrode layer 427 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0140] (Embodiment 2) In this embodiment, an example in which the first heat treatment is different from that in Embodiment 1 is shown in FIG. 4. Since the steps are the same except that they are partially different from those in FIGS. 2 and 3, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted.

[0141] Cross-sectional views of the manufacturing process of two thin film transistors are shown in FIGS. 4(A) to (C).

[0142] First, according to the manufacturing process shown in Embodiment 1, gate electrodes layers 411 and 421 are formed on a substrate 400 having an insulating surface.

[0143] Next, a gate insulating layer 402 is formed on the gate electrode layers 411 and 421.

[0144] Next, an oxide semiconductor film 430 having a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 402 (see FIG. 4(A)). Note that the steps up to this point are the same as those in Embodiment 1 , and FIG. 4(A) corresponds to FIG. 2(A).

[0145] Next, in an inert gas atmosphere or under reduced pressure, dehydration or dehydrogenation of the oxide semiconductor film 480 is carried out. The temperature of the first heat treatment for dehydration or dehydrogenation is set to 350°C or higher and lower than the strain point of the substrate, preferably 400°C or higher. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor film in a nitrogen atmosphere. After that, without exposing to the atmosphere, re - mixing of water and hydrogen into the oxide semiconductor film is prevented, and the oxide semiconductor film is made oxygen - deficient to reduce the resistance, that is, to make it N - type (N - doping, etc.). Then, high - purity oxygen gas or high - purity N2O gas, or ultra - dry air (dew point is - 40°C or lower, preferably - 60°C or lower) is introduced for cooling. It is preferable that the oxygen gas or N2O gas does not contain water, - hydrogen, etc. Or, the purity of the oxygen gas or N2O gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.9999 9%) or higher (that is, the impurity concentration in the oxygen gas or N2O gas is 1 ppm or lower, preferably 0.1 ppm or lower). Alternatively, heat treatment may be performed in an oxygen gas atmosphere, or an N2O gas atmosphere, or an ultra - dry air (dew point is - 40°C or lower, preferably - 60°C or lower) atmosphere at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower, after the first heat treatment for dehydration or dehydrogenation. By going through the above steps, the entire oxide semiconductor film 430 is made in an oxygen - excessive state, resulting in an increase in resistance, that is, making it I - type, and forming the oxide semiconductor film 434 (see Fig. 4(B)).

[0146] After the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed in an oxygen gas atmosphere, or an N2O gas atmosphere, or an ultra - dry air (dew point is - 40°C or lower, preferably - 60°C or lower) atmosphere at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower. By going through the above steps, the entire oxide semiconductor film 430 is made in an oxygen - excessive state, resulting in an increase in resistance, that is, making it I - type, and forming the oxide semiconductor film 434 (see Fig. 4(B)).

[0147] By going through the above steps, the entire oxide semiconductor film 430 is made in an oxygen - excessive state, resulting in an increase in resistance, that is, making it I - type, and forming the oxide semiconductor film 434 (see Fig. 4(B)). As a result, the reliability of the thin film transistor formed later can be improved.

[0148] In this embodiment, an example of performing dehydration or dehydrogenation after forming the oxide semiconductor film is shown. However, it is not particularly limited, and the first heat treatment can also be performed after processing the island-shaped oxide semiconductor layer in the same manner as in Embodiment 1.

[0149] Also, in an inert gas atmosphere, dehydration or dehydrogenation of the oxide semiconductor film is performed, and after cooling in an inert gas atmosphere, a resist mask is formed by a photolithography process, and the oxide semiconductor film 434 is selectively etched using the resist mask, to form an oxide semiconductor layer that is an island-shaped oxide semiconductor layer, and then at 200°C or higher and 400°C or lower , preferably at a temperature of 200°C or higher and 300°C or lower, in an oxygen gas atmosphere, an N2O gas atmosphere , or an ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) atmosphere, heat treatment may be performed.

[0150] Also, before forming the oxide semiconductor film 434, a heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), an oxygen atmosphere, or an ultra-dry air (dew point of -40°C or lower, preferably - 60°C or lower) atmosphere to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0151] Next, a resist mask is formed on the oxide semiconductor film 434 by a second photolithography process, and the oxide semiconductor film 434 is selectively etched using the resist mask, to form an oxide semiconductor layer 443 that is an island-shaped oxide semiconductor layer, ​Form 445.

[0152] Subsequently, the resist mask is removed, and in the same manner as FIGS. 2(C), 2(D), and 2(E) of Embodiment 1, FIGS. 3(A), 3(B), and 3(C), a low-resistance source region 408a and a low-resistance drain region 408b in contact with the oxide semiconductor layer 443 are formed, and on the upper surface of the oxide semiconductor layer 443, and an oxide insulating layer 416 in contact with the peripheries and side surfaces of the low-resistance source region 408a and the low-resistance drain region 408b is formed. On the other hand, in the pixel portion, a source electrode layer 409a and a drain electrode layer 409 b, which are conductive layers having translucency and are in contact with the oxide semiconductor layer 445, are formed, and an oxide insulating layer 416 in contact with the oxide semiconductor layer 445 is formed. Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere. As the conditions for the second heat treatment, the same conditions as those in the method for manufacturing a semiconductor device shown in Embodiment 1 can be used. For example, a second heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. Next, a part of the low-resistance source region 408a and the low-resistance drain region 408b is exposed, and a contact hole reaching the drain electrode layer 409b is formed in the oxide insulating layer 416. Further,

[0153] a conductive film is formed on the oxide insulating layer 416, and the conductive film is selectively etched to form a source electrode layer 415a in contact with the low-resistance source region 408a and a drain electrode layer 415b in contact with the low-resistance drain region 408b. Next, a planarization insulating layer 4 04 is formed in contact with the oxide insulating layer 416, a contact hole reaching the drain electrode layer 409b is formed in the planarization insulating layer 404, and a conductive film having translucency is formed on the contact hole and the planarization insulating layer 404.

[0154] ​​​​​​​​The light-transmitting conductive film is selectively etched to electrically connect the drain electrode layer 409b to the drain electrode layer 409b. A pixel electrode layer 427 and a conductive layer 417 to be connected are formed (see FIG. 4C).

[0155] Through the above steps, the entire oxide semiconductor layer was formed on the same substrate using eight masks. A thin film transistor 449 and a thin film transistor 451 are connected to a driver circuit or a pixel circuit. The thin film transistor 449 for the driver circuit is an I-type transistor. The thin film transistor is a thin film transistor for a pixel including an oxide semiconductor layer 443. The thin film transistor 451 also includes an oxide semiconductor layer 445 whose entire structure is i-type.

[0156] In addition, the gate insulating layer 402 serves as a dielectric, and the storage capacitor formed by the capacitance wiring and the capacitance electrode also The thin film transistor 449 and the thin film transistor 451 can be formed over the same substrate. The thin film transistors 451 and storage capacitors are arranged in a matrix in correspondence with each pixel. A pixel portion is formed, and a driver circuit having a thin film transistor 449 is arranged around the pixel portion. This makes it possible to fabricate one of the substrates for an active matrix display device. Cut.

[0157] In addition, the conductive layer 417 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 443. As a result, in the BT test, the threshold voltage of the thin film transistor 449 before and after the BT test was In addition, the conductive layer 417 has a potential that is different from that of the gate electrode layer 4. 11 may be the same as or different from the gate electrode layer. The conductive layer 417 is in a GND state, a state in which a potential of 0V is applied, or a floating state. The device may be in a ring state.

[0158] (Embodiment 3) A method for manufacturing a semiconductor device different from that of Embodiment 1 will be described with reference to FIG. 5. The same parts or parts having similar functions, and steps can be performed in the same manner as in Embodiment 1 , and repeated descriptions will be omitted.

[0159] Cross-sectional views of the manufacturing process of two thin-film transistors are shown in FIGS. 5(A) to (C).

[0160] First, in the same manner as FIG. 2(A) of Embodiment 1, a gate electrode layer 411 and a gate electrode layer 421 are formed on a substrate 400 having an insulating surface, and a gate insulating layer 402 is formed on the gate electrode layer 411 and the gate electrode layer 421, and an oxide semiconductor film 430 is formed on the gate insulating layer 402 (see FIG. 5(A)).

[0161] Next, a resist mask is formed on the oxide semiconductor film 430 by a second photolithography process, and the oxide semiconductor film 430 is selectively etched using the resist mask to form an oxide semiconductor layer that is an island-shaped oxide semiconductor layer.

[0162] Next, the resist mask is removed, and the first heat treatment is performed in the same manner as FIG. 2(B) of Embodiment 1 to perform dehydration or dehydrogenation of the oxide semiconductor layer. As the conditions for the first heat treatment for dehydration or dehydrogenation, the same conditions as those of the method for manufacturing a semiconductor device shown in Embodiment 1 can be applied . Here, a substrate on which an oxide semiconductor layer is formed is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing heat treatment on the oxide semiconductor layer in a nitrogen atmosphere, without exposing it to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 4 is obtained. 31. Obtain 432 (see Fig. 5(B)).

[0163] Next, form an oxide conductive film on the oxide semiconductor layers 431 and 432 and the gate insulating layer 402 After that, form resist masks 445a and 445b by a third photolithography process and selectively etch using the resist masks 445a and 445b to form a low-resistance source region 408a, a low-resistance drain region 408b, a source electrode layer 409a, and a drain electrode layer 409b (see Fig. 5(C)). As the material of the oxide conductive film, the same materials as in Embodiment 1 can be used.

[0164] Note that in this etching process, it is preferable that the underlying oxide semiconductor layers 431 and oxide semiconductor layer 4 32 are not etched, and the etching conditions can be appropriately set so that they are not etched. For example, the etching time can be controlled.

[0165] Also, as the materials constituting the oxide semiconductor layers 431 and 432 and the low-resistance source region 408a and the low-resistance drain region 408b, the source electrode layer 409a, and the drain electrode layer 409b, it is preferable to use materials with a high etching selectivity respectively. For example as the material constituting the oxide semiconductor layer, a metal oxide material containing Sn (for example, SnZn Ox (x>0), or SnGaZnO (x>0), etc.) is used, and as the material constituting the oxide conductive layer x Al-Zn-O-based materials, Al-Zn-O-N-based materials, Zn-O-based materials, etc. can be used. Such materials mainly composed of zinc oxide can be etched, for example, using an alkaline solution . Also, Al-Zn-O-based materials, Al-Zn-O-N-based materials ​​When using a material containing aluminum such as the material, the resist used for etching When removing the mask, it is preferable to use a method in which the oxide conductive layer is not removed together with the resist mask to remove the resist mask. For example, the resist mask can be removed by dry etching so that the resist mask can be removed without removing the oxide conductive layer.

[0166] The oxide semiconductor layer preferably has a film thickness of 50 nm or less in order to maintain an amorphous state. For example, the average film thickness of the finally fabricated thin film transistor is preferably 5 nm or more and 20 nm or less to be.

[0167] Next, in the same manner as FIG. 2(E) of Embodiment 1, an oxide insulating layer 416 in contact with the oxide semiconductor layer 431 and the oxide semiconductor layer 4 32 is formed, and a second heat treatment is performed to make the channel formation region 413 overlapping the gate electrode layer 411 of type I, and the channel formation region 423 overlapping the gate electrode layer 421 of type I, and a high-resistance source region 414a overlapping the low-resistance source region 408a is self-alignedly formed, and a high-resistance drain region 414 b overlapping the low-resistance drain region 408b is self-alignedly formed, and a high-resistance source region 424a overlapping the source electrode layer 409a is self-alignedly formed, and a high-resistance drain region 424b overlapping the drain electrode layer 409b is self-alignedly formed. As the conditions for the second heat treatment, the same conditions as the manufacturing method of the semiconductor device shown in Embodiment 1 can be used. As the conditions for the second heat treatment, the same conditions as the manufacturing method of the semiconductor device shown in Embodiment 1 can be used. to use.

[0168] Next, in the same manner as FIG. 3(A) of Embodiment 1, a fourth photolithography process is performed to form a resist mask, and by etching the oxide insulating layer 416, a low-resistance source region A region 418 in which a portion of the low-resistance drain region 408a is exposed and a region 418 in which a portion of the low-resistance drain region 408b is exposed A contact hole 426 is formed on the contact region 419 and the drain electrode layer 409b. The oxide insulating layer 416 is formed on a part of the oxide semiconductor layer 431 and the low-resistance source region 408a. And it has a structure in contact with the periphery and side surfaces of the low-resistance drain region 408b.

[0169] Next, similarly to FIG. 3(B) of the first embodiment, the resist mask is removed, and then at least the exposed On the exposed low-resistance source region 408a and low-resistance drain region 408b, contact holes A conductive film is formed over the oxide insulating layer 426 and the oxide insulating layer 416, and a fifth photolithography process is performed. Then, resist masks 438a and 438b are formed on the conductive film by selective etching. A source electrode layer 415a and a drain electrode layer 415b are formed by performing a process.

[0170] Next, similarly to FIG. 3C of the first embodiment, the resist masks 438a and 438b are removed. Then, the source electrode layer 415a, the drain electrode layer 415b, and the oxide insulating layer 416 are A planarization insulating layer 404 is formed on the insulating film 402, and a sixth photolithography step is performed. The planarization insulating layer 404 is then etched to form a contact that reaches the drain electrode layer 409b. A contact hole 441 is formed.

[0171] Next, after forming a contact hole in the same manner as in FIG. 3(D) of the first embodiment, a light-transmitting A conductive film is formed, a seventh photolithography step is performed, a resist mask is formed, and an etching process is performed. Unnecessary portions are removed by etching to form a pixel electrode layer 427 and a conductive layer 417 .

[0172] Through the above steps, using seven masks, thin film transistors 410 and thin film transistors 420 can be separately fabricated in a driving circuit or a pixel portion on the same substrate, and the number of masks can be reduced compared to the fabrication process of Embodiment 1. The thin film transistor 410 of the driving circuit is a thin film transistor including an oxide semiconductor layer 412 having a high resistance source region 414a, a high resistance drain region 414b, and a channel formation region 413, and the thin film transistor 420 of the pixel portion is a thin film transistor including an oxide semiconductor layer 422 having a high resistance source region 424a, a high resistance drain region 424 b, and a channel formation region 423. The thin film transistors 410 and 420 are such that even when a high electric field is applied, the high resistance source region 414a, the high resistance drain region 414b, the high resistance source region 424a, and the high resistance drain region 424b act as buffers and no local electric field concentration occurs, resulting in a configuration that improves the breakdown voltage of the transistor.

[0173] (Embodiment 4) A semiconductor device different from Embodiment 1 and a method of manufacturing the semiconductor device will be described with reference to FIGS. 38 to 40. FIGS. 38(B) and (C) show an example of the cross-sectional structure of two thin film transistors having different structures fabricated on the same substrate. The thin film transistors 460 and 470 shown in FIG. 38 are transistors having a bottom gate structure.

[0174] FIG. 38(A1) is a plan view of the thin film transistor 460 disposed in the driving circuit, and FIG. 38 (A2) is a plan view of the thin film transistor 470 disposed in the pixel. FIG. 38(B) is the cross-sectional structure along line G1 - G2 of FIG. 38(A1) and along line H1 - H2 of FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). There is such a thing.

[0175] The thin film transistor 460 disposed in the drive circuit includes a gate electrode layer 461, a gate insulating layer 452, an oxide semiconductor layer 462 having at least a channel formation region 463, a high-resistance source region 464a, and a high-resistance drain region 464b on a substrate 450 having an insulating surface, a low-resistance source region 446a, a low-resistance drain region 446b, a source electrode layer 465a, and a drain electrode layer 465b. Further, the thin film transistor 460 has a structure in which an oxide insulating layer 466 is provided in contact with the peripheries and sides of the low-resistance source region 446a and the low-resistance drain region 446b and a part of the oxide semiconductor layer 462. FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2).

[0176] The high-resistance source region 464a is formed self-aligned in contact with the lower surface of the low-resistance source region 446a. Further, the high-resistance drain region 464b is formed self-aligned in contact with the lower surface of the low-resistance drain region 446b. The channel formation region 463 is in contact with the oxide insulating layer 466 and is a region (type I region) having a higher resistance than the high-resistance source region 464a and the high-resistance drain region 464b. FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2).

[0177] The source electrode layer 465a is in contact with the low-resistance source region 446a, and the drain electrode layer 465b is in contact with the low-resistance drain region 446b. FIG. 38(A1) is a cross-sectional view showing a cross-sectional structure taken along line G3-G, and FIG. 38(C) is a cross-sectional view showing a cross-sectional structure taken along line G3-G in FIG. 38(A1) and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2).

[0178] Further, the thin film transistor 460 includes a low-resistance source region 446a and a low-resistance drain region 44 By providing 6b, it has a thermally stable operation compared to a Schottky junction. As such, an ohmic contact is formed by intentionally providing a low-resistance source region and a low-resistance drain region having a carrier concentration higher than that of the oxide semiconductor layer.

[0179] Also, in order to reduce the resistance of the wiring of the thin-film transistor 460, it is preferable to use a metal material for the source electrode layer 465a and the drain electrode layer 465b.

[0180] Also, a conductive layer 467 overlapping the channel formation region 463 is provided above the channel formation region 463. By electrically connecting the conductive layer 467 to the gate electrode layer 461 and setting them to the same potential, a gate voltage can be applied to the oxide semiconductor layer 462 disposed between the gate electrode layer 461 and the conductive layer 467 from above and below. Also, when the gate electrode layer 461 and the conductive layer 467 are set to different potentials, for example, a fixed potential, a GND potential, 0 V, electrical characteristics of the TFT, such as a threshold voltage, can be controlled. That is, by causing one of the gate electrode layer 461 and the conductive layer 467 to function as a first gate electrode layer and the other of the gate electrode layer 461 and the conductive layer 467 to function as a second gate electrode layer, the thin-film transistor 460 can be used as a four-terminal thin-film transistor.

[0181] Also, a planarization insulating layer 454 is laminated between the conductive layer 467, the source electrode layer 465a, the drain electrode layer 465b, and the oxide insulating layer 466.

[0182] The thin-film transistor 470 disposed in the pixel has a gate electrode layer 471, a gate insulating layer 452, at least a channel formation region 473, a high-resistance source ​ An oxide semiconductor layer 472 having a high-resistance source region 474a and a high-resistance drain region 474b, a source electrode layer 447a, and a drain electrode layer 447b are included.

[0183] Also, the high-resistance source region 474a is self-alignedly formed in contact with the lower surface of the source electrode layer 447a. Also, the high-resistance drain region 474b is self-alignedly formed in contact with the lower surface of the drain electrode layer 447b. Also, the channel formation region 473 is in contact with the oxide insulating layer 466 and is set as a region (type I region) having a higher resistance than the high-resistance source region 474a and the high-resistance drain region 474b.

[0184] Note that the oxide semiconductor layer 462 is formed below the source electrode layer 465a and the drain electrode layer 465b and partially overlaps. Also, the oxide semiconductor layer 462 overlaps with the gate electrode layer 461 via the gate insulating layer 452. That is, the gate electrode layer 461 is provided below the oxide semiconductor layer with the gate insulating layer 452 interposed therebetween. Also, the oxide semiconductor layer 472 is formed below the source electrode layer 447a and the drain electrode layer 447b and partially overlaps. Also, the oxide semiconductor layer 472 overlaps with the gate electrode layer 471 via the gate insulating layer 452. That is, the gate electrode layer 471 is provided below the oxide semiconductor layer 472 via the gate insulating layer 452.

[0185] Also, in order to realize a display device having an aperture ratio, the source electrode layer 447a and the drain electrode layer 447b of the thin film transistor 470 are formed using a conductive film having translucency.

[0186] Also, the gate electrode layer 471 of the thin film transistor 470 is also formed using a conductive film having translucency.​​​​​ is formed.

[0187] Also, in the pixel where the thin film transistor 470 is disposed, the pixel electrode layer 477 and other electrode layers (such as a capacitor electrode layer) and wiring layers (such as a capacitor wiring layer) are formed using a conductive film having light transmittance with respect to visible light, thereby realizing a display device having a high aperture ratio. Of course, it is preferable that the gate insulating layer 452 and the oxide insulating layer 466 also use films having light transmittance with respect to visible light. is preferable.

[0188] The pixel electrode layer 477 is in contact with the drain electrode layer 447b through the opening provided in the oxide insulating layer 466 and the opening provided in the planarization insulating layer 454. Note that the opening provided in the oxide insulating layer 466 is not necessarily provided.

[0189] Note that the oxide semiconductor layer 462 and the oxide semiconductor layer 472 are subjected to a heat treatment (heat treatment for dehydration or dehydrogenation) for reducing impurities such as moisture which are impurities at least after the formation of the oxide semiconductor film. After performing the heat treatment for dehydration or dehydrogenation and slow cooling, forming an oxide insulating film in contact with the oxide semiconductor layer or the like to reduce the carrier concentration of the oxide semiconductor layer is connected to the improvement of the electrical characteristics and the reliability of the thin film transistor 460 and the thin film transistor 470.

[0190] Note that in the semiconductor device shown in FIG. 38, as an example, the channel lengths of the thin film transistor 460 and the thin film transistor 470 are the same, but it is not limited thereto. For example, since the thin film transistor of the drive circuit is required to operate at a higher speed than the thin film transistor of the pixel portion, the channel length of the thin film transistor 460 may be made narrower than the channel length of the thin film transistor 470. ​ At this time, for example, the channel length of the thin film transistor 460 is about 1 μm to 5 μm. It is preferable that the channel length of the thin film transistor 470 is about 5 μm to 20 μm. is preferred.

[0191] As described above, the semiconductor device shown in FIG. 38 has a first thin film transistor on the same substrate. The pixel has a driver circuit and a second thin film transistor. The first thin film transistor is made of a light-transmitting material. The pixel portion is made of a material having a lower resistance than the material having an opening. The efficiency can be improved, and the operating speed of the drive circuit can be improved. By providing a driver circuit and a pixel portion on the same substrate, a wiring for connecting the driver circuit and the pixel portion is provided. The number of lines and the length of the wiring can be reduced, which contributes to the miniaturization and cost reduction of semiconductor devices. It is possible.

[0192] In addition, in the semiconductor device shown in FIG. 38, a source electrode layer in a thin film transistor of a driver circuit A low-resistance solenoid is provided between the drain electrode layer and the oxide semiconductor layer in which a channel formation region is formed. The structure has a low-resistance source region and a low-resistance drain region. By providing an in-region, it is possible to improve the frequency characteristics of the peripheral circuits (drive circuits). Compared with the contact between the metal electrode layer and the oxide semiconductor layer, the contact between the metal electrode layer and the low resistance source region and This is because contact with the low-resistance drain region can reduce the contact resistance. Electrode layers using molybdenum (e.g., stacking of molybdenum layer, aluminum layer, molybdenum layer, etc.) The contact resistance with the oxide semiconductor layer is high because molybdenum is less susceptible to oxidation than titanium. Since it is difficult to extract oxygen from the oxide semiconductor layer, the action of extracting oxygen is weak, and the contact interface between the molybdenum layer and the oxide semiconductor layer does not become n-type. However, by interposing a low-resistance source region and a low-resistance drain region between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (driving circuit) can be improved. Further, by providing a low-resistance source region and a low-resistance drain region, the channel length of the thin-film transistor can be determined during the etching of the layer that becomes the low-resistance source region and the low-resistance drain region, so that the channel length can be made shorter. This is because the contact interface between the oxide semiconductor layer and the source electrode layer and the drain electrode layer does not become n-type. However, by interposing a low-resistance source region and a low-resistance drain region between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (driving circuit) can be improved. Further, by providing a low-resistance source region and a low-resistance drain region, the channel length of the thin-film transistor can be determined during the etching of the layer that becomes the low-resistance source region and the low-resistance drain region, so that the channel length can be made shorter. Also, by providing a low-resistance source region and a low-resistance drain region, the channel length of the thin-film transistor can be determined during the etching of the layer that becomes the low-resistance source region and the low-resistance drain region, so that the channel length can be made shorter. This is because the channel length of the thin-film transistor is determined during the etching of the layer that becomes the low-resistance source region and the low-resistance drain region, so that the channel length can be made shorter. This is because the channel length of the thin-film transistor is determined during the etching of the layer that becomes the low-resistance source region and the low-resistance drain region, so that the channel length can be made shorter.

[0193] In addition, the semiconductor device shown in FIG. 38 has a structure in which the end of the oxide semiconductor layer of the first thin-film transistor protrudes from the ends of the low-resistance source region and the low-resistance drain region, and the end of the oxide semiconductor layer of the second thin-film transistor protrudes from the ends of the source electrode layer and the drain electrode layer. This is because the end of the oxide semiconductor layer of the first thin-film transistor protrudes from the ends of the low-resistance source region and the low-resistance drain region, and the end of the oxide semiconductor layer of the second thin-film transistor protrudes from the ends of the source electrode layer and the drain electrode layer. This is because the end of the oxide semiconductor layer of the first thin-film transistor protrudes from the ends of the low-resistance source region and the low-resistance drain region, and the end of the oxide semiconductor layer of the second thin-film transistor protrudes from the ends of the source electrode layer and the drain electrode layer. This is because the end of the oxide semiconductor layer of the first thin-film transistor protrudes from the ends of the low-resistance source region and the low-resistance drain region, and the end of the oxide semiconductor layer of the second thin-film transistor protrudes from the ends of the source electrode layer and the drain electrode layer.

[0194] In addition, the semiconductor device shown in FIG. 38 has a structure in which an oxide insulating layer is in contact with a part of the oxide semiconductor layer and the periphery and side surfaces of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer in the thin-film transistor of the driving circuit. By adopting this structure, when there is a portion (also referred to as an intersection portion) where the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode cross with an insulating layer interposed therebetween, the distance between the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode can be increased, so that the parasitic capacitance can be reduced. This is because the end of the oxide semiconductor layer of the first thin-film transistor protrudes from the ends of the low-resistance source region and the low-resistance drain region, and the end of the oxide semiconductor layer of the second thin-film transistor protrudes from the ends of the source electrode layer and the drain electrode layer. In addition, the semiconductor device shown in FIG. 38 has a structure in which an oxide insulating layer is in contact with a part of the oxide semiconductor layer and the periphery and side surfaces of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer in the thin-film transistor of the driving circuit. By adopting this structure, when there is a portion (also referred to as an intersection portion) where the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode cross with an insulating layer interposed therebetween, the distance between the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode can be increased, so that the parasitic capacitance can be reduced. In addition, the semiconductor device shown in FIG. 38 has a structure in which an oxide insulating layer is in contact with a part of the oxide semiconductor layer and the periphery and side surfaces of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer in the thin-film transistor of the driving circuit. By adopting this structure, when there is a portion (also referred to as an intersection portion) where the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode cross with an insulating layer interposed therebetween, the distance between the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode can be increased, so that the parasitic capacitance can be reduced. In addition, the semiconductor device shown in FIG. 38 has a structure in which an oxide insulating layer is in contact with a part of the oxide semiconductor layer and the periphery and side surfaces of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer in the thin-film transistor of the driving circuit. By adopting this structure, when there is a portion (also referred to as an intersection portion) where the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode cross with an insulating layer interposed therebetween, the distance between the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode can be increased, so that the parasitic capacitance can be reduced. In addition, the semiconductor device shown in FIG. 38 has a structure in which an oxide insulating layer is in contact with a part of the oxide semiconductor layer and the periphery and side surfaces of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer in the thin-film transistor of the driving circuit. By adopting this structure, when there is a portion (also referred to as an intersection portion) where the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode cross with an insulating layer interposed therebetween, the distance between the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode can be increased, so that the parasitic capacitance can be reduced. In addition, the semiconductor device shown in FIG. 38 has a structure in which an oxide insulating layer is in contact with a part of the oxide semiconductor layer and the periphery and side surfaces of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer in the thin-film transistor of the driving circuit. By adopting this structure, when there is a portion (also referred to as an intersection portion) where the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode cross with an insulating layer interposed therebetween, the distance between the wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and the drain electrode can be increased, so that the parasitic capacitance can be reduced.

[0195] Furthermore, the transistor of the present embodiment can also have the structure shown in FIG. 42. As shown in FIG. 42, The semiconductor device shown has a gate insulating layer formed by stacking a plurality of insulating layers and has a protective insulating layer on the oxide insulating layer in contact with the semiconductor layer, which is different from the semiconductor device shown in Fig. 38(B). That is, the semiconductor device shown in Fig. 42 has a stack of a gate insulating layer 452a and a gate insulating layer 452b instead of the gate insulating layer 452 shown in Fig. 38, and has a protective insulating layer 453 on the oxide insulating layer 466 shown in Fig. 38. In other configurations of the semiconductor device shown in Fig. 42, parts common to the semiconductor device shown in Fig. 38 shall be appropriately referred to the description of the semiconductor device shown in Fig. 38, and the description here shall be omitted. As the gate insulating layer 452a and the gate insulating layer 452b, for example, materials applicable to the gate insulating layer 452 shown in Fig. 38 can be used. As the gate insulating layer 452a, for example, a nitride insulating layer can be used, and as the gate insulating layer 452b, for example, an oxide insulating layer can be used. The protective insulating layer 453 is preferably configured to be in contact with the gate insulating layer 452a provided below the oxide insulating layer 466 or an insulating film serving as a base, and blocks the intrusion of moisture, hydrogen ions, and impurities such as OH from near the side surface of the substrate. In particular, it is effective to use a silicon nitride film as the gate insulating layer 452a or the insulating film serving as a base in contact with the oxide insulating layer 466. That is, when a silicon nitride layer is provided so as to surround the lower surface, upper surface, and side surface of the oxide semiconductor layer, the reliability of the semiconductor device is improved. Hereinafter, using Figs. 39(A) to (E) and Figs. 40(A) to (D), thin films on the same substrate

[0196]

[0197] -

[0198] ​​​​​​​​​​​​​​​Describe the manufacturing process of the transistor 460 and the thin-film transistor 470.

[0199] First, after forming a conductive film with light-transmitting properties on a substrate 450 having an insulating surface, a first photo lithography process is used to form a resist mask on the conductive film, and selective etching is performed using the resist mask to form the gate electrode layers 461 and 471. Also, in the pixel portion, a capacitive wiring is formed using the same material and the same first photolithography process as the gate electrode layers 461 and 471. Also, when a capacitor is required not only in the pixel portion but also in the driving circuit a capacitive wiring is formed in the driving circuit as well. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used the manufacturing cost can be reduced.

[0200] There are no major restrictions on the substrate that can be used for the substrate 450 having an insulating surface, but at least it is necessary to have heat resistance to withstand subsequent heat treatment. For the substrate 450 having an insulating surface a glass substrate or the like can be used, for example.

[0201] Also, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is advisable to use one having a strain point of 730 °C or higher Also, for the glass substrate, glass materials such as aluminosilicate glass, al uminophosphate glass, barium borate glass, etc. are used. In addition, by including more barium oxide (BaO) compared to boric acid, a more practical heat-resistant glass can be obtained. For this reason, it is preferable to use a glass substrate containing more BaO than B2O3.

[0202] ​​Note that, instead of the above glass substrate, as the substrate 450, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, as the substrate 450, crystallized glass or the like can be used. Also, an insulating film serving as an underlayer film may be provided between the substrate 450 and the gate electrode layers 461 and 471. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 450, and can be formed by a single film or a stacked film composed of a film selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0203] As materials for the gate electrode layers 461 and 471, conductive materials having translucency to visible light, for example, conductive metal oxides of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, Zn-O system can be applied, and the film thicknesses of the gate electrode layers 461 and 471 are set within the range of 50 nm or more and 300 nm or less. As a method for forming the conductive film used for the gate electrode layers 461 and 471, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spraying method is used. When the sputtering method is used, film formation is performed using a target containing 2 wt% or more and 10 wt% or less of SiO2, and the formed conductive film having translucency may contain SiOx (x>0) that inhibits crystallization. Thereby, crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process can be suppressed.

[0204] As materials for the gate electrode layers 461 and 471, conductive materials having translucency to visible light, for example, conductive metal oxides of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, Zn-O system can be applied, and the film thicknesses of the gate electrode layers 461 and 471 are set within the range of 50 nm or more and 300 nm or less. For example, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based Al-Zn-O-based, In-Sn-O-based, In-O-based, Sn-O-based, Zn-O-based conductive metal oxides can be applied, and the film thicknesses of the gate electrode layers 461 and 471 are in the range of 50 nm or more and 300 nm or less. As the method for forming the conductive film used for the gate electrode layers 461 and 471, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spraying method is used. When using the sputtering method, film formation is performed using a target containing 2 wt% or more and 10 wt% or less of SiO2, and the formed translucent conductive film may contain SiOx (x>0) that inhibits crystallization. This can suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process.

[0205] ​ Next, the resist mask is removed, and a gate insulating layer 452 is formed over the gate electrode layer 461. .

[0206] The gate insulating layer 452 can be formed of a single layer or a stack of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer by using, for example, a plasma CVD method or a sputtering method. For example, when forming a silicon oxynitride layer, the silicon oxynitride layer may be formed by a plasma CVD method using SiH4, oxygen, and nitrogen as film formation gases.

[0207] The film thickness of the gate insulating layer 452 is set to be 100 nm or more and 500 nm or less. In the case of a stack, for example, it is a stack of a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less formed over the first gate insulating layer.

[0208] In this embodiment, the gate insulating layer 452 is a silicon nitride layer having a film thickness of 200 nm or less formed by a plasma CVD method.

[0209] Next, an oxide semiconductor film 480 having a film thickness of 2 nm or more and 200 nm or less is formed over the gate insulating layer 452 (see FIG. 39(A)). Even if a heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 480, it is preferable to make the film thickness 50 nm or less in order to make the oxide semiconductor layer to be formed later amorphous. By reducing the film thickness of the oxide semiconductor film 480, when a heat treatment is performed after the formation of the oxide semiconductor film 480, crystallization of the oxide semiconductor layer to be formed later can be suppressed.

[0210] Note that before forming the oxide semiconductor film 480 by a sputtering method, argon gas is introduced. Reverse sputtering is performed to generate plasma, and it is preferable to remove dust adhering to the surface of the gate insulating layer 452. Reverse sputtering is a method of applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to form plasma near the substrate and modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. The oxide semiconductor film 480 is an In-Ga-Zn-O-based polycrystalline film, or an oxide semiconductor film of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, or Zn-O system is used. In this embodiment, the oxide semiconductor film 480 is formed by a sputtering ring method using an In-Ga-Zn-O-based oxide semiconductor target. Also, the oxide semiconductor film 480 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, the oxide semiconductor film 480 is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film 480. Thereby, it is possible to suppress crystallization of the oxide semiconductor layer formed later during the heat treatment for dehydration or dehydrogenation performed in a later step. Next, dehydration or dehydrogenation of the oxide semiconductor film 480 is performed. Reverse sputtering is a method of applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to form plasma near the substrate and modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere.

[0211] The oxide semiconductor film 480 is an In-Ga-Zn-O-based polycrystalline film, or an oxide semiconductor film of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, or Zn-O system is used. In this embodiment, the oxide semiconductor film 480 is formed by a sputtering ring method using an In-Ga-Zn-O-based oxide semiconductor target. Also, the oxide semiconductor film 480 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, the oxide semiconductor film 480 is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film 480. Thereby, it is possible to suppress crystallization of the oxide semiconductor layer formed later during the heat treatment for dehydration or dehydrogenation performed in a later step. The oxide semiconductor film 480 is an In-Ga-Zn-O-based polycrystalline film, or an oxide semiconductor film of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, or Zn-O system is used. In this embodiment, the oxide semiconductor film 480 is formed by a sputtering ring method using an In-Ga-Zn-O-based oxide semiconductor target. Also, the oxide semiconductor film 480 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, the oxide semiconductor film 480 is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film 480. Thereby, it is possible to suppress crystallization of the oxide semiconductor layer formed later during the heat treatment for dehydration or dehydrogenation performed in a later step. The oxide semiconductor film 480 is an In-Ga-Zn-O-based polycrystalline film, or an oxide semiconductor film of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, or Zn-O system is used. In this embodiment, the oxide semiconductor film 480 is formed by a sputtering ring method using an In-Ga-Zn-O-based oxide semiconductor target. Also, the oxide semiconductor film 480 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, the oxide semiconductor film 480 is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film 480. Thereby, it is possible to suppress crystallization of the oxide semiconductor layer formed later during the heat treatment for dehydration or dehydrogenation performed in a later step. The oxide semiconductor film 480 is an In-Ga-Zn-O-based polycrystalline film, or an oxide semiconductor film of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, or Zn-O system is used. In this embodiment, the oxide semiconductor film 480 is formed by a sputtering ring method using an In-Ga-Zn-O-based oxide semiconductor target. Also, the oxide semiconductor film 480 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, the oxide semiconductor film 480 is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film 480. Thereby, it is possible to suppress crystallization of the oxide semiconductor layer formed later during the heat treatment for dehydration or dehydrogenation performed in a later step. The oxide semiconductor film 480 is an In-Ga-Zn-O-based polycrystalline film, or an oxide semiconductor film of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, or Zn-O system is used. In this embodiment, the oxide semiconductor film 480 is formed by a sputtering ring method using an In-Ga-Zn-O-based oxide semiconductor target. Also, the oxide semiconductor film 480 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, the oxide semiconductor film 480 is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film 480. Thereby, it is possible to suppress crystallization of the oxide semiconductor layer formed later during the heat treatment for dehydration or dehydrogenation performed in a later step. The oxide semiconductor film 480 is an In-Ga-Zn-O-based polycrystalline film, or an oxide semiconductor film of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, or Zn-O system is used. In this embodiment, the oxide semiconductor film 480 is formed by a sputtering ring method using an In-Ga-Zn-O-based oxide semiconductor target. Also, the oxide semiconductor film 480 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, the oxide semiconductor film 480 is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film 480. Thereby, it is possible to suppress crystallization of the oxide semiconductor layer formed later during the heat treatment for dehydration or dehydrogenation performed in a later step. The oxide semiconductor film 480 is an In-Ga-Zn-O-based polycrystalline film, or an oxide semiconductor film of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, or Zn-O system is used.

[0212] Next, dehydration or dehydrogenation of the oxide semiconductor film 480 is performed.​ The temperature of the first heat treatment is 400°C or higher and lower than the strain point of the substrate, for example, 400°C or higher and 700°C or lower, preferably 425°C or higher and 700°C or lower. If it is 425°C or higher and 700°C or lower, the heat treatment time may be 1 hour or less. If it is less than 425°C, the heat treatment time shall be longer than 1 hour. Here, a substrate 450 with an oxide semiconductor film formed thereon is introduced into an electric furnace, which is one of the heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor film in a nitrogen atmosphere. After that, without exposing it to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor film is prevented to obtain an oxide semiconductor film with reduced resistance (see Fig. 39(B)). In this embodiment, from the heating temperature T for dehydrating or dehydrogenating the oxide semiconductor film 480, the same furnace is used to cool it slowly in a nitrogen atmosphere to a sufficient temperature at which water and hydrogen will not enter again. Specifically, it is cooled to a temperature 100°C or more lower than the heating temperature T. Also, it is not limited to a nitrogen atmosphere, and dehydration or dehydrogenation may be performed in an atmosphere of a noble gas such as helium, neon, or argon.

[0213] In the first heat treatment, it is preferable that nitrogen or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Or, the purity of the nitrogen or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0214] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor film 480, crystallization may occur, and it may become a microcrystalline film or a polycrystalline film.

[0215] ​​​​​​​​​​​​​​​Also, before forming the oxide semiconductor film 480, heat treatment (at 400 °C or higher and below the strain point of the substrate) may be performed in an oxygen atmosphere under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the gate insulating layer 452.

[0216] Next, an oxide conductive film is formed on the oxide semiconductor film 480, and resist masks 482a and 482b are formed by a second photolithography process. Using the resist masks 482a and 482b, the oxide conductive film and the oxide semiconductor film 480 are selectively and simultaneously etched to form oxide semiconductor layers 462 and 472, which are island-shaped oxide semiconductor layers, and oxide conductive layers 442 and 444 (see Fig. 38(C)). Note that the resist masks 482a and 482b may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0217] As a method for forming the oxide conductive film, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method is used. As the material of the oxide conductive film, a material having a higher resistance than the oxide semiconductor film 480 and a lower resistance than the source electrode layer 465a and the drain electrode layer 465b can be used. For example, conductive metal oxides of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Sn-O system, In-O system, Sn-O system, and Zn-O system can be applied. This is achievable. Also, the film thickness of the oxide conductive film is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx ( x > 0) that inhibits crystallization may be included in the conductive film having translucency. It is possible to suppress the crystallization of the oxide conductive film. .

[0218] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO = 1:1:1 [molar ratio], In:Ga:Zn = 1:1:0.5 [atom ratio]) is used, and the distance between the substrate 450 and the target is 100 mm, the pressure is 0.2 Pa, and a direct current (DC) power supply of 0.5 kW, argon and oxygen (argon:oxygen = 30 sccm:20 s ccm, oxygen flow ratio 40%) atmosphere is used to form the oxide conductive film. Note that when using a pulsed direct current (DC) power supply, dust can be reduced and the film thickness distribution becomes uniform, which is preferable. The film thickness of the In- Ga-Zn-O-based non-single crystal film is set to 5 nm to 200 nm. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O-based oxide semiconductor target is used to sputter a 20-nm-thick In-Ga-Zn-O-based non-single crystal film is formed by the ing method. Also, as the oxide semiconductor target material, for example, a target material such as In:Ga:ZnO = 1:1:1 or In :Ga:ZnO = 1:1:4 can also be used.

[0219] Note that the resist masks 482a and 482b in this embodiment are resist masks having concave parts or convex parts. In other words, it can also be said to be a resist mask composed of a plurality of regions (here two regions) with different thicknesses. The resist mask 48 In 2a or the resist mask 482b, the thick region is referred to as the convex portion of the resist mask 482a or the resist mask 482b, and the thin region is referred to as the concave portion of the resist mask 482a or the resist mask 482b. In the resist masks 482a and 482b, convex portions are formed in the portions where the source electrode layer and the drain electrode layer are formed at the lower part, and concave portions are formed in the portions where the channel formation region is formed at the lower part later.

[0220] The resist masks 482a and 482b can be formed by using a multi-tone mask. A multi-tone mask is a mask capable of performing exposure with multi-level light amounts, and typically refers to a mask that performs exposure with three levels of light amounts: an exposed region, a semi-exposed region, and an unexposed region. By using a multi-tone mask, resist masks having a plurality (typically two types) of thicknesses can be formed by a single exposure and development process. Therefore, by using a multi-tone mask, the number of photomasks can be reduced.

[0221] By exposing and developing using a multi-tone mask, resist masks 482a and 482b having regions with different thicknesses can be formed. However, it is not limited to this, and the resist masks 482a and 482b may be formed without using a multi-tone mask.

[0222] By exposing and developing using a multi-tone mask, resist masks 482a and 482b having regions with different thicknesses can be formed. However, it is not limited to this, and the resist masks 482a and 482b may be formed without using a multi-tone mask.

[0223] Next, by retracting (reducing) the resist masks 482a and 482b, the resist masks 487a and 487b are formed. To retract (reduce) the resist mask, an oxygen plasma By using ashing with Zuma, the resist mask can be reduced. As a result, the oxide semiconductor layer 462 and the oxide semiconductor layer 472 are partly exposed.

[0224] Next, selective etching is performed using the resist mask 487a and the resist mask 487b. By this, a low resistance source region 446a, a low resistance drain region 446b, and A source electrode layer 447a and a drain electrode layer 447b are formed (FIG. 39(D)).

[0225] As shown in FIG. 39(D), the resist masks 482a and 482b are recessed (reduced). The resist mask 487a and the resist mask 487b are used for etching to form an oxide film. The end of the compound semiconductor layer 462 is a low-resistance source region 446a and a low-resistance drain region 446b. The end of the oxide semiconductor layer 472 is connected to the source electrode layer 447a and the drain electrode It protrudes beyond the end of layer 447b.

[0226] In this etching process, the oxide semiconductor layer 462 and the oxide semiconductor layer 4 The etching conditions may be appropriately set so that the layer 72 remains. For example, the etching time It is sufficient to control the above.

[0227] In addition, the materials constituting the oxide semiconductor layers 462 and 472 and the oxide conductive layers 442 and 4 It is preferable to use materials having a high etching selectivity as the materials constituting 44. For example, a metal oxide material containing Sn (e.g., SnZnO x (x>0), or SnGaZnO x (x>0, etc.) and an oxide conductive layer The materials that make up the material are Al-Zn-O-based materials, Al-Zn-ON-based materials, and Zn-O-based materials. Materials or the like can be used. Materials mainly composed of such zinc oxide can be etched, for example, using an alkaline solution. When using materials containing aluminum, such as Al-Zn-O-based materials and Al-Zn- O-N-based materials, it is preferable to use a method in which the oxide conductive layer is not removed together when removing the resist mask used for etching. For example, by removing the resist mask by dry etching, the resist mask can be removed without removing the oxide conductive layer. When removing the resist mask used for etching, it is preferable to use a method in which the oxide conductive layer is not removed together. For example, by removing the resist mask by dry etching, the resist mask can be removed without removing the oxide conductive layer. For example, by removing the resist mask by dry etching, the resist mask can be removed without removing the oxide conductive layer. By removing the resist mask by dry etching, the resist mask can be removed without removing the oxide conductive layer. .

[0228] Next, after removing the resist mask 487a and the resist mask 487b, an oxide insulating layer 466 in contact with a part of the oxide semiconductor layer 462 and the oxide semiconductor layer 472 is formed. The oxide insulating layer 466 has a film thickness of at least 1 nm or more, and the oxide insulating layer 466 can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the oxide insulating layer 466, such as a sputtering method. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating layer 466 using the sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. The film formation of the silicon oxide film by the sputtering method can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, a silicon oxide film is formed by the sputtering method in an atmosphere of oxygen and nitrogen.

[0229] The oxide insulating layer 466 has a film thickness of at least 1 nm or more, and the oxide insulating layer 466 can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the oxide insulating layer 466, such as a sputtering method. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating layer 466 using the sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. The film formation of the silicon oxide film by the sputtering method can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. 6 can be formed. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating layer 466 using the sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. m of silicon oxide film is formed using the sputtering method. The substrate temperature during film formation should be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. 00 °C or lower, and in this embodiment, it is 100 °C. The silicon oxide film is formed by sputtering The film formation of the silicon oxide film by the sputtering method can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating layer 466 using the sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. The film formation of the silicon oxide film by the sputtering method can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. When using materials containing aluminum, such as Al-Zn-O-based materials and Al-Zn- O-N-based materials, it is preferable to use a method in which the oxide conductive layer is not removed together when removing the resist mask used for etching. For example, by removing the resist mask by dry etching, the resist mask can be removed without removing the oxide conductive layer. It is possible. The oxide insulating layer in contact with the oxide semiconductor layer 462 and the oxide semiconductor layer 472 466 does not contain impurities such as moisture, hydrogen ions, and OH - and blocks the intrusion of these from the outside and is formed using an inorganic insulating film, and typically formed using a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film, etc. Also, the oxide insulating layer 466 is formed using a silicon oxide film formed by using a boron-doped silicon target material to suppress the intrusion of impurities (such as moisture, hydrogen ions, and OH - etc.) ).

[0230] Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 35 0°C or lower) is performed. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer 462 and the oxide semiconductor layer 472 is heated in a state of being in contact with the oxide insulating layer 466.

[0231] By going through the above steps, the oxide semiconductor layer 462 and the oxide semiconductor layer 472 are made low-resistance oxidized, and a part of the oxide semiconductor layer 462 and the oxide semiconductor layer 472 is selectively made into an oxygen-excessive state. As a result, the channel formation region 463 overlapping with the gate electrode layer 461 becomes of type I, and the channel formation region 473 overlapping with the gate electrode layer 471 becomes of type I. A high-resistance source region 464a is self-alignedly formed in the part of the oxide semiconductor layer 462 overlapping with the low-resistance source region 446a, a high-resistance drain region 464b is self-alignedly formed in the part of the oxide semiconductor layer 462 overlapping with the low-resistance drain region 446b, and the oxide overlapping with the source electrode layer 447a resistance drain region 464b is self-alignedly formed, and the oxide A high-resistance source region 474a is self-alignedly formed in a portion of the oxide semiconductor layer 472, and a drain A high-resistance drain region 474b is self-formed in a portion of the oxide semiconductor layer 472 that overlaps with the drain electrode layer 447b (see Fig. 39(E)).

[0232] In addition, by forming a high-resistance drain region 464b (or a high-resistance source region 464a) in the oxide semiconductor layer 462 that overlaps with the low-resistance source region 446a (and the low-resistance drain region 446b), the reliability of the drive circuit can be improved. Specifically, by forming the high-resistance drain region 464b, a structure can be obtained in which the conductivity changes stepwise from the drain electrode layer 465b through the high-resistance drain region 464b to the channel formation region 463. Therefore, when the transistor is operated by electrically connecting the drain electrode layer to a wiring that supplies a high power supply potential VDD, even if a high electric field is applied between the gate electrode layer 461 and the drain electrode layer 465b, the high-resistance drain region acts as a buffer and no local electric field concentration occurs, so that the breakdown voltage of the transistor can be improved.

[0233] Also, by forming a high-resistance drain region 464b (or a high-resistance source region 464a) in the oxide semiconductor layer 462 that overlaps with the low-resistance source region 446a (and the low-resistance drain region 446b), the leakage current of the transistor in the drive circuit can be reduced.

[0234] In addition, in the oxide semiconductor layer 472 that overlaps with the drain electrode layer 447b (and the source electrode layer 447a), a high-resistance drain region 474b (or a high-resistance source region 474a) is formed. ​By doing so, the reliability of the pixel can be improved. Specifically, a high-resistance drain region 474b is formed, enabling the transistor to have a structure in which the conductivity changes step by step from the drain electrode layer 447b through the high-resistance drain region 474b to the channel formation region 473. Therefore, when the drain electrode layer 447b is electrically connected to a wiring supplying a high power supply potential VDD and operated, even if a high electric field is applied between the gate electrode layer 471 and the drain electrode layer 447b, the high-resistance drain region 474b serves as a buffer, preventing local electric field

[0235] concentration and enabling a configuration that improves the breakdown voltage of the transistor. Moreover, by forming a high-resistance drain region 474b (and a high-resistance source region 474a) in the oxide semiconductor layer 472 overlapping with the drain electrode layer 447b (and the source electrode layer 447a), the leakage current of the transistor in the pixel can be reduced.

[0236] In the semiconductor device of this embodiment, a protective insulating layer can also be provided on the oxide insulating layer 466. When providing the protective insulating layer, in this embodiment, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a film formation method for the protective insulating layer because of its good mass productivity. For example, a protective insulating layer can be formed using an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH - and blocks these from entering from the outside. A silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. can be used to form the protective insulating layer. Of course, the protective insulating layer is a transparent insulating layer.

[0237] ​​​​​​ Next, a third photolithography process is performed to form a resist mask, and a part of the low-resistance source region 446a is exposed in the oxide insulating layer 4 66 by etching, the region 428 where a part of the low-resistance drain region 446b is exposed, the low-resistance contact hole 437 reaching the drain electrode layer 447b is formed, and the oxide insulating layer 466 is on the upper surface of the oxide semiconductor layer 462 , and a structure in contact with the peripheries and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b is formed (see Fig. 40(A)). Here, the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. , and the peripheries and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b are in contact ). Note that the resist mask here may be formed by the inkjet method. Forming the resist mask by the inkjet method can reduce the manufacturing cost because a photomask is not used. Next, after removing the resist mask, a conductive film is formed on at least the exposed low-resistance source region 446a and the low-resistance drain region 446b and on the oxide insulating layer 466, and resist masks 491a and 491b are formed on the conductive film by a fourth photolithography process,

[0238] and the conductive film is selectively etched to form the source electrode layer 405a and the drain electrode layer 405b . (See Fig. 40(B)).

[0239]

[0240] Examples of the material of the conductive film for forming the source electrode layer 405a and the drain electrode layer 405b include elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, alloys containing the above-described elements as components, alloys combining the above-described elements, and the like. Examples of the conductive film include a three-layer laminated film of a titanium film, an aluminum film provided on the titanium film, and a titanium film provided on the aluminum film, or a molybdenum film, and a molybdenum film provided on the molybdenum film

[0240] ​​It is preferable to use a three-layer laminated film of a provided aluminum film and a molybdenum film provided on the aluminum film. Of course, a single-layer film, a two-layer laminated film, or a laminated film of four or more layers may be used as the conductive film. Further, when a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used as the conductive film, it can be etched by a dry etching method using chlorine gas. Next, a planarization insulating layer 454 is formed on the oxide insulating layer 466. As the planarization insulating layer 454, an organic material having heat resistance such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphorus glass), BPSG (borophosphosilicate glass), etc. can be used as the planarization insulating layer 454. Note that the planarization insulating layer 454 may be formed by laminating a plurality of insulating films formed of these materials. The method for forming the planarization insulating layer 454 is not particularly limited, and depending on the material, sputtering, SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), or tools such as a doctor knife, a roll coater, a curtain coater, and a knife coater can be used. Next, a fifth photolithography process is performed to form a resist mask, and a contact hole 494 reaching the drain electrode layer 447b is formed by etching the planarization insulating layer 454 (see FIG. 39(B)). Further, the gate electrode layers 461 and 47 are also etched here.

[0241]

[0242]

[0243] ​​​​​​​​​​​​​​Also form contact holes that reach 1. Further, a resist mask for forming contact holes that reach the drain electrode layer 447b may be formed by an inkjet method. Since forming the resist mask by the inkjet method does not use a photomask, the manufacturing cost can be reduced.

[0244] Next, after removing the resist mask, a conductive film having translucency is formed. For example, indium oxide (In2O3), indium oxide - tin oxide alloy (In2O3 - SnO2, abbreviated as ITO), etc. are formed into a conductive film having translucency by using a sputtering method, a vacuum evaporation method, etc. Further, as the conductive film having translucency, an Al - Zn - O - based non - single - crystal film containing nitrogen, that is, an Al - Zn - O - N - based non - single - crystal film, a Zn - O - N - based non - single - crystal film, or a Sn - Zn - O - N - based non - single - crystal film may be used. The composition ratio (atomic%) of zinc in the Al - Zn - O - N - based non - single - crystal film is 47 atomic% or less, is larger than the composition ratio (atomic%) of aluminum in the Al - Zn - O - N - based non - single - crystal film, and the composition ratio (atomic%) of aluminum in the Al - Zn - O - N - based non - single - crystal film is larger than the composition ratio (atomic%) of nitrogen in the Al - Zn - O - N - based non - single - crystal film. The etching treatment of a film having such a material is performed with a hydrochloric acid - based solution. However, especially for the etching of ITO, since residues are likely to occur, an indium oxide - zinc oxide alloy (In2O3 - ZnO) may be used to improve the etching processability.

[0245] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions of the conductive film having translucency are removed by etching and the resist mask is removed, ​​​​​​​​​​​​​​​​Form the pixel electrode layer 477 and the conductive layer 467 (see Fig. 39(D)).

[0246] Through the above steps, using six masks, the thin film transistors 460 and the thin film transistors 470 can be separately fabricated in the driving circuit or the pixel portion on the same substrate . The thin film transistor 460 for the driving circuit is a thin film transistor including an oxide semiconductor layer 462 having a high-resistance source region 464a, a high-resistance drain region 464b, and a channel formation region 463. The thin film transistor 470 for the pixel is a thin film transistor including an oxide semiconductor layer 472 having a high-resistance source region 474a, a high resistance drain region 474b, and a channel formation region 473 . The thin film transistors 460 and 470 are configured such that even when a high electric field is applied, the high-resistance source region 464a, the high-resistance drain region 464b, the high-resistance source region 474a, and the high-resistance drain region 474b act as buffers, preventing local electric field concentration and improving the breakdown voltage of the transistor .

[0247] Also, in the method for manufacturing the semiconductor device shown in Figs. 39 and 40, the gate insulating layer 452 is used as a dielectric, and the holding capacitor formed by the capacitance wiring and the capacitance electrode can also be formed on the same substrate as the thin film transistors 460 and the thin film transistors 470. The thin film transistor 470 and the holding capacitance are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having the thin film transistor 460 is arranged around the pixel portion, thereby forming one substrate for manufacturing an active matrix type display device .

[0248] Note that the pixel electrode layer 477 is formed in the contact hole 494 formed in the planarization insulating layer 454​​ and is electrically connected to the capacitive electrode layer through the contact hole 437 formed in the oxide insulating layer 466. Note that the capacitive electrode layer can be formed of the same material and in the same process as the source electrode layer 447a and the drain electrode layer 447b.

[0249] Further, by providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer 462, the change amount of the threshold voltage of the thin film transistor 460 before and after the bias - thermal stress test (hereinafter referred to as the BT test) for examining the reliability of the thin film transistor can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can function as the gate electrode layer. Further, the conductive layer 467 may be in a GND state, a state where a potential of 0 V is applied, or a floating state.

[0250] Also, a resist mask for forming the pixel electrode layer 477 and the conductive layer 467 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0251] (Embodiment 5) In this embodiment, an example in which the first heat treatment is different from that in Embodiment 4 is shown in FIG. 41. Since the processes are the same except that they are partially different from FIGS. 39 to 40, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted.

[0252] Cross - sectional views of the manufacturing processes of two thin film transistors are shown in FIGS. 41(A) to (C).

[0253] First, according to Embodiment 4, gate electrode layers 461 and 4 71 are formed on a substrate 450 having an insulating surface.

[0254] Next, a gate insulating layer 452 is formed on the gate electrode layers 461 and 471.

[0255] Next, an oxide semiconductor film 480 with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 452 (see Fig. 41(A)). The steps up to this point are the same as those in Embodiment 4, and Fig. 41(A) corresponds to Fig. 39(A).

[0256] Then, in an inert gas atmosphere or under reduced pressure, dehydration or dehydrogenation of the oxide semiconductor film 480 is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 350°C or higher and lower than the strain point of the substrate, preferably 400°C or higher. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor film in a nitrogen atmosphere. After that, without exposing it to the atmosphere, re - mixing of water and hydrogen into the oxide semiconductor film is prevented, and the oxide semiconductor film is made oxygen - deficient type to reduce the resistance, that is, to make it N - type (N type conversion, etc.). Then, high - purity oxygen gas or high - purity N2O gas, or ultra - dry air (dew point is - 40°C or lower , preferably - 60°C or lower) is introduced into the same furnace for cooling. It is preferable that the oxygen gas or N2O gas does not contain water, - hydrogen, etc. Or, the purity of the oxygen gas or N2O gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.9999 9%) or higher, (that is, the impurity concentration in the oxygen gas or N2O gas is 1 ppm or lower, preferably 0.1 ppm or lower).

[0257] Also, after the first heat treatment for dehydration or dehydrogenation, heating may be performed at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower, in an oxygen gas atmosphere, or in an N2O gas atmosphere or in an atmosphere of ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower). The treatment may be carried out.

[0258] By going through the above steps, the entire oxide semiconductor layer is brought into an oxygen-excessive state, increasing the resistance, i.e., making it type-I, to form the oxide semiconductor film 496 (see Fig. 41(B)). As a result, the reliability of the thin film transistor formed later can be enhanced.

[0259] Also, in an inert gas atmosphere, dehydration or dehydrogenation of the oxide semiconductor film is performed, and after cooling in the inert gas atmosphere, a resist mask is formed by a photolithography process, and the oxide semiconductor film 496 is selectively etched using the resist mask to form an oxide semiconductor layer that is an island-shaped oxide semiconductor layer. Then, heating treatment may be carried out at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower, and in an oxygen gas atmosphere, an N2O gas atmosphere, or an atmosphere of ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower). The treatment may be carried out.

[0260] Also, before forming the oxide semiconductor film 480, heat treatment (400°C or higher and below the distortion point of the substrate) may be performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), an oxygen atmosphere, or an atmosphere of ultra-dry air (dew point of -40°C or lower, preferably -60 °C or lower) to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0261] Next, in the same manner as FIGS. 39(C), 39(D), 39(E), 40(A), and 40(B) of Embodiment 4, oxide semiconductor layers 497 and 498 are formed, and low-resistance source region 446a and low-resistance drain region 446b that are in contact with oxide semiconductor layer 497 are formed. An oxide insulating layer 466 that contacts a part of oxide semiconductor layer 497 and the peripheries and sides of low-resistance source region 446a and low-resistance drain region 446b is formed. On the other hand, in the pixel portion, a source electrode layer 447a and a drain electrode layer 447b, which are conductive layers having translucency and are in contact with oxide semiconductor layer 498, are formed, and an oxide insulating layer 466 that contacts a part of oxide semiconductor layer 498 is formed. Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. As the conditions of the second heat treatment, the same conditions as those of the method for manufacturing a semiconductor device shown in Embodiment 4 can be used. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Next, a part of low-resistance source region 446a and low-resistance drain region 446b is exposed, a contact hole reaching drain electrode layer 447b is formed in oxide insulating layer 466, a conductive film is formed on oxide insulating layer 466, and the conductive film is selectively etched to form a source electrode layer 465a that contacts low-resistance source region 446a and a drain electrode layer 465b that contacts low-resistance drain region 446b. A planarization insulating layer 454 is formed in contact with oxide insulating layer 466, a contact hole reaching drain electrode layer 447b is formed in planarization insulating layer 454, and contact...

[0262]

[0263] ​​​​​​​​​​​​​​A light-transmitting conductive film is formed over the holes and the planarization insulating layer 454. A pixel electrode layer electrically connected to the drain electrode layer 447b by selectively etching the conductive film. A conductive layer 477 is formed, and then a conductive layer 467 is formed (see FIG. 41C).

[0264] Through the above steps, the entire oxide semiconductor layer was formed into an I-type structure on the same substrate using six masks. The thin film transistor 492 and the thin film transistor 493 are formed in a driver circuit or a pixel portion. The thin film transistor 492 for the driver circuit is an I-type transistor. The thin film transistor 4 for a pixel includes an oxide semiconductor layer 497. Reference numeral 93 denotes a thin film transistor including an oxide semiconductor layer 498 which is entirely i-type.

[0265] In addition, the storage capacitor formed by the capacitance wiring layer and the capacitance electrode with the gate insulating layer 452 as a dielectric is The thin film transistor 492 and the thin film transistor 493 can be formed over the same substrate. The thin film transistors 493 and storage capacitors are arranged in a matrix in correspondence with each pixel. A pixel portion is formed, and a driver circuit having a thin film transistor 492 is arranged around the pixel portion. This makes it possible to fabricate one of the substrates for an active matrix display device. Cut.

[0266] In addition, the conductive layer 467 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 497. As a result, in the BT test, the threshold voltage of the thin film transistor 492 before and after the BT test In addition, the conductive layer 467 has a potential that is different from that of the gate electrode layer 4 61 may be the same as or different from the gate electrode layer. It is also possible that the conductive layer 467 is in a GND state, a state in which a potential of 0 V is applied, or a floating state.

[0267] (Embodiment 6) A semiconductor device different from that of Embodiment 1 and a method of manufacturing the semiconductor device will be described with reference to FIGS. 43 and 44.

[0268] The semiconductor device shown in FIG. 43 has a different structure of the conductive layer overlapping the source electrode, the drain electrode, and the channel formation region of the thin film transistor in the drive circuit as compared with the semiconductor device shown in FIG. 1. Therefore, for the parts that are the same as those of the semiconductor device shown in FIG. 1, the description of the semiconductor device shown in FIG. 1 will be appropriately incorporated and the description here will be omitted.

[0269] FIG. 43(A1) is a plan view of the thin film transistor 440 arranged in the drive circuit, FIG. 43 (A2) is a plan view of the thin film transistor 420 arranged in the pixel, and FIG. 43(B) is a cross-sectional structure taken along line C5-C6 of FIG. 43 (A1) and a cross-sectional structure taken along line D5-D6 of FIG. 43(A2). FIG. 43(C) is a cross-sectional view showing the cross-sectional structure taken along line C7-C8 of FIG. 43(A1) and the cross-sectional structure taken along line D7-D8 of FIG. 43(A2).

[0270] The thin film transistor 440 arranged in the drive circuit, similar to FIG. 1, includes a gate electrode layer 411, a gate insulating layer 402, and an oxide semiconductor layer 412 having at least a channel formation region 413, a high-resistance source region 414a, and a high-resistance drain region 414b on a substrate 400 having an insulating surface. It also includes a low-resistance source region 408a and a low-resistance drain region 408b, a source electrode layer 405a, and a drain electrode layer 405b. Also, the thin film transistor ​​​​​​​​​ 440 includes the peripheries and sides of the low-resistance source region 408a and the low-resistance drain region 408b, and an oxide insulating layer 416 in contact with the oxide semiconductor layer.

[0271] Also, the high-resistance source region 414a is formed self-aligned in contact with the lower surface of the low-resistance source region 408a. Also, the high-resistance drain region 414b is formed self-aligned in contact with the lower surface of the low-resistance drain region 408 b. Also, the channel formation region 413 is in contact with the oxide insulating layer 416 and is made into a region (type I region) with higher resistance than the high-resistance source region 414a and the high-resistance drain region 414b.

[0272] Note that the semiconductor device shown in FIG. 43 has a structure having a high-resistance source region and a high-resistance drain region in the oxide semiconductor layer of the thin-film transistor, but is not limited thereto, and it is also possible to have a structure in which the entire oxide semiconductor layer is a high-resistance region (type I region) without providing the high-resistance source region and the high-resistance drain region.

[0273] The source electrode layer 405a is in contact with the low-resistance source region 408a, and the drain electrode layer 405b is in contact with the low-resistance drain region 408b.

[0274] Also, the drive circuit shown in FIG. 43 has a conductive layer 405c overlapping the channel formation region 413 above the channel formation region 413. By electrically connecting the conductive layer 405c to the gate electrode layer 411 and setting them to the same potential, a gate voltage can be applied to the oxide semiconductor layer 412 disposed between the gate electrode layer 411 and the conductive layer 405c from above and below. Also, when the gate electrode layer 41 1 and the conductive layer 405c are set to different potentials, for example, a fixed potential, GND, 0V, then TF 1 The electrical characteristics of T, such as the threshold voltage, etc., can be controlled.

[0275] The source electrode layer 405a, the drain electrode layer 405b, and the conductive layer 405c can be formed using the same material, and it is preferable to use, for example, a metal material. Furthermore, a planarization insulating layer 404 is provided on the conductive layer 405c, the source electrode layer 405a, the drain electrode layer 405b, and the oxide insulating layer 416.

[0276] Moreover, since the structure of the thin film transistor 420 disposed in the pixel is the same as that of the semiconductor device shown in FIG. 1, the description of the semiconductor device shown in FIG. 1 is incorporated herein and the description is omitted here. In the semiconductor device shown in FIG. 43, as an example, the channel lengths of the thin film transistor 440 and the thin film transistor 420 are the same, but it is not limited thereto. For example, since the thin film transistor in the driving circuit is required to operate faster than the thin film transistor in the pixel portion, the channel length of the thin film transistor 440 may be made narrower than the channel length of the thin film transistor 420.

[0277] At this time, for example, the channel length of the thin film transistor 440 is preferably about 1 μm to 5 μm, and the channel length of the thin film transistor 420 is preferably about 5 μm to 20 μm. As described above, the semiconductor device shown in FIG. 43 has a structure having a driving circuit having a first thin film transistor and a pixel portion having a second thin film transistor on the same substrate. The second thin film transistor is composed of a material having translucency, and the first thin film transistor is translucent.

[0278]

[0279] ​​​​​​​​​​It is composed of a material with lower resistance than the material having the property. Thereby, in the pixel portion, the opening ratio can be improved, and the operating speed of the drive circuit can be improved. Also , by providing the drive circuit and the pixel portion on the same substrate, the number of wirings connecting the drive circuit and the pixel portion can be reduced and the length of the wirings can be shortened, so that the semiconductor device can be miniaturized and the cost can be reduced. is possible.

[0280] Also, in the semiconductor device shown in FIG. 43, in the thin film transistor of the drive circuit, on a part of the oxide semiconductor layer, and on the periphery and side surfaces of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer, an oxide insulating layer is in contact. By adopting this structure, when there is a portion (also referred to as an intersection portion) where wirings of the same layer as the gate electrode layer and wirings of the same layer as the source electrode and the drain electrode cross each other with an insulating layer interposed therebetween, the distance between the wiring of the same layer as the gate electrode layer and the wirings of the same layer as the source electrode and the drain electrode can be widened, so that the parasitic capacitance can be reduced.

[0281] Also, in the semiconductor device shown in FIG. 43, in the thin film transistor of the drive circuit, a low-resistance source region and a low-resistance drain region are provided between the source electrode layer and the drain electrode layer and the oxide semiconductor layer in which the channel formation region is formed. By providing the low-resistance source region and the low-resistance drain region, the frequency characteristics of the peripheral circuit (drive circuit) can be improved. This is because the contact between the metal electrode layer and the low-resistance source region and the low-resistance drain region can reduce the contact resistance compared to the contact between the metal electrode layer and the oxide semiconductor layer. Also, for the electrode layer using molybdenum (for example, a stack of a molybdenum layer, an aluminum layer, and a molybdenum layer (Mo) has a high contact resistance with the oxide semiconductor layer because molybdenum is less likely to oxidize than titanium, resulting in a weak effect of extracting oxygen from the oxide semiconductor layer, and the contact interface between the molybdenum layer and the oxide semiconductor layer does not become n-type. However, by interposing low-resistance source regions and low-resistance drain regions between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (driving circuit) can be improved. Also, by providing the low-resistance source regions and the low-resistance drain regions, the channel length (L) of the thin-film transistor can be determined during the etching of the layers that become the low-resistance source regions and the low-resistance drain regions, so that the channel length can be made shorter. This is because it is difficult to oxidize, resulting in a weak effect of extracting oxygen from the oxide semiconductor layer, and the contact interface between the molybdenum layer and the oxide semiconductor layer does not become n-type. However, by interposing low-resistance source regions and low-resistance drain regions between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (driving circuit) can be improved. resistance can be reduced, and the frequency characteristics of the peripheral circuit (driving circuit) can be improved. Also, by providing low-resistance source regions and low-resistance drain regions, the frequency characteristics of the peripheral circuit (driving circuit) can be improved. By providing the low-resistance source regions and the low-resistance drain regions, the channel length (L) of the thin-film transistor can be determined during the etching of the layers that become the low-resistance source regions and the low-resistance drain regions, so that the channel length can be made shorter. This is because the channel length (L) of the thin-film transistor is determined during the etching of the layers that become the low-resistance source regions and the low-resistance drain regions, so that the channel length can be made shorter. Therefore, the channel length can be made shorter.

[0282] Also, the semiconductor device shown in FIG. 43 can have a structure in which a conductive layer formed of the same material as the source electrode layer and the drain electrode layer overlaps with the channel formation region with an oxide insulating layer interposed therebetween, and thereby the threshold voltage of the thin-film transistor can be controlled. Also, since the conductive layer is formed of the same material as the source electrode layer and the drain electrode layer of the thin-film transistor in the driving circuit, the wiring resistance can be reduced. Note that since the conductive layer is the same layer as the source electrode layer and the drain electrode layer, it is preferably arranged so as not to contact the source electrode layer or the drain electrode layer. For example, by providing another conductive layer via an insulating layer on the upper layer of the conductive layer and making an electrical connection via a contact hole provided in the insulating layer, the conductive layer can be routed. A structure can be adopted in which a conductive layer formed of the same material as the source electrode layer and the drain electrode layer overlaps with the channel formation region with an oxide insulating layer interposed therebetween, and thereby the threshold voltage of the thin-film transistor can be controlled. This allows the threshold voltage of the thin-film transistor to be controlled. Also, since the conductive layer is formed of the same material as the source electrode layer and the drain electrode layer of the thin-film transistor in the driving circuit, the wiring resistance can be reduced. Since the conductive layer is formed of the same material as the source electrode layer and the drain electrode layer of the thin-film transistor in the driving circuit, the wiring resistance can be reduced. Note that since the conductive layer is the same layer as the source electrode layer and the drain electrode layer, it is preferably arranged so as not to contact the source electrode layer or the drain electrode layer. For example, by providing another conductive layer via an insulating layer on the upper layer of the conductive layer and making an electrical connection via a contact hole provided in the insulating layer, the conductive layer can be routed. For example, by providing another conductive layer via an insulating layer on the upper layer of the conductive layer and making an electrical connection via a contact hole provided in the insulating layer, the conductive layer can be routed. By forming a structure in which an electrical connection is made via a contact hole provided in the insulating layer, the conductive layer can be routed.

[0283] Furthermore, similar to Embodiment 1, the semiconductor device of this embodiment has a gate of the thin-film transistor. The trench insulating layer can also have a two-layer structure with a protective insulating layer on the oxide insulating layer. It is possible.

[0284] Hereinafter, with reference to FIG. 44, an example of a method for manufacturing the thin film transistor 440 and the thin film transistor 420 on the same substrate will be described. An example of the manufacturing method will be described.

[0285] First, in the same manner as FIGS. 2(A), 2(B), 2(C), 2(D), 2(E) of Embodiment 1 and FIG. 3(A), a gate electrode layer 411 and a gate electrode layer 421 are formed on the substrate 400, a gate insulating layer 402 is formed on the gate electrode layer 411 and the gate electrode layer 421, an oxide semiconductor layer 412 is formed on the gate electrode layer 411 with the gate insulating layer 402 interposed therebetween, and an oxide semiconductor layer 422 is formed on the gate electrode layer 421 with the gate insulating layer 402 interposed therebetween. A first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer 412 and the oxide semiconductor layer 422. A low-resistance source region 408a and a low-resistance drain region 408b formed of an oxide conductive layer are formed on the oxide semiconductor layer 412, and a source electrode layer 409a and a drain electrode layer 409b formed of an oxide conductive layer are formed on the oxide semiconductor layer 422. An oxide insulating layer 416 is formed on a part of the oxide semiconductor layer 412, the peripheries and sides of the low-resistance source region 408a and the low-resistance drain region 408b, and the source electrode layer 409a and the drain electrode layer 409b. A second heat treatment is performed, and a part of the oxide insulating layer 416 is removed to expose a part of the low-resistance source region 408a and the low-resistance drain region 408b, and a contact hole 426 reaching the drain electrode layer 409b is formed in the oxide insulating layer 416. And an oxide semiconductor layer 422 is formed on the gate electrode layer 421 with the gate insulating layer 402 interposed therebetween. A first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer 412 and the oxide semiconductor layer 422. A low-resistance source region 408a and a low-resistance drain region 408b formed of an oxide conductive layer are formed on the oxide semiconductor layer 412. And a source electrode layer 409a and a drain electrode layer 409b formed of an oxide conductive layer are formed on the oxide semiconductor layer 422. A part of the oxide semiconductor layer 412, the peripheries and sides of the low-resistance source region 408a and the low-resistance drain region 408b, and the source electrode layer 409a and the drain electrode layer 409b. An oxide insulating layer 416 is formed on the source electrode layer 409a and the drain electrode layer 409b. A second heat treatment is performed, and a part of the oxide insulating layer 416 is removed to expose a part of the low-resistance source region 408a and the low-resistance drain region 408b. And a contact hole 426 reaching the drain electrode layer 409b is formed in the oxide insulating layer 416.

[0286]

[0286] Further, a conductive film is formed on the oxide insulating layer 416, and resist masks 448a, 448b, and 448c are formed by a photolithography process. Using the resist masks 448a, 448b, 448c, etching is performed to form the source electrode layer 405a, the drain electrode layer 405b, and the conductive layer 405c (see FIG. 44(A)).

[0287] Note that in this etching process, it is preferable that the lower-layer low-resistance source region 408a, the low-resistance drain region 408b, the source electrode layer 409a, the drain electrode layer 409b, the oxide semiconductor layer 412 and the oxide semiconductor layer 422 are not etched. To prevent etching, the etching conditions can be appropriately set. For example, the etching time can be controlled. .

[0288] Also, as the materials constituting the oxide semiconductor layers 412 and 422, and the low-resistance source region 408a and the low-resistance drain region 408b, the source electrode layer 409a, and the drain electrode layer 409b, it is preferable to use materials with a high etching selectivity respectively. For example, as the material constituting the oxide semiconductor layer, a metal oxide material containing Sn (e.g., SnZn O x (x > 0), or SnGaZnO x (x > 0), etc.) can be used. As the material constituting the oxide conductive layer, an Al-Zn-O-based material, an Al-Zn-O-N-based material, a Zn-O-based material, etc. can be used. A material mainly composed of zinc oxide such as this can be etched using, for example, an alkaline solution. Also, when using a material containing aluminum such as an Al-Zn-O-based material or an Al-Zn-O-N-based material, the resist used for etching The resist mask is removed by a method in which the oxide conductive layer is not removed together with the mask. For example, the resist mask is preferably removed by dry etching. In this manner, the resist mask can be removed without removing the oxide conductive layer.

[0289] Next, the resist masks 448a to 448c are removed, and then the source electrode layer 405a and the drain electrode layer 405b are A planarizing insulating layer 405 is formed on the conductive layer 405b and the oxide insulating layer 416. 4, a photolithography process is performed to form a resist mask, and a planarizing insulating layer 4 A contact hole 441 reaching the drain electrode layer 409b is formed by etching in step 04. (See Figure 44(B)).

[0290] Next, after removing the resist mask, a conductive film having light transmitting properties is formed, and then photolithography is performed. A resist mask is formed, and unnecessary parts are removed by etching to form pixel electrodes. The pole layer 427 is formed (see FIG. 44(C)).

[0291] In the method for manufacturing the semiconductor device of the present embodiment, as shown in FIG. The source electrode layer 409a and the drain electrode layer 409b are connected to the low-resistance drain region 408a and the low-resistance drain region 408b. The electrode layer 409b can also be formed using one mask.

[0292] Through the above steps, thin film transistors 44 are formed on the same substrate using seven or eight masks. 0 and the thin film transistor 420 are separately fabricated in the driver circuit or pixel portion. The thin film transistor 440 of the driving circuit has a high resistance source region 414a, a high resistance drain region 414b, and a The thin film including the oxide semiconductor layer 412 including the drain region 414b and the channel formation region 413 is It is a thin-film transistor, and the thin-film transistor 420 in the pixel portion has a high-resistance source region 424a , a high-resistance drain region 424b, and an oxide semiconductor layer 42 2 including a channel formation region 423. The thin-film transistor 440 and the thin-film transistor 420 are configured such that even when a high electric field is applied, the high-resistance source region 414a, the high-resistance drain region 414b, the high -resistance source region 424a, and the high-resistance drain region 424b serve as buffers and no local electric field concentration occurs, improving the breakdown voltage of the transistor.

[0293] Also, in the method of manufacturing the semiconductor device of the present embodiment, in the thin-film transistor of the drive circuit , a conductive layer overlapping the channel formation region of the semiconductor layer can be formed in the same process as the source electrode layer and the drain electrode layer. As a result, it can be manufactured without increasing the number of processes.

[0294] (Embodiment 7) A semiconductor device and a method of manufacturing a semiconductor device different from Embodiment 6 will be described with reference to FIGS. 45 and 46.

[0295] The semiconductor device shown in FIG. 45 has a different conductive layer structure overlapping the source electrode, the drain electrode, and the channel formation region of the thin-film transistor in the drive circuit compared to the semiconductor device shown in FIG. 38 of Embodiment 4. Therefore, for the same parts as those of the semiconductor device shown in FIG. 38, the description of the semiconductor device shown in FIG. 3 8 will be appropriately incorporated, and the description here will be omitted.

[0296] FIG. 45(A1) is a plan view of the thin-film transistor 490 arranged in the drive circuit, FIG. 45 (A2) is a plan view of the thin-film transistor 470 arranged in the pixel, and FIG. 45(B) is a view of FIG. Cross-sectional structure along line G5 - G6 in 45(A1) and along line H5 - H6 in Fig. 45(A2). It is a cross-sectional view showing the cross-sectional structure along line G7 - G8 in Fig. 45(A1) and the cross-sectional structure along line H7 - H8 in Fig. 45(A2). Also, Fig. 45(C) is a cross-sectional view showing the cross-sectional structure along line G7 - G8 in Fig. 45(A1) and the cross-sectional structure along line H7 - H8 in Fig. 45(A2). It is a cross-sectional view showing the cross-sectional structure along line G7 - G8 in Fig. 45(A1) and the cross-sectional structure along line H7 - H8 in Fig. 45(A2). is.

[0297] The thin film transistor 490 disposed in the drive circuit, similar to Fig. 38, has a gate electrode layer 461, a gate insulating layer 452, at least a channel formation region 463, a high-resistance source region 464a, and a high-resistance drain region 464b on a substrate 450 having an insulating surface, an oxide semiconductor layer 462, a low-resistance source region 446a, a low-resistance drain region 446b, a source electrode layer 495a, and a drain electrode layer 495b. Also, the thin film transistor 490 has a protective insulating layer 453 provided in contact with the periphery and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b, and a part of the oxide semiconductor layer 462. on a substrate 450 having an insulating surface, a gate electrode layer 461, a gate insulating layer 452, at least a channel formation region 463, a high-resistance source region 464a, and a high-resistance drain region 464b on a substrate 450 having an insulating surface, an oxide semiconductor layer 462, a low-resistance source region 446a, a low-resistance drain region 446b, a source electrode layer 495a, and a drain electrode layer 495b. Also, the thin film transistor 490 has a protective insulating layer 453 provided in contact with the periphery and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b, and a part of the oxide semiconductor layer 462. 463, a high-resistance source region 464a, and a high-resistance drain region 464b on a substrate 450 having an insulating surface, an oxide semiconductor layer 462, a low-resistance source region 446a, a low-resistance drain region 446b, a source electrode layer 495a, and a drain electrode layer 495b. Also, the thin film transistor 490 has a protective insulating layer 453 provided in contact with the periphery and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b, and a part of the oxide semiconductor layer 462. oxide semiconductor layer 462, a low-resistance source region 446a, a low-resistance drain region 446b, a source electrode layer 495a, and a drain electrode layer 495b. Also, the thin film transistor 490 has a protective insulating layer 453 provided in contact with the periphery and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b, and a part of the oxide semiconductor layer 462. 95a, and a drain electrode layer 495b. Also, the thin film transistor 490 has a protective insulating layer 453 provided in contact with the periphery and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b, and a part of the oxide semiconductor layer 462. The thin film transistor 490 has a protective insulating layer 453 provided in contact with the periphery and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b, and a part of the oxide semiconductor layer 462. is structured.

[0298] Also, the high-resistance source region 464a is formed self-aligned in contact with the lower surface of the low-resistance source region 446a. Also, the high-resistance drain region 464b is formed self-aligned in contact with the lower surface of the low-resistance drain region 446b. Also, the channel formation region 463 is in contact with the protective insulating layer 453 and is a region (type I region) with higher resistance than the high-resistance source region 464a and the high-resistance drain region 464b. Also, the high-resistance source region 464a is formed self-aligned in contact with the lower surface of the low-resistance source region 446a. Also, the high-resistance drain region 464b is formed self-aligned in contact with the lower surface of the low-resistance drain region 446b. Also, the channel formation region 463 is in contact with the protective insulating layer 453 and is a region (type I region) with higher resistance than the high-resistance source region 464a and the high-resistance drain region 464b. b and is formed self-aligned in contact with the lower surface of the low-resistance drain region 446b. Also, the channel formation region 463 is in contact with the protective insulating layer 453 and is a region (type I region) with higher resistance than the high-resistance source region 464a and the high-resistance drain region 464b. The channel formation region 463 is in contact with the protective insulating layer 453 and is a region (type I region) with higher resistance than the high-resistance source region 464a and the high-resistance drain region 464b. is made into a region with higher resistance (type I region).

[0299] Note that the semiconductor device shown in Fig. 45 has a structure with a high-resistance source region and a high-resistance drain region in the oxide semiconductor layer of the thin film transistor, but is not limited to this, and the high-resistance source region and high-resistance drain region, but is not limited to this, and the high-resistance source region and the structure can be such that the entire oxide semiconductor layer is a high-resistance region (type I region) without providing a high-resistance drain region can also be adopted.

[0300] The source electrode layer 495a is in contact with the low-resistance source region 446a, and the drain electrode layer 495b is in contact with the low-resistance drain region 446b.

[0301] Also, the drive circuit shown in FIG. 45 has a conductive layer 495c overlapping the channel formation region 463 above the channel formation region 463 By electrically connecting the conductive layer 495c to the gate electrode layer 461 and setting them to the same potential, a gate voltage can be applied to the oxide semiconductor layer 462 disposed between the gate electrode layer 461 and the conductive layer 495c from above and below. Further, when the gate electrode layer 46 1 and the conductive layer 495c are set to different potentials, for example, a fixed potential, GND, 0V, the electrical characteristics of the TFT , such as the threshold voltage, can be controlled. can be controlled.

[0302] The source electrode layer 495a, the drain electrode layer 495b, and the conductive layer 495c can be formed of the same material and it is preferable to use, for example, a metal material.

[0303] Also, in the drive circuit, a planarization insulating layer 454 is provided between the conductive layer 495c, the source electrode layer 495a and the drain electrode layer 495 b, and the oxide insulating layer 466.

[0304] Furthermore, FIG. 45(A2) is a plan view of the thin film transistor 470 disposed in the pixel. Since the structure of the thin film transistor 470 is the same as that of the semiconductor device shown in FIG. 38, the description of the semiconductor device shown in FIG. 38 is incorporated herein and the description is omitted here. is incorporated herein and the description is omitted here.

[0305] In the semiconductor device shown in FIG. 45, as an example, the channel lengths of the thin film transistor 490 and the thin film transistor 470 are the same, but it is not limited thereto. For example, since the thin film transistor in the driving circuit is required to operate at a higher speed than the thin film transistor in the pixel portion, the channel length of the thin film transistor 490 may be made narrower than the channel length of the thin film transistor 470. At this time, for example, the channel length of the thin film transistor 490 is preferably about 1 μm to 5 μm, and the channel length of the thin film transistor 470 is preferably about 5 μm to 20 μm. As described above, the semiconductor device shown in FIG. 45 has a structure including a driving circuit having a first thin film transistor and a pixel portion having a second thin film transistor on the same substrate. The second thin film transistor is formed of a light-transmissive material, and the first thin film transistor is formed of a material having a lower resistance value than the light-transmissive material. Thereby, in the pixel portion, the aperture ratio can be improved, and the operation speed of the driving circuit can be improved. Further, by providing the driving circuit and the pixel portion on the same substrate, the number of wirings for connecting the driving circuit and the pixel portion can be reduced and the length of the wirings can be shortened, so that the semiconductor device can be miniaturized and the cost can be reduced. In addition, in the semiconductor device shown in FIG. 45, the end portion of the oxide semiconductor layer of the first thin film transistor protrudes from the end portions of the low resistance source region and the low resistance drain region, and the end portion of the oxide semiconductor layer of the second thin film transistor protrudes from the end portions of the source electrode layer and the drain electrode layer. 。 。 。

[0306] 。 。 。 。 。 。 。 。

[0307] 。 。 。 。

[0308] In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, a low-resistance source region is provided between the source electrode layer and the drain electrode layer and the oxide semiconductor layer in which the channel formation region is formed. It has a structure having a low-resistance drain region. By providing the low-resistance source region and the low-resistance drain region, the frequency characteristics of the peripheral circuit (drive circuit) can be improved. This is because the contact between the metal electrode layer and the low-resistance source region and the low-resistance drain region can reduce the contact resistance compared to the contact between the metal electrode layer and the oxide semiconductor layer. Also, an electrode layer using molybdenum (for example, a stack of a molybdenum layer, an aluminum layer, a molybdenum layer, etc.) has a high contact resistance with the oxide semiconductor layer. This is because molybdenum is less likely to oxidize compared to titanium, so the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between the molybdenum layer and the oxide semiconductor layer does not become n-type. However, by interposing a low-resistance source region and a low-resistance drain region between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Also, by providing the low-resistance source region and the low-resistance drain region, the channel length (L) of the thin film transistor can be determined during the etching of the layer that becomes the low-resistance source region and the low-resistance drain region, so the channel length can be made shorter. In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, an oxide insulating layer is in contact with the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer and on a part of the oxide semiconductor layer. By adopting this structure, the thin film transistor's

[0309] In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, on a part of the oxide semiconductor layer, and on the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer, an oxide insulating layer is in contact. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, on a part of the oxide semiconductor layer, and on the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer, an oxide insulating layer is in contact. By adopting this structure, the thin film transistor's In addition, in the thin film transistor of the drive circuit of the semiconductor device shown in FIG. 45, on a part of the oxide semiconductor layer, and on the periphery and the side surface of the oxide conductive layer that is in contact with the source electrode layer and the drain electrode layer, an oxide insulating layer is in contact. By adopting this structure, the thin film transistor's The wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and drain electrode are provided in the peripheral area. When the insulating layer is sandwiched between the gate electrode layer and the gate electrode layer, the insulating layer is formed on the same layer as the gate electrode layer. Since the distance between the wiring and the wiring in the same layer as the source electrode and the drain electrode can be increased, The parasitic capacitance can be reduced.

[0310] In addition, in the semiconductor device shown in FIG. 45, an oxide insulating layer is formed in the thin film transistor of the driver circuit. The source electrode layer and the drain electrode layer are made of the same material as the drain electrode layer. A structure having a conductive layer formed thereon can be obtained, which reduces the threshold voltage of the thin film transistor. The conductive layer can be used as a source electrode of a thin film transistor of a driving circuit. Since the drain electrode layer and the drain electrode layer are made of the same material, the wiring resistance can be reduced. do.

[0311] Further, as in the fourth embodiment, the semiconductor device of the present embodiment has a gate electrode for a thin film transistor. Alternatively, the oxide insulating layer may be made into a two-layer structure with a protective insulating layer on top of the oxide insulating layer. do.

[0312] In the following, referring to FIG. 46, a thin film transistor 490 and a thin film transistor 470 are formed on the same substrate. An example of a method for producing the above will be described.

[0313] First, referring to FIG. 39(A), FIG. 39(B), FIG. 39(C), FIG. 39(D), and FIG. 40(A), a gate electrode layer 461 and a gate electrode layer 462 are formed on a substrate 450. A gate electrode layer 461 is formed on the gate electrode layer 471, and a gate insulating layer 45 is formed on the gate electrode layer 461 and the gate electrode layer 471. 2, an oxide semiconductor film 480 is formed over the gate insulating layer 452, and first heat treatment is performed. Perform dehydration or dehydrogenation of the oxide semiconductor film to obtain the oxide semiconductor film 481, and further form an oxide conductive film on the oxide semiconductor film 481, and form resist masks 482a and resist mask 482b using a multi-tone mask, and etch the oxide semiconductor film 481 and the oxide conductive film using the resist masks 482a and resist mask 482b. Thereby, an oxide semiconductor layer 462 is formed on the gate electrode layer 461 with the gate insulating layer 452 interposed therebetween, and an oxide semiconductor layer 47 2 is formed on the gate electrode layer 471 with the gate insulating layer 452 interposed therebetween, the resist masks 482a and resist mask 482b are removed, and a low-resistance source region 446a and a low-resistance drain region 446b composed of an oxide conductive layer are formed on the oxide semiconductor layer 462, and a source electrode layer 447a and a drain electrode layer 447b composed of an oxide conductive layer are formed on the oxide semiconductor layer 472. An oxide insulating layer 466 is formed on a part of the oxide semiconductor layer, the peripheries and sides of the low-resistance source region 446a and the low-resistance drain region 446b, and the source electrode layer 447a and the drain electrode layer 447b. A second heat treatment is performed, and a part of the oxide insulating layer 466 is removed to expose a part of the low-resistance source region 4 46a and the low-resistance drain region 446b, and a contact hole 437 reaching the drain electrode layer 409b is formed in the oxide insulating layer 466. Furthermore, a conductive film is formed on the oxide insulating layer 466, and resist masks 455a, 455b, and 455c are formed by a photolithography process, and selective etching is performed to form a source electrode layer 495a, a drain electrode layer 495b, and a conductive layer 495c (see FIG. 46(A) ).

[0314] ).

[0315] Note that in this etching process, the lower-layer low-resistance source region 446a, low-resistance drain region 446b, source electrode layer 447a, drain electrode layer 447b, oxide semiconductor layer 462 and oxide semiconductor layer 472 are preferably not etched, and the etching conditions can be appropriately set to achieve this. For example, the etching time can be controlled. .

[0316] Also, as the materials constituting the oxide semiconductor layers 462 and 472, and the low-resistance source region 446a, low-resistance drain region 446b, source electrode layer 447a, and drain electrode layer 447b, it is preferable to use materials with a high etching selectivity respectively. For example, as the material constituting the oxide semiconductor layer, a metal oxide material containing Sn (such as SnZnOx or SnGaZnOx, etc.) can be used, and as the material constituting the oxide conductive layer, an Al-Zn-O-based material, an Al-Zn-O-N-based material, a Zn-O-based material, etc. can be used. A material mainly composed of zinc oxide like this can be etched using, for example, an alkaline solution. Also, when using a material containing aluminum such as an Al-Zn-O-based material or an Al-Zn-O-N-based material, it is preferable to remove the resist mask using a method such that the oxide conductive layer is not removed together. For example, by removing the resist mask by dry etching, the resist mask can be removed without removing the oxide conductive layer.

[0317] Next, after removing the resist masks 455a to 455c, the source electrode layer 495a, drain A planarization insulating layer 45 is formed on the oxide insulating layer 466 and the conductive layer 495c. 4, a photolithography process is performed to form a resist mask, and a planarizing insulating layer 4 A contact hole 494 reaching the drain electrode layer 447b is formed by etching 54. (See Figure 46(B)).

[0318] Next, after removing the resist mask, a conductive film having light transmitting properties is formed, and then photolithography is performed. A resist mask is formed, and unnecessary parts are removed by etching to form pixel electrodes. A pole layer 477 is formed.

[0319] Through the above steps, the thin film transistor 490 and the thin film transistor 491 are formed on the same substrate using six masks. The film transistor 470 can be separately manufactured for the driver circuit or pixel portion, In addition, the number of masks can be reduced compared to the manufacturing process of the sixth embodiment. The transistor 490 includes a high-resistance source region 464a, a high-resistance drain region 464b, and a channel region 464c. A thin film transistor including an oxide semiconductor layer 462 including a panel formation region 463 is provided. The thin film transistor 470 has a high resistance source region 474a and a high resistance drain region 474b. and a thin film transistor including an oxide semiconductor layer 472 including a channel formation region 473. The thin film transistor 490 and the thin film transistor 470 have high resistance even when a high electric field is applied. A high-resistance source region 464a, a high-resistance drain region 464b, a high-resistance source region 474a, The anti-drain region 474b acts as a buffer to prevent localized electric field concentration, and the transistor insulation This structure improves edge pressure resistance.

[0320] In addition, in the method for manufacturing the semiconductor device of this embodiment mode, In the same process as the source electrode layer and the drain electrode layer, a conductive layer overlapping the channel formation region of the semiconductor layer can be formed. As a result, it can be manufactured without increasing the number of processes. Note that this embodiment can be appropriately combined with other embodiments.

[0321] (Embodiment 8) In this embodiment, an example of manufacturing an active matrix type liquid crystal display device using the active matrix substrate shown in Embodiment 1 will be described. Note that this embodiment can also be applied to the active matrix substrates shown in Embodiments 2 to 7.

[0322] An example of the cross-sectional structure of the active matrix substrate is shown in FIG. 7(A).

[0323] In Embodiments 1 to 7, the thin film transistors of the drive circuit and the thin film transistors of the pixel portion are illustrated on the same substrate. However, in this embodiment, in addition to those thin film transistors, the holding capacitor, the terminal portions of the gate wiring, the source wiring, and the wiring crossing portions will also be illustrated and described. The capacitor, the gate wiring, the terminal portions of the source wiring, and the wiring crossing portions can be formed in the same process as any of the manufacturing processes of the semiconductor devices shown in Embodiments 1 to 7, and can be manufactured without increasing the number of photomasks or the number of processes. Also, in the portion that becomes the display region of the pixel portion, all of the gate wiring, the source wiring, and the capacitor wiring layer are formed of a conductive film having translucency, and a high aperture ratio is realized. Further, for the source wiring layer in the portion that is not the display region, a metal wiring can be used to reduce the wiring resistance to a low resistance. Note that in this embodiment, as an example of the thin film transistor of the drive circuit, the thin film transistor 440 shown in FIG. 43 is A case of use will be described, and as an example of the thin film transistor in the pixel portion, the thin film transistor 420 shown in FIG. 43 will be described, but the present invention is not limited thereto.

[0324] In FIG. 7(A), the thin film transistor 210 is a thin film transistor provided in the driving circuit, and the thin film transistor 220 electrically connected to the pixel electrode layer 227 is a thin film transistor provided in the pixel portion.

[0325] As the thin film transistor 220 formed above the substrate 200, in the present embodiment, the same structure as the thin film transistor 440 in FIG. 43 is used.

[0326] The material having the same light transmissivity as the gate electrode layer of the thin film transistor 220 and the capacitive wiring layer 230 formed in the same process overlap with the capacitive electrode layer 231 via the gate insulating layer 202 serving as a dielectric to form a holding capacitor. Note that the capacitive electrode layer 231 is made of the same material having the same light transmissivity as the source electrode layer or the drain electrode layer of the thin film transistor 220 and is formed in the same process. Therefore, in addition to the

[0327] fact that the thin film transistor 220 has light transmissivity, each holding capacitor also has light transmissivity, so that the aperture ratio can be improved. The fact that the holding capacitor has light transmissivity is important for improving the aperture ratio. Especially in a small liquid crystal display panel of 10 inches or less, in order to increase the number of gate wirings and refine the display image, even if the pixel This is possible. That is, even when a high-density thin-film transistor group is arranged, the aperture ratio can be increased, and the area of the display region can be sufficiently secured. For example, when there are 2 to 4 sub-pixels and a holding capacitance in one pixel, in addition to the thin-film transistor having translucency, each holding capacitance also has translucency, so the aperture ratio can be improved.

[0328] Note that the holding capacitance is provided below the pixel electrode layer 227, and the capacitance electrode layer 231 is electrically connected to the pixel electrode layer 227.

[0329] In this embodiment, an example of forming the holding capacitance using the capacitance electrode layer 231 and the capacitance wiring layer 230 is shown, but the structure for forming the holding capacitance is not particularly limited. For example, without providing the capacitance wiring layer, the pixel electrode layer may be overlapped with the gate wiring of adjacent pixels through the planarization insulating layer, the oxide insulating layer, and the gate insulating layer to form the holding capacitance.

[0330] Also, in FIG. 7(A), since the holding capacitance forms a large capacitance, only the gate insulating layer 202 is provided between the capacitance wiring and the capacitance electrode, and at the wiring intersection, in order to reduce the parasitic capacitance, a gate insulating layer 202 and an oxide insulating layer 266 are provided between the gate wiring layer 232 and the wiring formed above it. Note that in order to increase the holding capacitance, it is preferable to reduce the film thickness of the gate insulating layer. Therefore, a configuration may be adopted in which the gate insulating layer on the capacitance wiring is thinned during the selective etching of the oxide insulating layer 266.

[0331] Also, a plurality of gate wirings, source wirings, and capacitance wiring layers are provided according to the pixel density. ​​​​​​​​​This is the case. Also, in the terminal portion, a plurality of terminal electrodes having the same potential as the gate wiring, terminal electrodes having the same potential as the source wiring, terminal electrodes having the same potential as the capacitor wiring layer, etc. are arranged side by side. The number of each of these terminal electrodes may be arbitrarily set, and the implementer may appropriately determine it. In the terminal portion, the terminal electrode having the same potential as the gate wiring can be formed of a material having the same light transmissivity as the pixel electrode layer 227. The terminal electrode having the same potential as the gate wiring is electrically connected to the gate wiring through a contact hole reaching the gate wiring. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. Also, the gate electrode layer of the thin film transistor 210 in the drive circuit may be structured to be electrically connected to the conductive layer 405c provided above the oxide semiconductor layer. In that case, using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227, the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 are selectively etched to form a contact hole. The conductive layer 405c and the gate electrode layer of the thin film transistor 210 in the drive circuit are electrically connected through this contact hole. Further, the terminal electrode layer 235 having the same potential as the terminal electrode layer 234 in the drive circuit is the same as the pixel electrode layer 227.

[0332] In the terminal portion, the terminal electrode having the same potential as the gate wiring can be formed of a material having the same light transmissivity as the pixel electrode layer 227. The terminal electrode having the same potential as the gate wiring is electrically connected to the gate wiring through a contact hole reaching the gate wiring. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The number of each of these terminal electrodes may be arbitrarily set, and the implementer may appropriately determine it. In the terminal portion, the terminal electrode having the same potential as the gate wiring can be formed of a material having the same light transmissivity as the pixel electrode layer 227. The terminal electrode having the same potential as the gate wiring is electrically connected to the gate wiring through a contact hole reaching the gate wiring. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227.

[0333] Also, the gate electrode layer of the thin film transistor 210 in the drive circuit may be structured to be electrically connected to the conductive layer 405c provided above the oxide semiconductor layer. In that case, using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227, the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 are selectively etched to form a contact hole. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The contact hole reaching the gate wiring is formed by selectively etching the planarization insulating layer 204, the oxide insulating layer 266, and the gate insulating layer 202 using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227.

[0334] Also, the terminal electrode layer 235 having the same potential as the terminal electrode layer 234 in the drive circuit is the same as the pixel electrode layer 227. It can be formed of a material having the same light transmittance. The terminal electrode layer 235 is electrically connected to the terminal electrode layer 23 4 through a contact hole reaching the terminal electrode layer 234. The terminal electrode layer 234 is a metal wiring, formed of the same material and by the same process as the source electrode layer of the thin film transistor 210, and has the same potential.

[0335] Also, the third terminal electrode having the same potential as the capacitance wiring layer 230 can be formed of a material having the same light transmittance as the pixel electrode layer 227. Further, the contact hole reaching the capacitance wiring layer 230 can be formed by the same photomask and the same process as the contact hole for electrically connecting the capacitance electrode layer 231 to the pixel electrode layer 227.

[0336] Also, when manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode (also referred to as a counter electrode layer), and the active matrix substrate and the counter substrate are fixed. Note that a common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrode electrically connected to the common electrode is provided at the terminal portion. This fourth terminal electrode is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc. The fourth terminal electrode can be formed of a material having the same light transmittance as the pixel electrode layer 227.

[0337] Also, the gate electrode layer of the thin film transistor 210 of the drive circuit or the terminal electrode having the same potential as the gate electrode layer and the drain electrode layer of the thin film transistor 210 of the drive circuit or the terminal electrode having the same potential as the drain electrode layer are connected through a contact hole provided by etching the gate insulating layer 202. It can be electrically connected via. For example, as shown in FIG. 7, the electrode 272 can be electrically connected to the electrode 271 through a contact hole provided in the gate insulating layer 202. At this time, a part of the oxide insulating layer 266 may be removed. Thereby, a good contact can be obtained and the contact resistance can be reduced. Therefore, the number of openings can be reduced, and the occupied area can be reduced by reducing the number of openings. Also, in FIG. 7, an example in which the gate electrode layer of the thin film transistor 210 in the drive circuit or the terminal electrode having the same potential as the gate electrode layer and the drain electrode layer or the terminal electrode having the same potential as the drain electrode layer are electrically connected through a contact hole provided in the gate insulating layer 202 has been described. However, the present invention is not limited to this, and the gate electrode layer of the thin film transistor 220 in the pixel portion or the terminal electrode having the same potential as the gate electrode layer and the drain electrode layer or the terminal electrode having the same potential as the drain electrode layer may be electrically connected through a contact hole provided in the gate insulating layer 202. Moreover, the structure for electrically connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 is not particularly limited. For example, a connection electrode connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be formed in the same process as the pixel electrode layer 227. Also, in a portion that is not the display area, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be configured to be in contact with each other and overlapped. Note that the cross-sectional structure of the gate wiring layer 232 of the drive circuit is shown in FIG. 7(A).

[0338]

[0339]

[0340] ​​​​​​​​​​​​​​ Since the state is an example of a small liquid crystal display panel with a size of 10 inches or less, the gate wiring layer of the driving circuit 232 uses a material having the same light transmissivity as the gate electrode layer of the thin film transistor 220 .

[0341] In addition, if the same material is used for the gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrode layer or other wiring layer, a common sputtering target and a common manufacturing apparatus can be used, and the material cost and the cost required for the etchant (or etching gas) used during etching can be reduced, and as a result, the manufacturing cost can be reduced .

[0342] In addition, in the structure of FIG. 7(A), when a photosensitive resin material is used as the planarization insulating layer 204 , the step of forming a resist mask can be omitted.

[0343] In addition, FIG. 7(B) shows a cross-sectional structure partially different from that of FIG. 7(A). Since FIG. 7(B) is the same as FIG. 7( A) except that the planarization insulating layer 204 does not exist, the same reference numerals are used for the same locations, and the detailed description of the same locations is omitted. In FIG. 7(B), the pixel electrode layer 227 and the conductive layer 405c are formed in contact with the oxide insulating layer 266, and the terminal electrode layer 235 is formed on the terminal electrode layer 234 . If the structure of FIG. 7(B) is adopted, the step of the planarization insulating layer 204 can be omitted. .

[0344] If the structure of FIG. 7(B) is adopted, the step of the planarization insulating layer 204 can be omitted.

[0345] (Embodiment 9) In this embodiment, when the size of the liquid crystal display panel exceeds 10 inches, is 60 inches, or even 120 inches, there is a possibility that the wiring resistance of the light-transmissive wiring may become a problem. Therefore An example of reducing wiring resistance by using a...

Claims

【Claim 1】 A driving circuit having a first thin film transistor and a pixel having a second thin film transistor on the same substrate, wherein the first thin film transistor includes: a first gate electrode layer; a gate insulating layer provided on the first gate electrode layer; a first oxide semiconductor layer provided on the first gate electrode layer with the gate insulating layer therebetween and having a first channel formation region; a first oxide conductive layer and a second oxide conductive layer provided on the first oxide semiconductor layer; an oxide insulating layer in contact with a part of the first oxide semiconductor layer and in contact with the peripheries and sides of the first oxide conductive layer and the second oxide conductive layer; a first source electrode layer in contact with the first oxide conductive layer; a first drain electrode layer in contact with the second oxide conductive layer; and the second thin film transistor includes: a second gate electrode layer made of a light-transmissive material; a second oxide semiconductor layer provided on the second gate electrode layer with the gate insulating layer therebetween and having a second channel formation region; a second source electrode layer and a second drain electrode layer provided on the second oxide semiconductor layer and made of a light-transmissive material. A semiconductor device.

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