Method for manufacturing semiconductor device

Abstract

To provide a semiconductor device that can prevent a reduction in the mobility of a carrier.SOLUTION: A method for manufacturing a semiconductor device of an embodiment includes: performing first ion injection of injecting aluminum (Al) into a silicon carbide layer in a first projected range and with a first dosage; performing second ion injection of injecting carbon (C) into the silicon carbide layer in a second projected range and with a second dosage that is 10 or more times the first dosage; performing first heat treatment at 1600°C or more; performing oxidation treatment of oxidizing the silicon carbide layer; performing etching treatment of etching the silicon carbide layer in an atmosphere including hydrogen gas; forming a silicon oxide film on the silicon carbide layer; and forming a gate electrode on the silicon oxide film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device, a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator.

Background Art

[0002] Silicon carbide (SiC) is expected as a material for next-generation semiconductor devices. Silicon carbide has excellent physical properties such as a bandgap three times that of silicon (Si), a breakdown electric field strength about 10 times that of silicon, and a thermal conductivity about 3 times that of silicon. By utilizing these characteristics, a semiconductor device capable of low-loss and high-temperature operation can be realized.

[0003] For example, when forming a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) using silicon carbide, there are problems such as a decrease in carrier mobility and fluctuations in the threshold voltage.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing a decrease in carrier mobility.

Means for Solving the Problems

[0007] The method for manufacturing a semiconductor device according to an embodiment performs a first ion implantation for implanting aluminum (Al) into a silicon carbide layer with a first projected range and a first dose amount, performs a second ion implantation for implanting carbon (C) into the silicon carbide layer with a second projected range and a second dose amount that is 10 times or more the first dose amount, performs a first heat treatment at 1600°C or higher, performs an oxidation treatment for oxidizing the silicon carbide layer, performs an etching treatment for etching the silicon carbide layer in an atmosphere containing hydrogen gas, forms a silicon oxide film on the silicon carbide layer, and forms a gate electrode on the silicon oxide film.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] Also, in the following description, when there is notation of n + , n, n - and, p + , p, p - , it represents the relative high and low of the impurity concentration in each conductivity type. That is, n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that the n + type and n - type may be simply described as the n-type, and the p + type and p - type may be simply described as the p-type. The impurity concentration of each region is represented by the value of the impurity concentration at the center of each region, unless otherwise specified.

[0011] The impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Also, the relative level of the impurity concentration can be determined, for example, from the level of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). Further, distances such as the width and depth of the impurity region can be obtained, for example, by SIMS. Also, distances such as the width and depth of the impurity region can be obtained, for example, from the SCM image.

[0012] The depth of the trench, the thickness of the insulating layer, etc. can be measured, for example, from the SIMS profile, on the image of a Transmission Electron Microscope (TEM), or on the image of a Scanning Electron Microscope (SEM).

[0013] The bonding states of silicon atoms, carbon atoms, nitrogen atoms, and oxygen atoms in the silicon carbide layer can be identified, for example, by using X-ray photoelectron spectroscopy (XPS). Also, the concentrations of various bonding states and the magnitude relationship of the concentrations can be determined, for example, by using X-ray photoelectron spectroscopy (XPS).

[0014] (First Embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer, a gate electrode, a silicon oxide layer between the silicon carbide layer and the gate electrode, and a region located between the silicon carbide layer and the silicon oxide layer, where the nitrogen concentration is 1×10 21 cm -3 or higher, and the concentration distributions of nitrogen in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, and in the portion between the silicon oxide layer and the first position 100 nm away from the silicon carbide layer side of the silicon oxide layer, the ratio of the intensity of the infrared absorption at a wave number of 838 cm -1 to the intensity of the infrared absorption at a wave number of 970 cm -1 is 1.0 or less, and the nitrogen concentration at the second position 1 nm away from the peak toward the silicon oxide layer side is 1×1018 cm -3 is as follows, and the concentration of carbon at the second position is 1×10 18 cm -3 is as follows, and the concentration of nitrogen at the third position 1 nm away from the peak toward the silicon carbide layer is 1×10 18 cm -3 is as follows.

[0015] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. The semiconductor device is a MOSFET 100. The MOSFET 100 is a Double Implantation MOSFET (DIMOSFET) that forms a p-well and a source region by ion implantation. Also, the MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0016] The MOSFET 100 includes a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, and an interface termination region 40 (region).

[0017] The silicon carbide layer 10 includes a drain region 12, a drift region 14 (first silicon carbide region), a p-well region 16 (second silicon carbide region), a source region 18, and a p-well contact region 20. The p-well region 16 has a channel portion 16a (portion).

[0018] The silicon carbide layer 10 is, for example, a single crystal of 4H-SiC. The silicon carbide layer 10 is located between the source electrode 34 and the drain electrode 36.

[0019] FIG. 2 is a diagram showing the crystal structure of a SiC semiconductor. A typical crystal structure of a SiC semiconductor is a hexagonal system such as 4H-SiC. One of the planes (the top surface of the hexagonal prism) with the c-axis along the axial direction of the hexagonal prism as the normal is the (0001) plane. A plane equivalent to the (0001) plane is referred to as the silicon plane (Si plane) and denoted as {0001} plane. Silicon atoms (Si) are arranged on the outermost surface of the silicon plane.

[0020] The other surface (the top surface of the hexagonal prism) with the c-axis along the axial direction of the hexagonal prism as the normal is the (000-1) plane. A plane equivalent to the (000-1) plane is referred to as the carbon plane (C plane) and denoted as {000-1} plane. Carbon atoms (C) are arranged on the outermost surface of the carbon plane.

[0021] On the other hand, the side surface (cylindrical surface) of the hexagonal prism is the m plane, which is a plane equivalent to the (1-100) plane, that is, the {1-100} plane. Also, the plane passing through a pair of non-adjacent ridge lines is the a plane, which is a plane equivalent to the (11-20) plane, that is, the {11-20} plane. Both silicon atoms (Si) and carbon atoms (C) are arranged on the outermost surfaces of the m plane and the a plane.

[0022] Hereinafter, a case where the front surface of the silicon carbide layer 10 is inclined by 0 degrees or more and 8 degrees or less with respect to the silicon plane and the back surface is inclined by 0 degrees or more and 8 degrees or less with respect to the carbon plane will be described as an example. The front surface of the silicon carbide layer 10 has an off-angle of 0 degrees or more and 8 degrees or less with respect to the silicon plane.

[0023] The drain region 12 is made of n + -type SiC. The drain region 12 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 or more and 1×10 21 cm -3 or less.

[0024] The drift region 14 is provided above the drain region 12. The drift region 14 is made of n - -type SiC. The drift region 14 contains, for example, nitrogen as an n-type impurity.

[0025] The n-type impurity concentration of the drift region 14 is lower than the n-type impurity concentration of the drain region 12. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 or more and 2×10 16 cm -3 or less. The drift region 14 is, for example, an epitaxial growth layer of SiC formed on the drain region 12 by an epitaxial growth method.

[0026] The thickness of the drift region 14 is, for example, 5 μm or more and 100 μm or less.

[0027] The p-well region 16 is provided on a part of the surface of the drift region 14. The p-well region 16 is located between the drift region 14 and the gate insulating layer 28. The p-well region 16 is made of p-type SiC.

[0028] The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 16 is, for example, 1×10 16 cm -3 or more and 1×10 20 cm -3 or less.

[0029] The depth of the p-well region 16 is, for example, 0.4 μm or more and 0.8 μm or less. The p-well region 16 functions as the channel region of the MOSFET 100.

[0030] The channel portion 16a is located between the gate insulating layer 28 and a first position (X1 in FIG. 1) 100 nm away from the gate insulating layer 28 toward the side of the silicon carbide layer 10. The channel portion 16a is located within the p-well region 16.

[0031] In the channel portion 16a, the ratio of the intensity of the infrared absorption at a wave number of 838 cm -1 to the intensity of the infrared absorption at a wave number of 970 cm -1 measured by the attenuated total reflection method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) is 1.0 or less.

[0032] In the channel portion 16a, the Z 1 / 2 level density measured by Deep Level Transient Spectroscopy (DLTS) is 1×10 11 cm -3 or less. The carbon vacancy density in the channel portion 16a is 1×10 11 cm -3 or less.

[0033] The hole mobility of the channel portion 16a is, for example, 200 cm 2 / V·s or more. The hole mobility is the mobility of electrons measured by Hall Effect Measurement.

[0034] The source region 18 is provided on a part of the surface of the p-well region 16. The source region 18 is made of n + -type SiC. The source region 18 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 18 is, for example, 1×10 18 cm -3 or more and 1×10 22 cm -3 or less.

[0035] The depth of the source region 18 is shallower than the depth of the p-well region 16. The depth of the source region 18 is, for example, 0.2 μm or more and 0.4 μm or less.

[0036] The p-well contact region 20 is provided on a part of the surface of the p-well region 16. The p-well contact region 20 is provided on the side of the source region 18. The p-well contact region 20 is made of p + -type SiC.

[0037] The p-well contact region 20 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the p-well contact region 20 is, for example, 1×10 18 cm -3 or more and 1×10 22 cm -3 or less.

[0038] The depth of the p-well contact region 20 is shallower than the depth of the p-well region 16. The depth of the p-well contact region 20 is, for example, 0.2 μm or more and 0.4 μm or less.

[0039] The gate insulating layer 28 is provided between the silicon carbide layer 10 and the gate electrode 30. The gate insulating layer 28 is provided between the drift region 14 and the gate electrode 30, and between the p-well region 16 and the gate electrode 30. The gate insulating layer 28 is provided over the drift region 14 and the p-well region 16. The gate insulating layer 28 is continuously formed on the surfaces of the drift region 14 and the p-well region 16.

[0040] The gate insulating layer 28 contains silicon oxide. The gate insulating layer 28 is an example of a silicon oxide layer.

[0041] The thickness of the gate insulating layer 28 is, for example, 30 nm or more and 100 nm or less. The gate insulating layer 28 functions as the gate insulating layer of the MOSFET 100.

[0042] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the gate insulating layer 28, and between the p-well region 16 and the gate insulating layer 28. The interface termination region 40 contains nitrogen (N) as a termination element that terminates the dangling bonds of the silicon carbide layer 10. The interface termination region 40 is an example of a region.

[0043] The nitrogen concentration in the interface termination region 40 is, for example, 1×10 21 cm -3 or more.

[0044] FIG. 3 is a diagram showing the element concentration distribution of the semiconductor device of the first embodiment. FIG. 3 is a diagram showing the element concentration distribution in the gate insulating layer 28, the interface termination region 40, and the silicon carbide layer 10. FIG. 3 shows the concentration distributions of nitrogen and carbon.

[0045] The nitrogen concentration distribution has a peak in the interface termination region 40. The peak nitrogen concentration is, for example, 1×10 22 cm -3 or more. The full width at half maximum of the nitrogen concentration distribution peak is, for example, 1 nm or less. Nitrogen is segregated at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0046] The nitrogen concentration at the peak of the nitrogen concentration distribution is, for example, 1×10 21 cm -3 or more and 4×10 23 cm -3 or less.

[0047] The nitrogen concentration at a second position (X2 in FIG. 3) 1 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28 is 1×10 18 cm -3 or less. Also, the nitrogen concentration at a third position (X3 in FIG. 3) 1 nm away from the peak of the nitrogen concentration distribution toward the silicon carbide layer 10 is 1×10 18 cm -3 or less.

[0048] FIG. 4 is a schematic diagram showing the bonding state of nitrogen atoms in the semiconductor device of the first embodiment. FIG. 4(a) shows the case where the nitrogen atom is three-coordinated, and FIG. 4(b) shows the case where the nitrogen atom is four-coordinated.

[0049] In the case of three-coordination shown in FIG. 4(a), the nitrogen atom bonds to three silicon atoms. In the case of four-coordination shown in FIG. 4(b), the nitrogen atom bonds to four silicon atoms.

[0050] In the interface termination region 40, the amount of nitrogen atoms bonding to three silicon atoms is larger than the amount of nitrogen atoms bonding to four silicon atoms. In other words, in the interface termination region 40, the amount of three-coordinated nitrogen atoms is larger than the amount of four-coordinated nitrogen atoms.

[0051] For example, 90% or more of the nitrogen atoms present in the interface termination region 40 are three-coordinated nitrogen atoms. The concentration of the three-coordinated nitrogen atoms is, for example, 1×10 21 cm -3 or more.

[0052] The three-coordinated nitrogen atoms present in the interface termination region 40 terminate the dangling bonds on the surface of the silicon carbide layer 10.

[0053] The nitrogen atoms in the interface termination region 40 replace the carbon atoms in the outermost layer of the silicon carbide layer 10. The nitrogen atoms in the interface termination region 40 are bonded to the silicon carbide layer 10 in a three-coordination manner. The nitrogen atoms are located at the positions of the carbon atoms in the crystal structure of silicon carbide. The silicon atoms of the silicon carbide layer 10 are three-coordinated to the nitrogen atoms.

[0054] The nitrogen atoms in the interface termination region 40 replace the carbon atoms of the bilayer constituting the outermost layer of the silicon carbide layer 10. The terminal element is finally bonded to the silicon carbide layer 10 in a three-coordination manner. The surplus silicon atoms and carbon atoms are released from the silicon carbide layer 10 toward the gate insulating layer 28 side. The nitrogen atoms are located at the positions of the carbon atoms in the crystal structure of silicon carbide. A part of the outermost surface silicon atoms enters the gate insulating layer 28, and the nitrogen atoms are three-coordinated to the silicon atoms of the silicon carbide layer 10.

[0055] The nitrogen atoms present in the bulk of the silicon carbide layer 10 and replacing the carbon sites in the crystal structure of silicon carbide are four-coordinated. The four-coordinated nitrogen atoms function as n-type dopants, thus reducing the threshold voltage of the MOSFET.

[0056] The concentration of nitrogen atoms bonded to the four silicon atoms at the third position X3 is 1×10 18 cm -3 or less. In other words, the concentration of the four-coordinated nitrogen atoms at the third position X3 is 1×10 18 cm -3 or less.

[0057] The carbon concentration distribution decreases from the interface termination region 40 toward the gate insulating layer 28. The carbon concentration at the second position X2 is 1×10 18 cm -3 or less.

[0058] The concentration of the composite defects of carbon defects and nitrogen defects, including the carbon atoms bonded to oxygen atoms and the nitrogen atoms bonded to oxygen atoms, at the second position X2 is, for example, 1×10 18 cm -3 or less.

[0059] The composite defects of carbon defects and nitrogen defects have a C-O-N bonding state. Carbon and nitrogen are formed by entering the silicon sites of silicon oxide in the gate insulating layer 28, and are adjacent to each other with one oxygen in between.

[0060] This composite defect is formed when a large amount of carbon and nitrogen are present during the formation process of silicon oxide. The carbon defect existing alone is formed by carbon entering the oxygen position of silicon oxide. Also, the nitrogen defect existing alone is formed by nitrogen entering the oxygen position of silicon oxide. Therefore, the carbon defect and nitrogen defect existing alone can be removed by oxidation.

[0061] However, the composite defect is difficult to be removed by oxidation, remains in the silicon oxide, and causes the characteristic degradation of the MOSFET. To form silicon oxide with fewer composite defects, it is preferable to have a manufacturing process in which excess carbon and excess nitrogen do not coexist in the silicon oxide.

[0062] The amount of nitrogen atoms bonded to 4 silicon atoms at the fourth position (X4 in FIG. 1) 5 nm away from the side of the silicon carbide layer 10 from the gate insulating layer 28 is, for example, 80% or more and 120% or less of the amount of nitrogen atoms bonded to 4 silicon atoms at the fifth position (X5 in FIG. 1) 5 μm away from the side of the silicon carbide layer 10 from the gate insulating layer 28. In other words, the amount of four-coordinated nitrogen atoms at the fourth position X4 is 80% or more and 120% or less of the amount of four-coordinated nitrogen atoms at the fifth position X5.

[0063] The concentration of nitrogen at the fourth position X4 is, for example, 1×10 18 cm -3 or less. The concentration of nitrogen at the fifth position X5 is, for example, 1×10 18 cm -3 or less. The concentration of nitrogen at the fourth position X4 is, for example, 80% or more and 120% or less of the concentration of nitrogen at the fifth position X5.

[0064] The fourth position X4 is located, for example, within the p-well region 16. The fifth position X5 is located, for example, within the drift region 14.

[0065] The gate electrode 30 is provided on the gate insulating layer 28. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the silicon carbide layer 10. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the drift region 14. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the p-well region 16.

[0066] The gate electrode 30 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0067] The interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is located between the gate electrode 30 and the source electrode 34. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0068] The source electrode 34 is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16. The source electrode 34 is in contact with, for example, the source region 18 and the p-well contact region 20.

[0069] The source electrode 34 has, for example, a laminated structure of a barrier metal layer of Ni (nickel) and a metal layer of aluminum on the barrier metal layer. The barrier metal layer of nickel and the silicon carbide layer may react to form nickel silicide (such as NiSi, Ni2Si). The barrier metal layer of nickel and the metal layer of aluminum may react to form an alloy.

[0070] The drain electrode 36 is provided on the side opposite to the source electrode 34 of the silicon carbide layer 10, that is, on the back side. The drain electrode 36 is electrically connected to the drain region 12. The drain electrode 36 is in contact with, for example, the drain region 12.

[0071] The drain electrode 36 is, for example, nickel. Nickel may react with the drain region 12 to form nickel silicide (such as NiSi, Ni2Si).

[0072] In the first embodiment, the n-type impurity is, for example, nitrogen or phosphorus. It is also possible to apply arsenic (As) or antimony (Sb) as the n-type impurity.

[0073] In the first embodiment, the p-type impurity is, for example, aluminum. It is also possible to apply boron (B), gallium (Ga), or indium (In) as the p-type impurity.

[0074] Next, an example of the manufacturing method of the semiconductor device of the first embodiment will be described.

[0075] The manufacturing method of the semiconductor device of the first embodiment performs a first ion implantation of injecting aluminum (Al) into the silicon carbide layer with a first projected range and a first dose amount, a second ion implantation of injecting carbon (C) into the silicon carbide layer with a second projected range and a second dose amount which is 10 times or more of the first dose amount, performs a first heat treatment at 1600 °C or higher, performs an oxidation treatment of oxidizing the silicon carbide layer, performs an etching treatment of etching the silicon carbide layer in an atmosphere containing hydrogen gas, forms a silicon oxide film on the silicon carbide layer, and forms a gate electrode on the silicon oxide film. Also, the manufacturing method of the semiconductor device of the first embodiment performs a second heat treatment in an atmosphere containing nitrogen after forming the silicon oxide film. And the above atmosphere is at least one atmosphere selected from the group consisting of a first atmosphere containing ammonia gas, a second atmosphere containing nitrogen gas and hydrogen gas, and a third atmosphere containing nitrogen gas and carbon dioxide gas.

[0076] Hereinafter, the case where the second heat treatment is performed in a first atmosphere containing ammonia gas (NH3) will be described as an example.

[0077] FIG. 5 is a process flow diagram of a method for manufacturing a semiconductor device according to the first embodiment. FIGS. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 are explanatory diagrams of the method for manufacturing a semiconductor device according to the first embodiment. FIGS. 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 are cross-sectional views during manufacturing. FIG. 9 is a diagram showing the element distribution immediately after ion implantation.

[0078] As shown in FIG. 5, the method for manufacturing a semiconductor device according to the first embodiment includes silicon carbide layer preparation (step S100), aluminum ion implantation (step S101), carbon ion implantation (step S102), phosphorus ion implantation (step S103), aluminum ion implantation (step S104), carbon film formation (step S105), first heat treatment (step S106), carbon film removal (step S107), field oxide film formation (step S108), sacrificial oxide film formation (step S109), hydrogen etching treatment (step S110), silicon oxide film formation (step S111), second heat treatment (step S112), third heat treatment (step S113), gate electrode formation (step S114), interlayer insulating film formation (step S115), and source electrode / drain electrode formation (step S116).

[0079] In step S100, a silicon carbide layer 10 is prepared (FIG. 6). The silicon carbide layer 10 includes an n + -type drain region 12 and an n - -type drift region 14. The drift region 14 is formed, for example, by epitaxial growth on the drain region 12.

[0080] The drain region 12 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 or more and 1×10 21 cm -3 or less.

[0081] The drift region 14 contains nitrogen as an n-type impurity. The n-type impurity concentration in the drift region 14 is, for example, 1×10 15 cm -3 or more and 2×10 16 cm -3 or less. The thickness of the drift region 14 is, for example, 5 μm or more and 100 μm or less.

[0082] In step S101, for example, the first mask material 51 is formed by forming an insulating film and patterning the insulating film by photolithography and etching. Then, using the first mask material 51 as an ion implantation mask, aluminum is ion-implanted into the drift region 14. By the ion implantation, a p-well region 16 is formed (FIG. 7).

[0083] The ion implantation for forming the p-well region 16 is an example of the first ion implantation. The ion implantation of aluminum is performed with a first projected range and a first dose amount. The projected range is the average projected range.

[0084] The first projected range is, for example, 0.1 μm or more and 0.6 μm or less. The first dose amount is, for example, 1×10 12 cm -2 or more and 1×10 14 cm -2 or less.

[0085] In step S102, using the first mask material 51 as an ion implantation mask, carbon is ion-implanted into the p-well region 16 (FIG. 8). The ion implantation of carbon into the p-well region 16 is an example of the second ion implantation. The ion implantation of carbon is performed with a second projected range and a second dose amount. Then, the first mask material 51 is removed.

[0086] The second projected range is, for example, 0.1 μm or more and 0.6 μm or less. The second projected range is, for example, 80% or more and 120% or less of the first projected range. The second dose amount is 10 times or more the first dose amount. The second dose amount is, for example, 10,000 times or less the first dose amount. The second dose amount is, for example, 1×10 15 cm -2 or more and 1×10 18 cm -2 or less.

[0087] FIG. 9 shows the concentration distribution of aluminum implanted into the silicon carbide layer 10 by the first ion implantation and the concentration distribution of carbon implanted into the silicon carbide layer 10 by the second ion implantation. FIG. 9 shows the elemental distribution immediately after the ion implantation.

[0088] As shown in FIG. 9, the second projected range Rp2 of the carbon ion implantation is located in the vicinity of the first projected range Rp1 of the aluminum ion implantation. And since the second dose amount of the carbon ion implantation is 10 times or more the first dose amount of the aluminum ion implantation, the concentration distribution of carbon after the ion implantation completely covers, for example, the concentration distribution of aluminum after the ion implantation.

[0089] The peak concentration of the aluminum distribution is, for example, 1×10 16 cm -3 or more and 1×10 20 cm -3 or less. The peak concentration of the carbon distribution is, for example, 1×10 18 cm -3 or more and 1×10 22 cm -3 or less.

[0090] In step S103, for example, the second mask material 52 is formed by forming an insulating film and patterning the insulating film by photolithography and etching. Then, using the second mask material 52 as an ion implantation mask, phosphorus (P) is ion implanted into the drift region 14 to form the source region 18 (FIG. 10). Thereafter, the second mask material 52 is removed.

[0091] In step S104, for example, the third mask material 53 is formed by forming an insulating film and patterning the insulating film by photolithography and etching. Using the third mask material 53 as an ion implantation mask, aluminum is ion-implanted into the drift region 14 to form the p-well contact region 20 (FIG. 11).

[0092] Next, the third mask material 53 is removed (FIG. 12).

[0093] In step S105, a carbon film 54 is formed on the silicon carbide layer 10 (FIG. 13).

[0094] In step S106, a first heat treatment is performed. The first heat treatment is performed at 1600° C. or higher. The first heat treatment is performed, for example, at 2000° C. or lower. The first heat treatment is performed in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The first heat treatment is performed, for example, in an argon gas atmosphere.

[0095] By the first heat treatment, the aluminum and phosphorus ion-implanted into the silicon carbide layer 10 are activated. The first heat treatment is an activation anneal of aluminum and phosphorus. Further, by the first heat treatment, the interstitial carbon formed by carbon ion implantation into the silicon carbide layer 10 fills the carbon vacancies in the silicon carbide layer 10.

[0096] The carbon film 54 suppresses the desorption of silicon and carbon from the silicon carbide layer 10 into the atmosphere during the first heat treatment. Further, the carbon film 54 absorbs the excess interstitial carbon in the silicon carbide layer 10 during the first heat treatment.

[0097] The first heat treatment is composed of, for example, a first step at 1600° C. or higher and a second step at a temperature lower than the first step. The second step is, for example, 1000° C. or lower.

[0098] For example, in the first step, aluminum and phosphorus ion-implanted into the silicon carbide layer 10 are activated, and the interstitial carbon fills the carbon vacancies. For example, in the second step at a low temperature, the excess interstitial carbon is expelled from the silicon carbide layer 10 and absorbed by the carbon film 54.

[0099] In step S107, the carbon film 54 is removed (FIG. 14). The removal of the carbon film 54 is performed by an ashing process using oxygen plasma. The carbon film 54 is removed in the oxygen plasma.

[0100] When performing the ashing process using oxygen plasma, the surface of the silicon carbide layer 10 is oxidized. The ashing process using oxygen plasma is an example of an oxidation process.

[0101] In step S108, a field oxide film 55 is formed on the silicon carbide layer 10 (FIG. 15). The field oxide film 55 contains oxygen. The field oxide film 55 is, for example, a silicon oxide film. The field oxide film 55 is deposited, for example, by a vapor phase growth method. The field oxide film 55 is formed, for example, by a Chemical Vapor Deposition method (CVD method) or a Physical Vapor Deposition method (PVD method).

[0102] When depositing the field oxide film 55, the surface of the silicon carbide layer 10 is oxidized. The deposition process for depositing the field oxide film 55 is an example of an oxidation process. The field oxide film 55 functions as an element isolation region in a peripheral region (not shown), for example.

[0103] Next, the field oxide film 55 is removed. The field oxide film 55 is removed, for example, using a wet etching method.

[0104] In step S109, a sacrificial oxide film 56 is formed on the silicon carbide layer 10 (FIG. 16). The sacrificial oxide film 56 is, for example, a silicon oxide film. The sacrificial oxide film 56 is formed by thermal oxidation of the surface of the silicon carbide layer 10.

[0105] When forming the sacrificial oxide film 56, the surface of the silicon carbide layer 10 is oxidized. The thermal oxidation process for forming the sacrificial oxide film 56 is an example of an oxidation process. By forming the sacrificial oxide film 56, for example, impurities and damage on the surface of the silicon carbide layer 10 are removed.

[0106] Next, the sacrificial oxide film 56 is removed. The sacrificial oxide film 56 is removed, for example, by using a wet etching method.

[0107] In step S110, a hydrogen etching process is performed to etch the surface of the silicon carbide layer 10 in an atmosphere containing hydrogen gas (FIG. 17). The temperature of the hydrogen etching process is, for example, 1300 °C or higher and 1500 °C or lower. By the hydrogen etching process, the surface of the silicon carbide layer 10 is etched, for example, 10 nm or more and 100 nm or less.

[0108] The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 90% or higher. The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 95% or higher. The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 100%. The atmosphere of the hydrogen etching process may contain, for example, argon gas.

[0109] In step S111, a silicon oxide film 57 is formed on the silicon carbide layer 10 (FIG. 18). The silicon oxide film 57 will ultimately become the gate insulating layer 28.

[0110] The silicon oxide film 57 is formed, for example, by a vapor deposition method at low temperature and low oxygen partial pressure. The silicon oxide film 57 is formed, for example, by a CVD method or a PVD method at low temperature and low oxygen partial pressure. The silicon oxide film 57 is a deposited film. The thickness of the silicon oxide film 57 is, for example, 30 nm or more and 100 nm or less.

[0111] The silicon oxide film 57 is, for example, a silicon oxide film formed by CVD using tetraethyl orthosilicate (TEOS) as a source gas. Also, the silicon oxide film 57 is, for example, a silicon oxide film formed by CVD using dichlorosilane gas (SiH2Cl2) and nitrous oxide gas (N2O) as source gases.

[0112] In step S112, a second heat treatment is performed. The second heat treatment is performed in an atmosphere containing ammonia gas (NH3).

[0113] For example, ammonia gas (NH3) is supplied to a reactor containing the silicon carbide layer 10 for heat treatment.

[0114] The temperature of the second heat treatment is, for example, 1200 °C or higher and 1600 °C or lower.

[0115] The partial pressure of ammonia gas in the atmosphere of the second heat treatment is, for example, 90% or higher.

[0116] By the second heat treatment, an interface termination region 40 is formed at the interface between the silicon carbide layer 10 and the silicon oxide film (Fig. 19).

[0117] The second heat treatment also functions as a densification anneal of the silicon oxide film. By the second heat treatment, the silicon oxide film becomes a high-density film.

[0118] In step S113, a third heat treatment is performed. The third heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx). The nitrogen oxide gas is, for example, nitric oxide gas (NO). Also, the nitrogen oxide gas is, for example, nitrous oxide gas (N2O).

[0119] For example, nitrogen oxide gas (NOx) is supplied to a reactor containing the silicon carbide layer 10 for heat treatment.

[0120] The temperature of the third heat treatment is, for example, 750°C or higher and 1050°C or lower. The temperature of the third heat treatment is, for example, lower than the temperature of the second heat treatment.

[0121] The partial pressure of nitrogen oxide gas in the atmosphere of the third heat treatment is, for example, 10% or higher.

[0122] By the third heat treatment, nitrogen in the silicon oxide film is removed. By the third heat treatment, a silicon oxide film with reduced nitrogen defects is formed.

[0123] In step S114, a gate electrode 30 is formed on the gate insulating layer 28. The gate electrode 30 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0124] In step S115, an interlayer insulating film 32 is formed on the gate electrode 30 (FIG. 20). The interlayer insulating film 32 is, for example, a silicon oxide film.

[0125] In step S116, a source electrode 34 and a drain electrode 36 are formed. The source electrode 34 is formed on the source region 18 and the p-well contact region 20. The source electrode 34 is formed, for example, by sputtering nickel (Ni) and aluminum (Al).

[0126] The drain electrode 36 is formed on the back side of the silicon carbide layer 10. The drain electrode 36 is formed, for example, by sputtering nickel.

[0127] By the above manufacturing method, the MOSFET 100 shown in FIG. 1 is formed.

[0128] Next, the operations and effects of the semiconductor device and the manufacturing method of the semiconductor device according to the first embodiment will be described.

[0129] In the MOSFET 100 of the first embodiment, the amount of carbon vacancies in the silicon carbide layer 10 is reduced, thereby suppressing a decrease in carrier mobility. Further, in the manufacturing method of the MOSFET 100 of the first embodiment, in addition to ion implantation of aluminum, carbon is ion implanted, and after the oxidation treatment, the surface of the silicon carbide layer 10 is subjected to hydrogen etching treatment, whereby the amount of carbon vacancies in the silicon carbide layer 10 is reduced. This will be described in detail below.

[0130] When forming a MOSFET using silicon carbide, there is a problem that the carrier mobility decreases. One factor contributing to the decrease in carrier mobility is considered to be the intersurface state between the silicon carbide layer and the gate insulating layer. The interface level is considered to be caused by dangling bonds existing on the surface of the silicon carbide layer.

[0131] The MOSFET 100 of the first embodiment includes an interface termination region 40 in which nitrogen is segregated between the silicon carbide layer 10 and the gate insulating layer 28. In the interface termination region 40, nitrogen atoms are bonded to silicon atoms in a three-fold coordination, thereby reducing dangling bonds. Therefore, a MOSFET with suppressed reduction in carrier mobility is realized.

[0132] It is preferable that 90% or more of the nitrogen atoms present in the interface termination region 40 are three-fold coordinated nitrogen atoms, and more preferably 99% or more are three-fold coordinated nitrogen atoms. The concentration of three-fold coordinated nitrogen atoms is, for example, 1×10 21 cm -3 or more. The concentration of four-fold coordinated nitrogen atoms is, for example, 1×10 19 cm -3 or less. The concentration of four-fold coordinated nitrogen atoms is preferably 1×10 18 cm -3 or less, and more preferably 1×10 17 cm -3 or less.

[0133] From the viewpoint of suppressing the decrease in carrier mobility of the MOSFET 100, the nitrogen concentration at the peak of the nitrogen concentration distribution in the interface termination region 40 is 1×1022 cm -3 It is preferably the above, and 5×10 22 cm -3 It is more preferably the above.

[0134] When there is excess nitrogen, the nitrogen concentration at the peak of the interface termination region 40 of the nitrogen concentration distribution becomes a charge trap, so 1×10 23 cm -3 The following is preferred.

[0135] The nitrogen concentration at the peak of the interface termination region 40 of the nitrogen concentration distribution is 5.0×10 22 cm -3 ±5% is preferable. When the peak nitrogen concentration is in the range of 5.0×10 22 cm -3 ±5%, the MOSFET 100 exhibits good characteristics with few charge traps.

[0136] The surface density of nitrogen in the interface termination region 40 is 1×10 14 cm -2 or more and 2.5×10 15 cm -2 or less is preferable. The surface density of nitrogen in the interface termination region 40 is 1.4×10 15 cm -2 ±5% is preferable. When the surface density of nitrogen is in the above range, the MOSFET 100 exhibits good characteristics with few charge traps.

[0137] Also, when forming a MOSFET using silicon carbide, there are problems such as a decrease in carrier mobility and fluctuations in the threshold voltage. There are also problems such as an increase in the leakage current of the gate insulating layer and a decrease in the reliability of the gate insulating layer. One factor causing the above problems is considered to be carbon defects and nitrogen defects present in the gate insulating layer.

[0138] Carbon defects and nitrogen defects are considered to be factors causing the above problems by forming trap levels in the gate insulating layer.

[0139] In the MOSFET 100 of the first embodiment, the nitrogen concentration at the second position X2, which is 1 nm away from the peak of the interface termination region 40 of the nitrogen concentration distribution, toward the gate insulating layer 28, is 1×10 18 cm -3 or less, and the carbon concentration at the second position X2 is 1×10 18 cm -3 or less. In the MOSFET 100, the concentrations of carbon and nitrogen in the gate insulating layer 28 are low. Therefore, the amounts of carbon defects and nitrogen defects in the gate insulating layer 28 are sufficiently reduced. Thus, a decrease in carrier mobility, fluctuations in threshold voltage, an increase in leakage current of the gate insulating layer, or a decrease in reliability of the gate insulating layer due to carbon defects or nitrogen defects is suppressed.

[0140] The nitrogen concentration at the second position X2, which is 1 nm away from the peak of the interface termination region 40 of the nitrogen concentration distribution, toward the gate insulating layer 28, is preferably 1×10 17 cm -3 or less, and more preferably 1×10 16 cm -3 or less.

[0141] Another factor contributing to the problem of a decrease in carrier mobility when forming a MOSFET using silicon carbide is considered to be the presence of carbon vacancies in the silicon carbide layer 10.

[0142] For example, it is considered that the presence of carbon vacancies in the channel formation region of the MOSFET scatters carriers and reduces the carrier mobility.

[0143] In the MOSFET 100 of the first embodiment, in the channel portion 16a between the gate insulating layer 28 and the first position X1, which is 100 nm away from the gate insulating layer 28 toward the silicon carbide layer 10, the Z 1 / 2 level density measured by DLTS is 1×10 11 cm -3 or less.

[0144] The Z 1 / 2The level density corresponds to the density of carbon vacancies. Z 1 / 2 When the level density is 1×10 11 cm -3 or less, the density of carbon vacancies under the gate insulating layer 28 becomes 1×10 11 cm -3 or less. The density of carbon vacancies under the channel portion 16a of the gate insulating layer 28 is sufficiently reduced. Therefore, a decrease in carrier mobility due to carbon vacancies in the silicon carbide layer 10 is suppressed.

[0145] The Z measured by DLTS 1 / 2 level density is preferably 5×10 10 cm -3 or less, and more preferably 1×10 10 cm -3 or less. That is, the density of carbon vacancies under the gate insulating layer 28 is preferably 5×10 10 cm -3 or less, and more preferably 1×10 10 cm -3 or less. A decrease in carrier mobility due to carbon vacancies in the silicon carbide layer 10 is further suppressed.

[0146] The intensity of infrared absorption at a wave number of 838 cm -1 measured by the total reflection measurement method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) corresponds to the density of carbon vacancies. The infrared absorption at a wave number of 838 cm -1 corresponds to residual products generated in the silicon carbide layer when the silicon carbide layer is oxidized. The residual products have Si-O bonds. The infrared absorption at a wave number of 838 cm -1 is based on the presence of Si-O bonds.

[0147] When the silicon carbide layer is oxidized, the lattice of silicon carbide is distorted and carbon vacancies are formed. Therefore, the density of carbon vacancies is high in a portion where the density of residual products in the silicon carbide layer is high.

[0148] In the MOSFET 100 of the first embodiment, in the channel portion 16a between the gate insulating layer 28 and the first position X1 which is 100 nm away from the gate insulating layer 28 toward the side of the silicon carbide layer 10, the ratio of the intensity of infrared absorption at a wave number of 838 cm -1 to the intensity of infrared absorption at a wave number of 970 cm -1 measured by the total reflection measurement method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) is 1.0 or less. The infrared absorption at a wave number of 970 cm -1 corresponds to the longitudinal optical phonon mode of silicon carbide. The intensity of infrared absorption at a wave number of 970 cm -1 is used to normalize the intensity of infrared absorption at a wave number of 838 cm -1 .

[0149] In the channel portion 16a of the p-well region 16 of the MOSFET 100, the ratio of the intensity of infrared absorption at a wave number of 838 cm -1 to the intensity of infrared absorption at a wave number of 970 cm -1 measured by the total reflection measurement method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) is 1.0 or less, and the density of carbon vacancies in the p-well region 16 directly under the gate insulating layer 28 is low. Therefore, a decrease in carrier mobility due to carbon vacancies in the silicon carbide layer 10 is suppressed.

[0150] From the viewpoint of suppressing a decrease in carrier mobility, in the channel portion 16a of the p-well region 16, the ratio of the intensity of infrared absorption at a wave number of 838 cm -1 to the intensity of infrared absorption at a wave number of 970 cm -1 measured by the total reflection measurement method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) is preferably 0.5 or less, and more preferably 0.1 or less.

[0151] In MOSFET 100, the amount of nitrogen atoms bonded to four silicon atoms at the fourth position X4, which is 5 nm away from the gate insulating layer 28 toward the silicon carbide layer 10, is 80% or more and 120% or less of the amount of nitrogen atoms bonded to four silicon atoms at the fifth position X5, which is 5 μm away from the gate insulating layer 28 toward the silicon carbide layer 10. In other words, the amount of four-coordinated nitrogen atoms at the fourth position X4 is 80% or more and 120% or less of the amount of four-coordinated nitrogen atoms at the fifth position X5. The four-coordinated nitrogen atoms function as donors.

[0152] The concentration of nitrogen at the fourth position X4 is preferably 18 cm -3 or less, more preferably 17 cm -3 or less, and even more preferably 16 cm -3 or less. The concentration of nitrogen at the fifth position X5 is preferably 18 cm -3 or less, more preferably 17 cm -3 or less, and even more preferably 16 cm -3 or less.

[0153] In MOSFET 100, due to the low density of carbon vacancies in the channel portion 16a, the density of carbon vacancies in the channel portion 16a is substantially equal to the density of carbon vacancies in the drift region 14. Therefore, the amount of nitrogen atoms that fill the carbon vacancies in the channel portion 16a to form four coordination is substantially equal to the amount of nitrogen atoms that fill the carbon vacancies in the drift region 14 to form four coordination. Thus, the amount of four-coordinated nitrogen atoms in the channel portion 16a is 80% or more and 120% or less of the amount of four-coordinated nitrogen atoms in the drift region 14.

[0154] In the MOSFET 100 of the first embodiment, the density of carbon vacancies in the channel portion 16a is sufficiently low. For this reason, the hole mobility of electrons in the channel portion 16a is 2 / V·s or more. The hole mobility of electrons in the channel portion 16a is2 Preferably, it is 450 cm or more per V·s, and more preferably 450 cm or more per V·s. 2 / V·s or more is even more preferable.

[0155] The field-effect mobility, which is an index of the on-current of the MOSFET, is determined according to the ratio of mobile charges among the hole mobilities. That is, the field-effect mobility is smaller than the hole mobility. At the MOS interface of silicon carbide, due to the poor interface termination efficiency and a large number of substrate defects and defects in the gate insulating layer, the ratio of mobile charges is low. Charges other than mobile charges are trap charges.

[0156] For example, it is possible to increase the ratio of mobile charges by optimizing the interface termination method and termination elements. However, if the hole mobility is low, it is difficult to significantly improve the field-effect mobility. In order to significantly improve the field-effect mobility, it is desired to improve the hole mobility to 150 cm or more per V·s. 2 / V·s or more.

[0157] In the first embodiment, by reducing the density of carbon vacancies, it becomes possible to significantly improve the hole mobility. The hole mobility is, for example, 200 cm or more per V·s. By further reducing the density of carbon vacancies, a hole mobility of 350 cm or more per V·s, and further 450 cm or more per V·s can be realized. 2 / V·s or more. By further reducing the density of carbon vacancies, a hole mobility of 350 cm or more per V·s, and further 450 cm or more per V·s can be realized. 2 / V·s or more, and further 450 cm or more per V·s can be realized. 2 / V·s or more is realized.

[0158] In addition, in the MOSFET 100 of the first embodiment, the concentration of nitrogen at the third position X3, which is 1 nm away from the peak of the interface termination region 40 of the nitrogen concentration distribution toward the silicon carbide layer side, is 1×10 18 cm -3 or less. Since the nitrogen concentration in the silicon carbide layer 10 near the gate insulating layer 28 is low, a high threshold voltage of the MOSFET 100 can be realized.

[0159] The concentration of nitrogen at the third position X3, which is 1 nm away from the peak of the interface termination region 40 of the nitrogen concentration distribution toward the silicon carbide layer side, is 1×10 18 cm -3The following is the case. The nitrogen concentration at the third position X3 is preferably 1×10 17 cm -3 or less, and more preferably 2×10 16 cm -3 or less.

[0160] When manufacturing a MOSFET, the following three processes are conceivable as manufacturing processes in which carbon vacancies that reduce the carrier mobility are generated in the silicon carbide layer.

[0161] The first process is ion implantation of impurities into the silicon carbide layer. Depending on the energy of the ions implanted with impurities, carbon vacancies and interstitial carbon are formed in the silicon carbide layer 10. For example, in the p-well region, carbon vacancies and interstitial carbon with a volume density approximately the same as that of the implanted ions are formed.

[0162] The second process is activation annealing for activating the impurities introduced into the silicon carbide layer by ion implantation. During activation annealing, in order to reduce the free energy of the system of the silicon carbide layer, carbon vacancies and interstitial carbon are generated in the silicon carbide layer and the entropy increases. The amount of carbon vacancies and interstitial carbon generated increases as the temperature of the activation annealing is higher. Since the formation of the silicon carbide layer by epitaxial growth is also a high-temperature treatment, carbon vacancies on the order of 10 13 cm -3 remain in the silicon carbide layer. Also, when performing high-temperature activation annealing, carbon vacancies on the order of 1×10 14 cm -3 are formed.

[0163] The third process is a process of oxidizing the surface of the silicon carbide layer. For example, it is an ashing process, a deposition process of depositing an oxide film, or a thermal oxidation process of forming a thermal oxide film. Also, for example, it is a process of using nitrogen oxide gas for forming an interface termination region. During oxidation, due to the strain generated on the surface of the silicon carbide layer, carbon vacancies and interstitial carbon are formed in the silicon carbide layer. The surface is greatly strained by oxidation, and 1×10 18 cm -3Order carbon vacancies can be created.

[0164] In the manufacturing method of the MOSFET 100 of the first embodiment, after performing aluminum ion implantation to form a p-well region 16 in the silicon carbide layer 10, carbon ion implantation is performed in the same region of the silicon carbide layer 10. The second dose amount of carbon is 10 times or more the first dose amount of aluminum.

[0165] According to the manufacturing method of the MOSFET 100 of the first embodiment, due to carbon ion implantation, a large amount of excess inter-lattice carbon will exist in the p-well region 16. By the heat treatment performed after carbon ion implantation, the carbon vacancies generated by aluminum ion implantation are filled by the excess inter-lattice carbon. Therefore, the amount of carbon vacancies in the p-well region 16 is reduced.

[0166] From the viewpoint of appropriately maintaining the p-type impurity concentration of the p-well region 16, the first dose amount of aluminum is preferably 1×10 14 cm -2 or less. From the viewpoint of reducing the amount of carbon vacancies in the p-well region 16, the second dose amount of carbon is preferably 1×10 15 cm -2 or more, and more preferably 1×10 16 cm -2 or more.

[0167] From the viewpoint of reducing the amount of carbon vacancies in the p-well region 16, the second dose amount of carbon is preferably 100 times or more the first dose amount of aluminum.

[0168] From the viewpoint of reducing the amount of carbon vacancies in the p-well region 16, the second projected range Rp2 of carbon ion implantation is preferably 80% or more and 120% or less of the first projected range Rp1 of aluminum ion implantation, and more preferably 90% or more and 110% or less.

[0169] By bringing the first projected range Rp1 and the second projected range Rp2 closer, it becomes easier for the concentration distribution of carbon after ion implantation to completely cover the concentration distribution of aluminum after ion implantation. By having the concentration distribution of carbon after ion implantation completely cover the concentration distribution of aluminum after ion implantation, the amount of carbon vacancies in the p-well region 16 is reduced.

[0170] From the viewpoint of appropriately maintaining the depth of the p-well region 16, the first projected range Rp1 and the second projected range Rp2 are preferably 0.6 μm or less.

[0171] In the method for manufacturing the MOSFET 100 according to the first embodiment, during the first heat treatment for activating aluminum introduced into the silicon carbide layer 10 by ion implantation, a large amount of excess interstitial carbon will exist in the silicon carbide layer 10. The presence of a large amount of interstitial carbon provides an increase in entropy necessary to reduce the free energy of the system of the silicon carbide layer 10. Therefore, an increase in carbon vacancies in the silicon carbide layer 10 due to the first heat treatment is suppressed.

[0172] In the method for manufacturing the MOSFET 100 according to the first embodiment, during the first heat treatment, the presence of a large amount of excess interstitial carbon in the silicon carbide layer 10 suppresses aluminum atoms from entering the carbon sites of silicon carbide. Therefore, aluminum atoms are promoted to enter the silicon sites of silicon carbide. Thus, the activation rate of aluminum is improved.

[0173] Also, in the method for manufacturing the MOSFET 100 according to the first embodiment, during the first heat treatment, the presence of a large amount of excess interstitial carbon in the silicon carbide layer 10 suppresses an increase in the amount of carbon vacancies in the silicon carbide layer 10 even when the first heat treatment is performed at a high temperature. Therefore, it is possible to perform the first heat treatment at a high temperature. Thus, it is possible to improve the activation rate of aluminum.

[0174] From the perspective of improving the activation rate of aluminum, the temperature of the first heat treatment is preferably 1850 °C or higher, more preferably 1900 °C or higher, and even more preferably 1950 °C or higher. From the perspective of implementing an efficient process, the temperature of the first heat treatment is preferably 2000 °C or lower. From the perspective of the activation rate, even if the temperature exceeds 2000 °C, a significant increase in the activation rate cannot be expected.

[0175] The first heat treatment preferably consists of a first step at 1600 °C or higher and a second step at a temperature lower than the first step. The second step is preferably 1000 °C or lower. The heat treatment time of the second step is longer than the heat treatment time of the first step.

[0176] In the first step, the aluminum and phosphorus ion-implanted into the silicon carbide layer 10 are activated, and the interstitial carbon fills the carbon vacancies. Even when the carbon vacancies are filled, there is still excess interstitial carbon. Then, in the second low-temperature step, the excess interstitial carbon is expelled from the silicon carbide layer 10 and absorbed by the carbon film 54.

[0177] By performing the second step at a low temperature, an increase in carbon vacancies is suppressed. It becomes possible to reduce the interstitial carbon in the silicon carbide layer 10 in the second step. Therefore, an increase in carbon defects in the gate insulating layer 28 can be suppressed in the heat treatment after the first heat treatment.

[0178] FIG. 21 is an explanatory diagram of the operation and effect of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 21 is a diagram showing the relationship between the depth from the surface of the silicon carbide layer and the carbon vacancy density.

[0179] As shown in FIG. 21, when carbon ion implantation is performed in addition to aluminum ion implantation, if the silicon carbide layer is not subjected to an oxidation treatment, the carbon vacancy density is 1E11 cm -3It can be suppressed to be as low as the following. However, when oxidation treatment is performed after ion implantation, for example, the carbon vacancy density increases in the region up to 25 nm from the surface of the silicon carbide layer. This is presumably because carbon vacancies are generated due to the strain generated on the surface of the silicon carbide layer during the oxidation treatment.

[0180] To make the carbon vacancy density 1E11 cm -3 or less, the first heat treatment preferably consists of a first step at 1600 °C or higher and a second step at a lower temperature than the first step. The second step is preferably 1000 °C or lower. For example, the heat treatment time of the second step is longer than that of the first step. In the first step, the interstitial carbon fills the carbon vacancies. Even when the carbon vacancies are filled, there is excess interstitial carbon. Then, in the low-temperature second step, the excess interstitial carbon is expelled from the silicon carbide layer and absorbed by the carbon film covering the surface during annealing.

[0181] By increasing the temperature and prolonging the time of the first heat treatment, the carbon vacancy density in the silicon carbide layer can be made 1E10 cm -3 or less. Also, even in the case with oxidation treatment, similarly, from the position 25 nm from the surface of the silicon carbide layer inward, the carbon vacancy density can be made 1E11 cm -3 or less. From the position 50 nm from the surface inward, the carbon vacancy density can be made 1E10 cm -3 or less.

[0182] As shown in FIG. 21, when carbon ion implantation is not performed in addition to aluminum ion implantation, when oxidation treatment is performed after ion implantation, for example, the carbon vacancy density increases in the region up to 200 nm from the surface of the silicon carbide layer. When carbon ion implantation is not performed, the aluminum ion implantation damage remains, and the carbon vacancy density in the silicon carbide layer before oxidation treatment is as high as about 1E14 cm -3 This is presumably because the diffusion of oxygen through the carbon vacancies is promoted, and strain in the silicon carbide occurs up to a deep region of the silicon carbide layer. For example, when the p-well region is formed by epitaxial growth instead of ion implantation, the carbon vacancy density in the silicon carbide layer is also 1E13 cm-3 The above is the case, and it is considered that the diffusion of oxygen through carbon vacancies is promoted, distortion of silicon carbide occurs up to a deep region of the silicon carbide layer, and the carbon vacancy density increases.

[0183] In the method for manufacturing the MOSFET 100 of the first embodiment, after performing an oxidation treatment on the silicon carbide layer 10, the surface of the silicon carbide layer 10 is etched by a hydrogen etching treatment. The oxidation treatment is, for example, an ashing treatment using oxygen plasma for removing the carbon film 54, a deposition treatment for depositing the field oxide film 55, and a thermal oxidation treatment for forming the sacrificial oxide film 56.

[0184] By removing the region with a high carbon vacancy density by the hydrogen etching treatment, the carbon vacancy density on the surface of the silicon carbide layer 10 is reduced. Therefore, the amount of carbon vacancies in the p-well region 16 directly under the gate insulating layer 28 is reduced.

[0185] From the viewpoint of reducing the carbon vacancy density on the surface of the silicon carbide layer 10, the etching amount of the surface of the silicon carbide layer 10 by the hydrogen etching treatment is at least 10 nm or more. It is preferably 15 nm or more, more preferably 25 nm or more, and still more preferably 50 nm or more. Since there is no change in the carbon vacancy density even when hydrogen etching of 100 nm or more is performed, etching of 100 nm or more is not necessarily required.

[0186] When the carbon vacancy density is 1E17 cm -3 , the hole mobility is observed to be about 130 cm 2 / V·s, and when the carbon vacancy density is 1E16 cm -3 , the hole mobility is observed to be about 160 cm 2 / V·s, and when the carbon vacancy density is 1E15 cm -3 , the hole mobility is observed to be about 180 cm 2 / V·s, and when the carbon vacancy density is 1E14 cm -3 , the hole mobility is observed to be about 200 cm 2 / V·s, and when the carbon vacancy density is 1E13 cm -3 , the hole mobility is observed to be about 250 cm 2 / V·s or less is achieved and the carbon vacancy density is 1E12 cm -3 then, the hole mobility is 300 cm 2 / V·s or less is achieved and the carbon vacancy density is 1E11 cm -3 then, the hole mobility is 350 cm 2 / V·s or less is achieved and the carbon vacancy density is 5E10 cm -3 then, the hole mobility is 400 cm 2 / V·s or less is achieved and the carbon vacancy density is 1E10 cm -3 then, the hole mobility is 450 cm 2 / V·s or less is achieved.

[0187] If the etching amount of the surface of the silicon carbide layer 10 by the hydrogen etching treatment is 15 nm or more, the hole mobility becomes about 200 cm 2 / V·s. The numerical value of the hole mobility of 200 cm 2 / V·s is considered to be a value that is difficult to achieve without performing a hydrogen etching treatment after performing a large amount of carbon ion implantation in addition to aluminum ion implantation and then performing an oxidation treatment. If the etching amount is 25 nm or more, the hole mobility becomes about 350 cm 2 / V·s. If the etching amount is 50 nm or more, the hole mobility reaches 450 cm 2 / V·s.

[0188] In the manufacturing method of the MOSFET 100 according to the first embodiment, the gate insulating layer 28 is formed by a vapor phase growth method at a low temperature and a low oxygen partial pressure. Therefore, the oxidation of the surface of the silicon carbide layer 10 is suppressed as compared with thermal oxidation. Thus, an increase in carbon vacancies in the silicon carbide layer 10 during the formation of the gate insulating layer 28 is suppressed.

[0189] Also, in the manufacturing method of the MOSFET 100 according to the first embodiment, the interface termination region 40 is formed by a second heat treatment in an atmosphere containing ammonia gas (NH3). By forming the interface termination region 40 without interface oxidation in an atmosphere containing ammonia gas, an increase in carbon vacancies in the silicon carbide layer 10 is suppressed.

[0190] Furthermore, since the second heat treatment does not involve oxidation, there is no release of excess carbon from the silicon carbide layer 10. Therefore, it is possible to suppress the diffusion of excess carbon into the gate insulating layer and the formation of carbon defects in the gate insulating layer.

[0191] It is preferable to adjust the conditions of the second heat treatment so that the interface termination region 40 sufficiently doped with nitrogen can be formed. The second heat treatment is performed, for example, in a low oxygen state with an oxygen partial pressure of 1 ppm or less. The second heat treatment is a high temperature treatment at, for example, 1200°C or higher and 1600°C or lower. From the viewpoint of increasing the nitrogen concentration in the interface termination region 40, the second heat treatment is preferably 1300°C or higher, more preferably 1400°C or higher.

[0192] Even if nitrogen is introduced into the gate insulating layer, no composite defects (C-O-N defects) are formed by nitrogen and carbon as long as carbon does not coexist in the gate insulating layer. Therefore, it is possible to perform the second heat treatment for a long time. Thus, it is possible to perform the treatment for a long time until the nitrogen in the interface termination region 40 reaches a sufficient amount, for example, 1×10 22 cm -3 or more. The second heat treatment is, for example, 1300°C for 1 hour and 1400°C for 30 minutes.

[0193] For example, it is also possible to form the interface termination region 40 with interface oxidation by high temperature treatment with nitric oxide (NO) or the like. In this case, carbon vacancies are formed in the silicon carbide layer due to the strain generated on the surface of the silicon carbide layer during interface oxidation. Therefore, even if the carbon vacancies are reduced before forming the interface termination region 40, the carbon vacancies will increase again. That is, when forming the interface termination region 40 with interface oxidation, even if the carbon vacancies are reduced before forming the interface termination region 40, the final reduction of carbon vacancies cannot be achieved.

[0194] In addition, when the interface termination region 40 is formed with interface oxidation by high-temperature treatment with nitric oxide (NO) or the like, carbon remaining after the substrate is oxidized from the silicon carbide layer 10 is released. There is also a problem that the released carbon diffuses into the gate insulating layer and a large amount of carbon defects are generated in the gate insulating layer.

[0195] Note that even if the second heat treatment is performed in a second atmosphere containing nitrogen gas and hydrogen gas, or a third atmosphere containing nitrogen gas and carbon dioxide gas, an increase in carbon vacancies in the silicon carbide layer 10 can be suppressed.

[0196] In the manufacturing method of the MOSFET 100 according to the first embodiment, after the second heat treatment for forming the interface termination region 40, a third heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx).

[0197] By the third heat treatment, nitrogen in the gate insulating layer 28 is removed. By the third heat treatment, a gate insulating layer 28 with reduced nitrogen defects is formed.

[0198] From the viewpoint of suppressing oxidation of the surface of the silicon carbide layer 10 by the third heat treatment, the temperature of the third heat treatment is preferably lower than the temperature of the second heat treatment.

[0199] From the viewpoint of reducing nitrogen defects in the gate insulating layer 28, the temperature of the third heat treatment is preferably 800 °C or higher, more preferably 850 °C or higher, and still more preferably 925 °C or higher.

[0200] From the viewpoint of reducing nitrogen defects in the gate insulating layer 28, the nitrogen oxide gas for the third heat treatment is preferably dinitrogen monoxide gas (N2O) with high oxidizing power.

[0201] Also, from the viewpoint of suppressing oxidation of the silicon carbide layer 10, the temperature of the third heat treatment is preferably 1000 °C or lower, and more preferably 950 °C or lower.

[0202] In the manufacturing method of the MOSFET 100 according to the first embodiment, the interface termination region 40 sufficiently filled with nitrogen is formed by the second heat treatment. The second heat treatment is preferably in a low oxygen state with an oxygen partial pressure of 1 ppm or less, at a high temperature, and for a long time. By the second heat treatment, the oxidation resistance of the silicon carbide layer 10 is improved.

[0203] Therefore, even if the third heat treatment is, for example, at a high temperature of 1050°C, if it is, for example, 5 minutes or less, oxidation of the surface of the silicon carbide layer 10 is suppressed. In order to surely expel nitrogen from the gate insulating layer 28, a long-time treatment at a low temperature with less concern about oxidation of the surface of the silicon carbide layer 10 is preferable. For example, the third heat treatment is preferably a heat treatment with nitrous oxide gas (N2O) at 950°C for 3 hours.

[0204] After the third heat treatment, for example, by measuring that no change in the capacitance of the gate MOS capacitor occurs, it can be confirmed that oxidation of the surface of the silicon carbide layer 10 has not occurred. Or, by directly looking at the TEM image, it can be confirmed that no oxide layer has grown on the surface of the silicon carbide layer 10.

[0205] It can be said that the point of improving the oxidation resistance of the silicon carbide layer 10 by the second heat treatment is a prerequisite for the third heat treatment. If the second treatment is not performed appropriately, the surface of the silicon carbide layer 10 is oxidized by the third treatment. Oxidation is not preferable because carbon vacancies are formed in the silicon carbide layer 10.

[0206] In the manufacturing method of the MOSFET 100 according to the first embodiment, by suppressing oxidation of the surface of the silicon carbide layer after forming the gate insulating layer 28, the amount of carbon in the gate insulating layer 28 is reduced, and the amount of carbon defects in the gate insulating layer 28 is also reduced.

[0207] Also, in the method for manufacturing the MOSFET 100 of the first embodiment, an increase in carbon vacancies in the silicon carbide layer 10 is suppressed. For example, when forming the interface termination region 40, nitrogen atoms are suppressed from entering the carbon vacancies and becoming donors. Therefore, a decrease in the threshold voltage of the MOSFET 100 is suppressed.

[0208] As described above, according to the first embodiment, by reducing the amount of carbon vacancies in the silicon carbide layer, a semiconductor device and a method for manufacturing a semiconductor device capable of suppressing a decrease in carrier mobility are realized.

[0209] (Second Embodiment) The method for manufacturing a semiconductor device according to the second embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment in that a second heat treatment is performed in an atmosphere containing nitrogen before forming the silicon oxide film. Hereinafter, descriptions of parts overlapping with the first embodiment will be omitted.

[0210] Hereinafter, a case where the second heat treatment is performed in a first atmosphere containing ammonia gas will be described as an example.

[0211] FIG. 22 is a process flow diagram of the method for manufacturing a semiconductor device according to the second embodiment. The MOSFET 100 shown in FIG. 1 is formed by the method for manufacturing a semiconductor device according to the second embodiment.

[0212] As shown in FIG. 22, the method for manufacturing a semiconductor device according to the second embodiment includes preparing a silicon carbide layer (step S200), implanting aluminum ions (step S201), implanting carbon ions (step S202), implanting phosphorus ions (step S203), implanting aluminum ions (step S204), forming a carbon film (step S205), performing a first heat treatment (step S206), removing the carbon film (step S207), forming a field oxide film (step S208), forming a sacrificial oxide film (step S209), performing a hydrogen etching treatment (step S210), performing a second heat treatment (step S211), forming a silicon oxide film (step S212), performing a third heat treatment (step S213), performing a fourth heat treatment (step S214), forming a gate electrode (step S215), forming an interlayer insulating film (step S216), and forming source and drain electrodes (step S217).

[0213] In step S200, a silicon carbide layer 10 is prepared. The silicon carbide layer 10 includes an n + -type drain region 12 and an n - -type drift region 14.

[0214] In step S201, a first mask material is formed. Then, using the first mask material as an ion implantation mask, aluminum is ion-implanted into the drift region 14. By the ion implantation, a p-well region 16 is formed.

[0215] The ion implantation for forming the p-well region 16 is an example of the first ion implantation. The ion implantation of aluminum is performed with a first projected range and a first dose amount.

[0216] In step S202, using the first mask material as an ion implantation mask, carbon is ion-implanted into the p-well region 16. The ion implantation of carbon into the p-well region 16 is an example of the second ion implantation. The ion implantation of carbon is performed with a second projected range and a second dose amount. Then, the first mask material is removed.

[0217] In step S203, a second mask material is formed. Then, using the second mask material as an ion implantation mask, phosphorus, which is an n-type impurity, is ion-implanted into the drift region 14 to form the source region 18. Thereafter, the second mask material is removed.

[0218] In step S204, a third mask material is formed. Using the third mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift region 14 to form the p-well contact region 20. Thereafter, the third mask material is removed.

[0219] In step S205, a carbon film is formed on the silicon carbide layer 10.

[0220] In step S206, a first heat treatment is performed. The first heat treatment is performed at 1600 °C or higher. The first heat treatment is performed in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The first heat treatment is performed, for example, in an argon gas atmosphere.

[0221] By the first heat treatment, the aluminum and phosphorus ion-implanted into the silicon carbide layer 10 are activated. The first heat treatment is an activation anneal for aluminum and phosphorus.

[0222] In step S207, the carbon film is removed. The removal of the carbon film is performed by an ashing process using oxygen plasma.

[0223] In step S208, a field oxide film is formed on the silicon carbide layer 10. The field oxide film contains oxygen. The field oxide film is, for example, a silicon oxide film. The field oxide film is deposited, for example, by a vapor phase growth method.

[0224] Next, the field oxide film is removed.

[0225] In step S209, a sacrificial oxide film is formed on the silicon carbide layer 10. The sacrificial oxide film is, for example, a silicon oxide film. The sacrificial oxide film is formed by thermal oxidation of the surface of the silicon carbide layer.

[0226] Next, the sacrificial oxide film is removed.

[0227] In step S210, a hydrogen etching process is performed to etch the surface of the silicon carbide layer 10 in an atmosphere containing hydrogen gas. By the hydrogen etching process, the surface of the silicon carbide layer 10 is etched, for example, by 10 nm or more and 100 nm or less. The etching amount is preferably 15 nm or more, more preferably 25 nm or more, and still more preferably 50 nm or more. In the method for manufacturing a semiconductor device according to the second embodiment, even if the etching exceeds 100 nm, the effect of the hydrogen etching process does not change significantly, so etching exceeding 100 nm is not necessarily required.

[0228] In step S211, a second heat treatment is performed. The second heat treatment is performed in an atmosphere containing ammonia gas (NH3).

[0229] By the second heat treatment, an interface termination region 40 is formed on the surface of the silicon carbide layer 10.

[0230] In step S212, a silicon oxide film is formed on the silicon carbide layer 10. The silicon oxide film will ultimately become the gate insulating layer 28. The silicon oxide film is formed, for example, by a vapor phase growth method at a low temperature and a low oxygen partial pressure.

[0231] The silicon oxide film is preferably formed at a temperature of 600 °C or lower, more preferably at a temperature of 500 °C or lower, and still more preferably at a temperature of 450 °C or lower. By forming the silicon oxide film at a low temperature, oxidation of the surface of the silicon carbide layer is suppressed.

[0232] The silicon oxide film formed in step S212 is preferably a silicon-rich silicon oxide film throughout the film by reducing the oxygen partial pressure during growth. SiO 2-δ As, 0.01 ≦ δ ≦ 0.1 is preferable. That is, it is preferable to adjust so that the oxygen deficiency is 0.5% or more and 5% or less. This is because if there is excess oxygen in the silicon oxide film, the silicon carbide layer may be oxidized during the subsequent high-temperature treatment, so it is preferable to have a state without excess oxygen. By performing the third heat treatment, oxygen is supplied to the oxygen deficiency in the silicon oxide film, and finally, a good silicon oxide film without oxygen deficiency is obtained.

[0233] In step S213, a third heat treatment is performed. The third heat treatment is performed in an atmosphere containing an inert gas. The second heat treatment is performed in a non-oxidizing atmosphere in which the surface of the silicon carbide layer 10 is not oxidized.

[0234] For example, argon gas (Ar) or nitrogen gas (N2) is supplied to the reactor containing the silicon carbide layer 10 and heat treatment is performed.

[0235] The temperature of the third heat treatment is, for example, 1000 ° C or higher and 1400 ° C or lower.

[0236] The third heat treatment also functions as a densification anneal of the silicon oxide film. By the third heat treatment, the silicon oxide film becomes a high-density film.

[0237] In step S214, a fourth heat treatment is performed. The fourth heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx). By the fourth heat treatment, nitrogen in the silicon oxide film is removed.

[0238] In step S215, a gate electrode 30 is formed on the gate insulating layer 28.

[0239] In step S216, an interlayer insulating film 32 is formed on the gate electrode 30.

[0240] In step S215, a source electrode 34 and a drain electrode 36 are formed.

[0241] By the above manufacturing method, the MOSFET 100 shown in FIG. 1 is formed.

[0242] As described above, according to the second embodiment, similar to the first embodiment, a manufacturing method of a semiconductor device capable of suppressing a decrease in carrier mobility by reducing the amount of carbon vacancies in the silicon carbide layer is realized.

[0243] (Third Embodiment) The manufacturing method of the semiconductor device according to the third embodiment performs a first ion implantation of injecting aluminum (Al) into the silicon carbide layer, performs a first heat treatment at 1600° C. or higher, performs an oxidation treatment of oxidizing the silicon carbide layer, performs an etching treatment of etching the silicon carbide layer by 25 nm or more in an atmosphere containing hydrogen gas, forms a silicon oxide film on the silicon carbide layer, and forms a gate electrode on the silicon oxide film. The manufacturing method of the semiconductor device according to the third embodiment is different from the manufacturing method of the semiconductor device according to the first embodiment in that it does not include a second ion implantation of injecting carbon (C) into the silicon carbide layer. Hereinafter, for the content overlapping with the first embodiment, some descriptions may be omitted.

[0244] As shown in FIG. 21 of the first embodiment, when carbon ion implantation is not performed in addition to aluminum ion implantation, when an oxidation treatment is performed after ion implantation, for example, the carbon vacancy density becomes high from the surface of the silicon carbide layer to a region of 200 nm or more. When carbon ion implantation is not performed, since the carbon vacancy density of the silicon carbide layer before the oxidation treatment is high, it is considered that the diffusion of oxygen through the carbon vacancies is promoted, and strain of the silicon carbide occurs even in a deep region of the silicon carbide layer.

[0245] In the manufacturing method of the semiconductor device according to the third embodiment, after the silicon carbide layer 10 is subjected to an oxidation treatment, the surface of the silicon carbide layer 10 is etched by a hydrogen etching treatment. The etching amount of the surface of the silicon carbide layer 10 by the hydrogen etching treatment is 25 nm or more. By etching the surface of the silicon carbide layer 10 by 25 nm or more, the carbon vacancy density is 1016 cm -3 Remove the above region. By removing the region with a high carbon vacancy density, the carbon vacancy density on the surface of the silicon carbide layer 10 is reduced. Therefore, the amount of carbon vacancies in the p-well region 16 directly under the gate insulating layer 28 is reduced. As a result, the hole mobility becomes, for example, 160 cm 2 / V·s or more.

[0246] From the viewpoint of reducing the carbon vacancy density on the surface of the silicon carbide layer 10, the etching amount of the surface of the silicon carbide layer 10 by the hydrogen etching treatment is preferably 50 nm or more, more preferably 75 nm or more, still more preferably 100 nm or more. And most preferably 200 nm or more. When the etching amount is 50 nm or more, the hole mobility becomes, for example, 160 cm 2 / V·s or more. When the etching amount is 200 nm or more, the hole mobility becomes, for example, 200 cm 2 / V·s or more. Since there are a large number of carbon vacancies deep inside, they are removed by etching from the surface to the deep inside.

[0247] As described above, according to the third embodiment, a semiconductor device and a method for manufacturing the semiconductor device that can suppress a decrease in carrier mobility by reducing the amount of carbon vacancies in the silicon carbide layer are realized.

[0248] (Fourth Embodiment) The semiconductor device of the fourth embodiment is different from the first embodiment in that it is a trench gate type MOSFET having a gate electrode in a trench. Hereinafter, the description of the content overlapping with the first embodiment will be partially omitted.

[0249] FIG. 23 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment. The semiconductor device of the fourth embodiment is a MOSFET 200. The MOSFET 200 is a trench gate type MOSFET having a gate electrode in a trench. Also, the MOSFET 200 is an n-channel type MOSFET using electrons as carriers.

[0250] The MOSFET 200 includes a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, an interface termination region 40 (region), and a trench 50.

[0251] The silicon carbide layer 10 includes a drain region 12, a drift region 14, a p-well region 16, a source region 18, and a p-well contact region 20.

[0252] The trench 50 penetrates through the source region 18 and the p-well region 16 and reaches the drift region 14. The bottom surface of the trench 50 is located in the drift region 14.

[0253] The gate insulating layer 28 and the gate electrode 30 are provided in the trench 50. The side surface of the trench 50 is, for example, a surface having an off-angle of 0 degrees or more and 8 degrees or less with respect to the m-plane.

[0254] The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 16 is, for example, 1×10 16 cm -3 or more and 1×10 20 cm -3 or less. Similar to the manufacturing method of the first embodiment, as shown in FIG. 9 of the first embodiment, carbon is introduced by ion implantation so as to cover the distribution of aluminum.

[0255] The depth of the p-well region 16 is, for example, 0.4 μm or more and 0.8 μm or less. The p-well region 16 functions as a channel region of the MOSFET 200.

[0256] A channel portion 16a is located between the gate insulating layer 28 and a first position (X1 in FIG. 23) that is 100 nm away from the gate insulating layer 28 toward the side of the silicon carbide layer 10. The channel portion 16a is located in the p-well region 16.

[0257] In the channel portion 16a, the ratio of the intensity of infrared absorption at a wave number of 838 cm -1 to the intensity of infrared absorption at a wave number of 970 cm -1 measured by the attenuated total reflection method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) is 1.0 or less.

[0258] In the channel portion 16a, the Z 1 / 2 level density measured by DLTS is 1 × 10 11 cm -3 or less. 5 × 10 10 cm -3 or less is preferable, and 1 × 10 10 cm -3 or less is more preferable.

[0259] The hole mobility of electrons in the channel portion 16a is, for example, 200 cm 2 / V·s or more. 350 cm 2 / V·s or more is preferable, and 450 cm 2 / V·s or more is more preferable.

[0260] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the p-well region 16 and the gate insulating layer 28. The interface termination region 40 contains nitrogen (N) as a termination element that terminates the dangling bonds of the silicon carbide layer 10. The interface termination region 40 is an example of a region.

[0261] The nitrogen concentration in the interface termination region 40 is 1 × 10 21 cm -3 or more.

[0262] As shown in FIG. 3, the nitrogen concentration distribution has a peak in the interface termination region 40. The peak nitrogen concentration is, for example, 1 × 10 22 cm -3 or more. The full width at half maximum of the nitrogen concentration distribution peak is, for example, 1 nm or less. Nitrogen is segregated at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0263] The nitrogen concentration at the peak of the nitrogen concentration distribution is, for example, 1×10 22 cm -3 or more.

[0264] The nitrogen concentration at the second position X2, which is 1 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28, is 1×10 18 cm -3 or less. Also, the nitrogen concentration at the third position X3, which is 1 nm away from the peak of the nitrogen concentration distribution toward the silicon carbide layer 10, is 1×10 18 cm -3 or less. The nitrogen concentration at the third position X3 is preferably 1×10 17 cm -3 or less, and more preferably 2×10 16 cm -3 or less.

[0265] The amount of nitrogen atoms bonded to four silicon atoms at the fourth position (X4 in FIG. 23), which is 5 nm away from the gate insulating layer 28 toward the silicon carbide layer 10, is, for example, 80% or more and 120% or less of the amount of nitrogen atoms bonded to four silicon atoms at the fifth position (X5 in FIG. 23), which is 5 μm away from the gate insulating layer 28 toward the silicon carbide layer 10. In other words, the amount of four - coordinated nitrogen atoms at the fourth position X4 is 80% or more and 120% or less of the amount of four - coordinated nitrogen atoms at the fifth position X5.

[0266] The fourth position X4 is located within the p - well region 16. The fifth position X5 is located within the drift region 14.

[0267] Note that the MOSFET 200 can be manufactured, for example, by forming the trench 50 after the first heat treatment and before the etching process in the manufacturing method of the first embodiment.

[0268] As described above, according to the fourth embodiment, similar to the first, second, and third embodiments, a semiconductor device capable of suppressing a decrease in carrier mobility is realized by reducing the amount of carbon vacancies in the silicon carbide layer. Further, since it is a trench gate type, the channel density per unit area of the chip increases, and the on-resistance of the MOSFET decreases.

[0269] (Fifth Embodiment) The inverter circuit and the drive device according to the fifth embodiment are an inverter circuit and a drive device including the semiconductor device according to the first embodiment.

[0270] FIG. 24 is a schematic diagram of the drive device according to the fifth embodiment. The drive device 700 includes a motor 140 and an inverter circuit 150.

[0271] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c using the MOSFET 100 according to the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

[0272] According to the fifth embodiment, by including the MOSFET 100 with improved characteristics, the characteristics of the inverter circuit 150 and the drive device 700 are improved.

[0273] (Sixth Embodiment) The vehicle according to the sixth embodiment is a vehicle including the semiconductor device according to the first embodiment.

[0274] FIG. 25 is a schematic diagram of the vehicle according to the sixth embodiment. The vehicle 800 according to the sixth embodiment is a railway vehicle. The vehicle 800 includes a motor 140 and an inverter circuit 150.

[0275] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three output terminals U, V, and W for alternating voltage is realized. The motor 140 is driven by the alternating voltage output from the inverter circuit 150. The wheels 90 of the vehicle 800 are rotated by the motor 140.

[0276] According to the sixth embodiment, by providing the MOSFET 100 with improved characteristics, the characteristics of the vehicle 800 are improved.

[0277] (Seventh Embodiment) The vehicle of the seventh embodiment is a vehicle including the semiconductor device of the first embodiment.

[0278] FIG. 26 is a schematic diagram of the vehicle of the seventh embodiment. The vehicle 900 of the seventh embodiment is an automobile. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0279] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three output terminals U, V, and W for alternating voltage is realized.

[0280] The motor 140 is driven by the alternating voltage output from the inverter circuit 150. The wheels 90 of the vehicle 900 are rotated by the motor 140.

[0281] According to the seventh embodiment, by providing the MOSFET 100 with improved characteristics, the characteristics of the vehicle 900 are improved.

[0282] (Eighth Embodiment) The elevator of the eighth embodiment is an elevator including the semiconductor device of the first embodiment.

[0283] FIG. 27 is a schematic diagram of an elevator according to the eighth embodiment. The elevator 1000 according to the eighth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0284] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0285] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The hoist 616 is rotated by the motor 140, and the car 610 moves up and down.

[0286] According to the eighth embodiment, by providing the MOSFET 100 with improved characteristics, the characteristics of the elevator 1000 are improved.

[0287] As described above, in the first to fourth embodiments, the case of 4H-SiC as the crystal structure of silicon carbide has been described as an example. However, the present invention can also be applied to silicon carbide having other crystal structures such as 6H-SiC and 3C-SiC.

[0288] Also, in the first to fourth embodiments, the case where the gate insulating layer 28 is provided on the silicon surface or the m-plane of the silicon carbide layer has been described as an example. However, the present invention can also be applied to the case where the gate insulating layer 28 is provided on other surfaces of silicon carbide, for example, the carbon surface, the a-plane, the (0-33-8) plane, and the like.

[0289] The present invention can also be applied to an n-channel IGBT (Insulated Gate Bipolar Transistor).

[0290] In the fifth to eighth embodiments, the case where the semiconductor device of the present invention is applied to a vehicle or an elevator has been described as an example. However, the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0291] In the fifth to eighth embodiments, the case where the semiconductor device of the first embodiment is applied has been described as an example. However, for example, it is also possible to apply the semiconductor device of the second, third, or fourth embodiment.

[0292] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or changed with those of another embodiment. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0293] 10 Silicon carbide layer 14 Drift region (first silicon carbide region) 16 p-well region (second silicon carbide region) 16a Channel portion (portion) 28 Gate insulating layer (silicon oxide layer) 30 Gate electrode 40 Interface termination region (region) 54 Carbon film 57 Silicon oxide film 100 MOSFET (semiconductor device) 150 Inverter circuit 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 400 MOSFET (semiconductor device) 700 Driving device 800 Vehicle 900 Vehicle 1000 Elevator Rp1 First Projected Range Rp2 Second Projected Range X1 First Position X2 Second Position X3 Third Position X4 Fourth Position X5 Fifth Position

Claims

1. Perform a first ion implantation in which aluminum (Al) is implanted into the silicon carbide layer at a first projected range and a first dose amount, perform a second ion implantation in which carbon (C) is implanted into the silicon carbide layer at a second projected range and a second dose amount that is 10 times or more the first dose amount, perform a first heat treatment at 1600° C. or higher, perform an oxidation treatment for oxidizing the silicon carbide layer, perform an etching treatment for etching the silicon carbide layer in an atmosphere containing hydrogen gas, form a silicon oxide film on the silicon carbide layer, A method for manufacturing a semiconductor device in which a gate electrode is formed on the silicon oxide film.

2. The method for manufacturing a semiconductor device according to claim 1, wherein during the etching treatment, the silicon carbide layer is etched by 10 nm or more.

3. The method for manufacturing a semiconductor device according to claim 1, wherein during the etching treatment, the silicon carbide layer is etched by 15 nm or more.

4. The method for manufacturing a semiconductor device according to claim 1, wherein during the etching treatment, the silicon carbide layer is etched by 25 nm or more.

5. After the first ion implantation and before the first heat treatment, form a carbon film on the silicon carbide layer, The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the oxidation treatment is an ashing treatment for removing the carbon film in oxygen plasma.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the oxidation treatment is a thermal oxidation treatment.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the oxidation treatment is a deposition treatment for depositing an insulating film containing oxygen on the silicon carbide layer.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the temperature of the etching treatment is 1300° C. or higher and 1500° C. or lower.

9. The first dose amount is 1×10 １４ cm －２ The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the above is 1×10

10. The second dose amount is 1×10 １５ cm －２ or more. The method for manufacturing a semiconductor device according to any one of claims 1 to 9.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the first projected range and the second projected range are 0.6 μm or less.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein the second projected range is 80% or more and 120% or less of the first projected range.

13. The manufacturing method of a semiconductor device according to any one of claims 1 to 12, wherein the first ion implantation and the second ion implantation are performed on the same region of the silicon carbide layer.

14. The manufacturing method of a semiconductor device according to any one of claims 1 to 13, wherein after forming the silicon oxide film and before forming the gate electrode, a second heat treatment is performed in an atmosphere containing nitrogen (N).

15. Perform a first ion implantation of implanting aluminum (Al) into the silicon carbide layer, Perform a first heat treatment at 1600 °C or higher, Perform an oxidation treatment of oxidizing the silicon carbide layer, Perform an etching treatment of etching the silicon carbide layer by 25 nm or more in an atmosphere containing hydrogen gas, Form a silicon oxide film on the silicon carbide layer, The manufacturing method of a semiconductor device of forming a gate electrode on the silicon oxide film.

16. The manufacturing method of a semiconductor device according to claim 15, wherein during the etching treatment, the silicon carbide layer is etched by 50 nm or more.

17. A silicon carbide layer, A gate electrode, A silicon oxide layer between the silicon carbide layer and the gate electrode, Located between the silicon carbide layer and the silicon oxide layer, and having a region with a nitrogen concentration of 1×10 ２１ cm －３ or more, and comprising The concentration distribution of nitrogen in the silicon carbide layer, the silicon oxide layer, and the region has a peak in the region, In the portion between the silicon oxide layer and the first position 100 nm away from the silicon oxide layer toward the silicon carbide layer side, the ratio of the intensity of infrared absorption at a wave number of 838 cm －１ to the intensity of infrared absorption at a wave number of 970 cm －１ measured by the total reflection measurement method (ATR method) of Fourier transform infrared spectroscopy (FTIR method) is 1.0 or less, The concentration of nitrogen at a second position 1 nm away from the peak toward the silicon oxide layer is 1 × 10 １８ cm －３ or less, and the concentration of carbon at the second position is 1 × 10 １８ cm －３ or less, A semiconductor device in which the nitrogen concentration at a third position 1 nm away from the peak toward the silicon carbide layer is 1×10 １８ cm －３ or less.

18. The nitrogen concentration of the peak is 1×10 ２２ cm －３ or more, and the semiconductor device according to claim 17.

19. The silicon carbide layer includes an n-type first silicon carbide region and a p-type second silicon carbide region located between the first silicon carbide region and the silicon oxide layer. The semiconductor device according to claim 17 or claim 18, wherein the portion is located in the second silicon carbide region.

20. An inverter circuit including the semiconductor device according to any one of claims 17 to 19.

21. A driving device including the semiconductor device according to any one of claims 17 to 19.

22. A vehicle including the semiconductor device according to any one of claims 17 to 19.

23. An elevator including the semiconductor device according to any one of claims 17 to 19.

Images