Manufacturing method of packaging substrate and packaging substrate using the same

Abstract

To provide a packaging substrate in which a gap between a sidewall of a cavity part and a cavity element is formed in a small volume, a semiconductor package, a method of manufacturing a packaging substrate, and a method of manufacturing a semiconductor package.SOLUTION: A packaging substrate 200 according to the present specification includes: a glass substrate 100 having first and second sides facing each other; a cavity part formed in the glass substrate; and a cavity element 210 disposed in the cavity part. The cavity part includes a cavity space in which at least a portion of the cavity element is inserted, a sidewall surrounding the cavity space, and a gap 280 disposed between one side of the cavity element and the sidewall. In the gap, a filling part 220 filled with a filling material is formed. The gap may have a length of 50 μm or less.SELECTED DRAWING: Figure 4A

Description

Technical Field

[0001] Embodiments relate to a packaging substrate, a semiconductor package, a method of manufacturing a packaging substrate, a method of manufacturing a semiconductor package, and the like.

Background Art

[0002] In fabricating electronic components, forming a circuit on a semiconductor wafer is referred to as the front-end (FE) process, and assembling the wafer into a state where it can be used as an actual product is referred to as the back-end (BE) process. This back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron nanometer line widths, over ten million cells, high-speed operation, and a large amount of heat dissipation. However, relatively speaking, there is no technology that perfectly supports packaging this. Therefore, the electrical performance of a semiconductor can sometimes be determined by packaging technology and the electrical connections it provides, rather than the performance of the semiconductor technology itself.

[0004] As materials for packaging substrates, ceramics or resins are applied. In the case of a ceramic substrate such as a silicon substrate, it is not easy to mount high-performance high-frequency semiconductor elements because of its high resistance value or high dielectric constant. In the case of a resin substrate, relatively high-performance high-frequency semiconductor elements can be mounted. However, there is a limit to reducing the wiring pitch.

[0005] Recently, silicon and glass can be applied to high-end packaging substrates. By forming through-holes in a silicon or glass substrate and applying a conductive material to these through-holes, the wiring length between the element and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

[0006] In addition, a semiconductor package may generate heat during operation, and may further include a heat dissipation means for dissipating such heat.

[0007] As related prior arts, there are Korean Patent Publication No. 10-2021-0022980, Korean Patent Publication No. 10-2022-0050121, etc.

Summary of the Invention

Problems to be Solved by the Invention

[0008] An object of the embodiment is to provide a method for manufacturing a packaging substrate in which a glass substrate is used, and a packaging substrate using the same, which form a gap between a side wall of a cavity portion and a cavity element with a small volume.

[0009] Another object of the embodiment is to provide a method for manufacturing a packaging substrate and a packaging substrate using the same, which are advantageous for forming a layer build-up by reducing surface fluctuation, such as reducing loss of a filling material for filling a gap by forming the side wall of the cavity portion to be inclined to form a tapered gap.

Means for Solving the Problems

[0010] To achieve the above object, a packaging substrate according to an embodiment includes a glass substrate having a first surface and a second surface facing each other, a cavity portion formed in the glass substrate, and a cavity element disposed in the cavity portion.

[0011] The cavity portion includes a cavity space into which at least a part of the cavity element is inserted, a side wall surrounding the cavity space, and a gap is disposed between one side surface of the cavity element and the side wall.

[0012] The gap may be filled with one or more filling materials.

[0013] The length of the gap can be 50 μm or less.

[0014] The side wall is inclined, and the angle between the side wall and the second surface can be 65° or more.

[0015] When the side surface is inclined, the length of the gap is the maximum value among the distances between the side wall and one side surface of the cavity element, and the length of the gap can be 50 μm or less.

[0016] The cavity portion may be a full cavity type in which the cavity space penetrates the glass substrate; or a half cavity type in which the cavity space is in a form in which the first surface or the second surface of the glass substrate is recessed.

[0017] The cavity portion has an opening surface located at an opening of the cavity space; and a bottom surface of a recess portion of the cavity space or a bottom surface facing the opening surface, and the area of the opening surface can be larger than the area of the bottom surface.

[0018] The glass substrate can include a first cavity portion and a second cavity portion.

[0019] A first cavity element can be arranged in the first cavity portion, and a second cavity element can be arranged in the second cavity portion.

[0020] In a cross-sectional view, the sum of the gaps arranged on both sides of the first cavity element and the gaps arranged on both sides of the second cavity element can be 200 μm or less.

[0021] A first cavity element and a second cavity element can be arranged in the cavity portion.

[0022] In a cross-sectional view, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element can be 150 μm or less.

[0023] On the other hand, in order to achieve the above object, a method for manufacturing a packaging substrate according to an embodiment includes the steps of preparing a glass substrate provided with a cavity portion and a cavity element, and disposing and filling the cavity element in the cavity portion.

[0024] The glass substrate has a first surface and a second surface facing each other.

[0025] The cavity portion includes a cavity space into which at least a part of the cavity element is inserted, a side wall surrounding the cavity space, and a gap disposed between one side surface of the cavity element and the side wall. The filling can form a filling portion by filling the gap with a filling material.

[0026] In the cavity portion, the cavity space is a full cavity penetrating the glass substrate, and the placement is performed with a support layer attached under the second surface. The support layer can be removed after the filling step.

[0027] The side wall is inclined, and the required amount of the filling material can be reduced by 30% or more compared to when the side wall is perpendicular to the second surface.

Advantages of the Invention

[0028] The method for manufacturing a packaging substrate, the packaging substrate, etc. according to the embodiment can reduce the volume for filling the gap between the side wall of the cavity portion and the cavity element. Through this, the utilization area of the glass substrate can be increased, the loss of the filling substance can be reduced, and the surface fluctuation can be reduced, which can advantageously produce the effect of forming an additional build-up layer.

[0029] Also, by forming the side wall of the cavity portion to be inclined or the like, the volume for filling the gap between the side wall of the cavity portion and the cavity element can be reduced. Through this, the utilization area of the glass substrate can be increased, the loss of the filling material can be reduced, and the surface fluctuation can be reduced, thereby producing an effect that is advantageous for the formation of an additional build-up layer.

Brief Description of the Drawings

[0030]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4A

Figure 4B

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Figure 7A

Figure 7B

Best Mode for Carrying Out the Invention

[0031] To assist in a comprehensive understanding of the methods, apparatuses, and / or systems described in this specification, the following detailed description is provided. However, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described in this specification will become apparent after understanding the content presented in this application. For example, the order of operations described in this specification is merely illustrative and is not limited to the operations described herein. Except for steps that must proceed in a certain order, the order of operations may be changed according to the understanding of the content presented in this application. Also, the description of well-known features may be omitted to enhance clarity and conciseness after understanding the disclosure of this application. However, the omission of such features and their descriptions is not intended to be recognized as common knowledge.

[0032] The features described in this specification can be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described in this specification are provided to illustrate some of the ways of implementing many possible methods, apparatuses, and / or systems described in this specification that will become apparent after understanding the disclosure of this application.

[0033] In this specification, terms such as "first," "second," "third," etc. can be used to describe various members, components, regions, layers, or cross-sections, but these members, components, regions, layers, or cross-sections are not limited to these words. Instead, such terms are used for the purpose of distinguishing one member, component, region, layer, or section from another member, component, region, layer, or section. Therefore, the first member, component, region, layer, or section referred to in the examples described in this specification can also be called the second member, component, region, layer, or section without departing from the teachings of the examples.

[0034] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on," "connected to," or "coupled to" another element, it can be described as being directly "on," "connected to," or "coupled to" the other element, or one or more other elements can intervene therebetween. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to," no other element can intervene therebetween. Similarly, expressions such as, for example, "between" and "directly between," and "contact" and "directly contact" can be interpreted as described above.

[0035] The terms used in this specification are for illustrative purposes only and are not used to limit the disclosure. The singular forms used in this specification are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "and / or" used in this specification includes any one or more combinations of the related listed items. The terms "comprising," "consisting of," and "including" used in this specification specify the presence of the stated features, numbers, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof. In this specification, the use of the term "can" in connection with an illustration or example (e.g., with respect to what an illustration or example includes or can embody) means that there is at least one illustration or example in which such a feature is included or embodied, but not all examples are limited thereto.

[0036] In this application, "B is located on A" means that B is in direct contact with A, or is disposed on A with another layer or structure intervening therebetween, and thus, B should not be interpreted as being in direct contact with A.

[0037] Unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the prior art and this invention, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0038] In the above one or more examples, the description of "A and / or B" means "A, B, or A and B".

[0039] In the above one or more examples, terms such as "first", "second", "A", or "B" are used to distinguish the same terms from each other.

[0040] In the above one or more examples, the singular form is contextually interpreted to include not only the singular form but also the plural form unless otherwise specified.

[0041] Packaging substrate FIG. 1 is a conceptual diagram for explaining an example of a glass substrate of a packaging substrate according to an embodiment, FIG. 2A is a conceptual diagram for explaining an A-A' cross-section of the glass substrate according to an embodiment, and FIG. 2B is a conceptual diagram for explaining an A-A' cross-section of the glass substrate according to another embodiment. Hereinafter, with reference to FIGS. 1 to 2B, the glass substrate included in the packaging substrate will be described in detail.

[0042] The glass substrate 100 according to one or more examples includes an element region 110 and a substrate region 120 that are divided from each other. The element region 110 is a region where a cavity portion is disposed, and the substrate region 120 is a region where no cavity portion is disposed. The element region 110 and the substrate region 120 may be disposed adjacent to each other. The glass substrate 100 may include one element region 110 or may include two or more element regions 110. The element region may also be called a cavity structure.

[0043] The glass substrate 100 has a first surface and a second surface facing each other, and these two surfaces are substantially parallel to each other, so the glass substrate 100 has a constant thickness throughout.

[0044] As a packaging substrate for semiconductor devices, conventionally, a form in which a silicon substrate and an organic substrate are laminated has been applied. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a possibility of generating parasitic elements when applied to a high-speed circuit, and there is a drawback that power loss is relatively large. In the case of an organic substrate, in order to form a more complex distribution pattern, it is necessary to increase the area, but this does not conform to the manufacturing process of miniaturized electronic devices. In order to form a complex distribution pattern within a defined size, it is necessary to substantially miniaturize the pattern, but due to the characteristics of materials such as polymers applied to organic substrates, there is a substantial limit to pattern miniaturization.

[0045] In an embodiment, as a method for solving such problems, the glass substrate 100 is applied as a support of the packaging substrate. Further, by applying a core via formed through the glass substrate 100 together with the glass substrate 100, the length of the electrical flow is further shortened, and a packaging substrate having further miniaturization, faster reaction, and less loss characteristics is provided.

[0046] It is preferable to apply a glass substrate applied to a semiconductor to the glass substrate 100. For example, a borosilicate glass substrate, a non-alkali glass substrate, etc. may be applied, but it is not limited thereto.

[0047] The core via penetrates the glass substrate 100. The core via can be formed by a method of removing a predetermined area of the glass substrate 100, and specifically, it can be formed by etching plate-shaped glass by a physical and / or chemical method.

[0048] Specifically, for the formation of the core vias, after forming defects (scratches) on the surface of the glass substrate by a method such as a laser, a method of chemically etching, laser etching, etc. may be applied, but it is not limited thereto.

[0049] The core vias may be located in a number ranging from 100 to 3,000, from 100 to 2,500, or from 225 to 1,024 based on the unit area (1 cm × 1 cm) of the glass substrate 100. When such pitch conditions are satisfied, the formation of an electrically conductive layer, etc. and the performance of the packaging substrate can be improved.

[0050] The cavity portion 110 may include a cavity structure.

[0051] The cavity structure refers to a structure including a recessed portion in a part of the glass substrate 100 that allows elements to be arranged substantially inside the glass substrate 100. The space formed by the recessed portion is referred to as a cavity space.

[0052] The cavity portion 110 may include a cavity space into which at least a part of a cavity element is inserted; side walls surrounding the cavity space; and a contact surface that is selectively a bottom surface.

[0053] Referring to FIGS. 2A and 2B, a cavity portion 110 may be formed in the glass substrate 100 having a first surface and a second surface facing each other.

[0054] For example, referring to FIG. 2A, the cavity portion 110 may have a space in which elements are arranged, penetrating the first surface and the second surface of the glass substrate 100. The cavity space of the cavity portion 110 shown in FIG. 2A may be a full cavity type penetrating the glass substrate 100.

[0055] For example, referring to FIG. 2B, the cavity portion 110 can be formed in the form of a recessed surface with only one of the first surface and the second surface being open. By forming the cavity portion 110 in the form of a recessed surface with only one of the first surface and the second surface being open, it can have a space where the element is disposed. The cavity space of the cavity portion 110 shown in FIG. 2B can be a half-cavity type in which the first surface or the second surface of the glass substrate 100 is recessed.

[0056] The contact surface of the cavity portion 110 contacts the element directly or through another layer when the element is disposed in the cavity. The contact surface is disposed opposite to the opening.

[0057] The side wall of the cavity portion 110 is a wall surrounding the contact surface. That is, it can be a wall surrounding the cavity space of the cavity portion 110. When the contact surface has a rectangular shape, the side wall can include four surfaces.

[0058] The side wall connects the first surface of the substrate region 120 and the contact surface.

[0059] When viewed from above the opening, the cavity portion 110 can have a shape such as substantially circular, triangular, rectangular, hexagonal, octagonal, cruciform, etc., without limitation to its shape.

[0060] On the other hand, as described above, a cavity portion can be formed in the glass substrate, and a cavity element can be disposed in the cavity portion. In this case, in order to prevent the occurrence of a short circuit of the cavity element, etc., a gap can be disposed between the cavity element and the side wall in the cavity portion. A filling portion can be disposed in the gap.

[0061] The cavity element can include an active element such as a transistor, or a power transmission element such as a multilayer ceramic capacitor (MLCC), that is, a passive element.

[0062] When an active element such as a transistor that serves to convert an electrical signal between a motherboard and a semiconductor element part to an appropriate level is applied as the cavity element, a transistor or the like is applied to the passage of the packaging substrate, so that a more efficient and faster semiconductor device can be provided.

[0063] Also, a power transmission element such as a multilayer ceramic capacitor (MLCC) plays an important role in the performance of semiconductor elements. The power transmission element, which is a passive element, can be applied to at least 200 or more semiconductor elements, and a plate shape or the like may be applied according to the form, and the number of power transmission elements applied can be different.

[0064] In transmitting power, the performance is also affected by the characteristics of the electrically conductive layer around the element. In one embodiment, a non-circular core via can be applied where a low-resistance electrically conductive layer is required like such a power transmission element.

[0065] On the other hand, the cavity element may be applied with the elements inserted individually, or an element group including a number of elements embedded between insulator layers (cavity element insulator layers) may be inserted into the cavity element after being formed such that the electrodes are exposed. In the latter case, the workability of manufacturing the packaging substrate can be made smoother, and it is more advantageous for the insulating layer to be positioned in the space between complex elements sufficiently and with high reliability.

[0066] Here, depending on the shape and size in which the gap is formed, a large loss of the filling material for arranging the filling portion may occur. An embodiment can reduce the surface fluctuation of the filling material by substantially reducing the volume of the filling portion, which may be advantageous for the formation of an additional build-up layer.

[0067] That is, this specification proposes an embodiment in which the volume of the gap within the cavity portion is reduced or the surface fluctuation is decreased. Through this, the utilization area of the glass substrate can be increased, the loss of the filling material can be reduced, and the effect of facilitating the formation of an additional build-up layer can be achieved.

[0068] FIG. 3 is a diagram exemplarily showing the structure of a packaging substrate according to an embodiment, FIG. 4A is a conceptual diagram explaining the cross-section of a packaging substrate according to an embodiment, and FIG. 4B is a conceptual diagram explaining the cross-section of a glass substrate according to another embodiment. Also, FIG. 5A is a conceptual diagram explaining the cross-section of a packaging substrate according to another embodiment, and FIG. 5B is a conceptual diagram explaining the cross-section of a glass substrate according to another embodiment.

[0069] Referring to FIG. 3, the packaging substrate 200 may include a glass substrate 100 having a first surface and a second surface, and a cavity portion may be formed in the glass substrate 100 having the first surface and the second surface. A cavity element 210 may be disposed in the cavity portion, and a filling portion 220 may be disposed in the gap between the cavity element 210 and the sidewall of the cavity portion.

[0070] Optionally, the packaging substrate 200 may further include a film layer 22 located under the glass substrate 100. The film layer 22 may be attached during the manufacturing process and then removed after being utilized in processes such as the placement and filling of the elements in the cavity portion. Exemplarily, an adhesive film such as a PI tape may be applied to the film layer.

[0071] In an embodiment, after the cavity elements 210 are arranged in the cavity portion, the filling portion 220 may be generated. For example, a method such as vacuum laminating the filling portion 220 in the form of a film may be applied. When performing vacuum lamination in this way, the filling portion 220 is sufficiently embedded into the empty space inside the cavity portion, so that a filling portion 220 without void formation can be formed. The filling portion 220 may be filled with a filling material.

[0072] One type or two or more types of the filling materials may be applied together.

[0073] Two or more types of the filling materials may be applied with the space being divided.

[0074] The filling material may be filled in portions two or more times. Depending on the filling timing, a boundary line may be arranged in the filling material. Since the materials of the boundary lines are different from each other, they can appear as distinct boundary lines, or the first material and the second material can be expressed in a form where they are partially mixed and gradated near the boundary line.

[0075] An insulating material may be applied as the filling material.

[0076] Both an insulating material and a metallic material may be applied as the filling material.

[0077] As the insulating material, a polymer resin, a mixed material of a polymer resin and a filler (such as inorganic particles, organic particles, organic-inorganic composite particles), an inorganic vapor deposition layer, etc. may be applied.

[0078] Exemplarily, as the polymer resin, an acrylic resin, an epoxy resin, a modified resin thereof, etc. may be applied, and a material applicable for purposes such as molding in an electronic device may be applied. Exemplarily, LCP (liquid crystal polymer), etc. may be applied.

[0079] Exemplarily, the mixed material may be a mixture of an acrylic resin and a filler, a mixture of a mixture of an acrylic resin and an epoxy resin and a filler, a mixture of an epoxy resin and a filler, etc. As the filler, inorganic particles may be applied, and exemplarily, silica particles may be applied. As commercially available products, ABF (Ajinomoto Build-up Film), EMC (Epoxy Molding Compound), MPI (Modified Polyimide), etc. may be applied, but are not limited thereto.

[0080] The metal material can perform functions such as an electrically conductive layer and a heat dissipation layer.

[0081] As the metal material, copper or an alloy of copper and titanium, chromium, nickel, etc. may be applied. Also, as the metal material, aluminum or an alloy containing the same may be applied.

[0082] When the filling material is filled in portions separately two or more times, a boundary line may be arranged in the form of a dimple or an inclined surface in the filling portion.

[0083] Referring to FIG. 4A, the cavity space of the cavity portion formed in the glass substrate 100 may be a full cavity type penetrating the glass substrate 100. The cavity portion may include a gap 280 disposed between the cavity element 210 and the side wall of the cavity portion, and a filling portion 220 may be disposed in the gap 280. For example, the width of the gap 280 may be 50 μm or less, 45 μm or less, 40 μm or less, 35 μm or less, 30 μm or less, or 25 μm or less. The width of the gap 280 may be 15 μm or more, or 20 μm or more. When the width of the gap 280 is different for each measurement position above and below the gap, the width at the widest position is treated as the width of the gap. Other characteristics such as the packaging substrate 200 may include a film layer 22 located under the second surface of the glass substrate 100 are all applicable to the embodiments described above.

[0084] Referring to FIG. 4B, the cavity space of the cavity portion formed in the glass substrate 100 may be a half-cavity type in which the first surface or the second surface of the glass substrate 100 is recessed. The cavity portion may include a cavity space into which at least a part of the cavity element 210 is inserted, sidewalls surrounding the cavity space, and a contact surface. Further, the cavity portion may include a gap 280 disposed between the cavity element 210 and the sidewall of the cavity portion, and a filling portion 220 may be disposed in the gap 280. For example, the width of the gap 280 may be 50 μm or less, 45 μm or less, 40 μm or less, 35 μm or less, 30 μm or less, or 25 μm or less. The width of the gap 280 may be 15 μm or more, or 20 μm or more. When the width of the gap 280 varies at each measurement position above and below the gap, the width at the widest position is treated as the width of the gap. The packaging substrate 200 may include a film layer 22 located under the second surface of the glass substrate 100. Other characteristics such as this are all applicable to the embodiments described above.

[0085] This specification proposes an embodiment in which the gap in the cavity portion is formed in a tapered structure so that the volume of the gap is reduced. For example, the cavity portion includes a gap disposed between the cavity element and the sidewall, and the sidewall can be inclined at a specific angle with respect to the first surface or the second surface of the glass substrate. Through this, the utilization area of the glass substrate can be increased, the loss of the filling material can be reduced, and the surface fluctuation of the filling material can be reduced, thereby advantageously forming an additional build-up layer.

[0086] Referring to FIG. 5A, the cavity space of the cavity portion formed in the glass substrate 100 can be a cavity type that penetrates the glass substrate 100. The cavity portion can include a gap 280 disposed between the cavity element 210 and the side wall of the cavity portion, and a filling portion 220 can be disposed in the gap 280. The side wall can be inclined at a specific angle 225 with respect to the second surface of the glass substrate. For example, the angle 225 between the side wall and the second surface may be 65° or more, 70° or more, 75° or more, 80° or more, 82° or more, or 83° or more. The angle 225 may be 86° or less, or 85° or less.

[0087] The cavity portion has an opening surface located at the opening of the cavity space; and a bottom surface of the recess of the cavity space, or a bottom surface facing the opening surface, and can have the feature that the area of the opening surface is larger than the area of the bottom surface.

[0088] Other characteristics such as the width of the gap 280 and the film layer 22 located under the second surface of the glass substrate 100 can be included, and all of the above-described characteristics are applicable to the embodiments.

[0089] Referring to FIG. 5B, the cavity space of the cavity portion formed in the glass substrate 100 may be a half-cavity type in which the first surface or the second surface of the glass substrate 100 is recessed. The cavity portion may include a cavity space into which at least a part of the cavity element 210 is inserted, a side wall surrounding the cavity space, and a contact surface. The cavity portion may include a gap 280 disposed between the cavity element 210 and the side wall of the cavity portion, and a filling portion 220 may be disposed in the gap 280. The side wall may be inclined at a specific angle with reference to the second surface of the glass substrate. For example, the angle 225 between the side wall and the second surface may be 65° or more, 70° or more, 75° or more, 80° or more, 82° or more, or 83° or more. The angle 225 may be 86° or less, or 85° or less. Other characteristics such as the width of the gap 280 are such that all of the above-described characteristics are applicable to the embodiments.

[0090] A plurality of cavity elements may be arranged on the glass substrate. This specification proposes an embodiment in which a gap is formed in a cavity portion in which a plurality of cavity elements are arranged.

[0091] FIG. 6A is a conceptual diagram for explaining a cross-section of a packaging substrate according to another embodiment, and FIG. 6B is a conceptual diagram for explaining a cross-section of a glass substrate according to another embodiment.

[0092] Referring to FIG. 6A, the cavity space of the cavity portion formed in the glass substrate 100 may be a cavity type that penetrates the glass substrate 100. A plurality of cavity elements 210 may be arranged in the cavity portion.

[0093] For example, the glass substrate 100 can include a first cavity portion and a second cavity portion. A first cavity element can be disposed in the first cavity portion, and a second cavity element can be disposed in the second cavity portion. The first cavity portion can include a gap 280 disposed between the first cavity element and the sidewall of the first cavity portion, and the second cavity portion can include a gap 280 disposed between the second cavity element and the sidewall of the second cavity portion. Also, a gap 280 can be disposed between the first cavity portion and the second cavity portion. Referring to FIG. 6A, in a cross-sectional view, gaps can be disposed on both sides of the first cavity element and on both sides of the second cavity element. For example, in a cross-sectional view, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element can be 200 μm or less. The sum of the gaps can be 200 μm or less, 190 μm or less, 180 μm or less, 170 μm or less, 160 μm or less, 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 110 μm or less, 100 μm or less, or 98 μm or less. The sum of the gaps can also be 60 μm or more, 70 μm or more, or 80 μm or more. A filling portion 220 can be disposed in the gap 280.

[0094] Other characteristics, such as the angle 225 between the sidewall and the second surface, and the film layer 22 located under the second surface of the glass substrate 100, can be such that all of the above-described characteristics are applicable to the embodiments.

[0095] Alternatively, although not shown in FIG. 6A for example, the first cavity element and the second cavity element may be arranged together in one cavity portion. In a cross-sectional view, the cavity portion may include a gap between the first cavity element and the second cavity element, and two gaps arranged between each cavity element and the side wall. In this case, the sum of the gaps may be 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 100 μm or less, 90 μm or less, or 80 μm or less. The sum of the gaps may be 50 μm or more, 60 μm or more, or 70 μm or more. A filling portion 220 may be arranged in the gap 280.

[0096] Other characteristics such as the angle 225 between the side wall and the second surface, and the film layer 22 located under the second surface of the glass substrate 100 can be included, and all of the above-described characteristics are applicable to the embodiments.

[0097] Referring to FIG. 6B, the cavity space of the cavity portion formed in the glass substrate 100 may be of a half-cavity type in which the first surface or the second surface of the glass substrate 100 is recessed. The cavity portion may include a cavity space into which at least a part of the cavity element 210 is inserted, a side wall surrounding the cavity space, and a contact surface.

[0098] For example, the glass substrate 100 can include a cavity portion, and a first cavity element and a second cavity element can be disposed in the cavity portion. The cavity portion can include a gap 280 disposed between the first cavity element and the side wall of the cavity portion, and a gap 280 disposed between the second cavity element and the side wall of the cavity portion. Also, a gap 280 can be disposed between the first cavity element and the second cavity element. Referring to FIG. 6A, in a cross-sectional view, gaps can be disposed on both sides of the first cavity element and on both sides of the second cavity element. For example, in a cross-sectional view, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element can be 150 μm or less. That is, the sum of the gaps may be 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 100 μm or less, 90 μm or less, or 80 μm or less. The sum of the gaps may also be 50 μm or more, 60 μm or more, or 70 μm or more. A filling portion 220 can be disposed in the gap 280.

[0099] Although not shown in FIG. 6B, the glass substrate 100 can include a first cavity portion and a second cavity portion, a first cavity element can be disposed in the first cavity portion, and a second cavity element can be disposed in the second cavity portion. The first cavity portion can include a gap 280 disposed between the first cavity element and the side walls on both sides of the first cavity portion, and the second cavity portion can include a gap 280 disposed between the second cavity element and the side walls on both sides of the second cavity portion. The sum of the gaps may be 200 μm or less, 190 μm or less, 180 μm or less, 170 μm or less, 160 μm or less, 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 110 μm or less, 100 μm or less, or 98 μm or less. The sum of the gaps may also be 60 μm or more, 70 μm or more, or 80 μm or more. A filling portion 220 can be disposed in the gap 280.

[0100] Other characteristics, such as the angle 225 between the side wall and the second surface, and the film layer 22 located under the second surface of the glass substrate 100, etc., can be included, and all of the above-described characteristics are applicable to the embodiments.

[0101] Also, a packaging substrate 200 according to an embodiment includes a glass substrate 100, an upper layer 300 located on one surface of the glass substrate 100, and a cavity portion 110 where a cavity element can be located.

[0102] The packaging substrate 200 can further include a lower layer 400 located under the other surface of the glass substrate 100.

[0103] FIGS. 7A and 7B are an example of a cross-sectional structure of a packaging substrate generated according to an embodiment. In the drawings, the upper layer and the lower layer are shown schematically with the display of the internal electrically conductive layer, the structure of the insulating layer, etc. omitted.

[0104] Referring to FIG. 7A, the packaging substrate 200 can include a glass substrate in which a cavity portion including a cavity element and a gap is formed. An upper layer 300 can be disposed on one surface of the glass substrate 100, and a lower layer 400 can be disposed under the other surface of the glass substrate 100. Also, referring to FIG. 7B, the packaging substrate 200 can include a glass substrate in which a cavity portion including a cavity element and a gap is formed and a film layer. An upper layer 300 can be disposed on one surface of the glass substrate 100, and a lower layer 400 can be disposed under the other surface of the glass substrate 100.

[0105] The upper layer 300 includes an upper distribution layer and an upper surface connection layer located on the upper distribution layer, and the uppermost surface of the upper layer 300 can be protected by a cover layer in which an opening is formed where the connection electrode of the semiconductor element portion can be directly abutted.

[0106] The upper distribution layer includes an upper insulating layer located on the first surface, and an electrically conductive layer having a predetermined pattern and being electrically connected to at least a part of the core distribution layer, the upper distribution pattern being built in the upper insulating layer.

[0107] The upper insulating layer can be applied as an insulator layer to a semiconductor element or a packaging substrate. For example, an epoxy resin containing a filler may be applied, but it is not limited thereto.

[0108] The insulator layer may be formed by a method of forming a coating layer and curing it, or may be formed by a method of laminating an insulator film formed into a film in an uncured or semi-cured state on the glass substrate 100 and then curing it. At this time, if a vacuum lamination method or the like is applied, the insulator can be embedded even in the internal space of the core via, and an efficient process can proceed.

[0109] Semiconductor device To achieve the above object, a semiconductor device according to an embodiment includes a semiconductor element portion where one or more semiconductor elements are located, a packaging substrate electrically connected to the semiconductor elements, and a motherboard electrically connected to the packaging substrate, transmitting electrical signals between the semiconductor elements and the outside, and connecting to each other.

[0110] The semiconductor element portion means an element mounted on a semiconductor device and is mounted on the packaging substrate by connection electrodes or the like. Specifically, as the semiconductor element portion, for example, arithmetic elements such as a CPU and a GPU, storage elements such as a memory chip, etc. may be applied, but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0111] As the motherboard, a motherboard such as a printed circuit board or a printed wiring board may be applied.

[0112] According to one embodiment, even when a multi-layer insulator layer is laminated and applied, it may be difficult to substantially distinguish between the insulator layers, and the plurality of insulator layers are collectively referred to as an upper insulator layer. Also, the same insulating material may be applied to the core insulating layer and the upper insulating layer, and in such a case, the boundary therebetween may be substantially difficult to distinguish. Alternatively, according to another embodiment, the boundary of the insulator layer can also be generated by setting different pressures and temperatures for curing the multi-layer insulator layer.

[0113] The upper distribution pattern means an electrically conductive layer located in the upper insulator layer in a preset form, and may be formed, for example, by a build-up layer method. Specifically, after forming an insulator layer and removing unnecessary portions of the insulator layer, an electrically conductive layer is formed by a method such as copper plating, and after selectively removing unnecessary portions of the electrically conductive layer, an insulator layer is formed again on this electrically conductive layer, and after removing unnecessary portions again, the method of forming an electrically conductive layer by a method such as plating is repeated to form an upper distribution pattern in which the electrically conductive layer is formed in a vertical or horizontal direction in an intended pattern.

[0114] Since the upper distribution pattern is located between the glass substrate 100 and the semiconductor element portion, electrical signals are smoothly transmitted between the semiconductor element portion, and at least a part thereof is formed to include a fine pattern so that an intended complex pattern can be sufficiently accommodated. At this time, the fine pattern may have a width and a pitch each less than 4 μm, may be 3.5 μm or less, may be 3 μm or less, may be 2.5 μm or less, or may be 1 to 2.3 μm (hereinafter, the description of the fine pattern is the same).

[0115] The upper surface connection layer includes an upper surface connection pattern that is electrically connected to at least a part of the upper distribution pattern and is located on the upper insulating layer, and an upper surface connection electrode that electrically connects the semiconductor element portion and the upper surface connection pattern. The upper surface connection pattern may be located on one surface of the upper insulating layer, or at least a part of it may be embedded while being exposed on the upper insulating layer. For example, when the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating. When the upper surface connection pattern is embedded while a part of it is exposed on the upper insulating layer, it may be obtained by forming a copper plating layer or the like and then removing a part of the insulating layer or the electrically conductive layer by methods such as surface polishing and surface etching.

[0116] The upper surface connection pattern can include a fine pattern in at least a part of it, like the upper distribution pattern described above. The upper surface connection pattern including such a fine pattern enables more elements to be electrically connected in a narrow area, making the connection of electrical signals between elements or with the outside smoother and enabling more integrated packaging.

[0117] The upper surface connection electrode may be directly connected to the semiconductor element portion with a terminal or the like, or may be connected through an element connection portion such as a solder ball.

[0118] The packaging substrate 200 is also connected to the motherboard. The motherboard may be directly connected to a core distribution pattern located on at least a part of the second surface of the glass substrate 100 and a terminal of the motherboard, or may be electrically connected through a board connection portion such as a solder ball. Also, the core distribution pattern in contact with the motherboard may be connected to the motherboard through a lower layer 400 located below the glass substrate 100.

[0119] In one example, on the packaging substrate 200 positioned between the semiconductor element portion and the mother board, substantially no additional other substrate other than the glass substrate can be applied.

[0120] Method for manufacturing a packaging substrate To achieve the above object, this specification proposes a method for manufacturing a packaging substrate according to an embodiment. For example, the method for manufacturing a packaging substrate according to an embodiment of this specification includes the steps of preparing a glass substrate provided with a cavity portion and a cavity element; and arranging and filling the cavity element in the cavity portion.

[0121] A plate glass having a first surface and a second surface facing each other, on which a cavity portion is formed, can be applied as the glass substrate. A glass substrate in which a through via is further formed together with the cavity portion can be applied. Since specific descriptions about the shape, characteristics, etc. of the cavity portion overlap with the above descriptions, detailed descriptions are omitted.

[0122] The cavity portion of the glass substrate can be formed through a defect forming process and an etching process. Defects are formed at positions where the cavity portion and / or the through via of the glass plate are to be formed by a laser or the like, and this is immersed in an etching solution, and by utilizing the difference in etching rate, a glass substrate having a cavity portion and / or a through via can be obtained.

[0123] Next, a cavity element can be arranged in the cavity portion. The cavity element can include an active element such as a transistor, or a power transmission element such as a multilayer ceramic capacitor (MLCC), that is, a passive element.

[0124] When the cavity element is arranged in the cavity portion, a gap is formed between the cavity element and the side wall of the cavity portion as described above. Since specific descriptions about this overlap with the above descriptions, detailed descriptions are omitted.

[0125] When the cavity part is a full cavity, before arranging the cavity elements, a support layer such as a film layer can be arranged under the second surface of the glass substrate, and this film layer can be an adhesive film. In this case, it may be more advantageous for aligning the positions of the cavity elements in the cavity part which is a full cavity.

[0126] As the filling material filled in the gap, the above-described filling material can be applied. Exemplarily, a material curable by methods such as ultraviolet curing or heat curing can be applied as the filling material. Therefore, for forming the filling part, a method of arranging the filling material in the gap by a method such as vacuum lamination and curing the filling material by a method such as ultraviolet curing or heat curing can be applied.

[0127] The formation of the filling part may be performed by one or more filling processes.

[0128] Exemplarily, a filling material (primary filling material) is arranged in the filling part by primary vacuum lamination or the like to form a primary filling part before curing, and curing or semi-curing is performed. Then, again, a filling material (secondary filling material) is arranged by secondary vacuum lamination or the like to form a secondary filling part before curing, and this can be cured or semi-cured again. In this case, in a cross-sectional view, a boundary line may be arranged between the primary filling part and the secondary filling part. Also, when forming the filling part in two steps like this, a boundary can be observed in the filling part. Further, forming the filling part in two or more steps can reduce the generation of stress in the glass substrate, which can help suppress the occurrence of warping. Also, by filling two or more times, formation of dimples, formation of inclined surfaces on the surface of the filling part, etc. can be substantially suppressed.

[0129] On the other hand, an upper layer can be arranged on one surface of the packaging substrate, and a lower layer can be arranged under the other surface of the packaging substrate. The formation of the upper layer and / or the lower layer is applicable as long as it is a method of forming redistribution lines.

[0130] Exemplarily, the upper layer manufacturing step is as follows.

[0131] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition for forming an insulating layer or by laminating an insulating film. For simplicity, it is preferable to apply the method of laminating an insulating film. The lamination of the insulating film can be performed by a process of laminating and curing the insulating film. At this time, the vacuum lamination method can be applied so that the insulating resin can be sufficiently embedded even in a layer where no electrically conductive layer is formed inside the core via. The upper insulating layer also directly abuts at least a part of it against the glass substrate. Therefore, one having sufficient adhesion is applied. Specifically, it is preferable that the glass substrate and the upper insulating layer have a characteristic that the adhesion test value according to ASTM D3359 satisfies 4B or more.

[0132] The upper distribution pattern can be formed by repeating the process of forming the insulating layer, forming an electrically conductive layer in a predetermined pattern, and etching unnecessary portions to form an etched layer of the electrically conductive layer. In the case of an electrically conductive layer formed so as to be adjacent to each other with an insulating layer interposed therebetween, it can be formed by a method of forming blind vias in the insulating layer and then performing a plating process. The formation of blind vias may be applied with a dry etching method such as laser etching or plasma etching, or a wet etching method using a masking layer and an etching solution.

[0133] Thereafter, although not shown, an upper surface connection layer and a cover layer may be formed.

[0134] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the formation of the upper sub-layer. Specifically, an etching layer of the insulating layer may be formed on the insulating layer, and after forming an electrically conductive layer thereon again, it may be formed by a method such as forming an etching layer of the electrically conductive layer. However, a method of selectively forming only the electrically conductive layer without applying an etching method may also be applied. The cover layer can be formed such that an opening is formed at a position corresponding to the upper connection electrode to expose the upper connection electrode, and it can be directly connected to an element connection portion or a terminal of an element.

[0135] When the upper layer is generated, a step of forming the lower connection layer and the cover layer to generate the lower layer can be performed. The lower sub-layer and / or the lower connection layer, and optionally the cover layer, can be formed in a manner similar to the above-described upper connection layer and cover layer formation steps.

[0136] The manufacturing method of the packaging substrate according to the embodiments described above and the packaging substrate using the same can increase the utilization area of the glass substrate by reducing the volume of the gap between the side wall of the cavity portion and the cavity element, reduce the loss of the filling material, and reduce the surface fluctuation of the filling material, thereby advantageously forming an additional build-up layer.

[0137] The present specification described above has been described with reference to the embodiments shown in the drawings, but this is merely exemplary, and those having ordinary knowledge in the art will understand that various modifications and variations of the embodiments are possible from now on. That is, the scope of rights of the present specification is not limited to the above-described embodiments, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the appended claims also belong to the scope of rights of the embodiments. Therefore, the true technical protection scope of the present specification must be determined by the technical idea of the appended claims.

Explanation of Reference Numerals

[0138] 100 Glass substrate 110 Cavity part 120 Substrate area 200 Packaging substrate 210 Cavity element 22 Film layer 220 Filling part 225 Specific angle 300 Upper layer 400 Lower layer

Claims

1. A glass substrate having a first surface and a second surface facing each other, a cavity portion formed in the glass substrate, and a cavity element disposed in the cavity portion, wherein the cavity portion includes a cavity space into which at least a part of the cavity element is inserted, a side wall surrounding the cavity space, and a gap is disposed between one side surface of the cavity element and the side wall, the gap is filled with one or more filling materials, and the length of the gap is 50 μm or less, a packaging substrate.

2. The side wall is inclined, the angle between the side wall and the second surface is 65° or more, and the length of the gap is the maximum value among the distances between the side wall and one side surface of the cavity element. The packaging substrate according to Claim 1.

3. The cavity portion includes the cavity space is a full cavity type penetrating the glass substrate, the cavity portion includes an opening surface located at an opening of the cavity space, and a bottom surface facing the opening surface, and the area of the opening surface is wider than the area of the bottom surface. The packaging substrate according to Claim 1.

4. The cavity portion includes the cavity space is a half cavity type in which the first surface or the second surface of the glass substrate is recessed, the cavity portion includes an opening surface located at an opening of the cavity space, and a bottom surface of a recess portion of the cavity space, and the area of the opening surface is wider than the area of the bottom surface. The packaging substrate according to Claim 1.

5. The glass substrate includes a first cavity portion and a second cavity portion, a first cavity element is disposed in the first cavity portion, a second cavity element is disposed in the second cavity portion, and in a cross-sectional view, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element is 200 μm or less. The packaging substrate according to Claim 1.

6. A first cavity element and a second cavity element are disposed in the cavity portion, in a cross-sectional view, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element is 150 μm or less. The packaging substrate according to Claim 1.

7. A method for manufacturing a substrate for packaging, Preparing a glass substrate provided with a cavity portion and a cavity element; Arranging and filling the cavity element in the cavity portion; and The glass substrate has a first surface and a second surface facing each other; The cavity portion is; A cavity space into which at least a part of the cavity element is inserted; A side wall surrounding the cavity space; and A gap is arranged between one side surface of the cavity element and the side wall; The filling is to fill the gap with a filling material to form a filling portion; A method for manufacturing a packaging substrate, wherein the length of the gap is 50 μm or less.

8. In the cavity portion, the cavity space is a full cavity penetrating the glass substrate; The arranging is performed with a support layer attached under the second surface; The method for manufacturing a packaging substrate according to claim 7, wherein the support layer is removed after the filling step.

9. The side wall is inclined; The method for manufacturing a packaging substrate according to claim 7, wherein the required amount of the filling material is reduced by 30% or more compared with the case where the side wall is perpendicular to the second surface.

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