Gradation voltage generation circuit, display driver, and display device

Abstract

To provide a gradation voltage generation circuit capable of precisely adjusting the gamma characteristics while suppressing the increase in circuit scale, a display driver, and a display device.SOLUTION: A gradation voltage generation circuit related to the present invention includes: first to y-th ladder resistors each generating multiple voltages each having a voltage value according to one gamma characteristic out of first to y-th gamma characteristics; a selection circuit applying multiple gamma voltages to one ladder resistor specified by a ladder resistor selection signal specifying one ladder resistor out of the first to y-th ladder resistors; and an output selector outputting multiple voltages generated by the one ladder resistor specified by the ladder resistor selection signal as multiple gradation voltages.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a gradation voltage generation circuit, a display driver, and a display device that generate a plurality of gradation voltages having different voltage values.

Background Art

[0002] A liquid crystal type or organic EL type display device includes a display panel in which a plurality of gate lines extending in the horizontal direction of a two-dimensional screen and a plurality of source lines extending in the vertical direction of the two-dimensional screen are arranged, a gate driver that drives the gate lines, and a source driver that drives the source lines.

[0003] The source driver receives a pixel data piece representing the luminance level of each pixel based on a video signal, and includes a decoder that converts each of the pixel data pieces into a gradation voltage having a voltage value corresponding to the luminance level indicated by the pixel data piece. The decoder selects one of the plurality of gradation voltages generated by the gradation voltage generation circuit corresponding to the luminance level indicated by the pixel data piece, and supplies the selected gradation voltage to the source line of the display panel.

[0004] The gradation voltage generation circuit includes a ladder resistor formed by directly connecting a plurality of resistors, and generates, as a gradation voltage, the voltage generated at each tap by applying a voltage to a specific tap among the connection points (taps) between the resistors in the ladder resistor. Each of the plurality of gradation voltages generated by the gradation voltage generation circuit has a voltage value along a desired gamma characteristic.

[0005] Also, as such a gradation voltage generation circuit, a circuit has been proposed in which a tap selector is used to select a specific tap from among a plurality of taps of a ladder resistor when applying a voltage (referred to as a tap voltage) to a specific tap of a single system of ladder resistor (see, for example, Patent Document 1). In the gradation voltage generation circuit, by being able to select a specific tap to which the tap voltage is applied, adjustment of the gamma curve by the plurality of generated gradation voltages becomes possible.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] By the way, in recent years, the required gamma curve form, when the range of expressible luminance levels is divided into three ranges of low luminance, medium luminance, and high luminance, has a constant slope in the medium luminance range regardless of the difference in gamma characteristics, but in the low luminance and high luminance ranges, it has a steep curve or a gentle curve depending on the difference in gamma characteristics.

[0008] At this time, since the resistance values of the plurality of resistors constituting one system of ladder resistors as described in Patent Document 1 are fixed, even if the tap to which the tap voltage is applied is changed, it is difficult to adjust to a gamma curve along the desired gamma characteristics with high precision.

[0009] Therefore, an object of the present invention is to provide a gradation voltage generation circuit, a display driver, and a display device capable of suppressing an increase in circuit scale and performing high-precision adjustment of gamma characteristics.

Means for Solving the Problems

[0010] The gradation voltage generation circuit according to the present invention includes first to y-th (y is an integer of 2 or more) ladder resistors that respectively generate a plurality of voltages having voltage values along first to y-th gamma characteristics, a ladder resistor selection signal that specifies one of the first to y-th ladder resistors, a selection circuit that applies a plurality of gamma voltages to the one ladder resistor specified by the ladder resistor selection signal among the first to y-th ladder resistors, and an output selector that outputs the plurality of voltages generated by the one ladder resistor specified by the ladder resistor selection signal as a plurality of gradation voltages.

[0011] The display driver according to the present invention receives a video signal, converts each of pixel data pieces representing the luminance level of each pixel based on the video signal into a gradation voltage having a voltage value corresponding to each of the luminance levels, and supplies a drive signal based on the gradation voltage to a data line of a display panel. The display driver includes a gradation voltage generation circuit that generates a plurality of gradation voltages having different voltage values from each other, a decoder unit that selects and outputs, for each of the pixel data pieces, a gradation voltage corresponding to the luminance level indicated by the pixel data piece from among the plurality of gradation voltages, and an output amplifier unit that generates the drive signal by amplifying the gradation voltage output from the decoder unit and supplies the drive signal to the data line of the display panel. The gradation voltage generation circuit includes first to y-th ladder resistors (where y is an integer of 2 or more) that respectively generate a plurality of voltages having voltage values along first to y-th gamma characteristics, a selection circuit that receives a ladder resistor selection signal specifying one of the first to y-th ladder resistors and applies a plurality of gamma voltages to the one ladder resistor specified by the ladder resistor selection signal among the first to y-th ladder resistors, and an output selector that outputs the plurality of voltages generated by the one ladder resistor specified by the ladder resistor selection signal as a plurality of gradation voltages.

[0012] The display device according to the present invention includes a display panel including a plurality of data lines to which a plurality of display cells are respectively connected, and a display driver that receives a video signal and converts each of pixel data pieces representing the luminance level of each pixel based on the video signal into a gradation voltage having a voltage value corresponding to each luminance level, and supplies a drive signal based on the gradation voltage to the data lines of the display panel. The display driver includes a gradation voltage generation circuit that generates a plurality of gradation voltages having different voltage values from each other, a decoder unit that selects and outputs, for each of the pixel data pieces, a gradation voltage corresponding to the luminance level indicated by the pixel data piece from among the plurality of gradation voltages, and an output amplifier unit that generates the drive signal by amplifying the gradation voltage output from the decoder unit and supplies the drive signal to the data lines of the display panel. The gradation voltage generation circuit includes first to y-th ladder resistors (where y is an integer of 2 or more) that respectively generate a plurality of voltages having voltage values along first to y-th gamma characteristics, a selection circuit that receives a ladder resistor selection signal specifying one of the first to y-th ladder resistors and applies a plurality of gamma voltages to the one ladder resistor specified by the ladder resistor selection signal among the first to y-th ladder resistors, and an output selector that outputs the plurality of voltages generated by the one ladder resistor specified by the ladder resistor selection signal as a plurality of gradation voltages.

Effect of the Invention

[0013] In the present invention, a plurality of ladder resistors corresponding to a plurality of required gamma characteristics are provided, and gradation voltage generation and adjustment are performed by applying a plurality of gamma voltages to one ladder resistor specified by a ladder resistor selection signal from among these ladder resistors.

[0014] Accordingly, compared with adjusting the gamma characteristics by switching the position of the tap to which the gamma voltage is applied with respect to a plurality of taps provided in one ladder resistor, it becomes possible to generate a gradation voltage with high accuracy along the required gamma characteristics. Further, according to such a configuration, it is not necessary to provide a gamma amplifier for generating a gamma voltage for each ladder resistor, so that an increase in circuit scale can be suppressed.

Brief Description of Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

Examples

[0016] Hereinafter, the present invention will be described in detail with reference to the drawings.

[0017] FIG. 1 is a block diagram showing a schematic configuration of a display device 100 equipped with a display driver including a gradation voltage generation circuit according to the present invention.

[0018] The display device 100 includes a display controller 10, a gate driver 11, a data driver 12, and a display panel 20.

[0019] The display panel 20 is composed of, for example, a liquid crystal or organic EL type display panel, and has gate lines GL1 to GLr (r is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen and data lines DL1 to DLw (w is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen. At each intersection of the gate lines GL1 to GLr and the data lines DL1 to DLw, display cells (regions surrounded by broken lines) for performing red, green, or blue display are formed.

[0020] The display controller 10 receives the video signal VD, and based on the video signal VD, supplies a gate timing signal indicating the timing for applying a gate selection signal to each of the gate lines GL1 to GLr to the gate driver 11.

[0021] In addition, the display controller 10 generates a video data signal DVS including various control signals including a clock signal and a load signal, etc., and a series of display data pieces representing the luminance level of each pixel as digital values based on the video signal VD, and supplies this to the data driver 12.

[0022] The gate driver 11 sequentially generates a gate selection signal including at least one pulse for selecting a gate line in response to the gate timing signal supplied from the display controller 10, and supplies it to each of the gate lines GL1 to GLr of the display panel 20.

[0023] The data driver 12 takes in each display data segment included in the video data signal DVS one horizontal scanning line (w pieces) at a time, and converts each display data segment into a drive signal having a voltage value corresponding to the luminance level represented by each. Then, the data driver 12 supplies the generated w drive signals as drive signals G1 to Gw to the data lines DL1 to DLw of the display panel 20, respectively.

[0024] FIG. 2 is a block diagram schematically showing the internal configuration of the data driver 12.

[0025] As shown in FIG. 2, the data driver 12 includes a control circuit 120, a data latch section 121, a gradation voltage generation circuit 122, a decoder section 123, and an amplifier section 124.

[0026] The control circuit 120 receives the video data signal DVS, extracts a control signal including a clock signal and a load signal, etc., and a series of display data segments from the video data signal DVS, and supplies them to the data latch section 121.

[0027] Furthermore, the control circuit 120 supplies a gamma characteristic designation signal de for designating the gamma characteristic, and ladder resistance selection signals e1 to e4 for designating the ladder resistance to the gradation voltage generation circuit 122. Note that each of the ladder resistance selection signals e1, e2, e3, and e4 is a binary signal of logic level 0 or 1.

[0028] When the control circuit 120 designates, as the ladder resistor to use, the first ladder resistor among the first to fourth ladder resistors, the control circuit 120 supplies the tone voltage generation circuit 122 with ladder resistor selection signals e1 to e4 in which, for example, only e1 among the ladder resistor selection signals e1 to e4 has a logical level of 1 and the others have a logical level of 0. Also, when designating the second ladder resistor, the control circuit 120 supplies the tone voltage generation circuit 122 with ladder resistor selection signals e1 to e4 in which only e2 among the ladder resistor selection signals e1 to e4 has a logical level of 1 and the others have a logical level of 0. Also, when designating the third ladder resistor, the control circuit 120 supplies the tone voltage generation circuit 122 with ladder resistor selection signals e1 to e4 in which only e3 among the ladder resistor selection signals e1 to e4 has a logical level of 1 and the others have a logical level of 0. Also, when designating the fourth ladder resistor, the control circuit 120 supplies the tone voltage generation circuit 122 with ladder resistor selection signals e1 to e4 in which only e4 among the ladder resistor selection signals e1 to e4 has a logical level of 1 and the others have a logical level of 0.

[0029] The data latch unit 121 sequentially captures each display data piece in the series of display data pieces at the timing of the clock signal in response to the load signal. Each time the data latch unit 121 captures w display data pieces, the data latch unit 121 outputs the w display data pieces to the decoder unit 123 as display data P1 to Pw.

[0030] The tone voltage generation circuit 122 generates tone voltages VG0 to VGn (n is an integer of 2 or more) each having a voltage value along the gamma characteristic specified by the gamma characteristic specification signal de, and supplies the tone voltages to the decoder unit 123.

[0031] The decoder unit 123 includes w decoders DEC that respectively receive the display data P1 to Pw output from the data latch unit 121 individually. Each of the decoders DEC receives the above-described tone voltages VG0 to VGn, and selects a tone voltage having a voltage value corresponding to the luminance level indicated by the display data piece received by the decoder from among the tone voltages VG0 to VGn. At this time, the decoder unit 123 supplies the w tone voltages selected by each decoder DEC to the amplifier unit 124 as tone voltages V1 to Vw.

[0032] The amplifier unit 124 generates, as the drive signals G1 to Gw described above, signals obtained by individually amplifying signals based on the gradation voltages V1 to Vw, and outputs them to the data lines DL1 to DLw of the display panel 20.

[0033] Next, the gradation voltage generation circuit 122 shown in FIG. 2 will be described in detail.

[0034] FIG. 3 is a block diagram showing the internal configuration of the gradation voltage generation circuit 122.

[0035] As shown in FIG. 3, the gradation voltage generation circuit 122 includes a ladder resistor LD, a gamma selector GSL, and a γ-curve selection ladder resistor circuit GLX, together with amplifiers GA0, GA1, and AP0 to APm (m is an integer of 2 or more and less than n).

[0036] The amplifiers GA0 and GA1 are input gamma amplifiers, each of which is composed of, for example, an operational amplifier of a voltage follower in which its inverting input terminal and output terminal are connected. The amplifier GA0 receives a first DC voltage VGMA0 at its non-inverting input terminal, and applies a voltage having the same voltage value as the voltage VGMA0 to the node nd1. The amplifier GA1 receives a second DC voltage VGMA1 having a voltage value lower than the voltage VGMA0 at its non-inverting input terminal, and applies a voltage having the same voltage value as the voltage VGMA1 to the node nd2.

[0037] The ladder resistor LD is composed of first to xth (x is an integer of 2 or more) resistors connected in series between the node nd1 and the node nd2, and outputs the voltages at each of the (x + 1) connection points (referred to as taps) in the first to xth resistors as reference voltages Rf0 to Rfx.

[0038] The gamma selector GSL receives the reference voltages RF0 to RFx, and selects (m + 1) reference voltages having voltage values along the gamma characteristic specified by the gamma characteristic designation signal de from among the reference voltages RF0 to RFx. Then, the gamma selector GSL supplies the selected reference voltage group as gamma voltages VI0 to VIm to the amplifiers AP0 to APm, respectively.

[0039] The amplifiers AP0 to APm are gamma amplifiers for outputting a gradation voltage, and each of them consists of, for example, an operational amplifier of a voltage follower in which its inverting input terminal and output terminal are connected. The amplifiers AP0 to APm individually receive the gamma voltages VI0 to VIm at their non-inverting input terminals, generate the amplified ones as gamma voltages γ0 to γm, and supply them to the gamma curve selection ladder resistance circuit GLX. At this time, among the gamma voltages γ0 to γm, the gamma voltage γ0 has the highest voltage value, and the gamma voltage γm has the lowest voltage value. Note that the amplifier AP0 outputs the gamma voltage γ0 having the highest voltage value generated by itself as the gradation voltage V0. Also, the amplifier APm outputs the gamma voltage γm having the lowest voltage value generated by itself as the gradation voltage Vn.

[0040] The gamma curve selection ladder resistance circuit GLX includes first to fourth ladder resistances. Note that the first to fourth ladder resistances correspond to first to fourth gamma characteristics having different voltage value transition forms, and can generate (n - 1) voltages along the gamma characteristic from (n - 1) taps provided in each of them. Here, the gamma curve selection ladder resistance circuit GLX selects one ladder resistance specified by the ladder resistance selection signals e1 to e4 from among the first to fourth ladder resistances, and applies the gamma voltages γ1 to γ(m - 1) to each of (m - 1) taps of the selected ladder resistance. At this time, the selected one ladder resistance has the gamma voltages γ0 and γm described above applied thereto together with the gamma voltages γ1 to γ(m - 1), and generates (n - 1) voltages at its (n - 1) taps. The gamma curve selection ladder resistance circuit GLX outputs the (n - 1) voltages generated by the one ladder resistance specified by the ladder resistance selection signals e1 to e4 as gradation voltages VG1 to VG(n - 1).

[0041] FIG. 4 is a circuit diagram showing an example of the internal configuration of the gamma curve selection ladder resistance circuit GLX.

[0042] The gamma curve selection ladder resistance circuit GLX includes first to fourth ladder resistors LDa to LDd, selection circuits SE1 to SE(m - 1), and an output selector OSE.

[0043] As shown in FIG. 4, a gamma voltage γ0 is applied to one end of each of the ladder resistors LDa to LDc, and a gamma voltage γm is applied to the other end of each of the ladder resistors LDa to LDc.

[0044] Each of the ladder resistors LDa to LDc is provided with taps for receiving gamma voltages γ1 to γ(m - 1), respectively. That is, the ladder resistor LDa is provided with taps t1a to t(m - 1)a, the ladder resistor LDb is provided with taps t1b to t(m - 1)b, the ladder resistor LDc is provided with taps t1c to t(m - 1)c, and the ladder resistor LDd is provided with taps t1d to t(m - 1)d.

[0045] The selection circuits SE1 to SE(m - 1) have the same internal configuration, that is, they include amplifiers GPa to GPd with a gain of 1 and an enable terminal.

[0046] As shown in FIG. 4, each output terminal of the amplifier GPa included in each of the selection circuits SE1 to SE(m - 1) is connected to the taps t1a to t(m - 1)a of the ladder resistor LDa. Also, each output terminal of the amplifier GPb included in each of the selection circuits SE1 to SE(m - 1) is connected to the taps t1b to t(m - 1)b of the ladder resistor LDb. Also, each output terminal of the amplifier GPc included in each of the selection circuits SE1 to SE(m - 1) is connected to the taps t1c to t(m - 1)c of the ladder resistor LDc. Also, each output terminal of the amplifier GPd included in each of the selection circuits SE1 to SE(m - 1) is connected to the taps t1d to t(m - 1)d of the ladder resistor LDd.

[0047] Also, a gamma voltage γ1 is supplied to the input terminals of each of the amplifiers GPa to GPd included in the selection circuit SE1, and a gamma voltage γ2 is supplied to the input terminals of each of the amplifiers GPa to GPd included in the selection circuit SE2. Similarly, a gamma voltage γv is supplied to the input terminals of each of the amplifiers GPa to GPd included in the selection circuit SEv (v is an integer from 3 to m - 1).

[0048] Here, the group of amplifiers GPa included in each of the selection circuits SE1 to SE(m - 1) becomes enabled when receiving a ladder resistor selection signal e1 of logic level 1 for selecting the first ladder resistor LDa. As a result, the group of amplifiers GPa applies voltages corresponding to the respective input gamma voltages to the taps t1a to t(m - 1)a of the ladder resistor LDa. Consequently, the ladder resistor LDa outputs the voltages generated at its (n - 1) taps as voltages a1 to a(m - 1) having voltage values along the first gamma curve. On the other hand, when receiving a ladder resistor selection signal e1 of logic level 0, each of the amplifiers GPa becomes disabled and stops applying voltages to the taps t1a to t(m - 1)a of the ladder resistor LDa.

[0049] Also, the group of amplifiers GPb included in each of the selection circuits SE1 to SE(m - 1) becomes enabled when receiving a ladder resistor selection signal e2 of logic level 1 for selecting the second ladder resistor LDb. As a result, the group of amplifiers GPb applies voltages corresponding to the respective input gamma voltages to the taps t1b to t(m - 1)b of the ladder resistor LDb. Consequently, the ladder resistor LDb outputs the voltages generated at its (n - 1) taps as voltages b1 to b(m - 1) having voltage values along the second gamma curve. On the other hand, when receiving a ladder resistor selection signal e2 of logic level 0, each of the amplifiers GPb becomes disabled and stops applying voltages to the taps t1b to t(m - 1)b of the ladder resistor LDb.

[0050] In addition, each of the amplifiers GPc included in the selection circuits SE1 to SE(m-1) becomes enabled when receiving a ladder resistor selection signal e3 of logic level 1 for selecting the third ladder resistor LDc. As a result, the group of amplifiers GPc applies voltages corresponding to the respective input gamma voltages to the taps t1c to t(m-1)c of the ladder resistor LDc. Consequently, the ladder resistor LDc outputs the voltages generated at its (n-1) taps as voltages c1 to c(m-1) having voltage values along the third gamma curve. On the other hand, when receiving a ladder resistor selection signal e3 of logic level 0, each of the amplifiers GPc becomes disabled and stops applying voltages to the taps t1c to t(m-1)c of the ladder resistor LDc.

[0051] In addition, each of the amplifiers GPd included in the selection circuits SE1 to SE(m-1) becomes enabled when receiving a ladder resistor selection signal e4 of logic level 1 for selecting the fourth ladder resistor LDd. As a result, the group of amplifiers GPd applies voltages corresponding to the respective input gamma voltages to the taps t1d to t(m-1)d of the ladder resistor LDd. Consequently, the ladder resistor LDd outputs the voltages generated at its (n-1) taps as voltages d1 to d(m-1) having voltage values along the fourth gamma curve. On the other hand, when receiving a ladder resistor selection signal e4 of logic level 0, each of the amplifiers GPd becomes disabled and stops applying voltages to the taps t1d to t(m-1)d of the ladder resistor LDd.

[0052] The output selector OSE receives, together with the ladder resistor selection signals e1 to e4, four sets of voltages a1 to a(n-1), voltages b1 to b(n-1), voltages c1 to c(n-1), and voltages d1 to d(n-1) output from the respective ladder resistors LDa to LDd.

[0053] The output selector OSE selects one set of voltage groups output from one of the four sets of ladder resistors (LDa, LDb, LDc, or LDd) indicated by the ladder resistor selection signals e1 to e4. For example, when the ladder resistor selection signals e1 to e4 indicate the ladder resistor LDa, the output selector OSE selects the voltage a1 to a(n - 1) from among the four sets of voltages a1 to a(n - 1), b1 to b(n - 1), c1 to c(n - 1), and d1 to d(n - 1). Also, when the ladder resistor selection signals e1 to e4 indicate the ladder resistor LDb, the output selector OSE selects the voltage b1 to b(n - 1) from among the above-described four sets of voltage groups.

[0054] Then, the output selector OSE outputs the one set of voltage groups selected as described above as the gradation voltages VG1 to VG(n - 1).

[0055] In this way, the gradation voltage generation circuit 122 includes the first to fourth ladder resistors LDa to LDd, each corresponding to one of the first to fourth gamma characteristics with different forms of the slope of the gamma curve, and each generating a plurality of voltages when the gamma voltages γ0 to γm are applied. Further, the gradation voltage generation circuit 122 includes selection circuits SE1 to SE(m - 1) that select one of the above-described first to fourth ladder resistors LDa to LDd specified by the ladder resistor selection signals e1 to e4 and apply the gamma voltages γ1 to γ(m - 1) to the selected ladder resistor, and the following output selector OSE.

[0056] The output selector OSE selects the ladder resistor specified by the above-described ladder resistor selection signals e1 to e4 from among the first to fourth ladder resistors LDa to LDd, and outputs the (n - 1) voltages generated by the selected ladder resistor as the gradation voltages VG1 to VG(n - 1).

[0057] That is, in the gradation voltage generation circuit 122, dedicated first to fourth ladder resistors LDa to LDd corresponding to the four required gamma characteristics are provided, and a gradation voltage is generated using only one ladder resistor specified by ladder resistor selection signals e1 to e4 from among these ladder resistors LDa to LDd. As a result, compared to the case where the gamma characteristics are adjusted by switching the position of the tap to which a voltage is applied with respect to a plurality of taps provided in one system of ladder resistors as disclosed in Patent Document 1, it becomes possible to generate a gradation voltage with high accuracy along the required gamma characteristics.

[0058] Further, in the gradation voltage generation circuit 122, the gamma voltages γ1 to γ(m - 1) generated by the amplifiers AP1 to AP(m - 1) are applied only to one ladder resistor selected by the selection circuits SE1 to SE(m - 1) from among the first to fourth ladder resistors LDa to LDd. Therefore, it becomes possible to reduce the circuit scale compared to the case where a plurality of amplifiers AP1 to AP(m - 1) are provided for each of the ladder resistors LDa to LDd.

[0059] By the way, in an example shown in FIG. 3, single-ended output type operational amplifiers are used as the amplifiers AP1 to AP(m - 1), but differential output type operational amplifiers may be employed.

[0060] FIG. 5 is a circuit diagram showing an excerpt of the internal configurations of the amplifiers GPa to GPd shown in FIG. 4 when differential output type operational amplifiers are employed as the amplifiers AP1 to AP(m - 1), with the amplifiers GPa to GPd included in the selection circuit SE1 extracted.

[0061] Also, in FIG. 5, a differential output type amplifier AP1x is adopted instead of the single-ended output type amplifier AP1. Similar to the amplifier AP1, the gamma voltage VI1 output from the gamma selector GSL is received at its non-inverting input terminal. The amplifier AP1x outputs a gamma voltage γ1p having a voltage value corresponding to the gamma voltage VI1 from its first output terminal, and supplies the gamma voltage γ1p to each of the amplifiers GPa to GPd. Further, the amplifier AP1x outputs a gamma voltage γ1n obtained by inverting the polarity of the gamma voltage γ1p from its second output terminal, and supplies the gamma voltage γ1n to each of the amplifiers GPa to GPd.

[0062] Each of the amplifiers GPa to GPd has the same internal configuration, that is, it includes a P-channel transistor Q1, an N-channel transistor Q2, and switch elements S1 to S3.

[0063] A power supply voltage Vdd is applied to the source of the transistor Q1, and the drain is connected to the output node nd0. A ground voltage Vss is applied to the source of the transistor Q2, and the drain is connected to the output node nd0. At this time, the output node nd0 of the amplifier GPa is connected to the tap t1a of the ladder resistor LDa, and the output node nd0 of the amplifier GPb is connected to the tap t1b of the ladder resistor LDb. Also, the output node nd0 of the amplifier GPc is connected to the tap t1c of the ladder resistor LDc, and the output node nd0 of the amplifier GPd is connected to the tap t1d of the ladder resistor LDd.

[0064] The switch elements S1 to S3 of amplifier GPa turn on when receiving the ladder resistor selection signal e1 having a logic level 1. Therefore, at this time, the switch elements S1 to S3 supply the gamma voltage γ1p output from the amplifier AP1x to the gate of the transistor Q1, supply the gamma voltage γ1n output from the amplifier AP1x to the gate of the transistor Q2, and supply the voltage of the output node nd0 as a feedback voltage to the inverting input terminal of the amplifier AP1x. As a result, the voltage corresponding to the gamma voltage VI1 is applied to the tap t1a of the ladder resistor LDa via the output node nd0, and the voltage is supplied as a feedback voltage to the inverting input terminal of the amplifier AP1x. On the other hand, when receiving the ladder resistor selection signal e1 having a logic level 0, the switch elements S1 to S3 of the amplifier GPa turn off, stopping the operation of the amplifier GPa described above.

[0065] The switch elements S1 to S3 of amplifier GPb turn on when receiving the ladder resistor selection signal e2 having a logic level 1. Therefore, at this time, the switch elements S1 to S3 supply the gamma voltage γ1p output from the amplifier AP1x to the gate of the transistor Q1, supply the gamma voltage γ1n output from the amplifier AP1x to the gate of the transistor Q2, and supply the voltage of the output node nd0 as a feedback voltage to the inverting input terminal of the amplifier AP1x. As a result, the voltage corresponding to the gamma voltage VI1 is applied to the tap t1b of the ladder resistor LDb via the output node nd0, and the voltage is supplied as a feedback voltage to the inverting input terminal of the amplifier AP1x. On the other hand, when receiving the ladder resistor selection signal e2 having a logic level 0, the switch elements S1 to S3 of the amplifier GPb turn off, stopping the operation of the amplifier GPb described above.

[0066] The switch elements S1 to S3 of the amplifier GPc are turned on when receiving the ladder resistor selection signal e3 having a logic level 1. Therefore, at this time, the switch elements S1 to S3 supply the gamma voltage γ1p output from the amplifier AP1x to the gate of the transistor Q1, supply the gamma voltage γ1n output from the amplifier AP1x to the gate of the transistor Q2, and supply the voltage of the output node nd0 as a feedback voltage to the inverting input terminal of the amplifier AP1x. Thereby, a voltage corresponding to the gamma voltage VI1 is applied to the tap t1c of the ladder resistor LDc via the output node nd0, and the voltage is supplied as a feedback voltage to the inverting input terminal of the amplifier AP1x. On the other hand, when receiving the ladder resistor selection signal e3 having a logic level 0, the switch elements S1 to S3 of the amplifier GPc are turned off, and the operation of the amplifier GPc described above is stopped.

[0067] The switch elements S1 to S3 of the amplifier GPd are turned on when receiving the ladder resistor selection signal e4 having a logic level 1. Therefore, at this time, the switch elements S1 to S3 supply the gamma voltage γ1p output from the amplifier AP1x to the gate of the transistor Q1, supply the gamma voltage γ1n output from the amplifier AP1x to the gate of the transistor Q2, and supply the voltage of the output node nd0 as a feedback voltage to the inverting input terminal of the amplifier AP1x. Thereby, a voltage corresponding to the gamma voltage VI1 is applied to the tap t1d of the ladder resistor LDd via the output node nd0, and the voltage is supplied as a feedback voltage to the inverting input terminal of the amplifier AP1x. On the other hand, when receiving the ladder resistor selection signal e4 having a logic level 0, the switch elements S1 to S3 of the amplifier GPd are turned off, and the operation of the amplifier GPd described above is stopped.

[0068] By the way, in the gamma characteristics required in recent years, in the low voltage section and the high voltage section when the range of the gamma voltage is divided into a low voltage section, an intermediate voltage section, and a high voltage section, various gamma curves with different slopes are obtained for each model of the display panel and each primary color (red, blue, green).

[0069] FIG. 6 is a diagram showing an example of the form of the gamma characteristics required in recent years.

[0070] As shown in FIG. 6, in such gamma characteristics, in the low voltage range and the high voltage range, for example, four gamma curves gm1 to gm4 are obtained. However, in the intermediate voltage range between both ranges, it is common regardless of the model of the display panel and the difference in primary colors (red, blue, green).

[0071] Therefore, as the gradation voltage generation circuit 122, a configuration may be adopted in which the gamma curve can be changed by the ladder resistor selection signals e1 to e4 only for the low voltage range and the high voltage range of the gamma voltage shown in FIG. 6.

Example

[0072] FIG. 7 is a block diagram showing the configuration of a gradation voltage generation circuit 122_1 as another example of the gradation voltage generation circuit 122 made in view of this point.

[0073] In addition, in the configuration shown in FIG. 7, other configurations are the same as the configuration shown in FIG. 3 except that a common ladder resistor section Lcm, gamma curve selection ladder resistor circuits GLX1 and GLX2 are adopted instead of the γ curve selection ladder resistor circuit GLX shown in FIG. 3.

[0074] Therefore, the common ladder resistor section Lcm, the gamma curve selection ladder resistor circuits GLX1 and GLX2 will be described below.

[0075] The gamma curve selection ladder resistor circuit GLX1 includes first to fourth high voltage side ladder resistors. The first to fourth high voltage side ladder resistors correspond to, for example, the first to fourth gamma curves gm1 to gm4 in the high voltage range shown in FIG. 6 with different voltage value transition forms, and can generate j (j is an integer of 2 or more) voltages along the gamma curve from j taps provided respectively. Here, the gamma curve selection ladder resistor circuit GLX1 selects one ladder resistor specified by the ladder resistor selection signals e1 to e4 from among the first to fourth high voltage side ladder resistors.

[0076] Then, the gamma curve selection ladder resistance circuit GLX1 applies the gamma voltage γ0 to one end of the selected high-voltage side ladder resistance and the gamma voltage γ1 to the other end. As a result, the gamma curve selection ladder resistance circuit GLX1 outputs the voltages generated at each of the j taps of the high-voltage side ladder resistance as high-voltage side gradation voltages VG1 to VGn having voltage values along the gamma curves gm1, gm2, gm3, or gm4 in the high-voltage section shown in FIG. 6.

[0077] In addition, in the gradation voltage generation circuit 122_1, similar to the gradation voltage generation circuit 122 shown in FIG. 3, the gamma voltage γ0 generated by the amplifier AP0 is output as the gradation voltage VG0 as it is.

[0078] The gamma curve selection ladder resistance circuit GLX2 includes the first to fourth low-voltage side ladder resistances. The first to fourth low-voltage side ladder resistances correspond to, for example, the first to fourth gamma curves gm1 to gm4 in the low-voltage section shown in FIG. 6, which have different voltage value transition forms, and are respectively provided with (n - i) (where i is an integer of 2 or more) taps from which (n - i) voltages along the gamma curve can be generated. Here, the gamma curve selection ladder resistance circuit GLX2 selects one ladder resistance specified by the ladder resistance selection signals e1 to e4 from among the first to fourth low-voltage side ladder resistances.

[0079] Then, the gamma curve selection ladder resistance circuit GLX2 applies the gamma voltage γm to one end of the selected low-voltage side ladder resistance and the gamma voltage γ(m - 1) to the other end. As a result, the gamma curve selection ladder resistance circuit GLX2 outputs the voltages generated at each of the (n - i) taps of the low-voltage side ladder resistance as low-voltage side gradation voltages VGi to VGn having voltage values along the gamma curves gm1, gm2, gm3, or gm4 in the low-voltage section shown in FIG. 6.

[0080] In addition, in the gradation voltage generation circuit 122_1, similar to the gradation voltage generation circuit 122 shown in FIG. 3, the gamma voltage γm generated by the amplifier APm is output as the gradation voltage VGn as it is.

[0081] The common ladder resistance section Lcm corresponds to the gamma curve within the intermediate voltage range shown in Fig. 6. By receiving the gamma voltages γ2 to γ(m-1) output from each of the amplifiers AP2 to AP(m-2) at its respective taps, it outputs the gradation voltages VG(j+1) to VG(i-1) along the gamma curve of the intermediate voltage range.

[0082] Fig. 8 is a circuit diagram showing an example of the internal configuration of the gamma curve selection ladder resistance circuits GLX1 and GLX2.

[0083] The gamma curve selection ladder resistance circuit GLX1 includes amplifiers GPa_1 to GPd_1 with enable terminals, high-voltage side ladder resistance sections La_1 to Ld_1 as the first to fourth ladder resistances, and an output selector OSE1.

[0084] The high-voltage side ladder resistance section La_1 has j taps for outputting j voltages along the first gamma curve gm1 within the high-voltage range shown in Fig. 6. One end of the high-voltage side ladder resistance section La_1 is connected to the output terminal of the amplifier GPa_1, and the gamma voltage γ1 is applied to the other end. The high-voltage side ladder resistance section Lb_1 has j taps for outputting j voltages along the second gamma curve gm2 within the high-voltage range shown in Fig. 6. One end of the high-voltage side ladder resistance section Lb_1 is connected to the output terminal of the amplifier GPb_1, and the gamma voltage γ1 is applied to the other end. The high-voltage side ladder resistance section Lc_1 has j taps for outputting j voltages along the third gamma curve gm3 within the high-voltage range shown in Fig. 6. One end of the high-voltage side ladder resistance section Lc_1 is connected to the output terminal of the amplifier GPc_1, and the gamma voltage γ1 is applied to the other end. The high-voltage side ladder resistance section Ld_1 has j taps for outputting j voltages along the fourth gamma curve gm4 within the high-voltage range shown in Fig. 6. One end of the high-voltage side ladder resistance section Ld_1 is connected to the output terminal of the amplifier GPd_1, and the gamma voltage γ1 is applied to the other end.

[0085] The other ends of these high-voltage side ladder resistance sections La_1 to Ld_1 are connected to one end of the common ladder resistance section Lcm.

[0086] When amplifier GPa_1 receives the ladder resistance selection signal e1 of logic level 1 that selects the first ladder resistance, it becomes enabled. As a result, the amplifier GPa_1 applies the voltage obtained by amplifying the gamma voltage γ0 input to itself to one end of the high-voltage side ladder resistance section La_1. At this time, the high-voltage side ladder resistance section La_1 outputs j voltages a1 to aj having voltage values along the gamma curve gm1 within the high-voltage range shown in FIG. 6 from its j taps. On the other hand, when receiving the ladder resistance selection signal e1 of logic level 0, the amplifier GPa_1 becomes disabled and stops applying voltage to the high-voltage side ladder resistance section La_1.

[0087] When amplifier GPb_1 receives the ladder resistance selection signal e2 of logic level 1 that selects the second ladder resistance, it becomes enabled. As a result, the amplifier GPb_1 applies the voltage obtained by amplifying the gamma voltage γ0 input to itself to one end of the high-voltage side ladder resistance section Lb_1. At this time, the high-voltage side ladder resistance section Lb_1 outputs j voltages b1 to bj having voltage values along the gamma curve gm2 within the high-voltage range shown in FIG. 6 from its j taps. On the other hand, when receiving the ladder resistance selection signal e2 of logic level 0, the amplifier GPb_1 becomes disabled and stops applying voltage to the high-voltage side ladder resistance section Lb_1.

[0088] When amplifier GPc_1 receives the ladder resistance selection signal e3 of logic level 1 that selects the third ladder resistance, it becomes enabled. As a result, the amplifier GPc_1 applies the voltage obtained by amplifying the gamma voltage γ0 input to itself to one end of the high-voltage side ladder resistance section Lc_1. At this time, the high-voltage side ladder resistance section Lc_1 outputs j voltages c1 to cj having voltage values along the gamma curve gm3 within the high-voltage range shown in FIG. 6 from its j taps. On the other hand, when receiving the ladder resistance selection signal e3 of logic level 0, the amplifier GPc_1 becomes disabled and stops applying voltage to the high-voltage side ladder resistance section Lc_1.

[0089] When the amplifier GPd_1 receives the ladder resistor selection signal e4 of logic level 1 that selects the fourth ladder resistor, it becomes enabled. As a result, the amplifier GPd_1 applies the voltage obtained by amplifying the gamma voltage γ0 input to itself to one end of the high-voltage side ladder resistor section Ld_1. At this time, the high-voltage side ladder resistor section Ld_1 outputs j voltages d1 to dj having voltage values along the gamma curve gm4 within the high-voltage range shown in FIG. 6 from its j taps. On the other hand, when the amplifier GPd_1 receives the ladder resistor selection signal e4 of logic level 0, it becomes disabled and stops applying voltage to the high-voltage side ladder resistor section Ld_1.

[0090] The output selector OSE1 receives four sets of voltages a1 to aj, b1 to bj, c1 to cj, and d1 to dj output from each of the high-voltage side ladder resistor sections La_1 to Ld_1 together with the ladder resistor selection signals e1 to e4.

[0091] The output selector OSE1 selects one set of voltage group output from the one high-voltage side ladder resistor indicated by the ladder resistor selection signals e1 to e4 from among the four sets of voltage groups. For example, when the ladder resistor selection signals e1 to e4 indicate the first ladder resistor, the output selector OSE1 selects the voltages a1 to aj from among the four sets of voltages a1 to aj, b1 to bj, c1 to cj, and d1 to dj. Also, when the ladder resistor selection signals e1 to e4 indicate the second ladder resistor, the output selector OSE1 selects the voltages b1 to bj from among the four sets of voltage groups described above.

[0092] Then, the output selector OSE1 outputs the one set of voltage group selected as described above as the gradation voltages VG1 to VGj included in the high-voltage range shown in FIG. 6.

[0093] The γ curve selection ladder resistor circuit GLX2 includes amplifiers GPa_2 to GPd_2 with enable terminals, low-voltage side ladder resistor sections La_2 to Ld_2 as the first to fourth ladder resistors, and an output selector OSE2.

[0094] The low-voltage side ladder resistor section La_2 has j taps for outputting j voltages along the first gamma curve gm1 within the low-voltage range shown in Fig. 6. One end of the low-voltage side ladder resistor section La_2 is connected to the output end of the amplifier GPa_2, and the gamma voltage γ(m - 1) is applied to the other end. The low-voltage side ladder resistor section Lb_2 has j taps for outputting j voltages along the second gamma curve gm2 within the low-voltage range shown in Fig. 6. One end of the low-voltage side ladder resistor section Lb_2 is connected to the output end of the amplifier GPb_2, and the gamma voltage γ(m - 1) is applied to the other end. The low-voltage side ladder resistor section Lc_2 has j taps for outputting j voltages along the third gamma curve gm3 within the low-voltage range shown in Fig. 6. One end of the low-voltage side ladder resistor section Lc_2 is connected to the output end of the amplifier GPc_2, and the gamma voltage γ(m - 1) is applied to the other end. The low-voltage side ladder resistor section Ld_2 has j taps for outputting j voltages along the fourth gamma curve gm4 within the low-voltage range shown in Fig. 6. One end of the low-voltage side ladder resistor section Ld_2 is connected to the output end of the amplifier GPd_2, and the gamma voltage γ(m - 1) is applied to the other end.

[0095] The other ends of these low-voltage side ladder resistor sections La_2 to Ld_2 are connected to the other end of the common ladder resistor section Lcm.

[0096] The amplifier GPa_2 becomes enabled when it receives the ladder resistor selection signal e1 of logic level 1 for selecting the first ladder resistor. Thereby, the amplifier GPa_2 applies the voltage obtained by amplifying the gamma voltage γm input to itself to one end of the low-voltage side ladder resistor section La_2. At this time, the low-voltage side ladder resistor section La_2 outputs j voltages ai to an having voltage values along the gamma curve gm1 within the low-voltage range shown in Fig. 6 from its j taps. On the other hand, when it receives the ladder resistor selection signal e1 of logic level 0, the amplifier GPa_2 becomes disabled and stops applying voltage to the low-voltage side ladder resistor section La_2.

[0097] When the amplifier GPb_2 receives the ladder resistance selection signal e2 of logic level 1 that selects the second ladder resistance, it becomes enabled. As a result, the amplifier GPb_2 applies the voltage obtained by amplifying the gamma voltage γm input to itself to one end of the low-voltage side ladder resistance section Lb_2. At this time, the low-voltage side ladder resistance section Lb_2 outputs j voltages bi~bn having voltage values along the gamma curve gm2 within the low-voltage range shown in FIG. 6 from its j taps. On the other hand, when the ladder resistance selection signal e2 of logic level 0 is received, the amplifier GPb_2 becomes disabled and stops applying voltage to the low-voltage side ladder resistance section Lb_2.

[0098] When the amplifier GPc_2 receives the ladder resistance selection signal e3 of logic level 1 that selects the third ladder resistance, it becomes enabled. As a result, the amplifier GPc_2 applies the voltage obtained by amplifying the gamma voltage γm input to itself to one end of the low-voltage side ladder resistance section Lc_2. At this time, the low-voltage side ladder resistance section Lc_2 outputs j voltages ci~cn having voltage values along the gamma curve gm3 within the low-voltage range shown in FIG. 6 from its j taps. On the other hand, when the ladder resistance selection signal e3 of logic level 0 is received, the amplifier GPc_2 becomes disabled and stops applying voltage to the low-voltage side ladder resistance section Lc_2.

[0099] When the amplifier GPd_2 receives the ladder resistance selection signal e4 of logic level 1 that selects the fourth ladder resistance, it becomes enabled. As a result, the amplifier GPd_2 applies the voltage obtained by amplifying the gamma voltage γm input to itself to one end of the low-voltage side ladder resistance section Ld_2. At this time, the low-voltage side ladder resistance section Ld_2 outputs j voltages di~dn having voltage values along the gamma curve gm4 within the low-voltage range shown in FIG. 6 from its j taps. On the other hand, when the ladder resistance selection signal e4 of logic level 0 is received, the amplifier GPd_2 becomes disabled and stops applying voltage to the low-voltage side ladder resistance section Ld_2.

[0100] The output selector OSE2 receives four sets of voltages ai~an, bi~bn, ci~cn, and di~dn output from each of the low-voltage side ladder resistors La_2~Ld_2 together with the ladder resistor selection signals e1~e4.

[0101] The output selector OSE2 selects one set of voltage groups output from the one low-voltage side ladder resistor indicated by the ladder resistor selection signals e1~e4 from among the four sets of voltage groups. For example, when the ladder resistor selection signals e1~e4 indicate the first ladder resistor, the output selector OSE2 selects the voltages ai~an from among the four sets of voltages ai~an, bi~bn, ci~cn, and di~dn. Also, when the ladder resistor selection signals e1~e4 indicate the second ladder resistor, the output selector OSE2 selects the voltages bi~bn from among the above-mentioned four sets of voltage groups.

[0102] Then, the output selector OSE2 outputs the one set of voltage groups selected as described above as the gradation voltages VGi~VG(n - 1) included in the low-voltage section shown in FIG. 6.

[0103] In addition, in an example shown in FIG. 7, single-ended output type operational amplifiers are used as the amplifiers AP0 and APm, but differential output type operational amplifiers may also be employed.

[0104] FIG. 9 is a circuit diagram showing an excerpt of the internal configurations of each of the amplifiers GPa_1~GPd_1 and GPa_2~GPd_2 shown in FIG. 8 when differential output type operational amplifiers are employed as the amplifiers AP1 and APm.

[0105] Also, in FIG. 8, a differential output type amplifier AP0x is adopted instead of the single-ended output type amplifier AP0. Similar to the amplifier AP0, the gamma voltage VI0 is received at its non-inverting input terminal. The amplifier AP0x outputs a gamma voltage γ0p having a voltage value corresponding to the gamma voltage VI0 from its first output terminal, and supplies the gamma voltage γ0p to each of the amplifiers GPa_1 to GPd_1. Further, the amplifier AP0x outputs a gamma voltage γ0n obtained by inverting the polarity of the gamma voltage γ0p from its second output terminal, and supplies the gamma voltage γ0n to each of the amplifiers GPa_1 to GPd_1.

[0106] Each of the amplifiers GPa_1 to GPd_1 has the same internal configuration, that is, includes a P-channel transistor Q1, an N-channel transistor Q2, and switch elements S1 to S3, similar to each of the amplifiers GPa to GPd shown in FIG. 5.

[0107] Also, since the connection forms and operations of the transistors Q1, Q2, and the switch elements S1 to S3 are the same as those shown in FIG. 5, the description thereof is omitted.

[0108] However, in the configuration shown in FIG. 9, the output node nd0 of the amplifier GPa_1 is connected to one end of the high-voltage side ladder resistor section La_1, and the output node nd0 of the amplifier GPb_1 is connected to one end of the high-voltage side ladder resistor section Lb_1. Also, the output node nd0 of the amplifier GPc_1 is connected to one end of the high-voltage side ladder resistor section Lc_1, and the output node nd0 of the amplifier GPd_1 is connected to one end of the high-voltage side ladder resistor section Ld_1. Further, in the configuration shown in FIG. 9, the voltages of the respective output nodes nd0 are supplied as feedback voltages to the inverting input terminal of the amplifier AP0X via the switch elements S3 of the amplifiers GPa_1 to GPd_1.

[0109] In this way, in the gradation voltage generation circuit 122_1, gamma curve adjustment is performed only on the gradation voltages included in the low voltage section and the high voltage section shown in FIG. 6. As a result, compared with the gradation voltage generation circuit 122 shown in FIGS. 3 and 4, in which the selection circuits SE1 to SE(m-1) are required to select the ladder resistors to which the gamma voltage is applied, the circuit scale of the selection circuits (GLX1, GLX2) and the ladder resistors (La_1 to Ld_1, Lcm, La_2 to Ld_2) can be reduced.

[0110] In addition, in the gradation voltage generation circuit shown in FIG. 4 or FIG. 7, the circuit configuration is shown when the required gamma characteristics are four systems (gm1 to gm4), but it may also correspond to two systems or five or more systems of gamma characteristics. That is, for the number of required gamma characteristics, the corresponding number of ladder resistors and selection circuits for each gamma characteristic may be provided.

[0111] Also, in the above embodiment, as the selection circuit of the gradation voltage generation circuit, enabled amplifiers such as the amplifiers GPa to GPd shown in FIG. 4, the amplifiers GPa_1 to GPd_1 shown in FIG. 8, and the amplifiers GPa_2 to GPd_2 are used. However, an analog demultiplexer may be employed instead of such an amplifier. For example, regarding the amplifiers GPa to GPd included in each of the selection circuits SE1 to SE(m-1) shown in FIG. 4, these can be replaced with one 1-to-4 demultiplexer.

[0112] In short, as the gradation voltage generation circuit according to the present invention, it may be any one including the following first to yth (y is an integer of 2 or more) ladder resistors, a selection circuit, and an output selector.

[0113] The first to y-th ladder resistors (LDa to LDd, La_1 to Ld_1, Lcm, La_2 to Ld_2) each correspond to one of the first to y-th gamma characteristics (e.g., gm1 to gm4), and each generate a plurality of voltages having voltage values along the one gamma characteristic. The selection circuits (GPa to GPd, GPa_1 to GPd_1, GPa_2 to GPd_2) receive ladder resistor selection signals (e.g., e1 to e4) that specify one of the first to y-th ladder resistors, and apply a plurality of gamma voltages [γ1 to γ(m - 1), γ0, and γ1] to the one ladder resistor specified by the ladder resistor selection signal among the first to y-th ladder resistors. The output selectors (OSE, OSE1, OSE2) output the plurality of voltages generated by the one ladder resistor specified by the ladder resistor selection signal as a plurality of gradation voltages [VG1 to VG(n - 1)].

Explanation of Signs

[0114] 12 Data driver 100 Display device 122, 122_1 Gradation voltage generation circuit AP0 to APm Amplifiers GLX, GLX1 - 2 Gamma curve selection ladder resistor circuit SE1 to SE(m - 1) Selection circuits OSE, OSE1 - 2 Output selectors LDa to LDd, La_1 to Ld_1, La_2 to Ld_2 Ladder resistors, Lcm Common ladder resistor

Claims

1. First to y-th ladder resistors (where y is an integer of 2 or more) each generating a plurality of voltages having voltage values along the first to y-th gamma characteristics, a selection circuit that receives a ladder resistor selection signal specifying one of the first to y-th ladder resistors and applies a plurality of gamma voltages to the one ladder resistor specified by the ladder resistor selection signal among the first to y-th ladder resistors, and an output selector that outputs, as a plurality of gradation voltages, the plurality of voltages generated by the one ladder resistor specified by the ladder resistor selection signal. A gradation voltage generation circuit characterized by comprising:

2. The gradation voltage generation circuit includes first to m-th (where m is an integer of 2 or more) gamma amplifiers each outputting first to m-th gamma voltages, each of the first to y-th ladder resistors receives the first gamma voltage at one end and the m-th gamma voltage at the other end, The selection circuit applies each of the first to (m - 1)-th gamma voltages among the first to m-th gamma voltages to the one ladder resistor specified by the ladder resistor selection signal. The gradation voltage generation circuit according to claim 1.

3. The gradation voltage generation circuit includes first to m-th (where m is an integer of 2 or more) gamma amplifiers each outputting first to m-th gamma voltages, each of the first to y-th ladder resistors receives the first to (m - 1)-th gamma voltages among the first to m-th gamma voltages, The selection circuit applies the first gamma voltage to one end of the one ladder resistor specified by the ladder resistor selection signal and applies the m-th gamma voltage to the other end of the one ladder resistor. The gradation voltage generation circuit according to claim 1.

4. The first gamma voltage has the highest voltage value among the first to m-th gamma voltages, the m-th gamma voltage has the lowest voltage value among the first to m-th gamma voltages, The first to y-th ladder resistors are a single common ladder resistor section that receives the first to (m - 1)-th gamma voltages, first to r-th high-voltage side ladder resistor sections each having one end connected to one end of the common ladder resistor section and the first gamma voltage applied to the other end by the selection circuit, A first to an r-th low-voltage side ladder resistor, each having one end connected to the other end of the common ladder resistor and having the m-th gamma voltage applied to the other end thereof by the selection circuit. The gradation voltage generation circuit according to claim 3, characterized in that it consists of

5. A display driver that receives a video signal, converts each of the pixel data pieces representing the luminance level of each pixel based on the video signal into a gradation voltage having a voltage value corresponding to each of the luminance levels, and supplies a drive signal based on the gradation voltage to a data line of a display panel, A gradation voltage generation circuit that generates a plurality of gradation voltages having different voltage values from each other; A decoder unit that, for each of the pixel data pieces, selects and outputs a gradation voltage corresponding to the luminance level indicated by the pixel data piece from among the plurality of gradation voltages; An output amplifier unit that generates the drive signal by amplifying the gradation voltage output from the decoder unit and supplies the drive signal to the data line of the display panel, and includes The gradation voltage generation circuit includes First to y-th ladder resistors (y is an integer of 2 or more), each generating a plurality of voltages having voltage values along first to y-th gamma characteristics; A selection circuit that receives a ladder resistor selection signal designating one of the first to y-th ladder resistors and applies a plurality of gamma voltages to the one ladder resistor designated by the ladder resistor selection signal among the first to y-th ladder resistors; An output selector that outputs a plurality of voltages generated by the one ladder resistor designated by the ladder resistor selection signal as a plurality of gradation voltages. The display driver is characterized by having

6. A display panel including a plurality of data lines to which a plurality of display cells are respectively connected; A display device including a display driver that receives a video signal, converts each of the pixel data pieces representing the luminance level of each pixel based on the video signal into a gradation voltage having a voltage value corresponding to each of the luminance levels, and supplies a drive signal based on the gradation voltage to a data line of the display panel, The display driver includes A gradation voltage generation circuit that generates a plurality of gradation voltages having different voltage values from each other; A decoder unit that, for each of the pixel data pieces, selects and outputs a gradation voltage corresponding to the luminance level indicated by the pixel data piece from among the plurality of gradation voltages; An output amplifier unit that generates the drive signal by amplifying the gradation voltage output from the decoder unit and supplies the drive signal to the data line of the display panel. The gradation voltage generation circuit includes: First to y-th ladder resistors (where y is an integer of 2 or more) each generating a plurality of voltages having voltage values along gamma characteristics of first to y-th; A selection circuit that receives a ladder resistor selection signal designating one of the first to y-th ladder resistors and applies a plurality of gamma voltages to the one ladder resistor designated by the ladder resistor selection signal among the first to y-th ladder resistors; An output selector that outputs a plurality of voltages generated by the one ladder resistor designated by the ladder resistor selection signal as a plurality of gradation voltages, characterized in that the display device has the above components.

Images