Gate signal generation circuit and display device including the same

Abstract

To compensate for transistor degradation per frame, reduce output deviations between stages, and suppress defects caused by degradation in a specific stage.SOLUTION: A display device of one embodiment includes a shift register with a plurality of stages. An Nth stage among the shift register stages includes a signal generator which operates on the basis of an Nth clock signal applied via an Nth clock signal line, a (N-4)th carry signal output via a (N-4)th stage carrier terminal, a (N+4)th gate signal output via a (N+4)th stage output terminal, a (N+4)th carry signal output from a (n+4)th stage carrier terminal, a first low voltage applied via a first low voltage line, and a second low voltage applied via a second low voltage line, and a compensation circuit which operates on the basis of signals output from stages different from the potentials of a Q-node and a QB-node included in the signal generator and including a transistor which forms a compensation voltage at the QB-node to compensate for deterioration of a transistor connected to the QB-node.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a gate signal generation circuit and a display device including the same.

Background Art

[0002] With the development of information technology, the market for display devices, which are the connection media between users and information, has been growing. As a result, the use of display devices such as light emitting display devices (LED), quantum dot display devices (QDD), and liquid crystal display devices (LCD) has been increasing.

[0003] The above-described display device includes a display panel including sub-pixels, a driving unit that outputs a driving signal for driving the display panel, and a power supply unit that generates a power supply to be supplied to the display panel or the driving unit.

[0004] In the above-described display device, when a driving signal, such as a scan signal and a data signal, is supplied to the sub-pixels formed on the display panel, the selected sub-pixels can display an image by transmitting light or directly emitting light.

Summary of the Invention

Problems to be Solved by the Invention

[0005] This specification compensates for the deterioration of transistors for each frame to improve problems due to threshold voltage shift, reduces the output deviation between stages, and prevents the phenomenon in which defects due to deterioration are transmitted to a specific stage.

Means for Solving the Problems

[0006] This specification includes a display panel for displaying an image, and a shift register including a stage connected to the display panel and having an output terminal for outputting a gate signal and a carry terminal for outputting a carry signal. Among the stages, the Nth stage is based on the Nth clock signal applied via the Nth clock signal line, the (N - 4)th carry signal output via the carry terminal of the (N - 4)th stage, the (N + 4)th gate signal output via the output terminal of the (N + 4)th stage, the (N + 4)th carry signal output from the carry terminal of the (N + 4)th stage, the first low voltage applied via the first low voltage line, and the second low voltage applied via the second low voltage line. It includes a signal generation unit that operates, and a compensation circuit unit that operates based on signals output from stages having different potentials from the potentials of the Q node and the QB node included in the signal generation unit and includes a transistor that forms a compensation voltage at the QB node to compensate for deterioration of the transistor connected to the QB node. A display device can be provided.

[0007] The compensation circuit unit can form a compensation voltage at the QB node based on at least one of the voltages of the potential of the Q node and the QB node, the (N + 4)th gate signal output via the output terminal of the (N + 4)th stage, and the (N + 4)th carry signal output via the carry terminal of the (N + 4)th stage.

[0008] The compensation circuit unit includes a first compensation transistor turned on based on the potential of the Q node, a second compensation transistor turned on based on the (N + 4)th carry signal, and a third compensation transistor turned on based on the potential of the QB node, and the compensation voltage can be formed corresponding to the sum of the potential of the QB node and the threshold voltage of the third compensation transistor.

[0009] The compensation circuit section may include a first compensation transistor having a gate electrode connected to the Q node, a first electrode connected to the output terminal of the (N + 4)-th stage, and a second electrode connected to the QB node; a second compensation transistor having a gate electrode connected to the carry terminal of the (N + 4)-th stage, a first electrode connected to the second electrode of the first compensation transistor and the QB node; and a third compensation transistor having a gate electrode connected to the QB node, a first electrode connected to the second electrode of the second compensation transistor, and a second electrode connected to a second low voltage line for applying a second low voltage lower than the first low voltage for constituting the carry signal.

[0010] The compensation circuit section may include a first compensation transistor having a gate electrode connected to the Q node, a first electrode connected to the carry terminal of the (N + 4)-th stage, and a second electrode connected to the QB node; a second compensation transistor having a gate electrode connected to the carry terminal of the (N + 4)-th stage, a first electrode connected to the second electrode of the first compensation transistor and the QB node; and a third compensation transistor having a gate electrode connected to the QB node, a first electrode connected to the second electrode of the second compensation transistor, and a second electrode connected to a second low voltage line for applying a second low voltage lower than the first low voltage for constituting the carry signal.

[0011] The compensation circuit section may include a first compensation transistor having a gate electrode connected to the Q node included in the signal generation section, a first electrode connected to the output terminal of the (N + 4)-th stage, and a second electrode connected to the QB node; a second compensation transistor having a gate electrode connected to the output terminal of the (N + 4)-th stage, a first electrode connected to the second electrode of the first compensation transistor and the QB node; and a third compensation transistor having a gate electrode connected to the QB node, a first electrode connected to the second electrode of the second compensation transistor, and a second electrode connected to a second low voltage line for applying a second low voltage lower than the first low voltage for constituting the carry signal.

[0012] In another aspect, this specification discloses a shift register including an output terminal for outputting a gate signal and a stage having a carry terminal for outputting a carry signal. Among the stages, the Nth stage operates based on an Nth clock signal applied via an Nth clock signal line, an (N - 4)th carry signal output via the carry terminal of the (N - 4)th stage, an (N + 4)th gate signal output via the output terminal of the (N + 4)th stage, an (N + 4)th carry signal output from the carry terminal of the (N + 4)th stage, a first low voltage applied via a first low voltage line, and a second low voltage applied via a second low voltage line. The shift register also includes a gate signal generation circuit including a signal generation unit and a compensation circuit unit. The signal generation unit operates based on signals output from stages having different potentials from the potentials of the Q node and the QB node included in the signal generation unit. The compensation circuit unit includes a transistor for forming a compensation voltage at the QB node to compensate for deterioration of the transistor connected to the QB node.

[0013] The compensation circuit unit may include a first compensation transistor having a gate electrode connected to the Q node, a first electrode connected to the output terminal of the (N + 4)th stage, and a second electrode connected to the QB node; a second compensation transistor having a gate electrode connected to the carry terminal of the (N + 4)th stage, a first electrode connected to the second electrode of the first compensation transistor and the QB node; and a third compensation transistor having a gate electrode connected to the QB node, a first electrode connected to the second electrode of the second compensation transistor, and a second electrode connected to a second low voltage line for applying a second low voltage lower than the first low voltage for forming the carry signal.

[0014] The compensation circuit unit may include a first compensation transistor having a gate electrode connected to the Q node, a first electrode connected to the carry terminal of the (N + 4)-th stage, and a second electrode connected to the QB node; a second compensation transistor having a gate electrode connected to the carry terminal of the (N + 4)-th stage, a first electrode connected to the second electrode of the first compensation transistor and the QB node; and a third compensation transistor having a gate electrode connected to the QB node, a first electrode connected to the second electrode of the second compensation transistor, and a second electrode connected to a second low voltage line for applying a second low voltage lower than a first low voltage for constituting the carry signal.

[0015] The compensation circuit unit may include a first compensation transistor having a gate electrode connected to the Q node included in the signal generation unit, a first electrode connected to the output terminal of the (N + 4)-th stage, and a second electrode connected to the QB node; a second compensation transistor having a gate electrode connected to the output terminal of the (N + 4)-th stage, a first electrode connected to the second electrode of the first compensation transistor and the QB node; and a third compensation transistor having a gate electrode connected to the QB node, a first electrode connected to the second electrode of the second compensation transistor, and a second electrode connected to a second low voltage line for applying a second low voltage lower than a first low voltage for constituting the carry signal.

Advantages of the Invention

[0016] This specification has the effect of being able to compensate for deterioration of transistors for each frame and improve problems caused by threshold voltage shift (e.g., multi-signal output due to ripple of T6 every time a clock signal is generated). Further, this specification has the effect of being able to compensate for deterioration of transistors for each frame and reduce output deviation between stages. Further, this specification has the effect of being able to prevent a phenomenon in which a defect due to deterioration is transmitted to a specific stage by performing deterioration compensation based on a signal output from a subordinately connected stage.

Brief Description of the Drawings

[0017]

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Embodiments for Carrying out the Invention

[0018] The display device according to this specification can be embodied in a television, a video player, a personal computer (PC), a home theater, automotive electrical equipment, a smartphone, etc., and is not limited thereto. The display device according to this specification can be embodied in a light emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, for the sake of convenience of explanation below, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is taken as an example.

[0019] Note that the thin film transistor described below can be embodied in a form in which an n-type thin film transistor, a p-type thin film transistor, or both n-type and p-type exist together. A thin film transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the thin film transistor, carriers start to flow from the source. The drain is an electrode through which carriers exit the thin film transistor to the outside. That is, the flow of carriers in the thin film transistor is from the source to the drain.

[0020] In the case of a p-type thin-film transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes flow from the source to the drain. In a p-type thin-film transistor, since holes flow from the source to the drain, the current flows from the source to the drain. In contrast, in the case of an n-type thin-film transistor, since the carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons flow from the source to the drain. In an n-type thin-film transistor, since electrons flow from the source to the drain, the direction of the current flows from the drain to the source. However, the source and drain of the thin-film transistor can be changed according to the applied voltage. Reflecting this, in the following description, either the source or the drain will be described as the first electrode, and the other of the source and the drain will be described as the second electrode.

[0021] FIG. 1 is a block diagram schematically showing a light-emitting display device, and FIG. 2 is a block diagram schematically showing the sub-pixels shown in FIG. 1.

[0022] As shown in FIGS. 1 and 2, the light-emitting display device may include a timing control unit 120, a gate driving unit 130, a data driving unit 140, a display panel 150, a power supply unit 180, and the like.

[0023] The video supply unit (set or host system) 110 can output various drive signals together with the video data signal supplied from the outside or the video data signal (image data signal) stored in the internal memory. The video supply unit 110 can supply the data signal and various drive signals to the timing control unit 120.

[0024] The timing control unit 120 can output a gate timing control signal GDC for controlling the operation timing of the gate driving unit 130, a data timing control signal DDC for controlling the operation timing of the data driving unit 140, and various synchronization signals (such as VSYNC which is a vertical synchronization signal and HSYNC which is a horizontal synchronization signal). The timing control unit 120 can supply the data signal DATA supplied from the video supply unit 110 to the data driving unit 140 together with the data timing control signal DDC. The timing control unit 120 may be formed in the form of an IC (Integrated Circuit) and mounted on a printed circuit board, but is not limited thereto.

[0025] The gate driving unit 130 can output a gate signal (or gate voltage) in response to the gate timing control signal GDC and the like supplied from the timing control unit 120. The gate driving unit 130 can supply the gate signal to the sub-pixels included in the display panel 150 via the gate lines GL1 to GLm. The gate driving unit 130 may be formed in the form of an IC, but may also be directly formed on the display panel 150 by the gate in panel method, but is not limited thereto.

[0026] The data driving unit 140 can sample and latch the data signal DATA in response to the data timing control signal DDC and the like supplied from the timing control unit 120, and convert the digital-form data signal into an analog-form data voltage based on the gamma reference voltage and output it. The data driving unit 140 can supply the data voltage to the sub-pixels included in the display panel 150 via the data lines DL1 to DLn. The data driving unit 140 may be formed in the form of an IC and mounted on the display panel 150, or may be mounted on a printed circuit board, but is not limited thereto.

[0027] The power supply unit 180 can generate a high-potential voltage and a low-potential voltage based on an externally supplied external input voltage and output them via a first power supply line EVDD and a second power supply line EVSS. The power supply unit 180 can generate and output not only the high-potential voltage and the low-potential voltage, but also voltages necessary for driving the gate driving unit 130 (for example, gate voltages including a gate high voltage and a gate low voltage) and voltages necessary for driving the data driving unit 140 (drain voltages including a drain voltage and a half-drain voltage).

[0028] The display panel 150 can display an image (picture) corresponding to a driving signal including a gate signal and a data voltage, a driving voltage including a high-potential voltage and a low-potential voltage, and the like. The sub-pixels of the display panel 150 emit light directly.

[0029] The display panel 150 can be manufactured based on a rigid or ductile substrate such as glass, silicon, polyimide, etc. And the sub-pixels that emit light may consist of pixels including red, green, blue, or pixels including red, green, blue, white.

[0030] For example, one sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power supply line EVDD, and a second power supply line EVSS, and can include a pixel circuit composed of a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode, etc. Since the sub-pixel SP used in the light-emitting display device emits light directly, the circuit configuration is complicated. Also, not only the organic light-emitting diode that emits light, but also compensation circuits for compensating for deterioration of driving transistors that supply the driving current necessary for driving the organic light-emitting diode are diverse. Therefore, please refer to the fact that the sub-pixel SP is simply shown in the form of a block.

[0031] In the above description, the timing control unit 120, the gate driving unit 130, the data driving unit 140, etc. were described as if they were each separate configurations. However, depending on the implementation method of the light-emitting display device, one or more of the timing control unit 120, the gate driving unit 130, and the data driving unit 140 can be integrated into one IC.

[0032] FIG. 3 and FIG. 4 are diagrams for explaining the configuration of a gate panel type gate driving unit, and FIG. 5 is a diagram showing an arrangement example of the gate panel type gate driving unit.

[0033] As shown in FIG. 3, the gate panel type gate driving unit 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a clock signal Clks, a start signal Vst, etc. based on the signals and voltages output from the timing control unit 120 and the power supply unit 180. The shift register 131 operates based on the clock signal Clks and the start signal Vst output from the level shifter 135, etc., and may output gate signals Gout[1] to Gout[m].

[0034] As shown in FIGS. 3 and 4, unlike the shift register 131, the level shifter 135 may be independently formed in an IC form or may be included inside the power supply unit 180. However, this is only an example and is not limited thereto.

[0035] As shown in FIG. 5, the first and second shift registers 131a and 131b that output gate signals in the gate panel type gate driving unit may be arranged in the non-display area NA of the display panel 150. The first and second shift registers 131a and 131b may be formed in a thin film shape on the display panel 150 by the gate panel method. The first and second shift registers 131a and 131b are shown as an example of being respectively arranged in the left and right non-display areas NA of the display panel 150, but are not limited thereto.

[0036] FIG. 6 is a block diagram showing a shift register according to the first embodiment, FIG. 7 is a block diagram showing a connection structure of stages included in the shift register, and FIG. 8 is a block diagram showing an Nth stage included in the shift register. FIG. 9 is a circuit diagram showing a compensation circuit unit included in the Nth stage, and FIG. 10 is a waveform diagram for explaining the operation of the compensation circuit unit and the deterioration compensation of the QB node associated therewith.

[0037] As shown in FIG. 6, the shift register 131 according to the first embodiment can be connected to a clock signal line CLKS, a start signal line VST, a high voltage line VGH, a first low voltage line VGL, and a second low voltage line VSS, respectively.

[0038] The shift register 131 may include a plurality of stages STG1 to STGm as a configuration for outputting gate signals Gout[1] to Gout[m]. The shift register 131 can output the gate signals Gout[1] to Gout[m] in various forms according to the connection structure between the plurality of stages STG1 to STGm and the clock signal line CLKS. Note that the clock signal line CLKS is shown as a single thick line, and the connection relationship between the plurality of stages STG1 to STGm and the clock signal line CLKS is not shown.

[0039] The plurality of stages STG1 to STGm can sequentially (in reverse order or non-sequentially) output the gate signals Gout[1] to Gout[m] via gate lines GL1 to GLm. For example, the plurality of stages STG1 to STGm can start outputting the first gate signal Gout[1] via the first gate line GL1 connected to the first stage STG1, and output the M-th gate signal Gout[m] via the M-th gate line GLm connected to the M-th stage STGm, thereby ending the output timing of one frame.

[0040] On the other hand, although not shown, the plurality of stages STG1 to STGm may include a dummy stage connected to the front end of the first stage STG1 and the rear end of the M-th stage STGm.

[0041] As shown in FIG. 7, according to the first embodiment, the plurality of stages STG1 to STGm may have a dependent connection structure. The Nth stage STGN may operate based on the signal output from the (N - 4)th stage STGN-4 (the stage located four stages before the Nth stage) and the signal output from the (N + 4)th stage (STGN+4) (the stage located four stages after the Nth stage). For this purpose, the Nth stage STGN may have a connection structure connected to the output terminal OUT[N - 4] of the (N - 4)th stage STGN-4 and the output terminal OUT[N + 4] of the (N + 4)th stage STGN+4.

[0042] According to the first embodiment, the plurality of stages, STGN, STGN+4 may each include a compensation circuit section NC. The compensation circuit section NC may serve to compensate for the degradation of at least one of the nodes (or transistors connected to the nodes) included in the plurality of stages STGN-4, STGN, STGN+4. The explanation regarding this will be dealt with below. Hereinafter, the compensation circuit section included in the first embodiment will be described by taking the Nth stage (any stage), which is one of the plurality of stages STG1 to STGm, as an example.

[0043] As shown in FIG. 8, according to the first embodiment, the Nth stage STGN may include a signal generation section SC and a compensation circuit section NC. The signal generation section SC may output an Nth carry signal via the Nth carry terminal CRY[N] and may output an Nth gate signal via the Nth output terminal OUT[N]. The compensation circuit section NC may compensate for the degradation of the QB node QBN (or the transistor connected to the QB node) included in the signal generation section SC.

[0044] The Nth stage STGN may be connected to the Nth clock signal line CLK[N], the carry terminal CRY[N - 4] of the (N - 4)th stage, the output terminal OUT[N + 4] of the (N + 4)th stage, the carry terminal CRY[N + 4] of the (N + 4)th stage, the first low voltage line VGL, and the second low voltage line VSS.

[0045] The Nth stage STGN can operate based on the Nth clock signal applied via the Nth clock signal line CLK[N], the (N - 4)th carry signal output via the carry terminal CRY[N - 4] of the (N - 4)th stage, the (N + 4)th gate signal output via the output terminal OUT[N + 4] of the (N + 4)th stage, the (N + 4)th carry signal output via the carry terminal CRY[N + 4] of the (N + 4)th stage, the first low voltage applied via the first low voltage line VGL, and the second low voltage applied via the second low voltage line VSS.

[0046] The first low voltage applied via the first low voltage line VGL and the second low voltage applied via the second low voltage line VSS may have a relationship of "the first low voltage > the second low voltage". For example, the first low voltage applied via the first low voltage line VGL may be set to -12V to -14V, and the second low voltage applied via the second low voltage line VSS may be set to -16V.

[0047] As shown in FIGS. 8 to 10, according to the first embodiment, the compensation circuit unit NC included in the Nth stage STGN may include a first compensation transistor TS1, a second compensation transistor TS2, and a third compensation transistor TS3.

[0048] The first compensation transistor TS1 has its gate electrode connected to the Q node QN, its first electrode connected to the output terminal OUT[N + 4] of the (N + 4)th stage, and can connect its second electrode to the first electrode of the second compensation transistor TS2, the gate electrode of the third compensation transistor TS3, and the QB node QBN. The first compensation transistor TS1 is turned on based on the potential Qn of the Q node QN and outputs the (N + 4)th gate signal output via the output terminal OUT[N + 4] of the (N + 4)th stage, and can transmit it to the QB node (QBN).

[0049] The second compensation transistor TS2 has its gate electrode connected to the carry terminal CRY[N+4] of the N+4th stage, its first electrode connected to the second electrode of the first compensation transistor TS1, the gate electrode of the third compensation transistor TS3, and the QB node QBN, and its second electrode connected to the first electrode of the third compensation transistor TS3. The second compensation transistor TS2 turns on based on the N+4th carry signal output via the carry terminal CRY[N+4] of the N+4th stage, and can connect the second electrode of the first compensation transistor TS1 and the first electrode of the third compensation transistor TS3.

[0050] The third compensation transistor TS3 has its gate electrode connected to the QB node QBN, its first electrode connected to the second electrode of the second compensation transistor TS2, and its second electrode connected to the second low voltage line VSS. The third compensation transistor TS3 is turned on based on the potential Qbn of the QB node QBN, and can transmit the second low voltage applied via the second low voltage line VSS to the second compensation transistor TS2. The compensation circuit section NC can operate as follows for the degradation compensation of the QB node (or the transistor connected to the QB node).

[0051] During the compensation period, the QB node QBN can be charged by the N+4th gate signal Gout[n+4] applied via the first compensation transistor TS1 turned on based on the potential Qn of the Q node QN. During the compensation period, the second compensation transistor TS2 turns on based on the N+4th carry signal, and the third compensation transistor TS3 can be turned on by the N+4th gate signal Gout[n+4] charged to the QB node QBN.

[0052] When the second compensation transistor TS2 and the third compensation transistor TS3 are turned on, the potential Qbn of the QB node QBN can be discharged via the second low voltage line VSS excluding the threshold voltage of the third compensation transistor TS3. Thereby, the potential Qbn of the QB node QBN can be determined as "Vss+Vth_TS3". Here, Vss corresponds to the second low voltage, and Vth_TS3 can correspond to the threshold voltage of the third compensation transistor.

[0053] According to the operation of the compensation circuit unit NC, the potential Qbn of the QB node QBN may determine and form a compensation voltage at "Vss + Vth_TS3", and thus at least one of the transistors connected to the QB node QBN may perform degradation compensation based on the compensation voltage. The description regarding the degradation compensation by the operation of the compensation circuit unit NC will be described in more detail in the second embodiment described below.

[0054] FIG. 11 is a circuit configuration diagram of the Nth stage according to the second embodiment, FIGS. 12 and 13 are drive waveform diagrams of the Nth stage according to the second embodiment, and FIGS. 14 and 15 are simulation results of the gate drive unit according to the second embodiment.

[0055] As shown in FIG. 11, the Nth stage STGN according to the second embodiment may include a signal generation unit SC that outputs an Nth carry signal via an Nth carry terminal CRY[N] and outputs an Nth gate signal via an Nth output terminal OUT[N], and a compensation circuit unit NC that compensates for degradation of the QB node QBN (or a transistor connected to the QB node) included in the signal generation unit SC.

[0056] According to the second embodiment, the signal generation unit SC may include a first transistor T1, a second transistor T5C, a third transistor T3, a fourth transistor T3N, a fifth transistor T3O, a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6C, a second pull-down transistor T7C, a first capacitor CC, and a second capacitor CB.

[0057] The gate electrode and the first electrode of the first transistor T1 may be connected to the carry terminal CRY[N - 4] (or the start signal line) of the (N - 4)th stage, and the second electrode may be connected to the Q node QN. The first transistor T1 may turn on based on the (N - 4)th carry signal output via the carry terminal CRY[N - 4] (or the start signal line) of the (N - 4)th stage and transmit the (N - 4)th carry signal to the Q node QN.

[0058] The second transistor T5C has its gate electrode connected to the carry terminal CRY[N-4] (or the start signal line) of the N-4th stage, its first electrode connected to the QB node QBN, and its second electrode can be connected to the second low voltage line VSS. The second transistor T5C is turned on based on the N-4th carry signal output via the carry terminal CRY[N-4] (or the start signal line) of the N-4th stage, and can transmit a second low voltage to the QB node QBN.

[0059] The third transistor T3 has its gate electrode connected to the QB node QBN, its first electrode connected to the Q node QN, and its second electrode connected to the second low voltage line VSS. The third transistor T3 is turned on based on the potential of the QB node QBN, and can transmit a second low voltage to the Q node QN.

[0060] The fourth transistor T3N has its gate electrode connected to the carry terminal CRY[N+4] of the N+4th stage, its first electrode connected to the Q node QN, and its second electrode can be connected to the second low voltage line VSS. The fourth transistor T3N is turned on based on the N+4th carry signal, and can transmit a second low voltage to the Q node QN.

[0061] The fifth transistor T3O has its gate electrode connected to the carry terminal CRY[N+4] of the N+4th stage, its first electrode connected to the Nth output terminal OUT[N], and its second electrode can be connected to the first low voltage line VGL. The fifth transistor T3O is turned on based on the N+4th carry signal, and can transmit a first low voltage to the Nth output terminal OUT[N].

[0062] The first pull-up transistor T6 has its gate electrode connected to the Q node QN, its first electrode connected to the N-th clock signal line CLK[N], and its second electrode connectable to the N-th output terminal OUT[N]. The first pull-up transistor T6 is turned on based on the potential of the Q node QN and transmits the N-th clock signal to the N-th output terminal OUT[N]. When the first pull-up transistor T6 is turned on, a high-voltage gate signal is output via the N-th output terminal OUT[N] of the N-th stage STGN.

[0063] The first pull-down transistor T7 has its gate electrode connected to the QB node QBN, its first electrode connected to the N-th output terminal OUT[N], and its second electrode connected to the first low-voltage line VGL. The first pull-down transistor T7 is turned on based on the potential of the QB node QBN and transmits the first low voltage to the N-th output terminal OUT[N]. When the first pull-down transistor T7 is turned on, a low-voltage gate signal is output via the N-th output terminal OUT[N] of the N-th stage STGN.

[0064] The second pull-up transistor T6C has its gate electrode connected to the Q node QN, its first electrode connected to the N-th clock signal line CLK[N], and its second electrode connectable to the N-th carry terminal CRY[N]. The second pull-up transistor T6C can be turned on based on the potential of the Q node QN and transmit the N-th clock signal to the N-th carry terminal CRY[N]. When the second pull-up transistor T6C is turned on, a high-voltage carry signal is output via the N-th carry terminal CRY[N] of the N-th stage STGN.

[0065] The second pull-down transistor T7C may have its gate electrode connected to the QB node QBN, its first electrode connected to the Nth carrier terminal CRY[N], and its second electrode connected to the second low voltage line VSS. The second pull-down transistor T7C turns on based on the potential of the QB node QBN and transmits the second low voltage to the Nth carrier terminal CRY[N]. When the second pull-down transistor T7C is turned on, a low-voltage carrier signal is output via the Nth carrier terminal CRY[N] of the Nth stage STGN.

[0066] The first capacitor CC may have its first electrode connected to the Nth clock signal line CLK[N], and its second electrode connected to the second electrode of the first compensation transistor TS1, the first electrode of the second compensation transistor TS2, and the QB node QBN. The first capacitor CC may serve to stably maintain the charging state of the QB node QBN corresponding to the Nth clock signal when the Q node QN is in a discharged state. As a result, the QB node QBN is formed in a floating state, but may couple and charge and discharge each time the Nth clock signal is applied by the first capacitor CC.

[0067] The second capacitor CB may have its first electrode connected to the Q node QN and the gate electrode of the first pull-up transistor T6, and its second electrode connected to the Nth output terminal OUT[N]. The second capacitor CB may function to bootstrap the Q node QN so that a stable output is provided from the Nth output terminal OUT[N].

[0068] According to the second embodiment, the compensation circuit unit NC may include a first compensation transistor TS1, a second compensation transistor TS2, and a third compensation transistor TS3.

[0069] The first compensation transistor TS1 has its gate electrode connected to the Q node QN, its first electrode connected to the output terminal OUT[N+4] of the (N+4)-th stage, and can connect its second electrode to the second electrode of the first capacitor CC, the first electrode of the second compensation transistor TS2, the gate electrode of the third compensation transistor TS3, and the QB node QBN. The first compensation transistor TS1 is turned on based on the potential of the Q node QN and may pass the (N+4)-th gate signal output via the output terminal OUT[N+4] of the (N+4)-th stage to the QB node QBN.

[0070] The second compensation transistor TS2 has its gate electrode connected to the carry terminal CRY[N+4] of the (N+4)-th stage, its first electrode connected to the second electrode of the first capacitor CC, the second electrode of the first compensation transistor TS1, the gate electrode of the third compensation transistor TS3, and the QB node QBN, and its second electrode connected to the first electrode of the third compensation transistor TS3. The second compensation transistor TS2 is turned on based on the (N+4)-th carry signal output via the carry terminal CRY[N+4] of the (N+4)-th stage and may connect the second electrode of the first compensation transistor TS1 and the first electrode of the third compensation transistor TS3. The third compensation transistor TS3 has its gate electrode connected to the QB node QBN, its first electrode connected to the second electrode of the second compensation transistor TS2, and its second electrode connected to the second low voltage line VSS. The third compensation transistor TS3 is turned on based on the potential of the QB node QBN and may transmit the second low voltage applied via the second low voltage line VSS to the second compensation transistor TS2.

[0071] As shown in FIGS. 6, 11, and 12, the shift register 131 implemented based on the Nth stage STGN according to the second embodiment can operate based on an 8-phase clock signal Clk[n-4] to Clk[n+3] in which 4H periods are superimposed. And any Nth stage STGN of the stages STG1 to STGm included in the shift register 131 can operate based on the N clock signal Clk[n] among the clock signals Clk[n-4] to Clk[n+3]. Here, the clock signals Clk[n-4] to Clk[n+3] can be composed of the levels of the high voltage Vgh and the second low voltage Vss.

[0072] When the potential Qn is charged to the Q node QN, the Nth stage STGN can output the Nth gate signal Gout[n] of the high voltage Vgh and the Nth carry signal Cry[n] of the high voltage Vgh. When the potential Qbn is charged to the QB node QBN, the Nth stage STGN can output the Nth gate signal Gout[n] of the first low voltage Vgl and the Nth carry signal Cry[n] of the second low voltage Vss.

[0073] The Q node QN can be discharged by the operations of the third transistor T3 and the third compensation transistor TS3. The third transistor T3 and the third compensation transistor TS3 turn on based on the potential Qbn of the QB node QBN to discharge the Q node QN. Since the third transistor T3 and the third compensation transistor TS3 operate under the same conditions over the same time, they can deteriorate in the same way. In other words, the degree of deterioration (Vth shift) with respect to the threshold voltage of the third transistor T3 and the threshold voltage of the third compensation transistor TS3 may be the same. According to the second embodiment, the shift register 131 can perform deterioration compensation of the QB node (or the transistor connected to the QB node) by the operation of the compensation circuit unit NC, and the explanation is as follows.

[0074] The shift register 131 realized based on the Nth stage STGN according to the second embodiment can be defined as a compensation period during which deterioration compensation of the QB node QBN (or the transistor connected to the QB node) is performed from the time when the Q node QN is discharged after being bootstrapped until the next clock signal is applied. During the compensation period, the QB node QBN can be charged by the (N + 4)th gate signal Gout[n + 4] applied through the first compensation transistor TS1 turned on based on the potential Qn of the Q node QN. During the compensation period, the second compensation transistor TS2 is turned on based on the (N + 4)th carry signal, and the third compensation transistor TS3 can be turned on by the (N + 4)th gate signal Gout[n + 4] charged to the QB node QBN.

[0075] When the second compensation transistor TS2 and the third compensation transistor TS3 are turned on, the potential Qbn of the QB node QBN can be discharged through the second low-voltage line VSS except for the threshold voltage of the third compensation transistor TS3. Thereby, the potential Qbn of the QB node QBN can be determined as "Vss + Vth_TS3". Here, Vss corresponds to the second low voltage, and Vth_TS3 can correspond to the threshold voltage of the third compensation transistor.

[0076] Therefore, when the next clock signal is applied, a voltage Vss + Vth_TS3 that is as high as the threshold voltage of the third compensation transistor TS3 can be formed at the QB node QBN. As a result, the deterioration of the third transistor T3 connected to the QB node QBN is compensated by the voltage Vss + Vth_TS3 formed at the QB node QBN. Such an operation can occur sequentially and identically not only in the Nth stage STGN but also in all stages included in the shift register 131.

[0077] On the other hand, the threshold voltage of the third compensation transistor TS3 can move in the positive direction (T3Vth > 0V) as a matter of course, and can also move in the negative direction (T3Vth < 0V).

[0078] FIG. 12 shows the voltage formed at the QB node during the compensation period when the threshold voltage of the third compensation transistor TS3 moves in the positive direction, and FIG. 13 shows the voltage formed at the QB node during the compensation period when the threshold voltage of the third compensation transistor TS3 moves in the negative direction.

[0079] FIG. 14 shows the simulation results obtained in the same case as FIG. 12 (T3Vth > 0V), and can be confirmed with reference to the voltage Vss+Vth_TS3 formed at the QB node QBN during the compensation period and the threshold voltage Vth_TS3 of the third compensation transistor TS3.

[0080] FIG. 15 shows the simulation results obtained in the same case as FIG. 13 (T3Vth < 0V), and can be confirmed with reference to the voltage Vss formed at the QB node QBN during the compensation period.

[0081] As shown in FIGS. 12 and 14, when the threshold voltage of the third compensation transistor TS3 moves in the positive direction, a voltage (Vss+Vth_TS3) as high as the threshold voltage of the third compensation transistor TS3 can be formed at the QB node QBN.

[0082] As shown in FIGS. 13 and 15, when the threshold voltage of the third compensation transistor TS3 moves in the negative direction, a lower voltage Vss can be formed at the QB node QBN than when the threshold voltage of the third compensation transistor TS3 moves in the positive direction.

[0083] At this time, since the gate-source voltage Vgs of the first compensation transistor TS1 has the condition of "Vgs < 0", there may be no leakage to the side of the Nth output terminal OUT[N]. And the gate-source voltages Vgs of the second compensation transistor TS2 and the third compensation transistor TS3 have conditions close to 0, but can be maintained by the second low voltage Vss formed at the QB node QBN.

[0084] Therefore, in the second embodiment, even if the threshold voltage of the third compensation transistor TS3 moves in the positive direction or the negative direction, it can operate strongly to compensate for degradation and form a stable output.

[0085] As a result, every time a clock signal is generated due to the threshold voltage movement of the third transistor T3, the ripple of the first pull-up transistor T6 is induced, and the problem that the gate signal is output in a multi-form can be improved. Further, the problem that the gate signal is not output due to the deterioration of the output characteristics of the first pull-up transistor T6 or the second pull-up transistor T6C due to the threshold voltage movement of the third transistor T3 can be improved.

[0086] On the other hand, the second embodiment is only an example, and the configuration of the compensation circuit section NC for achieving the effects described in this specification is not limited to this and can be deformed, which will be referred to in the following embodiments.

[0087] FIG. 16 is a circuit configuration diagram of the Nth stage according to the third embodiment, and FIG. 17 is a drive waveform diagram of the Nth stage according to the third embodiment.

[0088] As shown in FIGS. 16 and 17, the Nth stage STGN according to the third embodiment may include a signal generation unit SC that outputs an Nth carry signal via an Nth carry terminal CRY[N] and outputs an Nth gate signal via an Nth output terminal OUT[N], and a compensation circuit section NC that compensates for the degradation of the QB node QBN (or a transistor connected to the QB node) included in the signal generation unit SC.

[0089] According to the third embodiment, the signal generation unit SC may include a first transistor T1, a second transistor T5C, a third transistor T3, a fourth transistor T3N, a fifth transistor T3O, a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6C, a second pull-down transistor T7C, a first capacitor CC, and a second capacitor CB.

[0090] According to the third embodiment, the compensation circuit section NC may include a first compensation transistor TS1, a second compensation transistor TS2, and a third compensation transistor TS3.

[0091] The third embodiment is the same as the second embodiment except for the connection relationship of a part of the configuration included in the compensation circuit section NC. Therefore, only the configuration included in the compensation circuit section NC and its connection relationship will be described below, and for the parts not described, refer to the second embodiment.

[0092] The gate electrode of the first compensation transistor TS1 is connected to the Q node QN, the first electrode is connected to the carry terminal CRY[N+4] of the N+4th stage, and the second electrode of the first capacitor CC, the first electrode of the second compensation transistor TS2, the gate electrode of the third compensation transistor TS3, and the second electrode may be connected to the QB node QBN. The first compensation transistor TS1 can be turned on based on the potential Qn of the Q node QN and transmit the N+4th carry signal Cry[n+4] output via the carry terminal CRY[N+4] of the N+4th stage to the QB node QBN.

[0093] The gate electrode of the second compensation transistor TS2 is connected to the carry terminal CRY[N+4] of the N+4th stage, the first electrode is connected to the second electrode of the first capacitor CC, the second electrode of the first compensation transistor TS1, the gate electrode of the third compensation transistor TS3, and the QB node QBN, and the second electrode may be connected to the first electrode of the third compensation transistor TS3. The second compensation transistor TS2 can be turned on based on the N+4th carry signal Cry[n+4] output via the carry terminal CRY[N+4] of the N+4th stage and connect the second electrode of the first compensation transistor TS1 and the first electrode of the third compensation transistor TS3.

[0094] The third compensation transistor TS3 may have its gate electrode connected to the QB node QBN, its first electrode connected to the second electrode of the second compensation transistor TS2, and its second electrode connected to the second low voltage line VSS. The third compensation transistor TS3 may be turned on based on the potential Qbn of the QB node QBN and transmit the second low voltage applied via the second low voltage line VSS to the second compensation transistor TS2.

[0095] On the other hand, in the third embodiment, as shown in FIG. 17, only the voltage formed at the QB node during the compensation period when the threshold voltage of the third compensation transistor TS3 moves in the positive direction is exemplarily shown. However, refer to the fact that the third embodiment can also exhibit the effects as described in FIG. 13 of the second embodiment.

[0096] FIG. 18 is a circuit configuration diagram of the Nth stage according to the fourth embodiment, and FIG. 19 is a drive waveform diagram of the Nth stage according to the fourth embodiment.

[0097] As shown in FIGS. 18 and 19, the Nth stage STGN according to the fourth embodiment may include a signal generation unit SC that outputs an Nth carry signal via an Nth carry terminal CRY[N] and outputs an Nth gate signal via an Nth output terminal OUT[N], and a compensation circuit unit NC that compensates for deterioration of the QB node QBN (or a transistor connected to the QB node) included in the signal generation unit SC.

[0098] According to the fourth embodiment, the signal generation unit SC may include a first transistor T1, a second transistor T5C, a third transistor T3, a fourth transistor T3N, a fifth transistor T3O, a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6C, a second pull-down transistor T7C, a first capacitor CC, and a second capacitor CB.

[0099] According to the fourth embodiment, the compensation circuit unit NC may include a first compensation transistor TS1, a second compensation transistor TS2, and a third compensation transistor TS3.

[0100] The fourth embodiment is the same as the second embodiment except for the connection relationship of a part of the configuration included in the compensation circuit section NC. Therefore, only the configuration included in the compensation circuit section NC and its connection relationship will be described below, and for the parts not described, refer to the second embodiment.

[0101] The first compensation transistor TS1 has its gate electrode connected to the Q node QN, its first electrode connected to the output terminal OUT[N + 4] of the (N + 4)-th stage, and can connect its second electrode to the second electrode of the first capacitor CC, the first electrode of the second compensation transistor TS2, the gate electrode of the third compensation transistor TS3, and the QB node QBN. The first compensation transistor TS1 is turned on based on the potential Qn of the Q node QN, and can transmit the (N + 4)-th gate signal Gout[n + 4] output via the output terminal OUT[N + 4] of the (N + 4)-th stage to the QB node QBN.

[0102] The second compensation transistor TS2 has its gate electrode connected to the output terminal OUT[N + 4] of the (N + 4)-th stage, its first electrode connected to the second electrode of the first capacitor CC, the second electrode of the first compensation transistor TS1, the gate electrode of the third compensation transistor TS3, and the QB node QBN, and can connect its second electrode to the first electrode of the third compensation transistor TS3. The second compensation transistor TS2 is turned on based on the (N + 4)-th gate signal Gout[n + 4] output via the output terminal OUT[N + 4] of the (N + 4)-th stage, and can connect the second electrode of the first compensation transistor TS1 and the first electrode of the third compensation transistor TS3.

[0103] The third compensation transistor TS3 has its gate electrode connected to the QB node QBN, its first electrode connected to the second electrode of the second compensation transistor TS2, and can connect its second electrode to the second low voltage line VSS. The third compensation transistor TS3 is turned on based on the potential Qbn of the QB node QBN, and can transmit the second low voltage applied via the second low voltage line VSS to the second compensation transistor TS2.

[0104] On the other hand, in the fourth embodiment, as shown in FIG. 19, only the voltage formed at the QB node during the compensation period when the threshold voltage of the third compensation transistor TS3 moves in the positive direction is exemplarily shown. However, refer to the fact that the fourth embodiment can also exhibit the effects as described in FIG. 13 of the second embodiment.

[0105] As described above, in this specification, in order to reflect and compensate for the deterioration of the transistor with the gate electrode connected to the QB node for each frame, there is an effect that problems (such as multi-signal output or signal non-output) due to the movement of the threshold voltage of the transistor in the positive direction can be improved. Also, in this specification, the deterioration of the transistor with the gate electrode connected to the QB node can be compensated for each frame, and there is an effect that the output deviation between stages can be reduced. Further, in this specification, since the deterioration compensation is performed based on the signal output from the subordinate-connected stage, there is an effect that the phenomenon of the defect associated with the deterioration being transmitted to a specific stage can be prevented.

Explanation of Signs

[0106] 130 Gate driving unit 150 Display panel 131 Shift register 135 Level shifter SC signal generation unit NC compensation circuit unit TS1 First compensation transistor TS2 Second compensation transistor TS3 Third compensation transistor

Claims

1. A display panel for displaying an image, and a shift register connected to the display panel, wherein the shift register includes a plurality of stages each having an output terminal for outputting a gate signal and a carry terminal for outputting a carry signal, a first N-th stage of the plurality of stages is a signal generator that outputs the gate signal of a high voltage and the carry signal of a high voltage according to the potential of a Q node, and outputs the gate signal of a first low voltage and the carry signal of a second low voltage according to the potential of a QB node, the signal generator including a signal generation unit including a transistor that is turned on based on the potential of the QB node, a display device characterized by including a compensation circuit that forms a compensation voltage on the QB node based on the potentials of the Q node and the QB node and a signal output from another stage, and compensates for deterioration of the transistor included in the signal generation unit.

2. The display device according to claim 1, wherein the other stage is located after the N-th stage.

3. The display device according to claim 2, wherein the other stage is a (N + 4)-th stage located after the N-th stage.

4. The compensation circuit includes a first compensation transistor that is turned on based on the potential of the Q node, a second compensation transistor that is turned on based on a signal output from another stage, and a third compensation transistor that is turned on based on the potential of the QB node, and the display device according to claim 1, wherein the compensation voltage includes a threshold voltage of the third compensation transistor.

5. The first compensation transistor includes a gate electrode connected to the Q node, a first electrode receiving a signal output from another stage, and a second electrode connected to the QB node, the second compensation transistor includes a gate electrode receiving a signal output from another stage, a first electrode connected to the QB node, and a second electrode connected to the third compensation transistor, and the display device according to claim 4, wherein the third compensation transistor includes a gate electrode connected to the QB node, a first electrode connected to the second electrode of the second compensation transistor, and a second electrode receiving the second low voltage.

6. The display device according to claim 5, wherein the second low voltage is lower than the first low voltage.

7. The first electrode of the first compensation transistor is connected to the output terminal of the other stage and receives the gate signal output from the other stage. The display device according to claim 6, wherein the gate electrode of the second compensation transistor is connected to the carry terminal of the other stage and receives the carry signal output from the other stage.

8. The first electrode of the first compensation transistor is connected to the carry terminal of the other stage and receives the carry signal output from the other stage. The display device according to claim 6, wherein the gate electrode of the second compensation transistor is connected to the carry terminal of the other stage and receives the carry signal output from the other stage.

9. The first electrode of the first compensation transistor is connected to the output terminal of the other stage and receives the gate signal output from the other stage. The display device according to claim 6, wherein the gate electrode of the second compensation transistor is connected to the output terminal of the other stage and receives the gate signal output from the other stage.

10. A shift register including a plurality of stages each having an output terminal for outputting a gate signal and a carry terminal for outputting a carry signal, wherein the Nth stage among the plurality of stages is a signal generation unit that outputs the gate signal of a high voltage and the carry signal of a high voltage according to the potential of the Q node, and outputs the gate signal of a first low voltage and the carry signal of a second low voltage according to the potential of the QB node, the signal generation unit including a transistor that is turned on based on the potential of the QB node; a gate signal generation circuit, comprising: a compensation circuit that forms a compensation voltage at the QB node based on the potentials of the Q node and the QB node and a signal output from another stage, and compensates for deterioration of the transistor included in the signal generation unit.

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