Display device

Abstract

To provide a display device that can, when plural lines are used to supply different signals to plural pixels at the same timing, reduce difference in load capacity between the lines and reduce a gap in display gradation and / or signal delay.SOLUTION: A display device comprises a first data line to an N-th (N is a natural number of 3 or more) data line for supplying different video signals, and a pixel including a selection transistor connected to any one of the first data line to the N-th data line. One of the first data line to the N-th data line is connected to one terminal of the selection transistor by disposing the one of the first data line to the N-th data line at a place closest to the one terminal of the selection transistor in a manner that the first data line to the N-th data line cross each other.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a display device. Or the present invention relates to a method for driving a display device. Or, the present invention relates to an electronic device including the display device.

Background Art

[0002] Display devices, such as liquid crystal display devices using liquid crystal elements, are becoming increasingly popular, ranging from large display devices such as television receivers to small display devices such as mobile phones. In the future, products with higher added value are required and development is underway. In the future, in order to further increase the added value, it may be possible to increase the number of wirings such as scanning lines or data lines that supply signals to each pixel of the display device, and to make the driving of the pixels more highly functional. For example, Patent Document 1 discloses a display device provided with a plurality of data lines. Patent Document 1 discloses a configuration in which each of the plurality of data lines is connected to a transistor of a pixel.

[0003] In the future, in order to further increase the added value, it may be possible to increase the number of wirings such as scanning lines or data lines that supply signals to each pixel of the display device, and to make the driving of the pixels more highly functional. For example, Patent Document 1 discloses a display device provided with a plurality of data lines. Patent Document 1 discloses a configuration in which each of the plurality of data lines is connected to a transistor of a pixel. Or, for example, Patent Document 1 discloses a display device provided with a plurality of data lines. Patent Document 1 discloses a configuration in which each of the plurality of data lines is connected to a transistor of a pixel.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When increasing the number of wirings such as scanning lines or data lines that supply signals to each pixel of the display device in the same manner as in Patent Document 1 above, the wiring is extended from the transistor of the pixel to supply a signal to the pixel. It is configured to connect to wirings such as scanning lines or data lines. In this configuration, there is a problem that differences occur in the load capacities of the respective wirings, resulting in display defects. The case where differences occur in the load capacities will be described with reference to the following drawings. When differences occur in the load capacities, it will be described with reference to the following drawings. When differences occur in the load capacities, it will be described with reference to the following drawings.

[0006] FIG. 15(A) shows the circuit configuration of pixels included in a display device. In FIG. 15(A), as N (where N is a natural number of 3 or more) data lines (also referred to as signal lines), specifically, the circuit configuration in the case of supplying different video signals from three data lines to three different pixels is shown. Pixel 1501A includes transistor 1504A (also referred to as a selection transistor) and display element section 1505A. The transistor 1504A of pixel 1501A has its gate terminal connected to scanning line 1503A, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the first data line 1502A, and the other terminal is connected to display element section 1505A. Pixel 1501B includes transistor 1504B (also referred to as a selection transistor) and display element section 1505B. The transistor 1504B of pixel 1501B has its gate terminal connected to scanning line 1503B, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the second data line 1502B, and the other terminal is connected to display element section 1505B. Pixel 1501C includes transistor 1504C (also referred to as a selection transistor) and display element section 1505C. The transistor 1504C of pixel 1501C has its gate terminal connected to scanning line 1503C, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the third data line 1502C, and the other terminal is connected to display element section 1505C. As described above, in FIG. 15(A) As N (where N is a natural number of 3 or more) data lines (also referred to as signal lines), specifically, the circuit configuration in the case of supplying different video signals from three data lines to three different pixels is shown. As N (where N is a natural number of 3 or more) data lines (also referred to as signal lines), specifically, the circuit configuration in the case of supplying different video signals from three data lines to three different pixels is shown. Pixel 1501A includes transistor 1504A (also referred to as a selection transistor) and display element section 1505A. The transistor 1504A of pixel 1501A has its gate terminal connected to scanning line 1503A, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the first data line 1502A, and the other terminal is connected to display element section 1505A. The transistor 1504A of pixel 1501A has its gate terminal connected to scanning line 1503A, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the first data line 1502A, and the other terminal is connected to display element section 1505A. The transistor 1504A of pixel 1501A has its gate terminal connected to scanning line 1503A, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the first data line 1502A, and the other terminal is connected to display element section 1505A. Pixel 1501B includes transistor 1504B (also referred to as a selection transistor) and display element section 1505B. Pixel 1501B includes transistor 1504B (also referred to as a selection transistor) and display element section 1505B. The transistor 1504B of pixel 1501B has its gate terminal connected to scanning line 1503B, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the second data line 1502B, and the other terminal is connected to display element section 1505B. The transistor 1504B of pixel 1501B has its gate terminal connected to scanning line 1503B, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the second data line 1502B, and the other terminal is connected to display element section 1505B. The transistor 1504B of pixel 1501B has its gate terminal connected to scanning line 1503B, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the second data line 1502B, and the other terminal is connected to display element section 1505B. Pixel 1501C includes transistor 1504C (also referred to as a selection transistor) and display element section 1505C. The transistor 1504C of pixel 1501C has its gate terminal connected to scanning line 1503C, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the third data line 1502C, and the other terminal is connected to display element section 1505C. The transistor 1504C of pixel 1501C has its gate terminal connected to scanning line 1503C, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the third data line 1502C, and the other terminal is connected to display element section 1505C. The transistor 1504C of pixel 1501C has its gate terminal connected to scanning line 1503C, one terminal (also referred to as the first terminal) that serves as the source terminal or the drain terminal is connected to the third data line 1502C, and the other terminal is connected to display element section 1505C. As described above, in FIG. 15(A ) The circuit configuration shown, for example, by the scanning signals of scanning lines 1503A to 1503C simultaneously turns on transistors 1504A to 1504C (also referred to as the on state), and supplies different video signals from the first data line 1502A to the third data line 1502C to the display element units 1505A to 1505C, which is an effective configuration. There is.

[0007] Note that the description of the specific display elements for the display element units 1505A to 1505C is omitted. In the case of a liquid crystal display device, a configuration in which a liquid crystal element and a capacitive element are provided, or in the case of an EL element, a configuration in which a light emitting element and a transistor for driving the light emitting element are provided may be used. That's it.

[0008] When pixels are arranged and provided in a matrix, the first data line 1502A to the third data line 1502C is provided in a direction substantially orthogonal to the scanning lines 1503A to 1503C, and pixels 1501A to 1501C having transistors 1504A to 1504C are provided along the first data line 1502A to the third data line 1502C. Therefore, when the first data line 1502A to the third data line 1502C are provided in parallel, when connecting one terminal of the transistor 1504B to the second data line 1502B, the intersection 1506 shown in FIG. 15(A) is formed. Similarly, when connecting one terminal of the transistor 1504C to the third data line 1502C, the intersection 1507 shown in FIG. 15(A) is formed. At the intersection 1506 and the intersection 1507, an electrical short between the first data line 1502A to the third data line 1502C occurs. Similarly, when connecting one terminal of the transistor 1504C to the third data line 1502C, the intersection 1507 shown in FIG. 15(A) is formed. At the intersection 1506 and the intersection 1507, an electrical short between the first data line 1502A to the third data line 1502C occurs. To avoid crosstalk (short circuit), a conductive layer is formed in another layer, and through the conductive layer, one terminal of the transistor 1504B is connected to the second data line 1502B, and one terminal of the transistor 15 04C is connected to the third data line 1502C, as shown in the figure.

[0009] However, by connecting one terminal of the transistor 1504B to the second data line 1 502B and one terminal of the transistor 1504C to the third data line 1502 C through the conductive layer, as shown in the circuit diagram of FIG. 15(B), a load capacitance 1516 caused by the intersection 1506, a load capacitance 1517A and a load capacitance 151 7B caused by the intersection 1507 are formed. Specifically, the load capacitance 1516, the load capacitance 151 7A, and the load capacitance 1517B will vary depending on the area of the intersection of the aforementioned conductive layer and the first data line 1502A to the third data line 1502 C. Therefore, a difference in load capacitance occurs between the first data line 1502A and the second data line 1502B, making it difficult to supply signals of a desired potential to each pixel, resulting in problems such as display gradation deviation and / or signal delay becoming apparent. Therefore, an aspect of the present invention aims to provide a display device capable of reducing the difference in load capacitance formed in each wiring and reducing display gradation deviation and / or signal delay when supplying different signals to a plurality of pixels at the same timing using a plurality of wirings.

[0010] Therefore, an aspect of the present invention is to reduce the difference in load capacitance formed in each wiring and reduce display gradation deviation and / or or signal delay when supplying different signals to a plurality of pixels at the same timing using a plurality of wirings. The purpose is to provide a display device that can achieve this.

Means for Solving the Problem

[0011] One aspect of the present invention is a first data line to an Nth data line (N is 3 or more) for supplying different video signals a data line of the above natural numbers and is connected to any one of the first to Nth data lines a pixel having a selection transistor, and any one of the first to Nth data lines and one terminal of the selection transistor are arranged and connected closest to one terminal of the selection transistor by intersecting the first to Nth data lines to select any one of the first to Nth data lines It is a display device that is arranged and connected.

[0012] In one aspect of the present invention, a display device in which a display element having a liquid crystal element is connected to the other terminal of the selection transistor may be used.

[0013] In one aspect of the present invention, a display device in which a display element having a light-emitting element and a driving transistor for driving the light-emitting element is connected to the other terminal of the selection transistor may be used.

[0014] In one aspect of the present invention, the display device has scan lines, and the intersection of the first to Nth data lines may be provided using the same conductive layer as the scan lines.

[0015] In one aspect of the present invention, the resistance formed by the conductive layer at the intersection of the first to Nth data lines is evenly formed in the first to Nth data lines It may be a display device.

[0016] One aspect of the present invention is the first to Nth (N is a natural number of 3 or more) scan lines for supplying different scan signals and a pixel having a selection transistor connected to any one of the first to Nth scan lines, and any one of the first to Nth scan lines and the gate terminal of the selection transistor are arranged such that by intersecting the first to Nth scan lines, the first ​​​ One of the data lines from the first to the Nth scanning lines is disposed closest to the gate terminal of the selection transistor and connected thereto. This is a display device.

[0017] In one aspect of the present invention, any one of the first to Nth data lines is connected to one terminal of the selection transistor, and a display element having a liquid crystal element is connected to the other terminal of the selection transistor. A display device may be used. One of the data lines from the first to the Nth data lines is connected to one terminal of the selection transistor, and a display element having a light-emitting element and a drive transistor for driving the light-emitting element is connected to the other terminal of the selection transistor. A display device may be used. This is also good.

[0018] In one aspect of the present invention, any one of the first to Nth data lines is connected to one terminal of the selection transistor, and a light-emitting element and a drive transistor for driving the light-emitting element are connected to the other terminal of the selection transistor. A display element having a display device may be used. One of the data lines from the first to the Nth data lines is connected to one terminal of the selection transistor, and a display element having a light-emitting element and a drive transistor for driving the light-emitting element is connected to the other terminal of the selection transistor. A display device may be used. This is also good. This is also good.

Advantages of the Invention

[0019] According to one aspect of the present invention, it is possible to reduce the difference in load capacitance formed in each wiring and reduce the deviation of display gradation and / or signal delay. This is also good.

Brief Description of the Drawings

[0020]

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Embodiments for Carrying Out the Invention

[0021] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and it will be easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, it should not be construed as being limited to the description of the present embodiment. In the configuration of the present invention described below, reference numerals indicating the same object are common among different drawings. In addition, in the drawings and the like of each embodiment, the size, layer thickness, signal waveform, or

[0022] area of each component shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0023] The terms first, second, third, and up to n (n is a natural number) used in this specification are attached to avoid confusion of constituent elements, and it should be noted that they are not numerically limiting.

[0024] (Embodiment 1)​ In this embodiment, the circuit configuration of the pixels included in the display device will be described. In the circuit diagrams shown in this embodiment, in order to supply different signals to a plurality of pixels at the same timing, a plurality of wirings are used as N (N is a natural number of 3 or more) data lines (also referred to as signal lines), and an example will be described in which different video signals are supplied to a plurality of pixels based on the scan signals of the scan lines.

[0025] FIG. 1(A) shows the circuit configuration of the pixels included in the display device. In FIG. 1(A), as N ( N is a natural number of 3 or more) data lines (also referred to as signal lines), specifically, the circuit configuration when different video signals are supplied to three different pixels instead of three data lines is shown. Pixel 101A includes a transistor 104A (also referred to as a selection transistor) and a display element section 1 05A. The transistor 104A of pixel 101A has a gate terminal connected to scan line 103 A, one terminal (also referred to as the first terminal) that serves as a source terminal or a drain terminal is connected to the first data line 102A, and the other terminal is connected to the display element section 105A. Pixel 101B includes a transistor 104B (also referred to as a selection transistor) and a display element section 105B. The transistor 104B of pixel 101B has a gate terminal connected to scan line 10 3B, one terminal (also referred to as the first terminal) that serves as a source terminal or a drain terminal is connected to the second data line 102B, and the other terminal is connected to the display element section 105B. Pixel 101C includes a transistor 104C (also referred to as a selection transistor) and a display element section 105C. The transistor 104C of pixel 101C has a gate terminal connected to scan line 1 03C, one terminal (also referred to as the first terminal) that serves as a source terminal or a drain terminal ) is connected to the third data line 102C, and the other terminal is connected to the display element section 105C. The circuit configuration shown in Fig. 1(A) described above is, for example, when the scanning lines 103A to 103C turn on the transistors 104A to 104C simultaneously (also referred to as the on state), and supply different video signals to the display element sections 105A to 105C from the first data line 102A to the third data line 102C, it is an effective configuration.

[0026] When arranging pixels in a matrix, the first data line 102A to the third data line 102C are provided in a direction substantially orthogonal to the scanning lines 103A to 103C, and pixels 101A to 101C having the transistors 104A to 104C are provided along the first data line 102A to the third data line 102C. The difference between the circuit configuration shown in Fig. 1(A) and the circuit configuration shown in Fig. 15(A) above is that in the region where the first data line 102A to the third data line 102C are arranged, by providing the intersection of the first data line 102A to the third data line 102C, each of the first data line 102 A to the third data line 102C is arranged closest to one terminal of the transistor included in the corresponding pixel 101A to 101C. Then, the connection between one terminal of the transistor and the data line arranged closest is made.

[0027] Note that a pixel corresponds to a display unit that can control the brightness of one color element (for example, any one of R (red), G (green), and B (blue)). Therefore, in the case of a color display device, the minimum display unit of a color image is composed of three pixels: an R pixel, a G pixel, and a B pixel. ​​It is assumed that. However, the color elements for displaying a color image are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. Moreover, the transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and can allow current to flow through the drain region, the channel region, and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, in this specification, the regions functioning as the source and the drain may not be referred to as the source or the drain. In that case, as an example, each may be denoted as one terminal and the other terminal.

[0028] In addition, when it is stated in this specification that A and B are connected, it shall include not only the case where A and B are directly connected, but also the case where they are electrically connected. Here, when A and B are electrically connected, it means that there is an object having some electrical action between A and B, and it represents the case where the part between A and B including the object becomes a node. Specifically, A and B are connected via a switching element such as a transistor, and when A and B become substantially the same potential due to the conduction of the switching element, or A and Moreover, the transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and can allow current to flow through the drain region, the channel region, and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, in this specification, the regions functioning as the source and the drain may not be referred to as the source or the drain. In that case, as an example, each may be denoted as one terminal and the other terminal. Moreover, the transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and can allow current to flow through the drain region, the channel region, and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, in this specification, the regions functioning as the source and the drain may not be referred to as the source or the drain. In that case, as an example, each may be denoted as one terminal and the other terminal. Moreover, the transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and can allow current to flow through the drain region, the channel region, and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, in this specification, the regions functioning as the source and the drain may not be referred to as the source or the drain. In that case, as an example, each may be denoted as one terminal and the other terminal. Moreover, the transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and can allow current to flow through the drain region, the channel region, and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, in this specification, the regions functioning as the source and the drain may not be referred to as the source or the drain. In that case, as an example, each may be denoted as one terminal and the other terminal. Moreover, the transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and can allow current to flow through the drain region, the channel region, and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, in this specification, the regions functioning as the source and the drain may not be referred to as the source or the drain. In that case, as an example, each may be denoted as one terminal and the other terminal. In that case, as an example, each may be denoted as one terminal and the other terminal. Alternatively, each may be denoted as the first electrode (terminal) and the second electrode (terminal). Alternatively, they may be denoted as the source region and the drain region. Alternatively, they may be denoted as the source terminal and the drain terminal. Alternatively, they may be denoted as the source region and the drain region. Alternatively, they may be denoted as the source terminal and the drain terminal.

[0029] In addition, when it is stated in this specification that A and B are connected, it shall include not only the case where A and B are directly connected, but also the case where they are electrically connected. Here, when A and B are electrically connected, it means that there is an object having some electrical action between A and B, and it represents the case where the part between A and B including the object becomes a node. Specifically, A and B are connected via a switching element such as a transistor, and when A and B become substantially the same potential due to the conduction of the switching element, or A and In addition, when it is stated in this specification that A and B are connected, it shall include not only the case where A and B are directly connected, but also the case where they are electrically connected. Here, when A and B are electrically connected, it means that there is an object having some electrical action between A and B, and it represents the case where the part between A and B including the object becomes a node. Specifically, A and B are connected via a switching element such as a transistor, and when A and B become substantially the same potential due to the conduction of the switching element, or A and In addition, when it is stated in this specification that A and B are connected, it shall include not only the case where A and B are directly connected, but also the case where they are electrically connected. Here, when A and B are electrically connected, it means that there is an object having some electrical action between A and B, and it represents the case where the part between A and B including the object becomes a node. Specifically, A and B are connected via a switching element such as a transistor, and when A and B become substantially the same potential due to the conduction of the switching element, or A and In addition, when it is stated in this specification that A and B are connected, it shall include not only the case where A and B are directly connected, but also the case where they are electrically connected. Here, when A and B are electrically connected, it means that there is an object having some electrical action between A and B, and it represents the case where the part between A and B including the object becomes a node. Specifically, A and B are connected via a switching element such as a transistor, and when A and B become substantially the same potential due to the conduction of the switching element, or A and In addition, when it is stated in this specification that A and B are connected, it shall include not only the case where A and B are directly connected, but also the case where they are electrically connected. Here, when A and B are electrically connected, it means that there is an object having some electrical action between A and B, and it represents the case where the part between A and B including the object becomes a node. Specifically, A and B are connected via a switching element such as a transistor, and when A and B become substantially the same potential due to the conduction of the switching element, or A and In addition, when it is stated in this specification that A and B are connected, it shall include not only the case where A and B are directly connected, but also the case where they are electrically connected. Here, when A and B are electrically connected, it means that there is an object having some electrical action between A and B, and it represents the case where the part between A and B including the object becomes a node. Specifically, A and B are connected via a switching element such as a transistor, and when A and B become substantially the same potential due to the conduction of the switching element, or A and is connected to B, and when the potential difference generated across both ends of the resistive element does not affect the operation of the circuit including A and B, etc., considering the circuit operation, the portion between A and B can be regarded as the same node without any problem. This represents a situation where it is acceptable to consider the portion between A and B as the same node.

[0030] Note that voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference respectively.

[0031] Regarding the structure of the transistor provided in the pixel, an inverted staggered structure or a normal staggered structure may be used. Alternatively, a double-gate structure in which the channel region is divided into a plurality of regions and connected in series, or a dual-gate structure in which gate electrodes are provided above and below the channel region may be used. Also, the semiconductor layer constituting the transistor may be formed of a plurality of island-shaped semiconductor layers, and it may be used as a transistor element capable of realizing a switching operation.

[0032] In FIG. 1(A), the intersection 106 is the region where the second data line 102B and the third data line 102C intersect. Also, the intersection 107 is the region where the first data line 102A and the second data line 102B intersect. Also, the intersection 108 is the region where the first data line 102A and the third data line 102C intersect. Also, the intersection 109 is the region where the second data line 102B and the third data line 102C intersect. Also, the intersection 110 is the region where the first data line 102A and the second data line 102B intersect. Also, the intersection 111 is the region where the first data line 102A and the third data line 102C intersect. And the first data The data line 102A is disposed in the immediate vicinity of one terminal of the transistor 104A, and one terminal of the transistor 1 04A will be connected without passing through an intersection with other wiring. Also, the second data line 102B of the second is disposed in the immediate vicinity of one terminal of the transistor 104B, and the one terminal of the transistor 104B will be connected without passing through an intersection with other wiring. Also, the third data line 102C is disposed in the immediate vicinity of one terminal of the transistor 104C, and one terminal of the transistor 104C will be connected without passing through an intersection with other wiring.

[0033] The intersections 106 to 111 shown in FIG. 1(A) are formed by using another conductive layer for one of the intersecting data lines in order to avoid an electrical short circuit (short) between the first data line 102A to the third data line 102C. In the intersections 106 to 111 using the conductive layer, a load capacitance is formed between the intersecting data lines. The load capacitance is formed in a region where the intersecting data lines overlap, that is, in a region where the conductive layer forming the first data line 102A to the third data line 102C and another conductive layer at the intersection overlap.

[0034] FIG. 1(B) is a circuit diagram showing the intersections 106 to 111 by the first data line 102A to the third data line 102 C shown in FIG. 1(A) as load capacitances. In FIG. 1(B ), as in FIG. 1(A), the first data line 102A is connected to the first pixel 101A, the second data line 102B is connected to the second pixel 101B, and the third data line 102C is connected to the third pixel 101C. Also, in FIG. 1(B), the intersection 106 shown in FIG. 1(A) ​​​​The load capacitance caused thereby is represented by the capacitance element 191, and the load capacitance caused by the intersection portion 107 shown in Fig. 1(A) is represented by the capacitance element 192, and the load capacitance caused by the intersection portion 108 shown in Fig. 1(A) is represented by the capacitance element 193, and the load capacitance caused by the intersection portion 109 shown in Fig. 1(A) is represented by the capacitance element 1 94, and the load capacitance caused by the intersection portion 110 shown in Fig. 1(A) is represented by the capacitance element 195 , and the load capacitance caused by the intersection portion 111 shown in Fig. 1(A) is represented by the capacitance element 196.

[0035] As shown in Fig. 1(B), load capacitances are formed by the first data line 102A and the second data line 102B with the capacitance elements 192 and 195. Further, load capacitances are formed by the second data line 10 2B and the third data line 102C with the capacitance elements 191 and 194. Further, load capacitances are formed by the first data line 102A and the third data line 102C with the capacitance elements 193 and 196. As described above, the load capacitance is formed in a region where the conductive layer forming the first data line 102A to the third data line 102C overlaps with another conductive layer at the intersection. Therefore, in the configuration of the present embodiment, the first data line 102A to the third data line 102C are data lines with the same wiring width, and load capacitances can be formed evenly on each of the data lines. Therefore, in the configuration of the present embodiment, since the areas of the intersections formed by the first data line 102A to the third data line 102C can be made equal, load capacitances can be formed evenly on each of the data lines. As a result, the load capacitances are made equal among the first data line 102A to the third data

[0036] line 102C, and signals with desired potentials can be supplied to each pixel. Therefore, in the configuration of the present embodiment, since the areas of the intersections formed by the first data line 102A to the third data line 102C can be made equal, load capacitances can be formed evenly on each of the data lines. As a result, the load capacitances are made equal among the first data line 102A to the third data line 102C, and signals with desired potentials can be supplied to each pixel. line 102C, and signals with desired potentials can be supplied to each pixel. Then, the display device can reduce the display gradation deviation and / or signal delay caused by the difference in load capacitance between wirings.

[0037] Next, in FIGS. 2(A) and 2(B), an example of a specific display element for the display element units 105A to 105C shown in FIG. 1(A) will be described. Note that in the description of FIGS. 2(A) and 2(B), description of parts overlapping with the configuration other than the display element units 105A to 105C shown in FIG. 1(A) will be omitted. In the description of FIGS. 2(A) and 2(B), the description of parts overlapping with the configuration other than the display element units 105A to 105C shown in FIG. 1(A) will be omitted. description of parts overlapping with the configuration other than the display element units 105A to 105C shown in FIG. 1(A) will be omitted.

[0038] The circuit diagram shown in FIG. 2(A) shows an example in the case where the display element units 105A to 105C shown in FIG. 1(A) have a liquid crystal element configuration. The display element unit 105A shown in FIG. 2(A) has a liquid crystal element 121A and a capacitor element 122A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104A. The display element unit 105B shown in FIG. 2(A) has a liquid crystal element 121B and a capacitor element 122B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104B. The display element unit 105C shown in FIG. 2(A) has a liquid crystal element 121C and a capacitor element 122C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104C. Note that the liquid crystal elements 121A to 121C have one electrode (also referred to as a pixel electrode or a first electrode) connected to the other terminal of the transistors 104A to 104C, and the other electrode (also referred to as a counter electrode or a second electrode) connected to a common potential line (also referred to as a common line). Also, the capacitor elements 122A to 122C have one electrode (also referred to as a first electrode) connected to the transistors 104A to 104C, The circuit diagram shown in FIG. 2(A) shows an example in the case where the display element units 105A to 105C shown in FIG. 1(A) have a liquid crystal element configuration. The display element unit 105A shown in FIG. 2(A) has a liquid crystal element 121A and a capacitor element 122A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104A. The display element unit 105B shown in FIG. 2(A) has a liquid crystal element 121B and a capacitor element 122B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104B. The display element unit 105C shown in FIG. 2(A) has a liquid crystal element 121C and a capacitor element 122C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104C. Note that the liquid crystal elements 121A to 121C have one electrode (also referred to as a pixel electrode or a first electrode) connected to the other terminal of the transistors 104A to 104C, and the other electrode (also referred to as a counter electrode or a second electrode) connected to a common potential line (also referred to as a common line). Also, the capacitor elements 122A to 122C have one electrode (also referred to as a first electrode) connected to the transistors 104A to 104C, The display element unit 105A shown in FIG. 2(A) has a liquid crystal element 121A and a capacitor element 122A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104A. The display element unit 105A shown in FIG. 2(A) has a liquid crystal element 121A and a capacitor element 122A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104A. The display element unit 105B shown in FIG. 2(A) has a liquid crystal element 121B and a capacitor element 122B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104B. The display element unit 105B shown in FIG. 2(A) has a liquid crystal element 121B and a capacitor element 122B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104B. The display element unit 105C shown in FIG. 2(A) has a liquid crystal element 121C and a capacitor element 122C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104C. The display element unit 105C shown in FIG. 2(A) has a liquid crystal element 121C and a capacitor element 122C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104C. The display element unit 105C shown in FIG. 2(A) has a liquid crystal element 121C and a capacitor element 122C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104C. Note that the liquid crystal elements 121A to 121C have one electrode (also referred to as a pixel electrode or a first electrode) connected to the other terminal of the transistors 104A to 104C, and the other electrode (also referred to as a counter electrode or a second electrode) connected to a common potential line (also referred to as a common line). Also, the capacitor elements 122A to 122C have one electrode (also referred to as a first electrode) connected to the transistors 104A to 104C, The display element unit 105C shown in FIG. 2(A) has a liquid crystal element 121C and a capacitor element 122C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104C. Note that the liquid crystal elements 121A to 121C have one electrode (also referred to as a pixel electrode or a first electrode) connected to the other terminal of the transistors 104A to 104C, and the other electrode (also referred to as a counter electrode or a second electrode) connected to a common potential line (also referred to as a common line). Also, the capacitor elements 122A to 122C have one electrode (also referred to as a first electrode) connected to the transistors 104A to 104C, The display element unit 105C shown in FIG. 2(A) has a liquid crystal element 121C and a capacitor element 122C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104C. Note that the liquid crystal elements 121A to 121C have one electrode (also referred to as a pixel electrode or a first electrode) connected to the other terminal of the transistors 104A to 104C, and the other electrode (also referred to as a counter electrode or a second electrode) connected to a common potential line (also referred to as a common line). Also, the capacitor elements 122A to 122C have one electrode (also referred to as a first electrode) connected to the transistors 104A to 104C, The display element unit 105C shown in FIG. 2(A) has a liquid crystal element 121C and a capacitor element 122C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 104C. Note that the liquid crystal elements 121A to 121C have one electrode (also referred to as a pixel electrode or a first electrode) connected to the other terminal of the transistors 104A to 104C, and the other electrode (also referred to as a counter electrode or a second electrode) connected to a common potential line (also referred to as a common line). Also, the capacitor elements 122A to 122C have one electrode (also referred to as a first electrode) connected to the transistors 104A to 104C, The capacitor elements 122A to 122C have one electrode (also referred to as a first electrode) connected to the transistors 104A to 104C, It is connected to the other terminal of the transistor 104C, and the other electrode (also referred to as the second electrode) is connected to the capacitor line. The capacitor elements 122A to 122C may be provided as needed, and can also be omitted.

[0039] The circuit diagram shown in Fig. 2(B) shows an example of the case where the display element units 105A to 10 5C shown in Fig. 1(A) have a light-emitting element such as an EL (Electro Luminescence) element. The display element unit 105A shown in Fig. 2(B) has a light-emitting element 123A and a transistor 124A (also referred to as a driving transistor) for driving the light-emitting element 123A. The display element unit 105B shown in Fig. 2(B) has a light-emitting element 123 B and a transistor 124B (also referred to as a driving transistor) for driving the light-emitting element 123B. The display element unit 105C shown in Fig. 2(B) has a light-emitting element 123C and a transistor 124C (also referred to as a driving transistor) for driving the light-emitting element 123C. The gates of the transistors 124A to 124C are connected to the other terminals of the transistors 104A to 104C, and one terminal (also referred to as the first terminal) serving as the source terminal or the drain terminal is connected to a current supply line (also referred to as a power supply line) for passing current to the light-emitting elements 123A to 123C, and the other terminal (also referred to as the second terminal) serving as the source terminal or the drain terminal is connected to one electrode (also referred to as the first electrode) of the light-emitting elements 123A to 123C. The other electrodes (also referred to as the second electrodes) of the light-emitting elements 123A to 123 C are connected to the ground line (also referred to as a common potential line). C have. The gates of the transistors 124A to 124C are connected to the other terminals of the transistors 104A to 104C, and one terminal (also referred to as the first terminal) serving as the source terminal or the drain terminal is connected to a current supply line (also referred to as a power supply line) for passing current to the light-emitting elements 123A to 123C, and the other terminal (also referred to as the second terminal) serving as the source terminal or the drain terminal is connected to one electrode (also referred to as the first electrode) of the light-emitting elements 123A to 123C. The other electrodes (also referred to as the second electrodes) of the light-emitting elements 123A to 123 C are connected to the ground line (also referred to as a common potential line). C has. The gates of the transistors 124A to 124C are connected to the other terminals of the transistors 104A to 104C, and one terminal (also referred to as the first terminal) serving as the source terminal or the drain terminal is connected to a current supply line (also referred to as a power supply line) for passing current to the light-emitting elements 123A to 123C, and the other terminal (also referred to as the second terminal) serving as the source terminal or the drain terminal is connected to one electrode (also referred to as the first electrode) of the light-emitting elements 123A to 123C. The other electrodes (also referred to as the second electrodes) of the light-emitting elements 123A to 123 C are connected to the ground line (also referred to as a common potential line). It should be noted that for the transistors 124A to 124C, the gate terminals are connected to the other terminals of the transistors 104A to 104C, and one terminal (also referred to as the first terminal) serving as the source terminal or the drain terminal is connected to a current supply line (also referred to as a power supply line) for passing current to the light-emitting elements 123A to 123C, and the other terminal (also referred to as the second terminal) serving as the source terminal or the drain terminal is connected to one electrode (also referred to as the first electrode) of the light-emitting elements 123A to 123C. The other electrodes (also referred to as the second electrodes) of the light-emitting elements 123A to 123 C are connected to the ground line (also referred to as a common potential line). The other electrodes (also referred to as the second electrodes) of the light-emitting elements 123A to 123 C are connected to the ground line (also referred to as a common potential line). The other electrodes (also referred to as the second electrodes) of the light-emitting elements 123A to 123 C are connected to the ground line (also referred to as a common potential line). The other electrodes (also referred to as the second electrodes) of the light-emitting elements 123A to 123 C are connected to the ground line (also referred to as a common potential line). The other electrodes (also referred to as the second electrodes) of the light-emitting elements 123A to 123 C are connected to the ground line (also referred to as a common potential line). Between the gate terminals of transistors 124A to 124C and the first terminal A configuration in which a capacitive element may be provided may be adopted.

[0040] Next, a top view of a circuit diagram of the display element portions 105A to 105C shown in FIG. 2(A) having liquid crystal elements will be specifically shown, and the area of the intersection formed by the first data lines 102A to the third data lines 102C in one aspect of the present invention will be made equal, and the advantage that a load capacitance can be formed evenly on each of the data lines will be described.

[0041] The top view shown in FIG. 3 corresponds to the top view of the circuit diagram shown in FIG. 2(A). In FIG. 3, the capacitive elements 122A to 122C described in FIG. 2(A) are omitted for explanation, and as a configuration corresponding to the liquid crystal elements 121A to 121C, one electrode 131A to 131C (pixel electrode) of the liquid crystal elements 121A to 1 21C is shown. Also, the first data lines 102A to the third data lines 102C shown in FIG. 3 are provided in a direction orthogonal to the scanning lines 103A to the scanning lines 103C, and in addition to the conductive layer (first conductive layer 141), at the intersections 106 to 111, the same conductive layer (second conductive layer 142) as the scanning lines 103A to 103C is provided.

[0042] In the top view shown in FIG. 3, at the intersections 106 to 111, a load capacitance is formed in the region where the first conductive layer 141 and the second conductive layer 142 overlap. Specifically, at the intersection 106 between the first conductive layer 141 of the third data line 102C and the second conductive layer 142 of the second data line 102B, a load capacitance is formed. Also, at the intersection of the first data line 10 and the second conductive layer 142 of the second data line 102B, a load capacitance is formed. Also, at the intersection of the first data line 10 ​The first conductive layer 141 of 2A and the second conductive layer 142 of the second data line 102B A load capacitance is formed at the intersection 107 therebetween. Also, the first conductive layer 141 of the first data line 102A and the second conductive layer 142 of the third data line 102C form a load capacitance at the intersection 108 therebetween. Also, the first conductive layer 141 of the second data line 102B and the second conductive layer 142 of the third data line 102C form a load capacitance at the intersection 109 therebetween . Also, the first conductive layer 141 of the second data line 102B and the second conductive layer 142 of the first data line 1 02A form a load capacitance at the intersection 110 therebetween. Also, the first conductive layer 141 of the third data line 102C and the second conductive layer 142 of the first data line 102A form a load capacitance at the intersection 111 therebetween. And between the first data line 10 2A to the third data line 102C, the number of intersections (intersections 106 to 111) formed using the first conductive layer 141 and the second conductive layer 142 can be made equal to each other. Therefore, by making the first data line 102A to the third data line 102C data lines with equal wiring widths , a load capacitance can be formed evenly for each of the data lines .

[0043] Therefore, in the configuration of this embodiment, the areas of the intersections formed with the first data line 102A to the third data line 102C can be made equal, so that a load capacitance can be formed evenly for each of the data lines . As a result, the load capacitances are equalized between the first data line 102A to the third data line 102C, and a signal with a desired potential can be supplied to each pixel . And the display device can prevent display gradation deviation and / or ​Signal delay can be reduced.

[0044] Also, in the first data line 102A to the third data line 102C shown in FIG. 3, by using conductive layers with different conductivity between the first conductive layer 141 and the second conductive layer 142, the wiring resistance of the first data line 102A to the third data line 102C may be different. In FIG. 4(A), it is a circuit diagram showing the second conductive layer 142 in the top view shown in FIG. 3 as a resistance element.

[0045] As shown in FIG. 4(A), the second conductive layer 142 constituting the intersection 106 in FIG. 3 is represented as the first resistance element 151B of the second data line 102B. Also, the second conductive layer 142 constituting the intersection 107 in FIG. 3 is represented as the second resistance element 152B of the second data line 102B. Also, the second conductive layer 142 constituting the intersection 108 in FIG. 3 is represented as the first resistance element 151C of the third data line 102C. Also, the second conductive layer 142 constituting the intersection 109 in FIG. 3 is represented as the second resistance element 152C of the third data line 102C. Also, the second conductive layer 142 constituting the intersection 110 in FIG. 3 is represented as the first resistance element 151A of the first data line 102A. Also, the second conductive layer 142 constituting the intersection 111 in FIG. 3 is represented as the second resistance element 152A of the first data line 102A. As shown in FIG. 4(A), in the configuration of this embodiment, the first data line 102A has the first resistance element 151A and the second resistance element 152A, and the second data line 102B has the first resistance element 151A and the second resistance element 152A.

[0046] element 151A and the second resistance element 152A, and the second data line 102B has the first resistance element 151B and the second resistance element 152B. ​It can be configured to include a first resistor element 151B and a second resistor element 152B, and the third data line 102C can include a first resistor element 151C and a second resistor element 152C. That is in the configuration of this embodiment, the number of resistor elements included in each of the first data line 102A to the third data line 102C can be made equal. Therefore, by configuring the second conductive layer 142 with the same conductive material and the same wiring width, the wiring resistance of the first data line 102A to the third data line 102C can be made uniform. In the configuration of this embodiment, each of the first data line 102A to the third data line 102C has a resistor element, and the number of resistor elements can be made equal. Therefore, by configuring the second conductive layer 142 with the same conductive material and the same wiring width, the wiring resistance of the first data line 102A to the third data line 102C can be made uniform. Moreover, the first resistor elements 151A to 151C and the second resistor elements 152A to 152C in the first data line 102A to the third data line 102C may be located at any position in the first data line 102A to the third data line 102C. For example, as shown in FIG. 4(B), a configuration may be adopted in which the second conductive layer 142 serving as a resistor element is provided and formed.

[0047] In the configuration of this embodiment, the first data line 102A to the third data line 102C include the first resistor elements 151A to 151C and the second resistor elements 152A to 152C. The first resistor elements 151A to 151C and the second resistor elements 152A to 152C may be located at any position in the first data line 102A to the third data line 102C. For example, as shown in FIG. 4(B), a configuration may be adopted in which the second conductive layer 142 serving as a resistor element is provided and formed. That is, it may be configured as such.

[0048] In the configuration of this embodiment, a display device having the first data line to the third data line as a plurality of wirings for supplying different signals to a plurality of pixels at the same timing has been described. However, the present invention is also applicable to other wirings. For example, in the configuration having the light-emitting elements described with reference to FIG. 2(B), the current supply lines for supplying current to the light-emitting elements 123A to 123C may be configured as shown in FIG. 5 to be divided into a first current supply line 125A, a second current supply line 125B, and a third current supply line 125C, and cross portions 161 to 166 may be provided. By providing the cross portions 161 to 166 in the first current supply line 125A, the second current supply line 125B, and the third current supply line 125C, the first current supply Although the configuration of the display device having the first data line to the third data line as a plurality of wirings for supplying different signals to a plurality of pixels at the same timing has been described, the present invention is also applicable to other wirings. For example, in the configuration having the light-emitting elements described with reference to FIG. 2(B), the current supply lines for supplying current to the light-emitting elements 123A to 123C may be configured as shown in FIG. 5 to be divided into a first current supply line 125A, a second current supply line 125B, and a third current supply line 125C, and cross portions 161 to 166 may be provided. In the configuration having the light-emitting elements described with reference to FIG. 2(B), the current supply lines for supplying current to the light-emitting elements 123A to 123C may be divided into a first current supply line 125A, a second current supply line 125B, and a third current supply line 125C as shown in FIG. 5, and cross portions 161 to 166 may be provided. In the configuration having the light-emitting elements described with reference to FIG. 2(B), the current supply lines for supplying current to the light-emitting elements 123A to 123C may be divided into a first current supply line 125A, a second current supply line 125B, and a third current supply line 125C as shown in FIG. 5, and cross portions 161 to 166 may be provided. By providing the cross portions 161 to 166 in the first current supply line 125A, the second current supply line 125B, and the third current supply line 125C, the first current supply line 125A, the second current supply line 125B, and the third current supply line 125C may be provided with the cross portions 161 to 166, so that the first current supply Arrange the first current supply line 125A to the third current supply line 125C in the immediate vicinity of one terminal of the transistors 124A to 124C, and connect one terminal of the transistors 124A to 124C to the first current supply line 125A to the third current supply line 125C without passing through the intersection with other wirings. Arrange them in the immediate vicinity of one terminal of the transistors 124A to 124C, and connect one terminal of the transistors 124A to 124C to the first current supply line 125A to the third current supply line 125C without passing through the intersection with other wirings. Arrange them in the immediate vicinity of one terminal of the transistors 124A to 124C, and connect one terminal of the transistors 124A to 124C to the first current supply line 125A to the third current supply line 125C without passing through the intersection with other wirings. It can be connected.

[0049] Therefore, in the configuration of this embodiment, the load capacitances can be evenly formed on each of the current supply lines in the same manner as the first data line 102A to the third data line 102C. As a result, the load capacitances of the first current supply line 125A to the third current supply line 125C are made equal, and signals of a desired potential can be supplied to each pixel. And the display device can reduce the display gradation deviation and / or signal delay caused by the difference in load capacitance between the wirings. Therefore, in the configuration of this embodiment, the load capacitances can be evenly formed on each of the current supply lines in the same manner as the first data line 102A to the third data line 102C. As a result, the load capacitances of the first current supply line 125A to the third current supply line 125C are made equal, and signals of a desired potential can be supplied to each pixel. And the display device can reduce the display gradation deviation and / or signal delay caused by the difference in load capacitance between the wirings. Therefore, in the configuration of this embodiment, the load capacitances can be evenly formed on each of the current supply lines in the same manner as the first data line 102A to the third data line 102C. As a result, the load capacitances of the first current supply line 125A to the third current supply line 125C are made equal, and signals of a desired potential can be supplied to each pixel. And the display device can reduce the display gradation deviation and / or signal delay caused by the difference in load capacitance between the wirings. Therefore, in the configuration of this embodiment, the load capacitances can be evenly formed on each of the current supply lines in the same manner as the first data line 102A to the third data line 102C. As a result, the load capacitances of the first current supply line 125A to the third current supply line 125C are made equal, and signals of a desired potential can be supplied to each pixel. And the display device can reduce the display gradation deviation and / or signal delay caused by the difference in load capacitance between the wirings. It can reduce the display gradation deviation and / or signal delay caused by the difference in load capacitance between the wirings.

[0050] As described above, the difference in load capacitance between the data lines or the current supply lines can be reduced. As a result, the display gradation deviation and / or signal delay caused by the difference in load capacitance can be reduced. As described above, the difference in load capacitance between the data lines or the current supply lines can be reduced. As a result, the display gradation deviation and / or signal delay caused by the difference in load capacitance can be reduced. It can reduce the display gradation deviation and / or signal delay caused by the difference in load capacitance.

[0051] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0052] (Embodiment 2) In this embodiment, a configuration different from that of the above-described Embodiment 1 will be described with reference to FIGS. 6 and 7. Note that the difference between the configuration shown in this embodiment and the configurations shown in FIGS. 1 and 2 described in the above Embodiment 1 is that a plurality of scanning lines are provided as a plurality of wirings. Specifically, in the circuit diagram shown in this embodiment, a plurality of wirings for supplying different signals to a plurality of pixels at the same timing Note that the difference between the configuration shown in this embodiment and the configurations shown in FIGS. 1 and 2 described in the above Embodiment 1 is that a plurality of scanning lines are provided as a plurality of wirings. Specifically, in the circuit diagram shown in this embodiment, a plurality of wirings for supplying different signals to a plurality of pixels at the same timing Note that the difference between the configuration shown in this embodiment and the configurations shown in FIGS. 1 and 2 described in the above Embodiment 1 is that a plurality of scanning lines are provided as a plurality of wirings. Specifically, in the circuit diagram shown in this embodiment, a plurality of wirings for supplying different signals to a plurality of pixels at the same timing Note that the difference between the configuration shown in this embodiment and the configurations shown in FIGS. 1 and 2 described in the above Embodiment 1 is that a plurality of scanning lines are provided as a plurality of wirings. Specifically, in the circuit diagram shown in this embodiment, a plurality of wirings for supplying different signals to a plurality of pixels at the same timing Using N scanning lines (where N is a natural number of 3 or more), different scanning signals are supplied to a plurality of pixels. An example will be described.

[0053] FIG. 6(A) shows the circuit configuration of the pixels included in the display device. In FIG. 6(A), for N scanning lines, specifically, the circuit configuration in the case where different scanning signals are supplied to three different pixels from three scanning lines is shown. Pixel 201A has a transistor 204A (also referred to as a selection transistor) and a display element section 205A. The transistor 204A of pixel 201A has its gate terminal connected to the first scanning line 203A, one terminal (also referred to as the first terminal) that becomes the source terminal or the drain terminal connected to the data line 202A, and the other terminal connected to the display element section 205A. Pixel 201B has a transistor 204B (also referred to as a selection transistor) and a display element section 205B. The transistor 204B of pixel 201B has its gate terminal connected to the second scanning line 203B, one terminal (also referred to as the first terminal) that becomes the source terminal or the drain terminal connected to the data line 202B, and the other terminal connected to the display element section 205B. Pixel 201C has a transistor 204C (also referred to as a selection transistor) and a display element section 205C. The transistor 204C of pixel 201C has its gate terminal connected to the third scanning line 203C, one terminal (also referred to as the first terminal) that becomes the source terminal or the drain terminal connected to the data line 202C, and the other terminal connected to the display element section 205C. The circuit configuration shown in FIG. 6(A) described above is, for example, to individually turn on (also referred to as the on state) the transistors 204A to 204C by the scanning signals of the first scanning line 203A to the third scanning line 203C, and display For example, by the scanning signals of the first scanning line 203A to the third scanning line 203C, the transistors 204A to 204C are individually turned on (also referred to as the on state) to display When supplying video signals to the display element sections 205A to 205C from the data lines 202A to 202C, it is an effective configuration.

[0054] When arranging pixels in a matrix, the first scanning line 203A to the third scanning line 20 3C is provided in a direction substantially orthogonal to the data lines 202A to 202C, and pixels 201A to 201C having transistors 204A to transistors 204C are provided along the first scanning line 203A to the third scanning line 203C. The circuit configuration shown in Fig. 6(A) provides the intersection of the first scanning line 203A to the third scanning line 203C so that each of the first scanning line 203A to the third scanning line 203C is disposed closest to the gate terminals of the transistors included in the corresponding pixels 201A to 201C. Then, the connection between the gate terminals of the transistors and the scanning lines disposed closest is made.

[0055] In Fig. 6(A), the intersection 206 is the region where the second scanning line 203B and the third scanning line 203C intersect. Also, the intersection 207 is the region where the first scanning line 203A and the second scanning line 203B intersect. Also, the intersection 208 is the region where the first scanning line 203A and the third scanning line 20 3C intersect. Also, the intersection 209 is the region where the second scanning line 203B and the third scanning line 203C intersect. Also, the intersection 210 is the region where the first scanning line 203A and the second scanning line 203B intersect. Also, the intersection 211 is the region where the first scanning line 203A and the third scanning line 203C intersect. And the first scanning line 203A is disposed closest to the gate terminal of the transistor 204A, and the gate terminal of the transistor 204A is arranged in other It will be connected without passing through an intersection with a line. Also, the second scanning line 203B is arranged in the immediate vicinity of the gate terminal of the transistor 204B, and the gate terminal of the transistor 204B will be connected without passing through an intersection with other wirings. Further, the third scanning line 203C is arranged in the immediate vicinity of the gate terminal of the transistor 204C, and the gate terminal of the transistor 204C will be connected without passing through an intersection with other wirings. It is arranged in the immediate vicinity of the gate terminal of the transistor 204B, and the gate terminal of the transistor 204B will be connected without passing through an intersection with other wirings. It will be connected without passing through an intersection with other wirings. Also, the third scanning line 203C is arranged in the immediate vicinity of the gate terminal of the transistor 204C, and the gate of the transistor 204C terminal will be connected without passing through an intersection with other wirings.

[0056] The intersections 206 to 211 shown in FIG. 6(A) are formed using another conductive layer for one of the intersecting scanning lines in order to avoid an electrical short circuit (short) between the first scanning line 203A to the third scanning line 203C. In the intersections 206 to 211 using the conductive layer, a load capacitance is formed between the intersecting scanning lines. The load capacitance is formed in a region where the intersecting scanning lines overlap, that is, in a region where the conductive layer forming the first scanning line 203A to the third scanning line 203C and another conductive layer at the intersection overlap. In order to avoid an electrical short circuit (short) between the intersecting scanning lines, one of the intersecting scanning lines will be formed using another conductive layer. In the intersections 206 to 211 using the conductive layer, a load capacitance is formed between the intersecting scanning lines. The load capacitance is formed in a region where the intersecting scanning lines overlap, that is, in a region where the conductive layer forming the first scanning line 203A to the third scanning line 203C and another conductive layer at the intersection overlap. It is formed in a region where the conductive layer forming the first scanning line 203A to the third scanning line 203C and another conductive layer at the intersection overlap.

[0057] FIG. 6(B) is a circuit diagram showing the intersections 206 to 211 due to the first scanning line 203A to the third scanning line 203C shown in FIG. 6(A) as load capacitances. In FIG. 6(B), similar to FIG. 6(A), the first scanning line 203A is connected to the first pixel 201A, the second scanning line 203B is connected to the second pixel 201B, and the third scanning line 203C is connected to the third pixel 201C. Also, in FIG. 6(B), the load capacitance caused by the intersection 206 shown in FIG. 6(A) is represented by the capacitance element 291, the load capacitance caused by the intersection 207 shown in FIG. 6(A) is represented by the capacitance element 292, and the load capacitance caused by the intersection 208 shown in FIG. 6(A) is represented by the capacitance element 2 In FIG. 6(B), the second scanning line 203B is connected to the second pixel 201B, and the third scanning line 203C is connected to the third pixel 201C. Also, in FIG. 6(B), the load capacitance caused by the intersection 206 shown in FIG. 6(A) is represented by the capacitance element 291, the load capacitance caused by the intersection 207 shown in FIG. 6(A) is represented by the capacitance element 292, and the load capacitance caused by the intersection 208 shown in FIG. 6(A) is represented by the capacitance element 2 In FIG. 6(B), the load capacitance caused by the intersection 208 shown in FIG. 6(A) is represented by the capacitance element 2 It is represented by 93, and the load capacitance caused by the intersection 209 shown in FIG. 6(A) is represented by the capacitive element 294. , the load capacitance caused by the intersection 210 shown in FIG. 6(A) is represented by the capacitive element 295, and FIG. 6(A ) the load capacitance caused by the intersection 211 shown in is represented by the capacitive element 296.

[0058] As shown in FIG. 6(B), between the first scanning line 203A and the second scanning line 203B, the capacitive elements 292 and the load capacitance due to the capacitive element 295 are formed. Also, between the second scanning line 203B and the third scanning line 203C, the load capacitance due to the capacitive element 291 and the capacitive element 294 is formed . Also, between the first scanning line 203A and the third scanning line 203C, the capacitive elements 293 and the load capacitance due to the capacitive element 296 is formed. As described above, the load capacitance is such that the first scanning line 20 3A to the third scanning line 203C, the conductive layer forming them, and another conductive layer at the intersection overlap in the region where it is formed. Therefore, in the configuration of the present embodiment, the first scanning line 203A to the third scanning line 203C are made into scanning lines with the same wiring width, so that each of the scanning lines can form a load capacitance evenly.

[0059] Therefore, in the configuration of the present embodiment, the area of the intersection between the first scanning line 203A to the third scanning line 203C can be made equal, so that a load capacitance can be formed evenly for each of the scanning lines . As a result, the load capacitance is made even between the first scanning line 203A to the third scanning line 203C, and a scanning signal can be supplied to each pixel at a desired timing. And the display device can reduce the delay of the scanning signal due to the difference in the load capacitance between the wirings. .

[0060] Next, FIGS. 7(A) and 7(B) will explain an example of a specific display element for the display element units 205A to 205C shown in FIG. 6(A). In the description of FIGS. 7(A) and 7(B), explanation of the parts overlapping with the configurations other than the display element units 205A to 205C shown in FIG. 6(A) will be omitted. The circuit diagram shown in FIG. 7(A) shows an example in the case where the display element units 205A to 205C shown in FIG. 6(A) have a liquid crystal element configuration. The display element unit 205A shown in FIG. 7(A) has a liquid crystal element 221A and a capacitor element 222A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204A. The display element unit 205B shown in FIG. 7(A) has a liquid crystal element 221B and a capacitor element 222B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204B. The display element unit 205C shown in FIG. 7(A) has a liquid crystal element 221C and a capacitor element 222C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204C. Note that for the liquid crystal elements 221A to 221C, one electrode (also referred to as a pixel electrode or a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a counter electrode or a second electrode) is connected to a common potential line (also referred to as a common line). Also, for the capacitor elements 222A to 222C, one electrode (also referred to as a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a second electrode) is connected to a capacitor line. Note that the capacitor elements 222A to 222C may be provided as necessary. The circuit diagram shown in FIG. 7(A) shows an example in the case where the display element units 205A to 205C shown in FIG. 6(A) have a liquid crystal element configuration. The display element unit 205A shown in FIG. 7(A) has a liquid crystal element 221A and a capacitor element 222A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204A. The display element unit 205B shown in FIG. 7(A) has a liquid crystal element 221B and a capacitor element 222B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204B. The display element unit 205C shown in FIG. 7(A) has a liquid crystal element 221C and a capacitor element 222C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204C. Note that for the liquid crystal elements 221A to 221C, one electrode (also referred to as a pixel electrode or a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a counter electrode or a second electrode) is connected to a common potential line (also referred to as a common line). Also, for the capacitor elements 222A to 222C, one electrode (also referred to as a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a second electrode) is connected to a capacitor line. Note that the capacitor elements 222A to 222C may be provided as necessary.

[0061] The circuit diagram shown in FIG. 7(A) shows an example in the case where the display element units 205A to 205C shown in FIG. 6(A) have a liquid crystal element configuration. The display element unit 205A shown in FIG. 7(A) has a liquid crystal element 221A and a capacitor element 222A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204A. The display element unit 205B shown in FIG. 7(A) has a liquid crystal element 221B and a capacitor element 222B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204B. The display element unit 205C shown in FIG. 7(A) has a liquid crystal element 221C and a capacitor element 222C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204C. Note that for the liquid crystal elements 221A to 221C, one electrode (also referred to as a pixel electrode or a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a counter electrode or a second electrode) is connected to a common potential line (also referred to as a common line). Also, for the capacitor elements 222A to 222C, one electrode (also referred to as a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a second electrode) is connected to a capacitor line. Note that the capacitor elements 222A to 222C may be provided as necessary. The circuit diagram shown in FIG. 7(A) shows an example in the case where the display element units 205A to 205C shown in FIG. 6(A) have a liquid crystal element configuration. The display element unit 205A shown in FIG. 7(A) has a liquid crystal element 221A and a capacitor element 222A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204A. The display element unit 205B shown in FIG. 7(A) has a liquid crystal element 221B and a capacitor element 222B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204B. The display element unit 205C shown in FIG. 7(A) has a liquid crystal element 221C and a capacitor element 222C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204C. Note that for the liquid crystal elements 221A to 221C, one electrode (also referred to as a pixel electrode or a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a counter electrode or a second electrode) is connected to a common potential line (also referred to as a common line). Also, for the capacitor elements 222A to 222C, one electrode (also referred to as a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a second electrode) is connected to a capacitor line. Note that the capacitor elements 222A to 222C may be provided as necessary. The display element unit 205A shown in FIG. 7(A) has a liquid crystal element 221A and a capacitor element 222A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204A. The display element unit 205A shown in FIG. 7(A) has a liquid crystal element 221A and a capacitor element 222A connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204A. The display element unit 205B shown in FIG. 7(A) has a liquid crystal element 221B and a capacitor element 222B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204B. The display element unit 205B shown in FIG. 7(A) has a liquid crystal element 221B and a capacitor element 222B connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204B. The display element unit 205C shown in FIG. 7(A) has a liquid crystal element 221C and a capacitor element 222C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204C. The display element unit 205C shown in FIG. 7(A) has a liquid crystal element 221C and a capacitor element 222C connected to the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal of the transistor 204C. Note that for the liquid crystal elements 221A to 221C, one electrode (also referred to as a pixel electrode or a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a counter electrode or a second electrode) is connected to a common potential line (also referred to as a common line). Note that for the liquid crystal elements 221A to 221C, one electrode (also referred to as a pixel electrode or a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a counter electrode or a second electrode) is connected to a common potential line (also referred to as a common line). Also, for the capacitor elements 222A to 222C, one electrode (also referred to as a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a second electrode) is connected to a capacitor line. Also, for the capacitor elements 222A to 222C, one electrode (also referred to as a first electrode) is connected to the other terminal of the transistors 204A to 204C, and the other electrode (also referred to as a second electrode) is connected to a capacitor line. Note that the capacitor elements 222A to 222C may be provided as necessary. Note that the capacitor elements 222A to 222C may be provided as necessary. Note that the capacitor elements 222A to 222C may be provided as necessary. <, it is also possible to omit.

[0062] The circuit diagram shown in Fig. 7(B) shows the display element parts 205A to 20 5C having a light-emitting element such as an EL (Electro Luminescence) element. This is an example of a case where it is configured. The display element part 205A shown in Fig. 7(B) has a light-emitting element 223A and a transistor 224A (also referred to as a driving transistor) for driving the light-emitting element 223A. The display element part 205B shown in Fig. 7(B) has a light-emitting element 223 B and a transistor 224B (also referred to as a driving transistor) for driving the light-emitting element 223B. The display element part 205C shown in Fig. 7(B) has a light-emitting element 223C and a transistor 224C (also referred to as a driving transistor) for driving the light-emitting element 223C. Note that the transistors 224A to 224C have their gate terminals connected to the other terminals of the transistors 204A to 204C, and one terminal (also referred to as the first terminal) that becomes the source terminal or the drain terminal is connected to a current supply line (also referred to as a power supply line) for flowing current to the light-emitting elements 223A to 223C, and the other terminal (also referred to as the second terminal) that becomes the source terminal or the drain terminal is connected to one electrode (also referred to as the first electrode) of the light-emitting elements 223A to 223C. The other electrodes (also referred to as the second electrodes) of the light-emitting elements 223A to 223C are connected to a ground line (also referred to as a common potential line). A capacitor element may be provided between the gate terminals and the first terminals of the transistors 224A to 224C.

[0063]

[0063] ​​​From the above, the difference in the load capacity of the scanning lines can be reduced. As a result, the delay of the scanning signal due to the difference in the load capacity can be reduced.

[0064] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0065] (Embodiment 3) In this embodiment, an example of a display device that performs field sequential display with the circuit configuration described in Embodiment 1 will be described with reference to FIGS. 8 to 11. Note that in the display device of this embodiment, a liquid crystal display device using a liquid crystal element as a display element will be described.

[0066] <Configuration Example of Liquid Crystal Display Device> FIG. 8(A) is a diagram showing a configuration example of a liquid crystal display device. The liquid crystal display device shown in FIG. 8(A) includes a pixel portion 30, a scanning line driving circuit 31, a data line driving circuit 32 (also referred to as a signal line driving circuit), 3n scanning lines 33 (where n is a natural number of 2 or more) that are each arranged in parallel or substantially parallel and whose potential is controlled by the scanning line driving circuit 31, and m first data lines 341 (where m is a natural number of 2 or more), m second data lines 342, and m third data lines 3 43 that are each arranged in parallel or substantially parallel and whose potential is controlled by the data line driving circuit 32.

[0067] Furthermore, the pixel portion 30 is divided into three regions (regions 301 to 303), and each region has a plurality of pixels arranged in a matrix (n rows and m columns). Note that each scanning line 33 is one of the plurality of pixels arranged in a matrix (3n rows and m columns) in the pixel portion 30. ​​​​is connected to m pixels arranged in the row. Also, each first data line 341 is connected to n pixels arranged in any one of a plurality of pixels 351 arranged in a matrix (n rows and m columns) in region 30 1. Further, each second data line 342 is connected to n pixels arranged in any one of a plurality of pixels 352 arranged in a matrix (n rows and m columns) in region 302 . Also, each third data line 343 is connected to n pixels arranged in any one of a plurality of pixels 353 arranged in a matrix (n rows and m columns) in region 303 . Note that, as described in the first embodiment, the first data line 341 to the third data line 3 43 are provided with the intersection portion 361, and the first data line 341 to the third data line 343 are arranged closest to one terminal of the transistors of the pixels in regions 301 to 303 . Therefore, a load capacitance can be formed evenly on each of the first data line 341 to the third data line 343. As a result, a video signal with a desired potential can be supplied to each pixel, and display gradation deviation and / or signal delay caused by the difference in load capacitance between the data lines can be reduced . Note that a start signal for the scanning line driving circuit (GSP), a clock signal for the scanning line driving circuit (GCK), and driving power supplies such as a high power supply potential and a low power supply potential are input to the scanning line driving circuit 31 . Also, a start signal for the data line driving circuit (SSP), a clock signal for the data line driving circuit (SCK), signals such as image signals (data1 to data3), and driving power supplies such as a high power supply potential and a low power supply potential are input to the data line driving circuit 32 .

[0068] Note that a start signal for the scanning line driving circuit (GSP), a clock signal for the scanning line driving circuit (GCK), and driving power supplies such as a high power supply potential and a low power supply potential are input to the scanning line driving circuit 31 . Also, a start signal for the data line driving circuit (SSP), a clock signal for the data line driving circuit (SCK), signals such as image signals (data1 to data3), and driving power supplies such as a high power supply potential and a low power supply potential are input to the data line driving circuit 32 . Also, signals such as a start signal for the data line driving circuit (SSP), a clock signal for the data line driving circuit (SCK), image signals (data1 to data3), and driving power supplies such as a high power supply potential and a low power supply potential are input to the data line driving circuit 32

[0069] Figs. 8(B) to 8(D) are diagrams showing circuit configuration examples of pixels. Specifically, Fig. 8(B ) is a diagram showing a circuit configuration example of pixel 351 disposed in region 301, Fig. 8(C) is a diagram showing a circuit configuration example of pixel 352 disposed in region 302, and Fig. 8(D) is a diagram showing a circuit configuration example of pixel 353 disposed in region 3 03. Pixel 351 shown in Fig. 8(B ) includes transistor 3511 having a gate terminal connected to scanning line 33 and one of the source and drain terminals connected to first data line 341, capacitor element 3512 having one electrode connected to the other one of the source and drain terminals of transistor 3511 and the other electrode connected to a capacitance line, and liquid crystal element 3514 having one electrode (pixel electrode) connected to the other one of the source and drain terminals of transistor 3511 and one electrode of capacitor element 3512

[0070] and the other electrode (opposing electrode) connected to a wiring for supplying an opposing potential. The circuit configurations of pixel 352 shown in Fig. 8(C) and pixel 353 shown in Fig. 8(D) are the same as that of pixel 351 shown in Fig. 8( B). However, in pixel 352 shown in Fig. 8(C), one of the source and drain of transistor 3521 is connected to second data line 342 instead of first data line 341, which is different from pixel 351 shown in Fig. 8(B). In pixel 353 shown in Fig. 8(D), one of the source and drain of transistor 3531 is connected to third data line 343 instead of first data line 34

[0071] <Configuration Example of Scanning Line Driving Circuit 31> Fig. 9(A) shows a configuration example of scanning line driving circuit 31 included in the liquid crystal This is a schematic diagram. The scanning line driving circuit 31 shown in FIG. 9(A) has shift registers 311 to 313 having n output terminals. Each of the output terminals of the shift register 311 is connected to any one of the n scanning lines 33 arranged in the region 301. Each of the output terminals of the shift register 312 is connected to any one of the n scanning lines 33 arranged in the region 302. Each of the output terminals of the shift register 313 is connected to any one of the n scanning lines 33 arranged in the region 303. That is, the shift register 311 is a shift register that supplies a scanning signal in the region 301, the shift register 312 is a shift register that supplies a scanning signal in the region 302, and the shift register 313 is a shift register that supplies a scanning signal in the region 303. Specifically, the shift register 311 has a function of sequentially shifting a scanning signal starting from the scanning line 33 arranged in the first row, triggered by a start pulse signal (GSP) for the scanning line driving circuit input from the outside (selecting the scanning line 33 sequentially every half cycle of the clock signal (GCK) for the scanning line driving circuit). The shift register 312 has a function of sequentially shifting a scanning signal starting from the scanning line 33 arranged in the (n + 1)-th row, triggered by a start pulse signal (GSP) for the scanning line driving circuit input from the outside. The shift register 313 has a function of sequentially shifting a scanning signal starting from the scanning line 33 arranged in the (2n + 1)-th row, triggered by a start pulse signal (GSP) for the scanning line driving circuit input from the outside.

[0072] <Operating Example of Scanning Line Driving Circuit 31> An operating example of the scanning line driving circuit 31 described above will be described with reference to FIG. 9(B).​ In 9(B), there are shown a clock signal (GCK) for a scanning line driving circuit, a signal (SR311out) output from n output terminals of the shift register 311, a signal (SR312out) output from n output terminals of the shift register 312, and a signal (SR313out) output from n output terminals of the shift register 313. In the sampling period (T1), in the shift register 311, the high-level potential sequentially shifts from the scanning line 33 arranged in the first row to the scanning line 33 arranged in the n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 312, the high-level potential sequentially shifts from the scanning line 33 arranged in the (n + 1)-th row to the scanning line 33 arranged in the 2n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 313, the high-level potential sequentially shifts from the scanning line 33 arranged in the (2n + 1)-th row to the scanning line 33 arranged in the 3n-th row every 1 / 2 clock cycle (horizontal scanning period). Therefore, the scanning line driving circuit 31 sequentially selects m pixels 351 arranged in the first row to m pixels 351 arranged in the n-th row via the scanning line 33, sequentially selects m pixels 352 arranged in the (n + 1)-th row to m pixels 352 arranged in the 2n-th row, and sequentially selects m pixels 353 arranged in the (2n + 1)-th row to m pixels 353 arranged in the 3n-th row. That is, the scanning line driving circuit 31 can supply a scanning signal to 3m pixels arranged in three different rows for each horizontal scanning period. In the sampling periods (T2) and (T3), the shift register 31

[0073] In the sampling period (T1), in the shift register 311, starting from the scanning line 33 arranged in the first row, the high-level potential shifts sequentially to the scanning line 33 arranged in the n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 312, starting from the scanning line 33 arranged in the (n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 2n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 313, starting from the scanning line 33 arranged in the (2n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 3n-th row every 1 / 2 clock cycle (horizontal scanning period). As a result, the scanning line driving circuit 31 sequentially selects the m pixels 351 arranged in the first row to the m pixels 351 arranged in the n-th row via the scanning line 33, sequentially selects the m pixels 352 arranged in the (n + 1)-th row to the m pixels 352 arranged in the 2n-th row, and sequentially selects the m pixels 353 arranged in the (2n + 1)-th row to the m pixels 353 arranged in the 3n-th row. That is, the scanning line driving circuit 31 can supply a scanning signal to 3m pixels arranged in three different rows for each horizontal scanning period. In the sampling period (T1), in the shift register 311, starting from the scanning line 33 arranged in the first row, the high-level potential shifts sequentially to the scanning line 33 arranged in the n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 312, starting from the scanning line 33 arranged in the (n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 2n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 313, starting from the scanning line 33 arranged in the (2n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 3n-th row every 1 / 2 clock cycle (horizontal scanning period). As a result, the scanning line driving circuit 31 sequentially selects the m pixels 351 arranged in the first row to the m pixels 351 arranged in the n-th row via the scanning line 33, sequentially selects the m pixels 352 arranged in the (n + 1)-th row to the m pixels 352 arranged in the 2n-th row, and sequentially selects the m pixels 353 arranged in the (2n + 1)-th row to the m pixels 353 arranged in the 3n-th row. That is, the scanning line driving circuit 31 can supply a scanning signal to 3m pixels arranged in three different rows for each horizontal scanning period. In the sampling period (T1), in the shift register 311, starting from the scanning line 33 arranged in the first row, the high-level potential shifts sequentially to the scanning line 33 arranged in the n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 312, starting from the scanning line 33 arranged in the (n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 2n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 313, starting from the scanning line 33 arranged in the (2n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 3n-th row every 1 / 2 clock cycle (horizontal scanning period). As a result, the scanning line driving circuit 31 sequentially selects the m pixels 351 arranged in the first row to the m pixels 351 arranged in the n-th row via the scanning line 33, sequentially selects the m pixels 352 arranged in the (n + 1)-th row to the m pixels 352 arranged in the 2n-th row, and sequentially selects the m pixels 353 arranged in the (2n + 1)-th row to the m pixels 353 arranged in the 3n-th row. That is, the scanning line driving circuit 31 can supply a scanning signal to 3m pixels arranged in three different rows for each horizontal scanning period. In the sampling period (T1), in the shift register 311, starting from the scanning line 33 arranged in the first row, the high-level potential shifts sequentially to the scanning line 33 arranged in the n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 312, starting from the scanning line 33 arranged in the (n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 2n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 313, starting from the scanning line 33 arranged in the (2n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 3n-th row every 1 / 2 clock cycle (horizontal scanning period). As a result, the scanning line driving circuit 31 sequentially selects the m pixels 351 arranged in the first row to the m pixels 351 arranged in the n-th row via the scanning line 33, sequentially selects the m pixels 352 arranged in the (n + 1)-th row to the m pixels 352 arranged in the 2n-th row, and sequentially selects the m pixels 353 arranged in the (2n + 1)-th row to the m pixels 353 arranged in the 3n-th row. That is, the scanning line driving circuit 31 can supply a scanning signal to 3m pixels arranged in three different rows for each horizontal scanning period. In the sampling period (T1), in the shift register 311, starting from the scanning line 33 arranged in the first row, the high-level potential shifts sequentially to the scanning line 33 arranged in the n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 312, starting from the scanning line 33 arranged in the (n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 2n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 313, starting from the scanning line 33 arranged in the (2n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 3n-th row every 1 / 2 clock cycle (horizontal scanning period). As a result, the scanning line driving circuit 31 sequentially selects the m pixels 351 arranged in the first row to the m pixels 351 arranged in the n-th row via the scanning line 33, sequentially selects the m pixels 352 arranged in the (n + 1)-th row to the m pixels 352 arranged in the 2n-th row, and sequentially selects the m pixels 353 arranged in the (2n + 1)-th row to the m pixels 353 arranged in the 3n-th row. That is, the scanning line driving circuit 31 can supply a scanning signal to 3m pixels arranged in three different rows for each horizontal scanning period. In the sampling period (T1), in the shift register 311, starting from the scanning line 33 arranged in the first row, the high-level potential shifts sequentially to the scanning line 33 arranged in the n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 312, starting from the scanning line 33 arranged in the (n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 2n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 313, starting from the scanning line 33 arranged in the (2n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 3n-th row every 1 / 2 clock cycle (horizontal scanning period). As a result, the scanning line driving circuit 31 sequentially selects the m pixels 351 arranged in the first row to the m pixels 351 arranged in the n-th row via the scanning line 33, sequentially selects the m pixels 352 arranged in the (n + 1)-th row to the m pixels 352 arranged in the 2n-th row, and sequentially selects the m pixels 353 arranged in the (2n + 1)-th row to the m pixels 353 arranged in the 3n-th row. That is, the scanning line driving circuit 31 can supply a scanning signal to 3m pixels arranged in three different rows for each horizontal scanning period. In the sampling period (T1), in the shift register 311, starting from the scanning line 33 arranged in the first row, the high-level potential shifts sequentially to the scanning line 33 arranged in the n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 312, starting from the scanning line 33 arranged in the (n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 2n-th row every 1 / 2 clock cycle (horizontal scanning period). In the shift register 313, starting from the scanning line 33 arranged in the (2n + 1)-th row, the high-level potential shifts sequentially to the scanning line 33 arranged in the 3n-th row every 1 / 2 clock cycle (horizontal scanning period).

[0074] In the sampling periods (T2) and (T3), the shift register 31 The operations of the shift registers 311 to 313 are the same as the sampling period (T1). That is, similarly to the sampling period (T1), the scanning line driving circuit 31 can supply a scanning signal to 3m pixels arranged in three specific rows for each horizontal scanning period.

[0075] <Configuration Example of Data Line Driving Circuit 32> FIG. 10(A) is a diagram showing a configuration example of the data line driving circuit 32 included in the liquid crystal display device shown in FIG. 8(A). The data line driving circuit 32 shown in FIG. 10(A) includes a shift register 320 having m output terminals, m transistors 321, m transistors 322, and m transistors 323. The gate terminal of transistor 321 is connected to the j-th (j is a natural number from 1 to m) output terminal of the shift register 320, one of the source and drain terminals is connected to a wiring for supplying the first image signal (data1), and the other of the source and drain terminals is connected to the first data line 341 arranged in the j-th column in the pixel section 30. Also, the gate terminal of transistor 322 is connected to the j-th (j is a natural number from 1 to m) output terminal of the shift register 320, one of the source and drain terminals is connected to a wiring for supplying the second image signal (data2), and the other of the source and drain terminals is connected to the second data line 342 arranged in the j-th column in the pixel section 30. Also, the gate terminal of transistor 323 is connected to the j-th (j is a natural number from 1 to m) output terminal of the shift register 320, one of the source and drain terminals is connected to a wiring for supplying the third image signal (data3), and the other of the source and drain terminals is connected to the third data line 343 arranged in the j-th column in the pixel section 30. The other terminal of the source and the drain is connected to the third data line disposed in the j-th column in the pixel portion 30. It is connected to 343.

[0076] Here, the first image signal (data1) is during the sampling period (T1), the image signal of red (R) (the image signal held in the pixel when the backlight lights up red (R)) is supplied to the first data line 341, and during the sampling period (T2), green (G) the image signal is supplied to the first data line 341, and during the sampling period (T3) the image signal of blue (B) is supplied to the first data line 341. Also, the second image signal (data2) is the image signal of blue (B) supplied to the second data line 342 during the sampling period (T1), and the image signal of red (R) is supplied to the second data line 342 during the sampling period (T2), and the image signal of green (G) is supplied to the second data line 342 during the sampling period (T3). Also, the third image signal (data3) is the image signal of green (G) supplied to the third data line 343 during the sampling period (T1) and the image signal of blue (B) is supplied to the third data line 34 3 during the sampling period (T2), and the image signal of red (R) is supplied to the third data line 343 during the sampling period (T3).

[0077] <Configuration Example of Backlight> FIG. 10(B) is a diagram showing a configuration example of a backlight provided behind the pixel portion 30 of the liquid crystal display device shown in FIG. 8(A). The backlight shown in FIG. 10(B) has a plurality of backlight units 36 each including a light source exhibiting three colors of red (R), green (G ), and blue (B). Note that ) , A plurality of backlight units 36 are arranged in a matrix and can control lighting for specific regions each. Here, as a backlight for a plurality of pixels arranged in 3n rows and m columns, at least every k rows and m columns (here, k is set to n / 4) a backlight unit 36 is provided, and the lighting of the backlight unit 36 can be independently controlled . That is, the backlight has a backlight unit for pixels from at least the first row to the k-th row ~ a backlight unit for pixels from the 2n + 3k + 1-th row to the 3n-th row, and it is assumed that the lighting of each backlight unit can be independently controlled.

[0078] <Operating Example of Liquid Crystal Display Device> FIG. 11 is a diagram showing the scanning of the scanning signal and the lighting timing of the backlight in the above-described liquid crystal display device. In the liquid crystal display device during the sampling period (T1), m pixels 351 arranged in the first row are sequentially selected from the m pixels 351 arranged in the n-th row, and m pixels 352 arranged in the (n + 1)-th row are sequentially selected from the m pixels 352 arranged in the 2n-th row, and m pixels 353 arranged in the (2n + 1)-th row are sequentially selected from the m pixels 353 arranged in the 3n-th row, so that an image signal can be input to each pixel

[0079] Also, in the liquid crystal display device shown in FIG. 11, the scanning of the scanning signal and the lighting timing of the backlight can be set such that the scanning of the scanning signal and the lighting of the backlight unit presenting a specific color (red (R), green (G ), or blue (B)) are performed in parallel for each region (the first row to the n-th row, the (n + 1)-th row to the 2n-th row, and the (2n + 1)-th row to the 3n-th row). Note that In the liquid crystal display device of this embodiment, one image is formed in the pixel portion 30 by the operations performed during the sampling period (T1) to the sampling period (T3 ). That is, in this liquid crystal display device, the sampling period (T1) to the sampling period (T3) are one frame period.

[0080] <Regarding the liquid crystal display device of this embodiment> For the liquid crystal display device of this embodiment, the first data line to which the configuration of the above-described Embodiment 1 can be applied 341 to the third data line 343 can form a load capacitance evenly on each wiring. As a result, a video signal having a desired potential can be supplied to each pixel, and display gradation shift and / or signal delay caused by the difference in load capacitance between the data lines can be reduced .

[0081] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments .

[0082] (Embodiment 4) In this embodiment, an example of a plan view and a cross-sectional view of a pixel included in a display device, here a liquid crystal display device, will be described with reference to the drawings.

[0083] FIG. 12(A) shows a plan view of one of a plurality of pixels included in a display panel. FIG. 12(B ) is a cross-sectional view taken along the dashed line A - B in FIG. 12(A).

[0084] In FIG. 12(A), the wiring layers (including the source electrode layers 1201A to 1201C and the drain electrode layer 1202) that become the first data line to the third data line are arranged to extend in the vertical direction (column direction) in the figure. The wiring layer (gate electrode layer 1 including 203) extends in a direction (the left - right direction (row direction) in the figure) that is substantially orthogonal to the source electrode layers 1201A to 1201C. The capacitance wiring layer 1204 is arranged to extend in a direction that is substantially parallel to the gate electrode layer 1203 and substantially orthogonal to the source electrode layers 1201A to 1201C (the left - right direction (row direction) in the figure). The intersection 1209 is formed by a wiring layer formed in the same layer as the gate electrode layer 1203 and the capacitance wiring layer 12 04, showing the state where the source electrode layers 1201B and 1201C intersect. In FIG. 12(A), a transistor 1205 having a gate electrode layer 1203 is provided in the pixel of the display panel. On the transistor 1205, an insulating film 1227, an insulating film 1228, and an interlayer film 1229 are provided. The pixel of the display panel shown in FIGS. 12(A) and 12(B) has a transparent electrode layer 1208 as a first electrode layer connected to the transistor 1205. Openings (contact holes) are formed in the insulating film

[0085] 1227, the insulating film 1228, and the interlayer film 1229 on the transistor 1205. In the opening (contact hole), the transparent electrode layer 1208 and the transistor 1 205 are connected. The transistor 1205 shown in FIGS. 12(A) and 12(B) has a semiconductor layer 1206 disposed on the gate electrode layer 1203 with a gate insulating layer 1212 interposed therebetween, and has a source electrode layer 1201A and a drain electrode layer 1202 in contact with the semiconductor layer 1206. Also, the capacitance wiring layer

[0086] 1204, the gate insulating layer 1212, and the drain electrode layer 1202 are stacked to form a capacitance element 1 The pixel of the display panel shown in FIGS. 12(A) and 12(B) has a transparent electrode layer 1208 as a first electrode layer connected to the transistor 1205. Openings (contact holes) are formed in the insulating film 1227, the insulating film 1228, and the interlayer film 1229 on the transistor 1205. In the opening (contact hole), the transparent electrode layer 1208 and the transistor 1205 are connected. 1227, the insulating film 1228, and the interlayer film 1229 on the transistor 1205. In the opening (contact hole), the transparent electrode layer 1208 and the transistor 1205 are connected. 1227, the insulating film 1228, and the interlayer film 1229 on the transistor 1205. In the opening (contact hole), the transparent electrode layer 1208 and the transistor 1205 are connected. 1227, the insulating film 1228, and the interlayer film 1229 on the transistor 1205. In the opening (contact hole), the transparent electrode layer 1208 and the transistor 1205 are connected.

[0087] The transistor 1205 shown in FIGS. 12(A) and 12(B) has a semiconductor layer 1206 disposed on the gate electrode layer 1203 with a gate insulating layer 1212 interposed therebetween, and has a source electrode layer 1201A and a drain electrode layer 1202 in contact with the semiconductor layer 1206. Also, the capacitance wiring layer 1204, the gate insulating layer 1212, and the drain electrode layer 1202 are stacked to form a capacitance element 1 The transistor 1205 shown in FIGS. 12(A) and 12(B) has a semiconductor layer 1206 disposed on the gate electrode layer 1203 with a gate insulating layer 1212 interposed therebetween, and has a source electrode layer 1201A and a drain electrode layer 1202 in contact with the semiconductor layer 1206. Also, the capacitance wiring layer 1204, the gate insulating layer 1212, and the drain electrode layer 1202 are stacked to form a capacitance element 1 The transistor 1205 shown in FIGS. 12(A) and 12(B) has a semiconductor layer 1206 disposed on the gate electrode layer 1203 with a gate insulating layer 1212 interposed therebetween, and has a source electrode layer 1201A and a drain electrode layer 1202 in contact with the semiconductor layer 1206. Also, the capacitance wiring layer 1204, the gate insulating layer 1212, and the drain electrode layer 1202 are stacked to form a capacitance element 1 1204, the gate insulating layer 1212, and the drain electrode layer 1202 are stacked to form a capacitance element 1 It forms 207.

[0088] In addition, the first substrate 1218 on which the transistor 1205 is formed is arranged to overlap with the second substrate 1219 with the liquid crystal layer 1217 interposed therebetween. It is arranged to overlap with the second substrate 1219 with the liquid crystal layer 1217 interposed therebetween.

[0089] In FIG. 12(B), an example of using an inverted staggered transistor with a bottom gate structure as the transistor 1205 is shown, but the structure of the transistor applicable to the liquid crystal display device disclosed in this specification is not particularly limited. For example, a transistor with a top gate structure in which a gate electrode layer is arranged above a semiconductor layer via a gate insulating layer, and a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. In FIG. 12(B), an example of using an inverted staggered transistor with a bottom gate structure as the transistor 1205 is shown, but the structure of the transistor applicable to the liquid crystal display device disclosed in this specification is not particularly limited. For example, a transistor with a top gate structure in which a gate electrode layer is arranged above a semiconductor layer via a gate insulating layer, and a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. For example, a transistor with a top gate structure in which a gate electrode layer is arranged above a semiconductor layer via a gate insulating layer, and a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. For example, a transistor with a top gate structure in which a gate electrode layer is arranged above a semiconductor layer via a gate insulating layer, and a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. For example, a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. For example, a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used.

[0090] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0091] (Embodiment 5) In this embodiment, examples of transistors applicable to the liquid crystal display device disclosed in this specification are shown. The structure of the transistor applicable to the liquid crystal display device disclosed in this specification is not particularly limited. For example, a top gate structure in which a gate electrode is arranged above a semiconductor layer via a gate insulating layer, or a staggered and planar type with a bottom gate structure in which a gate electrode is arranged below a semiconductor layer via a gate insulating layer can be used. For example, a staggered and planar type with a bottom gate structure in which a gate electrode is arranged below a semiconductor layer via a gate insulating layer can be used. In addition, the transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two are formed, or a triple gate structure in which three are formed. In addition, the transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two are formed, or a triple gate structure in which three are formed. A dual gate having two gate electrode layers arranged via a gate insulating layer above and below it It may be of the type. An example of the cross-sectional structure of the transistor is shown below in FIGS. 13(A) to 13(D). Shown.

[0092] Note that the transistors shown in FIGS. 13(A) to 13(D) use an oxide semiconductor as the semiconductor layer. The advantage of using an oxide semiconductor is that in the on state of the transistor, it has a high field-effect mobility (maximum value of 5 cm / Vsec or more, preferably a maximum value of 1 2 0 cm / Vsec to 150 cm 2 / Vsec), and in the off state of the transistor, it has a low 2 off-current per unit channel width (for example, the off-current per unit channel width is less than 1 aA / μm, more preferably less than 10 zA / μm, and less than 100 zA / μm at 85°C). μm, and even more preferably less than 10 zA / μm, and less than 100 zA / μm at 85°C). This is what can be obtained.

[0093] The transistor 410 shown in FIG. 13(A) is one of the transistors with a bottom gate structure, and is also called an inverse staggered transistor.

[0094] The transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 40 5b on a substrate 400 having an insulating surface. Also, an insulating film 407 that covers the transistor 410 and is laminated on the oxide semiconductor layer 403 is provided. 5b. Further, a protective insulating layer 409 is formed on the insulating film 407. 407 is provided. A protective insulating layer 409 is further formed on the insulating film 407. .

[0095] The transistor 420 shown in FIG. 13(B) is a channel protection type (also called a channel stop type). It is one of the bottom gate structures called (う) and is also called an inverse staggered transistor.

[0096] Transistor 420 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, an insulating layer 427 that functions as a channel protection layer covering the channel formation region of the oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Further, a protective insulating layer 409 is formed to cover the transistor 420.

[0097] The transistor 430 shown in FIG. 13(C) is a bottom gate type transistor, and includes a gate electrode layer 401, a gate insulating layer 402, a source electrode layer 4 05a, a drain electrode layer 405b, and an oxide semiconductor layer 403 on a substrate 400 having an insulating surface. Further, an insulating film 407 in contact with the oxide semiconductor layer 403 is provided to cover the transistor 430. A protective insulating layer 409 is further formed on the insulating film 407.

[0098] In the transistor 430, the gate insulating layer 402 is provided in contact with the substrate 400 and the gate electrode layer 4 01, and the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the gate insulating layer 402. Then, the oxide semiconductor layer 403 is provided on the gate insulating layer 402, and the source electrode layer 40 5a and the drain electrode layer 405b.

[0099] The transistor 440 shown in FIG. 13(D) is one of the transistors with a top gate structure. The transistor 440 includes an insulating layer 437, an oxide semiconductor layer 403, a source electrode layer 405a, a drain electrode layer 405b, a gate insulating layer 402, on a substrate 400 having an insulating surface. ​​​​and includes a gate electrode layer 401, and wiring layers 436a and 436b are respectively in contact with and connected to a source electrode layer 405a and a drain electrode layer 405b.

[0100] In this embodiment, as described above, an oxide semiconductor layer 403 is used as the semiconductor layer. As the oxide semiconductor used for the oxide semiconductor layer 403, a quaternary metal oxide such as an In-Sn-Ga-Zn-O-based oxide semiconductor, a ternary metal oxide such as an In-Ga-Zn-O-based oxide semiconductor, an In-Sn-Zn-O-based oxide semiconductor, an In-Al-Zn-O-based oxide semiconductor, a Sn-Ga-Zn-O-based oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, an Sn-Al-Zn-O-based oxide semiconductor, a binary metal oxide such as an In-Zn-O-based oxide semiconductor, a Sn-Zn-O-based oxide semiconductor, an Al-Zn-O-based oxide semiconductor, a Zn-Mg-O-based oxide semiconductor, a Sn-Mg-O-based oxide semiconductor, an In-Mg-O-based oxide semiconductor, an In-O-based oxide semiconductor, a Sn-O-based oxide semiconductor, a Zn-O-based oxide semiconductor, an In-Ga-O-based oxide semiconductor, etc. can be used. Further, the above oxide semiconductor may contain SiO2. Here, for example, the In-Ga-Zn-O-based oxide semiconductor means an oxide film having indium (In), gallium (Ga), and zinc (Zn), and its stoichiometric ratio is not particularly limited. Further, it may contain elements other than In, Ga, and Zn.

[0101] Further, as the oxide semiconductor layer 403, a thin film represented by the chemical formula InMO3(ZnO) m (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, Ga, Ga and Al, Ga and Mn, ​ or there is Ga, Co, etc.

[0102] For transistors 410, 420, transistor 430, and transistor 440 using the oxide semiconductor layer 403, the current value in the off state (off-current value) can be lowered. Therefore, in a pixel, a capacitor element for holding an electrical signal such as a video signal can be designed to be small. Therefore, the aperture ratio of the pixel can be improved, and thus an effect such as power consumption reduction can be achieved.

[0103] In addition, for transistors 410, 420, transistor 430, and transistor 440 using the oxide semiconductor layer 403, the off-current can be reduced. Therefore, in a pixel, the holding time of an electrical signal such as a video signal can be lengthened, and the writing interval can also be set long. Therefore, the cycle of one frame period can be lengthened, and the frequency of the refresh operation during the still image display period can be reduced, so that the effect of suppressing power consumption can be enhanced. In addition, since the above transistors can be manufactured separately for a drive circuit portion or a pixel portion on the same substrate, the number of components of the liquid crystal display device can be reduced.

[0104] There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but a glass substrate such as barium borosilicate glass or aluminoborosilicate glass is used.

[0105] In transistors 410, 420, and 430 having a bottom gate structure, an insulating film serving as an underlying film may be provided between the substrate and the gate electrode layer. The underlying film may be a substrate or It has a function of preventing the diffusion of impurity elements, and is formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed.

[0106] The material of the gate electrode layer 401 can be formed as a single layer or by lamination using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material having these as a main component. The material of the gate electrode layer 401 can be formed as a single layer or by lamination using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material having these as a main component. It can be formed as a single layer or by lamination.

[0107] The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm. The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm. The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm. The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm. The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm. y The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm. The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm. x The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm. The gate insulating layer 402 can be formed as a single layer or by lamination using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by a plasma CVD method or a sputtering method. For example, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO(x>0)) having a film thickness of 5 nm or more and 300 nm or less is laminated on the first gate insulating layer as the second gate insulating layer to obtain a gate insulating layer having a total film thickness of 200 nm.

[0108] As the conductive film used for the source electrode layer 405a and the drain electrode layer 405b, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) having the above-mentioned elements as components can be used. Also, one of the lower side or the upper side of a metal film such as Al or Cu As the conductive film used for the source electrode layer 405a and the drain electrode layer 405b, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) having the above-mentioned elements as components can be used. Also, one of the lower side or the upper side of a metal film such as Al or Cu As the conductive film used for the source electrode layer 405a and the drain electrode layer 405b, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) having the above-mentioned elements as components can be used. Also, one of the lower side or the upper side of a metal film such as Al or Cu As the conductive film used for the source electrode layer 405a and the drain electrode layer 405b, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) having the above-mentioned elements as components can be used. Also, one of the lower side or the upper side of a metal film such as Al or Cu Both are made of high melting point metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film A laminate of a nitride film, a molybdenum nitride film, and a tungsten nitride film may be used.

[0109] The wiring layer 436a and the wiring layer 436b are connected to the source electrode layer 405a and the drain electrode layer 405b, respectively. The conductive film such as 6b is also made of the same material as the source electrode layer 405a and the drain electrode layer 405b. It can be used.

[0110] In addition, the source electrode layer 405a, the drain electrode layer 405b (wiring formed in the same layer as this The conductive film (including the layer) may be formed of a conductive metal oxide. The oxides are indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide Indium zinc oxide alloy (In2O3-ZnO) or these metal oxide materials with silicon oxide Containing kon can be used.

[0111] Insulating films 407 and 427 are provided above the oxide semiconductor layer, and an insulating layer 43 is provided below the oxide semiconductor layer. 7 is typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an oxide An inorganic insulating film such as an aluminum nitride film can be used.

[0112] The protective insulating layer 409 provided above the oxide semiconductor layer is formed of a silicon nitride film, an alumina film, or the like. Inorganic insulating films such as aluminum film, silicon nitride oxide film, and aluminum nitride oxide film are used. It is possible.

[0113] In addition, a planarizing insulating film is formed on the protective insulating layer 409 in order to reduce surface irregularities caused by the transistor. It may be formed. As the planarization insulating film, organic materials such as polyimide, acrylic, and benzocyclobutene , etc. can be used. In addition to the above organic materials, low dielectric constant materials (low -k materials), etc. can be used. Note that a planarization insulating film may be formed by laminating a plurality of insulating films formed of these materials.

[0114] A transistor including an oxide semiconductor layer manufactured using this embodiment can reduce the off-current by being purified by removing hydrogen and moisture. Further, the highly purified oxide semiconductor layer can be manufactured without going through processes such as laser irradiation, and it is suitable because it enables the formation of transistors on a large-area substrate.

[0115] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0116] (Embodiment 6) The display device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, television devices (also referred to as TVs or television receivers), monitors for computers, cameras such as digital cameras and digital video cameras , cameras such as digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices) , portable game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines. Examples of electronic devices equipped with the display device described in the above embodiment will be described.

[0117] FIG. 14(A) shows an example of an electronic book. The electronic book shown in FIG. 14(A) has a housing 1 It is composed of two housings, namely housing 1700 and housing 1701. Housing 1700 and housing 1701 are integrated by a hinge 1704 and can perform an opening and closing operation. With such a structure it becomes possible to perform operations similar to those of a book.

[0118] A display unit 1702 is incorporated in housing 1700, and a display unit 1703 is incorporated in housing 1701. The display unit 1702 and the display unit 1703 may be configured to display a continuous screen or to display different screens. When configured to display different screens, for example, text can be displayed on the right display unit (display unit 1702 in FIG. 14(A)), and an image can be displayed on the left display unit (display unit 1703 in FIG. 14(A)).

[0119] Also, in FIG. 14(A), an example in which housing 1700 is provided with an operation unit etc. is shown. For example, housing 1700 is provided with a power input terminal 1705, operation keys 1706, a speaker 1707, etc. Pages can be turned by the operation keys 1706. In addition, a configuration may be adopted in which a keyboard, a pointing device, etc. are provided on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (terminals connectable to various cables such as earphone terminals, USB terminals, and USB cables), a recording medium insertion part, etc. may be provided. Furthermore, the e-book shown in FIG. 14(A) may be configured to have a function as an electronic dictionary.

[0120] FIG. 14(B) shows an example of a digital photo frame using a display device. For example, the digital photo frame shown in FIG. 14(B) has a display unit 1712 incorporated in housing 1711. The display unit 1712 can display various images. For example, digital By displaying the image data captured by a tal camera or the like, it can function in the same way as a normal photo stand. It can be made to work.

[0121] Note that the digital photo frame shown in Fig. 14(B) includes an operation unit, external connection terminals (such as USB terminals, terminals connectable to various cables such as USB cables), a recording medium insertion unit, etc. It shall have a configuration including these components. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or the back surface because it improves the design. For example, a memory storing the image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to import the image data, and the imported image data can be displayed on the display unit 1712. It may be incorporated on the same surface as the display unit, but it is preferably provided on the side or the back surface because it improves the design. For example, a memory storing the image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to import the image data, and the imported image data can be displayed on the display unit 1712. For example, a memory storing the image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to import the image data, and the imported image data can be displayed on the display unit 1712. For example, a memory storing the image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to import the image data, and the imported image data can be displayed on the display unit 1712. For example, a memory storing the image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to import the image data, and the imported image data can be displayed on the display unit 1712.

[0122] Fig. 14(C) shows an example of a television device using a display device. The television device shown in Fig. 14(C) has a display unit 1722 incorporated in a housing 1721. With the display unit 1722, it is possible to display video. Also, here, a configuration is shown in which the housing 1721 is supported by a stand 1723. The display unit 1722 can apply the display device shown in the above embodiment. With the display unit 1722, it is possible to display video. Also, here, a configuration is shown in which the housing 1721 is supported by a stand 1723. The display unit 1722 can apply the display device shown in the above embodiment. With the display unit 1722, it is possible to display video. Also, here, a configuration is shown in which the housing 1721 is supported by a stand 1723. The display unit 1722 can apply the display device shown in the above embodiment. With the display unit 1722, it is possible to display video. Also, here, a configuration is shown in which the housing 1721 is supported by a stand 1723. The display unit 1722 can apply the display device shown in the above embodiment.

[0123] The operation of the television device shown in Fig. 14(C) can be performed by operation switches provided on the housing 1721 or by a separate remote control operation unit. By the operation keys provided on the remote control operation unit, operations such as changing channels and adjusting the volume can be performed, and the video displayed on the display unit 1722 can be operated. By the operation keys provided on the remote control operation unit, operations such as changing channels and adjusting the volume can be performed, and the video displayed on the display unit 1722 can be operated. By the operation keys provided on the remote control operation unit, operations such as changing channels and adjusting the volume can be performed, and the video displayed on the display unit 1722 can be operated. Also, the remote control operation unit may be configured to be provided with a display unit for displaying the information output from the remote control operation unit.

[0124] FIG. 14(D) shows an example of a mobile phone using a display device. As shown in FIG. 14(D), the mobile phone includes, in addition to a display unit 1732 incorporated in a housing 1731, operation buttons 1733, operation buttons 1737, an external connection port 1734, a speaker 1735, and a microphone 1736 and the like.

[0125] In the mobile phone shown in FIG. 14(D), the display unit 1732 is a touch panel, and the display content of the display unit 1732 can be operated by contact with a finger or the like. Also, making a phone call or creating an email or the like can be performed by contacting the display unit 1732 with a finger or the like.

[0126] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

Description of Reference Numerals

[0127] 101A Pixel 101B Pixel 101C Pixel 102A First Data Line 102B Second Data Line 102C Third Data Line 103A Scanning Line 103B Scanning Line 103C Scanning Line 104A Transistor 104B Transistor 104C Transistor 105A Display Element Section 105B Display Element Section 105C Display Element Section 106 Intersection 107 Intersection 108 Intersection 109 Intersection 110 Intersection 111 Intersection 121A Liquid Crystal Element ​​121B Liquid crystal element 121C Liquid crystal element 122A Capacitor element 122B Capacitor element 122C Capacitor element 123A Light-emitting element 123B Light-emitting element 123C Light-emitting element 124A Transistor 124B Transistor 124C Transistor 125A First current supply line 125B Second current supply line 125C Third current supply line 131A One electrode 131B One electrode 131C One electrode 141 First conductive layer 142 Second conductive layer 161 Intersection 162 Intersection 163 Intersection 164 Intersection 165 Intersection 166 Intersection 191 Capacitor element 192 Capacitor element 193 Capacitor element 194 Capacitor element 195 Capacitor element 196 Capacitor element 201A Pixel 201B Pixel 201C Pixel 202A Data line 202B Data line 202C Data line 203A First scanning line 203B Second scanning line 203C Third scanning line 204A Transistor 204B Transistor 204C Transistor 205A Display element part 205B Display element part 205C represents the element part 206 Intersection part 207 Intersection part 208 Intersection part 209 Intersection part 210 Intersection part 211 Intersection part 221A Liquid crystal element 221B Liquid crystal element 221C Liquid crystal element 222A Capacitance element 222B Capacitance element 222C Capacitance element 223A Light emitting element 223B Light emitting element 223C Light emitting element 224A Transistor 224B Transistor 224C Transistor 291 Capacitance element 292 Capacitance element 293 Capacitance element 294 Capacitance element 295 Capacitance element 296 Capacitance element 30 Pixel part 31 Scanning line drive circuit 32 Data line drive circuit 33 Scanning line 301 Region 302 Region 303 Region 311 Shift register 312 Shift register 313 Shift register 320 Shift register 321 Transistor 322 Transistor 323 Transistor 341 First data line 342 Second data line 343 Third data line 351 Pixel 352 Pixel 353 Pixel 3511 Transistor 3512 Capacitance element 3514 Liquid crystal element 3521 Transistor 3531 Transistor 36 Backlight unit 361 Intersection 400 Substrate 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating film 409 Protective insulating layer 410 Transistor 420 Transistor 427 Insulating layer 430 Transistor 436a Wiring layer 436b Wiring layer 437 Insulating layer 440 Transistor 1201A Source electrode layer 1201B Source electrode layer 1201C Source electrode layer 1202 Drain electrode layer 1203 Gate electrode layer 1204 Capacitance wiring layer 1205 Transistor 1206 Semiconductor layer 1207 Capacitance element 1208 Transparent electrode layer 1209 Intersection 1212 Gate insulating layer 1217 Liquid crystal layer 1218 First substrate 1219 Second substrate 1227 Insulating film 1228 Insulating film 1229 Interlayer film 1501A Pixel 1501B Pixel 1501C Pixel 1502A First data line 1502B Second data line 1502C Third data line 1503A Scanning line 1503B Scanning line 1503C Scanning line 1504A Transistor 1504B Transistor 1504C Transistor 1505A Display element section 1505B Display element section 1505C Display element section 1506 Intersection section 1507 Intersection section 1516 Load capacitance 1517A Load capacitance 1517B Load capacitance 151A Resistive element 151B Resistive element 151C Resistive element 152A Resistive element 152B Resistive element 152C Resistive element 1700 Housing 1701 Housing 1702 Display section 1703 Display section 1704 Hinge 1705 Power input terminal 1706 Operation key 1707 Speaker 1711 Housing 1712 Display section 1721 Housing 1722 Display section 1723 Stand 1731 Housing 1732 Display section 1733 Operation button 1734 External connection port 1735 Speaker 1736 Microphone 1737 Operation button

Claims

1. having a first pixel and a second pixel arranged in sequence along one direction, the first pixel having a first transistor whose gate is always conducting with a first scanning line, the second pixel having a second transistor whose gate is always conducting with a second scanning line, a display device, a first conductive film having a function as the second scanning line and overlapping with a channel region of the second transistor, a first insulating film having a region disposed above the first conductive film, a second conductive film having a region in contact with an upper surface of the first insulating film and always conducting with one of a source or a drain of the second transistor, a third conductive film having a region disposed below the second conductive film through the first insulating film and always conducting with the second conductive film, a fourth conductive film having a region in contact with an upper surface of the first insulating film and always conducting with the second conductive film through the third conductive film, a fifth conductive film having a region disposed below the fourth conductive film through the first insulating film and always conducting with the third conductive film through the fourth conductive film, a sixth conductive film having a function as the first scanning line and overlapping with a channel region of the first transistor, having a seventh conductive film having a region intersecting with the first conductive film, having a region intersecting with the sixth conductive film, and always conducting with one of a source or a drain of the first transistor, the seventh conductive film having a region intersecting with the third conductive film, a display device.

2. having a first pixel and a second pixel arranged in sequence along one direction, the first pixel having a first transistor whose gate is always conducting with a first scanning line, the second pixel having a second transistor whose gate is always conducting with a second scanning line, a display device, a first conductive film having a function as the second scanning line and overlapping with a channel region of the second transistor, a first insulating film having a region disposed above the first conductive film, a second conductive film having a region in contact with an upper surface of the first insulating film and always conducting with one of a source or a drain of the second transistor, a third conductive film having a region disposed below the second conductive film through the first insulating film and always conducting with the second conductive film, A fourth conductive film having a region in contact with the upper surface of the first insulating film and always conducting with the second conductive film through the third conductive film; A fifth conductive film having a region disposed below the fourth conductive film through the first insulating film and always conducting with the third conductive film through the fourth conductive film; A sixth conductive film having a function as the first scanning line and overlapping with the channel region of the first transistor; A seventh conductive film having a region intersecting with the first conductive film, a region intersecting with the sixth conductive film, and always conducting with one of the source or drain of the first transistor; Each of the first conductive film, the third conductive film, the fifth conductive film, the sixth conductive film, and the seventh conductive film has a region in contact with an insulating surface; The seventh conductive film has a region intersecting with the third conductive film; A display device.

3. A display device having a first pixel and a second pixel arranged in order along one direction; The first pixel has a first transistor whose gate is always conducting with a first scanning line; The second pixel has a second transistor whose gate is always conducting with a second scanning line, A first conductive film having a function as the second scanning line and overlapping with the channel region of the second transistor; A first insulating film having a region disposed above the first conductive film; A second conductive film having a region in contact with the upper surface of the first insulating film and always conducting with one of the source or drain of the second transistor; A third conductive film having a region disposed below the second conductive film through the first insulating film and always conducting with the second conductive film; A fourth conductive film having a region in contact with the upper surface of the first insulating film and always conducting with the second conductive film through the third conductive film; A fifth conductive film having a region disposed below the fourth conductive film through the first insulating film and always conducting with the third conductive film through the fourth conductive film; A sixth conductive film having a function as the first scanning line and overlapping with the channel region of the first transistor; A seventh conductive film having a region intersecting with the first conductive film, a region intersecting with the sixth conductive film, and always conducting with one of the source or drain of the first transistor; In a plan view, the fifth conductive film is disposed in a region between the first conductive film and the sixth conductive film. The seventh conductive film has a region intersecting with the third conductive film. Display device.

4. A display device having a first pixel and a second pixel arranged in order along one direction. The first pixel has a first transistor whose gate is always in conduction with a first scanning line. The second pixel has a second transistor whose gate is always in conduction with a second scanning line, A first conductive film having a function as the second scanning line and overlapping with a channel region of the second transistor, A first insulating film having a region disposed above the first conductive film, A second conductive film having a region in contact with an upper surface of the first insulating film and always in conduction with one of a source or a drain of the second transistor, A third conductive film having a region disposed below the second conductive film via the first insulating film and always in conduction with the second conductive film, A fourth conductive film having a region in contact with an upper surface of the first insulating film and always in conduction with the second conductive film via the third conductive film, A fifth conductive film having a region disposed below the fourth conductive film via the first insulating film and always in conduction with the third conductive film via the fourth conductive film, A sixth conductive film having a function as the first scanning line and overlapping with a channel region of the first transistor, A seventh conductive film having a region intersecting with the first conductive film, a region intersecting with the sixth conductive film, and always in conduction with one of a source or a drain of the first transistor. Each of the first conductive film, the third conductive film, the fifth conductive film, the sixth conductive film, and the seventh conductive film has a region in contact with an insulating surface. In a plan view, the fifth conductive film is disposed in a region between the first conductive film and the sixth conductive film. The seventh conductive film has a region intersecting with the third conductive film. Display device.

Images