Display device

Abstract

To provide a display device capable of further improving the display quality.SOLUTION: In an embodiment, a display device includes a plurality of first subpixels arranged in a display region, a plurality of second subpixels arranged in the display region, a first signal line that supplies a video signal to each of the first subpixels, a second signal line that supplies the video signal to each of the second subpixels, a first correction capacitance part disposed in a peripheral region around the display region and connected to the first signal line, a second correction capacitance part disposed in the peripheral region and connected to the second signal line, and a connection wire with a meandering shape that connects the first correction capacitance part and the second correction capacitance part.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for further improving display quality are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of further improving display quality.

Means for Solving the Problems

[0005] Generally, according to an embodiment, a display device includes a plurality of first sub-pixels arranged in a display area, a plurality of second sub-pixels arranged in the display area, a first signal line that supplies a video signal to each of the plurality of first sub-pixels, a second signal line that supplies a video signal to each of the plurality of second sub-pixels, a first correction capacitor portion disposed in a peripheral area around the display area and connected to the first signal line, a second correction capacitor portion disposed in the peripheral area and connected to the second signal line, and a meandering connection wiring that connects the first correction capacitor portion and the second correction capacitor portion.

[0006] According to another aspect of the embodiment, a display device includes a plurality of sub-pixels disposed in a display area, a signal line that supplies a video signal to each of the plurality of sub-pixels, a power supply line that supplies a power supply voltage to each of the plurality of sub-pixels, and a correction capacitor portion disposed in a peripheral area around the display area and connected to the signal line. Each of the plurality of sub-pixels includes a pixel circuit connected to the signal line and the power supply line, a lower electrode connected to the pixel circuit, an upper electrode facing the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to an applied voltage. Further, the correction capacitor portion includes a first capacitive electrode formed of the same material as the signal line in the same layer as the signal line and connected to the signal line, and a second capacitive electrode formed of the same material as the power supply line in the same layer as the power supply line and forming a correction capacitance with the first capacitive electrode.

[0007] According to still another aspect of the embodiment, the display device includes a plurality of sub-pixels arranged in a display area, a signal line for supplying a video signal to each of the plurality of sub-pixels, and a correction capacitor unit arranged in a peripheral area around the display area and connected to the signal line. Each of the plurality of sub-pixels includes a transistor including a gate electrode and a semiconductor, a pixel circuit connected to the signal line, a lower electrode connected to the pixel circuit, an upper electrode facing the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to the application of a voltage. Further, the correction capacitor unit includes a first capacitor electrode formed of the same material as the gate electrode in the same layer as the gate electrode and connected to the signal line, and a second capacitor electrode formed of the same material as the semiconductor in the same layer as the semiconductor and forming a correction capacitance with the first capacitor electrode.

Brief Description of the Drawings

[0008]

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[0009] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, components that exhibit the same or similar functions as those described above for the already presented drawings may be assigned the same reference numerals, and detailed descriptions may be appropriately omitted as needed.

[0010] In the drawings, for ease of understanding if necessary, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are described. The direction along the X-axis is referred to as the X direction, the direction along the Y-axis is referred to as the Y direction, and the direction along the Z-axis is referred to as the Z direction. The Z direction is the normal direction of the plane including the X direction and the Y direction. Also, viewing various elements parallel to the Z direction is referred to as a plan view.

[0011] The display device according to each embodiment is an organic electroluminescence display device including an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, and a wearable terminal.

[0012] FIG. 1 is a diagram showing a configuration example of a display device DSP according to an embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a resin film having flexibility.

[0013] In the present embodiment, the shapes of the substrate 10 and the display area DA in a plan view are elliptical. However, the shapes of the substrate 10 and the display area DA in a plan view are not limited to elliptical, and may be other shapes such as a rectangle, a square, or a perfect circle.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, a case where the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3 is assumed. However, the pixel PX may include sub-pixels SP of other colors such as white, together with or in place of any of the sub-pixels SP1, SP2, and SP3.

[0015] The display device DSP further includes a terminal portion T disposed in the peripheral region SA. A flexible circuit board for supplying, for example, a voltage or a signal for driving the display device DSP is connected to the terminal portion T.

[0016] FIG. 2 is a circuit diagram showing an example of a configuration applicable to a pixel circuit PC included in each of the sub-pixels SP (SP1, SP2, SP3). The pixel circuit PC shown in this figure includes seven transistors TR1 to TR7 and one holding capacitor Cst.

[0017] In the following description, one of the source-drain electrodes of each of the transistors TR1 to TR7 is referred to as a first electrode, and the other is referred to as a second electrode. Similarly, one electrode of the holding capacitor Cst is referred to as a first electrode, and the other electrode is referred to as a second electrode.

[0018] The first electrode of the transistor TR1 is connected to the node n1. The second electrode of the transistor TR1 is connected to a signal line SL that supplies the video signal Sdata. The video signal Sdata is a signal written to the pixel for image display.

[0019] The transistor TR2 corresponds to a driving transistor that supplies current to a light-emitting element DE included in the sub-pixel SP. The first electrode of the transistor TR2 is connected to the node n1. The second electrode of the transistor TR2 is connected to the node n2.

[0020] The first electrode of the transistor TR3 is connected to the node n3. The second electrode of the transistor TR3 is connected to the node n2.

[0021] The first electrode of the transistor TR4 is connected to the node n2. The second electrode of the transistor TR4 is connected to a power supply line PL1 that supplies the power supply voltage VDDEL.

[0022] The first electrode of the transistor TR5 is connected to the node n4. The second electrode of the transistor TR5 is connected to the node n1.

[0023] The first electrode of transistor TR6 is connected to node n4. The second electrode of transistor TR6 is connected to an initialization line IL that supplies an initialization voltage Vini.

[0024] The first electrode of transistor TR7 is connected to node n2. The second electrode of transistor TR7 is connected to a power supply line PL2 that supplies a power supply voltage VSH.

[0025] The first electrode of the holding capacitor Cst is connected to node n3. The second electrode of the holding capacitor Cst is connected to node n4.

[0026] The gate electrode of transistor TR1 is connected to a scanning line GL1 that supplies a scanning signal Sg1. The gate electrode of transistor TR3 is connected to a scanning line GL2 that supplies a scanning signal Sg2. The gate electrodes of transistors TR4, TR5, and TR6 are connected to a scanning line GL3 that supplies a scanning signal Sg3. The gate electrode of transistor TR7 is connected to a scanning line GL4 that supplies a scanning signal Sg4.

[0027] The anode of the display element DE is connected to node n4. The cathode of the display element DE is connected to a power supply line PL3 that supplies a power supply voltage VSSEL. The above-described power supply voltage VDDEL corresponds to the anode voltage supplied to the display element DE, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the display element DE.

[0028] Note that the configuration of the pixel circuit PC is not limited to the example shown in FIG. 2. For example, the pixel circuit PC may include six or fewer or eight or more transistors. Also, the pixel circuit PC may include a plurality of holding capacitors Cst.

[0029] FIG. 3 is a schematic plan view showing an example of the arrangement mode of the pixel circuit PC arranged for one pixel PX. In the example of FIG. 3, the pixel circuits PC (PC1, PC2, PC3) of the sub-pixels SP1, SP2, and SP3 are arranged in the X direction.

[0030] The pixel circuits PC1, PC2, and PC3 are connected to the display elements DE of the sub-pixels SP1, SP2, and SP3, respectively, via contact holes CH1, CH2, and CH3 provided in the organic insulating layer 12 described later. In the example of FIG. 3, the contact holes CH1, CH2, and CH3 are arranged in the X direction.

[0031] FIG. 4 is a schematic plan view showing an example of the layout of the display elements DE (DE1, DE2, DE3) of the sub-pixels SP1, SP2, and SP3. In the example of FIG. 4, the display elements DE1 and DE2 are arranged in the X direction with the display element DE3, respectively. Further, the display elements DE1 and DE2 are arranged in the Y direction.

[0032] When the display elements DE1, DE2, and DE3 are in such a layout, in the display area DA, a column in which the display elements DE1 and DE2 are alternately arranged in the Y direction and a column in which a plurality of display elements DE3 are repeatedly arranged in the Y direction are formed. These columns are alternately arranged in the X direction. Note that the layout of the display elements DE1, DE2, and DE3 is not limited to the example of FIG. 4.

[0033] In the display area DA, a rib 5 is arranged. The rib 5 has a pixel aperture AP1 surrounding the display element DE1, a pixel aperture AP2 surrounding the display element DE2, and a pixel aperture AP3 surrounding the display element DE3.

[0034] In the example of FIG. 4, the pixel aperture AP2 is larger than the pixel aperture AP1, and the pixel aperture AP3 is larger than the pixel aperture AP2. That is, among the sub-pixels SP1, SP2, and SP3, the aperture ratio of the sub-pixel SP3 is the largest, and the aperture ratio of the sub-pixel SP1 is the smallest. However, the relationship of the aperture ratios of the sub-pixels SP1, SP2, and SP3 is not limited to this example.

[0035] The display element DE1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that respectively overlap with the pixel aperture AP1. The display element DE2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that respectively overlap with the pixel aperture AP2. The display element DE3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively overlap with the pixel aperture AP3.

[0036] On the rib 5, a lattice-shaped partition wall 6 is arranged. The partition wall 6 entirely overlaps with the rib 5 and has the same planar shape as the rib 5. That is, the partition wall 6 has an opening that surrounds the display elements DE1, DE2, and DE3. The partition wall 6 serves as a wiring for supplying a cathode voltage to the upper electrodes UE1, UE2, and UE3. The above-mentioned contact holes CH1, CH2, and CH3 respectively overlap with the rib 5 and the partition wall 6.

[0037] FIG. 5 is a schematic cross-sectional view of the display device DSP along the line V-V in FIG. 4. A circuit layer 11 is arranged on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits PC (PC1, PC2, PC3), signal lines SL, initialization lines IL, power supply lines PL1, PL2, PL3, and scanning lines GL1, GL2, GL3, GL4 shown in FIG. 2. The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film that planarizes the unevenness caused by the circuit layer 11.

[0038] The lower electrodes LE1, LE2, and LE3 are arranged on the organic insulating layer 12. The rib 5 is arranged on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. The lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuits PC1, PC2, and PC3 of the circuit layer 11 through the contact holes CH1, CH2, and CH3 (see FIGS. 3 and 4) provided in the organic insulating layer 12.

[0039] The partition wall 6 includes a conductive lower part 61 disposed on the rib 5 and an upper part 62 disposed on the lower part 61. The upper part 62 has a width larger than that of the lower part 61. As a result, both ends of the upper part 62 protrude beyond the side surfaces of the lower part 61. Such a shape of the partition wall 6 is called an overhang shape.

[0040] In the example of FIG. 5, the lower part 61 has a bottom layer 63 disposed on the rib 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Also, in the example of FIG. 5, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0041] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower part 61 of the partition wall 6.

[0042] The display element DE1 includes a cap layer CP1 disposed on the upper electrode UE1. The display element DE2 includes a cap layer CP2 disposed on the upper electrode UE2. The display element DE3 includes a cap layer CP3 disposed on the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as an optical adjustment layer for improving the light extraction efficiency of the organic layers OR1, OR2, and OR3, respectively.

[0043] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is referred to as a stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is referred to as a stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is referred to as a stacked film FL3.

[0044] A part of the stacked film FL1 is located above the upper part 62. This part is separated from the part of the stacked film FL1 located around the partition wall 6 (the part constituting the display element DE1). Similarly, a part of the stacked film FL2 is located above the upper part 62, and this part is separated from the part of the stacked film FL2 located around the partition wall 6 (the part constituting the display element DE2). Further, a part of the stacked film FL3 is located above the upper part 62, and this part is separated from the part of the stacked film FL3 located around the partition wall 6 (the part constituting the display element DE3).

[0045] Sealing layers SE11, SE12, and SE13 are arranged in the sub-pixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the sub-pixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the sub-pixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the sub-pixel SP3.

[0046] In the example of FIG. 5, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the display elements DE1 and DE3 are separated from the stacked film FL3 and the sealing layer SE13 on the same partition wall 6. Also, the stacked film FL2 and the sealing layer SE12 on the partition wall 6 between the display elements DE2 and DE3 are separated from the stacked film FL3 and the sealing layer SE13 on the same partition wall 6.

[0047] The sealing layers SE11, SE12, and SE13 are covered by a resin layer RS1. The resin layer RS1 is covered by a sealing layer SE2. The sealing layer SE2 is covered by a resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least over the entire display area DA, and a part thereof also extends to the peripheral area SA.

[0048] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further arranged above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as an OCA (Optical Clear Adhesive).

[0049] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The ribs 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the ribs 5 are formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as an epoxy resin or an acrylic resin.

[0050] The lower electrodes LE1, LE2, LE3 have, for example, a reflective layer formed of silver and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0051] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). In the present embodiment, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0052] The organic layers OR1, OR2, OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in the Z direction in order. However, the organic layers OR1, OR2, OR3 may have another structure such as a so-called tandem structure including a plurality of light-emitting layers.

[0053] The cap layers CP1, CP2, CP3 have, for example, a laminated structure in which a plurality of transparent layers are laminated. These transparent layers may include a layer formed of an inorganic material and a layer formed of an organic material. Further, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, UE3 and the refractive indices of the sealing layers SE11, SE12, SE13. Note that at least one of the cap layers CP1, CP2, CP3 may be omitted.

[0054] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. As the metal material of the bottom layer 63, for example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW) or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY) or aluminum-silicon alloy (AlSi) can be used. Note that the shaft layer 64 may be formed of an insulating material.

[0055] For example, the upper part 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. As the metal material for forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy or molybdenum-niobium alloy can be used. As the conductive oxide for forming the upper layer, for example, ITO or IZO can be used. Note that the upper part 62 may have a single-layer structure of a metal material. Further, the upper part 62 may include a layer formed of an insulating material.

[0056] A cathode voltage is supplied to the partition wall 6. This cathode voltage is supplied to the upper electrodes UE1, UE2, UE3 in contact with the side surface of the lower part 61, respectively. Voltages corresponding to the video signal Sdata of the signal line SL are supplied to the lower electrodes LE1, LE2, LE3 through the pixel circuits PC (PC1, PC2, PC3) of the sub-pixels SP1, SP2, SP3, respectively.

[0057] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength range.

[0058] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer into light of colors corresponding to the sub-pixels SP1, SP2, and SP3. Further, the display device DSP may include a layer containing quantum dots that generate light of colors corresponding to the sub-pixels SP1, SP2, and SP3 by being excited by the light emitted by the light-emitting layer.

[0059] FIG. 6 is a schematic cross-sectional view showing an example of a layer structure applicable to the circuit layer 11. In the example of this figure, the circuit layer 11 includes semiconductor layers 31 and 32, metal layers 41, 42, 43, and 44, inorganic insulating layers 51, 52, 53, 54, and 55, and an organic insulating layer 56.

[0060] For example, the semiconductor layer 31 corresponds to the lowermost layer of the circuit layer 11. However, an insulating layer may be disposed below the semiconductor layer 31. The inorganic insulating layer 51 covers the semiconductor layer 31. The metal layer 41 is disposed on the inorganic insulating layer 51. The inorganic insulating layer 52 covers the metal layer 41. The semiconductor layer 32 is disposed on the inorganic insulating layer 52. The inorganic insulating layer 53 covers the semiconductor layer 32. The metal layer 42 is disposed on the inorganic insulating layer 53. The inorganic insulating layer 54 covers the metal layer 42. The metal layer 43 is disposed on the inorganic insulating layer 54. The inorganic insulating layer 55 covers the metal layer 43. The organic insulating layer 56 covers the inorganic insulating layer 55. The metal layer 44 is disposed on the organic insulating layer 56 and is covered by the organic insulating layer 12 shown in FIG. 5.

[0061] For example, the semiconductor layer 31 is formed of low-temperature polysilicon formed at a low temperature, and the semiconductor layer 32 is formed of an oxide semiconductor. For the metal layers 41 to 44, a single-layer structure of a metal material or a laminated structure using a plurality of metal materials can be applied. In one example, the metal layers 41 and 42 are formed of a molybdenum-tungsten alloy (MoW), and the metal layers 43 and 44 are formed of a laminated structure (so-called TAT) in which an aluminum layer is sandwiched between a pair of tungsten layers.

[0062] The inorganic insulating layers 51 to 55 are formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. Further, the organic insulating layer 56 is formed of an organic insulating material such as polyimide to be thicker than the inorganic insulating layers 51 to 55.

[0063] FIGS. 7 and 8 are diagrams showing configuration examples of transistors (TFTs) included in the circuit layer 11. The transistor TRa shown in FIG. 7 includes a semiconductor SCa and a gate electrode GEa facing the semiconductor SCa. The semiconductor SCa is formed of the semiconductor layer 31. The gate electrode GEa is formed of the metal layer 41.

[0064] On the other hand, the transistor TRb shown in FIG. 8 includes a semiconductor SCb and gate electrodes GEb1 and GEb2 facing the semiconductor SCb. The semiconductor SCb is formed of the semiconductor layer 32. The gate electrode GEb1 is formed of the metal layer 41. The gate electrode GEb2 is formed of the metal layer 42.

[0065] For the transistors TR1 to TR7 shown in FIG. 2, one of the structures of these transistors TRa and TRb can be applied. The source / drain electrodes (the first electrode and the second electrode) of the transistors TR1 to TR7 can be formed of at least one of the metal layers 41 to 44.

[0066] In addition, the signal line SL, initialization line IL, power supply lines PL1 to PL3, and scanning lines GL1 to GL4 shown in FIG. 2 are formed by any one of the metal layers 41 to 44. In one example, the signal line SL, power supply line PL1, and initialization line IL are formed by the metal layer 43, the power supply lines PL2 and PL3 are formed by the metal layer 44, and the scanning lines GL1 to GL4 are formed by at least one of the metal layers 41 and 42.

[0067] FIG. 9 is a schematic plan view showing a circuit related to the above-described power supply voltage VDDEL. As shown in FIG. 2, the power supply voltage VDDEL is supplied to the pixel circuit PC of each sub-pixel SP via the power supply line PL1. In the example of FIG. 9, a plurality of power supply lines PL1 extending in the Y direction are arranged in the display area DA.

[0068] One end of each power supply line PL1 is connected to the connection portion CN1, and the other end is connected to the connection portion CN2. Both the connection portions CN1 and CN2 are located in the peripheral area SA. In the example of FIG. 9, the connection portions CN1 and CN2 have a shape curved along the display area DA.

[0069] The connection portion CN1 is located between the display area DA and the terminal portion T, and is connected to the terminal portion T by a pair of wirings L1 and L2. The power supply voltage VDDEL is supplied to each power supply line PL1 via the terminal portion T, the wirings L1 and L2, and the connection portion CN1.

[0070] FIG. 10 is a plan view showing a schematic configuration of the connection portion CN2. In this figure, the pixel circuit PC, the power supply line PL1, and the signal line SL are shown as elements arranged in the display area DA.

[0071] As shown in FIGS. 1 and 9, the display area DA is elliptical as a whole. Such a shape is realized by arranging the pixel circuits PC (sub-pixels SP) in a stepped manner at the edge of the display area DA as shown in FIG. 10.

[0072] A plurality of pixel circuits PC (sub-pixels SP) to which a power supply voltage VDDEL is supplied by one power supply line PL1 are arranged in the Y direction. From another perspective, a plurality of pixel circuits PC (sub-pixels SP) to which a video signal Sdata is supplied by one signal line SL are arranged in the Y direction.

[0073] The connection portion CN2 includes a plurality of correction capacitor portions 7. In the example of FIG. 10, one correction capacitor portion 7 is provided for each of the pair of power supply lines PL1 and signal lines SL. However, there may be a signal line SL for which the correction capacitor portion 7 is not provided.

[0074] The correction capacitor portion 7 includes at least one capacitance electrode 71 (first capacitance electrode) and at least one capacitance electrode 72 (second capacitance electrode). The capacitance electrode 71 is connected to the signal line SL. The capacitance electrode 72 is connected to the power supply line PL1. The voltage of the signal line SL is applied to the capacitance electrode 71, and the power supply voltage VDDEL of the power supply line PL1 is applied to the capacitance electrode 72.

[0075] The capacitance electrodes 71 and 72 face each other in the Z direction. Thereby, a correction capacitor C that applies a load to the signal line SL is formed between the capacitance electrodes 71 and 72.

[0076] Each capacitance electrode 72 is connected by a connection wiring CL arranged in the peripheral region SA. The connection wiring CL has a meandering shape. That is, the connection wiring CL bends a plurality of times between adjacent capacitance electrodes 72. From another perspective, the connection wiring CL has a waveform in which portions convex upward (in the direction away from the display area DA) and portions convex downward (in the direction approaching the display area DA) in the figure are repeated a plurality of times. The connection wiring CL has a width that is sufficiently smaller than the capacitance electrode 72.

[0077] FIG. 11 is a diagram for explaining the role of the correction capacitor C. For example, when the display area DA is elliptical as in the present embodiment, the number of sub-pixels SP (pixel circuits PC) connected to each signal line SL can be different.

[0078] Specifically, more pixel circuits PC are connected to the signal lines SL closer to the center O of the display area DA. As a result, the loads (capacitances) of the respective signal lines SL are different.

[0079] The graph in FIG. 11 shows an example of the load Cx of the signal line SL located between the center O and the end E in the X direction of the display area DA. In the graph, the horizontal axis is the distance Dx from the center O. The solid line in the graph shows the distribution Q1 of the load Cx when there is no correction capacitance section 7. The broken line in the graph shows the distribution Q2 of the load Cx when there is a correction capacitance section 7.

[0080] Many pixel circuits PC are connected to the signal lines SL near the center O. Therefore, as shown by the distribution Q1, when there is no correction capacitance section 7, the load Cx of the signal line SL decreases as it moves away from the center O. Such a difference in the load Cx can cause an undesired luminance distribution in the display area DA. Specifically, the luminance of the sub-pixel SP near the end E where the load Cx is small becomes high.

[0081] The correction capacitance C of the correction capacitance section 7 alleviates such a luminance distribution. That is, by giving a larger correction capacitance C to the signal lines SL closer to the end E, it is possible to reduce the difference in the load Cx of the respective signal lines SL. Thereby, the luminance distribution in the display area DA is alleviated. In one example, it is preferable that the load Cx of each signal line SL is uniform as in the distribution Q2.

[0082] FIG. 12 is a diagram showing an example of the arrangement mode of the correction capacitance section 7. In this figure, attention is paid to three signal lines SL (SLa, SLb, SLc). The signal line SLa is connected to the pixel circuits PC of Na sub-pixels SPa. The signal line SLb is connected to the pixel circuits PC of Nb sub-pixels SPb. The signal line SLc is connected to the pixel circuits PC of Nc sub-pixels SPc.

[0083] The pixel circuit PC of each sub-pixel SPa is supplied with a power supply voltage VDDEL via a power supply line PL1a. The pixel circuit PC of each sub-pixel SPb is supplied with a power supply voltage VDDEL via a power supply line PL1b. The pixel circuit PC of each sub-pixel SPc is supplied with a power supply voltage VDDEL via a power supply line PL1c.

[0084] Correction capacitor units 7a, 7b, and 7c are respectively connected to signal lines SLa, SLb, and SLc. Specifically, signal line SLa is connected to the capacitance electrode 71a of correction capacitor unit 7a, and power supply line PL1a is connected to the capacitance electrode 72a of correction capacitor unit 7a. Signal line SLb is connected to the capacitance electrode 71b of correction capacitor unit 7b, and power supply line PL1b is connected to the capacitance electrode 72b of correction capacitor unit 7b. Signal line SLc is connected to the capacitance electrode 71c of correction capacitor unit 7c, and power supply line PL1c is connected to the capacitance electrode 72c of correction capacitor unit 7c.

[0085] Signal line SLb is located between signal line SLa and the center O of the display area DA. Therefore, the number Nb of sub-pixels SPb is larger than the number Na of sub-pixels SPa (Nb > Na). In order to mitigate the difference in the loads of signal lines SLa and SLb caused by such a difference in the number of sub-pixels SPa and SPb, the correction capacitance Ca of correction capacitor unit 7a is set to be larger than the correction capacitance Cb of correction capacitor unit 7b (Cb < Ca).

[0086] On the other hand, signal line SLc is located between signal line SLa and the end E in the X direction of the display area DA. Therefore, the number Nc of sub-pixels SPc is smaller than the number Na of sub-pixels SPa (Nc < Na). In order to mitigate the difference in the loads of signal lines SLa and SLc caused by such a difference in the number of sub-pixels SPa and SPc, the correction capacitance Cc of correction capacitor unit 7c is set to be larger than the correction capacitance Ca of correction capacitor unit 7a (Ca < Cc).

[0087] FIG. 13 is a diagram showing another example of the arrangement mode of correction capacitor unit 7. Also in the example of this figure, attention is paid to signal lines SLa, SLb, and SLc as in the example of FIG. 12.

[0088] In the example of FIG. 13, the correction capacitance section 7a has two capacitance electrodes 71a and two capacitance electrodes 72a that face the capacitance electrodes 71a respectively. Further, the correction capacitance section 7c has three capacitance electrodes 71c and three capacitance electrodes 72c that face the capacitance electrodes 71c respectively. The correction capacitance section 7b has one capacitance electrode 71b and one capacitance electrode 72b, similar to the example of FIG. 12.

[0089] Thus, in the example of FIG. 13, many capacitance electrodes 71 are connected to the signal line SL with a small load by the pixel circuit PC, and capacitances are formed between each of these capacitance electrodes 71 and the capacitance electrode 72. Thereby, the correction capacitances Ca, Cb, and Cc of the correction capacitance sections 7a, 7b, and 7c can be adjusted, and the difference in the loads of the signal lines SLa, SLb, and SLc can be alleviated.

[0090] For example, the capacitance formed by one capacitance electrode 71a and one capacitance electrode 72a, the capacitance formed by one capacitance electrode 71b and one capacitance electrode 72b, and the capacitance formed by one capacitance electrode 71c and one capacitance electrode 72c are the same. As another example, these capacitances may be different.

[0091] Note that the number of capacitance electrodes 71 connected to one signal line SL is not limited to one, two, or three as in the example of FIG. 13, and more capacitance electrodes 71 may be connected.

[0092] Subsequently, referring to FIGS. 14 to 20, some specific embodiments applicable to the correction capacitance section 7 are shown. Not limited to these embodiments, various configurations can be applied to the correction capacitance section 7.

[0093] FIG. 14 is a schematic plan view of a plurality of correction capacitance sections 7 (correction capacitance section 7p) according to the first embodiment. FIG. 15 is an enlarged schematic plan view of one correction capacitance section 7p. FIG. 16 is a schematic cross-sectional view of the correction capacitance section 7p taken along the line XVI-XVI in FIG. 15.

[0094] The elements shown in FIGS. 14 and 15 are mainly formed by the metal layers 41 to 44 shown in FIG. 6. FIGS. 14 and 15 also show the correspondence between the line types and hatchings of each element and the metal layers 41 to 44.

[0095] As shown in FIGS. 14 and 15, the correction capacitor portion 7p has a capacitive electrode 71p, a capacitive electrode 72p, and a capacitive electrode 73. The capacitive electrode 71p is formed by the metal layer 43. The capacitive electrode 72p is formed by the metal layer 44. The capacitive electrode 73 is formed by the metal layer 42. Also, the signal line SL and the power line PL1 are formed by the metal layer 43. Thus, in the first embodiment, the capacitive electrode 71p (first capacitive electrode) is formed of the same material as the signal line SL in the same layer as the signal line SL.

[0096] For example, the capacitive electrode 71p is formed integrally with the signal line SL. The capacitive electrode 72p is connected to the power line PL1 through a contact hole CHa that penetrates the inorganic insulating layer 55 and the organic insulating layer 56. The capacitive electrode 73 is connected to the power line PL1 through a contact hole CHb that penetrates the inorganic insulating layer 54.

[0097] In the example of FIG. 14, the capacitive electrode 72p has a size that overlaps the three capacitive electrodes 71p. As another example, a capacitive electrode 72p may be provided for each capacitive electrode 71p.

[0098] In the examples of FIGS. 14 and 15, a part of the capacitive electrode 73 extends upward in the figure. The said part is connected to a relay wiring 74 formed by the metal layer 43 through a contact hole CHc that penetrates the inorganic insulating layer 54.

[0099] The connection wiring CL shown in FIG. 10 is connected to the relay wiring 74. The connection wiring CL can be formed by, for example, the metal layer 42. In this case, the relay wiring 74 and the connection wiring CL are connected through a contact hole penetrating the inorganic insulating layer 54. Not limited to this example, the connection wiring CL may be formed by any of the metal layers 41, 43, and 44.

[0100] In the examples of FIGS. 14 and 15, wirings L11 to L15 formed by the metal layer 41 and wirings L21 and L22 formed by the metal layer 44 are arranged. The wirings L11 to L15, L21, and L22 all extend in the X direction. The wirings L11 to L15, L21, and L22 are insulated from the signal line SL, the power supply line PL1, the capacitor electrodes 71p, 72p, 73, and the relay wiring 74.

[0101] For example, the scanning lines GL1 to GL4 shown in FIG. 2 are any of the wirings L11 to L15. Also, the power supply lines PL2 and PL3 shown in FIG. 2 are any of the wirings L21 and L22. That is, in the first embodiment, the capacitor electrode 72p (second capacitor electrode) is formed of the same material as the power supply lines PL2 and PL3 in the same layer as the power supply lines PL2 and PL3.

[0102] As shown in FIG. 16, the organic insulating layer 56 has an opening 56a. As shown in FIGS. 14 and 15, the opening 56a overlaps with the capacitor electrodes 71p and 72p.

[0103] In the region where such an opening 56a is provided, the capacitor electrode 71p connected to the signal line SL and the capacitor electrode 72p connected to the power supply line PL1 face each other through a relatively thin inorganic insulating layer 55. Thereby, a good capacitance is formed between the capacitor electrodes 71p and 72p. Also, a capacitance can be formed between the capacitor electrodes 71p and 73. These capacitances correspond to the correction capacitance C shown in FIG. 10 (correction capacitances Ca, Cb, and Cc in FIGS. 12 and 13).

[0104] FIG. 17 is a schematic plan view of a plurality of correction capacitor portions 7 (correction capacitor portion 7q) according to the second embodiment. FIG. 18 is a schematic plan view of one enlarged correction capacitor portion 7q. FIG. 19 is a schematic cross-sectional view of the correction capacitor portion 7q along line IXX-IXX in FIG. 18.

[0105] The elements shown in FIGS. 17 and 18 are mainly formed by the semiconductor layer 31 and the metal layers 41 to 44 shown in FIG. 6. In FIGS. 17 and 18, the line types and hatchings of each element and the correspondence with the semiconductor layer 31 and the metal layers 41 to 44 are also shown.

[0106] As shown in FIGS. 17 and 18, the correction capacitor portion 7q has a capacitor electrode 71q, a capacitor electrode 72q, and a relay wiring 75. Also, the correction capacitor portion 7q, similar to the correction capacitor portion 7p according to the first embodiment, has capacitor electrodes 72p, 73 and a relay wiring 74. In the second embodiment, an opening 56a is not provided in the organic insulating layer 56.

[0107] The capacitor electrode 71q is formed by the metal layer 41. The capacitor electrode 72q is formed by the semiconductor layer 31. The relay wiring 75 is formed by the metal layer 42. Similar to the first embodiment, the capacitor electrode 73 is formed by the metal layer 42, and the signal line SL, the power supply line PL1, and the relay wiring 74 are formed by the metal layer 43.

[0108] Thus, the capacitor electrode 71q (first capacitor electrode) in the second embodiment is formed of the same material as these gate electrodes GEa and GEb1 in the same layer as the gate electrode GEa shown in FIG. 7 and the gate electrode GEb1 shown in FIG. 8. Also, the capacitor electrode 72q (second capacitor electrode) is formed of the same material as the semiconductor SCa in the same layer as the semiconductor SCa shown in FIG. 7.

[0109] The relay wiring 75 is connected to the signal line SL through a contact hole CHd that penetrates the inorganic insulating layer 54. The capacitive electrode 71q is connected to the relay wiring 75 through a contact hole CHe that penetrates the inorganic insulating layers 52 and 53. Similar to the first embodiment, the capacitive electrode 72p is connected to the power line PL1 through a contact hole CHa that penetrates the inorganic insulating layer 55 and the organic insulating layer 56. Also, the capacitive electrode 73 is connected to the power line PL1 through a contact hole CHb that penetrates the inorganic insulating layer 54. The capacitive electrode 72q is connected to the capacitive electrode 73 through a contact hole CHf that penetrates the inorganic insulating layers 51 to 53.

[0110] As shown in FIGS. 17 and 18, the capacitive electrodes 71q, 72q, and 73 overlap in a plan view. As shown in FIG. 19, the capacitive electrodes 71q and 72q face each other with the relatively thin inorganic insulating layer 51 interposed therebetween. Thereby, a good capacitance is formed between the capacitive electrode 71q connected to the signal line SL and the capacitive electrode 72q connected to the power line PL1. Also, a capacitance can be formed between the capacitive electrodes 71q and 73. These capacitances correspond to the correction capacitance C shown in FIG. 10 (correction capacitances Ca, Cb, and Cc in FIGS. 12 and 13).

[0111] FIG. 20 is a schematic cross-sectional view of the correction capacitance portion 7 (correction capacitance portion 7r) according to the third embodiment. The correction capacitance portion 7r has a structure that combines the correction capacitance portion 7p according to the first embodiment and the correction capacitance portion 7q according to the second embodiment.

[0112] Specifically, the correction capacitance portion 7r includes a capacitive electrode 71p (first capacitive electrode) connected to the signal line SL, a capacitive electrode 72p (second capacitive electrode) connected to the power line PL1, a capacitive electrode 71q (third capacitive electrode) connected to the signal line SL, a capacitive electrode 72q (fourth capacitive electrode) connected to the power line PL1, and a capacitive electrode 73. With such a configuration, the correction capacitance portion 7r can obtain a correction capacitance C having a magnitude that combines the correction capacitances of the correction capacitance portions 7p and 7q.

[0113] The planar shapes of the capacitance electrodes 71p, 72p, 73 and the opening 56a of the organic insulating layer 56 are the same as those shown in FIG. 15. The planar shapes of the capacitance electrodes 71q, 72q are the same as those shown in FIG. 18.

[0114] For example, the correction capacitance C of the correction capacitance section 7p is larger than the correction capacitance C of the correction capacitance section 7q. In such a case, the correction capacitance section 7p may be applied to the correction capacitance section 7a shown in FIG. 12, the correction capacitance section 7q may be applied to the correction capacitance section 7b, and the correction capacitance section 7r may be applied to the correction capacitance section 7c.

[0115] According to the above-described embodiment, as described with reference to FIG. 11, by providing the correction capacitance section 7, the difference in the load Cx of each signal line SL can be reduced, and an undesired luminance distribution in the display area DA can be alleviated.

[0116] In an electronic device equipped with the display device DSP, an antenna for near-field wireless communication (NFC) may be disposed on the back side of the display device DSP. In this case, as shown in FIG. 9, if the both ends of each power line PL1 are connected by the connection portions CN1, CN2, the conductor composed of the power line PL1 and the connection portions CN1, CN2 may contribute to reducing the sensitivity of the wireless communication by the antenna.

[0117] Specifically, eddy currents are generated in the conductor by the magnetic field formed by the antenna. Due to this eddy current, a magnetic field in a direction to cancel the magnetic field is formed, and the signal strength is attenuated. Therefore, when performing wireless communication via the display device DSP, the communication sensitivity may decrease. In particular, when the capacitance electrode 72 of the correction capacitance section 7 is formed of a wide metal material, the connection portion CN2 has a low resistance. As a result, a large eddy current and an accompanying strong magnetic field are generated in the conductor, and the communication sensitivity is likely to decrease.

[0118] In contrast, in the present embodiment, each capacitive electrode 72 is connected by a meandering connection wiring CL as shown in FIG. 10. In this case, the resistance of the connection portion CN2 can be increased as compared with the case where the capacitive electrodes 72 are integrally connected or connected by a straight wiring. As a result, the generation of the eddy current can be suppressed, and the communication sensitivity of the short-range wireless communication can be enhanced.

[0119] In the present embodiment, the configuration related to the correction capacitance unit 7 has been described by taking the display device DSP having an elliptical display area DA as an example. That is, when the display area DA has such a shape, as described with reference to FIG. 9, the loads of the respective signal lines SL are not uniform, and thus adjustment of the load by the correction capacitance unit 7 is required.

[0120] The loads of the respective signal lines SL can be non-uniform not only in an elliptical shape but also in a circular display area DA. Further, for example, even when the display area DA is generally rectangular but a notch for arranging a camera or the like is provided on one side thereof, the loads of the respective signal lines SL can be non-uniform. The configuration related to the correction capacitance unit 7 disclosed in the present embodiment also exhibits a good effect when applied to a display device DSP having a display area DA other than such an elliptical shape.

[0121] Based on the display devices disclosed in the above embodiments, all display devices that can be appropriately designed and modified by those skilled in the art also belong to the scope of the present invention as long as they include the gist of the present invention.

[0122] Within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications, and these modifications are also understood to belong to the scope of the present invention. For example, those obtained by appropriately adding, deleting, or modifying components, or adding, omitting, or changing conditions to the above-described embodiments also fall within the scope of the present invention as long as they have the gist of the present invention.

[0123] In addition, with regard to other operational effects brought about by the aspects described in the above embodiments, those that are obvious from the description in this specification or that can be appropriately conceived by those skilled in the art are naturally construed as being brought about by the present invention.

Description of Reference Numerals

[0124] DSP... display device, DA... display area, SA... peripheral area, PX... pixel, SP1, SP2, SP3... sub-pixels, LE1, LE2, LE3... lower electrodes, OR1, OR2, OR3... organic layers, UE1, UE2, UE3... upper electrodes, SE11, SE12, SE13, SE2... sealing layers, RS1, RS2... resin layers, CL... connection wiring, 5... rib layer, 6... partition wall, 61... lower part, 62... upper part, 63... bottom layer, 64... shaft layer, 7... correction capacitor section, 71, 72... capacitor electrodes.

Claims

1. A plurality of first sub-pixels arranged in the display area, a plurality of second sub-pixels arranged in the display area, a first signal line for supplying a video signal to each of the plurality of first sub-pixels, a second signal line for supplying a video signal to each of the plurality of second sub-pixels, a first correction capacitor unit disposed in a peripheral area around the display area and connected to the first signal line, a second correction capacitor unit disposed in the peripheral area and connected to the second signal line, a serpentine connection wiring connecting the first correction capacitor unit and the second correction capacitor unit, A display device comprising the same.

2. Each of the first correction capacitor unit and the second correction capacitor unit includes a first capacitor electrode and a second capacitor electrode that forms a correction capacitor with the first capacitor electrode, The first capacitor electrode of the first correction capacitor unit is connected to the first signal line, The first capacitor electrode of the second correction capacitor unit is connected to the second signal line, The second capacitor electrode of the first correction capacitor unit and the second capacitor electrode of the second correction capacitor unit are connected to the connection wiring, The display device according to claim 1.

3. The number of the plurality of first sub-pixels is different from the number of the plurality of second sub-pixels, The correction capacitance of the first correction capacitor unit is different from the correction capacitance of the second correction capacitor unit, The display device according to claim 2.

4. The number of the plurality of first sub-pixels is larger than the number of the plurality of second sub-pixels, The correction capacitance of the first correction capacitor unit is smaller than the correction capacitance of the second correction capacitor unit, The display device according to claim 3.

5. The first capacitor electrode of at least one of the first correction capacitor unit and the second correction capacitor unit is formed of the same material as the first signal line and the second signal line on the same layer as the first signal line and the second signal line, The display device according to claim 2.

6. Further comprising a power supply line for supplying a power supply voltage to each of the plurality of first sub-pixels and the plurality of second sub-pixels, Each of the plurality of first sub-pixels and the plurality of second sub-pixels a pixel circuit connected to the power supply line, a lower electrode connected to the pixel circuit, an upper electrode facing the lower electrode, an organic layer located between the lower electrode and the upper electrode and emitting light in response to the application of a voltage, Including, The second capacitor electrode of at least one of the first correction capacitor unit and the second correction capacitor unit is formed of the same material as the power supply line on the same layer as the power supply line, The display device according to claim 5.

7. Each of the plurality of first sub-pixels and the plurality of second sub-pixels includes a pixel circuit including a transistor including a gate electrode and a semiconductor, a lower electrode connected to the pixel circuit, an upper electrode facing the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to an applied voltage. It includes At least one of the first capacitor electrodes of the first correction capacitor portion and the second correction capacitor portion is formed of the same material as the gate electrode in the same layer as the gate electrode. The display device according to claim 2.

8. At least one of the second capacitor electrodes of the first correction capacitor portion and the second correction capacitor portion is formed of the same material as the semiconductor in the same layer as the semiconductor. The display device according to claim 7.

9. Each of the plurality of first sub-pixels and the plurality of second sub-pixels includes a lower electrode, an upper electrode facing the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to an applied voltage. It includes The display device according to any one of claims 1 to 4.

10. It further includes a partition wall surrounding each of the plurality of first sub-pixels and the plurality of second sub-pixels, and the partition wall includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The display device according to claim 9.

11. The upper electrode is in contact with a side surface of the lower portion. The display device according to claim 10.

12. a plurality of sub-pixels arranged in a display area, a signal line for supplying a video signal to each of the plurality of sub-pixels, a power supply line for supplying a power supply voltage to each of the plurality of sub-pixels, and a correction capacitor portion arranged in a peripheral area around the display area and connected to the signal line. It includes Each of the plurality of sub-pixels includes a pixel circuit connected to the signal line and the power supply line, a lower electrode connected to the pixel circuit, an upper electrode facing the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to an applied voltage. It includes The correction capacitor portion includes a first capacitor electrode formed of the same material as the signal line in the same layer as the signal line and connected to the signal line, and a second capacitor electrode formed of the same material as the power supply line in the same layer as the power supply line and forming a correction capacitor with the first capacitor electrode. It is a display device including

13. The correction capacitor portion further includes a third capacitor electrode connected to the signal line, and a fourth capacitor electrode forming a correction capacitor with the third capacitor electrode. It further includes The display device according to claim 12.

14. The pixel circuit includes a transistor including a gate electrode and a semiconductor. The third capacitive electrode is formed of the same material as the gate electrode in the same layer as the gate electrode. The display device according to claim 13.

15. The fourth capacitive electrode is formed of the same material as the semiconductor in the same layer as the semiconductor. The display device according to claim 14.

16. The display device further includes a partition wall surrounding each of the plurality of sub-pixels. The partition wall includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The display device according to claim 13.

17. The upper electrode is in contact with the side surface of the lower portion. The display device according to claim 16.

18. A plurality of sub-pixels arranged in a display area, A signal line for supplying a video signal to each of the plurality of sub-pixels, A correction capacitance unit arranged in a peripheral area around the display area and connected to the signal line, Comprising: Each of the plurality of sub-pixels, Includes a transistor including a gate electrode and a semiconductor, a pixel circuit connected to the signal line, A lower electrode connected to the pixel circuit, An upper electrode facing the lower electrode, An organic layer located between the lower electrode and the upper electrode and emitting light in response to an applied voltage, Including, The correction capacitance unit, A first capacitive electrode formed of the same material as the gate electrode in the same layer as the gate electrode and connected to the signal line, A second capacitive electrode formed of the same material as the semiconductor in the same layer as the semiconductor and forming a correction capacitance with the first capacitive electrode, A display device including.

19. The display device further includes a partition wall surrounding each of the plurality of sub-pixels. The partition wall includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The display device according to claim 18.

20. The upper electrode is in contact with the side surface of the lower portion. The display device according to claim 19.

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