Manufacturing method for display device

Abstract

To suppress decrease in reliability.SOLUTION: A manufacturing method for a display device in an embodiment includes: preparing a process substrate including a lower electrode, an inorganic insulating layer, and a partition wall having a lower part existing on the inorganic insulating layer and an upper part existing on the lower part and projecting from a side surface of the lower part; forming a multilayer film including an upper electrode on the lower electrode in an opening by evaporation using the partition wall as a mask; forming a sealing layer using an inorganic insulating material on the multilayer film; forming a patterned resist on the sealing layer; removing the sealing layer exposed from the resist; and removing the multilayer film exposed from the resist. The removing of the multilayer film includes removing the upper electrode in contact with the lower part with an etchant. The etchant is a mixture of nitric acid, phosphoric acid, and acetic acid. The nitric acid has a concentration of 26% or more. The phosphoric acid has a concentration of 0.5% or more and 10% or less, and the acetic acid has a concentration of 0.5% or more and 15% or less.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to the light-emitting layer. In the process of manufacturing such a display element, a technique for suppressing a decrease in reliability is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a method for manufacturing a display device capable of suppressing a decrease in reliability.

Means for Solving the Problem

[0005] According to one embodiment, a method for manufacturing a display device includes: preparing a processing substrate on which a lower electrode positioned above a substrate, an inorganic insulating layer having an opening overlapping with the lower electrode, and a partition wall including a lower portion positioned on the inorganic insulating layer and an upper portion positioned on the lower portion and protruding from a side surface of the lower portion are formed; forming a laminated film including an upper electrode by vapor deposition using the partition wall as a mask on the lower electrode in the opening; forming a sealing layer with an inorganic insulating material on the laminated film; forming a patterned resist on the sealing layer; removing the sealing layer exposed from the resist; removing the laminated film exposed from the resist; the step of removing the laminated film includes a step of removing the upper electrode in contact with the lower portion with an etching solution, the etching solution is a mixture of nitric acid, phosphoric acid, and acetic acid, the concentration of the nitric acid is 26% or more, the concentration of the phosphoric acid is 0.5% or more and 10% or less, and the concentration of the acetic acid is 0.5% or more and 15% or less.

[0006] According to one embodiment, a method for manufacturing a display device includes: A first lower electrode and a second lower electrode located above the substrate, an inorganic insulating layer having a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode, and a lower part located on the inorganic insulating layer between the first opening and the second opening and an upper part located on the lower part and protruding from the side surface of the lower part. A processing substrate formed with a partition wall is prepared. A laminated film including an upper electrode is formed by vapor deposition using the partition wall as a mask on the first lower electrode in the first opening and on the second lower electrode in the second opening. An encapsulation layer is formed of an inorganic insulating material on the laminated film. A patterned resist is formed on the encapsulation layer located directly above the first lower electrode. The encapsulation layer exposed from the resist is removed to expose the laminated film overlapping the second lower electrode. The laminated film exposed from the resist is removed to expose the second lower electrode from the second opening and to expose the side surface of the lower part facing the second opening. The step of removing the laminated film includes a step of removing the upper electrode in contact with the lower part with an etching solution. The etching solution is a mixture of nitric acid, phosphoric acid, and acetic acid. The concentration of the nitric acid is 26% or more. The concentration of the phosphoric acid is 0.5% or more and 10% or less. The concentration of the acetic acid is 0.5% or more and 15% or less.

Brief Description of Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0008] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each figure, components that exhibit the same or similar functions as those described above with respect to the previously presented figures may be assigned the same reference numerals, and detailed descriptions of duplicates may be omitted as appropriate.

[0009] In the drawings, for ease of understanding if necessary, the X-axis, Y-axis, and Z-axis orthogonal to each other are described. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Looking at various elements parallel to the third direction Z is called a plan view.

[0010] The display device according to the present embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, or the like.

[0011] FIG. 1 is a diagram showing a configuration example of a display device DSP.

[0012] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.

[0013] In the present embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different from each other. Note that the pixel PX may include sub-pixels SP of other colors such as white together with or in place of the sub-pixels SP1, SP2, and SP3.

[0015] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] The display element DE is an organic light emitting diode (OLED) as a light emitting element, and may be referred to as an organic EL element.

[0019] The peripheral region SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along the first direction X. Each of the terminals TE extends in the second direction Y, but is not limited thereto. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0020] FIG. 2 is a diagram showing an example of the layout of the sub-pixels SP1, SP2, and SP3.

[0021] In the illustrated example, the sub-pixels SP2 and SP3 are arranged in the second direction Y. The sub-pixels SP1 and SP2 are arranged in the first direction X, and the sub-pixels SP1 and SP3 are arranged in the first direction X.

[0022] When the sub-pixels SP1, SP2, and SP3 are in such a layout, in the display area DA, a column in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and a column in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed. These columns are alternately arranged in the first direction X.

[0023] Note that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example in FIG. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0024] In the display area DA, an inorganic insulating layer 5 and a partition wall 6 are arranged. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0025] The partition wall 6 overlaps the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3 similar to the inorganic insulating layer 5. The partition wall 6 has conductivity and is electrically connected to the terminal TE having a common potential among the plurality of terminals TE shown in FIG. 1.

[0026] The sub-pixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as display elements DE.

[0027] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the opening AP1, respectively. The peripheral portion of the lower electrode LE1 is covered with the inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by the partition wall 6 in a plan view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap the inorganic insulating layer 5 in a plan view. The organic layer OR1 includes, for example, a light-emitting layer that emits light in the blue wavelength range.

[0028] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that respectively overlap with the aperture AP2. The peripheral portion of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a plan view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 respectively overlap with the inorganic insulating layer 5 in a plan view. The organic layer OR2 includes, for example, a light-emitting layer that emits light in the green wavelength range.

[0029] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively overlap with the aperture AP3. The peripheral portion of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a plan view. The peripheral portions of the organic layer OR3 and the upper electrode UE3 respectively overlap with the inorganic insulating layer 5 in a plan view. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength range.

[0030] In the illustrated example, the outer shapes of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3, and the upper electrodes UE1, UE2, and UE3 are shown by dashed-dotted lines. Note that the outer shapes of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect the exact shapes.

[0031] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes or common electrodes of the display elements and are in contact with the partition wall 6.

[0032] The lower electrode LE1 is electrically connected to the pixel circuit 1 (see FIG. 1) of the sub-pixel SP1. The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0033] In the illustrated example, the area of the opening AP1, the area of the opening AP2, and the area of the opening AP3 are different from each other. The area of the opening AP1 is larger than the area of the opening AP2, and the area of the opening AP2 is larger than the area of the opening AP3. In other words, the area of the lower electrode LE1 exposed from the opening AP1 is larger than the area of the lower electrode LE2 exposed from the opening AP2, and the area of the lower electrode LE2 exposed from the opening AP2 is larger than the area of the lower electrode LE3 exposed from the opening AP3.

[0034] FIG. 3 is a schematic cross-sectional view of the display device DSP along the line A-B in FIG. 2.

[0035] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 is an organic insulating layer that planarizes the unevenness generated by the circuit layer 11.

[0036] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the inorganic insulating layer 5 overlaps the lower electrode LE1, the opening AP2 overlaps the lower electrode LE2, and the opening AP3 overlaps the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted in FIG. 3.

[0037] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width larger than that of the lower portion 61. Both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhang shape.

[0038] In the illustrated example, the lower part 61 has a first conductive layer 63 disposed on the inorganic insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed thinner than the second conductive layer 64. Both ends of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64. The upper part 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both ends of the first thin film 65 and the second thin film 66 protrude from the side surfaces of the second conductive layer 64.

[0039] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower part 61.

[0040] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower part 61.

[0041] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and contacts the lower part 61.

[0042] In the illustrated example, the sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, the sub-pixel SP2 has a cap layer CP2 and a sealing layer SE2, and the sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, CP3 each have a role as an optical adjustment layer for improving the light extraction efficiency of the light emitted from the organic layers OR1, OR2, OR3. Note that the cap layers CP1, CP2, CP3 may be omitted.

[0043] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0044] The sealing layer SE1 is disposed on the cap layer CP1, contacts the partition wall 6, and continuously covers each member of the sub-pixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, contacts the partition wall 6, and continuously covers each member of the sub-pixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, contacts the partition wall 6, and continuously covers each member of the sub-pixel SP3.

[0045] In the following description, a multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is referred to as a stacked film FL1, a multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is referred to as a stacked film FL2, and a multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is referred to as a stacked film FL3.

[0046] In the illustrated example, a part of the stacked film FL1 is located on the partition wall 6 around the sub-pixel SP1 and is separated from the stacked film FL1 (the part constituting the display element DE1) located in the opening AP1. Similarly, a part of the stacked film FL2 is located on the partition wall 6 around the sub-pixel SP2 and is separated from the stacked film FL2 (the part constituting the display element DE2) located in the opening AP2. Similarly, a part of the stacked film FL3 is located on the partition wall 6 around the sub-pixel SP3 and is separated from the stacked film FL3 (the part constituting the display element DE3) located in the opening AP3. Note that the stacked films FL1, FL2, and FL3 on the partition wall 6 may be omitted. In this case, a cavity is formed between the sealing layers SE1, SE2, SE3 and the partition wall 6.

[0047] The ends of the sealing layers SE1, SE2, and SE3 are respectively located on the partition wall 6. In the illustrated example, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are spaced apart from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. Also, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are spaced apart from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0048] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered by the resin layer 13. When cavities are formed between the sealing layers SE1, SE2, SE3 and the partition wall 6, the resin layer 13 fills these cavities. The resin layer 13 is covered by the sealing layer 14. The sealing layer 14 is covered by the resin layer 15.

[0049] The inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3), for example.

[0050] The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound, for example. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper part 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound, for example.

[0051] The upper part 62 of the partition wall 6 is formed of a conductive material, for example, but may also be formed of an insulating material. The upper part 62 is formed of a material different from the lower part 61. The first thin film 65 is formed of a titanium-based material such as titanium or a titanium compound, for example. The second thin film 66 is formed of an oxide conductive material such as indium tin oxide (ITO), for example.

[0052] The lower electrodes LE1, LE2, and LE3 are multilayer bodies including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer bodies including a reflective layer between a pair of transparent layers.

[0053] The organic layer OR1 includes the light-emitting layer EM1. The organic layer OR2 includes the light-emitting layer EM2. The organic layer OR3 includes the light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of different materials from each other. In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength range. Also, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0054] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), for example.

[0055] The cap layers CP1, CP2, and CP3 are multilayer bodies of a plurality of thin films. The plurality of thin films are all transparent and have different refractive indices from each other.

[0056] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are arranged across the display area DA and the peripheral area SA.

[0057] Next, a method for manufacturing the display device DSP will be described. Note that illustrations below the insulating layer 12 are omitted for each figure for explaining the manufacturing method.

[0058] First, as shown in FIG. 4, a processing substrate SUB having lower electrodes LE1, LE2, LE3, an inorganic insulating layer 5, and a partition wall 6 is prepared. The step of preparing the processing substrate SUB includes the following steps. That is, on the substrate 10, a circuit layer 11 and an insulating layer 12 are formed across the display area DA and the peripheral area SA. Thereafter, on the insulating layer 12, the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are formed. Thereafter, an inorganic insulating layer 5 covering the peripheral portions of the lower electrodes LE1, LE2, LE3 is formed. The inorganic insulating layer 5 is formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. Thereafter, a partition wall 6 having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61 is formed. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from the side surface of the second conductive layer 64 of the lower portion 61. The first conductive layer 63 is formed of a titanium-based material, and the second conductive layer 64 is formed of an aluminum-based material. Note that the step of forming the openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before or after forming the partition wall 6.

[0059] Subsequently, a display element DE1 is formed.

[0060] First, as shown in FIG. 5, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The step of forming the laminated film FL1 includes a step of forming an organic layer OR1 in contact with the lower electrode LE1 at the opening AP1, a step of forming an upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6, and a step of forming a cap layer CP1 located on the upper electrode UE1. The step of forming the organic layer OR1 includes steps of forming a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like, respectively. The upper electrode UE1 is formed of a mixture of magnesium and silver.

[0061] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by vapor deposition using the partition wall 6 as a mask. The laminated film FL1 is divided into a plurality of parts by the overhanging partition wall 6. These organic layer OR1, upper electrode UE1, and cap layer CP1 are continuously formed while maintaining a vacuum environment. Such a laminated film FL1 is also formed on the lower electrodes LE2 and LE3.

[0062] Thereafter, a sealing layer SE1 is formed on the laminated film FL1 by depositing an inorganic insulating material. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each divided part of the laminated film FL1 and the partition wall 6.

[0063] Subsequently, as shown in FIG. 6, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps with the sub-pixel SP1 and a part of the surrounding partition wall 6.

[0064] Subsequently, etching is performed using the resist RS as a mask, and the sealing layer SE1 and the laminated film FL1 exposed from the resist RS are sequentially removed. This etching process will be described in detail with reference to an enlarged cross-sectional view including the lower electrodes LE1 and LE2.

[0065] First, as shown in FIG. 7, the sealing layer SE1 exposed from the resist RS is removed. As a result, a part of the cap layer CP1 is exposed on the partition wall 6, and the cap layer CP1 on the lower electrode LE2 is also exposed. Although not shown, the cap layer CP1 on the lower electrode LE3 is also exposed. Further, the side surface of the lower portion 61 (or the second conductive layer 64) of the partition wall 6 facing the lower electrode LE2 is also exposed.

[0066] Subsequently, as shown in FIG. 8, the cap layer CP1 exposed from the resist RS is removed. As a result, a part of the upper electrode UE1 is exposed on the partition wall 6, and the upper electrode UE1 on the lower electrode LE2 is also exposed. Although not shown, the upper electrode UE1 on the lower electrode LE3 is also exposed.

[0067] Subsequently, the exposed upper electrode UE1 is removed from the resist RS. The step of removing the upper electrode UE1 is performed by wet etching using a predetermined etching solution.

[0068] FIG. 9 is a diagram schematically showing a configuration example of an etching apparatus 200 for removing the upper electrode UE1.

[0069] The etching apparatus 200 includes a nozzle 210 that injects the etching solution 211 and a light source 220 that illuminates the inside of the apparatus. The etching solution 211 is a mixture of nitric acid, phosphoric acid, and acetic acid. The concentration of nitric acid is 26% or more. The concentration of phosphoric acid is 0.5% or more and 10% or less. The concentration of acetic acid is 0.5% or more and 15% or less. The concentrations in this specification are all volume % concentrations, and the unit may be expressed as vol%. The light source 220 has an emission line spectrum at a wavelength of 550 nm or more. As the light source 220, for example, it is desirable to use a low-pressure sodium lamp.

[0070] When the processed substrate SUB with the cap layer CP1 removed is carried into the etching apparatus 200, the etching solution 211 is injected from the nozzle 210 toward the processed substrate SUB. The etching solution 211 exposes the side surfaces of the upper electrode UE1 exposed from the resist RS and the lower portion 61 (or the second conductive layer 64) facing the lower electrode LE2.

[0071] Thereby, as shown in FIG. 10, the upper electrode UE1 exposed from the resist RS is removed, and a part of the organic layer OR1 is exposed on the partition wall 6, and the organic layer OR1 on the lower electrode LE2 is also exposed. Although not shown, the organic layer OR1 on the lower electrode LE3 is also exposed.

[0072] Subsequently, as shown in FIG. 11, the organic layer OR1 exposed from the resist RS is removed. Thereby, a part of the upper portion 62 of the partition wall 6 is exposed, and the lower electrode LE2 is exposed.

[0073] As shown in FIG. 12, a stacked film FL1 covered with a resist RS remains in the sub-pixel SP1, the lower electrode LE2 is exposed in the sub-pixel SP2, and the lower electrode LE3 is exposed in the sub-pixel SP3. Thereafter, the resist RS is removed. Thereby, the display element DE1 is formed in the sub-pixel SP1.

[0074] Subsequently, as shown in FIG. 13, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are sequentially formed on the lower electrode LE2 to form a stacked film FL2. Thereafter, a sealing layer SE2 is formed on the stacked film FL2. Thereafter, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. Thereby, the display element DE2 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0075] Subsequently, as shown in FIG. 14, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as the procedure for forming the display element DE1. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are sequentially formed on the lower electrode LE3 to form a stacked film FL3. Thereafter, a sealing layer SE3 is formed on the stacked film FL3. Thereafter, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. Thereby, the display element DE3 is formed in the sub-pixel SP3.

[0076] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in FIG. 3 are sequentially formed. Thereby, the display device DSP is completed.

[0077] In the above manufacturing process, it is assumed that the display element DE1 is first formed, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0078] Figure 15 shows the experimental results of the relationship between the composition ratio of the etching solution and the peeling of the organic layer.

[0079] Among the etching solutions, the concentration of nitric acid was set at 30%. The horizontal axis in the figure corresponds to the concentration of phosphoric acid, and the vertical axis corresponds to the concentration of acetic acid. The time for exposing the processing substrate SUB to the etching solution is 15 to 300 seconds. "〇" in the figure indicates that no peeling of the organic layer occurred when the processing substrate SUB was exposed to the etching solution, and "×" in the figure indicates that peeling of the organic layer occurred when the processing substrate SUB was exposed to the etching solution.

[0080] In the region A surrounded by the solid line in the figure, generally no peeling of the organic layer was confirmed. At this time, the concentration of nitric acid is 30% or more, the concentration of phosphoric acid is 0.5% or more and 10% or less, and the concentration of acetic acid is 0.5% or more and 15% or less. Furthermore, in the region B surrounded by the dashed-dotted line in the figure, no peeling of the organic layer was confirmed at all. At this time, the concentration of nitric acid is 30% or more, the concentration of phosphoric acid is 0.5% or more and 8% or less, and the concentration of acetic acid is 0.5% or more and 8% or less.

[0081] Here, the problem caused by the peeling of the organic layer when removing the upper electrode will be described.

[0082] The organic layer is formed by vapor deposition and is presumed to be in close contact with the lower electrode due to an electrical effect. Therefore, when the ion density of the etching solution increases, the electrostatic action between the lower electrode and the organic layer is inhibited, the adhesion between the two decreases, and the organic layer is likely to peel off.

[0083] On the one hand, the second conductive layer 64 included in the lower portion 61 of the partition wall 6 is formed of an aluminum-based material, and when exposed to an etching solution, it is necessary to prevent undesired etching of the second conductive layer 64. For this reason, from the viewpoint of promoting the oxidation of the surface of the second conductive layer 64, the etching solution needs to contain nitric acid, which is a strong acid with a concentration of 26% or more (desirably 30% or more).

[0084] When such an etching solution reacts with the upper electrode formed of a mixture of magnesium and silver, it ionizes into nitrate ions (NO3-) and silver ions (Ag+). Silver has a lower ionization tendency compared to aluminum. For this reason, silver ions receive electrons from aluminum, precipitate as silver, and aluminum flows out as ions.

[0085] When the organic layer peels off during the etching process of the upper electrode, the lower electrode is exposed, and a battery effect occurs between the lower electrode and the upper electrode through the etching solution. The exchange of electrons as described above is further promoted by this battery effect. Therefore, when the second conductive layer 64 of the partition wall 6 is exposed to the etching solution, aluminum is excessively eluted, and the side surface of the second conductive layer 64 recedes. In some cases, the etching solution may penetrate into the second conductive layer 64 and cavities may be formed in the second conductive layer 64. Such a phenomenon occurs on the side surface of the second conductive layer 64 facing the display elements DE2 and DE3. For this reason, poor connection between the upper electrode and the second conductive layer 64 in the display elements DE2 and DE3 is caused. Further, when cavities are formed, deterioration of the organic layer in the display elements DE2 and DE3 is caused by the moisture remaining in the cavities. Further, the growth of the precipitated silver in the partition wall 6 causes deterioration of the sealing performance in the display elements DE2 and DE3.

[0086] For this reason, it is extremely important to suppress peeling of the organic layer when etching the upper electrode. For example, in the process of forming the display element DE1, when etching the upper electrode UE1, it is required that the organic layer OR1 covers the lower electrodes LE2 and LE3, and in the process of forming the display element DE2, when etching the upper electrode UE2, it is required that the organic layer OR2 covers the lower electrode LE3.

[0087] Therefore, in the present embodiment, in addition to the above nitric acid, a mixture of phosphoric acid having a concentration of 0.5% or more and 10% or less and acetic acid having a concentration of 0.5% or more and 15% or less is used as an etching solution. Phosphate ions (PO4 3- ) contained in the etching solution are likely to bind to silver ions contained in the etching solution. For this reason, silver ions in the etching solution can be reduced, the electron exchange between silver ions and aluminum is suppressed, and silver deposition can be suppressed. Acetic acid contained in the etching solution exhibits an effect as a surfactant and can suppress insufficient etching of the upper electrode.

[0088] And for phosphoric acid and acetic acid, it is desirable that their concentrations be low enough to exhibit the above functions. When the concentrations of phosphoric acid and acetic acid in the etching solution are high, the ion density contained in the etching solution increases, and as described above, the electrostatic action between the lower electrode and the organic layer is inhibited, and peeling of the organic layer is likely to occur. For this reason, phosphoric acid is 10% or less, desirably 8% or less. Also, acetic acid is 15% or less, desirably 8% or less.

[0089] By applying such an etching solution, peeling of the organic layer is suppressed during the etching process of the upper electrode. Thereby, excessive recession of the side surface of the second conductive layer 64, formation of voids in the second conductive layer 64, and deposition of undesired silver as described above can be suppressed. Therefore, connection failure between the upper electrode and the second conductive layer 64 in the display elements DE2 and DE3, deterioration of the organic layer in the display elements DE2 and DE3, and deterioration of the sealing performance in the display elements DE2 and DE3 can be suppressed, and a decrease in reliability is suppressed.

[0090] Further, the light source 220 of the etching apparatus 200 has an emission line spectrum at a wavelength of 550 nm or more. Silver phosphate formed by phosphate ions and silver ions in the etching solution is known to absorb light with a wavelength shorter than 550 nm and decompose. Therefore, by applying the above light source 220, the decomposition of silver phosphate can be suppressed, and silver deposition can be suppressed.

[0091] The inventor variously examined the etching time for exposing the processing substrate SUB to the etching solution in the range of 15 to 300 seconds. According to this, from the viewpoint of suppressing silver deposition, it is desirable that the etching time be as short as possible, and it is desirable that the etching time be 120 seconds or less. Further, from the viewpoint of suppressing insufficient etching of the upper electrode, it is desirable that the etching time be as long as possible, and it is desirable that the etching time be 60 seconds or more.

[0092] In the above embodiment, for example, in the inorganic insulating layer 5, the opening AP1 corresponds to the first opening, and the opening AP2 corresponds to the second opening. The lower electrode LE1 corresponds to the first lower electrode, and the lower electrode LE2 corresponds to the second lower electrode. The organic layer OR1 corresponds to the first organic layer, and the organic layer OR2 corresponds to the second organic layer. The upper electrode UE1 corresponds to the first upper electrode, and the upper electrode UE2 corresponds to the second upper electrode.

[0093] As described above, according to the present embodiment, it is possible to provide a method for manufacturing a display device capable of suppressing a decrease in reliability.

[0094] Based on the method for manufacturing a display device described as an embodiment of the present invention above, all methods for manufacturing a display device that can be appropriately designed and modified by those skilled in the art also belong to the scope of the present invention as long as they include the gist of the present invention.

[0095] Within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications, and those modifications are also understood to belong to the scope of the present invention. For example, with respect to the above-described embodiments, those obtained by appropriately adding, deleting, or changing the design of components by those skilled in the art, or those obtained by adding, omitting, or changing conditions of processes, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0096] In addition, with respect to other operational effects brought about by the aspects described in the above-described embodiments, those that are obvious from the description of this specification or those that can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0097] DSP... Display device 10... Substrate 5... Inorganic insulating layer AP1, AP2, AP3... Aperture 6... Partition wall 61... Lower part 62... Upper part 63... First conductive layer 64... Second conductive layer SP1, SP2, SP3... Sub-pixels DE1, DE2, DE3... Display elements (organic EL elements) LE1, LE2, LE3... Lower electrodes UE1, UE2, UE3... Upper electrodes OR1, OR2, OR3... Organic layers CP1, CP2, CP3... Cap layers SE1, SE2, SE3... Encapsulation layers DA... Display area SA... Peripheral area SUB... Processing substrate 200... Etching device 210... Nozzle 211... Etching solution 220... Light source

Claims

1. Prepare a processing substrate formed with a lower electrode positioned above a substrate, an inorganic insulating layer having an opening overlapping with the lower electrode, and a partition wall including a lower portion positioned on the inorganic insulating layer and an upper portion positioned on the lower portion and protruding from a side surface of the lower portion. Form a laminated film including an upper electrode by vapor deposition using the partition wall as a mask on the lower electrode in the opening. Form a sealing layer of an inorganic insulating material on the laminated film. Form a patterned resist on the sealing layer. Remove the sealing layer exposed from the resist. Remove the laminated film exposed from the resist. The step of removing the laminated film includes a step of removing the upper electrode in contact with the lower portion with an etching solution. The etching solution is a mixture of nitric acid, phosphoric acid, and acetic acid. The concentration of the nitric acid is 26% or more. The concentration of the phosphoric acid is 0.5% or more and 10% or less. The concentration of the acetic acid is 0.5% or more and 15% or less. A method for manufacturing a display device.

2. The concentration of the phosphoric acid is 8% or less. The method for manufacturing a display device according to Claim 1.

3. The concentration of the acetic acid is 8% or less. The method for manufacturing a display device according to Claim 2.

4. The concentration of the nitric acid is 30% or more. The method for manufacturing a display device according to Claim 3.

5. The time for removing the upper electrode with the etching solution is 60 seconds or more and 120 seconds or less. The method for manufacturing a display device according to Claim 1.

6. The step of removing the upper electrode with the etching solution is performed under a light source having an emission line spectrum at a wavelength of 550 nm or more. The method for manufacturing a display device according to Claim 1.

7. Use a sodium lamp as the light source. The method for manufacturing a display device according to Claim 6.

8. Among the lower portion, a first conductive layer positioned on the inorganic insulating layer is formed of a titanium-based material, and a second conductive layer positioned between the first conductive layer and the upper portion is formed of an aluminum-based material. The method for manufacturing a display device according to Claim 1.

9. The upper electrode is formed of a mixture of magnesium and silver. The method for manufacturing a display device according to Claim 8.

10. The step of forming the laminated film includes: a step of forming an organic layer including a light-emitting layer on the lower electrode; a step of forming an upper electrode on the organic layer; a step of forming a cap layer on the upper electrode. When removing the sealing layer, a part of the lower part and the cap layer are exposed. In the step of removing the upper electrode with the etching solution, a part of the lower part is exposed to the etching solution. The method of manufacturing a display device according to claim 9.

11. Prepare a processed substrate formed with a first lower electrode and a second lower electrode located above the substrate, an inorganic insulating layer having a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode, and a partition wall including a lower part located on the inorganic insulating layer between the first opening and the second opening and an upper part located on the lower part and protruding from the side surface of the lower part. Form a laminated film including an upper electrode by vapor deposition using the partition wall as a mask on the first lower electrode in the first opening and on the second lower electrode in the second opening. Form a sealing layer of an inorganic insulating material on the laminated film. Form a patterned resist on the sealing layer located directly above the first lower electrode. Remove the sealing layer exposed from the resist to expose the laminated film overlapping the second lower electrode. Remove the laminated film exposed from the resist to expose the second lower electrode from the second opening and to expose the side surface of the lower part facing the second opening. The step of removing the laminated film includes a step of removing the upper electrode in contact with the lower part with an etching solution. The etching solution is a mixture of nitric acid, phosphoric acid, and acetic acid. The concentration of the nitric acid is 26% or more. The concentration of the phosphoric acid is 0.5% or more and 10% or less. The concentration of the acetic acid is 0.5% or more and 15% or less. The method of manufacturing a display device.

Images