Electronic device

Abstract

To provide an electronic device that permits an improvement in signal waveform quality.SOLUTION: A plurality of wirings included on a wiring board PCB has: a plurality of wirings WR1t that respectively transmit, to two memory devices ME1 and ME2 loaded on a surface 20, a clock signal CK1 and a chip select signal CS1; and a plurality of wirings WR1b that respectively transmit, to two memory devices ME3 and ME4 loaded on a rear surface 21, a clock signal CK2 and a chip select signal CS2. Here, the plurality of wirings WR1b are provided at a wiring layer 15 on a surface side out of a plurality of wiring layers, and the plurality of wirings WR1b are provided at a wiring layer 16 on a rear surface side out of the plurality of wiring layers.SELECTED DRAWING: Figure 4A

Description

Technical Field

[0001] The present invention relates to an electronic device, for example, an electronic device having a control device and a plurality of memory devices mounted on a wiring board.

Background Art

[0002] Patent Document 1 (Japanese Patent Application Laid-Open No. 2015-35159) discloses an electronic device capable of mitigating the influence of signal reflection even when a branch wiring associated with a fly-by topology is long. The electronic device includes a mounting board on which a plurality of first semiconductor components and a second semiconductor component for controlling them are mounted. The mounting board includes a main wiring and a branch wiring that electrically connect the second semiconductor component and the plurality of first semiconductor components. A chip resistor is connected in series in the middle of the branch wiring leading to the first semiconductor component.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, miniaturization of electronic devices, that is, reduction of the mounting area of each device on a wiring board has been demanded. In addition to this, particularly with the increase in the speed of electronic devices, improvement in waveform quality has been demanded for each signal propagating within the wiring board. As a method for improving waveform quality, for example, as shown in Patent Document 1, a method of providing a resistance element for attenuating a reflected signal can be considered. However, when a resistance element is provided, the mounting area increases. Therefore, a mechanism capable of enhancing waveform quality without providing such a resistance element is desired.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problem

[0006] An electronic device according to an embodiment has a first surface and a second surface opposite to the first surface, and includes a wiring board including a plurality of wiring layers and a plurality of wirings, a first memory device and a second memory device mounted on the first surface, a third memory device and a fourth memory device mounted on the second surface, and a control device. The control device is mounted on the first surface and accesses each of the first and second memory devices using a common first clock signal and a common first chip select signal, and accesses each of the third and fourth memory devices using a common second clock signal and a common second chip select signal. The plurality of wirings include a plurality of first wirings that respectively propagate the first clock signal and the first chip select signal, and a plurality of second wirings that respectively propagate the second clock signal and the second chip select signal. Here, the plurality of first wirings are provided in a wiring layer closer to the first surface than the second surface among the plurality of wiring layers, and the plurality of second wirings are provided in a wiring layer closer to the second surface than the first surface among the plurality of wiring layers.

Advantages of the Invention

[0007] By using the electronic device according to an embodiment, the waveform quality of a signal can be improved.

Brief Description of the Drawings

[0008]

Figure 1A

Figure 1B

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Figure 8A

Figure 8B

Figure 9

Figure 10

Figure 11A

Figure 11B

Figure 12

Figure 13

Figure 14

Figure 15A

Figure 15B

Figure 16

Figure 17A

Figure 17B

Embodiments for Carrying Out the Invention

[0009] In the following embodiments, when necessary for convenience, they will be described by being divided into a plurality of sections or embodiments. However, unless otherwise specifically stated, they are not unrelated to each other, and one is related to a partial or entire modification example, details, supplementary explanation, etc. of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specifically stated and unless it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number.

[0010] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, except in cases where it is specifically stated and in cases where it is considered clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it shall include those that are substantially approximated or similar to the shape, etc., except in cases where it is specifically stated and in cases where it is considered clearly not so in principle. This also applies to the above numerical values and ranges.

[0011] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated descriptions thereof are omitted. Further, in the following embodiments, descriptions of the same or similar parts will not be repeated in principle, except when particularly necessary.

[0012] (First Embodiment) <Schematic of the Whole Electronic Device> FIGS. 1A and 1B are plan views showing a schematic configuration example of an electronic device according to the first embodiment. The electronic device 10 shown in FIGS. 1A and 1B includes a wiring substrate PCB, a plurality of memory devices ME, and a control device CTL. The electronic device 10 can be particularly applied to a signal processing device or an information processing device that requires a broadband and large-capacity memory, such as a data center, a network base station, a game terminal, etc.

[0013] The wiring substrate PCB has a surface (first surface) 20 and a back surface (second surface) 21 opposite to this surface 20, and includes a plurality of wiring layers and a plurality of wirings. FIGS. 1A and 1B show configuration examples of the surface 20 and the back surface 21 of the wiring substrate PCB, respectively. In the specification, the directions orthogonal to each other are defined as the X-axis direction, the Y-axis direction, and the Z-axis direction. The plane direction of the wiring substrate PCB is called the X-axis direction and the Y-axis direction, and the thickness direction of the wiring substrate PCB is called the Z-axis direction.

[0014] Each of the plurality of memory devices ME is, for example, DDR5_SDRAM (Double Data Rate 5_Synchronous Dynamic Random Access Memory) or the like. In this example, 32 memory devices ME are mounted on each of the front surface 20 and the back surface 21 of the wiring board PCB. The 32 memory devices ME mounted on the front surface 20 are arranged, for example, along the outer periphery of the wiring board PCB (here, three sides out of four sides) and in a 2-row and 16-column form. The 32 memory devices ME mounted on the back surface 21 are arranged to face the 32 memory devices ME mounted on the front surface 20 in the Z-axis direction.

[0015] The control device CTL is, for example, an SoC (System on Chip) including various circuit blocks typified by a processor. The control device CTL is mounted on the front surface 20 of the wiring board PCB and is arranged near the center of the wiring board PCB in this example. The control device CTL includes a plurality of memory interfaces for accessing the plurality of memory devices ME. In this example, two memory interfaces MIF1 and MIF2 among the plurality of memory interfaces are illustrated.

[0016] FIG. 2 is a plan view showing a configuration example focusing on a partial region 11 in FIGS. 1A and 1B. In FIG. 2, the memory interface MIF1 is connected to two memory devices ME1 and ME2 mounted on the front surface 20 of the wiring board PCB and two memory devices ME3 and ME4 mounted on the back surface 21 so as to face them via a plurality of wirings WR1 in the wiring board PCB. Similarly, the memory interface MIF2 is connected to two memory devices ME5 and ME6 mounted on the front surface 20 of the wiring board PCB and two memory devices ME7 and ME8 mounted on the back surface 21 so as to face them via a plurality of wirings WR2 in the wiring board PCB.

[0017] The two memory devices ME1 and ME2 are arranged side by side in the X-axis direction. The two memory devices ME5 and ME6 are also arranged side by side in the X-axis direction. The memory device ME1 and the memory device ME5 are arranged side by side in the Y-axis direction on the side closer to the control device CTL. The memory device ME2 and the memory device ME6 are arranged side by side in the Y-axis direction on the side farther from the control device CTL.

[0018] Also, the memory interfaces MIF1 and MIF2 are arranged side by side in the X-axis direction. And the memory interface MIF2, and thus its external terminals, are arranged inside the control device CTL compared to the memory interface MIF1, and thus its external terminals. In other words, the memory interface MIF1 is arranged on the outer peripheral side of the control device CTL compared to the memory interface MIF2.

[0019] Here, in FIG. 1A, more specifically, a set of memory interfaces MIF1 and MIF2 as shown in FIG. 2 are arranged side by side along the outer periphery of the control device CTL. In the example of FIG. 1A, eight sets of memory interfaces MIF1 and MIF2 are provided. In this way, by arranging the memory interfaces MIF1 and MIF2 side by side in the X-axis direction instead of the Y-axis direction, the length of the outer periphery of the control device CTL can be shortened, and the size of the control device CTL, and thus the electronic device 10, can be reduced.

[0020] FIG. 3 is a circuit diagram showing an example of the connection relationship between the memory interfaces MIF1 and MIF2 and the memory devices ME1 - ME8 in FIG. 2. Each of the memory devices ME1 - ME8 inputs and outputs a "k + 1" - bit data signal DQ[k:0] mainly by inputting control signals including a clock signal CK, a chip select signal CS, and a "i + 1" - bit command address signal CA[i:0]. The clock signal CK is more specifically composed of a positive clock signal CK(t) and a negative clock signal CK(c) that form a differential pair.

[0021] Memory devices ME1, ME2, ME5, and ME6 mounted on the surface 20 of the wiring board constitute the memory device ME of rank 0. Memory devices ME3, ME4, ME7, and ME8 mounted on the back surface of the wiring board constitute the memory device ME of rank 1. Memory interface MIF1 accesses memory devices ME1 and ME2 of rank 0 using a common clock signal CK0 and a common chip select signal CS0.

[0022] Also, memory interface MIF1 accesses memory devices ME3 and ME4 of rank 1 using a common clock signal CK1 and a common chip select signal CS1 different from the clock signal CK0 and the chip select signal CS0. Further, memory interface MIF1 outputs a common command address signal CA to memory devices ME1 - ME4 of rank 0 and rank 1.

[0023] When memory interface MIF1 accesses memory devices ME1 and ME2 of rank 0, it inputs and outputs the data signal DQ of memory device ME1 as a lower data signal DQ - L, and inputs and outputs the data signal DQ of memory device ME2 as an upper data signal DQ - U. On the other hand, when memory interface MIF1 accesses memory devices ME3 and ME4 of rank 1, it inputs and outputs the data signal DQ of memory device ME3 as a lower data signal DQ - L, and inputs and outputs the data signal DQ of memory device ME4 as an upper data signal DQ - U.

[0024] Similar to the case of memory interface MIF1, memory interface MIF2 accesses memory devices ME5 and ME6 of rank 0 using a common clock signal CK2 and a common chip select signal CS2. Also, memory interface MIF2 accesses memory devices ME7 and ME8 of rank 1 using a common clock signal CK3 and a common chip select signal CS3. Further, memory interface MIF2 outputs a common command address signal CA to memory devices ME5 - ME8 of rank 0 and rank 1.

[0025] When the memory interface MIF2 accesses the memory devices ME5 and ME6 of rank 0, it inputs and outputs the data signal DQ of the memory device ME5 as the lower data signal DQ-L, and inputs and outputs the data signal DQ of the memory device ME6 as the upper data signal DQ-U. On the other hand, when the memory interface MIF2 accesses the memory devices ME7 and ME8 of rank 1, it inputs and outputs the data signal DQ of the memory device ME7 as the lower data signal DQ-L, and inputs and outputs the data signal DQ of the memory device ME8 as the upper data signal DQ-U.

[0026] The clock signal CK0 and chip select signal CS0, and the clock signal CK2 and chip select signal CS2 are output in parallel in time. Similarly, the clock signal CK1 and chip select signal CS1, and the clock signal CK3 and chip select signal CS3 are output in parallel in time. Therefore, focusing on the relationship between the memory interface MIF2 and the memory devices ME5 - ME8, the clock signals CK2, CK3 and chip select signals CS2, CS3 are respectively the clock signals CK0, CK1 and chip select signals CS0, CS1 as well.

[0027] Here, for example, assume that the data signal DQ[k:0] is 8 bits, that is, 1 byte. In this case, the control device CTL accesses the memory device ME of rank 0 in FIG. 1A using the clock signal CK0 and chip select signal CS0, and inputs and outputs a total of 32 bytes of data signals DQ-L and DQ-U. Similarly, the control device CTL accesses the memory device ME of rank 1 in FIG. 1B using the clock signal CK1 and chip select signal CS1, and inputs and outputs a total of 32 bytes of data signals DQ-L and DQ-U.

[0028] <Schematic cross-sectional configuration of the electronic device> FIG. 4A is a cross-sectional view showing a schematic configuration example regarding the clock signal and the chip select signal between A-A' in FIG. 2. FIG. 4B is a cross-sectional view showing a schematic configuration example regarding the clock signal and the chip select signal between B-B' in FIG. 2. Here, for easier explanation of the configuration, the cross-sectional configuration between A-A' is shown divided into two figures. The same applies to the cross-sectional configuration between B-B'.

[0029] In FIG. 4A, the control device CTL includes a semiconductor chip CP and a package substrate PKG on which the semiconductor chip CP is mounted. A memory interface MIF1 formed on the semiconductor chip CP is connected to the package substrate PKG via an external terminal of the semiconductor chip CP. Further, the memory interface MIF1 is connected to an external terminal PNc1 of the control device CTL via an internal wiring of the package substrate PKG.

[0030] The wiring substrate PCB includes a plurality of wiring layers sequentially laminated with an insulating layer interposed therebetween in the Z-axis direction, wirings formed in each wiring layer, and a plurality of through-via wirings VAt1 - VAt3, VAb1 - VAb3. In the specification, the plurality of through-via wirings are collectively referred to as through-via wiring VA. The through-via wiring VA is provided so as to penetrate a plurality of wiring layers between the front surface 20 and the back surface 21 of the wiring substrate PCB. Among the plurality of wirings formed in a predetermined wiring layer, there are included a plurality of wirings WR1t and a plurality of wirings WR1b.

[0031] The plurality of wirings WR1t propagate the clock signal CK0 and the chip select signal CS0 propagated from the external terminal PNc1 via the through-via wiring VAt1 to the memory devices ME1, ME2 of rank 0, respectively. At this time, the through-via wiring VAt2 connects the plurality of wirings WR1t to the external terminal PNm of only the memory device ME1 among the memory devices ME1, ME3. The through-via wiring VAt3 connects the plurality of wirings WR1t to the external terminal PNm of only the memory device ME2 among the memory devices ME2, ME4.

[0032] On one hand, a plurality of wirings WR1b propagate the clock signal CK1 and the chip select signal CS1 propagated from the external terminal PNc1 via the through-via wiring VAb1 to the memory devices ME3 and ME4 of rank 1, respectively. At this time, the through-via wiring VAb2 connects the plurality of wirings WR1b to the external terminal PNm of only the memory device ME3 among the memory devices ME1 and ME3. The through-via wiring VAb3 connects the plurality of wirings WR1b to the external terminal PNm of only the memory device ME4 among the memory devices ME2 and ME4.

[0033] More specifically, the number of the plurality of wirings WR1t is three for propagating a pair of clock signals CK0 and the chip select signal CS0, respectively. The same applies to the number of the plurality of wirings WR1b. Further, the number of each of the external terminal PNc1 and the through-via wirings VAt1 - VAt3, VAb1 - VAb3 is also provided in the same number as the number of signals.

[0034] On the other hand, in FIG. 4B, the memory interface MIF2 formed on the semiconductor chip CP is connected to the package substrate PKG via the external terminal of the semiconductor chip CP. Further, the memory interface MIF2 is connected to the external terminal PNc2 of the control device CTL via the internal wiring of the package substrate PKG. The memory interface MIF2 is formed inside the semiconductor chip CP more than the memory interface MIF1 shown in FIG. 4A. Along with this, the external terminal PNc2 is also arranged inside the control device CTL more than the external terminal PNc1 shown in FIG. 4A.

[0035] The wiring substrate PCB includes a plurality of through-via wirings VAt4-VAt6, VAb4-VAb6 in addition to a plurality of wiring layers and a plurality of wirings. Among the plurality of wirings formed on a predetermined wiring layer, there are included a plurality of wirings WR2t and a plurality of wirings WR2b. The plurality of wirings WR2t propagate the clock signal CK0 and the chip select signal CS0 propagated from the external terminal PNc2 via the through-via wiring VAt4 to the memory devices ME5, ME6 of rank 0, respectively. At this time, the through-via wiring VAt5 connects the plurality of wirings WR2t to the external terminal PNm of only the memory device ME5 among the memory devices ME5, ME7. The through-via wiring VAt6 connects the plurality of wirings WR2t to the external terminal PNm of only the memory device ME6 among the memory devices ME6, ME8.

[0036] On the other hand, the plurality of wirings WR2b propagate the clock signal CK1 and the chip select signal CS1 propagated from the external terminal PNc2 via the through-via wiring VAb4 to the memory devices ME7, ME8 of rank 1, respectively. At this time, the through-via wiring VAb5 connects the plurality of wirings WR2b to the external terminal PNm of only the memory device ME7 among the memory devices ME5, ME7. The through-via wiring VAb6 connects the plurality of wirings WR2b to the external terminal PNm of only the memory device ME8 among the memory devices ME6, ME8. Note that the more detailed numbers such as the wiring WR2b are the same as in the case of FIG. 4A.

[0037] FIG. 5 is a cross-sectional view showing a schematic configuration example regarding the command address signal between A-A' in FIG. 2. Although illustration is omitted, the cross-sectional configuration between B-B' is also the same as in the case of FIG. 5. In FIG. 5, the memory interface MIF1 formed on the semiconductor chip CP is connected to the package substrate PKG via the external terminal of the semiconductor chip CP. Further, the memory interface MIF1 is connected to the external terminal PNc of the control device CTL via the internal wiring of the package substrate PKG. The wiring substrate PCB includes a plurality of through-via wirings VA1-VA3 in addition to a plurality of wiring layers and a plurality of wirings.

[0038] Among a plurality of wirings formed in a predetermined wiring layer, a plurality of wirings WR1tb are included. The plurality of wirings WR1tb each propagate a plurality of command address signals CA propagated from an external terminal PNc via a through-via wiring VA1 to memory devices ME1 - ME4 of rank 0 and rank 1. At this time, the through-via wiring VA2 commonly connects the plurality of wirings WR1tb to the external terminals PNm of the memory devices ME1 and ME3. The through-via wiring VA3 commonly connects the plurality of wirings WR1tb to the external terminals PNm of the memory devices ME2 and ME4. More specifically, the number of wirings such as WR1tb is determined based on the number of command address signals CA.

[0039] <Details of the problem and comparative examples> FIGS. 15A and 15B are diagrams schematically illustrating an example of problems in a general electronic device. In FIG. 15A, a portion related to rank 0 among the configuration examples shown in FIG. 4A is shown in a simplified manner. In FIG. 15B, an example of each signal waveform propagated within the configuration shown in FIG. 15A is shown.

[0040] For example, in an electronic device constituting a next-generation network processor or the like, a broadband and large-capacity memory may be required. For this reason, as shown in FIG. 15A, by branching a wiring WR for propagating a control signal into two by two through-via wirings VA, the same wiring WR may be connected to two memory devices ME1 and ME2. Thereby, a small-bit memory can be treated as if it were a multi-bit memory, and a broadband memory can be realized. Such a method is also called a fly-by method.

[0041] However, when using the fly-by method, as shown in FIGS. 15A and 15B, the reflected signal SG2 reflected at the far-side branch overlaps with the input signal SG1 of the memory device ME1 arranged at the branch closer to the control device CTL. As a result, particularly in the input signal "SG1+SG2" of the memory device ME1 arranged at the closer branch, the waveform quality deteriorates, and there is a risk of errors occurring when accessing the memory device ME1.

[0042] Furthermore, for the purpose of increasing the memory capacity, as shown in FIG. 4A and the like, two ranks of memory devices ME separated by a chip select signal CS may be mounted on both sides of the wiring board PCB. Such a method is also called Clamshell. However, with the recent increase in system functionality, the number of wiring layers increases and the wiring board PCB tends to become thicker. Along with this, when using the Clamshell configuration, the through-via wiring VA also becomes longer. As a result, the magnitude of the reflected signal SG2 further increases, and a further deterioration in waveform quality may occur.

[0043] Therefore, as shown in FIG. 15A, it is conceivable to insert a resistor element Rd, that is, a damping resistor, in series in the wiring near the external terminal PNm of the memory device ME1 arranged at the closer branch. Thereby, the reflected signal SG2 generated at the far-side branch is attenuated before being input to the memory device ME1 arranged at the closer branch. However, the resistor element Rd attenuates not only the reflected signal SG2 but also the normal input signal SG1. That is, the attenuation of the normal input signal SG1 and the attenuation of the reflected signal SG2 are in a trade-off relationship.

[0044] The attenuation of the regular input signal SG1 means that power is being wasted. Also, if resistance elements Rd as shown in FIG. 15A are provided for the number of signals, the mounting area of the wiring board PCB increases, and it may become difficult to miniaturize the electronic device. Furthermore, component costs and the like associated with the mounting of the resistance elements Rd may also increase. For this reason, it is desirable to improve the waveform quality without providing the resistance elements Rd. Also, the through via wiring VA causes signal reflection due to impedance mismatch and attenuates the passing signal by the amount of the reflection. This signal attenuation is also desirably minimized.

[0045] FIG. 16 is a diagram showing an example of the waveform shapes of the clock signals CK respectively input by two memory devices ME1 and ME2 in FIG. 15A. As yet another problem, when the fly-by method is used, the waveform shapes of the clock signal CK input by the memory device ME1 and the waveform shape of the clock signal CK input by the memory device ME2 may become asymmetric with respect to each other due to repeated signal reflection at the branch points. This is because the amount and timing of the combined reflected signals are different between the side closer to the control device CTL and the side farther from it.

[0046] In FIG. 16, for example, it is desirable that the waveform shape of the negative clock signal CK(c) input to the memory device ME1 and the waveform shape of the positive clock signal CK(t) input to the memory device ME2 be equivalent. However, in FIG. 16, these have completely different waveform shapes from each other. As a result, for example, a decrease in the operating margin may occur.

[0047] FIG. 17A is a cross-sectional view showing a configuration example different from that of FIG. 4A in an electronic device according to a comparative example. FIG. 17B is a cross-sectional view showing a configuration example different from that of FIG. 4B in an electronic device according to a comparative example. FIGS. 17A and 17B show configuration examples based on a general concept. For example, when wiring is drawn out from a control device CTL mounted on the surface 20 of a wiring board PCB, generally, the wiring drawn out from the end side of the device is assigned to the wiring layer on the surface side, and the wiring drawn out from the inside of the device is assigned to the wiring layer on the back side. Thereby, wiring can be performed so that the wiring drawn out from the end side of the device does not obstruct the wiring drawn out from the inside.

[0048] Based on this concept, when the memory interfaces MIF1 and MIF2 are arranged as shown in FIG. 2, a plurality of wirings WR1 drawn out from the memory interface MIF1 located at the end side of the device are assigned to the wiring layer on the surface side. On the other hand, a plurality of wirings WR2 drawn out from the memory interface MIF2 located inside the device are assigned to the wiring layer on the back side. That is, the wiring layer to be assigned is determined by the arrangement of the memory interfaces MIF1 and MIF2.

[0049] Accordingly, in the example of FIG. 17A, both the plurality of wirings WR1t and the plurality of wirings WR1b are assigned to the wiring layer 15 on the surface side. Similar to the case of FIG. 4A, the plurality of wirings WR1t propagate the clock signal CK0 and the chip select signal CS0 from the memory interface MIF1 to the memory devices ME1 and ME2 of rank 0. The plurality of wirings WR1b propagate the clock signal CK1 and the chip select signal CS1 from the same memory interface MIF1 to the memory devices ME3 and ME4 of rank 1.

[0050] On the other hand, in the example of FIG. 17B, the plurality of wirings WR2t and the plurality of wirings WR2b are both assigned to the backside wiring layer 16. Similar to the case of FIG. 4B, the plurality of wirings WR2t propagate the clock signal CK0 and the chip select signal CS0 from the memory interface MIF2 to the memory devices ME5 and ME6 of rank 0. The plurality of wirings WR2b propagate the clock signal CK1 and the chip select signal CS1 from the same memory interface MIF2 to the memory devices ME7 and ME8 of rank 1.

[0051] Here, in FIG. 17A, for example, focusing on the signal paths of the chip select signals CS0 and CS1, the lengths of the through-via wirings VA along the signal paths are different between the case of accessing rank 0 and the case of accessing rank 1. As a specific example, the through-via wiring VAt3 for connecting to the memory device ME2 of rank 0 specifically has a via portion SBt1 for signal propagation and an open stub SBo1.

[0052] The via portion SBt1 for signal propagation is a via portion for propagating a signal to the target memory device ME. Here, the via portion SBt1 for signal propagation is composed of a section from the connection point with the wiring WR1t to the surface 20 of the wiring board PCB. On the other hand, the open stub SBo1 is a stub having an open end. Here, the open stub SBo1 is composed of a section from the connection point with the wiring WR1t to the back surface 21 of the wiring board PCB.

[0053] Similarly, the through-via wiring VAb3 for connecting to the memory device ME4 of rank 1 also has a via portion SBt2 for signal propagation and an open stub SBo2. Here, contrary to the case of the through-via wiring VAt3, the via portion SBt2 for signal propagation is composed of a section from the connection point with the wiring WR1b to the back surface 21 of the wiring board PCB. On the other hand, the open stub SBo2 is composed of a section from the connection point with the wiring WR1b to the surface 20 of the wiring board PCB.

[0054] Here, when accessing rank 0, the length of the via portion SBt1 for signal propagation is "h1". In contrast, when accessing rank 1, the length of the via portion SBt2 for signal propagation is "h2", which is longer than "h1". In other words, the length of the open stub SBo1 is "h2", while the length of the open stub SBo2 is "h1", which is shorter than "h2".

[0055] Also in FIG. 17B, as in the case of FIG. 17A, the length of the through-via wiring VA along the signal path is different between the case of accessing rank 0 and the case of accessing rank 1. That is, in the through-via wiring VAt6 for accessing rank 0, the length of the via portion SBt1 for signal propagation is "h2". On the other hand, in the through-via wiring VAb6 for accessing rank 1, the length of the via portion SBt2 for signal propagation is "h1", which is shorter than "h2". Here, the signal paths of the chip select signals CS0, CS1 are taken as an example for explanation, but the same applies to the signal paths of the clock signals CK0, CK1.

[0056] Thus, when the length of the through-via wiring VA along the signal path is different between the case of accessing rank 0 and the case of accessing rank 1, the waveforms of the reflected signals as described in FIGS. 15A and 15B are different between the case of accessing rank 0 and the case of accessing rank 1. As a result, the signals reaching the front and back memory devices ME become asymmetric. Consequently, when accessing the memory device ME, a decrease in the operation margin may occur. This is because the overall operation margin is determined based on the worse waveform quality. Also, when the operation margin decreases, errors may occur when accessing the memory device ME.

[0057] Here, particularly regarding the chip select signal CS, since it is an important signal for switching between rank 0 and rank 1, it is desirable to expand the operating margin by improving the waveform quality, for example, the symmetry of the signal. And by doing so, it is desirable to reduce the errors during access to the memory device ME to near zero. Further, regarding the clock signal CK, since it is an important signal for determining the timing of all signals, it is desirable to improve the waveform quality, for example, the symmetry of the signal.

[0058] <Details of the electronic device (embodiment)> Therefore, it is beneficial to use the configuration examples shown in FIGS. 4A and 4B. There are the following two differences between the configuration examples shown in FIGS. 4A and 4B and the configuration examples shown in FIGS. 17A and 17B. As the first difference, in FIGS. 4A and 4B, the plurality of wirings WR1t, WR1b, WR2t, WR2b for propagating the clock signal CK and the chip select signal CS are assigned to the wiring layers in a different way from FIGS. 17A and 17B. As the second difference, in FIGS. 4A and 4B, in each rank, the arrangement interval between two adjacent memory devices ME is determined to be a predetermined value.

[0059] <<Regarding the method of assignment to the wiring layer>> Regarding the first difference, in the configuration example shown in FIG. 4A, the plurality of wirings WR1t from the memory interface MIF1 to the memory devices ME1, ME2 of rank 0 are provided in the wiring layer 15 on the surface side among the plurality of wiring layers, that is, the wiring layer closer to the surface 20 than the back surface 21. On the other hand, the plurality of wirings WR1b from the same memory interface MIF1 to the memory devices ME3, ME4 of rank 1 are provided in the wiring layer 16 on the back surface side among the plurality of wiring layers, that is, the wiring layer closer to the back surface 21 than the surface 20.

[0060] Similarly, in the configuration example shown in FIG. 4B, a plurality of wirings WR2t from the memory interface MIF2 to the memory devices ME5 and ME6 of rank 0 are provided in the wiring layer 15 on the surface side. On the other hand, a plurality of wirings WR2b from the same memory interface MIF2 to the memory devices ME7 and ME8 of rank 1 are provided in the wiring layer 16 on the back side. Thus, in FIGS. 4A and 4B, unlike the cases of FIGS. 17A and 17B, the wiring layer is determined based on the arrangement of the memory devices ME, that is, the rank, rather than the memory interfaces MIF1 and MIF2.

[0061] With such a configuration, in the through-via wirings VAt3 and VAb3 shown in FIG. 4A, the lengths "h1" of the via portions SBt1 and SBt2 for signal propagation are both shorter than the length "h2" of the open stubs SBo1 and SBo2. Similarly, in the through-via wirings VAt6 and VAb6 shown in FIG. 4B, the lengths "h1" of the via portions SBt1 and SBt2 for signal propagation are both shorter than the length "h2" of the open stubs SBo1 and SBo2.

[0062] That is, in FIGS. 4A and 4B, regardless of access to rank 0 and access to rank 1, the via portions SBt1 and SBt2 for signal propagation are configured to be short. In the specification, the plurality of via portions SBt1 and SBt2 for signal propagation are collectively referred to as the via portion SBt for signal propagation. Also, the plurality of open stubs SBo1 and SBo2 are collectively referred to as the open stub SBo.

[0063] The effects obtained by such a configuration are reduction of the load capacitance in the via portion SBt for signal propagation, attenuation of the reflected signal thereby, and improvement of the quality of the transmitted signal. Note that the clock signal CK and the chip select signal CS are propagated only to the memory device ME mounted on either the surface 20 or the back surface 21. For this reason, the plurality of through-via wirings VA that propagate these signals necessarily have open stubs SBo.

[0064] FIG. 6 is an impedance chart showing an example of the impedance characteristics of the via portion SBt and the open stub SBo for signal propagation in FIGS. 4A and 4B. As shown in the impedance chart in FIG. 6, that is, the Smith chart, the impedance of the open stub SBo is infinite when the length is zero, and zero when the length is 1 / 4 of the wavelength λ of the propagation signal. The characteristic points at the intermediate lengths rotate clockwise on the outer circumference of the chart as the length of the open stub SBo, or the frequency of the propagation signal, increases. Along with this, the impedance decreases.

[0065] On the other hand, for example, assuming that the input terminal of the memory device ME is terminated to 50 ohms by ODT (On Die Termination), the impedance of the via portion SBt for signal propagation is 50 ohms when the length is zero. On the other hand, when the via portion SBt for signal propagation has a finite length, it functions as a capacitance in parallel connection and as a kind of short stub due to the input capacitance of the memory device ME and the coupling capacitance with the wiring board PCB. The coupling capacitance increases as the length of the via portion SBt for signal propagation increases. Therefore, the characteristic points of the via portion SBt for signal propagation rotate clockwise on the constant conductance circle from the 50-ohm point as the length of the via portion SBt, or the frequency of the propagation signal, increases. Along with this, the impedance decreases.

[0066] Considering such characteristics, when the length of the open stub SBo is sufficiently shorter than λ / 4, the relationship shown in Equation (1) holds for each unit length of the through-via wiring VA. On the other hand, when the frequency of the propagation signal increases and the length of the open stub SBo approaches λ / 4, the open stub SBo is converted into a short stub and suddenly has a large capacitance. As a result, the relationship shown in Equation (1) is reversed as in Equation (2). Capacitance load of SBo < Capacitance load of SBt …(1) Capacitance load of SBo > Capacitance load of SBt …(2)

[0067] The opposite equations (1) and (2) mean that when the length of the open stub SBo is much shorter than λ / 4, a longer open stub SBo and a shorter via portion SBt for signal propagation can reduce signal reflection and improve signal transmission characteristics. That is, as can be seen from FIG. 6, when the length of the open stub SBo is much shorter than λ / 4, the impedance of the open stub SBo becomes sufficiently higher than that of the via portion SBt for signal propagation. Therefore, the reflection characteristics at the branch point are determined mainly by the capacitance characteristics of the via portion SBt for signal propagation. And by shortening the via portion SBt for signal propagation, the impedance can be made closer to 50 ohms and the reflected signal can be reduced.

[0068] Thus, it is important to configure the length of the open stub SBo to be at least shorter than λ / 4 in consideration of λ / 4. FIG. 7 is a diagram showing an example of the result of calculating how long the length of 1 / 4 of the wavelength λ of the propagation signal becomes according to the Nyquist frequency. Here, the relative permittivity ε r of the dielectric constituting the wiring board PCB is assumed to be 4.0, and the calculation result is shown. In DDR5_SDRAM, the Nyquist frequency is equal to the clock frequency. At 3.6 GHz, which is the highest Nyquist frequency applicable in DDR5_SDRAM, the length of 1 / 4 of the wavelength λ is, for example, about 10.4 mm.

[0069] On the other hand, the thickness of the wiring board PCB is generally about 1.0 - 4.0 mm. Therefore, when the Nyquist frequency is 3.6 GHz, the length of the open stub SBo becomes much shorter than λ / 4, that is, 10.4 mm. Also, if the Nyquist frequency is 8.0 GHz, the length of 1 / 4 of the wavelength λ is 4.7 mm. Even in this case, the length of the open stub SBo is shorter than λ / 4, that is, 4.7 mm. That is, unless an extremely thick wiring board PCB is used, it is considered that equation (1) holds until the signal propagation speed of around 16 Gbps is exceeded.

[0070] Therefore, particularly in the electronic device 10 equipped with a memory device ME such as DDR5_SDRAM, as shown in FIGS. 4A and 4B, it is beneficial to configure the length of the via portion SBt for signal propagation to be short. As a result, the total load capacitance of the through-via wiring VA is minimized, the reflected signal is reduced, and the transmitted signal is increased. As a result, the waveform quality can be improved.

[0071] <<Regarding the arrangement interval of memory devices>> Regarding the second difference, in the configuration example shown in FIG. 4A, the arrangement interval Lm between the memory device ME1 and the memory device ME2 that constitute rank 0 is determined based on the propagation delay time given by Equation (3). That is, the arrangement interval Lm is determined based on the wiring length of the wiring WR1 corresponding to the propagation delay time given by Equation (3). In Equation (3), Tck is the period of the clock signal CK. The arrangement interval Lm between the memory device ME3 and the memory device ME4 that constitute rank 1 is also determined based on the propagation delay time given by Equation (3). Also, in the configuration example shown in FIG. 4B, it is the same as the case of FIG. 4A. Lm = Tck / 2 …(3)

[0072] Furthermore, more desirably, the arrangement interval Lm between the two adjacent memory devices ME is determined based on the propagation delay time given by Equation (4). In Equation (4), τ va is the propagation delay time of the via portion SBt for signal propagation, and is given by Equation (5). In Equation (5), ε r is the relative permittivity of the dielectric that constitutes the wiring board PCB. c0 is the speed of light in a vacuum. Note that the arrangement interval Lm between the two memory devices ME is also the arrangement interval between the two through-via wirings VA that propagate the same signal, for example, the arrangement interval between the through-via wiring VAt2 and the through-via wiring VAt3 in FIG. 4A. Lm = Tck / 2 - τ va …(4) τ va = (length of SBt) × √(ε r ) / c0…(5)

[0073] By applying such an arrangement interval, as will be described below, the reflected signal can be canceled out. However, in practice, it is not easy to completely achieve the cancellation of the reflected signal. Therefore, it is more beneficial to use it in combination with the assignment method to the wiring layer described above. That is, it is more desirable to reduce the reflected signal in advance by the assignment method to the wiring layer described above.

[0074] FIG. 8A is a circuit diagram showing an equivalent configuration example regarding the signal propagation path to rank 0 in FIG. 4A. FIG. 8B is a timing chart conceptually showing the mechanism by which the reflected signal is canceled out in FIG. 8A. In FIG. 8A, a transmission line LN3 corresponding to a wiring WR1 for propagating a chip select signal CS is provided between two memory devices ME1 and ME2. The propagation delay time of the transmission line LN3 is determined here by Equation (3).

[0075] Also, a branch node N1 located at one end of the transmission line LN3 is connected to a receiver RV of the memory device ME1 via a transmission line LN1 corresponding to a via portion SBt for signal propagation. Further, the branch node N1 is connected to an open end via a transmission line LN2 corresponding to an open stub SBo. Similarly, a branch node N2 located at the other end of the transmission line LN3 is connected to a receiver RV of the memory device ME2 via a transmission line LN4 corresponding to a via portion SBt for signal propagation. Further, the branch node N2 is connected to an open end via a transmission line LN5 corresponding to an open stub SBo.

[0076] Figure 8B shows the clock signal CK, the chip select signal CS and the reflected signals CSr1 and CSr2 at the branch node N1, and the chip select signal CS and the reflected signal CSr2 at the branch node N2. The clock signal CK and the chip select signal CS are signals from a control device CTL (not shown). The reflected signal CSr1 is a signal reflected at the node N1 with respect to the chip select signal CS. The reflected signal CSr2 is a signal reflected at the node N2 with respect to the chip select signal CS. In this example, for simplicity of explanation, it is assumed that the phase component of the reflection coefficient at the branch nodes N1 and N2 is zero.

[0077] In Figure 8B, at the branch node N1, a reflected signal CSr1 in phase with the chip select signal CS is generated. On the other hand, the chip select signal CS that has passed through the branch node N1 reaches the branch node N2 after a delay of "Tck / 2". Accordingly, a reflected signal CSr2 similar to that in the case of the branch node N1 is also generated at the branch node N2. The reflected signal CSr2 returns to the branch node N1 after a delay of "Tck / 2".

[0078] Here, when the reflected signal CSr2 reaches the branch node N1, at the branch node N1, a reflected signal CSr1 with a polarity different from the previous one is generated. The reflected signal CSr1 with a different polarity and the reflected signal CSr2 from the branch node N2 cancel each other out at the branch node N1. In practice, the reflection coefficients at the branch nodes N1 and N2 have a phase component, that is, a reactance component. For this reason, the reflected signal mainly occurs during the rising / falling period of the chip select signal CS and has a phase different from that of the chip select signal CS. Even in this case, as long as the magnitudes and phases of the reflection coefficients are the same at the two branch nodes N1 and N2, the same mechanism as in the case of Figure 8B holds.

[0079] Thus, when the relationship of Equation (3) is satisfied, the reflection at the branch node N1 can be canceled for the chip select signal CS operating in the SDR (Single Data Rate) mode. The SDR mode is a mode that operates with the period Tck of the clock signal CK as one data unit. Thereby, in particular, in the memory device ME1 arranged at the branch closer to the control device CTL as described in FIGS. 15A and 15B, the waveform quality can be improved.

[0080] Note that when a signal is reflected by the through via wiring VA, strictly speaking, reflection does not occur with zero delay at the connection point between the wiring and the through via wiring VA, but reflection occurs such that the signal enters the through via wiring VA to some extent and then returns in the original direction. Therefore, more precisely, it is necessary to determine the propagation delay time between the two memory devices ME in consideration of the so-called penetration delay at this time. This penetration delay is reflected in the propagation delay time τ va in Equations (4) and (5).

[0081] Here, the round-trip delay time in the through via wiring VA can be approximated by the general relaxation time given by Equation (6) with e being the base of the natural logarithm. Also, the delay time per unit length in the through via wiring VA is usually longer than the delay time of the wiring, and strictly speaking, it has layout dependency, but is generally 1.3 to 1.4 times the delay time of the wiring. Therefore, when Equation (6) is replaced with the ordinary signal delay, Equation (7) is obtained. (Through via delay)×(1 / e)×2 …(6) (Ordinary signal delay)×(1.3 to 1.4)×(2 / e) =(Ordinary signal delay)×(0.96 to 1.03) …(7)

[0082] In this way, the round-trip delay time in the through-via wiring VA becomes approximately equal to the one-way delay time in a normal signal wiring. By reflecting this result, Equations (4) and (5) are obtained. Note that since the size of the bleeding delay changes when the wiring layer changes, the degree of the cancellation effect of the reflected signal slightly varies. However, as will be described later, the propagation delay time that determines the arrangement interval Lm has a certain tolerance for delay variations, for example, about 14%. Therefore, no particularly big problem occurs. Furthermore, because of having such a tolerance, the arrangement interval Lm given by Equation (3) may be applied instead of Equation (4).

[0083] <<Regarding the clock signal>> Regarding the clock signal CK as described in FIG. 16, by applying the arrangement interval Lm of the memory device ME described above, or in addition to this, by applying the above-described assignment method to the wiring layer, the waveform quality, for example, the symmetry of the waveform can be improved. Specifically, when Equation (3) or Equation (4) holds, the round-trip delay time between the memory devices ME in the clock signal CK becomes equal to the period of the clock signal CK. Therefore, for example, in the memory devices ME1 and ME2 that constitute Rank 0 shown in FIG. 4A, reflected signals of almost equal amounts are always synthesized at a constant timing.

[0084] As a result, a clock signal CK with a symmetric waveform shape can be input to the memory devices ME1 and ME2 to which the fly-by method is applied. Furthermore, for example, regarding the memory devices ME1 and ME3 on the front / back surfaces to which Clamshell is applied in FIG. 4A, by applying the above-described assignment method to the wiring layer, the reflection coefficients at the branch nodes corresponding to each memory device ME can be equalized. Therefore, a clock signal CK with almost the same waveform shape can be input to the memory devices ME1 and ME3.

[0085] In this regard, for example, in FIG. 4A, the length of the via portion SBt1 for signal propagation that propagates the clock signal CK0 and the length of the via portion SBt2 for signal propagation that propagates the clock signal CK1 may be equal. The same applies to the chip select signal CS. Therefore, the length of the via portion SBt1 for signal propagation that propagates the chip select signal CS0 and the length of the via portion SBt2 for signal propagation that propagates the chip select signal CS1 may be equal. That is, in the wiring board PCB, the wirings WR1t and WR1b that propagate the same type of signal may be symmetrically arranged with respect to the intermediate wiring layer.

[0086] <<Regarding the command address signal>> As shown in FIG. 5 and the like, with respect to the wiring WR1tb that propagates the command address signal CA, it is commonly connected to the memory devices ME1 and ME3 on the front / back surfaces. Therefore, the effect of reducing the capacitance of the through-via wiring VA described above, that is, the effect associated with the method of allocating to the wiring layer cannot be obtained. However, the effect of canceling the reflected signal described above, that is, the effect associated with the arrangement interval Lm of the memory devices ME can be obtained.

[0087] For example, in DDR5_SDRAM, a 2N mode is supported for the command address signal CA. The 2N mode is a mode of operation with two cycles “2×Tck” of the clock signal CK as one unit, as shown in FIG. 8B. In the 2N mode, the effect of canceling the reflected signal is slightly different from the case of the chip select signal CSm operating in the SDR mode. That is, in the 2N mode, each time the command address signal CA makes two round trips between two memory devices ME, a relationship is established in which the reflected signal becomes out of phase.

[0088] In the example shown in FIG. 8B, according to the command address signal CA, the reflected signal CSr2 generated in the first cycle of the clock signal CK and the reflected signal CSr1 generated in the third cycle of the clock signal are canceled out. As a result, as long as the reflection continues, every time the command address signal CA makes an even number of round trips, such as 2 round trips, 4 round trips, 6 round trips, etc., the reflected signals with opposite phases are canceled out with each other. Since cancellation does not occur in odd-numbered round trips, the cancellation effect of the reflected signal is approximately half that in the case of the chip select signal CS.

[0089] However, compared with the chip select signal CS and the clock signal CK, the command address signal CA has a relatively large tolerance for errors. Furthermore, since the use of the 2N mode itself expands the timing margin and the like, errors are less likely to occur. Therefore, regarding the waveform quality of the command address signal CA, particularly by using the 2N mode, the necessary quality can be sufficiently ensured.

[0090] <Simulation Results> FIG. 9 is a waveform diagram showing an example of a simulation result in which the input waveform of the chip select signal CS is observed for the memory device ME1 on the side closer to the control device CTL in FIG. 4A. Here, assuming that the signal propagation speed is 5600 Mbps, the arrangement interval Lm between the two memory devices ME1 and ME2 is determined using Equation (4), and this is defined as the optimum value. Then, while maintaining the arrangement interval Lm between the memory devices ME1 and ME2, the signal propagation speed is changed to 4800 Mbps and 3200 Mbps.

[0091] Accordingly, when the signal propagation speed is 4800 Mbps, the arrangement interval Lm between the memory devices ME1 and ME2 becomes approximately 14.3% shorter than the optimum value. Similarly, when the signal propagation speed is 3200 Mbps, the arrangement interval Lm between the memory devices ME1 and ME2 becomes approximately 42.9% shorter than the optimum value.

[0092] In Fig. 9, at 5600 Mbps and 4800 Mbps, the reflected signal is almost removed, and a good waveform shape of the chip select signal CS, that is, an eye pattern, is obtained. On the other hand, at 3200 Mbps, the reflected signal appears prominently without being canceled out. However, by using the above-described wiring layer allocation method, the magnitude of the reflected signal itself has been reduced. From this simulation result, it can be seen that a sufficient effect can be obtained even when the arrangement interval Lm between the two memory devices ME1 and ME2 is deviated by about 14%. Also, when the optimum value of the arrangement interval Lm is determined on the premise of a certain signal propagation speed in this way, the effect may become smaller when the signal propagation speed decreases.

[0093] Fig. 10 is a waveform diagram showing an example of a simulation result of observing the input waveform of the clock signal CK for the memory device ME1 on the side closer to the control device CTL and the memory device ME2 on the farther side in Fig. 4A. Here, the evaluation index is the symmetry of the waveform shape as also described in Fig. 16.

[0094] When the signal propagation speed is 5600 Mbps, a sufficiently symmetric waveform shape is obtained in the relationship between the clock signal CK to the memory device ME1 and the clock signal CK to the memory device ME2. That is, the waveform shapes of the negative clock signal CK(c) and the positive clock signal CK(t) to the memory device ME1 are respectively equivalent to the waveform shapes of the positive clock signal CK(t) and the negative clock signal CK(c) to the memory device ME2.

[0095] Also, when the signal propagation speed is 4800 Mbps, an almost symmetric waveform shape is obtained. On the other hand, when the signal propagation speed is 3200 Mbps, both waveform shapes are asymmetric. From this simulation result, it can be seen that the tolerance for the arrangement interval Lm between the two memory devices ME is about 14%, similar to the case of the chip select signal CS.

[0096] <Detailed Cross-sectional Configuration of the Electronic Device (Embodiment)> FIG. 11A is a cross-sectional view showing a more detailed configuration example between A-A' in FIG. 2. In FIG. 11A, as described in FIG. 4A, the wiring WR1 that propagates the chip select signal CS0 to the surface 20 side and the wiring WR1 that propagates the clock signal CK0 to the surface 20 side are provided in the surface-side wiring layer 15. On the other hand, the wiring WR1 that propagates the chip select signal CS1 to the back surface 21 side and the wiring WR1 that propagates the clock signal CK1 to the back surface 21 side are provided in the back surface-side wiring layer 16. Further, the external terminal PNc2 of the memory interface MIF2 is arranged inside the control device CTL more than the external terminal PNc1 of the memory interface MIF1.

[0097] Also, here, as an example, the length of the via portion SBt1k for signal propagation that propagates the clock signal CK0 to the surface 20 side and the length of the via portion SBt2k for signal propagation that propagates the clock signal CK1 to the back surface 21 side are both the same value "h1k". Similarly, the length of the via portion SBt1s for signal propagation that propagates the chip select signal CS0 to the surface 20 side and the length of the via portion SBt2s for signal propagation that propagates the chip select signal CS1 to the back surface 21 side are also both the same value "h1s".

[0098] The wiring WR1 that propagates the command address signal CA[i:0] is wire-or connected to all the memory devices ME1-ME4 mounted on the surface 20 and the back surface 21. Here, one example of the wiring WR1 is shown, but in detail, "i + 1" are provided. The "i + 1" wirings WR1 can be appropriately distributed and arranged in a plurality of wiring layers.

[0099] Furthermore, in this example, eight wirings WR1 that propagate the 8-bit data signal DQ[7:0] between one of the two memory devices ME1 and ME3 and eight wirings WR1 that propagate the 8-bit data signal DQ[15:8] between one of the two memory devices ME2 and ME4 are provided. The total of 16 wirings WR1 that propagate the data signal DQ[15:0] can also be appropriately distributed and arranged in a plurality of wiring layers.

[0100] FIG. 11B is a cross-sectional view showing a more detailed configuration example between B-B' in FIG. 2. In FIG. 11B, as described in FIG. 4B, the wiring WR2 that propagates the chip select signal CS0 to the surface 20 side and the wiring WR2 that propagates the clock signal CK0 to the surface 20 side are provided in the wiring layer 15 on the surface side. On the other hand, the wiring WR2 that propagates the chip select signal CS1 to the back surface 21 side and the wiring WR2 that propagates the clock signal CK1 to the back surface 21 side are provided in the wiring layer 16 on the back surface side. Here, regarding the length of the via portion for signal propagation, it is the same as in the case of FIG. 11A.

[0101] Also, similar to the case of FIG. 11A, the “i + 1” wirings WR2 that propagate the command address signal CA[i:0] can also be appropriately distributed and arranged in a plurality of wiring layers. Further, in this example, eight wirings WR2 that propagate the 8-bit data signal DQ[23:16] between one of the two memory devices ME5 and ME7, and eight wirings WR2 that propagate the 8-bit data signal DQ[31:24] between one of the two memory devices ME6 and ME8 are provided. Regarding the total 16 wirings WR2 that propagate the data signal DQ[31:16], they can also be appropriately distributed and arranged in a plurality of wiring layers.

[0102] <Regarding a modification> FIG. 12 is a cross-sectional view showing a configuration example that expands the configuration shown in FIG. 4A. In FIG. 12, on the surface 20 of the wiring board PCB, an even number, here four memory devices ME including the memory devices ME1 and ME2 shown in FIG. 4A are mounted. The even number of memory devices ME constitute rank 0 and are accessed using the common clock signal CK0 and the common chip select signal CS0.

[0103] Similarly, on the back surface 21 of the wiring board PCB, an even number, here four memory devices ME including the memory devices ME3 and ME4 shown in FIG. 4A are mounted. The even number of memory devices ME constitute rank 1 and are accessed using the common clock signal CK1 and the common chip select signal CS1.

[0104] Here, the arrangement intervals Lm between two adjacent memory devices ME among the even number of memory devices ME mounted on the front surface 20 are both determined based on the propagation delay time given by Equation (3) or Equation (4). Similarly, the arrangement intervals Lm between two adjacent memory devices ME among the even number of memory devices ME mounted on the back surface 21 are also both determined based on the propagation delay time given by Equation (3) or Equation (4).

[0105] When using the fly-by method in this way, the number of branches can be increased to two or more. In this case, as shown in FIG. 12, adjacent memory devices ME may be arranged at equal intervals. However, the number of memory devices ME mounted on each surface needs to be an even number. If an odd number of memory devices ME are mounted, a combination in which reflected signals reinforce each other may occur. Note that the bit width of the data signal DQ in the memory interfaces MIF1 and MIF2 is usually extended in units of 2 n units. Therefore, also from this perspective, the number of memory devices ME mounted on each surface can usually be an even number.

[0106] <Principal Effects of the First Embodiment> As described above, in the first embodiment, mainly, the method of allocating the wiring layers for the wiring that propagates the chip select signal and the clock signal, and the arrangement interval between adjacent memory devices are determined. And in the electronic device according to the first embodiment, at least one, preferably both, of the two technical elements are applied. Thereby, typically, the waveform quality of the chip select signal and the clock signal can be improved. Furthermore, the waveform quality can be improved without providing a resistance element as shown in Patent Document 1. As a result, miniaturization of the electronic device can be achieved.

[0107] (Second Embodiment) <Schematic Cross-Sectional Configuration of Electronic Device> FIG. 13 is a cross-sectional view showing a schematic configuration example regarding a clock signal, a chip select signal, and a command address signal between A and A' in FIG. 2 in the electronic device according to the second embodiment. FIG. 13 shows the same configuration as that shown in FIGS. 4A and 5. However, in FIG. 13, different from the cases of FIGS. 4A and 5, the wiring length LLc between an external terminal PNc that outputs a predetermined control signal from a control device CTL and through vias VAt and VAtb2 that propagate the predetermined control signal to memory devices ME1 and ME3 on the side closer to the control device CTL is set to a predetermined value.

[0108] Specifically, the wiring length LLc is determined based on the propagation delay time given by Equation (8). That is, the wiring length LLc represents the wiring lengths of wirings WR1t, WR1b, and WR1tb corresponding to the propagation delay time. In Equation (8), Tck is the period of the clock signal CK. n and m are non-negative integers. τ va is the propagation delay time of the via portion SBt for signal propagation described in Equation (5). However, similar to the case of the relationship between Equations (3) and (4) described above, τ in Equation (8) va may be zero. LLc = (Tck / 2)(n + m / 6) - τ va …(8)

[0109] FIG. 14 is a table showing combinations of n and m to be avoided in the wiring length LLc between the control device CTL and the memory device ME1 shown in FIG. 13. Also, in FIG. 14, priorities are set in descending order of the influence on waveform quality. In FIG. 14, regarding the command address signal CA, the case of operating in 2N mode is assumed, and the limitations in 2N mode are shown. If the command address signal CA operates in SDR mode, it may follow the rules of the chip select signal CS.

[0110] The influence of signal reflection can occur not only between adjacent memory devices ME described in the first embodiment in more detail, but also between the control device CTL and the memory device ME. That is, since the through-via wirings VAt1 and VAtb1 also exist on the control device CTL side, the signal reflection from the through-via wirings VAt1 and VAtb1 affects the cancellation effect of the reflected signal described in the first embodiment.

[0111] At this time, the reflected signals from the through-via wirings VAt1 and VAtb1 on the control device CTL side are generated when the remaining signals that were not canceled between the memory devices ME reach. Therefore, the influence on signals other than the clock signal CK is small. Reflecting this, in FIG. 14, the priority of signals other than the clock signal CK is set low.

[0112] Here, regarding the clock signal CK, even if there is no branch to the memory device ME, the wiring length itself, more precisely, the remainder obtained by dividing the delay by half of the clock period can affect the waveform quality. Therefore, the inventors investigated the influence of the wiring delay by simulation with a resolution of further 1 / 6 of the half period “Tck / 2” of the clock signal CK. As a result, as shown in FIG. 14, when m = 4, a tendency for the waveform quality to deteriorate, specifically a tendency for high-frequency components to decrease, was observed.

[0113] For example, in Equation (8), “m = 2” and “m = 4” are timings that are symmetric with respect to “3 / 6” corresponding to the center timing of the clock signal CK, meaning equivalent conditions. However, for example, in an actual clock driver circuit of a memory interface, the rising waveform and the falling waveform of the clock signal CK can be asymmetric, so either “m = 2” or “m = 4” becomes a condition to be avoided. That is, in the clock driver circuit used in this simulation, it just happened to be “m = 4”.

[0114] By applying the arrangement interval Lm between the two memory devices ME described in the first embodiment, a symmetric waveform shape was obtained for the clock signal CK observed at the input terminals of the two memory devices ME. Further, regarding the chip select signal CS operating in the SDR mode, as a result of waveform observation by simulation, as shown in FIG. 14, when "n = 0" and "m = 3" where the wiring length LLc is short, there was only a slight deterioration in waveform quality.

[0115] On the other hand, regarding the command address signal CA, since it operates in the 2N mode, the situation is slightly different. As described above, in the 2N mode, the reflected signal is canceled every time it makes two round trips between the two memory devices ME. Here, first, assume the case where the wiring length LLc shown in FIG. 13 is twice the arrangement interval Lm between the two memory devices ME, that is, in Equation (8), "n = 2" and "m = 0".

[0116] When using this wiring length LLc, in the command address signal CA as well, the cancellation condition for the reflected signal is satisfied, similar to the case of the chip select signal CS. That is, between the control device CTL and the memory device ME1 on the closer side, cancellation of the reflected signal occurs additionally in units of one round trip of the command address signal CA. As a result, the waveform quality is somewhat improved. Since the same phenomenon occurs even when the signal is shifted by one cycle unit, the cancellation condition for the reflected signal is satisfied when "n = even" and "m = 0". That is, "n = even" and "m = 0" are the optimal conditions.

[0117] Next, regarding the command address signal CA, assume a case where the wiring length LLc shown in FIG. 13 is equal to the arrangement interval Lm between the two memory devices ME, that is, in Equation (8), the case of "n = 1" and "m = 0". When using the wiring length LLc, the cancellation condition of the reflected signal is satisfied between the control device CTL and the memory device ME2 on the far side. In this case, since the reflected signal propagated from the memory device ME2 on the far side to the memory device ME1 on the near side decreases, the cancellation effect of the reflected signal becomes insufficient in the memory device ME1 on the near side, and the waveform quality may deteriorate. The same phenomenon occurs even when the signal is shifted by one cycle unit.

[0118] As described above, the conditions to be avoided regarding the command address signal CA are, as shown in FIG. 14, "n = odd" and "m = 0". Further, similar to the case of the chip select signal CS, as a result of performing waveform observation by simulation on the command address signal CA, a decrease in the waveform shape was observed at a point shifted by 1 / 2 of the arrangement interval Lm from the optimal conditions of "n = even" and "m = 0". Therefore, the additional conditions to be avoided are, as shown in FIG. 14, "n = even" and "m = 3".

[0119] <Principal Effects of the Second Embodiment> As described above, by using the electronic device according to the second embodiment, the same effects as those described in the first embodiment can be obtained. In addition to this, in the second embodiment, a limit is provided on the wiring length between the control device and the memory device on the nearer side. As a result, it is possible to suppress a situation where the cancellation effect of the reflected signal between adjacent memory devices is hindered. As a result, the waveform quality can be further improved. Furthermore, by providing a limit on the wiring length of the clock signal CK that is not directly related to the cancellation effect of the reflected signal, the waveform quality of the signal can be further improved.

[0120] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Reference Numerals

[0121] 10 Electronic device 15 Wiring layer on the front surface 16 Wiring layer on the back surface 20 Front surface 21 Back surface CTL Control device LLc Wiring length Lm Arrangement interval ME Memory device MIF1, MIF2 Memory interface PCB Wiring board SBo Open stub SBt Via portion for signal propagation VA Through-via wiring WR Wiring

Claims

1. A wiring board having a first surface and a second surface opposite to the first surface, and including a plurality of wiring layers and a plurality of wirings, A first memory device mounted on the first surface, A second memory device mounted on the first surface, A third memory device mounted on the second surface, A fourth memory device mounted on the second surface, A control device mounted on the first surface, accessing each of the first memory device and the second memory device using a common first clock signal and a common first chip select signal, and accessing each of the third memory device and the fourth memory device using a common second clock signal and a common second chip select signal, Comprising, The plurality of wirings, A plurality of first wirings respectively propagating the first clock signal and the first chip select signal, A plurality of second wirings respectively propagating the second clock signal and the second chip select signal, Having, The plurality of first wirings are provided in a wiring layer closer to the first surface than the second surface among the plurality of wiring layers, The plurality of second wirings are provided in a wiring layer closer to the second surface than the first surface among the plurality of wiring layers, An electronic device.

2. In the electronic device according to claim 1, When the period of the clock signal is "Tck", and the arrangement intervals between the first memory device and the second memory device, and between the third memory device and the fourth memory device are both "Lm", "Lm" is determined based on the propagation delay time of "Tck / 2", An electronic device.

3. In the electronic device according to claim 1, The wiring board includes a plurality of through-via wirings provided so as to penetrate the plurality of wiring layers between the first surface and the second surface, The plurality of through-via wirings, A first through-via wiring for connecting the first wiring to the first memory device or the second memory device, A second through-via wiring for connecting the second wiring to the third memory device or the fourth memory device, Having, The first through-via wiring has a first via portion from the connection point with the first wiring to the first surface and a first open stub from the connection point with the first wiring to the second surface. The second through-via has a second via portion from the connection point with the second wiring to the second surface and a second open stub from the connection point with the second wiring to the first surface. The length of the first via portion is shorter than the length of the first open stub. The length of the second via portion is shorter than the length of the second open stub. An electronic device.

4. In the electronic device according to claim 3, Let the period of the clock signal be "Tck", and let the arrangement interval between the first memory device and the second memory device, and the arrangement interval between the third memory device and the fourth memory device both be "Lm", and let the propagation delay time of the first via portion and the propagation delay time of the second via portion both be "τ ｖａ ” When "Lm" is determined based on the propagation delay time of "Tck / 2 - τ" ｖａ ". An electronic device.

5. In the electronic device according to claim 3, When the wavelength of the propagation signal propagating through the first wiring and the second wiring is "λ", the length of the first open stub and the length of the second open stub are both shorter than "λ / 4". An electronic device.

6. In the electronic device according to claim 3, when the first through-via wiring propagates the first clock signal and the second through-via wiring propagates the second clock signal, the lengths of the first via portion and the second via portion are equal; when the first through-via propagates the first chip select signal and the second through-via propagates the second chip select signal, the lengths of the first via portion and the second via portion are equal. An electronic device.

7. In the electronic device according to claim 2, the control device accesses the first memory device, the second memory device, the third memory device, and the fourth memory device using a common command address signal, and the command address signal is set to a 2N mode which operates with two cycles of the clock signal as one unit. An electronic device.

8. In the electronic device according to claim 7, the wiring substrate includes a plurality of through-via wirings provided to penetrate the plurality of wiring layers between the first surface and the second surface, and the plurality of through-via wirings have a wiring for propagating the command address signal and a third through-via wiring for connecting the first memory device and the third memory device. Let the period of the clock signal be "Tck", the length of the wiring between the external terminal that outputs the command address signal from the control device and the third through-wire be "LLc", and when n is an even number, "LLc" is defined as the length based on the propagation delay time of "(Tck / 2)×n". An electronic device.

9. In the electronic device according to claim 2, On the first surface, an even number of memory devices that are accessed using the common first clock signal and the common first chip select signal, including the first memory device and the second memory device, are mounted. On the second surface, an even number of memory devices that are accessed using the common second clock signal and the common second chip select signal, including the third memory device and the fourth memory device, are mounted. When the arrangement interval between two adjacent memory devices among the even number of memory devices mounted on the first surface is "Lm", and the arrangement interval between two adjacent memory devices among the even number of memory devices mounted on the second surface is also "Lm", "Lm" is defined based on the propagation delay time of "Tck / 2". An electronic device.

10. In the electronic device according to claim 1, The fifth memory device and the sixth memory device mounted on the first surface, The seventh memory device and the eighth memory device mounted on the second surface, And further include, The control device is A first memory interface that accesses each of the first memory device and the second memory device using the common first clock signal and the common first chip select signal, and accesses each of the third memory device and the fourth memory device using the common second clock signal and the common second chip select signal; A second memory interface that accesses each of the fifth memory device and the sixth memory device using the common third clock signal and the common third chip select signal, and accesses each of the seventh memory device and the eighth memory device using the common fourth clock signal and the common fourth chip select signal; And has The external terminals of the second memory interface are arranged inside the control device closer to the control device than the external terminals of the first memory interface. Electronic device.

11. A wiring board having a first surface and a second surface opposite to the first surface, and including a plurality of wiring layers and a plurality of wirings, A first memory device mounted on the first surface, A second memory device mounted on the first surface, A control device mounted on the first surface or the second surface, and accessing each of the first memory device and the second memory device using a common clock signal and a common chip select signal, Comprising When the period of the clock signal is "Tck" and the arrangement interval between the first memory device and the second memory device is "Lm", "Lm" is determined based on the propagation delay time of "Tck / 2". Electronic device.

12. In the electronic device according to claim 11, The wiring board, A plurality of first wirings that are part of the plurality of wirings and propagate the clock signal and the chip select signal respectively, A first through-via wiring provided to penetrate the plurality of wiring layers between the first surface and the second surface, and connecting the first wiring to the first memory device or the second memory device, Including The first through-via wiring has a first via portion from the connection point with the first wiring to the first surface and a first open stub from the connection point with the first wiring to the second surface. Electronic device.

13. In the electronic device according to claim 12, When the propagation delay time of the first via portion is "τ ｖａ ", "Lm" is determined based on the propagation delay time of "Tck / 2 - τ" ｖａ ". Electronic device.

14. In the electronic device according to claim 12, The length of the first via portion is shorter than the length of the first open stub. Electronic device.

15. In the electronic device according to claim 14, When the wavelength of the propagation signal propagating through the first wiring is "λ", The length of the first open stub is shorter than "λ / 4". Electronic device.

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