Display panel and display device including the same

Abstract

To provide a display panel and a display device including the same.SOLUTION: Disclosed are a display panel including a plurality of pixels and a gate line and data line connected to the plurality of pixels, and a display device including the display panel. The plurality of pixels include: a 1-1th subpixel and a 1-2th subpixel of a first color; a 2-1th subpixel and a 2-2th subpixel of a second color; and a 3-1th subpixel and a 3-2th subpixel of a third color. The 2-1th subpixel and the 2-2th subpixel respectively include a luminous element and a compensation circuit, and the compensation circuit of the 2-1th subpixel and the compensation circuit of the 2-2th subpixel are connected to one data line.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a display panel and a display device including the same.

Background Art

[0002] An organic light-emitting display device emits light from organic light-emitting diodes (OLEDs) arranged for each pixel in accordance with an input video signal to reproduce an image. The organic light-emitting display device has a fast response speed of pixels, high luminous efficiency, luminance, and viewing angle, and can express a black gradation as complete black, so it is excellent in contrast ratio and color reproducibility. Such an organic light-emitting display device does not require a backlight unit.

[0003] Recently, a micro display device that uses an LED (Light Emitting Diode), which is an inorganic light-emitting element, fabricated in a micro size of about 100 μm or less as a light-emitting element of a pixel has been attracting attention as a next-generation display device. Since an LED is made of an inorganic substance, a separate encapsulation layer for protecting the organic matter from moisture is not required, and it is more reliable and has a longer lifespan than an OLED. In addition, an LED has a fast lighting speed, excellent luminous efficiency, and impact resistance.

[0004] In such a micro display device, since two LEDs are arranged in parallel in one sub-pixel, if a short circuit failure occurs in any one of them and it becomes a dark spot, there is a problem that the remaining LEDs also become dark spots.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention provides a display panel and a display device including the same, in which, even if any one of a plurality of light-emitting elements in a sub-pixel becomes a dark spot, the remaining light-emitting elements can emit light.

[0006] Also provided are a display panel and a display device including the same, which can repair a light-emitting element.

[0007] The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0008] A display panel according to one feature of the present invention includes a plurality of pixels, a gate line, and a data line connected to the plurality of pixels. The plurality of pixels include a first-1 sub-pixel and a first-2 sub-pixel of a first color; a second-1 sub-pixel and a second-2 sub-pixel of a second color; and a third-1 sub-pixel and a third-2 sub-pixel of a third color. The second-1 sub-pixel and the second-2 sub-pixel each include a light-emitting element and a compensation circuit, and the compensation circuit of the second-1 sub-pixel and the compensation circuit of the second-2 sub-pixel are connected to one data line.

[0009] According to the present invention, even if any one of the light-emitting elements of the plurality of sub-pixels is darkened, the remaining light-emitting elements can emit light. Therefore, the number of dark light-emitting elements in the display device can be reduced. Also, low-power driving becomes possible.

[0010] Also, by using a pixel structure that is easy to improve dark electricity, a display panel advantageous for process optimization, high efficiency, high brightness, and long life can be realized.

[0011] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the claims.

Brief Description of the Drawings

[0012]

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BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Advantages and features of the invention disclosed in this specification, and methods for achieving them, will become clear by referring to the embodiments described in detail hereinafter together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but is embodied in various different forms, and the embodiments are merely provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention, and the present invention is only defined by the scope of the claims.

[0014] In explaining the present invention, when it is determined that a specific explanation of related known technologies will obscure the gist of the present invention, the detailed explanation thereof will be omitted.

[0015] When terms such as "comprise", "include", "contain", "have", "consist of", etc. mentioned in this specification are used, as long as "only" is not used, other parts can be added. When a component is expressed in the singular, it can be interpreted as plural unless there are special explicit descriptions.

[0016] When the positional relationship and the mutual connection relationship between two components are described, such as "on", "above", "below", "beside", "connect or couple", "crossing or intersecting", etc., unless there is a mention such as "immediately" or "directly", one or more other components may be interposed between those components.

[0017] When the temporal sequence relationship is described, such as "after", "subsequent to", "next", "before", etc., unless "immediately" or "directly" is used, it may not be continuous on the time axis.

[0018] The first, second, etc. may be used to distinguish components, but the functions and structures of these components are not limited by the ordinal numbers attached to the components or the names of the components.

[0019] The following embodiments can be partially or entirely combined or combined with each other, and various linkages and drives are technically possible. Each embodiment can also be implemented independently of each other or implemented together with a correlation relationship.

[0020] In an embodiment of the present invention, the pixel and the display panel driving circuit include a transistor. The transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, the carrier flows out from the source. The drain is an electrode through which the carrier exits the transistor to the outside. In the transistor, the flow of the carrier flows from the source to the drain. In the case of an n-channel transistor, since the carrier is an electron, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In the n-channel transistor, the direction of the current flows from the drain to the source side. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since holes flow from the source to the drain side in the p-channel transistor, the current flows from the source to the drain side. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first and second electrodes.

[0021] The gate signal can swing between a gate on voltage and a gate off voltage. The transistor is turned on in response to the gate on voltage and turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate on voltage can be a gate high voltage VGH, and the gate off voltage can be a gate low voltage VGL. In the case of a p-channel transistor, the gate on voltage can be a gate low voltage VGL, and the gate off voltage can be a gate high voltage VGH.

[0022] The "line" referred to in the embodiments of the present invention can be interpreted as a wiring to which a signal or a voltage is applied.

[0023] The terms (including technical and scientific terms) used in the embodiments of the present invention can be interpreted as meanings generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless specifically defined and described otherwise. Terms commonly used like those defined in a dictionary can have their meanings interpreted in consideration of the context of the related art.

[0024] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

[0025] Referring to FIG. 1, the display device 100 includes a display panel PN in which a plurality of pixels are arranged in a display area AA, and a display panel driving circuit that drives the pixels.

[0026] The display panel PN can be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction, but is not limited thereto. The pixel includes a plurality of sub-pixels SP having different colors. In the display panel PN, the display area AA where the input video is displayed can be a screen visible from the front of the display panel PN.

[0027] The display panel driving circuit includes a data driving unit DD, a gate driving unit GD, and a timing controller TC that controls the gate driving unit GD and the data driving unit DD.

[0028] An input video is displayed on a sub-pixel SP arranged in a display area AA of a display panel PN. Each of the sub-pixels SP includes a light-emitting element and a pixel circuit that drives the light-emitting element. The light-emitting element can be an LED (Light-emitting Diode) or a Micro LED (Micro Light-emitting Diode).

[0029] On the display panel PN, a plurality of gate lines SL and a plurality of data lines DL are arranged so as to intersect each other. Each of the sub-pixels SP is connected to the gate line SL and the data line DL. A power supply wiring omitted in FIG. 1 can be connected to each of the sub-pixels SP. In the display panel PN, a non-display area NA can be arranged outside the display area AA.

[0030] The gate driving unit GD supplies a gate signal to the gate line SL in response to a gate control signal provided from the timing controller TC. As shown in FIG. 1, the gate driving unit GD can be arranged at least in the non-display area NA of the display panel PN or within the display area AA.

[0031] The data driving unit DD converts video data received from the timing controller TC into a gamma compensation voltage and outputs a data voltage in response to a data control signal provided from the timing controller TC. The data voltage output from the data driving unit DD is supplied to the data line DL.

[0032] The timing controller TC aligns the video data input from the outside and supplies it to the data driver unit DD. The timing controller TC can generate a gate control signal and a data control signal based on a timing signal synchronized with the input video signal, such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. The timing controller TC supplies the gate control signal to the gate driver unit GD and the data control signal to the data driver unit DD to control the operation timing of the gate driver unit GD and the data driver unit DD.

[0033] In the non-display area NA, link wirings and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA can be arranged. In the non-display area NA, one or more of a gate driver IC in which the circuit of the gate driver unit GD is integrated and a data driver IC in which the circuit of the data driver unit DD is integrated can be arranged. The non-display area NA can include the back surface of the display panel PN, that is, the back surface without the sub-pixels SP. The non-display area NA can be minimized so as not to be visible when an image is displayed on the display panel PN.

[0034] The display panel driving circuit can be connected to the display panel PN in various ways to drive the pixels. For example, the gate driver unit GD can be arranged in the non-display area NA in the GIP (Gate In Panel) method, or can be arranged between the sub-pixels SP in the display area AA in the GIA (Gate In Active area) method. The data driver unit DD and the timing controller TC are formed on a separate flexible film and PCB, and the terminals of the flexible film are bonded to the pad electrodes formed in the non-display area NA of the display panel PN to electrically connect the data driver unit DD and the timing controller TC to the display panel PN. The flexible film bonded to the display panel PN can be connected to a PCB (Printed circuit board) on which circuit elements are mounted and wirings are formed.

[0035] Side wiring for connecting the signal wiring on the front surface of the display panel PN to the pad electrodes on the back surface of the display panel PN can be formed on the outer side surface of the display panel PN. The electrical connection method between the front and back surfaces of the display panel PN through the side wiring can minimize the non-display area NA visible from the front surface of the display panel PN. In FIG. 2, "SRL" indicates the side wiring. When the gate driving unit GD, the data driving unit DD, and the timing controller TC are electrically connected to the display panel PN by the above-described method, a bezel-less screen can be realized substantially on the display panel PN.

[0036] Referring to FIG. 2, a plurality of pad electrodes for transmitting various signals to the sub-pixels SP are arranged in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 for transmitting a signal to the sub-pixel SP may be arranged in the non-display area NA arranged on the front surface of the display panel PN. A second pad electrode PAD2 electrically connected to circuit components such as a flexible film and a PCB is arranged in the non-display area NA arranged on the back surface of the display panel PN. The non-display area NA arranged on the front outer periphery of the display panel PN where an image is displayed is arranged only in the pad area where the first pad electrode PAD1 is arranged, and its size can be minimized.

[0037] Various signal wirings connected to the sub-pixel SP, such as a gate line SL and a data line DL, etc., can extend into the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0038] The display panel PN may include side wirings SRL disposed on the outer side surfaces of the display panel PN. The side wirings SRL can electrically connect a first pad electrode PAD1 disposed on the front outer contour of the display panel PN across the side surface of the display panel PN and a second pad electrode PAD2 disposed on the back outer contour of the display panel PN. A signal output from a circuit component disposed on the back surface of the display panel PN can be transmitted to the sub-pixels SP and the gate driving unit GD within the display area AA through the second pad electrode PAD2, the side wiring SRL, and the first pad electrode PAD1. Accordingly, a signal transmission path that crosses the front, side, and back surfaces can be formed on the outer contour of the display panel PN, and the area of the non-display area NA on the front surface of the display panel PN can be minimized.

[0039] A plurality of display modules may be combined on a plane to be implemented as a large-screen tiling display device. Each of the display modules may be implemented as one display device, and a combination of a plurality of display modules may be implemented as a large-screen tiling display device. Each of the display modules includes a single display panel PN, a driving circuit of the display panel PN, circuit components coupled to the back surface of the display panel PN, and a module cover member.

[0040] Referring to FIG. 3, the large-screen tiling display device TD includes a plurality of display modules disposed on the XY plane. Each of the display modules includes a display panel PN that reproduces an input video. When the non-display area NA is minimized at the front outer contour of each of the display panels PN, a large-screen video without a visible seam can be reproduced between adjacent display panels PN.

[0041] The outermost pixel PX in one display panel PN and the outermost pixel PX of another display panel PN adjacent to the display panel PN are spaced apart by a distance D1 that is substantially the same as the distance D2 between adjacent pixels PX within the display area AA of the display panel PN, so that the display panel PN can be assembled flat. As a result, throughout the display area of the large screen of adjacent tiling display devices TD, the distances D1 and D2 between pixels PX are the same, and no seam area is visible.

[0042] In the tiling display device TD, a plurality of display modules can share one timing controller TC. The host system is connected to a plurality of timing controllers TC to transmit a video signal reproduced on all display panels PN that make up the large screen of the tiling display device TD to the timing controller TC and synchronize the timing controller TC.

[0043] FIG. 4 is a plan view schematically showing the planar structure of a display panel according to an embodiment of the present invention.

[0044] Referring to FIG. 4, the display panel PN includes a pixel array and a substrate SUBS on which the circuits of the gate driving unit GD are arranged. The display panel PN can be a panel having a rectangular structure with a length in the row direction (X-axis), a width in the column direction (Y-axis), and a thickness in the thickness direction (Z-axis), but is not limited thereto.

[0045] The substrate SUBS can be an insulating substrate that supports components arranged on the upper part of the display device. The substrate SUBS can have a structure in which a plurality of substrates are laminated. The substrate SUBS can be made of glass, a polymer resin, or a plastic substrate.

[0046] On one side (or the front side) of the substrate SUBS, the display area AA may include a plurality of pixel areas UPA, a plurality of gate driving areas GA, and a plurality of pad areas PA1, PA2. One or more pixels PX may be arranged in each of the pixel areas UPA. The pixel areas UPA may be arranged along a plurality of rows (row lines) and a plurality of columns (column lines). Each of the pixels PX includes a plurality of sub-pixels SP with different colors from each other. Each of the sub-pixels SP includes a light-emitting element and a pixel circuit and can emit light independently. The sub-pixels SP may include, but are not limited to, red sub-pixels, blue sub-pixels, and green sub-pixels, etc.

[0047] The plurality of gate driving areas GA include the circuits of the gate driving unit GD. The gate driving areas GA may be formed along the row direction and / or the column direction among the plurality of pixel areas UPA. The gate driving unit GD formed in the gate driving area GA can provide gate signals to a plurality of gate lines SL. The gate driving areas GA may be arranged between adjacent pixel areas UPA in the row direction (X-axis).

[0048] The first pad area PA1 includes a plurality of first pad electrodes PAD1 arranged on the outer front surface of one side (or the upper side) of the display panel PN. The first pad electrodes PAD1 can transmit various signals to various wirings extending in the column direction in the display area AA. The first pad electrodes PAD1 include a data pad DP connected to the data line DL to transmit a data voltage from the data driving unit DD to the data line DL, and a gate pad GP connected to the gate driving unit GD to transmit a clock signal, a start signal, a gate low voltage, a gate high voltage, etc. for driving the gate driving unit GD to the gate driving unit GD. The clock signal, start signal, gate low voltage, gate high voltage, etc. for driving the gate driving unit GD may be generated from the timing controller TC and applied to the gate pad GP through a level shifter and a PCB. The first pad electrodes PAD1 may include a plurality of power supply wirings to which a DC voltage (or a constant voltage) is applied.

[0049] The first substrate SUBS1 of the display panel PN is connected to the gate pad GP and includes gate driving wirings connected in the column direction and a plurality of gate driving wirings GVL extending in the row direction. The gate driving wirings in the column direction and the gate driving wirings GVL in the row direction can be connected through contact holes penetrating an insulating film. The gate driving wiring GVL transmits signals necessary for driving the gate driving units GD distributed in the gate driving region GA, such as clock signals, start signals, gate high voltages, gate low voltages, etc., to the circuits of the gate driving units GD.

[0050] The second pad region PA2 includes a plurality of second pad electrodes PAD2 disposed on the back outer contour of the other side (or the lower side) of the display panel PN. The second pad region PA2 may include a plurality of low potential power pads VP2.

[0051] A DC voltage applied from a power supply circuit (omitted in the drawings) to a power supply wiring is output and can be applied to pads VP1 and VP2 connected to the power supply wiring through a PCB. The power supply circuit may be a DC-DC converter disposed on a PCB or control boards CTB1 and CTB2 disposed on the back of the display panel PN, which converts a DC input voltage from a main power supply unit into a DC voltage suitable for driving the display panel PN.

[0052] The power pads VP1 and VP2 connected to the power supply wiring are disposed on the first pad region PA1 and include a plurality of high potential power pads VP1 that transmit a high potential power supply voltage to a high potential power supply wiring HL, and a plurality of low potential power pads VP2 disposed on the second pad region PA2 that transmit a low potential power supply voltage to a low potential power supply wiring CL.

[0053] The data pads DP connected to the data lines DL in a one-to-one manner may have a relatively narrow width, and the power pads VP1, VP2 and the gate pad GP may have a relatively wide width. The low potential power pad VP2 may have a wider width than the high potential power pad VP1.

[0054] In order to minimize the non-display area NA of the outermost contour of the display panel PN, after the pixel array, wiring, and pads are formed on the front surface of the substrate of the display panel PN, the outermost contour portion outside the scribing line SCL indicated by the dotted line is removed, and a substrate SUBS with a minimized non-display area NA can be provided. After the scribing process, the rough edge of the outer contour of the substrate SUBS can be ground or laser trimmed. In this way, short pad electrodes PAD1 and PAD2 remain on the front surface of the outer contour of the substrate SUBS whose size has been reduced.

[0055] The data line DL extends in the column direction (Y direction) on the first substrate SUBS and can overlap with the pixel region UPA. The data line DL supplies data voltage to the pixel circuits of each sub-pixel SP. The gate line SL extends in the row direction (X direction) on the substrate SUBS of the display panel PN and can overlap with the pixel region UPA and the gate drive region GA. The gate line SL can supply the gate signal from the gate drive unit GD to the pixel circuits of each sub-pixel SP across the pixel region UPA and the gate drive region GA.

[0056] The high-potential power supply wiring VL1 extends in the column direction (Y direction), and at least one of them is connected to the auxiliary high-potential power supply wiring AVL1 extending in the row direction (X direction) in a mesh structure. The auxiliary high-potential power supply wiring AVL1 is connected to the sub-pixels SP arranged in the row direction (X direction). Therefore, the high-potential power supply voltage applied to the high-potential power supply wiring VL1 can be transmitted to the sub-pixels SP through the auxiliary high-potential power supply wiring AVL1.

[0057] The low-potential power supply wiring VL2 extends in the column direction (Y direction), and at least one of them can be connected to the auxiliary low-potential power supply wiring AVL2 extending in the row direction (X direction) in a mesh structure. The auxiliary low-potential power supply wiring AVL2 is connected to the sub-pixels SP arranged in the row direction (X direction). Therefore, the sub-pixels SP are connected to the auxiliary high-potential power supply wiring AVL1 to which the low-potential power supply voltage is applied.

[0058] Due to the mesh structure of the power supply wiring, the resistance of the power supply wiring can be reduced, and the voltage drop of the high-potential power supply voltage and the variation in the power supply voltage within the display area AA can be improved.

[0059] The substrate SUBS of the display panel PN may include one or more alignment keys AK1, AK2 arranged between the pixel regions UPA. The alignment keys AK1, AK2 can be used for alignment in the manufacturing process of the display panel PN. The first alignment key AK1 can be arranged in the gate driving region GA. The first alignment key AK1 can be used to inspect the alignment positions of the respective light-emitting elements. The first alignment key AK1 can be formed by a cross pattern, but is not limited thereto. The second alignment key AK2 can be superimposed on the high-potential power supply wiring HL. The high-potential power supply wiring HL includes a hole formed at a position where it is superimposed on the second alignment key AK2, and the second alignment key AK2 and the high-potential power supply wiring HL can be separated. The second alignment key AK2 can be used when aligning the display panel PN and a donor substrate. The donor substrate is an intermediate medium for mounting light-emitting elements on the substrate SUBS of the display panel PN. A plurality of light-emitting elements manufactured on a semiconductor wafer are attached to and transferred by the donor substrate, and the light-emitting elements attached to the donor substrate can be transferred onto the substrate SUBS. The second alignment key AK2 can be formed from a circular or annular pattern, but is not limited thereto.

[0060] FIG. 5 is a cross-sectional view showing the cross-sectional structure of a display panel according to an embodiment of the present invention.

[0061] Referring to FIG. 5, on the first substrate SUBS1, a pixel circuit for driving a light-emitting element ED is arranged for each of the plurality of sub-pixels SP. The pixel circuit may include a plurality of thin-film transistors and one or more capacitors. For the sake of convenience of explanation, the driving element DT, the first capacitor C1, and the second capacitor C2 used in the pixel circuit are shown, but the display panel PN may further include other circuit elements.

[0062] On the first substrate SUBS1, a pattern of a first metal layer can be disposed. The pattern of the first metal layer may include a light-shielding layer BSM. The light-shielding layer BSM can block light incident on the active layer ACT of the driving element DT to minimize leakage current. The light-shielding layer BSM can be formed of an opaque conductive material, for example, a metal such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), etc., an alloy of these metals, or a multi-layer metal layer.

[0063] On the light-shielding layer BSM, a buffer layer BUF can be disposed. The buffer layer BUF can block the penetration of moisture or impurities through the first substrate SUBS1. The buffer layer BUF can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0064] On the buffer layer BUF, a driving element DT including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE can be disposed.

[0065] The active layer ACT can be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. The gate insulating layer GI electrically insulates the active layer ACT and the gate electrode GE of the driving element DT. The gate insulating layer GI can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0066] On the gate insulating layer GI, a pattern of a second metal layer can be disposed. The pattern of the second metal layer may include the gate electrode GE of the driving element DT. The second metal layer can be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer.

[0067] On the gate electrode GE, a first interlayer insulating layer ILD1 and a second interlayer insulating layer ILD2 are disposed. In the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, contact holes are formed for connecting the source electrode SE and the drain electrode DE of the driving element DT to the active layer ACT respectively. Each of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0068] On the second interlayer insulating layer ILD2, a pattern of a third metal layer can be disposed. The pattern of the third metal layer overlaps with the active layer ACT and can include a source electrode SE and a drain electrode DE connected to the active layer ACT through contact holes penetrating the interlayer insulating layers ILD1 and ILD2. The source electrode SE can be connected to the first electrodes E1 of the capacitors C1, C2 and the light-emitting element ED. The third metal layer can be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer.

[0069] The first capacitor C1 includes a first capacitor electrode C1a and a second capacitor electrode C1b. The first capacitor electrode C1a can be formed from a pattern of a second metal layer disposed on the gate insulating layer GI. The second capacitor electrode C1b is formed from a pattern of a fourth metal layer disposed on the first interlayer insulating layer ILD1 and overlaps with the first capacitor electrode C1a with the first interlayer insulating layer ILD1 interposed therebetween. The second capacitor electrode C1b can be connected to the source electrode SE of the driving element DT. The fourth metal layer can be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer.

[0070] The second capacitor C2 includes a third capacitor electrode C2a that overlaps with the first capacitor electrode C1a with the buffer layer BUF and the gate insulating layer GI interposed therebetween. The third capacitor electrode C2a can be formed from a pattern of a first metal layer disposed on the first substrate SUBS1.

[0071] The second capacitor C2 is electrically connected between the source electrode SE of the driving element DT and the light emitting element ED, can increase the capacitance of the light emitting element ED, and can increase the brightness when the light emitting element ED emits light.

[0072] The first passivation layer PAS1 covers the pattern of the third metal layer and the second interlayer insulating layer ILD2 so as to cover the pattern of the third metal layer. The first passivation layer PAS1 can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0073] A first planarization layer PLN1 is disposed on the first passivation layer PAS1. The first planarization layer PLN1 covers the first passivation layer PAS1 and planarizes the surface on which the light emitting element is disposed. The first planarization layer PLN1 can be a thick single-layer or multi-layer organic insulating layer made of benzocyclobutene or an acrylic-based organic material.

[0074] A pattern of a fifth metal layer can be disposed on the first planarization layer PLN1. The pattern of the fifth metal layer can include a reflective layer RF. The reflective layer RF reflects the light from the light emitting element ED to the front side of the display panel PN to enhance the light efficiency, and can be used as an electrode connecting the light emitting element ED to the pixel circuit or the power supply wiring. The reflective layer RF can be electrically connected to the source electrode SE of the driving element DT and the first capacitor C1 through a contact hole CH1 penetrating the first planarization layer PLN1 and the first passivation layer PAS1. Then, the reflective layer RF can be electrically connected to the first electrode E1 of the light emitting element ED through the anode electrode AND, or can electrically connect the second electrode E2 of the light emitting element ED and the high potential power supply wiring HL. The fifth metal layer can be formed of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), a transparent electrode material such as ITO (Indium Tin Oxide), or a multi-layer metal layer.

[0075] The second passivation layer PAS2 covers the pattern of the fifth metal layer and the first planarization layer PLN1. The second passivation layer PAS2 can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0076] On the second passivation layer PAS2, an adhesive layer AD can be disposed to fix the light-emitting element ED. The adhesive layer AD can be formed of a photocurable resin that can be cured by light. The adhesive layer AD can be formed of an acrylic-based substance containing a photosensitizer, but is not limited thereto. The adhesive layer AD can be formed on the entire surface of the first substrate SUBS1 except for the pad regions PA1 and PA2 where the first pad electrode PAD1 is disposed.

[0077] On the adhesive layer AD, the light-emitting elements ED of each sub-pixel SP can be disposed. The light-emitting element ED can be caused to emit light by a current from the driving element DT. The light-emitting element ED can include a red light-emitting element (ED), a green light-emitting element (ED), and a blue light-emitting element (ED). The light-emitting element ED can be an LED (Light Emitting Diode) or a micro LED.

[0078] Each of the light-emitting elements ED includes a first semiconductor pattern SEM1, a light-emitting layer EM, a second semiconductor pattern SEM2, a first electrode E1, and a second electrode E2.

[0079] A first semiconductor pattern SEM1 is disposed on the subsequent layer AD, and a second semiconductor pattern SEM2 is disposed on the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 can be formed from semiconductor patterns obtained by doping n-type and p-type impurities into a semiconductor material. For example, each of the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 can be a layer doped with n-type or p-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The p-type impurity can be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity can be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0080] An emission layer EM is disposed between the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2. The emission layer EM can be supplied with holes and electrons from the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 and can emit light. The emission layer EM can be composed of a single layer or a multi-quantum well (MQW) structure and can be formed from, for example, indium gallium nitride (InGaN) or gallium nitride (GaN).

[0081] A first electrode E1 is disposed on the first semiconductor pattern SEM1. The first electrode E1 electrically connects the driving element DT and the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 can be formed from a semiconductor layer doped with n-type impurities. The first electrode E1 can be an anode electrode of a light-emitting element ED disposed on the first semiconductor pattern SEM1 and electrically connected to the driving element DT through a reflective layer RF and capacitors C1 and C2. The first electrode E1 can be disposed on the upper surface of the first semiconductor layer SEM1. The first electrode E1 can be formed from a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0082] On the second semiconductor pattern SEM2, a second electrode E2 is disposed. The second electrode E2 electrically connects the high potential power supply wiring HL and the second semiconductor layer SEM2. The second semiconductor layer SEM2 can be formed from a semiconductor layer doped with p-type impurities. The second electrode E2 can be the cathode electrode of the light-emitting element ED. The second electrode E2 can be formed from a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0083] The light-emitting element ED may include a sealing layer ENS. The sealing layer ENS covers the semiconductor patterns SEM1, SEM2 and the electrodes E1, E2 to protect the light-emitting element ED. The sealing layer ENS and the third planarization layer PLN3 include contact holes that expose the first electrode E1 and the second electrode E2. The anode electrode AND is connected to the reflective layer RF through a first contact hole that penetrates the sealing layer ENS and the third planarization layer PLN3. The cathode electrode CAT is connected to the second electrode E2 through a second contact hole that penetrates the sealing layer ENS and the third planarization layer PLN3. On the other hand, a part of the side surface of the first semiconductor pattern SEM1 can be exposed without the sealing layer ENS.

[0084] The second planarization layer PLN2 and the third planarization layer PLN3 can cover the adhesive layer AD and the light-emitting element ED. The second planarization layer PLN2 contacts the lower end of the side surface of the light-emitting element ED to fix the light-emitting element ED. The third planarization layer PLN3 covers the light-emitting element ED on the second planarization layer PLN2. The third planarization layer PLN3 includes contact holes that expose the first electrode E1 and the second electrode E2 of the light-emitting element ED. The second planarization layer PLN2 and the third planarization layer PLN3 can be formed from a single-layer or multi-layer organic insulating material, such as a photoresist or an acrylic-based organic material.

[0085] On the third planarization layer PLN3, the pattern of the sixth metal layer may be disposed. The sixth metal layer may include an anode electrode AND and a cathode electrode CAT. The anode electrode AND electrically connects the first electrode E1 of the light emitting element ED and the reflective layer RF. The anode electrode AND is connected to the first electrode E1 of the light emitting element ED through a contact hole penetrating the insulating layers PLN3 and ENS, and may be connected to the reflective layer RF through a contact hole penetrating the insulating layers PAS2, AD, PLN2, and PLN3.

[0086] The cathode electrode CAT is connected to the second electrode E2 of the light emitting element ED through a contact hole penetrating the insulating layers PLN3 and ENS. The cathode electrode CAT may be connected to the low potential power supply wiring CL.

[0087] According to the embodiment, the light emitting element ED is shown as having a horizontal structure in which the electrodes are connected to the upper surfaces of the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2, but is not necessarily limited thereto. Exemplarily, the light emitting element ED may also have a vertical structure in which the anode electrode AND is disposed below the first semiconductor pattern SEM1.

[0088] On the second planarization layer PLN2, a bank pattern BB may be disposed. The bank pattern BB may be spaced apart from the light emitting element ED by a certain distance. The bank pattern BB can cover a part of the anode electrode AND present in the contact hole penetrating the insulating layers PLN2 and PLN3. The bank pattern BB can prevent optical crosstalk between the sub-pixels SP and reduce color mixing between the sub-pixels SP. For this purpose, the bank pattern BB may be formed of a black resin, but is not limited thereto.

[0089] The first protective layer CPA can cover the metal layer of the sixth metal layer, the bank pattern BB, the second planarization layer PLN2, and the third planarization layer PLN3. The first protective layer CPA may be formed from a single layer, a multi-layer insulating layer of a light-transmissive epoxy, silicon oxide (SiOx), silicon nitride (SiNx), or the like.

[0090] Each of the first pad electrodes PAD1 disposed in the pad regions PA1 and PA2 of the first substrate SUBS1 may have a multi-layer metal layer structure. For example, each of the first pad electrodes PAD1 may include a first pad metal layer PE1a, a second pad metal layer PE1b, and a third pad metal layer PE1c laminated on the front surface of the outermost contour of the first substrate SUBS1.

[0091] The pattern of the third metal layer disposed on the second interlayer insulating layer ILD2 may further include the first pad metal layer PE1a. The first pad metal layer PE1a may be formed of the same metal as the source electrode SE and the drain electrode DE of the driving element DT, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer.

[0092] The pattern of the fifth metal layer disposed on the first planarization layer PLN1 may further include the second pad metal layer PE1b. The second pad metal layer PE1b may be formed of the same metal as the reflective layer RF, for example, silver (Ag), aluminum (Al), molybdenum (Mo), or a multi-layer metal layer.

[0093] The pattern of the sixth metal layer disposed on the third planarization layer PLN3 may further include the third pad metal layer PE1c. The third pad metal layer PE1c may be formed of the same conductive material as the anode electrode AND and the cathode electrode CAT, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or a multi-layer metal layer.

[0094] Under the first pad electrode PAD1, the first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers may be arranged. By arranging the first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers under the first pad electrode PAD1, the step of the first pad electrode PAD1 can be adjusted. For example, a buffer layer BUF, a gate insulating layer GI, the first metal layer ML1, a first interlayer insulating layer ILD1, and the second metal layer ML2 may be sequentially arranged between the first pad electrode PAD1 and the first substrate SUBS1. The pattern of the second metal layer arranged on the gate insulating layer GI may include the first metal layer ML1. The pattern of the fourth metal layer arranged on the first interlayer insulating layer ILD1 may include the second metal layer ML2. The plurality of insulating layers and the metal layers ML1 and ML2 under the first pad electrode PAD1 are not limited to those shown in FIG. 5.

[0095] The second substrate SUBS2 may be arranged on the back surface of the first substrate SUBS1. A bonding layer BDL is arranged between the first substrate SUBS1 and the second substrate SUBS2. The bonding layer BDL is cured through various curing methods to bond the first substrate SUBS1 and the second substrate SUBS2 together. The bonding layer BDL may be arranged only in a partial region or in the entire region between the first substrate SUBS1 and the second substrate SUBS2. The first substrate SUBS1 and the second substrate SUBS are simultaneously scribed and ground so that the side surfaces of the first substrate SUBS1 and the second substrate SUBS2 can be side surfaces without a step.

[0096] A plurality of second pad electrodes PAD2 may be arranged on the outermost back surface of the second substrate SUBS2. The second pad electrode PAD2 is electrically connected to the side wiring SRL and the first pad electrode PAD1 to transmit a signal from a circuit component arranged on the back surface of the second substrate SUBS2 to a sub-pixel SP arranged on the upper surface of the first substrate SUBS1.

[0097] Each of the second pad electrodes PAD2 may have a multi-layer metal layer structure. For example, each of the second pad electrodes PAD2 may include a first pad metal layer PE2a, a second pad metal layer PE2b, and a third pad metal layer PE2c laminated on the back surface of the outermost contour of the second substrate SUBS2. Each of the first and second pad metal layers PE2a, PE2b may be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer. The third pad metal layer PE2c may be formed of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0098] A second protective layer BCL may be disposed on the back surface of the second substrate SUBS2. The second protective layer BCL can cover various wirings on the back surface of the second substrate SUBS2 except for the second pad electrode PAD2. The second protective layer BCL may be made of an organic insulating material and may be formed of, for example, benzocyclobutene or an acrylic-based organic insulating material.

[0099] Circuit components such as a plurality of flexible films and PCBs may be disposed on the back side of the second substrate SUBS2. An output terminal of the flexible film is electrically connected to the second pad electrode PAD2, and an input terminal of the flexible film is electrically connected to an output terminal of the PCB. Therefore, signals and voltages output from the PCB can be transmitted to the sub-pixels SP disposed on the front surface of the first substrate SUBS1 through the flexible film, the second pad electrode PAD2, the side wiring SRL, the plurality of first pad electrodes PAD1, and the wiring connected to the first pad electrode PAD1.

[0100] The side wiring SRL electrically connects the first pad electrode PAD1 and the second pad electrode PAD2 across the sides of the first substrate SUBS1 and the second substrate SUBS2. The side wiring SRL may be formed on the sides of the substrates SUBS1, SUBS2 by a pad printing method using a conductive ink, for example, a conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), and chromium (Cr).

[0101] The side insulation layer SDI can cover the side wiring SRL formed on the upper, side, and back surfaces of the outermost contours of the first substrate SUBS1 and the second substrate SUBS2 that are bonded to each other. When the side wiring SRL is made of metal, external light may be reflected from the side wiring SRL, or the light emitted from the light-emitting element ED may be reflected from the side wiring SRL and be visible to the user. In order to improve image quality degradation caused by such reflected light, the side insulation layer SDI may contain a black substance that absorbs external light. For example, the side insulation layer SDI may be formed on the outermost contours of the first substrate SUBS1 and the second substrate SUBS2 from black ink that can be applied by a printing method.

[0102] The protective layer (Seal) SS can cover the side insulation layer SDI and protect the display panel PN from external impact, moisture, oxygen, etc. For example, the protective layer SS may be made of black ink, polyimide (PI), polyurethane (Poly Urethane), epoxy (Epoxy), acrylic (Acryl) series insulating materials, etc. The protective layer SS may be a concept that includes the side insulation layer SDI. That is, the protective layer SS and the side insulation layer SDI can also be composed of one layer.

[0103] The cover film MF can cover the front surface of the first display panel PN. The cover film MF can be one or more of various functional films such as an anti-scattering film, an anti-glare film, an anti-reflecting film, a low-reflecting film, an oled transmittance controllable film, a color difference compensation film, and a polarizing plate. The anti-scattering film prevents the scattering of substrate fragments and particles when the display panel PN is damaged. The cover film MF can be cut and removed along with the outer contour portion of the protective layer SS along the cutting line that overlaps the protective layer SS after the protective layer SS is widely adhered to the front surface of the first substrate SUBS1. As a result, at the outermost contour of the cover film MF and the protective layer SS, the exposed side surfaces can form flush side surfaces without steps.

[0104] FIG. 6 is a diagram showing a pixel according to an embodiment of the present invention. FIG. 7 is a diagram showing a red sub-pixel according to an embodiment of the present invention. FIG. 8 is a diagram showing a green sub-pixel according to an embodiment of the present invention. FIG. 9 is a diagram showing a blue sub-pixel according to an embodiment of the present invention. FIG. 10 is a diagram showing the cathode electrodes of the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

[0105] Referring to FIG. 6, a pixel can include six sub-pixels. Exemplarily, a pixel can include two red sub-pixels R1, R2, two green sub-pixels G1, G2, and two blue sub-pixels B1, B2. Each sub-pixel can include a pixel circuit including a light-emitting element and a compensation circuit. The compensation circuit is a circuit for compensating the threshold voltage of the driving element, and the pixel circuit can be a concept including a light-emitting element, a driving element, and a compensation circuit. When a sub-pixel includes two light-emitting elements and one compensation circuit, it can be defined as one sub-pixel.

[0106] According to the embodiment, each of the sub-pixels R1, R2, G1, G2, B1, B2 can be driven independently or simultaneously. A plurality of sub-pixels R1, R2, G1, G2, B1, B2 can share a gate line and be driven simultaneously. However, it is not necessarily limited to this. The gate line can be composed of multiple lines, and a first pixel group R1, G1, B1 connected to the first gate line SCAN1 and a second pixel group R2, G2, B2 connected to the second gate line SCAN2 can also be driven independently.

[0107] The two red sub-pixels R1, R2 can be respectively connected to data lines VdataR1, VdataR2. In contrast, the two green sub-pixels G1, G2 can share one data line VdataG, and the two blue sub-pixels B1, B2 can share one data line VdataB. Therefore, the number of data wirings can be reduced.

[0108] Since the red sub-pixels R1, R2 are relatively inefficient, the two red sub-pixels are driven independently to adjust the luminance. On the other hand, since the green sub-pixels G1, G2 and the blue sub-pixels B1, B2 are relatively efficient, they can emit light simultaneously using one data line.

[0109] In this case, since two light-emitting elements are turned on simultaneously by one data voltage, there is an advantage that the desired luminance can be output even if the data voltage is lowered. However, it is not necessarily limited to this. The green sub-pixels and the blue sub-pixels can also be separately connected to data lines and driven independently.

[0110] Referring to FIG. 7, the red sub-pixel may include a first red sub-pixel (the first - 1 sub-pixel) R1 and a second red sub-pixel (the first - 2 sub-pixel) R2. The first red sub-pixel R1 may include a first red light-emitting element ED11 and a first red compensation circuit PC11. The first red light-emitting element ED11 may be connected to an anode electrode AND connected to the high-potential power supply wiring HL and a cathode electrode CAT connected to the low-potential power supply wiring CL1. The first red compensation circuit PC11 may be connected between the first data line VdataR1 and the low-potential power supply wiring CL1.

[0111] The second red sub-pixel R2 may include a second red light-emitting element ED12 and a second red compensation circuit PC12. The second red light-emitting element ED12 may be connected to an anode electrode connected to the high-potential power supply wiring HL and a cathode electrode connected to the low-potential power supply wiring CL2. The second red compensation circuit PC12 may be connected between the second data line VdataR2 and the low-potential power supply wiring CL2.

[0112] According to the embodiment, since the first red sub-pixel R1 and the second red sub-pixel R2 are respectively connected to the first data line VdataR1 and the second data line VdataR2, they can be independently driven. Therefore, when the voltage levels applied to the first data line VdataR1 and the second data line VdataR2 are adjusted differently, the first red light-emitting element ED11 and the second red light-emitting element ED12 can emit light with different luminances. That is, the luminances of the first red light-emitting element ED11 and the second red light-emitting element ED12 can be independently controlled according to the overall luminance of the red light to be output from the pixel. Or, the first red light-emitting element ED11 and the second red light-emitting element ED12 can also be alternately driven. However, it is not necessarily limited to this. The first red sub-pixel R1 and the second red sub-pixel R2 can also be simultaneously driven by one data line. Since the first red sub-pixel R1 and the second red sub-pixel R2 are each composed of independent pixels, even if a short-circuit failure occurs in either the first red sub-pixel R1 or the second red sub-pixel R2, it will not affect the other one.

[0113] Referring to FIG. 8, the green sub-pixel may include a first green sub-pixel (sub-pixel No. 2-1) G1 and a second green sub-pixel (sub-pixel No. 2-2) G2. The first green sub-pixel G1 may include a first green light-emitting element ED21 and a first green compensation circuit PC21. The first green light-emitting element ED21 may be connected to an anode electrode connected to the high-potential power supply wiring HL and a cathode electrode connected to the low-potential power supply wiring CL3. The first green compensation circuit PC21 may be connected between the third data line VdataG and the low-potential power supply wiring CL3.

[0114] The second green sub-pixel G2 may include a second green light-emitting element ED22 and a second green compensation circuit PC22. The second green light-emitting element ED22 may be connected to an anode electrode connected to the high-potential power supply wiring HL and a cathode electrode connected to the low-potential power supply wiring CL4. The second green compensation circuit PC22 may be connected between the third data line VdataG and the low-potential power supply wiring CL4.

[0115] According to the embodiment, since the first green sub-pixel G1 and the second green sub-pixel G2 are commonly connected to the third data line VdataG, they can be driven simultaneously. Therefore, the data voltage can be set relatively low. For example, if the data voltage to be applied to output the luminance of the green sub-pixel defined in the frame is 1V, even if the data voltage is lowered to 0.5V and applied, since the two green light-emitting elements emit light, green light of a desired luminance can be output.

[0116] Exemplarily, in the case of the second pixel in which any one of the first green sub-pixel G1 and the second green sub-pixel G2 is defective, since the luminance has to be adjusted using one pixel, a data voltage twice as high as that of the first pixel in which the two sub-pixels all emit light has to be applied to adjust the luminance to be the same.

[0117] According to the embodiment, the anode electrode of the first green light-emitting element ED21 and the anode electrode of the second green light-emitting element ED22 are electrically separated, and the cathode electrode of the first green light-emitting element ED21 and the cathode electrode of the second green light-emitting element ED22 can be electrically separated. Therefore, even if a short circuit occurs between the high potential voltage VDD and the low potential voltage VSS due to a defect in the first green light-emitting element ED21, causing the first green light-emitting element ED21 to become a dark spot, it will not affect the adjacent second green light-emitting element ED22.

[0118] The defect of the first green light-emitting element ED21 can be a defect in the electrode pad or a defect due to a defect in the semiconductor layer itself. In the case of a micro-sized light-emitting diode, it is small in size and vulnerable to static electricity, and after being fabricated in micro-size on a wafer and then transferred to a panel, the defect rate can be high due to various reasons.

[0119] Therefore, when the first green light-emitting element ED21 and the second green light-emitting element ED22 are connected in series or in parallel, if a short-circuit defect occurs in any one of the light-emitting elements, causing a short circuit between the high potential voltage VDD and the low potential voltage VSS and resulting in dark spots, the adjacent normal light-emitting elements can also have a short current flowing through them and become dark spots. However, according to the embodiment, since the anode electrode and the cathode electrode of the first green light-emitting element ED21 and the second green light-emitting element ED22 are separated from each other, even if a short-circuit defect occurs in any one of the light-emitting elements, it can be prevented from causing dark spots in the adjacent light-emitting elements. Therefore, the adjacent light-emitting elements can operate normally.

[0120] Referring to FIG. 9, the blue sub-pixel may include a first blue sub-pixel (the 3-1st sub-pixel) B1 and a second blue sub-pixel (the 3-2nd sub-pixel) B2. The first blue sub-pixel B1 may include a first blue light-emitting element ED31 and a first blue compensation circuit PC31. The first blue light-emitting element ED31 may be connected to an anode electrode connected to the high-potential power supply wiring HL and a cathode electrode connected to the low-potential power supply wiring CL5. The first blue compensation circuit PC31 may be connected between the fourth data line VdataB and the low-potential power supply wiring CL5.

[0121] The second blue sub-pixel B2 may include a second blue light-emitting element ED32 and a second blue compensation circuit PC32. The second blue light-emitting element ED32 may be connected to an anode electrode connected to the high-potential power supply wiring HL and a cathode electrode connected to the low-potential power supply wiring CL6. The second blue compensation circuit PC32 may be connected between the fourth data line VdataB and the low-potential power supply wiring CL6.

[0122] According to the embodiment, since the first blue sub-pixel B1 and the second blue sub-pixel B2 are commonly connected to the fourth data line VdataB, they can be driven simultaneously. Therefore, the data voltage can be set lower than the voltage level for causing one blue light-emitting element to emit light with a desired luminance.

[0123] Exemplarily, in the case of the third pixel in which any one of the first blue sub-pixel B1 and the second blue sub-pixel B2 is defective, since the luminance has to be adjusted using one pixel, it is necessary to apply a data voltage twice as high as that of the first pixel in which both of the two sub-pixels emit light to adjust the luminance to be the same.

[0124] Further, the anode electrode of the first blue light-emitting element ED31 and the anode electrode of the second blue light-emitting element ED32 are electrically separated, and the cathode electrode of the first blue light-emitting element ED31 and the cathode electrode of the second blue light-emitting element ED32 can be electrically separated. Therefore, even if a short-circuit failure occurs in any one of the light-emitting elements, it is possible to prevent the adjacent light-emitting elements from being darkened.

[0125] Referring to FIG. 10, within a pixel, the anode electrode AND1 of the first red sub-pixel R1, the anode electrode AND2 of the second red sub-pixel R2, the anode electrode AND3 of the first green sub-pixel G1, the anode electrode AND4 of the second green sub-pixel G2, the anode electrode AND5 of the first blue sub-pixel B1, and the anode electrode AND6 of the second blue sub-pixel B2 can be electrically separated from each other.

[0126] Also, the cathode electrode CAT1 of the first red sub-pixel R1, the cathode electrode CAT2 of the second red sub-pixel R2, the cathode electrode CAT3 of the first green sub-pixel G1, the cathode electrode CAT4 of the second green sub-pixel G2, the cathode electrode CAT5 of the first blue sub-pixel B1, and the cathode electrode CAT6 of the second blue sub-pixel B2 can be electrically separated from each other.

[0127] Also, a plurality of high-potential power supply lines HL connected to the respective anode electrodes AND1 to AND6 can be separated from each other, and a plurality of low-potential power supply lines CL connected to the respective cathode electrodes CAT1 to CAT6 can be separated from each other. Therefore, it is possible to prevent the light-emitting elements of adjacent sub-pixels from being darkened due to a short-circuit failure of any one of the light-emitting elements among the plurality of sub-pixels.

[0128] FIG. 11 is a circuit diagram showing a schematic pixel circuit according to an embodiment of the present invention. FIG. 12 is a circuit diagram showing a pixel circuit according to an embodiment of the present invention.

[0129] Referring to FIG. 11, sub-pixels SP1 and SP2 of the same color each include a light-emitting element ED, a driving element DT, a first switching element M1, and a compensation circuit PC. The sub-pixels SP1 and SP2 of the same color can be green or blue sub-pixels.

[0130] Since the two sub-pixels SP1 and SP2 have the same structure with the data line PL2 to which the data voltage Vdata is applied in between, the reference numerals of the pixel circuits of each sub-pixel will be described with the same reference numerals. Hereinafter, the description will be made based on the second sub-pixel SP2 arranged on the right side.

[0131] The second sub-pixel SP2 may include a light-emitting element ED, a driving element DT, a first switching element M1, and a compensation circuit PC. The light-emitting element ED, the driving element DT, and the switching element M1 can be connected in series between the high potential voltage VDD and the low potential voltage VSS.

[0132] The driving element DT adjusts the current flowing through the drain-source channel according to the gate-source voltage. The gate-source voltage of the driving element DT varies according to the data voltage Vdata of the pixel data applied to the gate electrode of the driving element DT. Therefore, the current flowing through the driving element DT changes according to the data voltage Vdata. The light-emitting element ED can be driven by the current from the driving element DT to emit light. A capacitor C can be connected between the gate electrode of the driving element DT and the first electrode. The gate-source voltage of the driving element DT is charged in the capacitor C.

[0133] The driving element DT can be connected between the light-emitting element ED and the first switching element M1. In this case, the driving element DT includes a gate electrode to which the data voltage Vdata is applied, a first electrode connected to the cathode electrode of the light-emitting element ED, and a second electrode connected to the first electrode of the first switching element M1.

[0134] The first switch element M1 switches the current path between the high potential voltage VDD and the low potential voltage VSS. The first switch element M1 can be turned on in response to the gate-on voltage of one of the gate signals GATE1 and GATE2, and can be turned off in response to the gate-off voltage. When the first switch element M1 is turned on, the drive element DT and the light-emitting element ED are electrically connected, and current can be supplied to the light-emitting element ED. When the first switch element M1 is turned off, the current path between the high potential voltage VDD and the low potential voltage VSS is interrupted, and no current is supplied to the light-emitting element ED.

[0135] The first switch element M1 can be connected between the drive element DT and the cathode voltage VSS. In this case, the first switch element M1 includes a gate electrode connected to the first gate line, a first electrode connected to the second electrode of the drive element DT, and a second electrode connected to the node to which the cathode voltage VSS is applied.

[0136] The pixel circuit may further include a second switch element M2. The second switch element M2 is connected between the cathode electrode and the anode electrode of the light-emitting element ED, and can be turned on in response to a gate signal applied through a compensation circuit. When the second switch element M2 is turned on, the cathode electrode and the anode electrode of the light-emitting element ED are short-circuited, and the light-emitting element ED does not emit light. The second switch element M2 can prevent the light-emitting element ED from emitting light when the pixel circuit is initialized and when the threshold voltage of the drive element DT is sampled. The second switch element M2 includes a gate electrode connected to the second gate line, a first electrode connected to the anode electrode of the light-emitting element ED, and a second electrode connected to the cathode electrode of the light-emitting element ED.

[0137] The first switch element M1 can be turned on in response to the gate-on voltage of the light emission signal and turned off in response to the gate-off voltage of the light emission signal, but is not limited thereto. The second switch element M2 can be turned on in response to the gate-on voltage of the first scan signal and turned off in response to the gate-off voltage of the first scan signal, but is not limited thereto.

[0138] The compensation circuit PC is connected to a data line to which a data voltage Vdata is applied, a gate line to which one or more scan signals SCAN1, SCAN2 are applied, the gate electrode of the drive element DT, and the gate electrode of the first switch element M1. One or more scan signals SCAN1, SCAN2 can be applied to the compensation circuit.

[0139] The compensation circuit uses a plurality of transistors to transmit the data voltage Vdata to the gate electrode of the drive element DT. The compensation circuit samples the threshold voltage of the drive element DT in the capacitor C and compensates the gate voltage of the drive element DT by only the threshold voltage of the drive element DT. The compensation circuit can compensate the threshold voltage of the drive element DT by using a source follower or a diode connection circuit.

[0140] Referring to FIG. 12, the pixel circuit may include a drive element DT connected to the light emitting element ED, a plurality of first switch elements M1 to M6, and a plurality of capacitors C1 to C3. The drive element DT and the plurality of first switch elements M1 to M6 may be P-channel transistors, but are not necessarily limited thereto.

[0141] The drive element DT may have its gate electrode G connected to the first node n1, its source electrode S connected to the second node n2, and its drain electrode D connected to the third node n3.

[0142] The light-emitting element ED can be arranged between the second node n2 and the high-potential voltage VDD. The light-emitting element ED can be a micro-sized light-emitting diode, but is not necessarily limited thereto. The source electrode S of the driving element DT can be connected to the cathode electrode of the light-emitting element ED.

[0143] The first switch element M1 can be connected between the third node n3 and the low-potential voltage VSS. When the first switch element M1 is turned on in response to the gate-on voltage of the light-emitting signal EM, the third node n3 and the low-potential voltage VSS can be connected.

[0144] The second switch element M2 is connected between the cathode electrode and the anode electrode of the light-emitting element ED, and can be turned on by the gate-on voltage of the first scan signal SCAN1. When the second switch element M2 is turned on, the light-emitting element stops emitting light.

[0145] The third switch element M3 is connected between the reference voltage line PL1 and the fourth node n4, and when turned on in response to the gate-on voltage of the light-emitting signal EM, the reference voltage Vref can be applied to the fourth node n4.

[0146] The fourth switch element M4 is arranged between the third node n3 and the first node n1, and when turned on in response to the gate-on voltage of the first scan signal SCAN1, the third node n3 and the first node n1 can be connected.

[0147] The fifth switch element M5 is arranged between the reference voltage line PL1 and the fifth node n5, and when turned on in response to the gate-on voltage of the second scan signal SCAN2, the reference voltage Vref can be applied to the fifth node n5.

[0148] The sixth switch element M6 is arranged between the data line PL2 and the fourth node n4, and when turned on in response to the gate-on voltage of the first scan signal SCAN1, the data voltage Vdata can be applied to the fourth node n4.

[0149] The first capacitor C1 is disposed between the first node n1 and the fourth node n4, the second capacitor C2 is disposed between the first node n1 and the second node n2, and the third capacitor C3 can be disposed between the second capacitor C2 and the anode electrode of the light-emitting element ED. The threshold voltage of the driving element and the data voltage can be stored in the second capacitor C2 and the third capacitor C3.

[0150] Referring to FIG. 13, in the first initialization period INI1, the first scan signal SCAN1 may output a gate-off voltage VGH, and the second scan signal SCAN2 may output a gate-on voltage VGL. The fifth switch element M5 to which the second scan signal SCAN2 is applied may be turned on, and the reference voltage may be applied to the third node n3. The reference voltage Vref applied during the emission period of the previous frame is maintained at the first node n1, and the reference voltage Vref may be applied to the third node n3.

[0151] In the second initialization period INI2, since both the first scan signal SCAN1 and the second scan signal SCAN2 are output with the gate-on voltage VGL, the second switch element M2, the fourth switch element M4, the fifth switch element M5, and the sixth switch element M6 may be turned on. Accordingly, the data voltage Vdata is charged to the first node n1, the reference voltage Vref is charged to the first node n1, and the first capacitor C1 may be initialized. Also, the gate electrode of the driving element DT may be initialized with the reference voltage Vref. At this time, since the second switch element M2 is turned on, the cathode electrode and the anode electrode of the light-emitting element ED may be short-circuited, and the light-emitting element ED may not emit light.

[0152] In the sampling period SAM, since the first scan signal SCAN1 is the gate-on voltage VGL and the second scan signal SCAN2 is the gate-off voltage VGH, the sixth switch element M6, the fourth switch element M4, and the second switch element M2 may be turned on. Therefore, the VDD + Vth voltage may be stored in the first node n1.

[0153] During the hold period HOL, since the first scan signal SCAN1, the second scan signal SCAN2, and the emission signal EM are all at the gate-off voltage VGH, all the switching elements can be turned off. Therefore, a voltage of VDD + Vth can be maintained at the first node n1.

[0154] During the emission period EMI, the first scan signal SCAN1 and the second scan signal SCAN2 are at the gate-off voltage VGH, and the emission signal EM can be at the gate-on voltage VGL. The first switching element M1 and the third switching element M3 can be turned on. Therefore, the reference voltage Vref is applied to the first node n1, and a voltage of VDD + Vth - (Vdata - Vref) can be applied to the first node n1 by capacitor coupling.

[0155] The current Ids flowing through the driving element DT can be defined as k(|Vgs| - |Vth|). 2 Therefore, since it is k(VDD - VDD - Vth + Vdata - Vref + Vth), when this is summarized, it can be simplified to k(Vdata - Vref). 2 Therefore, it can be simplified to k(Vdata - Vref). 2 Therefore, the threshold voltage of the driving element can be compensated.

[0156] FIG. 14 is a diagram showing a pixel in which sub-pixels are connected in parallel. FIG. 15 is a diagram showing the sub-pixels of FIG. 14.

[0157] Referring to FIGS. 14 and 15, the pixel can be composed of four sub-pixels R1, R2, G, and B. That is, the pixel can be composed of a first red sub-pixel R1, a second red sub-pixel R2, a green sub-pixel G, and a blue sub-pixel B.

[0158] The first red sub-pixel R1 and the second red sub-pixel R2 may each include a light-emitting element ED and a compensation circuit PC, similar to the structure described with reference to FIG. 7. However, for the green sub-pixel G, two green light-emitting elements ED may be arranged in parallel, and the two green light-emitting elements ED may share one compensation circuit PC. Also, for the red sub-pixel R, two red light-emitting elements ED may be arranged in parallel, and the two red light-emitting elements ED may share one compensation circuit PC. According to such a structure, the number of compensation circuits can be reduced, and the aperture ratio can be increased.

[0159] However, since the two green light-emitting elements ED1 and ED2 are connected in parallel, if a short-circuit defect occurs in any one of the light-emitting elements and it becomes a dark point, there is a problem that the adjacent light-emitting element is also short-circuited and becomes a dark point. Therefore, there is a problem that all of the green light-emitting elements ED1 and ED2 in the pixel become dark points.

[0160] FIGS. 16 and 17 are diagrams showing the process of repairing a sub-pixel.

[0161] Referring to FIG. 16, a plurality of pixels may include a first pixel PIXEL(N) arranged on a first pixel line and a second pixel PIXEL(N+1) arranged on a second pixel line. The first pixel PIXEL(N) may include a first sub-pixel SP1 and a second sub-pixel SP2 of the same color, and the second pixel PIXEL(N+1) may include a third sub-pixel SP3 and a fourth sub-pixel SP4 of the same color. The first pixel line and the second pixel line may be adjacent in the column direction (Y-axis), but are not limited thereto.

[0162] The first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 may each include a light-emitting element ED, a compensation circuit PC, a high-potential power supply wiring HL, and a low-potential power supply wiring CL.

[0163] The first sub-pixel SP1 can be arranged to face the third sub-pixel SP3 in the column direction, and the second sub-pixel SP2 can be arranged to face the fourth sub-pixel SP4 in the column direction.

[0164] The low-potential power supply wiring CL11 arranged in the first sub-pixel SP1 extends toward the third sub-pixel SP3, and the low-potential power supply wiring CL13 arranged in the third sub-pixel SP3 can extend toward the first sub-pixel SP1. Also, the low-potential power supply wiring CL12 arranged in the second sub-pixel SP2 extends toward the fourth sub-pixel SP4, and the low-potential power supply wiring CL14 arranged in the fourth sub-pixel SP4 can extend toward the second sub-pixel SP2.

[0165] Welding parts WP can be formed at the ends of the low-potential power supply wirings CL11, CL12, CL13, and CL14 that extend outside each sub-pixel. The welding part WP includes metal layers that overlap each other with an insulating layer in between and can be selectively connected in a welding process.

[0166] Referring to FIG. 17, when a defect occurs in the compensation circuit PC of the fourth sub-pixel SP4, the welding part WP of the low-potential power supply wiring CL14 of the fourth sub-pixel SP4 can be connected to the welding part WP of the low-potential power supply wiring CL12 of the second sub-pixel SP2 to form a repair part WP2. Therefore, in this case, in the fourth sub-pixel SP4, after electrically separating the light-emitting element ED and the compensation circuit PC, the welding part WP can be connected. According to such a configuration, when a defect occurs in the compensation circuit of each sub-pixel, it can be connected to the compensation circuit of an adjacent sub-pixel and operate normally.

[0167] The display panel according to an embodiment of the present invention and a display device including the same can be described as follows.

[0168] A display panel according to an embodiment of the present invention includes a plurality of pixels, and a gate line and a data line connected to the plurality of pixels. The plurality of pixels include a first-1 sub-pixel and a first-2 sub-pixel of a first color; a second-1 sub-pixel and a second-2 sub-pixel of a second color; and a third-1 sub-pixel and a third-2 sub-pixel of a third color. The second-1 sub-pixel and the second-2 sub-pixel each include a light-emitting element and a compensation circuit, and the compensation circuit of the second-1 sub-pixel and the compensation circuit of the second-2 sub-pixel are connected to one data line.

[0169] According to one or more embodiments of the present invention, the first-1 sub-pixel may include a first compensation circuit connected to a first data line, and the first-2 sub-pixel may include a second compensation circuit connected to a second data line.

[0170] According to one or more embodiments of the present invention, the third-1 sub-pixel and the third-2 sub-pixel each include a compensation circuit, and the compensation circuits of the third-1 sub-pixel and the third-2 sub-pixel may be connected to one data line.

[0171] According to one or more embodiments of the present invention, the first color may be red, the second color may be green, and the third color may be blue.

[0172] According to one or more embodiments of the present invention, the plurality of pixels may include a first pixel in which when a data voltage is applied, all of the second-1 sub-pixel and the second-2 sub-pixel emit light, and a second pixel in which when the data voltage is applied, only one of the second-1 sub-pixel and the second-2 sub-pixel emits light.

[0173] According to one or more embodiments of the present invention, the data voltages applied to the first sub-pixel and the second sub-pixel of the second pixel may be greater than the data voltages applied to the first sub-pixel and the second sub-pixel of the first pixel.

[0174] According to one or more embodiments of the present invention, the plurality of pixels may include a third pixel in which all of the first sub-pixel and the second sub-pixel emit light when a data voltage is applied, and a fourth pixel in which only one of the first sub-pixel and the second sub-pixel emits light when the data voltage is applied.

[0175] According to one or more embodiments of the present invention, the data voltages applied to the first sub-pixel and the second sub-pixel of the fourth pixel may be greater than the data voltages applied to the first sub-pixel and the second sub-pixel of the third pixel.

[0176] According to one or more embodiments of the present invention, it may include a first gate line to which the first sub-pixel, the second sub-pixel, and the third sub-pixel are connected, and a second gate line to which the second sub-pixel, the second sub-pixel, and the third sub-pixel are connected.

[0177] According to one or more embodiments of the present invention, the first sub-pixel to the third sub-pixel each include an anode electrode and a cathode electrode for applying a voltage to a light-emitting element, the anode electrodes of the first sub-pixel to the third sub-pixel are separated from each other, and the cathode electrodes of the first sub-pixel to the third sub-pixel may be separated from each other.

[0178] According to one or more embodiments of the present invention, the compensation circuit of the first sub-pixel and the compensation circuit of the second sub-pixel may have the same structure.

[0179] According to one or more embodiments of the present invention, a plurality of pixels includes a plurality of first pixels arranged in a first pixel line; and a plurality of second pixels arranged in a second pixel line adjacent to the first pixel line. The second-1 sub-pixel of the first pixel includes a first low-potential power supply line connected to a first cathode electrode. The second-1 sub-pixel of the second pixel includes a second low-potential power supply line connected to a second cathode electrode. The first low-potential power supply line extends toward the second cathode electrode, and the second low-potential power supply line extends toward the first cathode electrode. The first low-potential power supply line and the second low-potential power supply line may be electrically connected.

[0180] According to one or more embodiments of the present invention, in the second-1 sub-pixel of the first pixel, the first low-potential power supply line may be electrically connected to a compensation circuit of the second-1 sub-pixel of the second pixel.

[0181] According to one or more embodiments of the present invention, the first compensation circuit of the first-1 sub-pixel is connected between a data line and a low-potential line, and the second compensation circuit of the first-2 sub-pixel may be connected between the data line and the low-potential line.

[0182] A display device according to an embodiment of the present invention includes a display panel including a plurality of pixels, a gate line and a data line connected to the plurality of pixels; a gate driving unit connected to the gate line; and a data driving unit connected to the data line. The plurality of pixels include a first-1 sub-pixel and a first-2 sub-pixel of a first color; a second-1 sub-pixel and a second-2 sub-pixel of a second color; and a third-1 sub-pixel and a third-2 sub-pixel of a third color. The second-1 sub-pixel and the second-2 sub-pixel each include a light-emitting element and a compensation circuit. The compensation circuit of the second-1 sub-pixel and the compensation circuit of the second-2 sub-pixel are connected to one data line.

[0183] According to one or more embodiments of the present invention, the first-1 sub-pixel may include a first compensation circuit connected to a first data line, and the first-2 sub-pixel may include a second compensation circuit connected to a second data line.

[0184] According to one or more embodiments of the present invention, the third-1 sub-pixel and the third-2 sub-pixel each include a compensation circuit, and the compensation circuits of the third-1 sub-pixel and the third-2 sub-pixel may be connected to one data line.

[0185] According to one or more embodiments of the present invention, the first color may be red, the second color may be green, and the third color may be blue.

[0186] According to one or more embodiments of the present invention, when a data voltage is applied, the plurality of pixels may include a first pixel in which both the second-1 sub-pixel and the second-2 sub-pixel emit light, and a second pixel in which only one of the second-1 sub-pixel and the second-2 sub-pixel emits light when the data voltage is applied.

[0187] According to one or more embodiments of the present invention, the data voltage applied to the second-1 sub-pixel and the second-2 sub-pixel of the second pixel may be greater than the data voltage applied to the second-1 sub-pixel and the second-2 sub-pixel of the first pixel.

[0188] The display device according to an embodiment of the present invention is applicable to mobile devices, video telephones, smart watches, watch phones, wearable apparatuses, foldable apparatuses, rollable apparatuses, bendable apparatuses, flexible apparatuses, curved apparatuses, sliding apparatuses, variable apparatuses, electronic notebooks, electronic books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop personal computers, laptop personal computers, netbook computers, workstations, navigations, in-vehicle navigations, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, game devices, notebook computers, monitors, cameras, camcorders, and home appliances, etc.

[0189] The present invention described above is not limited to the foregoing embodiments and the accompanying drawings, and it will be apparent to those of ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical idea of the present invention. Therefore, the scope of the present invention is indicated by the claims described below, and any changes or modified forms derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention.

Description of Reference Numerals

[0190] R1: First red sub-pixel R2: Second red sub-pixel G1: First green sub-pixel G2: Second green sub-pixel B1: First blue sub-pixel B2: Second blue sub-pixel

Claims

1. A plurality of pixels, a gate line and a data line connected to the plurality of pixels, and the plurality of pixels include a first-1 sub-pixel and a first-2 sub-pixel of a first color, a second-1 sub-pixel and a second-2 sub-pixel of a second color, and a third-1 sub-pixel and a third-2 sub-pixel of a third color, the second-1 sub-pixel and the second-2 sub-pixel each include a light-emitting element and a compensation circuit, a display panel in which the compensation circuit of the second-1 sub-pixel and the compensation circuit of the second-2 sub-pixel are connected to one data line.

2. The first-1 sub-pixel includes a first compensation circuit connected to a first data line, The display panel according to claim 1, wherein the first-2 sub-pixel includes a second compensation circuit connected to a second data line.

3. The third-1 sub-pixel and the third-2 sub-pixel each include a compensation circuit, The display panel according to claim 1, wherein the compensation circuits of the third-1 sub-pixel and the third-2 sub-pixel are connected to one data line.

4. The first color is red, The second color is green, The display panel according to claim 1, wherein the third color is blue.

5. The plurality of pixels include a first pixel in which when a data voltage is applied, all of the second-1 sub-pixel and the second-2 sub-pixel emit light, and a second pixel in which when the data voltage is applied, only one of the second-1 sub-pixel and the second-2 sub-pixel emits light, of the display panel according to claim 1.

6. The data voltage applied to the second-1 sub-pixel and the second-2 sub-pixel of the second pixel is greater than the data voltage applied to the second-1 sub-pixel and the second-2 sub-pixel of the first pixel, of the display panel according to claim 5.

7. The plurality of pixels include a third pixel in which when a data voltage is applied, all of the third-1 sub-pixel and the third-2 sub-pixel emit light, and a fourth pixel in which when the data voltage is applied, only one of the third-1 sub-pixel and the third-2 sub-pixel emits light, of the display panel according to claim 5.

8. The data voltages applied to the 3-1st sub-pixel and the 3-2nd sub-pixel of the 4th pixel are greater than the data voltages applied to the 3-1st sub-pixel and the 3-2nd sub-pixel of the 3rd pixel. The display panel according to claim 7.

9. A first gate line to which the 1-1st sub-pixel, the 2-1st sub-pixel, and the 3-1st sub-pixel are connected, and The display panel according to claim 1, including a second gate line to which the 1-2nd sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel are connected.

10. The 1-1st sub-pixel to the 3-2nd sub-pixel each include an anode electrode and a cathode electrode for applying a voltage to a light-emitting element, The anode electrodes of the 1-1st sub-pixel to the 3-2nd sub-pixel are separated from each other, The display panel according to claim 1, wherein the cathode electrodes of the 1-1st sub-pixel to the 3-2nd sub-pixel are separated from each other.

11. The compensation circuit of the 2-1st sub-pixel and the compensation circuit of the 2-2nd sub-pixel have the same structure. The display panel according to claim 1.

12. The plurality of pixels are A plurality of first pixels arranged on a first pixel line; and Including a plurality of second pixels arranged on a second pixel line adjacent to the first pixel line, The 2-1st sub-pixel of the first pixel includes a first low-potential power supply wiring connected to the first cathode electrode of the 2-1st sub-pixel of the first pixel, The 2-1st sub-pixel of the second pixel includes a second low-potential power supply wiring connected to the second cathode electrode of the 2-1st sub-pixel of the second pixel, The first low-potential power supply wiring extends toward the second cathode electrode, The second low-potential power supply wiring extends toward the first cathode electrode, The display panel according to claim 1, wherein the first low-potential power supply wiring and the second low-potential power supply wiring are electrically connected to each other.

13. The 2-1st sub-pixel of the second pixel is such that the first low-potential power supply wiring is electrically connected to the compensation circuit of the 2-1st sub-pixel of the first pixel. The display panel according to claim 12.

14. The first compensation circuit of the 1-1st sub-pixel is connected between the first data line and the first low-potential line, The second compensation circuit of the first to second sub-pixels is connected between the second data line and the second low potential wiring, and the display panel according to claim 2.

15. A display panel including a plurality of pixels, a gate line and a data line connected to the plurality of pixels, A gate driving unit connected to the gate line, A data driving unit connected to the data line, and including, Each of the plurality of pixels, A first to first sub-pixel and a first to second sub-pixel of the first color, A second to first sub-pixel and a second to second sub-pixel of the second color, and, A third to first sub-pixel and a third to second sub-pixel of the third color, including, The second to first sub-pixel and the second to second sub-pixel each include a light emitting element and a compensation circuit, The compensation circuit of the second to first sub-pixel and the compensation circuit of the second to second sub-pixel are connected to one data line, and a display device.

16. The first to first sub-pixel includes a first compensation circuit connected to the first data line, The display device according to claim 15, wherein the first to second sub-pixel includes a second compensation circuit connected to the second data line.

17. The third to first sub-pixel and the third to second sub-pixel each include a compensation circuit, The display device according to claim 15, wherein the compensation circuits of the third to first sub-pixel and the third to second sub-pixel are connected to one data line.

18. The first color is red, The second color is green, The display device according to claim 15, wherein the third color is blue.

19. The plurality of pixels, When a data voltage is applied, a first pixel in which all of the second to first sub-pixels and the second to second sub-pixels emit light, and, The display device according to claim 15, including a second pixel in which only any one of the second to first sub-pixels and the second to second sub-pixels emits light when the data voltage is applied.

20. The data voltage applied to the second to first sub-pixel and the second to second sub-pixel of the second pixel is larger than the data voltage applied to the second to first sub-pixel and the second to second sub-pixel of the first pixel, and the display device according to claim 19.

Images