Storage system

Abstract

To improve write performance from a host in a storage system.SOLUTION: A storage system includes a controller and a network interface device connected to the controller. The network interface device receives an access request from a host, converts the access request into an access request interpretable by the controller, and issues the access request to the controller. In processing a data write request from the host, the network interface transmits a message for an instruction to start transmitting target data to the host, and then allocates a buffer that temporarily stores the target data, stores the target data received from the host in the buffer, and transfers the target data stored in the buffer to the controller.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a storage system.

Background Art

[0002] With the development of computer systems, new protocols and functions have come to be used, and storage systems for storing data are also required to support them. Moreover, today's storage systems are required to quickly support these new protocols and functions that keep emerging.

[0003] On the other hand, in order to achieve high reliability and availability in a storage system for storing data, special hardware and software different from those for general computer systems may be used to prepare for various failures. In adding protocols and functions in such a storage system, it is difficult to use software assuming the configuration of a general computer system, and since development for a system with a special configuration is required, it is difficult to quickly respond.

[0004] As a technology for solving these problems, a storage system using a SmartNIC is disclosed in Patent Document 1. A SmartNIC has hardware such as a CPU and memory capable of executing a program on a network card and system software, and it is possible to add a user program for packet processing.

[0005] By adding a SmartNIC to a storage system and implementing software on the added SmartNIC to share part of the processing performed by a storage controller, it is possible to support new protocols and functions without changing the configuration of the storage system or the hardware and software of the controller that controls it. Also, if it is possible to use existing software created for general computer systems on the SmartNIC, the period required for development can be further shortened, and thus the response period to new protocols and functions can be shortened.

[0006] When adding a SmartNIC to a storage system to share the processing of the controller, it is a problem that the hardware performance is lower than that of the controller itself. In Patent Document 1, for the purpose of accelerating the front-end processing in a storage using a SmartNIC, a technique is disclosed to prevent the buffer secured in the memory on the SmartNIC from overflowing from the CPU cache and avoid access to the slow memory.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] When a SmartNIC that performs the front-end processing of a storage system receives a Write request from a host, it is necessary to secure a buffer for temporarily storing the Write data on the memory of the SmartNIC. If the secured buffer is stored in the cache of the CPU mounted on the SmartNIC, the reading and writing of the data on the buffer are performed without involving slow memory access.

[0009] However, when receiving a large number of continuous Write requests from the host, the buffer cannot be completely stored in the cache of the CPU on the SmartNIC, and access to the slow memory occurs. As a result, the transfer of the Write data sent from the host to the storage controller is delayed, and the problem is that the Write performance deteriorates. In many cases, the SmartNIC has lower hardware performance than the controller itself, and the influence of the Write performance degradation due to the CPU cache miss is likely to be greater.

[0010] When the program of the front-end processing executed by the CPU mounted on the SmartNIC receives a Write request from the host, it secures a buffer on the memory of the SmartNIC according to the size of the data to be written. For example, after software that performs front-end processing of storage receives a Write request from the host, it can secure a buffer and then instruct the host to transmit the data to be written.

[0011] In this processing method, when the data to be written arrives from the host, the data can be immediately stored in the already-secured buffer. On the other hand, since the buffer continues to be secured while waiting for the data to be written to arrive from the host, the buffer capacity to be secured increases in proportion to the number of Write requests being processed simultaneously.

[0012] As a result, when the total capacity of the buffer exceeds the capacity that can be stored in the CPU cache, access to the slow memory occurs, leading to a decrease in Write performance. Also, as the network delay between the host and the SmartNIC increases, the waiting time for data arrival from the host increases, so more buffers are secured simultaneously, making it easier for the Write performance to decrease.

Means for Solving the Problem

[0013] A storage system according to one aspect of the present invention includes a controller and a network interface device connected to the controller. The network interface device receives an access request from a host, converts the access request into an access request interpretable by the controller, and issues it to the controller. In processing a write request for data from the host, after the network interface transmits a message instructing the start of transmission of the data to be written to the host, the network interface secures a buffer for temporarily storing the data to be written, stores the data to be written received from the host in the buffer, and transfers the data to be written stored in the buffer to the controller.

Advantages of the Invention

[0014] According to one aspect of the present invention, it is possible to improve the write performance in a storage system.

[0015] Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0016]

Fig. 1

Fig. 2

Fig. 3

Fig. 4

Fig. 5A

Fig. 5B

Fig. 5C

Fig. 6

Fig. 7

Fig. 8

Mode for Carrying Out the Invention

[0017] In the following, for convenience, when necessary, it will be divided into multiple sections or examples for explanation. However, unless otherwise specified, they are not unrelated to each other. One is related to a partial or total modification example, details, supplementary explanation, etc. of the other. Also, in the following, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and in cases where it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number.

[0018] One embodiment of this specification improves the write performance from a host to a storage in a storage system that executes front - end processing for access requests from a host by an interface device outside a controller such as a network card.

[0019] In one embodiment of this specification, the front-end processing of the storage system executed by the interface device instructs the host to start transmitting the data to be written before securing a buffer when receiving a Write request from the host. Thereby, by shortening the buffer securing time for each Write request and simultaneously reducing the total capacity of the buffer to be secured, an increase in cache misses of the processor in the interface device can be suppressed and the Write performance can be improved.

[0020] One embodiment of this specification may secure a buffer upon receiving a response from the host in response to the instruction to start transmitting the data to be written. Thereby, the Write performance can be improved more effectively.

[0021] One embodiment of this specification may secure a buffer upon the arrival of the data to be written from the host to the interface device, and temporarily store the received data to be written. By delaying the timing of securing the buffer until the arrival of the data to be written in the front-end processing, the Write performance can be improved more effectively.

[0022] One embodiment of this specification may prepare in advance a memory area to be used as a buffer for securing at the arrival of the data to be written in the front-end processing executed by the interface device, such that the total capacity is within the cache capacity of the processor mounted on the interface device. By preparing a memory area for the buffer, the range of the memory area of the buffer to be secured during the processing of the Write request can be fixed, and the occurrence of cache misses of the processor can be suppressed.

[0023] Furthermore, in one embodiment of the present specification, in the front-end processing that operates in the interface device, when there is a shortage of memory area upon arrival of data to be written, a spare buffer area may be secured and used. This suppresses the occurrence of buffer securing failures and timeouts due to waiting for buffer securing. Securing of the spare buffer area may be limited only when the memory area prepared for the buffer is insufficient. This reduces the frequency of use of areas other than the pre-prepared memory area as buffers, prevents expansion of the range of memory areas used as buffers, and suppresses the occurrence of cache misses in the processor.

[0024] The above description is applicable not only to an interface device whose functions can be programmed by software executed by a processor, but also to an interface device with a programmable logic circuit configuration such as an FPGA (Field Programmable Gate Array). The FPGA may include logic circuits that realize each function implemented by a program and cache memory used in calculations.

[0025] Hereinafter, in a storage system that performs front-end processing for access requests from a host in a SmartNIC, an embodiment of processing access requests from a host will be described. A SmartNIC is a high-performance network card that can program (add) functions desired by a user by software or hardware, and is a front-end interface device. The SmartNIC can execute functions of an application layer above the transport layer, for example. Note that this embodiment does not limit the scope of the claims in the present invention, and not all elements described in the embodiment are necessarily required to solve the problems in the present invention.

[0026] FIG. 1 is a diagram showing a configuration example of a storage system and a host that makes an access request to the storage system in one embodiment of the present specification. The storage system 100 includes a SmartNIC 101, a controller 102, and a storage medium 103. The storage system is connected to the front-end network 104 through the SmartNIC 101 to provide access to an external host 105. The storage system 100 and the host 105 are connected via the front-end network 104, and the host 105 makes an access request to the storage system 100.

[0027] The SmartNIC 101 is a network interface for connecting the storage system 100 to the front-end network 104, and performs front-end processing of an access request from the host 105 to the storage system 100. When the SmartNIC 101 receives an access request from the host 105 to the storage system 100 through the front-end network 104, it interprets the content of the access request and converts it into a form that can be interpreted by the controller 102. Then, the SmartNIC 101 notifies the controller 102 of the converted access request and responds to the host 105 with the result of the access request. In addition, the SmartNIC 101 transfers data requested to be read or written from the host 105 between itself and the controller 102.

[0028] The controller 102 receives the access request from the host 105 interpreted by the SmartNIC 101, and reads or writes the corresponding area of the storage medium 103 for the data for which access is requested. The storage medium 103 is connected to the controller 102 and provides a storage area of the storage system 100. The storage medium 103 may be mounted inside the housing of the storage system 100, or may be connected to the controller 102 via an external network. The storage medium 103 can include, for example, one or more storage drives, and examples of storage drives are hard disk drives, solid state drives, and the like.

[0029] The front-end network 104 connects the SmartNIC 101 and the host 105, and provides an access path from the host 105 to the storage system 100. The host 105 makes an access request to the storage area of the storage system 100 provided by the SmartNIC 101, the controller 102, and the storage medium 103.

[0030] Note that there may be a plurality of SmartNIC 101, controller 102, storage medium 103 included in the storage system 100, and host 105 that accesses the storage system, respectively.

[0031] Also, in the configuration of FIG. 1, the connection between the controller 102 and the SmartNIC 101, and the connection between the controller 102 and the storage medium 103 are not included in the front-end network 104, but a configuration in which one or both of these are included in the front-end network 104 may be used.

[0032] FIG. 2 is a diagram showing a configuration example of the SmartNIC 101 in an embodiment of this specification. The SmartNIC 101 has one or more network interfaces (I / F) 201, one or more controller connection I / Fs 202, one or more processors 203, one or more memories 204, and one or more internal switches 205.

[0033] The network I / F 201 is connected to the front-end network 104 and is used for transmitting and receiving data related to access requests from the host 105.

[0034] The controller connection I / F 202 connects between the SmartNIC 101 and the controller 102, and is used for notifying an access request from the SmartNIC 101 to the controller 102, and transmitting and receiving data for performing Read or Write.

[0035] The processor 203 can include one or more cores and executes a program for performing front-end processing of access requests to the storage system from the host 105 and system software necessary for its execution.

[0036] The memory 204 stores system software including an operating system necessary for operating a program on the SmartNIC 101, a program operating on the processor 203, metadata used by the program, and data that needs to be temporarily stored. The data stored in the memory 204 is stored in the cache memory 231 of the processor 203, and when there is a cache hit, the data stored therein can be referenced and updated without accessing the memory 204. The cache memory 231 is a memory that can be accessed more quickly than the memory 204 and its buffer area by hardware for performing operations, here the processor 203. The cache memory 231 can be composed of one or more levels.

[0037] The internal switch 205 connects the network I / F 201, the controller connection I / F 202, and the processor 203.

[0038] The communication standards and protocols in the network I / F 201 and the controller connection I / F 202 are not particularly limited as long as the above operations are possible. Also, the transmission and reception of data among the network I / F 201, the controller connection I / F 202, and the processor 203 are not limited to the configuration via the internal switch 205. For example, the network I / F 201 and the controller connection I / F 202 may be directly connected to the processor 203.

[0039] FIG. 3 is a diagram showing a configuration example of the data stored in the memory 204 included in the SmartNIC 101 in one embodiment of this specification. The memory 204 has a system software area 301, a front-end processing program area 302, a packet buffer area 303, a user buffer area 304, a spare buffer area 305, and a metadata area 306.

[0040] In the system software area 301, system software such as an operating system, a driver, and a library necessary for operating a user program such as front-end processing of a storage system in the processor 203 is stored.

[0041] In the front-end processing program area 302, a front-end processing program for performing front-end processing executed on the processor 203 is stored.

[0042] The packet buffer area 303 is an area managed by the OS, and data of network packets received from the host 105 via the network I / F 201 is temporarily stored.

[0043] The user buffer area 304 is a memory area secured and used by the front-end processing program, and data requested by the host 105 for Write is temporarily stored. The user buffer area 304 secured and used by the front-end processing program is limited by a predetermined maximum capacity in order to reduce accesses to the memory 204 due to cache misses. In one embodiment of the present specification, the total capacity of the user buffer area 304 is limited so as to fit in the cache memory.

[0044] The spare buffer area 305 is a memory area secured and used by the front-end processing program, and is secured as a buffer by the front-end processing program when buffer securing from the user buffer area 304 fails due to insufficient capacity. Unlike the user buffer area 304, the spare buffer area 305 does not have a limit on the secured capacity of the buffer based on the cache capacity of the processor 203, and the front-end processing program secures an area larger than the maximum capacity used in processing access requests from the host 105 as the spare buffer area 305.

[0045] The metadata area 306 is a memory area used by the front-end processing program, and stores the metadata necessary for front-end processing.

[0046] Figure 4 is a diagram showing a configuration example of stored data included in the metadata area 306 of the memory 204 in an embodiment of this specification. For each access request, the metadata area 306 stores an access request number 401, access request information 402, a used buffer address 403, and a used buffer size 404. The metadata area 306 also stores the total buffer allocation capacity 405 and the maximum buffer allocation capacity 406.

[0047] The access request number 401 is a unique number assigned for each access request to distinguish the access requests received from the host 105.

[0048] The access request information 402 represents the content of the access request received from the host 105, and includes information such as the access type indicating either Read or Write, the address of the data to be accessed, the size, and the address uniquely representing the host 105 that is the source of the access request.

[0049] The used buffer address 403 represents the address of the user buffer area 304 or the spare buffer area 305 allocated in the processing of each access request.

[0050] The used buffer size 404 represents the capacity of the buffer allocated from the user buffer area 304 or the spare buffer area 305 in the processing of each access request.

[0051] The total buffer allocation capacity 405 represents the total capacity of the buffers included in the user buffer area 304 secured by the front-end processing program in the processing of access requests.

[0052] The maximum buffer allocation capacity 406 represents the maximum capacity of the buffer that the front-end processing program is allowed to allocate from the user buffer area 304. The maximum buffer allocation capacity 406 is set in advance so that the capacity of the buffer allocated from the user buffer area 304 is within the cache capacity of the processor 203, in order to prevent cache misses in the processor 203 and write operations of data overflowing from the cache, which cause an increase in access to the memory 204. In a configuration where multiple processors are implemented, the cache capacity may be the total cache capacity of those processors.

[0053] When allocating a buffer, the front-end processing program compares the total buffer allocation capacity 405 with the maximum buffer allocation capacity 406, and allocates a buffer with a capacity that does not exceed the maximum buffer allocation capacity 406 from the memory area in the user buffer area 304. Thereby, the memory area used as the buffer continues to stay in the cache memory area, and it is possible to suppress a performance degradation caused by data overflowing from the cache memory area.

[0054] On the other hand, when the front-end processing program allocates a buffer and the total buffer allocation capacity 405 exceeds the maximum buffer allocation capacity 406, the buffer allocated by the preceding Write request is released, and it is necessary to wait until the total buffer allocation capacity 405 after buffer allocation does not exceed the maximum buffer allocation capacity 406.

[0055] At this time, if the release of the buffer is delayed due to the time required for the processing of the preceding Write request, the processing time of the Write request waiting for buffer allocation increases and exceeds the response time allowed by the host side, resulting in a timeout. The occurrence of a timeout may lead to errors or failures in the processing operating on the host side. Therefore, only when the total buffer allocation capacity 405 exceeds the maximum buffer allocation capacity 406, the front-end processing program temporarily allocates a buffer from the temporary buffer area 305 to prevent the occurrence of waiting in buffer allocation.

[0056] At this time, in addition to the user buffer area 304, the front-end processing program also secures a buffer from the spare buffer area 305. As a result, performance degradation occurs due to the data of the temporarily secured buffer overflowing from the cache of the processor 203. However, securing a buffer from the spare buffer area 305 is limited to the case where the total buffer securing capacity 405 exceeds the maximum buffer securing capacity 406. When the buffer is released and the total buffer securing capacity 405 decreases, the front-end processing program again secures a buffer only from the user buffer area 304, so the frequency of performance degradation can be suppressed.

[0057] The stored data in the metadata area 306 is not limited to the configuration shown in FIG. 4. For example, the access request number 401 may not be a number but a character string or the like that can uniquely identify an access request. When allocating a buffer so that the size of the buffer secured in the user buffer area 304 or the spare buffer area 305 can be determined by the used buffer address 403 corresponding to each access request, the used buffer size 404 may be omitted. The maximum buffer securing capacity 406 may be set so that, for example, in addition to the capacity of the buffer secured from the user buffer area 304, the capacity obtained by adding, for example, program code with a high reference frequency in the front-end processing program and the capacity of the metadata is within the cache capacity of the processor 203.

[0058] FIGS. 5A to 5C are flowcharts showing the flow of processing a Write request from the host 105 to the storage system by the SmartNIC 101 and the controller 102 in an embodiment of the present specification. FIG. 6 is a diagram showing the period during which a buffer is secured when processing a Write request from the host 105 according to the flowcharts shown in FIGS. 5A to 5C. The operations based on the flowcharts in FIGS. 5A to 5C are as follows.

[0059] First, refer to FIG. 5A. Step 501: The front-end processing program running on the processor 203 of the SmartNIC 101 receives a Write request from the host 105 through the network I / F 201, converts it into a format interpretable by the controller 102, and then proceeds to step 502.

[0060] Step 502: The front-end processing program running on the processor 203 of the SmartNIC 101 assigns an access request number 401 to the Write request received in step 501 and registers it in the metadata area 306 of the memory 204 together with the access request information 402 regarding the received Write request, and then proceeds to step 503.

[0061] Step 503: The front-end processing program running on the processor 203 of the SmartNIC 101 requests a Write by notifying the controller 102 of the information converted in step 501, and then proceeds to step 504.

[0062] Step 504: When the controller 102 receives a Write request from the SmartNIC 101, it secures a cache area on the controller 102 for storing the data to be written from the host 105 to the storage system. After the securing of the above cache area is completed, the controller 102 instructs the SmartNIC 101 to start transmitting the data to be written by sending a message to it, and then proceeds to step 505. (Hereinafter, in this specification, the message instructing the start of transmission of the data to be written is described as R2T: Ready To Transfer.)

[0063] Step 505: When the front-end processing program running on the processor 203 of the SmartNIC 101 receives the R2T from the controller 102 through the controller connection I / F 202, it instructs the start of transmission of the data to be written by sending an R2T message to the host 105 through the network I / F 201, and then proceeds to step 506.

[0064] Step 506: The front-end processing program running on the processor 203 of SmartNIC 101 waits until it receives the data to be written from the host 105. When the host 105 receives the R2T message from SmartNIC 101, it sends the data to be written to SmartNIC 101 and then proceeds to step 507.

[0065] Step 507: When the network I / F 201 of SmartNIC 101 and the system software running on the processor 203 receive a packet containing the data to be written from the host 105, they store the data contained in the packet in the packet buffer area 303 of the memory 204 and then proceed to step 508.

[0066] Next, refer to FIG. 5B. Step 508: When the front-end processing program running on the processor 203 of SmartNIC 101 receives a packet containing the data to be written from the host 105 in step 507 and detects that the data has been stored in the packet buffer area 303, it refers to the access request information 402, the total buffer allocation capacity 405, and the maximum buffer allocation capacity 406 included in the metadata area 306 of the memory 204, and checks whether the total buffer allocation capacity 405 exceeds the maximum buffer allocation capacity 406 when a buffer for storing the data to be written is allocated from the user buffer area 304, and then proceeds to step 509.

[0067] Step 509: Depending on the result of the check in step 508, if the total buffer allocation capacity 405 does not exceed the maximum buffer allocation capacity 406, the front-end processing program running on the processor 203 of SmartNIC 101 proceeds to step 510; if it exceeds, it proceeds to step 511.

[0068] Step 510: The front-end processing program running on the processor 203 of the SmartNIC 101 secures a buffer for storing the data to be written from the user buffer area 304, stores the used buffer address 403 corresponding to the write request being processed, the address of the secured buffer, and the capacity in the metadata area 306 of the memory 204 into the used buffer size 404, and updates by adding the capacity of the secured buffer to the total buffer securing capacity 405, and then proceeds to step 512.

[0069] Step 511: The front-end processing program running on the processor 203 of the SmartNIC 101 secures a buffer for storing the data to be written from the spare buffer area 305, stores the used buffer address 403 corresponding to the write request being processed, the address of the secured buffer, and the capacity in the metadata area 306 of the memory 204, and then proceeds to step 512.

[0070] Step 512: The front-end processing program running on the processor 203 of the SmartNIC 101 copies the data to be written stored in the packet buffer area 303 into the buffer secured in step 510 or step 511, and then proceeds to step 513.

[0071] Step 513: The front-end processing program running on the processor 203 of the SmartNIC 101 transfers the data to be written copied in step 512 to the controller 102 through the controller connection I / F 202, and then proceeds to step 514. The data transfer in this step can be realized, for example, by using DMA transfer for the buffer secured by the front-end processing program when the SmartNIC 101 is connected to the controller 102 by PCI-Express (trademark), but the means is not limited.

[0072] Step 514: When the front-end processing program being executed by the processor 203 of the SmartNIC 101 completes the transfer of the data to be written to the controller 102, it releases the buffer secured in step 510 or step 511, and then proceeds to step 515.

[0073] Next, refer to FIG. 5C. Step 515: The front-end processing program being executed by the processor 203 of the SmartNIC 101 checks whether the buffer released in step 514 was secured from the user buffer area 304 or the reserve buffer area 305, and then proceeds to step 516. The check of the area containing the released buffer in this step can be realized, for example, by referring to the used buffer address 403 included in the metadata area 306, but the means is not limited.

[0074] Step 516: If the buffer released in step 514 was secured from the user buffer area 304, the front-end processing program being executed by the processor 203 of the SmartNIC 101 proceeds to step 517; if it was secured from the reserve buffer area 305, it proceeds to step 518.

[0075] Step 517: The front-end processing program being executed by the processor 203 of the SmartNIC 101 updates by subtracting the capacity of the released buffer from the total buffer allocation capacity 405 included in the metadata area 306, and then proceeds to step 518.

[0076] Step 518: The front-end processing program being executed by the processor 203 of the SmartNIC 101 identifies the host that made the Write request being processed by referring to the access request information 402 included in the metadata area 306, notifies the completion of the Write request through the network I / F 201, and then proceeds to step 519.

[0077] Step 519: The front-end processing program being executed by the processor 203 of the SmartNIC 101 deletes the access request number 401, access request information 402, used buffer address 403, and used buffer size 404 corresponding to the Write request to be processed from the metadata area 306, and ends a series of operations.

[0078] The completion notification of the Write request to the host 105 in step 518 of the flowchart in FIG. 5C may be performed at any time after the transfer completion of the Write target data to the controller 102 in step 513 and before the execution of step 519. Also, the timing at which the controller 102 stores the Write target data transferred from the SmartNIC 101 in step 513 in the storage medium 103 is not limited and may be performed at any time.

[0079] Also, when the host 105 sends a response (R2T ACK) to R2T before sending the Write target data to the SmartNIC 101 after receiving the R2T message from the SmartNIC 101 in step 506 of the flowchart in FIG. 5A, the front-end processing program being executed by the processor 203 of the SmartNIC 101 may perform the processing from step 508 to step 509 upon receiving the R2T ACK message from the host 105.

[0080] At this time, the network I / F 201 performs the processing in step 507 before step 512 upon receiving the Write target data from the host 105, and the front-end program performs the operations after step 512 upon storing the Write target data in the packet buffer area 303 in step 507.

[0081] As described above, Fig. 6 shows an embodiment of this specification, and is a diagram showing a period during which a buffer is reserved when processing a write request from host 105 according to the flowcharts shown in Figs. 5A to 5C. Fig. 7 shows an embodiment of this specification, and is a diagram showing a period during which a buffer is reserved in step 552 in response to reception of an R2T ACK message transmitted from host 105 before the data to be written in step 551 in the flowcharts shown in Figs. 5A to 5C.

[0082] FIG. 8 illustrates a related technique, and, unlike the flowcharts illustrated in FIGS. 5A to 5C, shows the period during which a buffer is reserved in step 551 for storing data to be written before sending an R2T message to host 105 in step 505.

[0083] First, comparing FIG. 6 with FIG. 8, when a write request is processed according to the flowcharts shown in FIG. 5A to FIG. 5C, the time from buffer allocation to release is shortened by allocating a buffer after receiving the data to be written from the host 105.

[0084] 7 and 8, even in the case where buffer allocation is triggered by receiving an R2T ACK message, the buffer allocation time corresponding to sending an R2T message from SmartNIC 101 to host 105 and receiving an R2T ACK message from host 105 is shortened. Therefore, when continuous write requests are made from host 105, the total capacity of the buffers allocated at the same time decreases, reducing the frequency with which buffer data overflows from the cache of processor 203, and making it possible to improve write throughput for the storage system.

[0085] According to an embodiment of the present specification, in a storage system that performs front-end processing for access requests from a host using a SmartNIC, it is possible to prevent the data in the buffer secured in association with a Write request from the host from overflowing from the cache of the processor on the SmartNIC, and improve the Write throughput for the storage system.

[0086] Note that the present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can also be added to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations is possible.

[0087] Also, each of the above configurations, functions, processing units, etc. may be realized in hardware, for example, by designing a part or all of them with an integrated circuit. Further, each of the above configurations, functions, etc. may be realized in software by a processor interpreting and executing a program for realizing each function. Information such as a program, table, file, etc. for realizing each function can be placed in a memory, a recording device such as a hard disk, SSD (Solid State Drive), or a recording medium such as an IC card, SD card.

[0088] Also, control lines and information lines show those considered necessary for explanation, and not necessarily all control lines and information lines are shown on the product. In practice, it may be considered that almost all configurations are interconnected.

Explanation of Reference Numerals

[0089] 101…SmartNIC, 102…Controller, 103…Memory Medium, 104…Front-End Network, 105…Host, 201…Network I / F, 202…Controller Connection I / F, 203…Processor, 204…Memory, 205…Internal Switch, 301…System Software Area, 302…Front-End Processing Program Area, 303…Packet Buffer Area, 304…User Buffer Area, 305…Reserved Buffer Area, 306…Metadata Area, 401…Access Request Number, 402…Access Request Information, 403…Used Buffer Address, 404…Used Buffer Size, 405…Total Buffer Allocation Capacity, 406…Maximum Buffer Allocation Capacity

Claims

1. A controller, and a network interface device connected to the controller, wherein the network interface device receives an access request from a host, the network interface device converts the access request into an access request interpretable by the controller and issues the access request to the controller, in processing a write request for data from the host, the network interface device after sending a message instructing the start of transmission of write target data to the host, secures a buffer for temporarily storing the write target data, stores the write target data received from the host in the buffer, and transfers the write target data stored in the buffer to the controller, a storage system.

2. The storage system according to claim 1, wherein the network interface device secures a buffer for temporarily storing the write target data upon receiving the write target data from the host.

3. The storage system according to claim 1, wherein the network interface device secures a buffer for temporarily storing the write target data upon receiving a response from the host to the message.

4. The storage system according to claim 1, wherein the network interface device includes a processor that converts the access request into an access request interpretable by the controller and issues the access request to the controller, and a cache of the processor, and the total buffer capacity secured for temporarily storing write target data from the host is limited to fit within the cache.

5. The storage system according to claim 1, wherein the network interface device allocates a pre-secured spare memory area when the total buffer capacity secured for temporarily storing write target data from the host exceeds a preset maximum capacity.

6. The storage system according to claim 1, wherein the network interface device has a programmable implementation function.

7. A method executed in a storage system, wherein the storage system includes a network interface device connected to a controller, and the method comprises: the network interface device receiving an access request from a host, converting the access request into an access request interpretable by the controller and issuing the access request to the controller, in processing a write request for data from the host, after sending a message instructing the start of transmission of write target data to the host, securing a buffer for temporarily storing the write target data, storing the write target data received from the host in the buffer, and transferring the write target data stored in the buffer to the controller. **Claim 8** The method according to claim 7, wherein the network interface device secures a buffer for temporarily storing the write target data upon receiving the write target data from the host. **Claim 9** The method according to claim 7, wherein the total buffer capacity secured for temporarily storing the write target data from the host is limited to fit within the processor cache of the network interface device. **Claim 10** The method according to claim 7, wherein when the total buffer capacity secured by the network interface device for temporarily storing the write target data from the host exceeds a preset maximum capacity, an additional pre-secured memory area is allocated.

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