Semiconductor device and electronic apparatus

Abstract

To provide a semiconductor device with a hierarchical artificial neural network being constructed, a semiconductor device with low power consumption, and an electronic apparatus comprising such a semiconductor device.SOLUTION: A hierarchical artificial neural network 100 has a first layer comprising neurons N1(1) to Np(1) (where p is an integer of 1 or greater), a (k-1)th layer comprising neurons N1(k-1) to neuron Nm(k-1) (where m is an integer of 1 or greater), the k-th layer has neurons N1(k) to neuron Nn(k) (where n is an integer of 1 or greater). The R-th layer has neurons N1(R) to Nq(R) (where q is an integer of 1 or greater).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, their driving methods, their manufacturing methods, or their inspection methods.

Background Art

[0003] Currently, the development of integrated circuits that mimic the structure of the human brain is actively underway. The integrated circuit has a circuit structure in which the structure of the brain is incorporated as an electronic circuit, and has circuits corresponding to the "neurons" and "synapses" of the human brain. Therefore, such an integrated circuit is sometimes referred to as a "neuromorphic", "brainomorphic", or "brain-inspired" integrated circuit. The integrated circuit has a non-von Neumann architecture, and is expected to perform parallel processing with extremely low power consumption as compared with the von Neumann architecture in which power consumption increases as the processing speed increases. in which power consumption increases as the processing speed increases.

[0004] A model of information processing that mimics a neural network having "neurons" and "synapses" is an artificial It is called an artificial neural network (ANN). For example, Non-Patent Document 1 and Non-Patent Document 2 disclose an arithmetic unit that uses SRAM (Static Random Access Memory) to construct an artificial neural network.

Prior Art Documents

Non-Patent Documents

[0005]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In an artificial neural network, a calculation is performed by multiplying the connection strength (which may be referred to as a weight coefficient) of a synapse that connects two neurons and the signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, it is necessary to multiply and sum (perform a product-sum operation) the connection strength of each synapse between a plurality of first neurons in the first layer and one of the second neurons in the second layer, and each signal input from the plurality of first neurons in the first layer to one of the second neurons in the second layer. Depending on the scale of the artificial neural network, for example, the number of the connection strengths and the number of parameters indicating the signals are determined. That is, as the number of layers, the number of neurons, etc. of the artificial neural network increase, the number of circuits corresponding to each of "neurons" and "synapses" increases, and the amount of calculation may also become extremely large.

[0007] For example, in the calculation of a neural network, in addition to the product-sum calculation, there is also a calculation of an activation function, etc. In the calculation of the activation function, as the scale of the artificial neural network increases, the power consumption tends to increase.

[0008] One aspect of the present invention is to provide a semiconductor device in which a hierarchical artificial neural network is constructed, etc. Or, one aspect of the present invention is to provide a semiconductor device with low power consumption, etc. Or, one aspect of the present invention is to provide a novel semiconductor device, etc. Or, one aspect of the present invention is to provide an electronic device having the above semiconductor device as one of the problems.

[0009] Note that the problems of one aspect of the present invention are not limited to the above-listed problems. The above-listed problems do not prevent the existence of other problems. Other problems are those not mentioned in this item described below. Problems not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or the drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the above-listed problems and other problems. Note that one aspect of the present invention does not necessarily need to solve all of the above-listed problems and other problems.

Means for Solving the Problems

[0010] (1)​​ One aspect of the present invention has a cell and a first circuit. The first circuit has a first capacitor, a first input terminal, and a second input terminal. The cell is electrically connected to the first input terminal via a first wiring and is electrically connected to the second input terminal via a second wiring. The cell has a function of holding first data, and when second data is input to the cell, a first current corresponding to the first data and the second data flows between the cell and the first wiring, and a second current corresponding to the first data and the second data flows between the cell and the second wiring. The first capacitor has a function of holding a differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current. It is a semiconductor device.

[0011] (2) Alternatively, one aspect of the present invention, in the configuration of (1) above, the first circuit has a second circuit. The second circuit has a function of acquiring a differential voltage and outputting a signal corresponding to the differential voltage. It is a semiconductor device.

[0012] (3) Alternatively, one aspect of the present invention, in the configuration of (2) above, the first circuit has a first current-voltage conversion circuit, a second current-voltage conversion circuit, a first switch, a second switch, a third switch, and a fourth switch. The first input terminal is electrically connected to a first terminal of the first switch and a first terminal of the first current-voltage conversion circuit. A second terminal of the first switch is electrically connected to a first terminal of the second switch and a first terminal of the first capacitor. The second input terminal is electrically connected to a first terminal of the third switch and a first terminal of the second current-voltage conversion circuit. A The second terminal of the fourth switch is electrically connected to the first terminal of the second circuit, and a first current / voltage The conversion circuit converts the first current into a first terminal of the first current-voltage conversion circuit. The second current-voltage conversion circuit has a function of setting the potential of the first terminal of the voltage conversion circuit to a first potential, In response to the second current input to the first terminal of the second current-voltage conversion circuit, The semiconductor device has a function of setting the potential of the first terminal to the second potential.

[0013] (4) Alternatively, in one aspect of the present invention, in the configuration (3) above, the second terminal of the second switch is The first circuit is electrically connected to a third wiring that provides a semi-potential, and includes a first switch and a third switch. The first switch and the fourth switch are turned on, and the second switch and the fourth switch are turned off. a function of setting the first terminal of the first capacitor to a first potential and the second terminal of the first capacitor to a second potential; The third switch and the fourth switch are turned off, and the second switch is turned on. , by changing the first terminal of the first capacitance from the first potential to the reference potential, A function of changing a second potential of a second terminal of a first capacitance to a third potential; a first switch; and a second switch. The second switch and the third switch are turned off, and the fourth switch is turned on. and a function of inputting a third potential corresponding to the differential voltage to the first terminal of the semiconductor device. .

[0014] (5) Alternatively, one aspect of the present invention includes a cell and a first circuit, the first circuit including a first capacitance and a second capacitance. The cell has a first capacitance, a first input terminal, and a second input terminal. The cell is connected to the first capacitance through a first wiring. The cell is electrically connected to the input terminal, and the cell is electrically connected to the second input terminal via the second wiring. and the cell has a function of holding first data, and when second data is input into the cell, a first current corresponding to the first data and the second data flows between the cell and the first wiring, and the cell has a function of flowing a second current corresponding to the first data and the second data between the cell and the second wiring, the first capacitor has a function of holding a first differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current, and the second capacitor has a function of holding a second differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current, which is a semiconductor device.

[0015] (6) Alternatively, in one aspect of the present invention, in the configuration of (5) above, the first circuit has a second circuit and a third circuit, the second circuit has a function of obtaining a first differential voltage based on the potential of the first terminal of the first capacitor and outputting a first signal corresponding to the first differential voltage, and the third circuit has a function of obtaining a second differential voltage based on the potential of the second terminal of the second capacitor and outputting a second signal corresponding to the second differential voltage, which is a semiconductor device.

[0016] (7) Alternatively, in one aspect of the present invention, in the configuration of (6) above, the first circuit has a first current-voltage conversion circuit, a second current-voltage conversion circuit, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch, the first input terminal is electrically connected to the first terminal of the first switch, the first terminal of the fifth switch, and the first terminal of the first current-voltage conversion circuit, the second terminal of the first switch is electrically connected to the first terminal of the second switch and the first terminal of the first capacitor, the second terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the first terminal of the second capacitor, The two input terminals are electrically connected to the first terminal of the third switch, the first terminal of the seventh switch, and the first terminal of the second current-voltage conversion circuit. The second terminal of the third switch is electrically connected to the first terminal of the fourth switch and the second terminal of the first capacitor. The second terminal of the seventh switch is electrically connected to the first terminal of the eighth switch and the second terminal of the second capacitor. The second terminal of the fourth switch is electrically connected to the first terminal of the second circuit. The second terminal of the sixth switch is electrically connected to the first terminal of the third circuit. The first current-voltage conversion circuit has a function of setting the potential of the first terminal of the first current-voltage conversion circuit to a first potential according to the first current input to the first terminal of the first current-voltage conversion circuit. The second current-voltage conversion circuit has a function of setting the potential of the first terminal of the second current-voltage conversion circuit to a second potential according to the second current input to the first terminal of the second current-voltage conversion circuit. It is a semiconductor device.

[0017] (8) Alternatively, in one aspect of the present invention, in the configuration of (7) above, the second terminal of the second switch is electrically connected to a third wiring that provides a reference potential, the second terminal of the eighth switch is electrically connected to the third wiring that provides a reference potential, the first circuit turns on the first switch and the third switch, turns off the second switch and the fourth switch, sets the first terminal of the first capacitor to the first potential, and sets the second terminal of the first capacitor to the second potential. It also turns on the fifth switch and the seventh switch, turns off the sixth switch and the eighth switch, sets the first terminal of the second capacitor to the first potential, and sets the second terminal of the second capacitor to the second potential. It further turns off the first switch, the third switch, and the fourth switch, and turns on the second switch. ​Then, by changing the first terminal of the first capacitance from the first potential to the reference potential, a function of changing the second potential of the second terminal of the first capacitance to a third potential; a fifth switch; The sixth switch and the seventh switch are turned off, and the eighth switch is turned on. By changing the second terminal of the capacitor from the second potential to the reference potential, the first capacitor a function of changing a first potential of a first terminal of the variable resistor to a fourth potential; a first switch; and a second switch. and the third switch is turned off and the fourth switch is turned on to turn on the first switch of the second circuit. a function of inputting a third potential corresponding to the first differential voltage to a terminal; a fifth switch; and a seventh switch and the eighth switch are turned off, and the sixth switch is turned on to turn on the first switch of the third circuit. and a function of inputting a fourth potential corresponding to the second differential voltage to the terminal.

[0018] (9) Alternatively, in one aspect of the present invention, in any one of the configurations (1) to (8) above, the cell , a first cell and a second cell, the first cell being connected to a first wiring, a second wiring, and a first input wiring. The second cell is electrically connected to the first wiring, the second wiring, and the first input wiring. The first input wiring and the second input wiring are electrically connected to each other. Each of them has a function of providing a potential according to the second data, and the first cell is connected to the first input wiring. When a first input potential is input and a second input potential is input to the second input wiring, a first current to the first wiring, and the second input potential is input to the first input wiring and When the first input potential is input, the second current flows through the second wiring, and the second current flows through the first input wiring. When an input potential is input and a second input potential is input to the second input wiring, the first cell and the It has a function of making the state non-conductive between the first cell and the first wiring, and between the first cell and the second wiring, and the second When a first input potential is input to the first input wiring and a second input potential is input to the second input wiring in the second cell, it has a function of flowing a second current to the second wiring, and when a second input potential is input to the first input wiring and a first input potential is input to the second input wiring, it has a function of flowing a first current to the first wiring and when a second input potential is input to the first input wiring and a second input potential is input to the second input wiring in the second cell, it has a function of making the state non-conductive between the second cell and the first wiring, and between the second cell and the second wiring. It is a semiconductor device having such functions.

[0019] (10) Alternatively, in one aspect of the present invention, in the configuration of (9) above, the first cell includes a first transistor , a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, and a third capacitor , and the second cell includes a second transistor, a thirteenth switch, a fourteenth switch , a fifteenth switch, a sixteenth switch, and a fourth capacitor. The first terminal of the first transistor is electrically connected to the first terminal of the ninth switch, the first terminal of the tenth switch, and the first terminal of the eleventh switch. The gate of the first transistor is electrically connected to the first terminal of the third capacitor and the first terminal of the twelfth switch. The second terminal of the ninth switch is electrically connected to the second terminal of the twelfth switch. The second terminal of the tenth switch is electrically connected to the first wiring. The control terminal of the tenth switch is electrically connected to the first input wiring. The second terminal of the eleventh switch is electrically connected to the second wiring. The control terminal of the eleventh switch is electrically connected to the second input wiring. The first terminal of the second transistor is electrically connected to a terminal, a first terminal of a fourteenth switch, and a first terminal of a fifteenth switch. The gate of the second transistor is electrically connected to a first terminal of a fourth capacitor and a first terminal of a sixteenth switch. A second terminal of the thirteenth switch is electrically connected to a second terminal of the sixteenth switch. A second terminal of the fourteenth switch is electrically connected to a second wiring. A control terminal of the fourteenth switch is electrically connected to a first input wiring. A second terminal of the fifteenth switch is electrically connected to a first wiring. A control terminal of the fifteenth switch is electrically connected to a second input wiring. This is a semiconductor device. The gate of the second transistor is electrically connected to a first terminal of a fourth capacitor and a first terminal of a sixteenth switch. A second terminal of the thirteenth switch is electrically connected to a second terminal of the sixteenth switch. A second terminal of the fourteenth switch is electrically connected to a second wiring. A control terminal of the fourteenth switch is electrically connected to a first input wiring. A second terminal of the fifteenth switch is electrically connected to a first wiring. A control terminal of the fifteenth switch is electrically connected to a second input wiring. This is a semiconductor device.

[0020] (11) Alternatively, in one aspect of the present invention, in the configuration of (10) above, the twelfth switch includes a third transistor. The third transistor has a metal oxide in a channel formation region. The sixteenth switch includes a fourth transistor. The fourth transistor has a metal oxide in a channel formation region. This is a semiconductor device. The twelfth switch includes a third transistor. The third transistor has a metal oxide in a channel formation region. The sixteenth switch includes a fourth transistor. The fourth transistor has a metal oxide in a channel formation region. This is a semiconductor device. This is a semiconductor device.

[0021] (12) Alternatively, in one aspect of the present invention, there is an electronic device including any one of the semiconductor devices of (1) to (11) above and a housing, and performing neural network operations by the semiconductor device. This is an electronic device including any one of the semiconductor devices of (1) to (11) above and a housing, and performing neural network operations by the semiconductor device.

[0022] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Also, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device, etc. In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Also, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device, etc. are examples of semiconductor devices. It may itself be a semiconductor device and may have a semiconductor device.

[0023] Also, in this specification and the like, when it is described that X and Y are connected, it shall be disclosed in this specification and the like that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text shall also be regarded as disclosed in the figure or the text. X and Y shall be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). .

[0024] As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enables the electrical connection between X and Y can be connected between X and Y by one or more. Note that the switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not.

[0025] As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit (a DA conversion circuit, an AD conversion circuit, a gamma correction circuit, etc.), a potential level conversion circuit ( a power supply circuit (a boost circuit, a buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.) that enables the functional connection between X and Y ), a voltage source, a current source, a switching circuit, an amplifier circuit (a circuit such as an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc. that can increase the signal amplitude or current amount), a signal generation circuit, a memory circuit, a control circuit, etc.) can be connected between X and Y by one or more. Note that, as an example, even if another circuit is sandwiched between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0026] When it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, when they are connected with another element or another circuit sandwiched between X and Y) and the case where X and Y are directly connected (that is, when they are connected without another element or another circuit sandwiched between X and Y).

[0027] Also, for example, it can be expressed as "X, the source (or the first terminal, etc.) of the transistor, the drain ( or the second terminal, etc.) of the transistor, and Y are electrically connected to each other in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, and the drain ( or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y through the source (or the first terminal, etc.) and the drain ( or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." The source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor are The technical scope can be determined by distinguishing between the above. Note that these methods of expression are merely examples. , and are not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] In addition, the circuit diagram shows that independent components are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0029] In this specification, the term "resistance element" refers to a resistor having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistance element" may be used as a circuit element, wiring, etc. " refers to wiring with resistance, transistors with current flowing between the source and drain, and diodes. Therefore, the term "resistance element" includes "resistor," " "load" or "area having a resistance value" and conversely, "resistance" or The terms "load" and "region having a resistance value" can be rephrased as terms such as "resistive element". As the resistance value, for example, it can preferably be 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Also , for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0030] In this specification and the like, the "capacitive element" refers to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value, a parasitic capacitance, the gate capacitance of a transistor, etc. Therefore, in this specification and the like, the "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric included between the electrodes, but also a parasitic capacitance that appears between wirings, a gate capacitance that appears between one of the source or drain of a transistor and the gate, etc. Also, terms such as "capacitive element", "parasitic capacitance", "gate capacitance", etc. can be rephrased as terms such as "capacitance", etc., and conversely, the term "capacitance" can be rephrased as terms such as "capacitive element", "parasitic capacitance", "gate capacitance", etc. Also, the term "pair of electrodes" of "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", etc. Note that as the capacitance value it can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it may be 1 pF or more and 10 μF or less. In this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor.

[0031] ​​​The two terminals that function as a source or a drain are the input / output terminals of the transistor. 2 The two input / output terminals become either a source or a drain depending on the conductivity type of the transistor (n-channel type, p-channel type) and the magnitude of the potential applied to the three terminals of the transistor One becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain are assumed to be interchangeable Also, in this specification and the like, when explaining the connection relationship of the transistor, " one of the source or the drain" (or the first electrode, or the first terminal), "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Depending on the structure of the transistor in addition to the three terminals described above, there may be a back gate. In this case in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate and the other of the gate or the back gate of the transistor may be referred to as the second gate . Further, in the same transistor, the terms "gate" and "back gate" may be interchangeable with each other. Also, when the transistor has three or more gates in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, etc .

[0032] Also, in this specification and the like, a node can be equivalently referred to as a terminal, a wiring line, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on the circuit configuration, device structure, etc . Also, a terminal, a wiring, etc. can be equivalently referred to as a node

[0033] Also, in this specification and the like, "voltage" and "potential" can be equivalently interchanged as appropriate. " Voltage" is the potential difference from a reference potential. For example, when the reference potential is ground​ Assuming the ground potential as the reference potential, "voltage" can be rephrased as "potential". Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and when the reference potential changes, the potential applied to the wiring, the potential applied to a circuit, etc., and the potential output from a circuit, etc., also change.

[0034] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, a description such as "electrical conduction of a positive charged body is occurring" can be rephrased as "electrical conduction of a negative charged body is occurring in the opposite direction". Therefore, in this specification, etc., unless otherwise specified, "current" shall refer to the phenomenon of charge movement (electrical conduction) accompanying the movement of carriers. Here, the carriers include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, in a vacuum, etc.). Also, the "direction of current" in wiring, etc., is defined as the direction in which positive carriers move, and is described with a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed with a negative current amount. Therefore, in this specification, etc., when there is no specification regarding the positive or negative of current (or the direction of current), a description such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A", etc. Also, a description such as "current is input to element A" can be rephrased as "current is output from element A", etc. In addition, in this specification, etc., ordinal numbers such as "first", "second", and "third" are used for components

[0035] ​​​​​This is for avoiding confusion. Therefore, it does not limit the number of components. . Also, it does not limit the order of components. For example, in one of the embodiments such as this specification, the component referred to as "first" may be the component referred to as "second" in other embodiments or the claims. Also, for example, in one of the embodiments such as this specification, the component referred to as "first" may be omitted in other embodiments or the claims. the component referred to as "first" may be omitted in other embodiments or the claims.

[0036] Also, in this specification etc., terms indicating arrangements such as "above" and "below" may be used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification etc., and can be appropriately rephrased according to the situation. For example, in the expression "the insulator located on the upper surface of the conductor", by rotating the orientation of the shown drawing by 180 degrees, it can be rephrased as "the insulator located on the lower surface of the conductor".

[0037] Also, the terms "above" and "below" do not limit that the positional relationship between components is directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be directly formed in contact on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0038] Also, in this specification etc., terms such as "film" and "layer" can be mutually replaced according to the situation. For example, the term "conductive layer" can be changed to the term "conductive film". ​ It may be possible to change. Or, for example, the term "insulating film" may be changed to the term "insulating layer". It may be possible to change. Or, in some cases, or depending on the situation, it is possible to replace with another term without using terms such as "film" or "layer". For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

[0039] Also, in this specification, etc., terms such as "electrode", "wiring", and "terminal" do not functionally limit these constituent elements. For example, an "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wirings" are integrally formed. Also, for example, a "terminal" may be used as a part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be a part of "wiring" or "terminal", and for example, a "terminal" can be a part of "wiring" or "electrode". Also, the terms "electrode", "wiring", "terminal", etc. may be replaced with the term "region", etc. in some cases.

[0040] Also, in this specification, etc., the terms "wiring", "signal line", "power line", etc. may be interchanged with each other in some cases, or depending on the situation. For The term "signal line" may be changed to the term "wiring". Also, for example , the term "wiring" may be changed to terms such as "power line". Also , conversely, terms such as "signal line" and "power line" may be changed to the term "wiring". Terms such as "power line" may be changed to terms such as "signal line". Also, conversely, terms such as "signal line" may be changed to terms such as "power line". Also, the "potential" applied to the wiring may, in some cases or depending on the situation, be changed to terms such as "signal". Also, conversely, terms such as "signal" may be changed to the term "potential".

[0041] In this specification and the like, impurities in a semiconductor refer to, for example, components other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. When impurities are contained, for example, DOS (Density of States) may be formed in the semiconductor, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main component, and particularly, for example, hydrogen (also contained in water),

[0042] In this specification and the like, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to allow current to flow. Or, a switch refers to a device that has a function of selecting and switching a path through which current flows. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, the switch only needs to be able to control current and is not limited to a specific one. As an example of an electrical switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, transistor connected in diode configuration, etc.), or a logic circuit combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0043] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical-System) technology. The switch has electrodes that can be mechanically moved, and by moving the electrodes, it controls conduction and non-conduction to operate.

[0044] ​

[0045] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" or "approximately parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" or "approximately perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Advantages of the Invention

[0046] According to one aspect of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed can be provided. Or, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Or, one aspect of the present invention can provide a novel semiconductor device or the like. Or, one aspect of the present invention can provide an electronic device having the above semiconductor device.

[0047] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are effects not mentioned in this item described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, have the effects listed above.​​​​​​​​​​​​ It may not have.

Brief Description of the Drawings

[0048]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Embodiments for Carrying Out the Invention

[0049] In an artificial neural network (hereinafter referred to as a neural network), the synaptic connection strength can be changed by providing existing information to the neural network. In this way, the process of determining the connection strength by providing existing information to the neural network is sometimes called "learning".

[0050] Also, by providing some information to the neural network that has performed "learning" (determined the connection strength), new information can be output based on the connection strength. In this way, in a neural network, the process of outputting new information based on the provided information and the connection strength is sometimes called "inference" or "cognition".

[0051] Examples of neural network models include the Hopfield type, hierarchical type, etc. In particular, a neural network with a multi-layer structure is called a "deep neural network" (DNN), and machine learning using a deep neural network is sometimes called "deep learning".

[0052] In this specification, etc., a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also simply referred to as OS). For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, a metal oxide constitutes a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action. When possible, the metal oxide can be referred to as a metal oxide semiconductor, abbreviated as OS. Also, when described as an OS FET or an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor. conductor), which can be abbreviated as OS for short. Also, when described as an OS FET or an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0053] In addition, in this specification and the like, a metal oxide containing nitrogen may also be collectively referred to as a metal oxide. Also, a metal oxide containing nitrogen may be referred to as a metal oxynitride. ide). Also, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[0054] In addition, in this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Also, when multiple configuration examples are shown within one embodiment, it is possible to appropriately combine the configuration examples with each other. Further, when multiple configuration examples are shown within one embodiment, it is possible to appropriately combine the configuration examples with each other.

[0055] Note that the content described in a certain embodiment (even some of the content) can be applied, combined, or replaced with at least one of the content described in another part of the same embodiment (even some of the content), the content described in one or more other embodiments (even some of the content). Note that the content described in a certain embodiment (even some of the content) can be applied, combined, or replaced with at least one of the content described in another part of the same embodiment (even some of the content), the content described in one or more other embodiments (even some of the content).

[0056] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text written in the specification. Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text written in the specification.

[0057] Note that a figure (even a part of it) described in a certain embodiment can be combined with another part of the same figure, another figure (even a part of it) described in the same embodiment, and one or more other embodiments. Note that a figure (even a part of it) described in a certain embodiment can be combined with another part of the same figure, another figure (even a part of it) described in the same embodiment, and one or more other embodiments.​​​​​ For at least one of the figures (which may be only a part) described in the embodiments, by combining them, more figures can be further constituted.

[0058] The embodiments described in this specification will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used for the same parts or parts having similar functions between different drawings, and the repeated description may be omitted. Also, in perspective views and the like, in order to ensure the clarity of the drawings, the description of some components may be omitted.

[0059] In this specification and the like, when the same reference numerals are used for a plurality of elements, particularly when it is necessary to distinguish them, identification symbols such as “_1”, “[n]”, “[m,n]” may be added to the reference numerals for description.

[0060] Also, in the drawings of this specification, the size, the thickness of the layer, or the region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it can include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0061] Also, for this specification and the like, "In:Ga:Zn = 4:2:3 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 4, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 5:1:6 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 5, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, "In:Ga:Zn = 1:1:1 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 1, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, "In:Ga:Zn = 5:1:3 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 5, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 10:1:3 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 10, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Zn = 2:1 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 1, Zn is greater than 0.25 and 0.75 or less (0.25 < Zn ≤ 0.75). Also, "In:Zn = 5:1 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 1, Zn is greater than 0.12 and 0.25 or less (0.12 < Zn ≤ 0.25). Also, "In:Zn = 10:1 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12). With respect to the total number of atoms, when In is 4, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 5:1:6 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 5, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). With respect to the total number of atoms, when In is 5, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, "In:Ga:Zn = 1:1:1 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 1, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). With respect to the total number of atoms, when In is 1, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, "In:Ga:Zn = 5:1:3 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 5, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). With respect to the total number of atoms, when In is 5, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 10:1:3 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 10, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). With respect to the total number of atoms, when In is 10, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Zn = 2:1 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 1, Zn is greater than 0.25 and 0.75 or less (0.25 < Zn ≤ 0.75). With respect to the total number of atoms, when In is 1, Zn is greater than 0.25 and 0.75 or less (0.25 < Zn ≤ 0.75). Also, "In:Zn = 5:1 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 1, Zn is greater than 0.12 and 0.25 or less (0.12 < Zn ≤ 0.25). With respect to the total number of atoms, when In is 1, Zn is greater than 0.12 and 0.25 or less (0.12 < Zn ≤ 0.25). Also, "In:Zn = 10:1 or in the vicinity thereof" means that, with respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12). With respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12). With respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12). With respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12). With respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12).

[0062] (Embodiment 1) In this embodiment, an arithmetic circuit that performs the operation of a neural network, which is a semiconductor device according to one aspect of the present invention, will be described.

[0063] <Hierarchical Neural Network> First, the hierarchical neural network will be described. As an example, the hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in FIG. 1A shows an example thereof, and the neural network 100 has the first layer to the Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. Note that in FIG. 1A, the (k - 1)th layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted.

[0064] Each layer of the neural network 100 has one or more neurons. In FIG. 1A, the first layer has neurons N1 through neuron N (1) p (1) (where p is an integer of 1 or more ), the (k - 1)th layer has neurons N1 (k-1) through neuron N m (k-1) (where m is an integer of 1 or more), the kth layer has neurons N1 ( k) through neuron N n (k) (where n is an integer of 1 or more), and the Rth layer has ​​​​​​​​​​Neuron N1 (R) to neuron N q (R) (where q here is an integer of 1 or more.) has.

[0065] Note that in FIG. 1A, neuron N1 (1) , neuron N p (1) , neuron N1 ( k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition to, neuron N of the (k - 1)th layer i (k-1) (where i here is an integer of 1 or more and m or less), neuron N of the kth layer j ( k) (where j here is an integer of 1 or more and n or less) is also shown, and the illustration of other neurons is omitted.

[0066] Next, the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output in each neuron will be described. Note that in this description, attention is paid to neuron N of the kth layer In FIG. 1B, neuron N of the kth layer neuron N j (k) is focused on.

[0067] In FIG. 1B, neuron N of the kth layer j (k) and the signal input to neuron N j (k) and the signal output from neuron N neuron N j (k) are shown.

[0068] Specifically, the output signals z1 (k-1) to z m (k-1 ) of each of the neurons N1 (k-1) to N m (k-1) in the (k - 1)-th layer are output j ( k) towards the neuron N j (k) (k-1) m (k-1) j (k) in the k-th layer. And the neuron N j (k) generates z j (k) in response to z1 to z

[0069] and outputs z as an output signal towards each neuron in the (k + 1)-th layer (not shown). The signal input from the neurons in the previous layer to the neurons in the next layer is determined by the connection strength of the synapses (hereinafter referred to as the weight coefficient) connecting those neurons. In the neural network 100, the signal output from the neurons in the previous layer is multiplied by the corresponding weight coefficient and input to the neurons in the next layer. Let i be an integer greater than or equal to 1 and less than or equal to m. When the weight coefficient of the synapse between the neuron N i (k-1) in the (k - 1)-th layer and the neuron N j (k) in the k-th layer is w i (k-1) j (k) j (k) j (k) in the k-th layer can be expressed by Equation (1.1).

[0070]

Equation

[0071] That is, when signals are transmitted from each of neurons N1 (k-1) to N m (k-1) in the (k - 1)-th layer to neuron N in the k-th layer, for each of the signals z1 j (k) to z (k-1) to z m (k-1) corresponding weights (w1 (k-1 ) j (k) to w m (k-1) j (k) ) are multiplied. And for neuron N j (k) in the k-th layer, w1 (k-1) j (k) ·z1 (k-1) to w m (k-1) j (k) · z m (k-1) are input. At this time, the sum u j (k) of the signals input to neuron N in the k-th layer becomes Equation (1.2). j (k) That is,

[0072]

Equation

[0073] Also, the weights w1 (k-1) j (k) to w m (k-1) j (k) and the Signal z1 (k-1) through z m (k-1) For the sum-of-products result, a bias may be given as a bias. When the bias is b, Equation (1.2) can be rewritten as the following equation . .

[0074] [Number]

[0075] Neuron N j (k) outputs an output signal z j (k) in response to u j (k) . Here . The output signal z j (k) from neuron N j (k) is defined by the following equation.

[0076] [Number]

[0077] The function f(u j (k) ) is an activation function in a hierarchical neural network , and a step function, a linear ramp function, a sigmoid function, etc. can be used. Note that the activation function may be the same for all neurons, or may be different. In addition , the activation function of a neuron may be the same or different for each layer.

[0078] By the way, the signal output by the neurons in each layer, the weight coefficient w, or the bias b may be an analog value or a digital value. As a digital value, for example, it may be a binary value or a ternary value. Even values with a larger number of bits may be used. As an example In the case of an analog value, as the activation function, for example, a linear ramp function, a sigmoid function, etc. can be used. In the case of a digital binary value, for example, a step function that sets the output to -1 or 1, or 0 or 1 can be used. Also, the signal output by the neurons in each layer can be three values or more. For example, as the activation function that outputs three values, the output is -1, 0, or 1, or a step function that outputs 0, 1, or 2, etc. can be used. Also, for example, as the activation function that outputs five values, a step function that outputs -2, -1, 0, 1, or 2 can be used. By using digital values for at least one of the signal output by the neurons in each layer, the weight coefficient w, or the bias b, the circuit scale can be reduced, the power consumption can be reduced, or the operation speed can be increased, etc. Also, by using analog values for at least one of the signal output by the neurons in each layer, the weight coefficient w, or the bias b, the accuracy of the operation can be improved. When an input signal is input to the first layer (input layer) of the neural network 100, sequentially in each layer from the first layer (input layer) to the last layer (output layer), based on the signal input from the previous layer, the output signal is generated using Equation (1.1), Equation (1.2) (or Equation (1.3)), Equation (1.4) and the output signal is output to the next layer. The signal output from the last layer (output layer)

[0079] corresponds to the result calculated by the neural network 100.

[0080] <Configuration Example 1 of the Arithmetic Circuit>

[0080] <Configuration Example 1 of the Arithmetic Circuit> Here, in the neural network 100 described above, an example of an arithmetic circuit that can perform the operations of Expression (1.2) (or Expression (1 .3)), and Expression (1.4) will be described. Note that, as an example, in the arithmetic circuit, the weight coefficients of the synaptic circuits of the neural network 100 can be digital values of two or more values or analog values, and the activation function of the neuron can be a step function or the like. Also, in this specification and the like, either the weight coefficient or the value of the signal input from the neuron in the previous layer to the neuron in the next layer (which may be referred to as the arithmetic value) may be referred to as the first data, and the other may be referred to as the second data. Note that the weight coefficients and arithmetic values of the synaptic circuits of the neural network 100 are not limited to digital values, and analog values can be used for at least one of them. For the weight coefficient and the value of the signal input from the neuron in the previous layer to the neuron in the next layer (which may be referred to as the arithmetic value), either one of them may be referred to as the first data, and the other may be referred to as the second data. Note that the weight coefficients and arithmetic values of the synaptic circuits of the neural network 100 are not limited to digital values, and analog values can be used for at least one of them. data. Note that the weight coefficients and arithmetic values of the synaptic circuits of the neural network 100 are not limited to digital values, and analog values can be used for at least one of them. data. Note that the weight coefficients and arithmetic values of the synaptic circuits of the neural network 100 are not limited to digital values, and analog values can be used for at least one of them. It is also possible to use an analog value for at least one of them.

[0081] The arithmetic circuit 110 shown in FIG. 2A is, as an example, a semiconductor device having an array unit ALP and a circuit AFP. The arithmetic circuit 110 processes, for example, the signals input to the neuron N in the k-th layer in FIGS. 1A and 1B, and generates the signal z output from the neuron N j (k) . However, one aspect of the present invention is not limited to this. The arithmetic circuit 110 may function as a storage device or a memory circuit, for example. For example, the arithmetic circuit 110 may function as a DRAM, an SRAM, or a flash j (k) memory, for example. Alternatively, the arithmetic circuit 110 may be, for example, within a memory circuit. output from the neuron N j (k) . However, one aspect of the present invention is not limited to this. The arithmetic circuit 110 may function as a storage device or a memory circuit, for example. For example, the arithmetic circuit 110 may function as a DRAM, an SRAM, or a flash memory, for example. Alternatively, the arithmetic circuit 110 may be, for example, within a memory circuit. memory, for example. Alternatively, the arithmetic circuit 110 may be, for example, within a memory circuit. memory, for example. Alternatively, the arithmetic circuit 110 may be, for example, within a memory circuit. A circuit that performs calculations, that is, it may function as an in-memory computing circuit. .

[0082] The array unit ALP has, as an example, circuits MP[1,j] to MP[m,j]. . Also, the circuit AFP has, as an example, a circuit ACTF[j], and further, the circuit ACTF j] has a capacitance CRE, a circuit AC, a terminal T1, and a terminal T2.

[0083] Note that the capacitance CRE may be realized using a normal capacitive element, but one aspect of the present invention is not limited to this. For example, the capacitance CRE may be realized using the gate capacitance of a transistor, as shown in, for example, FIG. 2B or FIG. 2C. In this case, the transistor may be an N-channel type, a P-channel type, or both may be used and connected in parallel. Note that in FIGS. 2B and 2C, a transistor CRET is used instead of the capacitance CRE. As the transistor CRET, for example, an OS transistor can be applied. Note that the OS transistor will be described in detail in Embodiment 5. Also, other than the OS transistor, for example, a transistor having silicon in the channel formation region (hereinafter referred to as an Si transistor) can be used. Also, as the silicon, for example, single-crystalline silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used. Also, as transistors other than the OS transistor and the Si transistor, for example, a transistor having Ge as an active layer , a transistor having a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe as an active layer, a transistor having a carbon nanotube as an active layer, an organic semiconductor , etc. can be used. Also, as the silicon, for example, single-crystalline silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used. Also, as transistors other than the OS transistor and the Si transistor, for example, a transistor having Ge as an active layer , a transistor having a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe as an active layer, a transistor having a carbon nanotube as an active layer, an organic semiconductor can be used. Transistors or the like having this as the active layer can be used.

[0084] Each of circuits MP[1,j] to MP[m,j] is electrically connected to wiring OL[j] and wiring O LB[j]. Also, each of circuits MP[1,j] to MP[m ,j] is electrically connected to wirings XLS[1] to XLS[m]. . Further, wiring OL[j] is electrically connected to terminal T1, and terminal T1 is the first terminal of capacitor CRE. Wiring OLB[j] is electrically connected to terminal T2, and terminal T 2 is electrically connected to the second terminal of capacitor CRE. Note that, for example, between terminal T1 and the first terminal of capacitor CRE, some element or circuit (for example, a switch, transistor, etc.) may be connected. Similarly, for example, between terminal T2 and the second terminal of capacitor CRE, some element or circuit (for example, a switch, transistor, etc.) may be connected.

[0085] Each of wirings XLS[1] to XLS[m], as an example, has a function of transmitting a potential corresponding to signals z1 (k-1) to neuron N1 m (k-1) to z (k-1) m ( k-1) k-1) output from neuron N

[0086] Circuit MP[1,j], as an example, holds the weight coefficient w1 (k-1) between neuron N1 j (k ) and neuron N (k-1) j (k) (here it is the first data). has the ability, and similarly, the circuit MP[m,j], as an example, is a neuron N m (k-1) and the neuron N j (k) retains the weight coefficient w m (k-1) j (k) between them.

[0087] Also, the circuit MP[1,j], as an example, is a neuron N1 (k-1) output from signal z1 (k-1) (here it is the second data) and the first data w1 (k-1) j (k) has the function of outputting the product with. Similarly, the circuit MP[m,j], as an example, is a neuron N m (k-1) output signal z m (k-1) (here it is the second data) and the 1 data w m (k-1) j (k) has the function of outputting the product with.

[0088] As a specific example, for the circuit MP[1,j], by inputting the potential corresponding to the second data z 1 (k-1) through the wiring XLS[1], the circuit MP[1,j] outputs information (such as current, voltage, etc.) corresponding to the product of the first data w1 (k-1) j (k) and the second data z1 (k-1) to the wiring OL[j] and / or the wiring OLB[j]. Also, as another specific example, similarly, for the circuit MP[m,j], the second data z is input through the wiring XLS[m] m (k-1)When a potential corresponding thereto is input, circuit MP[m,j] outputs information (e.g., current, voltage, etc.) corresponding to the product of the first data w m (k-1) j (k) and the second data z m (k-1) to wiring OL[j] and / or wiring OLB[j]. Therefore, for example, in wiring OL, the information (e.g., current, voltage, etc.) output from each of circuits MP[1,j] to MP[m,j] is added together. Similarly, for example, in wiring OLB, the information (e.g., current, voltage, etc.) output from each of circuits MP[1,j] to MP[m,j] is added together. That is, information (e.g., current, voltage, etc.) corresponding to the sum of products of the first data w1

[0089] to w and the second data z1 to z flows through each of wiring OL and wiring OLB. However, one aspect of the present invention is not limited thereto. For example, in at least one of wiring OL or wiring OLB, information (e.g., current, voltage, etc.) serving as some reference (e.g., reference, precharge, bias, etc.) may flow. The specific circuit configurations of circuits MP[1,j] to MP[m,j] will be described later. (k-1) j (k) to w m (k -1) j (k) and the second data z1 (k-1) to z m (k-1) flows. However, one aspect of the present invention is not limited thereto. For example, in at least one of wiring OL or wiring OLB, information (e.g., current, voltage, etc.) serving as some reference (e.g., reference, precharge, bias, etc.) may flow. For example, information (e.g., current, voltage, etc.) corresponding to the sum of products of the first data w1 to w and the second data z1 to z

[0090] Note that the specific circuit configurations of circuits MP[1,j] to MP[m,j] will be described later. will be described later.

[0091] As an example, circuit ACTF[j] receives the first Obtain information (such as current, voltage, etc.) corresponding to the sum of products of data and second data, and new Ron N j (k) signal z output from j (k) function as a circuit to generate. Specifically is the circuit AC included in the circuit ACTF[j], from the information, binary, multi-valued output signal z represented by any digital value or analog value j (k) (in the case of a calculated value there is) is generated. That is, the circuit AC is, for example, treated as an activation function circuit .

[0092] As the circuit AC, for example, an analog-to-digital conversion circuit (sometimes called a sense amplifier etc.) can be used. Specifically, the circuit AC is, for example, when the result of the sum of products is "0" or less, the output signal z outputs a digital signal with a value of "0" as j (k) and when the result of the sum of products is "positive", the output signal z outputs a digital j (k) value of "positive" and can be an analog-to-digital conversion circuit or the like.

[0093] In addition, in this specification, etc., when not distinguishing each of the circuits MP[1,j] to MP[m,j], they are described as circuit MP. Similarly, when not distinguishing each of the wirings XLS[1] to wiring XLS[m], they are described as wiring XLS. Also, when not distinguishing each of the wirings OL[j] and OLB[j], they may be described as wiring OL and wiring OLB. Similarly, when omitting [j] of the circuit ACTF[j], it may be described as circuit ACTF. ​​

[0094] <Operation Example 1 of Calculation Circuit> Next, an operation example of the circuit ACTF[j] in FIG. 2A will be described. FIGS. 3A to 3C are circuit diagrams showing the order of operation examples of the circuit ACTF[j].

[0095] In FIG. 3A, an operation example of initializing the voltage between the first terminal and the second terminal of the capacitance CRE of the circuit ACTF[j] to 0 V is shown. Specifically, in the circuit of FIG. 3A, for each of the wiring OL[j] and the wiring OLB[j], as an initialization potential, for example, V is given. ini is given Let's assume that. As an example of V ini , when current flows from the wiring OL to the circuit MP, it becomes VDD, and when current flows from the circuit MP to the wiring OL, it becomes VSS or GND.

[0096] In FIG. 3B, by each of the circuits MP[1,j] to MP[m,j], information (for example, current, voltage, charge, etc.) corresponding to the sum of products of the first data w1 to w (k-1) j (k) to w m (k-1) j (k) and the second data z1 (k-1) to z to z m (k-1) is output to the wiring OL j] and the wiring OLB[j], and an operation example in which the circuit ACTF[j] acquires the information is shown. At this time, the potential V of the first terminal of the capacitance CRE ini changes to the potential V based on the information input from the circuit MP to the circuit ACTF[j] via the wiring OL[j], and the potential V OL of the second terminal of the capacitance CRE changes to the potential V based on the information input from the circuit MP to the circuit ACTF[j] via the wiring OLB[j]. ini via the wiring OLB[j] from the circuit MP ​The potential V changes based on the information input to circuit ACTF[j]. OLB It is assumed to change to At this time, the voltage across the first and second terminals of capacitor CRE is |V RD | (= |V OLB - V OL |). This |V RD | corresponds to, for example, the difference between the total amount of information flowing through wiring OL[j] and the total amount of information flowing through wiring OLB[j]. As an example, if the wiring OL[j] is the sum of positive values and the wiring OLB[j] is the sum of negative values, then |V | corresponds to the difference between the sum of positive values and the sum of negative values. Therefore, |V | corresponds to the result of the sum-of-products operation. That is, the sum-of-products result of the first data w1 RD through w RD and the second data z1 (k-1) j (k) through z m (k-1) j (k) can be held between the first and second terminals of capacitor CRE as the voltage |V |. (k-1) through z m (k-1) RD RD | and the voltage (charge) stored in capacitor CRE can be held between the first and second terminals of capacitor CRE

[0097] In FIG. 3C, as an example, the voltage (charge) stored in capacitor CRE is input to circuit AC to sense the amount of the voltage (charge) stored in capacitor CRE. In this case, the potential V OL and the potential V OLB change significantly according to the result of the sum-of-products. Therefore, if this potential is directly input to circuit AC, there may be drawbacks such as the circuit configuration of circuit AC becoming complex or the operating range of circuit AC becoming small. Therefore, As an example, the potential V OL , and even if the magnitudes of the potential V OLB are different, their difference is |V RD | (= |V OLB - V OL |). When this results in the same voltage, it is desirable for the circuit AC to be configured such that the same voltage is input. For example, even when the potential V O = 1 and the potential V L OLB = 2, or when the potential V OL = 3 and the potential V OLB RD = 4, in both cases, |V | = 1 and |V RD | has the same magnitude. Even in such cases , it is desirable for the circuit AC to be configured such that the same voltage is input. Therefore , as an example, at least one of the first and second terminals of the capacitor CRE is electrically floated , and then a reference potential (here, for example, the GND potential (0V). However, one aspect of the present invention is not limited to this and may also be a VDD potential, a precharge potential, a potential of (VDD / 2), etc )) is applied. Then, the potential of the other of the first or second terminal of the capacitor CRE can be set to |V RD OL OLB |. That is, even if the magnitudes of the potential V RD and the potential OL V V OLB are different, when |V RD | is the same, the same potential can be input to the circuit AC . And the circuit AC senses, for example, the potential of the second terminal of the capacitor CRE and outputs a signal z RD corresponding to the voltage V j (k) . That is, the operation shown in FIG. 3C As an example, the first data output by the circuits MP[1,j] to MP[m,j] As a result of the multiplication and accumulation of the first data, a signal z j (k) will be output.

[0098] Here, a specific example of the above operation will be described.

[0099] First data w1 (k-1) j (k) Or even w m (k-1) j (k) Each of the following is an explanation: For simplicity, let us assume that the second data can take any value, for example, “+1”, “0”, or “-1”. Ta z1 (k-1) ~z m (k-1) Each of these can be, for example, “+1”, “0”, “-1” " The value of this bit is either "

[0100] In the operation example of FIG. 3A, the potential V ini is assumed to be precharged to a high level potential.

[0101] In addition, in the circuit MP, when the product of the first data and the second data is “+1”, the circuit M The state between P and the wiring OL is conductive, and the state between the circuit MP and the wiring OLB is non-conductive. It is assumed that a current corresponding to "|+1|" flows from the wiring OL to the circuit MP. In addition, in the circuit MP, when the product of the first data and the second data is "-1", The circuit MP and the wiring OL are in a non-conductive state, and the circuit MP and the wiring OLB are in a conductive state. Then, a current according to "|-1|" (i.e. , it is assumed that a current having the same magnitude as the current corresponding to “|+1|” flows. Also, in circuit MP , when the product of the first data and the second data is “0”, the connection between circuit MP and wiring OL , and the connection between circuit MP and wiring OLB are in a non-conductive state. That is, in wiring OL , a current having the magnitude of the positive sum flows, and in wiring OLB, a current having the magnitude of the absolute value of the negative sum flows.

[0102] At this time, in the operation example of FIG. 3B, the magnitude of potential V OL is determined by the number of circuit MPs in which the product of the first data and the second data is “+1”. Specifically, the larger the number of circuit MPs in which the product of the first data and the second data is “+1”, the larger the total amount of current flowing from wiring OL to circuit M P[1,j] to circuit MP[m,j]. Also, since wiring OL is pre-charged with a high-level potential V ini , the larger the total amount of current flowing from wiring OL to circuit MP[1 ,j] to circuit MP[m,j], the larger the voltage drop from the potential V of wiring OL i ni . That is, the larger the number of circuit MPs in which the product of the first data and the second data is “+1” , the lower the potential V OL .

[0103] Similarly, the magnitude of potential V OLB is determined by the number of circuit MPs in which the product of the first data and the second data is “-1” . Specifically, the larger the number of circuit MPs in which the product of the first data and the second data is “-1” , the larger the total amount of current flowing from wiring OLB to circuit MP[1,j] to circuit M P[m,j]. Also, wiring OLB is pre-charged with a high-level potential V iniSince the circuits MP[1,j] to MP[ m, j], the larger the total current flowing through the wiring OLB, the greater the potential V ini Voltage drop from In other words, the product of the first data and the second data is "-1" in the circuit MP. The more the number, the greater the potential V OLB will be lower.

[0104] From the above, the number of circuits MP where the product of the first data and the second data is “+1” is the When the product of the first data and the second data is greater than the number of circuits MP that are "-1", The potential V of the first terminal of the quantity CRE OL is the potential V of the second terminal of the capacitance CRE OLB Lower than That is, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) And Day 2 Ta z1 (k-1) ~z m (k-1) When the sum of the products is positive, the potential V OL is the potential V OLB In addition, the product of the first data and the second data is "-1". The number of MPs is less than the number of circuit MPs where the product of the first data and the second data is “+1”. When the potential V of the first terminal of the capacitance CRE is large, OL is the potential V of the second terminal of the capacitance CRE O LB That is, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m(k-1) When the sum of products with [something] becomes "negative", the electric potential V OL is higher than the potential V OLB is.

[0105] Also, when the number of circuits MP where the product of the first data and the second data is "+1" is equal to the number of circuits MP where the product of the first data and the second data is "-1", or when, in all of the circuits MP[1,j] to MP[m,j], the product of the first data and the second data is "0", the potential V at the first terminal of the capacitor CRE is equal to the potential V at the second terminal of the capacitor CRE OL That is, the first data w1 and the potential V OLB become equal. That is, the first data w1 (k-1) j (k) to w m (k -1) j (k) and the second data z1 (k-1) to z m (k-1) and the sum of products is "0", the potential V OL and the potential V OLB become the same potential. Furthermore, when, in all cases, the product of the first data and the second data is "0", the potential V and the potential V OL and the potential V OLB remain at the potential V potential V ini as it is.

[0106] Note that the larger the absolute value of the sum of products of the first data w1 (k-1) j (k) to w m (k-1) j (k) and the second data z 1 (k-1) to z m (k-1) is, the greater the difference between the potential V OL and the potential V O LB The potential difference from this (the absolute value of the voltage between the first and second terminals of the first capacitor) increases.

[0107] Also, in the above operation example, the first data w1 (k-1) j (k) to w m (k-1) j ( k) each takes a value of, for example, either “+1”, “0”, or “-1” as described, but the operation of the semiconductor device according to one aspect of the present invention is not limited to this. For example, the first data w1 (k-1) j (k) to w m (k-1) j (k) possible values may be multiple values exceeding three values such as “+2 ”, “+1”, “0”, “-1”, “-2”, etc., or may be two values such as “+1”, “-1”, etc. Also, the amount of current flowing between the circuits MP[1,j] to MP[m,j] and the wiring OL and / or the wiring OLB is determined according to the result of the product of the possible values of the first data w1 held in each of the circuits MP[1 (k-1) j (k) to w m (k-1) j (k) and the second data. Specifically, for example, each of the first data w1 (k-1) j (k) to w m (k-1) j (k) takes one of “+2”, “+1”, “0”, “-1”, “-2”, and the second data z1 takes a value of, for example, either “+1”, “0”, or “-1” as(k-1) up to z m (k-1) each of them takes a value of either “+1”, “0”, “-1”. Here, in circuit MP, when the product of the first data and the second data is “+1”, it is assumed that the connection between circuit MP and wiring OL becomes conductive, and the connection between circuit MP and wiring OLB becomes non-conductive. A current of amount I ut flows from wiring OL to circuit MP. Also, in circuit MP, when the product of the first data and the second data is “+2”, it is assumed that the connection between circuit MP and wiring OL becomes conductive, and the connection between circuit MP and wiring OLB becomes non-conductive. A current of 2×I u t flows from wiring OL to circuit MP. Further, when the product of the first data and the second data is “-1”, it is assumed that the connection between circuit MP and wiring OL becomes non-conductive, and the connection between circuit MP and wiring OLB becomes conductive. A current of amount I ut flows from wiring OLB to circuit MP in this case. Also, when the product of the first data and the second data is “-2”, it is assumed that the connection between circuit MP and wiring OL becomes non-conductive, and the connection between circuit MP and wiring OLB becomes conductive. A current of 2×I ut flows from wiring OLB to circuit MP. Also, when the product of the first data and the second data is “0”, it is assumed that the connection between circuit MP and wiring OL becomes non-conductive, and the connection between circuit MP and wiring OLB becomes non-conductive.

[0108] From the above, by performing the operation example of FIG. 3B, the voltage between the first terminal - second terminal of the first capacitor is adjusted according to the first data w1 (k-1) j (k) up to w​m (k-1) j (k) and the second data z1 (k-1) to z m (k-1) The potential V corresponding to the sum of products with OL and the potential V OLB The potential difference with (voltage |V RD ) can be set as such.

[0109] Thereafter, as shown in the operation example shown in FIG. 3C, for example, the second terminal of the capacitor CRE is electrically put in a floating state (the first terminal of the capacitor CRE may also be electrically put in a floating state), and then, By setting the potential of the first terminal of the capacitor CRE to the GND potential, the potential of the second terminal of the capacitor CRE is V RD is set. The first data w1 (k-1) j (k) to w m (k-1) j (k) and the second data -ta z1 (k-1) to z m (k-1) When the sum of products with is "positive", the potential V of the second terminal of the capacitor CRE RD becomes a positive potential, and the first data w1 (k-1) j (k) to w m (k- 1) j (k) and the second data z1 (k-1) to z m (k-1) When the sum of products with is "negative", the potential V of the second terminal of the capacitor CRE RD becomes a negative potential. Also, the first data w1 (k- 1) j (k) to w m (k-1) j(k) and the second data z1 (k-1) to z m (k-1 ) When the sum of products with it is "0", the differential voltage between the first terminal and the second terminal of the capacitor CRE is approximately 0 Therefore, the potential V of the second terminal of the capacitor CRE RD becomes the GND potential.

[0110] And, by the circuit AC, by sensing the potential of the second terminal of the capacitor CRE thereby, the output signal z corresponding to the voltage V RD can be output. That is, the potential V of the first terminal of the capacitor CR j (k) E and the potential V of the second terminal of the capacitor CRE Even when they are large with respect to each other, or, the potential V of the first terminal of the capacitor CRE OL and the potential V of the second terminal of the capacitor CRE OLB even when they are small with respect to each other, if the differential voltage between the potential V and the potential V is equal in each case, the differential voltage is detected by the capacitor CRE, and a voltage of the same magnitude OL is input to the circuit AC, and the same result can be output as the output signal z O LB As a result, regardless of the magnitudes of the potential V OL and the potential V OLB a more accurate sum of products result can be obtained in each case. That is, regardless of the magnitudes of the potential V and the potential V, the same voltage is input to the circuit AC, and the same result can be output as the output signal z j (k) Therefore, regardless of the magnitudes of the potential V and the potential V OL a more accurate sum of products result can be obtained OLB without depending on the magnitudes of the potential V and the potential V.

[0111] In particular, in the case of a hierarchical neural network, as the circuit AC, an activation function circuit and that's all right. Depending on the type of activation function, for example, when the result of the sum of products of the first data and the second data is "0" or less, the output signal z j (k)Output a digital signal with a value of “0” and when the result of the sum of products of the first data and the second data is “positive”, the output signal z j (k) and it may be a circuit that can output a “positive” multi - value. As such a circuit, for example, it is preferable to use an analog - digital conversion circuit (such as a sense amplifier, comparator, etc.) that can sense only positive voltages.

[0112] In the above example, an example of use in a neural network was shown, but one aspect of the present invention is not limited to this. For example, the wiring OL outputs a signal from the memory cell to be read, and the wiring OLB outputs a signal from the reference memory cell, whereby it may be used as a function to read the information held in the memory cell to be read. That is, it may be used as DRAM, SRAM, or flash memory. For example, it may be operated as reading of multi - value data. Or, as an example, it may be used as a circuit that performs calculations within a memory circuit, that is, an in - memory computing circuit.

[0113] By the way, when the result of the sum of products of the first data and the second data is “negative”, if it is desired to output a “negative” multi - value as the output signal z j (k) for example, as the circuit AC, an analog - digital conversion circuit that can sense both positive and negative voltages added to a positive voltage may be used. Also in FIG. 3C, instead of setting the potential of the first terminal of the capacitor CRE to the GND potential, the potential of the first terminal of the capacitor CRE may be set to (VDD / 2). In this way, the first data ​​​​​When the sum of the products of the first data and the second data is zero, the circuit AC is supplied with a voltage of (VDD / 2). The first data and the second data are input in digits. And the result of multiplying and adding the first data and the second data is not only "positive", Even if the potential is very negative, if its absolute value is small, the AC circuit is input with a positive potential. As a result, an analog-to-digital conversion circuit that can sense only positive voltages is created. It is possible to use circuits (sense amplifiers, comparators, etc.) that are analog. Digital conversion circuits (sense amplifiers, comparators, etc.) operate in a manner that is consistent only when the input voltage is positive. In this case, the circuit can be simplified. That is, a negative power supply voltage is no longer required, so the voltage It is also possible to simplify the power supply circuit. In addition, a wider range of input voltages is available, which reduces noise. This allows for a large margin for noise, enabling accurate processing.

[0114] In addition, when the result of the multiplication and accumulation of the first data and the second data is negative, Output signal z j (k) As a method for outputting a “negative” multi-value as an input, for example, the calculation of FIG. The circuit 110 may be changed to the arithmetic circuit 120 shown in FIG. By increasing the number of inputs, even if the result of the multiplication and accumulation is negative, only positive voltages can be sensed. Use analog-to-digital conversion circuits (sense amplifiers, comparators, etc.) where possible As an example, the arithmetic circuit 120 may include a capacitance CREP, a capacitance CREM, and a circuit The first terminal of the capacitance CREP is electrically connected to the terminal T1. The second terminal of the capacitor CREP is electrically connected to the terminal T2. The first terminal is electrically connected to terminal T1, and the second terminal of the capacitance CREM is electrically connected to terminal T2. For example, the terminal T1 and the first terminal of the capacitance CREP (capacitor CREM) are connected to each other. Between the two, some element or circuit (such as a switch or transistor) is connected. Similarly, for example, the terminal T2 and the second terminal of the capacitance CREP (capacitor CREM) may be connected to each other. Between the terminals, some element or circuit (e.g., switch, transistor, etc.) is connected. The circuit ACP and the circuit ACM may be the same as those used in the arithmetic circuit 110 of FIG. As with AC circuits, for example, it is possible to sense positive voltages and perform analog-to-digital conversion. Circuits (sense amplifiers, comparators, etc.) are used. It is assumed that these are initialized before sensing, and the circuit ACP is the second capacitance CREP. The circuit ACM senses the potential of the first terminal of the capacitance CREM. In other words, the sensing terminal is changed depending on the capacitance CREP and the capacitance CREM. do.

[0115] The arithmetic circuit 120 in FIG. 4A changes the potential of the wiring OL to V OL The potential of the wiring OL is V OLB As a result, the voltage between the first and second terminals of the capacitance CREP is and the voltage between the first and second terminals of the capacitance CREP is |V RE | can be used.

[0116] Here, as shown in the operation example of FIG. 4B, the second terminal of the capacitance CREP, the first terminal of the capacitance CREM (the first terminal of the capacitance CREP and the The second terminal may be electrically floating), then the first terminal of the capacitor CREP and the The second terminal of the capacitor CREM and the second terminal of the capacitor CR The potential of the second terminal of the EP is V RD and the potential of the first terminal of the capacitor CREM is -V RD becomes . The first data w1 (k-1) j (k) to w m (k-1) j (k) and the second data z1 (k -1) to z m (k-1) When the result of the sum of products of and is "positive", V RD is a potential higher than 0 and becomes. The first data w1 (k-1) j (k) to w m (k-1) j (k) and the second data z 1 (k-1) to z m (k-1) When the result of the sum of products of and is "negative", V RD is lower than 0 and becomes a potential. That is, the first data w1 (k-1) j (k) to w m (k-1) j (k) and the second data z1 (k-1) to z m (k-1) When the result of the sum of products of and is "positive", the circuit ACM, since the potential -V of the first terminal of the capacitor CREM is negative, no potential output is made from the circuit ACM (or zero is output), and the circuit ACP senses because the potential V of the second terminal of the capacitor CREP is positive and outputs a potential corresponding to the potential V from the circuit ACP. Also, the first data w1 The potential of the first terminal of the capacitor CREM is -V RD Since it is negative, no potential output is made from the circuit ACM (or zero is output), and the circuit ACP senses because the potential V of the second terminal of the capacitor CREP is positive and outputs a potential corresponding to the potential V from the circuit ACP. Also, the first data w1 and outputs a potential. Also, the first data w1 The potential of the second terminal of the capacitor CREP is V RD Since it is positive, it senses and outputs a potential corresponding to the potential V from the circuit ACP. Also, the first data w1 RD According to the potential. Also, the first data w1 (k-1) j (k) to w m(k-1) j (k ) and the second data z1 (k-1) to z m (k-1) When the result of the sum of products of them is “negative”, since the potential V of the second terminal of the capacitor CREP in the circuit ACP RD is negative, no potential output is made from the circuit ACP (or zero is output), and since the potential -V of the first terminal of the capacitor CREM in the circuit ACM is positive, sensing is performed and a potential corresponding to the potential V RD from the circuit ACM is output. Note that the first data w1 RD corr esponding to the potential V is output. Note that the first data w1 (k-1) j (k) to w m (k-1) j ( k) and the second data z1 (k-1) to z m (k-1) When the result of the sum of products of them is “0” , since the potential of the first terminal of the capacitor CREP in the circuit ACP is the GND potential, no potential output is made from the circuit ACP (or zero is output), and also, since the potential of the second terminal of the capacitor CRE M in the circuit ACM is the GND potential, no potential output is made from the circuit ACM ( or zero is output). or zero is output).

[0117] Here, even when using an analog-digital conversion circuit (such as a sense amplifier, comparator, etc.) that can sense only positive voltages by corresponding the potential output from the circuit ACP to “positive” multi-values and the potential output from the circuit ACM to “negative” multi-values , even when the result of the sum of products of the first data and the second data is “negative”, the output signal z j (k) ​​It is possible to output "negative" multi-valued values. Regarding circuit AC, in FIG. 4 , an example of the case of having circuit ACP and circuit ACM is shown, but one aspect of the present invention is not limited to this. Circuit ACP and circuit ACM may be circuit AC only, and sensing may be performed twice by circuit AC. That is, the operation of circuit AC may be divided into two times and operated in a time-division manner. As a result, although the processing time becomes longer, the scale of the circuit can be reduced. .

[0118] <Configuration Example 2 of Arithmetic Circuit> Next, an example of the specific circuit configuration of circuit ACTF[j] will be described. Circuit ACTF j] can be, for example, the circuit configuration shown in FIG. 5. FIG. 5 is, as an example, a circuit that generates signal z j (k) in response to the current input from wiring OL[j] and wiring OLB[j]. Specifically, FIG. 5 shows an example of an arithmetic circuit that outputs an output signal z j (k) represented by a multi-valued or analog value. Therefore, circuit ACTF[j] can be configured to have, as an example, a function as an activation function circuit in a neural network. Note that FIG. 5 shows the electrical connection configuration between circuit ACTF[j] and peripheral circuits, and thus array section ALP and circuit AFP are also shown.

[0119] Circuit ACTF[j] shown in FIG. 5 has, as an example, switch SWR1, switch SWR 1B, switch SWR2, switch SWR2B, circuit IVTR, circuit IVTRr , capacitor CRE, and circuit AC.

[0120] Switch SWR1, switch SWR1B, switch SWR2, and switch SWR2B Each of them can be, for example, an electrical switch such as an analog switch or a transistor and the like can be applied. Note that at least one of switch SWR1, switch SWR1B, switch SWR2, and switch SWR2B, for example, when applying a transistor the transistor can be the same as the transistor used for transistor CRET and can be used. In addition to electrical switches, mechanical switches may also be applied .

[0121] Circuit IVTR is electrically connected to terminal T1 and the first terminal of switch SWR1 . The second terminal of switch SWR1 is electrically connected to the first terminal of capacitor CRE and the first terminal of switch SWR2. The second terminal of switch SWR2 is electrically connected to wiring VCN3 . Circuit IVTRr is electrically connected to terminal T2 and the first terminal of switch SWR1B . The second terminal of switch SWR1B is electrically connected to the second terminal of capacitor CRE and the first terminal of switch SWR2B. The second terminal of switch SWR 2B is electrically connected to terminal mbt1 of circuit AC

[0122] Wiring VCN3 functions as a wiring for supplying a constant voltage. As the constant voltage, for example it can be the ground potential GND or a low-level potential. Or, as an example, it can be VDD (high-level potential).

[0123] Circuit AC has terminal mbt1 and terminal mbt2. As circuit AC, as described above for example, it can be an analog-to-digital conversion circuit or the like as an example. The circuit shown in FIG. 5 The path AC senses the potential applied to the terminal mbt1 and outputs, as a digital signal, an output signal z corresponding to the potential from the terminal mbt2. Therefore, j (k) for example, when the circuit AC is an analog-to-digital conversion circuit that converts to a 1-bit digital signal, the terminal mbt2 is one, and when the circuit AC is an analog-to-digital conversion circuit that converts to a k-bit (k is an integer of 2 or more) digital signal, the terminal m bt2 is k. In FIG. 5, the terminal mbt2 is illustrated as a plurality of terminals. As an example, the circuit AC performs analog-to-digital conversion based on a plurality of predetermined potentials, converts the analog potential (or multi-valued digital value) of the terminal mbt1 into a digital signal, and outputs it. In particular, when applying the circuit ACTF[j] in FIG. 5 as the circuit of the activation function of a neuron in a hierarchical neural network, for example, in the analog-to-digital conversion, when the potential of the terminal mbt1 of the circuit AC is lower than the potential given by the wiring VCN3 (when the result of the sum of products of the first data and the second data is negative), instead of outputting that value, by configuring it to output zero, the circuit of the activation function can operate as a circuit that outputs the value of the step function. The circuit IVTR is a circuit having a function of converting the current flowing through the wiring OL[j] into a voltage value (or charge amount). The circuit IVTRr is a circuit having a function of converting the current flowing through the wiring OLB[j] into a voltage value (or charge amount), and has the same configuration as the circuit IVTR. value (or charge amount), and has the same configuration as the circuit IVTR. value (or charge amount), and has the same configuration as the circuit IVTR.

[0124] In particular, when applying the circuit ACTF[j] in FIG. 5 as the circuit of the activation function of a neuron in a hierarchical neural network, for example, in the analog-to-digital conversion, when the potential of the terminal mbt1 of the circuit AC is lower than the potential given by the wiring VCN3 (when the result of the sum of products of the first data and the second data is negative), instead of outputting that value, by configuring it to output zero, the circuit of the activation function can operate as a circuit that outputs the value of the step function. In particular, when applying the circuit ACTF[j] in FIG. 5 as the circuit of the activation function of a neuron in a hierarchical neural network, for example, in the analog-to-digital conversion, when the potential of the terminal mbt1 of the circuit AC is lower than the potential given by the wiring VCN3 (when the result of the sum of products of the first data and the second data is negative), instead of outputting that value, by configuring it to output zero, the circuit of the activation function can operate as a circuit that outputs the value of the step function. value (or charge amount), and has the same configuration as the circuit IVTR. value (or charge amount), and has the same configuration as the circuit IVTR. value (or charge amount), and has the same configuration as the circuit IVTR. value (or charge amount), and has the same configuration as the circuit IVTR.

[0125] The circuit IVTR is a circuit having a function of converting the current flowing through the wiring OL[j] into a voltage value (or charge amount). value (or charge amount). The circuit IVTRr is a circuit having a function of converting the current flowing through the wiring OLB[j] into a voltage value (or charge amount), and has the same configuration as the circuit IVTR. As a result, in the circuit ACTF[j] of FIG. The current flowing through the wiring OL[j] is converted into a voltage value (or charge amount), and the voltage value is switched. The first terminal of the switch SWR1 can be connected to the circuit IVT R, and the current flows to the wiring OLB[j]. The current flowing through the switch SWR1B is converted into a voltage value (or charge amount), and the voltage value is applied to the first terminal of the switch SWR1B. can be given to a child.

[0126] The circuit IVTR (circuit IVTRr) has a circuit configuration shown in, for example, FIGS. 6A to 6C. In order to distinguish between the circuit IVTR and the circuit IVTrr, In C, the symbols for the wiring OLB[j] and the circuit elements included in the circuit IVT R are written in parentheses. is doing.

[0127] The circuit IVTR (circuit IVTRr) shown in FIG. 3B) and a capacitance CRT (capacitor CRTB). ]) is the first terminal of the switch SWR3 (switch SWR3B) and the capacitance CRT (capacitor CR TB) and the first terminal of switch SWR3 (switch SWR3 The second terminal of B) is electrically connected to the second terminal of the capacitor CRT (capacitor CRTB) and the wiring VCN4. is connected.

[0128] The switches SWR3 and SWR3B may be, for example, Switch SWR1, Switch SWR1B, Switch SWR2, and Switch SWR2B Any applicable switch can be used.

[0129] The wiring VCN4 functions as a wiring that applies a constant voltage, for example. can be, for example, a high-level potential, a ground potential, or a low-level potential. As an example the wiring VCN4 may be given the same potential as the wiring VSO described later. Also as an example, the wiring VCN4 may be electrically connected to the wiring VSO. That is, the wiring VCN4 and the wiring VSO may be combined into one wiring.

[0130] The circuit IVTR (circuit IVTRr) shown in FIG. 6A turns on the switch SWR3 (switch SWR 3B) to make the connection between the wiring OL[j] (wiring OLB[j]) and the wiring VCN4 conductive, and can apply the fixed voltage of the wiring VCN4 to the wiring OL[j] (wiring OLB[j]). The operation of applying the fixed voltage of the wiring VCN4 to the wiring OL[j] (wiring OLB[j]) corresponds to an initial operation for reading information (such as current and voltage) from the circuits MP[1,j] to MP[m,j]. Or it corresponds to an operation of initializing the charge stored in the capacitor CRT (capacitor CRTB). Also, the circuit IVTR (circuit IVTRr) shown in FIG. 6A turns off the switch SWR3 (switch SWR3B) to charge the first terminal of the capacitor CRT with the amount of current flowing through the wiring OL[j] (wiring OLB[j]) as charge. That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through the wiring OL[j] (wiring OLB[j]).

[0131] Also, the amount of current flowing through the wiring OL[j] (wiring OLB[j]) can be, as an example, the sum of the currents flowing between the circuits MP [1,j] to MP[m,j] and the wiring OL[j] (wiring OLB[j]). Therefore, the circuits MP[1,j] to MP[m,j ​​The current flowing between each of [] and the wiring OL[j] (wiring OLB[j]) is allowed to flow for a certain period of time, so that the charge charged to the first terminal of the capacitor CRT is determined by the amount of current flowing through the wiring OL[j (wiring OLB[j]) and the certain period of time. That is, the voltage applied to the first terminal of the circuit IVTRr (circuit IVTRr) by the switch SWR1 (switch SWR1B) is determined by the amount of current flowing through each of the circuits MP[1,j] to MP[m,j and the time.

[0132] By the way, when the current flowing through the wiring OL[j] (wiring OLB[j]) is converted into a voltage due to the parasitic resistance or parasitic capacitance related to the wiring OL[j] (wiring OLB[j]), the circuit I VTR (circuit IVTRr) can have the circuit configuration shown in FIG. 6B. That is, the capacitor CRT (capacitor CRTB) can be omitted in the circuit IVTR (circuit IVTRr) of FIG. 6 A.

[0133] The circuit IVTR (circuit IVTRr) shown in FIG. 6C has a switch SWR3 (switch SWR 3B) and a resistor RRT (resistor RRTB). The wiring OL[j] (wiring OLB[j ) is electrically connected to the first terminal of the switch SWR3 (switch SWR3B) and the first terminal of the resistor RRT (resistor RR TB). The second terminal of the switch SWR3 (switch SWR3 B) is electrically connected to the second terminal of the resistor RRT (resistor RRTB) and the wiring VCN4.

[0134] The circuit IVTR (circuit IVTRr) shown in FIG. 6C connects the wiring OL[j] (wiring OLB[j]) and the wiring VCN4 by turning on the switch SWR3 (switch SWR 3B). ​​​​​can be made conductive, and a constant voltage of wiring VCN4 can be applied to wiring OL[j] (wiring OLB[j]). Applying a constant voltage of wiring VCN4 to wiring OL[j] (wiring OLB[j]) corresponds to an initial operation for reading information (such as current and voltage) from circuits MP[1,j] to MP[m,j]. Also, the circuit IVTR (circuit IVTRr) shown in FIG. 6C makes the switch SWR3 (switch SWR3B) in the off state, so that the amount of current flowing through wiring OL[j] (wiring OLB[j]) flows through the resistor RRT (resistor RRTB) and then through wiring VCN4 without passing through the switch SWR3 (switch SWR3B). At this time, a voltage corresponding to the resistance value of the resistor RRT (resistor RRTB) and the amount of current is generated between the first terminal and the second terminal of the resistor RRT (resistor RRTB). That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through wiring OL[j] (wiring OLB[j]) and the resistance value of the resistor RRT (resistor RRTB). Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided. can be applied. The operation of applying a constant voltage of wiring VCN4 to wiring OL[j] (wiring OLB[j]) corresponds to an initial operation for reading information (such as current and voltage) from circuits MP[1,j] to MP[m,j]. from circuits MP[1,j] to MP[m,j] (such as current and voltage). voltage). Also, the circuit IVTR (circuit IVTRr) shown in FIG. 6C makes the switch SWR3 (switch SWR3B) in the off state, so that the amount of current flowing through wiring OL[j] (wiring OLB[j]) flows through the resistor RRT (resistor RRTB) and then through wiring VCN4 without passing through the switch SWR3 (switch SWR3B). At this time, a voltage corresponding to the resistance value of the resistor RRT (resistor RRTB) and the amount of current is generated between the first terminal and the second terminal of the resistor RRT (resistor RRTB). That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through wiring OL[j] (wiring OLB[j]) and the resistance value of the resistor RRT (resistor RRTB). Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided. The amount of current flowing through wiring OL[j] (wiring OLB[j]) flows through the resistor RRT (resistor RRTB) and then through wiring VCN4 without passing through the switch SWR3 (switch SWR3B). At this time, a voltage corresponding to the resistance value of the resistor RRT (resistor RRTB) and the amount of current is generated between the first terminal and the second terminal of the resistor RRT (resistor RRTB). That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through wiring OL[j] (wiring OLB[j]) and the resistance value of the resistor RRT (resistor RRTB). Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided. At this time, a voltage corresponding to the resistance value of the resistor RRT (resistor RRTB) and the amount of current is generated between the first terminal and the second terminal of the resistor RRT (resistor RRTB). That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through wiring OL[j] (wiring OLB[j]) and the resistance value of the resistor RRT (resistor RRTB). Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided. resistor RRTB) and the amount of current is generated between the first terminal and the second terminal of the resistor RRT (resistor RRTB). That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through wiring OL[j] (wiring OLB[j]) and the resistance value of the resistor RRT (resistor RRTB). Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided. At this time, a voltage corresponding to the resistance value of the resistor RRT (resistor RRTB) and the amount of current is generated between the first terminal and the second terminal of the resistor RRT (resistor RRTB). That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through wiring OL[j] (wiring OLB[j]) and the resistance value of the resistor RRT (resistor RRTB). Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided. The potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through wiring OL[j] (wiring OLB[j]) and the resistance value of the resistor RRT (resistor RRTB). Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided. Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided.

[0135] Next, an example of a circuit configuration applicable to the circuit ACTF[j] in FIG. 2, which is different from the circuit ACTF[j] in FIG. 5, will be described. will be described.

[0136] The circuit ACTF[j] shown in FIG. 7A is an example of a circuit configuration obtained by changing the circuit configuration of the circuit ACTF[j] in FIG. 5. Specifically, it is different from the circuit ACTF[j] in FIG. 5 in that the terminal mbt1 of circuit AC is electrically connected to the second terminal of switch SWR2, and wiring VCN3 is electrically connected to the second terminal of switch SWR2B. The circuit ACTF[j] shown in FIG. 7A is an example of a circuit configuration obtained by changing the circuit configuration of the circuit ACTF[j] in FIG. 5. Specifically, it is different from the circuit ACTF[j] in FIG. 5 in that the terminal mbt1 of circuit AC is electrically connected to the second terminal of switch SWR2, and wiring VCN3 is electrically connected to the second terminal of switch SWR2B. the second terminal of switch SWR2B. is electrically connected to the second terminal of switch SWR2B.

[0137] In addition, as a circuit configuration applicable to the circuit ACTF[j] in FIG. 2, for example, as shown in FIG. 7B a circuit ACTF[j] can be used. The circuit ACTF[j] in FIG. 7B includes a switch S WR2, a switch SWR2B, a switch SWR6, a switch SWR6B, a switch SWR7, a switch SWR7B, a capacitor CRE, a circuit IVTR, a circuit IVTRr and a circuit AC.

[0138] The first terminal of the switch SWR6 is electrically connected to the terminal T1, and the second terminal of the switch SWR6 is electrically connected to the first terminal of the switch SWR7, the first terminal of the switch SWR2, and the first terminal of the capacitor CRE. The second terminal of the switch SWR7 is electrically connected to the circuit IVT R, and the second terminal of the switch SWR2 is electrically connected to the wiring VCN3 . The first terminal of the switch SWR6B is electrically connected to the terminal T2, and the second terminal of the switch SWR6B is electrically connected to the first terminal of the switch SWR7B, the first terminal of the switch SWR2B and the second terminal of the capacitor CRE. The second terminal of the switch SWR7B is electrically connected to the circuit IVTRr, and the second terminal of the switch SWR2B is electrically connected to the circuit AC .

[0139] For each of the switch SWR6, the switch SWR6B, the switch SWR7, and the switch SWR7B , for example, switches applicable in the same manner as the aforementioned switch SWR1, switch SWR1B, switch SWR2, and switch SWR2B can be used .

[0140] Regarding each of the circuit AC, the circuit IVTR, and the circuit IVTRr, the circuit AC in FIG. 5 ​Refer to the descriptions of circuit AC, circuit IVTR, and circuit IVTRr included in TF[j]. for reference.

[0141] In addition, as a circuit configuration applicable to the circuit ACTF[j] in FIG. 2A, for example, it can be the circuit ACTF[j] shown in FIG. 7C. The circuit ACTF[j] in FIG. 7C has a configuration in which the switch SWR7 and the switch SWR2B are not provided in the circuit ACTF[j] in FIG. 7B. That is, in the circuit ACTF[j] in FIG. 7C, the second terminal of the switch SWR6 is electrically connected to the circuit IVTR, and the terminal mbt1 of the circuit AC is electrically connected to the second terminal of the capacitor CRE, the second terminal of the switch SWR6B, and the first terminal of the switch SWR7B. shown circuit ACTF[j]. The circuit ACTF[j] in FIG. 7C has a configuration in which the switch SWR7 and the switch SWR2B are not provided in the circuit ACTF[j] in FIG. 7B. That is, in the circuit ACTF[j] in FIG. 7C, the second terminal of the switch SWR6 is electrically connected to the circuit IVTR, and the terminal mbt1 of the circuit AC is electrically connected to the second terminal of the capacitor CRE, the second terminal of the switch SWR6B, and the first terminal of the switch SWR7B. configured without the switch SWR7 and the switch SWR2B in the circuit ACTF[j] of FIG. 7B. That is, in the circuit ACTF[j] of FIG. 7C, the second terminal of the switch SWR6 is electrically connected to the circuit IVTR, and the terminal mbt1 of the circuit AC is the second terminal of the capacitor CRE and the second terminal of the switch SWR6B and the first terminal of the switch SWR7B are electrically connected.

[0142] By applying any one of the circuits ACTF[j] in FIGS. 7A to 7C to the circuit ACTF[j] in FIG. 2, similar to the circuit ACTF[j] in FIG. 5, as a result corresponding to the sum of products of the first data and the second data, the signal z can be output. as a result corresponding to the sum of products of the first data and the second data, the signal z j (k) can be output.

[0143] <Operation Example 2 of the Arithmetic Circuit> Subsequently, the operation example of the circuit ACTF[j] in FIG. 5 will be described. In the description of this operation example as an example, the arithmetic circuit 110A shown in FIG. 8 is used. The arithmetic circuit 110A has a configuration in which the circuit IVTR and the circuit IVTRr included in the circuit ACTF[j] shown in FIG. 5 are the circuit IVTR (circuit IVTRr) in FIG. 6A. applied. configured by applying the circuit IVTR (circuit IVTRr) in FIG. 6A.

[0144] In addition, in FIG. 8, as an example, the switches SWR1, switch SWR2, switch SWR3, switch SWR1B, switch SWR2B, switch SWR As wiring for switching between the on-state and off-state of each of the switches SWR3B, wiring SRL1, wiring SRL2-1, wiring SRL2-2, and wiring SRL3 are shown in the figure. Specifically, wiring SRL1 is electrically connected to the control terminal of switch SWR1 and the control terminal of switch SWR1B, wiring SRL2-1 is electrically connected to the control terminal of switch SWR2, wiring SRL2-2 is electrically connected to the control terminal of switch SWR2B, and wiring SRL3 is electrically connected to the control terminal of switch SWR3 and the control terminal of switch SWR3B. Note that, for example, switches SWR1, SWR2, SWR3, SWR1B, SWR2B, or switch SWR3 B may, in some cases or depending on the situation, omit some of them. That is, for example, switches SWR1, SWR2, SWR1B, and switch SWR2B may have a circuit configuration in which some of these switches are always in the on-state. Also, for example, by using other switches, switches SWR3 and SWR3B may have a circuit configuration in which some of these switches are always in the off-state. Or, for example, switches SWR1, SWR2, SWR3, SWR1B, SWR2B, and SWR3B may also change a part of the connection configuration. Note that, for example, wiring SRL1, wiring SRL2- 1, wiring SRL2-2, or wiring SRL3 may, in some cases or depending on the situation, omit some of them. For example, wiring SRL2-1 and wiring SRL2- 2, or wiring SRL3 may, in some cases or depending on the situation, omit some of them. For example, wiring SRL2-1 and wiring SRL2- 2 may be combined into a single wiring. Or, for example, by reversing the on / off polarities of switch SWR1 and switch SWR2 (switch SWR2B), wiring SRL1 and wiring SRL2-1 (wiring SRL2-2) may be combined into a single wiring. This enables switch SWR1 and switch SWR2 (switch SWR2B) to be turned on and off alternately with a single wiring. 2 may be combined into a single wiring. Or, for example, by reversing the on / off polarities of switch SWR1 and switch SWR2 (switch SWR2B), wiring SRL1 and wiring SRL2-1 (wiring SRL2-2) may be combined into a single wiring. This enables switch SWR1 and switch SWR2 (switch SWR2B) to be turned on and off alternately with a single wiring. 2 may be combined into a single wiring. Or, for example, by reversing the on / off polarities of switch SWR1 and switch SWR2 (switch SWR2B), wiring SRL1 and wiring SRL2-1 (wiring SRL2-2) may be combined into a single wiring.

[0145] Also, in FIG. 8, node n4 is illustrated as the electrical connection point of the first terminal of switch SWR1, the first terminal of capacitor CRT, and the first terminal of switch SWR3, and node n4r is illustrated as the electrical connection point of the first terminal of switch SWR1B, the first terminal of capacitor CRTB, and the first terminal of switch SWR3B. Further, node n5 is illustrated as the electrical connection point of the second terminal of switch SWR1, the first terminal of capacitor CRE, and the first terminal of switch SWR2, and node n5r is illustrated as the electrical connection point of the second terminal of switch SWR1B, the second terminal of capacitor CRE, and the first terminal of switch SWR2B. Also, in FIG. 8, node n4 is illustrated as the electrical connection point of the first terminal of switch SWR1, the first terminal of capacitor CRT, and the first terminal of switch SWR3, and node n4r is illustrated as the electrical connection point of the first terminal of switch SWR1B, the first terminal of capacitor CRTB, and the first terminal of switch SWR3B. Further, node n5 is illustrated as the electrical connection point of the second terminal of switch SWR1, the first terminal of capacitor CRE, and the first terminal of switch SWR2, and node n5r is illustrated as the electrical connection point of the second terminal of switch SWR1B, the second terminal of capacitor CRE, and the first terminal of switch SWR2B. Also, in FIG. 8, node n4 is illustrated as the electrical connection point of the first terminal of switch SWR1, the first terminal of capacitor CRT, and the first terminal of switch SWR3, and node n4r is illustrated as the electrical connection point of the first terminal of switch SWR1B, the first terminal of capacitor CRTB, and the first terminal of switch SWR3B. Further, node n5 is illustrated as the electrical connection point of the second terminal of switch SWR1, the first terminal of capacitor CRE, and the first terminal of switch SWR2, and node n5r is illustrated as the electrical connection point of the second terminal of switch SWR1B, the second terminal of capacitor CRE, and the first terminal of switch SWR2B. Also, in FIG. 8, node n4 is illustrated as the electrical connection point of the first terminal of switch SWR1, the first terminal of capacitor CRT, and the first terminal of switch SWR3, and node n4r is illustrated as the electrical connection point of the first terminal of switch SWR1B, the first terminal of capacitor CRTB, and the first terminal of switch SWR3B. Further, node n5 is illustrated as the electrical connection point of the second terminal of switch SWR1, the first terminal of capacitor CRE, and the first terminal of switch SWR2, and node n5r is illustrated as the electrical connection point of the second terminal of switch SWR1B, the second terminal of capacitor CRE, and the first terminal of switch SWR2B. Also, in FIG. 8, node n4 is illustrated as the electrical connection point of the first terminal of switch SWR1, the first terminal of capacitor CRT, and the first terminal of switch SWR3, and node n4r is illustrated as the electrical connection point of the first terminal of switch SWR1B, the first terminal of capacitor CRTB, and the first terminal of switch SWR3B. Further, node n5 is illustrated as the electrical connection point of the second terminal of switch SWR1, the first terminal of capacitor CRE, and the first terminal of switch SWR2, and node n5r is illustrated as the electrical connection point of the second terminal of switch SWR1B, the second terminal of capacitor CRE, and the first terminal of switch SWR2B. Also, in FIG. 8, node n4 is illustrated as the electrical connection point of the first terminal of switch SWR1, the first terminal of capacitor CRT, and the first terminal of switch SWR3, and node n4r is illustrated as the electrical connection point of the first terminal of switch SWR1B, the first terminal of capacitor CRTB, and the first terminal of switch SWR3B. Further, node n5 is illustrated as the electrical connection point of the second terminal of switch SWR1, the first terminal of capacitor CRE, and the first terminal of switch SWR2, and node n5r is illustrated as the electrical connection point of the second terminal of switch SWR1B, the second terminal of capacitor CRE, and the first terminal of switch SWR2B. Also, in FIG. 8, node n4 is illustrated as the electrical connection point of the first terminal of switch SWR1, the first terminal of capacitor CRT, and the first terminal of switch SWR3, and node n4r is illustrated as the electrical connection point of the first terminal of switch SWR1B, the first terminal of capacitor CRTB, and the first terminal of switch SWR3B. Further, node n5 is illustrated as the electrical connection point of the second terminal of switch SWR1, the first terminal of capacitor CRE, and the first terminal of switch SWR2, and node n5r is illustrated as the electrical connection point of the second terminal of switch SWR1B, the second terminal of capacitor CRE, and the first terminal of switch SWR2B.

[0146] FIG. 9 is a timing chart showing an operation example of circuit ACTF[j] of arithmetic circuit 110A in FIG. 8. The timing chart shows the potential fluctuations of wirings XLS[1] to XLS[m], wiring SRL1, wiring SRL2-1, wiring SRL2-2, wiring SRL3, node n4, node n4r, node n5, and node n5r from time T01 to time T08 and in the vicinity thereof. Note that high shown in FIG. 9 indicates a high-level potential, and low indicates a low-level potential. FIG. 9 is a timing chart showing an operation example of circuit ACTF[j] of arithmetic circuit 110A in FIG. 8. The timing chart shows the potential fluctuations of wirings XLS[1] to XLS[m], wiring SRL1, wiring SRL2-1, wiring SRL2-2, wiring SRL3, node n4, node n4r, node n5, and node n5r from time T01 to time T08 and in the vicinity thereof. Note that high shown in FIG. 9 indicates a high-level potential, and low indicates a low-level potential. FIG. 9 is a timing chart showing an operation example of circuit ACTF[j] of arithmetic circuit 110A in FIG. 8. The timing chart shows the potential fluctuations of wirings XLS[1] to XLS[m], wiring SRL1, wiring SRL2-1, wiring SRL2-2, wiring SRL3, node n4, node n4r, node n5, and node n5r from time T01 to time T08 and in the vicinity thereof. Note that high shown in FIG. 9 indicates a high-level potential, and low indicates a low-level potential. FIG. 9 is a timing chart showing an operation example of circuit ACTF[j] of arithmetic circuit 110A in FIG. 8. The timing chart shows the potential fluctuations of wirings XLS[1] to XLS[m], wiring SRL1, wiring SRL2-1, wiring SRL2-2, wiring SRL3, node n4, node n4r, node n5, and node n5r from time T01 to time T08 and in the vicinity thereof. Note that high shown in FIG. 9 indicates a high-level potential, and low indicates a low-level potential. FIG. 9 is a timing chart showing an operation example of circuit ACTF[j] of arithmetic circuit 110A in FIG. 8. The timing chart shows the potential fluctuations of wirings XLS[1] to XLS[m], wiring SRL1, wiring SRL2-1, wiring SRL2-2, wiring SRL3, node n4, node n4r, node n5, and node n5r from time T01 to time T08 and in the vicinity thereof. Note that high shown in FIG. 9 indicates a high-level potential, and low indicates a low-level potential. FIG. 9 is a timing chart showing an operation example of circuit ACTF[j] of arithmetic circuit 110A in FIG. 8. The timing chart shows the potential fluctuations of wirings XLS[1] to XLS[m], wiring SRL1, wiring SRL2-1, wiring SRL2-2, wiring SRL3, node n4, node n4r, node n5, and node n5r from time T01 to time T08 and in the vicinity thereof. Note that high shown in FIG. 9 indicates a high-level potential, and low indicates a low-level potential.

[0147] In this operation example, each of switch SWR1, switch SWR2, switch SWR1B , and switch SWR2B is assumed to be in the on state when a high-level potential is input to the control terminal and in the off state when a low-level potential is input to the control terminal.

[0148] Also, the timing chart in FIG. 9 shows the wirings XLS[1] to XLS[m] collectively. In the timing chart of FIG. 9, the period during which the second data is input to the wirings XLS[1] to XLS [m] is indicated by hatching.

[0149] In this operation example, it is assumed that current flows from the wiring OL[j] to the circuit MP and also from the wiring OLB j] to the circuit MP. Therefore, a wiring (for example, the wirings VE and VEr described in Embodiment 2) that supplies VSS (low-level potential) is electrically connected to the circuit MP (not shown in FIG. 8), and the constant voltage supplied by the wiring VCN4 is VDD (high-level potential). Also, the amount of current flowing from the wiring OL[j] to the circuit MP and the amount of current flowing from the wiring OLB[j] to the circuit MP are determined by the first data held in the circuit MP and the second data input from the wiring XLS. Also , the amount of current flowing from the wiring OL[j] to the circuit MP and / or the amount of current flowing from the wiring OLB[j] to the circuit MP may be zero. Also, the constant voltage supplied by the wiring VCN3 is VS S.

[0150] Before time T01, each of the circuits MP[1,j] to MP[m,j] has the weight coefficients w1 (k-1) j (k) to w m ​​​​​​​(k-1) j (k) shall be maintained.

[0151] Also, before time T01, a low-level potential is input to wirings XLS[1] to XLS[m], and a low-level potential is input to wirings SRL1, SRL2-1, SRL2-2, and SRL3. Further, the potentials of nodes n4, n4r, n5, and n5r are set to VSS.

[0152] Between time T01 and time T02, a high-level potential is input to wirings SRL1 and SRL3. When a high-level potential is input to wiring SRL1, switches SWR1 and SWR1B turn on, and when a high-level potential is input to wiring SRL3, switches SWR3 and SWR3B turn on.

[0153] Also, between time T01 and time T02, a low-level potential is input to wirings SRL2-1 and SRL2-2. When a low-level potential is input to wirings SRL2-1 and SRL2-2, switches SWR2 and SWR2B turn off.

[0154] As a result, conduction is established between wiring VCN4 and wiring OL[j], and between wiring VCN4 and the first terminal of capacitor CRE. Also, conduction is established between wiring VCN4 and wiring OLB[j], between wiring VCN4 and the second terminal of capacitor CRE, and between wiring VCN4 and terminal mbt1. Also, non-conduction is established between wiring VCN3 and the first terminal of capacitor CRE. For this reason, ​​​​​​​​​​​​​​The potentials of node n4, node n4r, node n5, and node n5r are all VD D.

[0155] During the period from time T02 to time T03, a low-level potential is input to wiring SRL3 . When a low-level potential is input to wiring SRL3, switches SWR3 and S WR3B turn off. As a result, the connection between wiring VCN4 and wiring OL[j] becomes non-conductive, the connection between wiring VCN4 and wiring OLB[j] becomes non-conductive, and nodes n4, node n5, node n4r, and node n5r are in a floating state.

[0156] During the period from time T03 to time T04, for each of circuits MP[1,j] to MP[m,j] in array section ALP, neuron signals z1 to z (k -1) as the second data are sent. m (k-1)

[0157] As a result, in circuit MP[i,j], according to weight coefficient w i (k-1) j (k) and neuron signal z1 , a current flows between one of wiring OL[j] or wiring OLB[j] and circuit MC, and a current flows between the other of wiring OL[j] or wiring OLB[j] and circuit MCr (k-1) . Here, let the sum of the currents flowing between each of circuits MP[1,j] to MP[m,j] and wiring OL[j] be I [j], and let the sum of the currents flowing between each of circuits MP[1,j] to MP[m,j] and wiring OLB[j] be I . out Let the sum of the currents flowing between each of circuits MP[1,j] to MP[m,j] and wiring OL[j] be I[j], and let the sum of the currents flowing between each of circuits MP[1,j] to MP[m,j] and wiring OLB[j] be I [j]. Bo ut ​

[0158] At this time, the potentials of node n4 and node n5 are determined by the current flowing through wiring OL[j]. They decrease, and the potentials of node n4r and node n5r decrease due to the current flowing through wiring OLB[j]. They decrease.

[0159] In this operation example, assume that I Bout [j] is larger than I out [j]. Therefore, the potential drops of node n4 and node n5 from time T03 to time T04 are assumed to be larger than the potential drops of node n4r and node n5r. In the timing chart of Fig. 9, at time T04, the potentials of node n4 and node n5 drop to V and the potentials of node n4r and node n5r drop to V as shown. I out up to a certain level, and the potentials of node n4r and node n5r drop to V IBout up to a certain level. It is assumed so.

[0160] Also, at time T04, a low-level potential is input to wiring SRL1. When a low-level potential is input to wiring SRL 1, switches SWR1 and SWR1B turn off. As a result, the connection between the first terminal of capacitor CRE and wiring OL[j] becomes non-conductive, and the connection between the second terminal of capacitor CRE and wiring OLB[j] becomes non-conductive. Thus, the potential drop at the first terminal (node n5) of capacitor CRE stops, and the potential drop at the second terminal (node n5r) of capacitor CRE stops. Also, the voltage between the first terminal (node n5) and the second terminal (node n5r) of capacitor CRE is held. The potentials of node n4 and node n4r continue to decrease as before time T04. become non-conductive states. As a result, the potential drop at the first terminal (node n5) of capacitor CRE stops, and the potential drop at the second terminal (node n5r) of capacitor CRE stops. Also, the voltage between the first terminal (node n5) and the second terminal (node n5r) of capacitor CRE is held. The potentials of node n4 and node n4r continue to decrease as before time T04. terminal (node n5) of capacitor CRE stops, and the potential drop at the second terminal (node n5r) of capacitor CRE stops. Also, the voltage between the first terminal (node n5) and the second terminal (node n5r) of capacitor CRE is held. The potentials of node n4 and node n4r continue to decrease as before time T04. node n5) of capacitor CRE and the second terminal (node n5r) of capacitor CRE is held. The potentials of node n4 and node n4r continue to decrease as before time T04. node n4 and node n4r continue to decrease as before time T04.

[0161] During the period from time T05 to time T06, low-level potentials are input to each of wirings XLS[1] to XLS[m]. As a result, for each of circuits MP[1, j] to MP[m,j] of the array unit ALP, the signals of neurons corresponding to the second data z1 (k-1) to z m (k-1) are stopped from being supplied. Thereby, the current flowing from wiring OLj to circuit MP stops, and the current flowing from wiring OLBj to circuit MP stops . Therefore, the decrease in the potential of each of node n4 and node n4r stops.

[0162] During the period from time T06 to time T07, a high-level potential is applied to wiring SRL2-1. When a high-level potential is input to wiring SRL2-1, switch SWR2 becomes in an on state. For this reason, a conductive state is established between the first terminal of capacitor CRE and wiring VCN3 , and the potential of the first terminal (node n5) of capacitor CRE becomes VSS.

[0163] By the way, since the second terminal (node n5r) of capacitor CRE is in a floating state, when the potential of the first terminal (node n5) of capacitor CRE changes from V Iout to VSS, the potential of the second terminal (node n5r) of capacitor CRE also changes due to capacitive coupling. Note that the amount of change in potential due to capacitive coupling is determined according to the capacitive coupling coefficient. However, in this specification and the like, for simplicity of explanation, when the potential of the first terminal of capacitor CRE changes from V to VSS, Iout the potential of the second terminal of capacitor CRE is V -(V IBout -VSS) (in the timing chart of FIG. 9, V Iout -VSS)(In the timing chart of FIG. 9, V In the timing chart of FIG. 9, V OPIt is assumed that it changes to (expressed as). That is, this potential change corresponds to the case where the capacitance coupling coefficient determined according to the capacitance CRE and the surrounding circuit elements is set to 1. .

[0164] During the period from time T07 to time T08, a high-level potential is applied to the wiring SRL2-2. When a high-level potential is applied to the wiring SRL2-2, the switch SWR2B turns on. As a result, the second terminal (node n5r) of the capacitance CRE and the terminal mbt1 are in a conductive state.

[0165] At this time, the potential V of the second terminal (node n5r) of the capacitance CRE is input to the terminal mbt1 of the circuit AC. OP

[0166] Thereby, the circuit AC outputs a digital signal corresponding to the potential V input to the terminal mbt1. OP j (k) A signal with the value of z is output.

[0167] z j (k) is a value output based on the potential difference between the potential V corresponding to the current flowing through the wiring OL[j] and the potential V corresponding to the current flowing through the wiring OLB[j]. That is, the potential V and the potential V are determined by I[j] and I Iout [j], and the time when the switches SWR1 and SWR2 are in the on state (the time from time T03 to time T04). I[j] and I IBout Iout IBout out [j] and I Bout j], and the time when the switches SWR1 and SWR2 are in the on state (the time from time T03 to time T04). I[j] and I 3 to time T04), and are held in each of the circuits MP[1,j] to MP[m,j]. out Bout [j] are the first​ The first data w1 which is data (k-1) j (k) to w m (k-1) j (k) and the circuit M The value z1 of the signal which is the second data input to P[1, j] to MP[m, j] (k- 1) to z m (k-1) and the result of the sum-of-products operation, that is, u in Expression (1.2) j (k) According to is the current. On the other hand, the potential V Iout The potential V IBout is, since the switches SWR1 and SWR change according to the time when the switches SWR2 are in the on state (the time from time T03 to time T04), it is preferable that the time is appropriately set according to the circuit AC .

[0168] In this operation example, by converting each of I out [j] and I Bout [j] into a potential and inputting the potential difference between them into the circuit AC, the value of z is output j (k) . That is, by using the circuit AC as the circuit of the activation function in the hierarchical neural network the value of z output as a digital signal can be made the potential corresponding to z in Expression (1.4) j (k) j (k ) ) .

[0169] By the way, during the period from time T07 to time T08, when the switch SWR2B becomes in the on state strictly speaking, considering the influence of parasitic resistance, parasitic capacitance, etc., at the terminal mb ​The potential input to t1 is V OP may vary. In this case, the circuit AC takes into account the resistance of the wiring between the second terminal of the capacitor C and the terminal mbt1, and is preferably designed to appropriately correct the potential input to the terminal mbt1 .

[0170] Also, in the above operation example, the case where I Bout [j] is larger than I out [j] was described . On the other hand, when I out [j] is larger than I Bout [j], at time T04 , the potential of node n5r, V Iout , is lower than the potential of node n5, V IBout . For this reason, when the switch SWR2 is in the ON state between time T06 and time T07 , the potential of node n5r becomes a potential lower than VSS due to the capacitive coupling of the capacitor CRE . Then, between time T07 and time T08, a potential lower than VSS is input to the terminal mbt1. At this time, as the configuration of the circuit AC, for example, the terminal mbt2 may be configured to output a digital signal corresponding to 0 as the output signal z j (k) . This corresponds to the activation function f(u j (k) ) in the hierarchical neural network functioning as a ramp function that outputs 0 when u j (k ) is negative.

[0171] <Configuration Example 3 of the Arithmetic Circuit> Note that one aspect of the present invention is not limited to the circuit configuration of the circuit ACTF[j] in FIG. 5 included in the arithmetic circuit. For example, in the semiconductor device (arithmetic circuit) of one aspect of the present invention, FIG. included The circuit ACTF[j] of 5 is to be changed to the circuit configuration shown in the circuit ACTF[j] of FIG. 10 is possible. The circuit ACTF[j] of FIG. 10 includes a switch SWR1, a switch SWR1B, , a switch SWR2, a switch SWR2B, a switch SWR3, a switch SWR3 B, a switch SWR4, a switch SWR4B, a load LE, a load LEB, an op-amp OP, an op-amp OPB, and a circuit AC. Note that the description of the parts overlapping with the circuit ACT F[j] shown in FIG. 5 is omitted.

[0172] Each of the switch SWR3, the switch SWR3B, the switch SWR4, and the switch SWR4B can be, for example, a switch that can be applied in the same manner as the switch SWR1, the switch SWR1B, the switch SWR2, and the switch SWR2B.

[0173] The first terminal of the switch SWR3 is electrically connected to the terminal T1, the first terminal of the switch SWR4, and the first terminal of the load L E. The second terminal of the switch SWR3 is electrically connected to the wiring VC N4. The non-inverting input terminal of the op-amp OP is electrically connected to the wiring Vref1L , the inverting input terminal of the op-amp OP is electrically connected to the second terminal of the switch SWR4, and the output terminal of the op-amp OP is electrically connected to the second terminal of the load LE and the first terminal of the switch SW R1.

[0174] The first terminal of the switch SWR3B is electrically connected to the terminal T2, the first terminal of the switch SWR4B, and the first terminal of the negative load LEB. The first terminal of the switch SWR3B is electrically connected to the wiring VCN4. The non-inverting input terminal of the op-amp OPB is connected to the wiring V is electrically connected to ref2L, and the inverting input terminal of the operational amplifier OPB is the switch SWR4 is electrically connected to the second terminal of B, and the output terminal of the operational amplifier OPB is electrically connected to the second terminal of the load LEB and the first terminal of the switch SWR1B.

[0175] Note that the wirings Vref1L and Vref2L here function as wirings that supply the same voltage or different voltages to each other. Therefore, the wirings Vref1L and Vref2 L may be combined into one wiring in some cases.

[0176] The circuit ACTF[j] in FIG. 10 can perform an initial operation of applying the constant voltage of the wiring VCN4 to the wiring OL[j] (wiring OLB[j]) in the same manner as in FIG. 10 by turning on the switch SWR3 (switch SWR3B) and turning off the switch SWR4 (switch SWR4B).

[0177] In the circuit ACTF[j] of FIG. 10, the loads LE and LEB can be, for example, resistors , capacitors, etc. In particular, by using capacitors as the loads LE and LEB, the operational amplifier OP and the load LE, and the operational amplifier OPB and the load LEB each function as an integrating circuit. That is, by turning off the switches SWR3 and SWR3B and turning on the switches SWR4 and SWR4B, charges are stored in the respective capacitors (loads LE and LEB ) according to the amount of current flowing through the wiring OL[j] or the wiring OLB[j]. That is, the current flowing from the wirings OL[j] and OLB[j] is converted into a voltage by the integrating circuit, and the respective voltages are output from the output terminals of the operational amplifier OP and the operational amplifier OPB. ) ​​​​​​​​​

[0178] By making the loads LE and LEB capacitive, the circuit ACTF[j] in FIG. 10 is The amount of charge flowing through the line OL[j] is converted into a voltage value, and the voltage value is applied to the first The charge flowing through the wiring OLB[j] can be converted into a voltage value, This voltage value can be provided to a first terminal of switch SWR1B.

[0179] The circuit ACTF[j] in FIG. 5 has a circuit configuration shown in the circuit ACTF[j] in FIG. 11A. The circuit ACTF[j] in FIG. 11A includes a switch SWR3 and a switch switch SWR3B, switch SWR4, switch SWR4B, switch SWR5, and negative The load LEA, the load LEAB, an operational amplifier OPA, and a circuit AC.

[0180] Switch SWR3, Switch SWR3B, Switch SWR4, Switch SWR4B, Switch For example, the switches SWR1, SWR1B, It can be applied in the same way as the switch SWR2 and the switch SWR2B. Cut.

[0181] The first terminal of the switch SWR3 is connected to the terminal T1, the first terminal of the switch SWR4, and the load L The first terminal of the switch SWR3 is electrically connected to the wiring V Electrically connected to CN4. The inverting input terminal of the operational amplifier OP is connected to the switch SWR4. The second terminal of the load LEA is electrically connected to the first terminal of the switch SWR5. The first terminal of the switch SWR3B is electrically connected to the terminal T2 and the The first terminal of the switch SWR4B and the first terminal of the load LEAB are electrically connected to each other. The second terminal of switch SWR3B is electrically connected to wiring VCN4. The non-inverting input terminal of operational amplifier OP is electrically connected to the second terminal of switch SWR4B. The second terminal of load LEAB is electrically connected to wiring VCN5. The output terminal of operational amplifier OP is electrically connected to the second terminal of switch SWR5 and terminal mbt1 of circuit AC.

[0182] Note that wiring VCN5 functions as a wiring for supplying a constant voltage. As the constant voltage, for example, it can be a ground potential or a low-level potential.

[0183] The circuit ACTF[j] in FIG. 11A can perform an initial operation of applying the constant voltage of wiring VCN4 to wiring OL[j] (wiring OLB[j]) in the same manner as in FIG. 10 by turning on switch SWR3 (switch SWR3B), turning off switch SWR4 (switch SWR4B), and turning off switch SWR5.

[0184] In the circuit ACTF[j] of FIG. 11A, as load LEA and load LEAB, for example, they can be a resistor, a capacitor, etc. Also, when configuring a subtraction circuit using operational amplifier OPA, a resistor can be used as load LEA and load LEAB. By using resistors for load LEA and load LEAB, a voltage corresponding to the difference in current flowing between the first and second terminals of load LEA and between the first and second terminals of load LEAB can be output from the output terminal of operational amplifier OPA. Thereby, switch SWR3 and switch SWR3B are turned off, switch SWR4 and switch SWR4B are turned on, and s witch SWR5 is turned off. By turning on the switch SWR5, a voltage corresponding to the difference in the currents flowing through the wirings OL[j] and OLB[j] can be output from the output terminal of the operational amplifier OPA. This is possible.

[0185] Also, the voltage output from the output terminal of the operational amplifier OPA is input to the input terminal of the circuit AC. As a result, the analog voltage output from the output terminal of the operational amplifier OPA can be converted into a digital signal by the circuit AC. Further, the digital signal can be output as the arithmetic value z of the neuron signal from the terminal mbt2 of the circuit AC. j (k) This is possible.

[0186] Also, the circuit configuration of the circuit ACTF[j] in FIG. 11A may be changed to the circuit ACTF [j] in FIG. 11B. The circuit ACTF[j] in FIG. 11B is configured such that the circuit AC is not provided in the circuit ACTF[j] in FIG. 11A. As a result, the analog voltage output from the output terminal of the operational amplifier OPA can be set as the arithmetic value z of the neuron signal. j (k) This is possible.

[0187] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0188] (Embodiment 2) In this embodiment, the circuit configurations around the arithmetic circuits 110, 110A, and 120 described in the above embodiment, and the operation examples in those arithmetic circuits will be described.

[0189] <Configuration Example 1 of Arithmetic Circuit> ​​​​​​The arithmetic circuit 130 shown in FIG. 12 is, as an example, a semiconductor device having an array section ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP. The arithmetic circuit 130 processes signals z1 (k) to z n (k) input to neurons N1 to N (k-1) in FIGS. 1A and 1B, layer k, and generates signals z1 m (k-1) to z (k) to N n (k) output from each of neurons N1 (k) to N n (k) . It is a circuit that performs such operations.

[0190] Note that the entire arithmetic circuit 130 or a part thereof may be used for applications other than neural networks and AI. For example, when performing multiplication-accumulation operation processing or matrix operation processing in graphic calculations, scientific calculations, etc., the entire arithmetic circuit 130 or a part thereof may be used for the processing. That is, not only for AI calculations, but also for general calculations, the entire arithmetic circuit 130 or a part thereof may be used. Also, for example, the entire arithmetic circuit 130 or a part thereof may be used for applications such as a storage device.

[0191] The circuit ILD is electrically connected to wirings IL[1] to IL[n] and wirings ILB[1] to ILB[n], as an example. The circuit WLD is electrically connected to wirings WLS[1] to WLS[m], as an example. The circuit XLD is electrically connected to wirings XLS[1] to XLS[m], as an example. The circuit AFP is, as an example, the wiring OL[1] to OL[n], and the wiring OLB[1] to OLB[n], are electrically connected thereto.

[0192] <<Array section ALP>> The array section ALP has, for example, m×n circuit elements MP. The circuit elements MP are, for example, arranged in a matrix of m rows and n columns within the array section ALP. In FIG. 12, the circuit element MP located at the i-th row and j-th column (where i is an integer from 1 to m, and j is an integer from 1 to n. ) is denoted as circuit element MP[i,j]. However, in FIG. 1 12, only the circuit elements MP[1,1], MP[m,1], MP[i,j], MP[1 ,n], and MP[m,n] are shown excerpted.

[0193] The circuit element MP[i,j] is, for example, connected electrically to the wiring IL[j], the wiring ILB[j], the wiring W LS[i], the wiring XLS[i], the wiring OL[j], and the wiring OLB[j]. are electrically connected thereto.

[0194] The circuit element MP[i,j] has, for example, the same functions as the circuit elements MP[1,j to MP[m,j] described in the above embodiment. Further, the circuit element MP[i,j] has a function of obtaining the weight coefficient (first data) held in the circuit M P[i,j] from the wiring IL[j] and the wiring ILB j]. In FIG. 12, an example in the case where the wiring IL[j] and the wiring ILB[j are arranged is shown, but one aspect of the present invention is not limited thereto. Either only the wiring IL[j] or the wiring ILB[j] may be arranged.

[0195] Note that specific descriptions of the circuit elements MP[1,1] to MP[m,n] will be described later 。

[0196] <<Circuit XLD>> The circuit XLD in FIG. 12, as an example, via wiring XLS[1] to wiring XLS[m] , for each of circuits MP[1,1] to circuit MP[m,n], neuron N1 (k -1) to neuron N m (k) The calculated values z1 (k-1) to z m ( k-1) (Sometimes referred to as first data or second data. Here, it is regarded as second data .). It has a function of supplying. Specifically, the circuit XLD supplies, to circuits MP[i,1] to circuit MP[i,n], the information (for example, potential, current value, etc.) corresponding to the second data z i (k-1) output from neuron N i (k -1) through wiring XLS[i]. Although an example where wiring XLS[i] is arranged is shown, one aspect of the present invention is not limited thereto. For example, in the arithmetic circuit 130 of FIG. 12, wiring XLS[i] may be multiple wirings.

[0197] <<Circuit WLD>> The circuit WLD in FIG. 12, as an example, has a function of selecting a circuit MP that is the destination for writing information (for example potential, resistance value, current value, etc.) corresponding to the weight coefficient (sometimes referred to as first data or second data. Here, it is regarded as first data.) input from the circuit ILD. For example, circuits MP[i,1] to circuit MP[i,n located in the i-th row of the array unit ALP When writing information (such as potential, resistance value, current value, etc.) to For example, the circuit WLD supplies a signal for turning on or off the writing switching elements included in the circuits MP[i,1] to MP[i,n] to the wiring WLS[i], and supplies a potential for turning off the writing switching elements included in the circuits MP other than the i-th row to the wiring WLS. Although an example in the case where the wiring WLS[i] is arranged has been shown, one aspect of the present invention is not limited thereto. In addition to the wiring WLS[i], for example, a wiring for transmitting an inverted signal of the signal input to the wiring WLS[i] may be separately arranged. That is, the wiring WLS[i] may be replaced with a plurality of

[0198] <<Circuit AFP>> As an example, the circuit AFP in FIG. 12 has circuits ACTF[1] to ACTF[n]. As an example, the circuits ACTF[1] to ACTF[n] can apply the circuit ACTF[j] described in the above embodiment. Thereby, the circuits ACTF[1] to ACTF[n] can generate, as an example, signals corresponding to the respective information (such as potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j]. As an example, the respective information (such as potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j] are compared, and a signal corresponding to j (k) the comparison result is generated. The signal is the signal z j(k) corresponds to. That is, circuit AC TF[1] to circuit ACTF[n] function as circuits for performing the operation of the activation function of the neural network described above, for example. as an example.

[0199] <<circuit MP>> Here, a configuration example of circuit MP[i,j] applicable to arithmetic circuit 130 will be described.

[0200] FIG. 13A shows a configuration example of circuit MP[i,j] applicable to arithmetic circuit 130. Circuit MP[i,j] has, for example, circuit MC and circuit MCr. Circuit MC and circuit MCr are circuits for calculating the product of the first data and the second data in circuit MP. Circuit MC can have the same configuration as circuit MCr or a different configuration from circuit MCr. Therefore, in order to distinguish circuit MCr from circuit MC, "r" is attached to the symbol. Also, "r" is attached to the symbols of the circuit elements described later included in circuit MCr.

[0201] Circuit MC has, for example, holding unit HC, and circuit MCr has holding unit HCr. Holding unit HC and holding unit HCr each have a function of holding information (for example, potential, resistance value, current value, etc.). ) i (k -1) j (k) The first data w set in circuit MP[i,j] is determined according to the information (for example, , potential, resistance value, current value, etc.) held in each of holding unit HC and holding unit HCr. Therefore, each of holding unit HC and holding unit HCr is the first data w i (k-1) j (k)Each piece of information according to (for example, potential, resistance value, current value, etc.) is electrically connected to wiring OL[j] and wiring OLB[j] that supply them.

[0202] In FIG. 13A, circuit MP[i,j] is electrically connected to wiring VE[j] and wiring VEr[j]. Wiring VE[j] and wiring VEr[j] function as wiring that supplies a constant voltage. Also, as an example, a current from wiring OL flows through wiring VE[j] via circuit MC. Further, as an example, a current from wiring OLB flows through wiring VEr[j] via circuit MCr.

[0203] Wiring WL[i] shown in FIG. 13A corresponds to wiring WLS[i] in FIG. 12. Wiring WL[i] is electrically connected to each of holding section HC and holding section HCr. When writing information (for example, potential, resistance value, current value, etc.) corresponding to first data w to holding section HC and holding section HCr included in circuit MP[i,j], by supplying a predetermined potential to wiring WL[i], i (k-1) j (k) a conductive state is established between wiring OL[j] and holding section HC, and a conductive state is established between wiring OLB[j] and holding section HCr. Then, by supplying a potential etc. corresponding to first data w to each of wiring IL[j] and wiring ILB[j], the potential etc. can be input to each of holding section HC and holding section HCr. Thereafter, by supplying a predetermined potential to wiring WL[i], a non-conductive state is established between wiring IL j] and holding section HC, and a non-conductive state is established between wiring ILB[j] and holding section HCr. i (k-1) j (k) etc. to each of holding section HC and holding section HCr. Thereafter, a predetermined potential is supplied to wiring WL[i] to make the connection between wiring IL j] and holding section HC non-conductive, and the connection between wiring ILB[j] and holding section HCr Set it to the non-conducting state. Then, each of the holding unit HC and the holding unit HCr holds respective currents corresponding to the first data w i (k-1) j (k) and so on.

[0204] For example, when the first data w i (k-1) j (k) takes any one of the three values of "-1", "0", and "1". Consider the case. When the first data w i (k-1) j (k) is "1", as an example a current corresponding to "1" flows from the wiring IL[j] through the circuit MC to the wiring VE[j]. A predetermined potential is held in the holding unit HC, and the potential V0 is held in the holding unit HCr so that no current flows from the wiring ILB[j] through the circuit MCr to the wiring VEr[j]. Also, when the first data w i (k-1) j (k) i (k-1) j (k) is "-1", as an example, the potential V0 is held in the holding unit HC so that no current flows from the wiring IL[j] through the circuit MC to the wiring VE[j], and a predetermined potential is held in the holding unit HCr so that a current corresponding to "-1" flows from the wiring ILB[j] through the circuit MCr to the wiring VEr j]. And when the first data w i (k-1) j (k) i is "0", as an example, the potential V0 is held in the holding unit HC so that no current flows from the wiring IL[j] through the circuit MC to the wiring VE[j], and the potential V0 is held in the holding unit HC, and no current flows from the wiring ILB[j] through the circuit MCr to the wiring VEr[j]. L[j] to the wiring VE[j], and the potential V0 is held in the holding unit HC, and no current flows from the wiring ILB[j] through the circuit MCr to the wiring VEr[j]. And the potential V0 is held in the holding unit HC, and no current flows from the wiring ILB[j] through the circuit MCr to the wiring VEr[j]. A potential V0 is held in the holding portion HCr so that the current does not flow. In the explanation of FIG. 14A, this can be the potential provided by the wiring VCN.

[0205] As another example, the first data w i (k-1) j (k) is the analog value, specifically, Consider the cases where the analog value is a negative value, a zero value, or a positive value. Data i (k-1) j (k) If is a "positive analog value", for example, wiring IL[ An analog current according to the “positive analog value” flows from the wire VE[j] through the circuit MC to the wiring VE[j]. A predetermined potential is held in the holding unit HC, and the line ILB[j] is connected to the circuit M The potential V0 is maintained in the holding part HCr so that no current flows through Cr to the wiring VEr[j]. Also, the first data w i (k-1) j (k) If is a "negative analog value", For example, we can prevent current from flowing from wiring IL[j] to wiring VE[j] via circuit MC. The potential V0 is held in the holding unit HC, and the potential V1 is supplied from the wiring ILB[j] through the circuit MCr. The holding part H A predetermined potential is held in Cr. i (k-1) j (k) is "0" For example, if a current flows from the wiring IL[j] to the wiring VE[j] via the circuit MC, In order to prevent current from flowing, the potential V0 is held in the holding section HC, and the potential V1 is connected from the wiring ILB[j] to the circuit MC The potential V0 is held in the holding unit HCr so that no current flows through the wiring VEr[j] via r. Note that the potential V0 can be the potential provided by the wiring VCN in the description of FIG. 14A described later, as in the previous example.

[0206] Also, as an example, the circuit MC has a function of outputting a current, voltage, etc. corresponding to the information (e.g., potential, resistance value, or current value, etc.) held in the holding unit HC to one of the wirings OL[j] or OLB[j]. The circuit MCr has a function of outputting a current, voltage, etc. corresponding to the information (e.g., potential, resistance value, or current value, etc.) held in the holding unit HCr to the other of the wirings OL[j] or OLB[j]. For example, when the first potential is held in the holding unit HC, the circuit MC is assumed to pass a current having the first current value from the wiring OL[j] or OLB[j] to the wiring VE. When the second potential is held in the holding unit HC, the circuit MC is assumed to pass a current having the second current value from the wiring OL[j] or OLB[j] to the wiring VE. Similarly, when the first potential is held in the holding unit HCr, the circuit MCr is assumed to pass a current having the first current value from the wiring OL j] or OLB[j] to the wiring VEr. When the second potential is held in the holding unit HCr, the circuit MCr is assumed to pass a current having the second current value from the wiring OL[j] or OLB [j] to the wiring VE. Note that the magnitudes of the first current value and the second current value are determined by the value of the first data w i (k-1) j (k) As an example, the first current value may be larger or smaller than the second current value. Further, as an example, one of the first current value or the second current value is a zero current, that is, a current value It may be 0. Or, the direction of current flow may be different between the current having the first current value and the current having the second current value. The direction of current flow may be different.

[0207] In particular, for example, when the first data w i (k-1) j (k) takes any one of the three values of "-1", "0", and "1", it is preferable to configure the circuit MC and the circuit MCr so that one of the first current value or the second current value becomes zero. Note that the first data w i (k-1) j (k) When taking an analog value, for example, "negative analog value", "0", or "positive analog value", it is possible for the first current value or the second current value to take an analog value as an example. It is possible.

[0208] By the way, the current flowing from the wiring OL[j] or the wiring OLB[j] (from the wiring IL[j]) to the wiring VE[j] via the circuit M C and the current flowing from the wiring OL[j] or the wiring OLB[j] (from the wiring ILB[j]) to the wiring VEr[j] via the circuit MCr are made equal. However, due to variations in the characteristics of the transistor caused by the manufacturing process of the transistor, etc., the potential held by the circuit MC and the potential held by the circuit MCr may not be equal. A semiconductor device according to one aspect of the present invention can make the amount of current flowing from the wiring OL[j] or the wiring OLB[j] (from the wiring IL[j]) to the wiring VE[j] via the circuit MC substantially equal to the amount of current flowing from the wiring OL[j] or the wiring OLB[j] (from the wiring ILB[j]) to the wiring VEr[j] via the circuit MCr even when there are variations in the characteristics of the transistor. It may be possible to make them substantially equal.

[0209] In addition, in this specification and the like, currents or voltages, etc., corresponding to the information held in the holding unit HC and the holding unit HCr (for example, potential, resistance value, or current value, etc.) may be positive currents or voltages, etc., or negative currents or voltages, etc., or zero currents or zero voltages, etc., or may have a mixture of positive, negative, and 0.

[0210] The wirings X1L[i] and X2L[i] shown in FIG. 13A correspond to the wiring X LS[i] in FIG. 12. Note that the second data z input to the circuit MP[i,j] i (k-1 ) is, as an example, determined by the respective potentials or currents, etc., of the wirings X1L[i] and X2L[i]. Therefore, to the circuits MC and MCr, for example, via the wirings X1 L[i] and X2L[i], each potential corresponding to the second data z is input. i (k-1)

[0211] The circuits MC and MCr, as an example, output currents or potentials, etc., corresponding to the product of the first data w and the second data z according to the potentials or currents, etc., input to the wirings X1L[i] and X2L[i]. As a specific example, the output destinations of the currents from the circuits MC and MCr are determined by the potentials of the wirings X1L[i] and X2L[i]. For example, the circuits M i (k-1) j (k) C and MCr output the current from the circuit MC to the wiring OL[j] or the wiring OLB i (k-1) is determined by the potential of the wirings X1L[i] and X2L[i]. For example, the circuits M C and MCr output the current from the circuit MC to the wiring OL[j] or the wiring OLB ​​​​​​flows to one side of [j], and the current output from circuit MCr flows through wiring OL[j] or wiring OLB[j to the other side. That is, the respective currents output from circuit MC and circuit MCr flow through different wirings instead of the same wiring. Note that in one example, there may be a case where no current flows through either wiring OL[j] or wiring OLB[j from circuit MC and circuit MCr.

[0212] For example, consider the case where the second data z i (k-1) takes one of the three values of "-1", "0", or "1". As an example, when the second data z i (k-1) is "1", circuit MP makes the connection between circuit MC and wiring OL[j] conductive, and the connection between circuit MCr and wiring OLB[j conductive. Also, as an example, when the second data z i (k-1) is "-1", circuit MP makes the connection between circuit MC and wiring OLB[j] conductive, and the connection between circuit MCr and wiring OL[j] conductive. Also, as an example, when the second data z i (k-1) is "0", in order to prevent the currents output from circuit MC and MCr from flowing through either wiring OL[j] or wiring OLB[j], circuit MP makes the connections between circuit MC and wiring OL[j], and between circuit MC and wiring OLB[j] non-conductive, and makes the connections between circuit M Cr and wiring OL[j], and between circuit MC and wiring OLB[j] non-conductive as well.

[0213] An example of summarizing the above operations is shown. When the first data w i (k-1) j (k) is "1", In this case, current may flow from wiring OL[j] or wiring OLB[j] to wiring VE[j] via circuit MC and current may not flow from wiring OL[j] or wiring OLB[j] to wiring VEr[j] via circuit MCr. When the first data w is "-1" i (k-1) j (k) in this case, current does not flow from wiring OL[j] or wiring OLB[j] to wiring VE[j] via circuit MC and current may flow from wiring OL[j] or wiring OLB[j] to wiring VEr[j] via circuit MCr. And when the second data z i (k-1) is "1" in this case, the connection between circuit MC and wiring OL[j], and the connection between circuit MCr and wiring OLB[j become conductive. When the second data z i (k-1) is "-1" in this case, the connection between circuit MC and wiring OLB[j], and the connection between circuit MCr and wiring OL[j] become conductive. From the above i (k-1) j (k) when the product of the first data w i (k-1) and the second data z is a positive value, current flows from wiring OL[j] to wiring VE[j] via circuit MCr or current flows from wiring OL[j] to wiring VEr[j] via circuit MCr. When the first data w i (k-1) j (k) and the second data z i (k-1) has a negative product in this case, current flows from wiring OL[j] to wiring VEr[j] via circuit MCr or current flows from wiring OLB[j] to wiring VE[j] via circuit MC​​ becomes. The first data w i (k-1) j (k) and the second data z i (k-1) has a zero value In this case, no current flows from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j] , and no current flows from the wiring OL[j] or the wiring OLB[j] to the wiring VEr[j].

[0214] Taking the above example as a specific example, the first data w i (k-1) j (k) is "1" and the second data z i (k-1) is "1", for example, a current I1[i, j] having a first current value flows from the circuit MC to the wiring OL [j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OLB[j] . At this time, as an example, the magnitude of the second current value is zero, that is, no current flows from the circuit MCr to the wiring OLB[j] can be assumed. The first data w i (k-1) j (k) is "-1" and the second data z i (k-1) i is "1", for example, a current I1[i, j] having a second current value flows from the circuit MC to the wiring OL , and a current I2[i, j] having a first current value flows from the circuit MCr to the wiring OLB[j] . At this time, as an example, the magnitude of the second current value is zero, that is, it can be assumed that no current flows from the circuit MC to the wiring OL[j]. The first data tag w i (k-1) j (k) is "0" and the second data z i(k-1) is “1” In this case, a current I1[i, j] having a second current value flows from the circuit MC to the wiring OLj, and the circuit a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OLBj. At this time , for example, the magnitude of the second current value is zero, that is, no current flows from the circuit MC to the wiring OLj and no current flows from the circuit MCr to the wiring OLBj can be the case.

[0215] Also, the first data w i (k-1) j (k) is “1” and the second data z i (k-1 ) is “-1”, a current I1 i, j] having a first current value flows from the circuit MC to the wiring OLBj, and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OLj. At this time, for example, the magnitude of the second current value is zero, that is, no current flows from the circuit MCr to the wiring OLj. The first data w i (k-1 ) j (k) is “-1” and the second data z i (k-1) is “-1”, a current I1[i, j] having a second current value flows from the circuit MC to the wiring OLBj, and a current I2[i, j] having a first current value flows from the circuit MCr to the wiring OLj. At this time, for example, the magnitude of the second current value is zero, that is, no current flows from the circuit MC to the wiring OLBj and it can be the case. The first data w i (k-1) j (k) is “0” and​ Second data z i (k-1) When it is “-1”, a current I1[i, j] with a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] with a second current value flows from the circuit MCr to the wiring OL[j]. At this time, as an example, the magnitude of the second current value is zero, that is, no current flows from the circuit MC to the wiring OLB[j], and it can be assumed that no current flows from the circuit MCr to the wiring OL[j]. a current I1[i, j] with a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] with a second current value flows from the circuit MCr to the wiring OL[j]. At this time, as an example, the magnitude of the second current value is zero, that is, no current flows from the circuit MC to the wiring OLB[j], and it can be assumed that no current flows from the circuit MCr to the wiring OL[j]. zero, that is, no current flows from the circuit MC to the wiring OLB[j], and it can be assumed that no current flows from the circuit MCr to the wiring OL[j]. from the circuit MCr to the wiring OL[j].

[0216] Also, when the second data z i (k-1) is “0”, as an example, between the circuit MC and the wiring OL[j], and between the circuit MC and the wiring OLB[j] are in a non-conductive state. Similarly between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j] are in a non-conductive state. Therefore, no matter what value the first data w i (k-1) j (k) is no current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j]. none.

[0217] Thus, as an example, when the value of the product of the first data w i (k-1) j (k) and the second data z i (k -1) takes a positive value, current flows from either the circuit MC or the circuit MCr to the wiring OL[j]. At this time, when the first data w i (k-1) j (k) is a positive value current flows from the circuit MC to the wiring OL[j], and when the first data w i(k-1) j ( k) When it is a negative value, current flows from the circuit MCr to the wiring OL[j]. On the other hand, the first data -ta w i (k-1) j (k) and the second data z i (k-1) When the value of the product of and takes a negative value, current flows from either the circuit MC or the circuit MCr to the wiring OLB[j]. At this time, when the first data w is a positive value, current flows from the circuit MC to the wiring O i (k-1) j (k) LB[j], and when the first data w is a negative value, current flows from the circuit i (k-1) j (k) is a negative value, current flows from the circuit MCr to the wiring OLB[j]. Therefore, the sum of the currents output from a plurality of circuits MC or MCr connected to the wiring OL[j] flows through the wiring OL[j]. That is, a current having a value obtained by taking the sum of positive values flows through the wiring OL[j]. On the other hand, the sum of the currents output from a plurality of circuits MC or MCr connected to the wiring OLB[j] flows through the wiring OLB[j]. That is, a current having a value obtained by taking the sum of negative values flows through the wiring OLB[j]. As a result of the above operation, the total current value flowing through the wiring OL[j], that is, the sum of positive values, and the total current value flowing through the wiring OLB[j], that is, the sum of negative values, can be used to perform the product-sum operation process. For example, when the total current value flowing through the wiring OL[j] is larger than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation is a positive value. For example, when the total current value flowing through the wiring OL[j] is larger than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation is a positive value. For example, when the total current value flowing through the wiring OL[j] is larger than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation is a positive value. For example, when the total current value flowing through the wiring OL[j] is larger than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation is a positive value. is cut off. When the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it can be determined that the result of the sum-of-products operation is a negative value. When the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the sum-of-products operation is a zero value. When considering that it also has the function as an activation function, if it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. That is, not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it may be determined that the result of the sum-of-products operation is a zero value. When the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it can be determined that the result of the sum-of-products operation is a negative value. When the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the sum-of-products operation is a zero value. When considering that it also has the function as an activation function, if it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. That is, not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it may be determined that the result of the sum-of-products operation is a zero value. When the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the sum-of-products operation is a zero value. When the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the sum-of-products operation is a zero value. When considering that it also has the function as an activation function, if it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. That is, not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it may be determined that the result of the sum-of-products operation is a zero value. When considering that it also has the function as an activation function, if it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. That is, not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it may be determined that the result of the sum-of-products operation is a zero value. When considering that it also has the function as an activation function, if it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. That is, not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it may be determined that the result of the sum-of-products operation is a zero value. When considering that it also has the function as an activation function, if it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. That is, not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it may be determined that the result of the sum-of-products operation is a zero value. When considering that it also has the function as an activation function, if it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. That is, not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it may be determined that the result of the sum-of-products operation is a zero value. When considering that it also has the function as an activation function, if it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. That is, not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it may be determined that the result of the sum-of-products operation is a zero value.

[0218] Note that the second data z i (k-1) is any two values among "-1", "0", and "1". For example, in the case of two values of "-1" and "1", or in the case of two values of "0" and "1", it can be operated in the same way. Similarly, the first data w is any two values among "-1", "0", and "1". For example, in the case of two values of "-1" and "1", or in the case of two values of "0" and "1", it can be operated in the same way. is any two values among "-1", "0", and "1". For example, in the case of two values of "-1" and "1", or in the case of two values of "0" and "1", it can be operated in the same way. i (k-1) j (k) If the first data w is any two values among "-1", "0", and "1". For example, in the case of two values of "-1" and "1", or in the case of two values of "0" and "1", it can be operated in the same way. is any two values among "-1", "0", and "1". For example, in the case of two values of "-1" and "1", or in the case of two values of "0" and "1", it can be operated in the same way.

[0219] Note that the first data w i (k-1) j (k) may take an analog value or a multi-bit (multi-value) digital value. As a specific example, instead of "-1", a "negative analog" The value", and instead of "1", it may take a "positive analog value". In this case, circuit M The magnitude of the current flowing from C or circuit MCr is also, as an example, the first data w i (k-1 ) j (k) becomes an analog value corresponding to the absolute value of the value of.

[0220] Next, an example of modifying the circuit MP[i, j] in FIG. 13A will be described. Note that for the modified example of circuit M P[i, j], the parts different from the circuit MP[i, j] in FIG. 13A will be mainly described, and the description of the parts common to the circuit MP[i, j] in FIG. 13A may be omitted. will be.

[0221] The circuit MP[i, j] shown in FIG. 13B has a configuration in which the wiring IL[i] and the wiring ILB[i] are combined as the wiring IL[j] in the circuit MP[i, j] of FIG. 13A.

[0222] The wirings W1L[i] and W2L[i] shown in FIG. 13B correspond to the wiring WLS[i in FIG. 12. The wiring W1L[i] is electrically connected to the holding part HC, and the wiring W2L[i] is electrically connected to the holding part HCr.

[0223] Also, the wiring IL[j] is electrically connected to the holding part HC and the holding part HCr. is.

[0224] In the circuit MP[i, j] of FIG. 13B, when different information (for example, voltage, resistance value, current, etc.) is held in each of the holding part HC and the holding part HCr, the information holding operations for the holding part HC and the holding part HCr are preferably not simultaneous but performed in order. For example, the first data w of the circuit MP[i, j] i (k-1)j (k) Consider the case where it can be expressed by holding the first information in the holding unit HC and the second information in the holding unit HCr. First, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i], so that the holding unit HC and the wiring IL[j] are in a conductive state, and the holding unit HCr and the wiring IL[j] are in a non-conductive state. Next a current, voltage, etc. corresponding to the first information is supplied to the wiring IL[j], so that the first information can be given to the holding unit HC. Then, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i], so that the holding unit HC and the wiring IL[j] are in a non-conductive state, and the holding unit HCr and the wiring IL[j] are in a conductive state. Then, a current, voltage, etc. corresponding to the second information is supplied to the wiring IL[j], so that the second information can be given to the holding unit HCr. Thereby, the circuit MP[i,j] can set w as the first data i (k-1) j (k)

[0225] Note that when each of the holding unit HC and the holding unit HCr holds substantially equal information (for example, voltage, resistance value, current, etc.) (when the first data w of the circuit MP[i,j] i (k-1) j (k) is set by each of the holding unit HC and the holding unit HCr holding substantially equal information), the holding unit HC and the wiring IL[j] are in a conductive state, and the holding unit HCr and the wiring IL[j] are in a conductive state, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i], and then, from the wiring IL[j], the holding unit HC, the holding unit H ​​​​​​​​For Cr, a current, voltage, etc. corresponding to the information may be supplied.

[0226] The circuit MP[i,j] in FIG. 13B holds a potential corresponding to the first data w in the holding unit HC and the holding unit HCr, and supplies a potential corresponding to the second data z to the wiring X1 i (k- 1) j (k) L[i] and the wiring X2L[i]. By doing so, similar to the circuit MP[i,j] in FIG. 13A, a current corresponding to the product of the first data w i (k-1) and the second data z can be output to the wiring OL[j] and the wiring OLB[j]. L[i] and the wiring X2L[i]. By doing so, similar to the circuit MP[i,j] in FIG. 13A, a current corresponding to the product of the first data w and the second data z can be output to the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k) and the second data z i (k-1) can be output to the wiring OL[j] and the wiring OLB[j].

[0227] The circuit MP[i,j] shown in FIG. 13C is a modified example of the circuit MP[i,j] in FIG. 13A . The circuit MP[i,j] in FIG. 13C has, similar to the circuit MP[i,j] in FIG. 13A, the circuit MC and the circuit MCr. However, the circuit MP[i,j] in FIG. 13C and the circuit M P[i,j] in FIG. 13A have different configurations of the electrically connected wirings.

[0228] Specifically, in the circuit MP[i,j] in FIG. 13C, in the circuit MP[i,j] in FIG. 13A, the wiring OL[j] and the circuit MCr are not electrically connected, and the wiring OLB[j] and the circuit MC are not electrically connected. Also, for this reason, the circuit MP[i,j] in FIG. 13C has a configuration in which the wiring X1L[i] and the wiring X2L[i] in the circuit MP[i,j] in FIG. 13A are replaced with the wiring XL[i]. Note that the wiring XL and the wiring X2L[i] in the circuit MP[i,j] in FIG. 13A are replaced with the wiring XL[i]. Note that the wiring XL and the wiring X2L[i] in the circuit MP[i,j] in FIG. 13A are replaced with the wiring XL[i]. Note that the wiring XL i] corresponds to wiring XLS[i] in FIG. 12 and is electrically connected to circuit MC and circuit MCr.

[0229] In the circuit MP[i,j] of FIG. 13C, wiring OL[j] and circuit MCr are electrically connected, but wiring OLB[j] and circuit MC are not electrically connected. Therefore, the second data (the value of the neuron signal) input to circuit MP differs from that in the circuit MP[i,j] of FIG. 13A. For example, when a high-level potential is applied to wiring XL, the second data (the value of the neuron signal) can be set to “+1”, and when a low-level potential is applied to wiring XL, the second data (the value of the neuron signal) can be set to “0”.

[0230] The circuit MP[i,j] shown in FIG. 13D, similar to FIG. 13A, outputs a current corresponding to the product of the first data w and the second data z i (k-1) j (k) i (k-1) to wiring OL[j] and wiring OLB[j]. Note that the circuit MP[i,j] in FIG. 13D can be applied to, for example, the arithmetic circuit 130 in FIG. 12.

[0231] The circuit MP[i,j] in FIG. 13D has a transistor MZ in addition to circuit MC and circuit MCr.

[0232] The first terminal of transistor MZ is electrically connected to the first terminal of circuit MC and the first terminal of circuit MCr. The second terminal of transistor MZ is electrically connected to wiring VL. The gate of transistor MZ is electrically connected to wiring XL[i].

[0233] ​​​​​​​The wiring VL, as an example, functions as a wiring that supplies a constant voltage, similar to the wiring VE[j] and the wiring VEr[j] shown in FIGS. 13A to 13C. The constant voltage is preferably determined by the configuration of the circuit MP i,j] or the arithmetic circuit 130 or the like. As the constant voltage for example, it can be VDD which is a high-level potential, VSS which is a low-level potential, a ground potential, or the like.

[0234] Also, the wiring WL[i] shown in FIG. 13D corresponds to the wiring WL S[i] in the arithmetic circuit 130 of FIG. 12. The wiring WL[i] is electrically connected to the holding unit HC and the holding unit HCr.

[0235] Also, the wiring OL[j] is electrically connected to the second terminal of the circuit MC. Also, the wiring OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0236] Also, the wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HCr.

[0237] In the circuit MP[i,j] of FIG. 13D, regarding the operation when each of the holding unit HC and the holding unit HCr holds a potential corresponding to the first data, refer to the description of the operation of holding the potential corresponding to the first data in the circuit MP[i,j] of FIG. 13A.

[0238] In the circuit MP[i,j] of FIG. 13D, when the constant voltage supplied by the wiring VL is supplied to the first terminal of the circuit MC, the circuit MC has a function of flowing a current corresponding to the potential held in the holding unit HC between the first terminal and the second terminal of the circuit MC. Also, the circuit MCr is the circuit M ​​​​​When a constant voltage supplied by wiring VL is applied to the first terminal of C, it has a function of flowing a current corresponding to the potential held in the holding part HCr between the first terminal and the second terminal of the circuit MCr. That is, by holding a potential corresponding to the first data w in each of the holding part HC and the holding part HCr of the circuit MP[i,j], the amount of current flowing between the first terminal and the second terminal of the circuit MC and the amount of current flowing between the first terminal and the second terminal of the circuit MCr can be determined. When the constant voltage supplied by the wiring VL is not applied to the first terminal of the circuit MC (circuit MCr), the circuit MC (circuit MCr) may not flow a current between the first terminal and the second terminal of the circuit MC (circuit MCr), for example. For example, when a potential corresponding to the first data w of "1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MC flows a predetermined current between the first terminal and the second terminal of the circuit MC. i ( k-1) j (k) Therefore, a current flows between the circuit MC and the wiring OL. At this time, it is assumed that no current flows between the first terminal and the second terminal of the circuit MCr. Therefore, no current flows between the circuit MCr and the wiring OLB. Also, for example, when a potential corresponding to the first data w of "-1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MCr That is, by holding a potential corresponding to the first data w in each of the holding part HC and the holding part HCr of the circuit MP[i,j], the amount of current flowing between the first terminal and the second terminal of the circuit MC and the amount of current flowing between the first terminal and the second terminal of the circuit MCr can be determined. When the constant voltage supplied by the wiring VL is not applied to the first terminal of the circuit MC (circuit MCr), the circuit MC (circuit MCr) may not flow a current between the first terminal and the second terminal of the circuit MC (circuit MCr), for example. For example, when a potential corresponding to the first data w of "1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MC flows a predetermined current between the first terminal and the second terminal of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. At this time, it is assumed that no current flows between the first terminal and the second terminal of the circuit MCr.

[0239] For example, when a potential corresponding to the first data w of "1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MC flows a predetermined current between the first terminal and the second terminal of the circuit MC. i (k-1) j (k) Therefore, a current flows between the circuit MC and the wiring OL. At this time, it is assumed that no current flows between the first terminal and the second terminal of the circuit MCr. Therefore, a current flows between the circuit MC and the wiring OL. At this time, it is assumed that no current flows between the first terminal and the second terminal of the circuit MCr. Therefore, a current flows between the circuit MC and the wiring OL. At this time, it is assumed that no current flows between the first terminal and the second terminal of the circuit MCr. Therefore, no current flows between the circuit MCr and the wiring OLB. Also, for example, when a potential corresponding to the first data w of "-1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MCr For example, when a potential corresponding to the first data w of "1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MC flows a predetermined current between the first terminal and the second terminal of the circuit MC. For example, when a potential corresponding to the first data w of "-1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MCr i (k-1) j (k) For example, when a potential corresponding to the first data w of "-1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MCr For example, when a potential corresponding to the first data w of "-1" is held in each of the holding part HC and the holding part HCr, when a constant voltage supplied by the wiring VL is applied to the circuit MC, the circuit MCr , a predetermined current is passed between the first terminal and the second terminal of the circuit MCr. Therefore, a current flows between the circuit MCr and the wiring OLB. At this time, it is assumed that no current flows between the first terminal and the second terminal of the circuit MC. Therefore, no current flows between the circuit MC and the wiring OL. Also, for example, when a potential corresponding to the first data w is held in each of the holding units HC and HCr i (k-1) j (k) , regardless of whether a constant voltage of the wiring VL is applied to the circuit MC and the circuit MCr, no current flows between the first terminal and the second terminal of the circuit MC, and no current flows between the first terminal and the second terminal of the circuit MCr. That is, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OLB.

[0240] In the circuit MP[i,j] of FIG. 13D, for specific examples of the potential corresponding to the first data w held in the holding units HC and HCr, refer to the description of the circuit MP[i,j] in FIG. 10A. Also, in the circuit MP[i,j] of FIG. 13D, the holding units HC and HCr, similar to the circuit MP[i,j] of FIG. 10A, i (k-1) j (k) have a function of holding information such as current and resistance value instead of potential, and the circuits MC and MCr may have a function of passing a current according to the information.

[0241] The wiring XL[i] shown in FIG. 13D corresponds to the wiring XLS[i in the arithmetic circuit 130 of FIG. 12. The second data z i (k-1) input to the circuit MP[i,j] is one For example, it is determined by the potential, current, etc. of the wiring XL[i]. Therefore, the trans To the gate of the transistor MZ, for example, via the wiring XL[i], the second data z i (k-1) is A potential corresponding thereto is input.

[0242] For example, the second data z i (k-1) is considered to take either of the two values of "0" and "1". For example, the second data z i (k-1) When it is "1", it is assumed that a high-level potential is applied to the wiring XL[i]. At this time, since the transistor MZ is turned on, the circuit MP makes the connection between the wiring VL and the first terminal of the circuit MC conductive, and makes the connection between the wiring VL and the first terminal of the circuit MCr conductive. That is, when the second data z is "1", a constant voltage from the wiring VL is applied to the circuit MC and the circuit MCr. Also, for example, i (k-1) when the second data z is "0", it is assumed that a low-level potential is applied to the wiring XL[i]. At this time, the circuit MP makes the connection between the circuit MC and the wiring OLB[j] non-conductive, and makes the connection between the circuit MCr and the wiring OL[j] non-conductive. That is, when the second data z is "0", i (k-1) a constant voltage from the wiring VL is not applied to the circuit MC and the circuit MCr. At this time, the circuit MP makes the connection between the circuit MC and the wiring OLB[j] non-conductive, and makes the connection between the circuit MCr and the wiring OL[j] non-conductive. That is, when the second data z is "0", a constant voltage from the wiring VL is not applied to the circuit MC and the circuit MCr. i (k-1) when the second data z is "0", a constant voltage from the wiring VL is not applied to the circuit MC and the circuit MCr.

[0243] Here, for example, when the first data w i (k-1) j (k) is "1" and the second data z i (k-1)When it is "1", current flows between the circuit MC and the wiring OL, and no current flows between the circuit MC r and the wiring OLB. Also, for example, when the first data w i ( k-1) j (k) is "-1" and the second data z i (k-1) is "1", no current flows between the circuit MC and the wiring OL, and current flows between the circuit MCr and the wiring OLB . Also, for example, when the first data w i (k-1) j (k) is "0" and , the second data z i (k-1) is "1", no current flows between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB. Also, for example, when the second data z i (k-1) is "0", regardless of whether the first data w i (k-1) j (k) is "-1", "0 ", or "1", no current flows between the circuit MC and the wiring OL, and between the circuit MCr and the wiring O LB.

[0244] That is, the circuit MP[i,j] in FIG. 13D, similar to the circuit MP[i,j] in FIG. 13C, As an example, when the first data w i (k-1) j (k) takes any one of the three values of "-1", "0", and "1", and the second data z takes either of the two values of "0" and "1", i (k-1) the operation can be performed. Also, similar to the circuit MP[i,j] in FIG. 13C, the circuit in FIG. 13D can perform the operation. The path MP[i,j] is the first data w i (k-1) j (k) is one of "-1", "0", "1" For any two values, for example, in the case of two values of "-1" and "1", or in the case of two values of "0" and "1" ", it can also be operated. Note that the first data w i (k-1) j (k) may take an analog value or a multi-bit (multi-value) digital value. As a specific example Instead of "-1", a "negative analog value" and instead of "1", a "positive analog log value" may be taken. In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr is also, as an example, the first data w i (k-1) j (k) an analog value corresponding to the absolute value of the value will be.

[0245] <<Circuit ILD>> The circuit ILD, as an example, has a function of inputting information (such as potential, resistance value, current value, etc.) corresponding to the first data w1 which is a weighting factor, to each of the circuits MP[1,1] to MP[m,n] via the wirings IL[1] to IL[n] and the wirings ILB[1] to ILB[n]. (k-1) 1 (k) to w m (k-1) n (k) Specifically, the circuit ILD inputs information (such as potential, resistance value, or current value corresponding to the first data w i (k-1) j (k) which is a weighting factor) to the circuit MP[i,j]. For example), supply it via wiring IL[j] and wiring ILB[j].

[0246] FIG. 14A shows an example of the circuit configuration of circuit ILD applicable to arithmetic circuit 130. Note that in FIG. 14A, in order to explain the electrical connection between circuit ILD and array section ALP, wiring OL[j] and wiring OLB[j] are also shown. Circuit ILD includes current source circuit ISC and , switch SWIA, switch SWIAB, switch SWLA, and switch SWLAB B. Wiring OL[j] is electrically connected to the first terminal of switch SWIA and the first terminal of switch SWLA . Wiring OLB[j] is electrically connected to the first terminal of switch SWIAB and the first terminal of switch SWLAB . Current source circuit ISC is electrically connected to the second terminal of switch SWIA and the second terminal of switch SWIAB . Wiring VCN is electrically connected to the second terminal of switch SWLA and the second terminal of switch SWLAB .

[0247] Current source circuit ISC has, for example, one or a plurality of constant current sources. In FIG. 14A, as an example, as a plurality of constant current sources, it has constant current source circuit ISC1, constant current source circuit ISC2 , and constant current source circuit ISC3. Also, current source circuit ISC has, as an example, a plurality of switches for selecting a plurality of constant current sources. In FIG. 14A, as a plurality of switches , it has switch SWC1, switch SWC2, and switch SWC3. Note that when current source circuit ISC has only one constant current source, current source circuit ISC may not have a switch . Or, constant current source circuit ISC1, constant current source circuit ISC2, and constant ​When the current source circuits ISC3 each have a function of controlling whether or not to output a current the switches SWC1, SWC2, and SWC3 need not be provided. It is also acceptable.

[0248] By the way, in any one of the circuits MP[1,j] to MP[m,j], for holding the first data ( weight coefficient), the currents flowing through the wiring OL[j] and the wiring OLB[j] respectively are preferably generated by the same current source circuit ISC as shown in FIG. 14A. When the currents flowing through the wiring OL[j] and the wiring OLB[j] are generated by different current source circuits variations in the characteristics of the transistor may occur due to, for example, the manufacturing process of the transistor, resulting in differences in performance between different current source circuits. On the other hand, when the same current source circuit is used, it is possible to flow currents of the same magnitude through the wiring OL[j] and the wiring OLB[j], and the calculation accuracy can be improved.

[0249] Note that, as the switches SWIA, SWIAB, SWLA , SWLAB, SWC1, SWC2, and SWC3 described with reference to FIG. 14A, respectively for example, switches that can be applied in the same manner as the aforementioned switches SWR1, SWR1B, SW R2, and SWR2B can be used.

[0250] Specific configuration examples of the constant current source circuits ISC1 to ISC3 are shown in FIGS. 14B and 14C. The constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in FIG. 14B has a transistor PTr that is a p-channel type transistor, and the transistor The first terminal of the PTr transistor is electrically connected to the wiring VSO, and the second terminal of the transistor PTr is electrically connected to the second terminal of the switch SWC1 (switch SWC2, switch SWC3), and the gate of the transistor PTr is electrically connected to the wiring VB. Also , the constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3 shown in FIG. 14C) has a transistor NTr of an n-channel type transistor, and the first terminal of the transistor NTr is electrically connected to the wiring VSO, and the second terminal of the transistor NTr is the switch SWC1 (switch SWC2, switch SWC3) is electrically connected to the second terminal, and the gate of the transistor NTr is electrically connected to the wiring VB. In FIGS. 14B and 14C , in each of the constant current source circuits ISC1 (constant current source circuit ISC2, constant current source circuit ISC3), the wiring VB functions as a wiring for inputting a bias voltage to the gate of each transistor. Note that a pulse signal may be supplied to the wiring VB. Thereby, it is possible to control whether or not to output a current from each constant current source circuit. In that case, the switches SWC1, SWC2, and SWC3 may not be provided. Also an analog voltage may be supplied to the wiring VB. Thereby, an analog current can be supplied from the constant current source circuit. The wiring VSO functions as a wiring for supplying a constant voltage to each of the constant current source circuits ISC1 to ISC3. For example, when a current flows from the circuit ILD (wiring VSO) to the wiring OL or the wiring OLB, the constant voltage is preferably a potential higher than the ground potential ( for example, VDD, etc.), and further, the constant current source circuit ISC1 shown in FIG. 14B In addition, an analog voltage may be supplied to the wiring VB. Thereby, an analog current can be supplied from the constant current source circuit. The wiring VSO functions as a wiring for supplying a constant voltage to each of the constant current source circuits ISC1 to ISC3. For example, when a current flows from the circuit ILD (wiring VSO) to the wiring OL or the wiring OLB, the constant voltage is preferably a potential higher than the ground potential (

[0251] The wiring VSO functions as a wiring for supplying a constant voltage to each of the constant current source circuits ISC1 to ISC3. For example, when a current flows from the circuit ILD (wiring VSO) to the wiring OL or the wiring OLB, the constant voltage is preferably a potential higher than the ground potential ( for example, VDD, etc.), and further, the constant current source circuit ISC1 shown in FIG. 14B When current flows from the circuit ILD (wiring VSO) to the wiring OL or the wiring OLB, the constant voltage is preferably a potential higher than the ground potential ( for example, VDD, etc.), and further, the constant current source circuit ISC1 shown in FIG. 14B It is preferable to use (constant current source circuit ISC2, constant current source circuit ISC3). Also, for example , when current flows from wiring OL or wiring OLB to circuit ILD (wiring VSO), the said voltage is preferably a potential higher than the ground potential and lower than the high-level potential, the ground potential, a negative potential, etc., and furthermore, it is preferable to use the constant current source circuit ISC1 (constant current source circuit I SC2, constant current source circuit ISC3) shown in FIG. 14C. In this specification etc., when the current flowing from circuit ILD to wiring OL or wiring OLB is described as a positive current. SC2, constant current source circuit ISC3) shown in FIG. 14C. In this specification etc., when the current flowing from circuit ILD to wiring OL or wiring OLB is described as a positive current. Therefore, there are cases where the current flowing from wiring OL or wiring OLB to circuit ILD is described as a negative current. Therefore, there are cases where the current flowing from wiring OL or wiring OLB to circuit ILD is described as a negative current.

[0252] By the way, when the current passed by the constant current source circuit ISC1 is I ut as an example, the current passed by the constant current source circuit ISC2 is preferably 2I ut and the current passed by the constant current source circuit ISC3 is preferably 4I ut That is, when the current source circuit ISC has P (P is an integer of 1 or more .) constant current sources, the current passed by the p-th (p is an integer of 1 or more and P or less.) constant current source is preferably 2 (p-1) ×I ut . That is, by switching each of switches SWC1 to SWC3 etc. between the on state and the off state, the magnitude of the current flowing from the current source circuit ISC can be changed.

[0253] For example, assume that the number of constant current sources of the current source circuit ISC is three (P = 3). When it is desired to pass a current of I through wiring OL[j] ut , turn on switch SWIA and turn on switch SWIAB After turning it off, turn on switch SWC1 and turn off switch SWC2 and switch SWC3. Also, if you want to pass a current of 5I through wiring OL[j], ut you can do the following: When you want to pass a current of 5I through wiring OL[j], turn on switch SWC1 and switch SWC3 and turn off switch SWC2. That is, the amount of current output from current source circuit ISC can be one of eight values ("0", "I", "2I", ut "3I", ut "4I", ut "5I", ut "6I", ut "7I" u t ). If you want to output a current with a value larger than the eight values, you can increase the number of constant current sources to four or more. Similarly, by turning off switch SWIA and turning on switch SWIAB, you can pass one of the eight values of current through a wiring OLB[j]. When no current is output from current source circuit ISC, you may not turn off switches SWC1 to SWC3 of current source circuit ISC and turn off switch SWIA and switch SWIAB. ut By arranging a plurality of constant current sources in this way, a circuit that can generate a current with a multi-valued current amount can be easily realized. Note that you may arrange only one current source circuit and operate it so as to change the current value output analogously. Wiring VCN functions as a wiring that supplies a constant voltage to wiring OL[j] and / or wiring OLB[j]. For example, when a current (positive current) flows from circuit ILD to wiring OL or wiring OLB, the constant voltage provided by wiring VCN is a low-level potential (e.g., VSS). By turning off switch SWIA and turning on switch SWIAB, one of the eight values of current can be passed through wiring OLB[j]. When no current is output from current source circuit ISC, you may not turn off switches SWC1 to SWC3 of current source circuit ISC and turn off switch SWIA and switch SWIAB. Wiring VCN functions as a wiring that supplies a constant voltage to wiring OL[j] and / or wiring OLB[j]. For example, when a current (positive current) flows from circuit ILD to wiring OL or wiring OLB, the constant voltage provided by wiring VCN is a low-level potential (e.g., VSS). When no current is output from current source circuit ISC, you may not turn off switches SWC1 to SWC3 of current source circuit ISC and turn off switch SWIA and switch SWIAB. By arranging a plurality of constant current sources in this way, a circuit that can generate a current with a multi-valued current amount can be easily realized. Note that you may arrange only one current source circuit and operate it so as to change the current value output analogously. By arranging a plurality of constant current sources in this way, a circuit that can generate a current with a multi-valued current amount can be easily realized. Note that you may arrange only one current source circuit and operate it so as to change the current value output analogously. By arranging a plurality of constant current sources in this way, a circuit that can generate a current with a multi-valued current amount can be easily realized. Note that you may arrange only one current source circuit and operate it so as to change the current value output analogously. By arranging a plurality of constant current sources in this way, a circuit that can generate a current with a multi-valued current amount can be easily realized. Note that you may arrange only one current source circuit and operate it so as to change the current value output analogously.

[0254] Wiring VCN functions as a wiring that supplies a constant voltage to wiring OL[j] and / or wiring OLB[j]. For example, when a current (positive current) flows from circuit ILD to wiring OL or wiring OLB, the constant voltage provided by wiring VCN is a low-level potential (e.g., VSS). Wiring VCN functions as a wiring that supplies a constant voltage to wiring OL[j] and / or wiring OLB[j]. For example, when a current (positive current) flows from circuit ILD to wiring OL or wiring OLB, the constant voltage provided by wiring VCN is a low-level potential (e.g., VSS). When a current (positive current) flows from circuit ILD to wiring OL or wiring OLB, the constant voltage provided by wiring VCN is a low-level potential (e.g., VSS). etc.) is preferable. Also, for example, when a current (negative current) flows from the wiring OL or the wiring OLB to the circuit ILD the constant potential provided by the wiring VCN is preferably a high-level potential and is preferable. As shown in FIGS. 20A to 20C, FIG. 21A, FIG. 21B, etc. described later the capacitor C1 is electrically connected to the source terminal of the transistor M1 or the like, and when the source terminal is connected to a power supply line or the like, when a positive current flows from the circuit ILD to the wiring OL or the wiring OL B, the constant voltage provided by the wiring VCN is preferably a low-level potential (for example VSS, etc.). That is, when supplying a constant voltage from the wiring VCN, it is desirable to make the potential difference across the capacitor C1 close to zero. In other words, it is desirable to supply a potential such that no current is output from the circuit MC, for example, a potential substantially equal to the potential provided by the wiring VE, to the wiring VCN. Here, the first data (weight coefficient) input to the circuit MP will be described. When it is desired to input positive first data to the circuit MP, a current corresponding to the first data may be input to the wiring OL[j], and the constant potential provided by the wiring VCN may be input to the wiring OLB[j]. As an example

[0255] the conduction state may be established between the current source circuit ISC and the wiring OL[j], the non-conduction state may be established between the current source circuit ISC and the wiring OLB[j], the non-conduction state may be established between the wiring VCN and the wiring OL[j], and the conduction state may be established between the wiring VCN and the wiring OLB[j]. That is,

[0256] the switch SWIA and the switch SWLAB may be turned on, and the switches SWIAB and SWLA may be turned off respectively. Thereby, the current source circuit ISC and the switch SWIA and the switch SWLAB may be turned on, and the switches SWIAB and SWLA may be turned off respectively. Thereby, the current source circuit ISC and Since it becomes conductive between the wiring OL[j], current can flow from the current source circuit ISC to the circuit MP through the wiring OL[j]. By the way, when the number of constant current sources of the current source circuit ISC is P, the current becomes one of the values of 2 −1 (excluding zero current). Since the positive weight coefficient input to the circuit MP is determined according to the current, the weight coefficient can be one of the values of 2 −1. Also, since it becomes conductive between the wiring VCN and the wiring OLB[j], a constant voltage from the wiring VCN is input to the wiring OLB[j]. P P

[0257] Also, when it is desired to input negative first data to the circuit MP, a current corresponding to the first data may be input to the wiring OLB[j], and a constant potential provided by the wiring VCN may be input to the wiring OL[j]. As an example, the state between the current source circuit ISC and the wiring OL[j] may be made non-conductive, the state between the current source circuit ISC and the wiring OLB[j] may be made conductive, the state between the wiring VCN and the wiring OL[j] may be made conductive, and the state between the wiring VCN and the wiring OLB[j] may be made non-conductive. That is, the switches SWIAB and SWLA may be turned on, and the switches SWIA and SWLAB may each be turned off. Thereby, since it becomes conductive between the current source circuit ISC and the wiring OLB [j], current can flow from the current source circuit ISC to the circuit MP through the wiring OLB[j]. By the way, when the number of constant current sources of the current source circuit ISC is P, the current becomes one of the values of 2 −1 (excluding zero current). P Since the negative weight coefficient input to the circuit MP is determined according to the current, the weight coefficient is 2 P ​​​​​​​​​​​​​It can be set to any one of the -1 values. Also, since the wiring VCN and the wiring OL[j] are in a conductive state, a constant voltage from the wiring VCN is input to the wiring OL[j]. Moreover, when it is desired to input 0 as the first data to the circuit MP, the constant potential given by the wiring VCN to each of the wiring OL[j] and the wiring OLB[j

[0258] may be input. As an example, the current source circuit ISC and the wiring OL[j] are made non-conductive, the current source circuit ISC and the wiring OLB[j are made non-conductive, the wiring VCN and the wiring OL[j] are made conductive, and the wiring VC N and the wiring OLB[j] are made conductive. That is, the switches SWLA and the switch SWLAB are turned on, and each of the switches SWIA and the switch SWIAB is turned off. As a result, the wiring VCN and the wiring OL[j] become conductive , and the wiring VCN and the wiring OLB[j] become conductive, so that a constant voltage from the wiring VCN is input to the wiring OL[j] and the wiring OLB[j]. That is, by setting the number of constant current sources of the current source circuit ISC to P, the number of weight coefficients (the total of positive weight coefficients, negative weight coefficients, and 0 weight coefficients) that can be input to the circuit MP is 2

[0259] P+ 1

[0260] Note that in the above, the circuit ILD has been described with a configuration having the current source circuit ISC, but one aspect of the present invention is not limited to this. For example, instead of having the current source circuit ISC, a voltage source circuit may be arranged. Also, for example, the current source circuit ISC may be separate circuits for the wiring OL[j and for the wiring OLB[j], respectively, They may be arranged at least one by one. Also, for example, as shown in FIG. 14A, wiring OL[j] and a set of wirings including wiring OLB[j] may have at least one current source circuit ISC. Note that circuit ILD may be arranged as a circuit separate from circuit AFP, but one aspect of the present invention is not limited to this. For example, circuit ILD may be an integrated circuit with circuit AFP.

[0261] <Operation example of arithmetic circuit> Next, an operation example of the arithmetic circuit 130 in FIG. 12 will be described. In the description of this operation example, as an example, the arithmetic circuit 130A shown in FIG. 15 is used.

[0262] The arithmetic circuit 130A shown in FIG. 15 is a diagram in which circuit ACT F[j] shown in FIG. 8 is applied to the arithmetic circuit 130 in FIG. 12, and is shown by focusing on the circuit located in the j-th column of the arithmetic circuit 130 in FIG. 12. Therefore, the arithmetic circuit 130A in FIG. 15 is the neuron N in the neural network 100 shown in FIG. 1A The signals z1 from neuron N1 j (k) to neuron N (k-1) up to neuron N m (k-1) (k-1) up to z m (k -1) (k-1) j (Sometimes referred to as first data or second data. Here, it is referred to as second data. ) and the weighted coefficients w1 (k-1) j (k) up to w m (k-1) j (k) (Sometimes referred to as first data or second data. Here, it is referred to as first data.) and the sum-of-products operation It corresponds to a circuit that performs an activation function operation using the result of the product-sum operation and the like.

[0263] Also, the circuit MP included in the array unit ALP of the arithmetic circuit 130A in FIG. 15 applies the circuit MP in FIG. 13 A, and shows the wirings WL[1] to WL[m] as the wirings WLS[1] to WLS[m], and shows the wirings X1L[1] to X1L[m] and the wirings X2L[1] to X2L[m] as the wirings XLS[1] to XLS[m]. 1] to the wiring X 1L[1] to the wiring X1L[m], and the wirings X2L[1] to X2L[m]. Also, as the circuit IVTR and the circuit IVTRr included in the circuit ACTF[j] of the arithmetic circuit 130A in FIG. 15, the circuit IVTR (circuit IVTRr) shown in FIG. 6A is applied.

[0264] First, in the arithmetic circuit 130A, the first data w1 to w (k-1) j (k) to w m (k-1) j (k) are set. The method of setting the first data w i (k-1) j (k) is to input a predetermined potential to the wirings WLS[1] to WLS[m] in order by the circuit WLD, select the circuits MP[1,j] to MP m,j] in order, and supply a potential, current, etc. corresponding to the first data to the holding units HC and HCr of the circuits MC and MCr included in the selected circuit MP from the circuit ILD via the wirings OL[j] and OLB j]. Then, after the supply of the potential, current, etc., each of the circuits MP[1,j] to MP[m,j] is selected by the circuit WLD. ​By deselecting, each of circuits MP[1,j] to MP[m,j] can have the holding unit HC of circuit MC and the holding unit HCr of circuit MCr hold the first data w1 (k-1) j (k) to w m (k-1) j (k) potentials, currents, etc. corresponding thereto. As an example, for any one of the first data w1 (k-1) j (k) to w m (k-1) j (k) if it takes a positive value, the holding unit HC is input with a value corresponding to the positive value, and the holding unit HCr is input with a value corresponding to zero. On the other hand, for any one of the first data w1 (k-1) j ( k) to w m (k-1) j (k) if it takes a negative value, the holding unit H C is input with a value corresponding to zero, and the holding unit HCr is input with a value corresponding to the absolute value of the negative value. Also, for any one of the first data w1 (k-1) j (k) m (k-1) j (k) (k-1) m if it takes a value of 0, the holding unit HC is input with a value corresponding to zero, and the holding unit HCr is input with a value corresponding to the absolute value of the zero value.

[0265] Next, by circuit XLD, the second data z1 is applied to each of wirings X1L[1] to X1L[m] and wirings X2L[1 to X2L[m], respectively. (k-1) to z m(k-1) to supply. As a specific example, the second data z1 (k-1) is supplied.

[0266] The second data z1 input to each of the circuits MP[1,j] to MP[m,j] ( k-1) to z m (k-1) correspondingly determines the conduction states of the circuits MC and MCr included in the circuits MP[1,j] to MP[m,j], and the wirings OL[j] and OLB[j]. Specifically, for example, the circuit MP[i,j] is, according to the second data z i (k-1) in one of the following modes: "the connection between the circuit MC and the wiring OL[j] becomes conductive, and the connection between the circuit MCr and the wiring OLB[j] becomes conductive", "the connection between the circuit MC and the wiring OLB[j] becomes conductive, and the connection between the circuit MCr and the wiring OL[j] becomes conductive", and "the circuits MC and MCr are each in a non-conductive state with the wirings OL[j] and OLB[j]"." The connection between the circuit MC and the wiring OL[j] becomes conductive, and the connection between the circuit MCr and the wiring OLB[j] becomes conductive", "the connection between the circuit MC and the wiring OLB[j] becomes conductive and the connection between the circuit MCr and the wiring OL[j] becomes conductive", and "the circuits MC and M Cr are each in a non-conductive state with the wirings OL[j] and OLB[j]". For example, when the second data z1 (k-1) takes a positive value, a value that can make the connection between the circuit MC and the wiring OL[j] conductive and the connection between the circuit MCr and the wiring OLB[j] conductive can be input to the wiring X1L[1]. And a value that can make the connection between the circuit MC and the wiring OLB[j] non-conductive and the connection between the circuit MCr and the wiring OL[j] non-conductive can be input to the wiring X2L[1]. Then when the second data z1 (k-1) takes a negative value, for the wiring X1L[1], (k-1) the connection between the circuit MC and the wiring OLB[j] becomes conductive, and the connection between the circuit MCr and the wiring OL j becomes non-conductive, and a value that can make the connection between the circuit MC and the wiring OLB[j] non-conductive and the connection between the circuit MCr and the wiring OL Enter a value that can make it conductive to [j]. Then, for wiring X2L[1], a value that can make it non-conductive between circuit MC and wiring OLj, and non-conductive between circuit MCr and wiring OL Enter a value that can make it non-conductive between B[j]. Then, for the second data z1 (k-1) When taking a value of zero for, for wiring X1L[1], it is non-conductive between circuit MC and wiring OLB[j], and a value that can make it non-conductive between circuit MCr and wiring OLj is entered. Then, for wiring X2L[1], it is non-conductive between circuit MC and wiring OLj, and a value that can make it non-conductive between circuit MCr and wiring OLB[j] is entered.

[0267] The second data z input to circuit MP[i,j] i (k-1) According to, in circuit MP[i, j], the conduction states between circuit MC, circuit MCr and wiring OLj, wiring OLB[j] included in circuit MP[i, j] are determined, and current input and output are performed between circuit MC, circuit MCr and wiring OLj, wiring OLB[j] . Further, the amount of the current is determined according to the first data w set in circuit MP[i,j] i (k-1) j (k) and / or the second data z i (k-1) and is determined according to .

[0268] For example, in circuit MP[i,j], let the current flowing from wiring OLj to circuit MC or circuit MCr be I[i,j], and the current flowing from wiring OLB[j] to circuit MC or circuit MCr be I [i,j]. Then, the current flowing from circuit ACTF[j] to wiring OLj is B [i,j]. Then, the current flowing from circuit ACTF[j] to wiring OLj Let the current flowing be I out [j], and let the current flowing from wiring OLB[j] to circuit ACTF[j] be I Bout [j]. Then, I out [j] and I Bout [j] are represented by the following equations and can be obtained as follows.

[0269]

Equation

[0270] In circuit MP[i,j], as an example, when the first data w i (k-1) j (k) is “+ 1”, a current I(+ 1) flows between circuit MC and one of wiring OL[j] or wiring OLB[j], and a current I(-1 ) flows between circuit MCr and the other of wiring OL[j] or wiring OLB[j]. When the first data w i (k-1) j (k) is “-1”, a current I(-1) flows between circuit M C and one of wiring OL[j] or wiring OLB[j], and a current I(+1) flows between circuit MCr and the other of wiring OL[j] or wiring OLB[j]. When the first data w is “0”, a current I(-1) flows between circuit MC and one of wiring OL[j] or wiring i (k-1) j (k) OLB[j], and a current I(-1) flows between circuit MCr and the other of wiring OL[j] or wiring OLB[j]. Assume this.

[0271] Furthermore, when the second data z i (k-1) is “+1”, “ A conduction state is established between the circuit MC and the wiring OL[j], and between the circuit MCr and the wiring OLB[j], a non-conduction state is established between the circuit MC and the wiring OLB[j], and between the circuit MCr and the wiring OL[j]. When the second data z takes the configuration of "-1", "a conduction state is established between the circuit MC and the wiring OLB[j], and between the circuit MCr and the wiring OL[j], a non-conduction state is established between the circuit MC and the wiring OL[j], and between the circuit MCr and the wiring OLB[j]". When the second data z i (k-1) is "-1", "a conduction state is established between the circuit MC and the wiring OLB[j], and between the circuit MCr and the wiring OL[j], a non-conduction state is established between the circuit MC and the wiring OL[j], and between the circuit MCr and the wiring OLB[j]". When the second data z is "0", "a non-conduction state is established between the circuit MC and the wiring OL[j], and between the circuit MC and the OLB[j], and a non-conduction state is established between the circuit MCr and the wiring OL[j], and between the circuit MCr and the OLB[j]". is "0", "a non-conduction state is established between the circuit MC and the wiring OL[j], and between the circuit MC and the OLB[j], and a non-conduction state is established between the circuit MCr and the wiring OL[j], and between the circuit MCr and the OLB[j]". Let it be assumed that the second data z i (k-1) is "0", "a non-conduction state is established between the circuit MC and the wiring OL[j], and between the circuit MC and the OLB[j], and a non-conduction state is established between the circuit MCr and the wiring OL[j], and between the circuit MCr and the OLB[j]". At this time, in the circuit MP[i,j], the current I[i,j] flowing from the wiring OL[j] to the circuit MC or the circuit MCr, and the current I [i,j] flowing from the wiring OLB[j] to the circuit MC or the circuit MCr are as shown in the following table. In some cases, the circuit MP[i,j] may be configured such that the current amount of I(- 1) becomes 0. The current I

[0272] i,j] may be the current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I i,j] may be the current flowing from the circuit MC or the circuit MCr to the wiring OLB[j]. B [i,j] may be the current flowing from the circuit MC or the circuit MCr to the wiring OLB[j]. 1) becomes 0. The current I i,j] may be the current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] may be the current flowing from the circuit MC or the circuit MCr to the wiring OLB[j]. is the current flowing from the circuit MC or the circuit MCr to the wiring OLB[j].

[0273]

Table 1

[0274] And the circuit ACTF[j] generates voltages corresponding to, for example, the currents flowing through wirings OL[j] and OLB[j]. I out [j] and I Bout [j], respectively. And, in response to the difference between the voltage corresponding to I o ut [j] and the voltage corresponding to I Bout [j], neuron N j (k) outputs a signal z to be transmitted to the neurons of the (k + 1)-th layer. j (k)

[0275] Note that for the operation of circuit ACTF[j], refer to the description of the operation example of arithmetic circuit 110A in FIG. 8 of Embodiment 1.

[0276] <Configuration Example 2 of Arithmetic Circuit> Note that the arithmetic circuit 130A shown in FIG. 15 outputs a positive-valued signal z when I Bout [j] is greater than I out [j] (when u is positive), and outputs an output signal z of 0 as a digital signal when I j (k) is greater than I j (k) [j] (when u is negative). However, one aspect of the present invention is not limited thereto. For example, the arithmetic circuit 130A outputs a signal z when I out [j] is greater than I Bout [j] (when u j (k) is negative). In this case, the circuit AC outputs an output signal z of 0 as a digital signal. j (k) However, one aspect of the present invention is not limited to this. For example, when I is greater than I out [j] (when u Bout is negative), the circuit AC j (k) ​​​The path AC may be changed to a configuration that outputs an output signal z that is a negative value. j (k)

[0277] An example of such an arithmetic circuit is shown in FIG. 16. The arithmetic circuit 140 shown in FIG. 16 has a configuration in which the circuit ACTF[j] included in the circuit AFP of the arithmetic circuit 130A in FIG. 15 is changed. Also, the circuit configuration of the arithmetic circuit 140 is also an example of the arithmetic circuit 120 shown in FIG. 4A. The circuit ACTF[j] includes a switch SWR1M, a switch SWR1MB, a switch SWR1P, a switch SWR1PB, a switch SWR2M, a switch SWR2MB, a switch SWR2P, a switch SWR2PB, a capacitor CREM, a capacitor CREP, a circuit ACM, a circuit ACP, a circuit IVTR, and a circuit IVTRr. The circuit ACP has a terminal mbt1p and a terminal mbt2p, and the circuit ACM has a terminal mbt1m and a terminal mbt2m.

[0278] Note that each of the switch SWR1P, the switch SWR2P, the switch SWR1PB, the switch SWR2PB, the capacitor CREP, and the circuit ACP included in the circuit ACTF[j] of the arithmetic circuit 140 corresponds to the switch SWR1, the switch SWR2, the switch SWR1B, the switch SWR2B, the capacitor CRE, and the circuit AC included in the circuit ACTF[j] in FIG. 15. Also, each of the terminal mbt1p and the terminal mbt2p of the circuit ACP in FIG. 16 corresponds to the terminal mbt1 and the terminal mbt2 of the circuit AC in FIG. 15. Therefore, regarding the connection configuration, functions, etc. of each of the switch SWR1P, the switch SWR2P, the switch SWR1PB, the switch SWR2PB, the capacitor CREP, and the circuit ACP, refer to FIG. 15. ​​​​​​​​​​​​​​​​Refer to the description of circuit ACTF[j].

[0279] The first terminal of switch SWR1M is electrically connected to circuit IVTR, terminal T1, and the first terminal of switch SWR1P. The second terminal of switch SWR1M is electrically connected to the first terminal of capacitor CREM and the first terminal of switch SWR2MB. The second terminal of switch SWR2MB is electrically connected to terminal mbt1m of circuit ACM. The first terminal of switch SWR1MB is electrically connected to circuit IVTRr, terminal T2, and the first terminal of switch SWR1PB. The second terminal of switch SWR1MB is electrically connected to the second terminal of capacitor CREM and the first terminal of switch SWR2M. The second terminal of switch SWR2M is electrically connected to wiring VCN3. Circuit ACM can have, for example, the same circuit configuration as circuit ACP, i.e., the circuit AC in FIG. 15. When a potential lower than a predetermined potential (e.g., GND potential) is input to terminal mbt1p of circuit ACP, as an example, circuit ACP outputs a signal with a value of 0 as a digital signal from terminal mbt2p. Similarly, when a potential lower than a predetermined potential (e.g., GND potential) is input to terminal mbt1m of circuit ACM, circuit ACM may be configured to output a signal with a value of 0 as a digital signal from terminal mbt2m.

[0280] For switches SWR1M, SWR2M, SWR1MB, and SWR2MB, for example, switches that can be applied in the same manner as the aforementioned switches SWR1, SWR1B, SWR2, and SWR2B can be used.

[0281] ​​​​​​​​It is possible. Also, here, switch SWR1M, switch SWR2M, switch SWR1MB, switch SWR2MB, switch SWR1P, switch SWR2P, and each of switch SWR1PB and switch SWR2PB shall be in the on state when a high-level potential is input to the control terminal, and in the off state when a low-level potential is input to the control terminal. It shall be as follows.

[0282] Also, the control terminals of switch SWR1M, switch SWR1P, switch SWR1MB, and switch S WR1PB are preferably electrically connected to the same wiring. That is, each of switch SWR1M, switch SWR1P, switch SWR1MB, and switch S WR1PB preferably operates so as to be in the on state or the off state simultaneously with each other. It is preferable.

[0283] Also, the control terminals of switch SWR2M and switch SWR2P are preferably electrically connected to the same wiring. That is, each of switch SWR2M and switch S WR2P preferably operates so as to be in the on state or the off state simultaneously with each other. It is preferable.

[0284] Also, the control terminals of switch SWR2MB and switch SWR2PB are preferably electrically connected to the same wiring. That is, each of switch SWR2MB and switch S WR2PB preferably operates so as to be in the on state or the off state simultaneously with each other. It is preferable.

[0285] Here, in the arithmetic circuit 140 of FIG. 16, circuit ACTF[j] is I flowing from wiring OL[j] out ​​​​​[j] and the current I flowing from the wiring OLB[j] Bout when reading I [j], consider. Note that the control terminals of switch SWR1M, switch SWR1P, switch SWR1MB, and switch SWR1PB are each electrically connected to the wiring SRL1, and the control terminals of switch SWR2M and switch SWR2P are each electrically connected to the wiring SRL2-1, and the control terminals of switch SWR2MB and switch SWR2PB are each electrically connected to the wiring SRL2-2. It is assumed to be the case.

[0286] Current I out [j] is I Bout If [j] is larger than I At time T04, the potential V of the first terminal of the capacitor CREP Iout is lower than the potential V of the second terminal of the capacitor CREP IBout . And between time T04 and time T05 the voltage between the first terminal and the second terminal of the capacitor CREP is held, and between time T06 and time T 07, due to the capacitive coupling of the capacitor CREP, the potential of the second terminal of the capacitor CREP becomes a potential higher than the GND potential. After time T07, the potential is input to the terminal mbt1p of the circuit ACP, and from the terminal mbt2p of the circuit ACP, a digital signal corresponding to the potential is output.

[0287] On the other hand, at time T04, the potential V of the first terminal of the capacitor CREM Iout is lower than the potential V of the second terminal of the capacitor CRE IBout M. And between time T04 and time T05 the voltage between the first terminal and the second terminal of the capacitor CREM is held, and between time T06 and time T07, due to the capacitive coupling of the capacitor CREM, the first​ The potential of terminal 1 becomes lower than the GND potential. After time T07, this potential is input to terminal mbt1m of circuit ACM, and a digital signal with a value of 0 is output from terminal mbt2m of circuit ACM. ACM's terminal mbt1m and a digital signal corresponding to the potential of terminal mbt1p is output from terminal mbt2p of circuit ACP. That is, when the current I

[0288] [j] is greater than I out [j], a digital signal corresponding to the potential of terminal mbt1p is output from terminal mbt2p of circuit ACP, and the GND potential is output from terminal mbt2m of circuit ACM. Then, a set of these two digital signals can be used as the positive output signal z output by circuit ACTF[j]. Bout [j], as described in the above operation example, at time T04, the potential V of the first terminal of capacitor CREP is higher than the potential V of the second terminal of capacitor CREP. And between time T04 and time T05, the voltage between the first terminal and the second terminal of capacitor CREP is held, and between time T06 and Z time T07, due to the capacitive coupling of capacitor CREP, the potential of the second terminal of capacitor CREP becomes lower than the GND potential. After time T07, this potential is input to terminal mbt1p of circuit ACP, and a digital signal with a value of 0 is output from terminal mbt2p of circuit ACP. On the other hand, at time T04, the potential V of the first terminal of capacitor CREM is lower than the potential V of the second terminal of capacitor CREM. j (k)

[0289] Also, when the current I out [j] is smaller than I Bout [j], as described in the above operation example, at time T04, the potential V of the first terminal of capacitor CREP is higher than the potential V of the second terminal of capacitor CREP. And between time T04 and time T05, the voltage between the first terminal and the second terminal of capacitor CREP is held, and between time T06 and Iout the second terminal of capacitor CREP becomes lower than the GND potential. After time T07, this potential is input to terminal mbt1p of circuit ACP, and a digital signal with a value of 0 is output from terminal mbt2p of circuit ACP. is higher than the potential V of the second terminal of capacitor CREP. And between time T04 and time T05, the voltage between the first terminal and the second terminal of capacitor CREP is held, and between time T06 and IBout time T07, due to the capacitive coupling of capacitor CREP, the potential of the second terminal of capacitor CREP becomes lower than the GND potential. After time T07, this potential is input to terminal mbt1p of circuit ACP, and a digital signal with a value of 0 is output from terminal mbt2p of circuit ACP. During this period, the voltage between the first and second terminals of capacitor CREP is maintained, and from time T06 to time T07, due to the capacitive coupling of capacitor CREP, the potential of the second terminal of capacitor CREP becomes lower than the GND potential. After time T07, this potential is input to terminal mbt1p of circuit ACP, and a digital signal with a value of 0 is output from terminal mbt2p of circuit ACP. ACM's terminal mbt1p and a digital signal with a value of 0 is output from terminal mbt2p of circuit ACP. P's terminal mbt1p and a digital signal with a value of 0 is output from terminal mbt2p of circuit ACP. signal is output.

[0290] On the other hand, at time T04, the potential V of the first terminal of capacitor CREM Iout is lower than the potential V of the second terminal of capacitor CRE M. IBout ​becomes higher. And between time T04 and time T05 the voltage between the first and second terminals of the capacitor CREM is held, and between time T06 and time T07, due to the capacitive coupling of the capacitor CREM, the potential of the first terminal of the capacitor CREM becomes a potential higher than the GND potential. After time T07, this potential is input to the terminal mbt1m of the circuit ACM, and a digital signal corresponding to this potential is output from the terminal mbt2m of the circuit ACM. That is, when the current I

[0291] [j] is smaller than I out [j], the GND potential is output from the terminal mbt2p of the circuit ACP, and a digital signal corresponding to the potential from the terminal mbt1p of the circuit ACM is output from the terminal mbt2m of the circuit ACM. Bout And a combination of these two digital signals can be made into the negative output signal z output by the circuit ACTF[j]. That is, when the current I [j] is smaller than I j (k) [j], the GND potential is output from the terminal mbt2p of the circuit ACP, and a digital signal corresponding to the potential from the terminal mbt1p of the circuit ACM is output from the terminal mbt2m of the circuit ACM. And a combination of these two digital signals can be made into the negative output signal z

[0292] <Configuration Example 3 of the Arithmetic Circuit> Note that in the arithmetic circuit 130 shown in FIG. 12, for the circuit MP[i, j], the wiring IL[j , the wiring ILB[j], the wiring OL[j], and the wiring OL[j] are electrically connected , but one aspect of the present invention is not limited to this. For example, the arithmetic circuit 130 can have a configuration in which the wiring I L[j] and the wiring OL[j] are combined into the wiring OL[j], and the wiring ILB[j] and the wiring O LB[j] are combined into the wiring OLB[j].

[0293] A configuration example of this arithmetic circuit is shown in FIG. 17. The arithmetic circuit 150 shown in FIG. 17 combines the wiring IL[j] and the wiring OL[j] into the wiring OL[j] in the arithmetic circuit 13 0, and combines the wiring I The configuration is such that LB[j] and the wiring OLB[j] are grouped together as the wiring OLB[j].

[0294] Also, the arithmetic circuit 150 has switching circuits TW[1] to TW[n]. Each of the switching circuits TW[1] to TW[n] has a terminal TSa, a terminal TSaB, a terminal TSb, a terminal TSbB, a terminal TSc, and a terminal TScB. The terminal T Sa is electrically connected to the wiring OL[j], the terminal TSbB is electrically connected to the circuit ILD, and the terminal TSc is electrically connected to the circuit ACTF[i]. The terminal TSaB is electrically connected to the wiring O LB[j], the terminal TSbB is electrically connected to the circuit ILD, and the terminal T ScB is electrically connected to the circuit ACTF[j].

[0295] The switching circuit TW[j] has a function of making the connection between the terminal TSa and one of the terminal TSb or the terminal TSc in a conductive state, and making the connection between the terminal TSa and the other of the terminal TSb or the terminal TSc in a non-conductive state. Also, the switching circuit TW[j] has a function of making the connection between the terminal TSaB and one of the terminal TSbB or the terminal TScB in a conductive state, and making the connection between the terminal TSaB and the other of the terminal TSbB or the terminal TS cB in a non-conductive state. That is, when it is desired to input information (for example, potential, resistance value, current value, etc.) corresponding to any one of the first data w1 to w

[0296] which are weight coefficients in any one of the circuits MP[1,j] to MP[m,j], in the switching circuit TW[j], the connection between the terminal TSa and the terminal TSb is made in a conductive state, and the connection between the terminal TSaB and the terminal TSbB is made in a conductive state, (k-1) 1 (k) and w m (k-1) n (k) to w In the case of inputting information (for example, potential, resistance value, current value, etc.) corresponding to w TSa and the terminal TSb is made in a conductive state, and the connection between the terminal TSaB and the terminal TSbB is made in a conductive state, and By setting it to the on state, the first data w1 (k-1) 1 (k) to w m (k-1) n (k) corresponding information (e.g., potential, resistance value, current value, etc.) can be supplied.

[0297] Also, when the circuit ACTF[j] wants to obtain the result of the sum of products (Equation (1.2)) of the weight coefficient and the value of the neuron signal calculated by the circuits MP[1,j] to MP[m,j], in the switching circuit TW[j], by making the connection between the terminal TSa and the terminal TSc conductive and making the connection between the terminal TSaB and the terminal TScB conductive, information (e.g., potential, current value, etc.) corresponding to the result of the sum of products can be supplied from the wiring OL[j] and the wiring OLB[j] to the circuit ACTF[j]. Also, in the circuit ACTF[j], the value of the activation function is calculated from the input result of the sum of products, and for example, as the output signal of the neuron signal z can be obtained.

[0298] j (k) Next, the switching circuit TW[j] and the circuit ILD included in the arithmetic circuit 150 will be described. FIG. 18A shows a configuration example of the switching circuit TW j] and the circuit ILD that can be applied to the arithmetic circuit 150. In FIG. 18A, for showing the electrical connection configuration of the switching circuit TW j] and the circuit ILD, the wiring OL[j], the wiring O [j] and the circuit AFP are also shown. LB[j], and the circuit AFP are also shown.

[0299] The switching circuit TW[j], as an example, includes a switch SWI, a switch SWIB, and an s It has an Ich SWO, a switch SWOB, a switch SWL, and a switch SWLB.

[0300] As an example, the circuit ILD has a current source circuit ISC. Note that the configuration of the current source circuit ISC can be the same as that of the current source circuit ISC of the circuit ILD in Fig. 14A. Therefore, the current source circuit ISC in Fig. 18A refers to the description of the circuit ISC included in the circuit ILD in Fig. 14A.

[0301] Note that as the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB described in Fig. 18A, for example, switches applicable in the same manner as the aforementioned switches SWR1, SWR1B, SWR2, and SWR2B can be used.

[0302] In an example of the switching circuit TW[j], the terminal TSa is electrically connected to the first terminal of the switch SWI, the first terminal of the switch SWO, and the first terminal of the switch SWL. The terminal TSaB is electrically connected to the first terminal of the switch SWIB, the first terminal of the switch SWOB, and the first terminal of the switch SWLB. The second terminal of the switch SWI is electrically connected to the terminal TSb1. The second terminal of the switch SWIB is electrically connected to the terminal TSbB1. The second terminal of the switch SWO is electrically connected to the terminal TSc. The second terminal of the switch SWOB is electrically connected to the terminal TScB. The second terminal of the switch SWL is electrically connected to the terminal TSb2. The second terminal of the switch SWLB is electrically connected to the terminal TSbB2. ​​​​​​​​​​​​​

[0303] The terminal TSb1 and the terminal TSb2 shown in FIG. 18A correspond to the terminal TSb shown in FIG. 17. Also, the terminal TSbB1 and the terminal TSbB2 shown in FIG. 18A correspond to the terminal TSbB shown in FIG. 17.

[0304] Similar to the wiring VCN of the circuit ILD in FIG. 14A, the wiring VCN functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. Therefore, the description of the wiring VCN in FIG. 14A is referred to for the wiring VCN in FIG. 18A.

[0305] The switching circuit TW[j] can change the circuit that becomes conductive with the wiring OL[j] and the wiring OLB[j] by switching each of the switch SWI, the switch SWIB, the switch SWO, the switch SWOB, the switch SWL, and the switch SWLB to an on state or an off state.

[0306] For example, when it is desired to input a positive weight coefficient to the circuit MP, a current corresponding to the weight coefficient may be input to the wiring OL[j], and a constant potential supplied by the wiring VCN may be input to the wiring OLB[j]. As an example, a conductive state may be established between the current source circuit ISC and the wiring OL[j], a non-conductive state may be established between the current source circuit ISC and the wiring OLB[j], a non-conductive state may be established between the circuit AFP and the wiring OL[j], a non-conductive state may be established between the circuit AFP and the wiring OLB[j], a non-conductive state may be established between the wiring VCN and the wiring OL[j], and a conductive state may be established between the wiring VCN and the wiring OLB[j]. That is, in the switching circuit TW[j], the switch SWI and the switch SWLB may be turned on, and the switches SWIB, SWO, and SWOB may be turned off. 、and turn off each of the switches SWL and SWI. As a result, the current source circuit ISC is connected to the wiring OL[j], allowing current to flow from the current source circuit ISC through the wiring OL[j] to the circuit MP. Also, since the wiring VCN is connected to the wiring OLB[j], a constant voltage from the wiring VCN is input to the wiring OLB[j].

[0307] Also, for example, when a negative weight coefficient is to be input to the circuit MP, a current corresponding to the weight coefficient is input to the wiring OLB[j], and the constant potential provided by the wiring VCN is input to the wiring OL[j]. As an example, make the connection between the current source circuit ISC and the wiring OL[j] non-conductive, make the connection between the current source circuit ISC and the wiring OLB[j] conductive, make the connection between the circuit AFP and the wiring OL[j] non-conductive, make the connection between the circuit AFP and the wiring OLB[j] non-conductive, make the connection between the wiring VCN and the wiring OL[j] conductive, and make the connection between the wiring VCN and the wiring OLB[j] non-conductive. That is, in the switching circuit TW[j], turn on the switches SWIB and SWL, and turn off each of the switches SWI, SWO, SWOB, and SWLB. As a result, the connection between the current source circuit ISC and the wiring OLB[j] becomes conductive, allowing current to flow from the current source circuit ISC through the wiring OLB[j] to the circuit MP. Also, since the wiring VCN is connected to the wiring OL[j], a constant voltage from the wiring VCN is input to the wiring OL[j].

[0308] Also, for example, when a weight coefficient of 0 is to be input to the circuit MP, the wiring OL[j], the wiring OL ​​It is only necessary to input the fixed potential given by the wiring VCN to each of B[j]. As an example, current The state between the current source circuit ISC and the wiring OL[j] is made non-conductive, and the state between the current source circuit ISC and the wiring OLB [j] is made non-conductive, the state between the circuit AFP and the wiring OL[j] is made non-conductive, The state between the circuit AFP and the wiring OLB[j] is made non-conductive, and the state between the wiring VCN and the wiring OL[j] is made conductive, and the state between the wiring VCN and the wiring OLB[j] may be made conductive. That is, in the switching circuit TW[j], the switches SWL and SWLB are turned on and the switches SWI, SWIB, SWO, and SWOB are each turned off. As a result, the state between the wiring VCN and the wiring OL[j] becomes conductive and the state between the wiring VCN and the wiring OLB[j] becomes conductive, so that a fixed voltage from the wiring VCN is input to the wiring OL j] and the wiring OLB[j]. In addition, for example, when information (for example, potential, current, etc.) is supplied from the circuit MP[i, j] to the circuit AFP, as an example, the state between the current source circuit ISC and the wiring OL[j] is made non-conductive

[0309] and the state between the current source circuit ISC and the wiring OLB[j] is made non-conductive, and the state between the circuit AFP and the wiring OL j] is made conductive, and the state between the circuit AFP and the wiring OLB[j] is made conductive and the state between the wiring VCN and the wiring OL[j] is made non-conductive, and the state between the wiring VCN and the wiring OLB[j is made non-conductive. That is, in the switching circuit TW[j], the switches SWO and SWOB are turned on, and the switches SWI, SWIB , SWL, and SWLB are each turned off. As a result, ​​Since the circuit between the circuit AFP and the circuit MP[i,j] is in a conductive state, information (e.g., potential, current, etc.) can be supplied from the circuit MP[i,j] to the circuit AFP.

[0310] Note that the switching circuit TW[j] and the circuit ILD applicable to the arithmetic circuit 150 according to one aspect of the present invention are not limited to the circuit configuration shown in FIG. 18A. The circuit configurations of the switching circuit TW[j] and the circuit ILD can be changed according to the situation. For example, a switch SWH and a switch SWHB are added to the switching circuit TW[j] shown in FIG. 18A, and a wiring VCN2 may be provided in the circuit ILD. An example of such a configuration is shown in FIG. 18B. In FIG. 18B, the first terminal of the switch SWH is electrically connected to the wiring OL[j], and the second terminal of the switch SWH is electrically connected to the wiring VCN2. Also, the first terminal of the switch SWHB is electrically connected to the wiring OLB[j],

[0311] and the second terminal of the switch SWHB is electrically connected to the wiring VCN2.

[0312] The wiring VCN2 functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, when a current (positive current) flows from the circuit ILD to the wiring OL or the wiring OLB via the switching circuit TW[j], it is preferable that the constant voltage provided by the wiring VCN2 be a high-level potential (e.g., VDD, etc.). Also, for example, when a current (negative current ) flows from the wiring OL or the wiring OLB to the circuit ILD via the switching circuit TW[j], it is preferable that the constant potential provided by the wiring VCN2 be a ground potential or a low-level potential ( e.g., VSS, etc.). In particular, the voltage provided by the wiring VCN4 is as shown in FIGS. 6A and ) ​ It is preferable that the wiring is the VCN4 described with reference to FIG. 6C.

[0313] In the circuit configuration of FIG. 18B, the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB are turned off, and the switches S WH and SWHB are turned on, whereby the voltages applied to the wiring OL[j] and the wiring O LB[J] can be input. Here, , for example, when the voltage applied by the wiring VCN2 is the same voltage as the wiring VCN4 described with reference to FIGS. 6A to 6C, from time T01 to time T02 in the operation example of the timing chart of FIG. 9 during, the switches SWR3 and SWR3B are not turned on, but the switches S WH and SWHB are turned on to apply the same voltage as the wiring VCN4 to the wiring OL[j] and the wiring O LB[j]. That is, by applying the circuit configuration of FIG. 18B to the arithmetic circuit 140, the switches SWR3 (switch SWR3B) shown in the circuit IVTR (circuit IVTRr) of FIGS. 6A to 6C can be omitted.

[0314] Here, a configuration example of the circuit MP[i,j] applicable to the arithmetic circuit 150 will be described.

[0315] FIG. 19A shows a configuration example of the circuit MP[i,j] applicable to the arithmetic circuit 150. Specifically, the circuit MP[i,j] in FIG. 19A is a circuit obtained by modifying the configuration of the circuit MP[i,j] in FIG. 13A, and combines the wiring IL[j] and the wiring OL[j into one, and combines the wiring ILB[j] and the wiring OLB[j] into one. is the case. Therefore, for the circuit MP[i,j] in FIG. 19A, refer to the description of the circuit M P[i,j] in FIG. 13A.

[0316] Next, an example of modifying the circuit MP[i,j] in FIG. 19A will be described. Note that for the modified example of the circuit M P[i,j], the parts different from the circuit MP[i,j] in FIG. 19A will be mainly described, and the description of the parts common to the circuit MP[i,j] in FIG. 19A may be omitted.

[0317] The circuit MP[i,j] shown in FIG. 19B has a configuration in which the wiring X1L[i] in the circuit MP[i,j] in FIG. 19A is replaced with the wiring WX1L[i]. That is, in the circuit MP[i,j] in FIG. 19B, the wiring WX1L[i] and the wiring WL[i] are used to switch between a conductive state and a non-conductive state between the wiring OL[j and the holding part HC, and between the wiring OLB[j] and the holding part HCr, and function as wiring for supplying a predetermined potential. Also, in the circuit MP[i,j] in FIG. 19B, the wiring WX1 L[i] and the wiring X2L[i] function as wiring for giving a current, voltage, etc. corresponding to the second data z input to the circuit MP[i,j]. Note that the specific circuit configuration of FIG. 19B will be described in Embodiment 3. i (k- 1)

[0318] Next, an example of modifying the circuit MP[i,j] in FIG. 19A, which is different from FIG. 19B, will be described. The circuit MP[i,j] shown in FIG. 19C is a modified example of the circuit MP[i,j] in FIG. 19A. The circuit MP[i,j] in FIG. 19C is the same as the circuit MP[i,j] in FIG. 19A in terms of the circuit ​​​​​​​It has a path MC and a circuit MCr. However, the circuit MP[i,j] in FIG. 19C is different from the circuit MP[i,j] in FIG. 19A in that the circuit MCr does not include a holding section HCr. Since the circuit MCr does not have a holding section HCr, the arithmetic circuit to which the circuit MP[i,j] in FIG. 19C is applied may not have wiring for supplying the potential held in the holding section HCr. In addition, the circuit MCr may not be electrically connected to the wiring WL[i].

[0319] In the circuit MP[i,j] of FIG. 19C, the holding section HC included in the circuit MC is electrically connected to the circuit MCr. That is, the circuit MP[i,j] of FIG. 19C is configured such that the circuit MCr and the circuit MC share the holding section HC with each other. As an example, an inverted signal can be supplied from the holding section HC to the circuit MCr for the signal held in the holding section HC. Thereby, different operations can be performed by the circuit MC and the circuit MCr. Or, the internal circuit configurations of the circuit MC and the circuit MCr are made different, and as a result, the magnitudes of the currents output by the circuit MC and the circuit MCr for the same signal held in the holding section HC can be made different. Here, by holding the potential corresponding to the first data w in the holding section HC and supplying the potential corresponding to the second data z to the wiring X1L[i] and the wiring X2L[i], the circuit MP[i,j] supplies the first data w and the second Since the circuit MCr does not have a holding section HCr, the arithmetic circuit to which the circuit MP[i,j] in FIG. 19C is applied may not have wiring for supplying the potential held in the holding section HCr. In addition, the circuit MCr may not be electrically connected to the wiring WL[i].

[0320] In the circuit MP[i,j] of FIG. 19C, the holding section HC included in the circuit MC is electrically connected to the circuit MCr. That is, the circuit MP[i,j] of FIG. 19C is configured such that the circuit MCr and the circuit MC share the holding section HC with each other. As an example, an inverted signal can be supplied from the holding section HC to the circuit MCr for the signal held in the holding section HC. Thereby, different operations can be performed by the circuit MC and the circuit MCr. Or, the internal circuit configurations of the circuit MC and the circuit MCr are made different, and as a result, the magnitudes of the currents output by the circuit MC and the circuit MCr for the same signal held in the holding section HC can be made different. Here, by holding the potential corresponding to the first data w in the holding section HC and supplying the potential corresponding to the second data z to the wiring X1L[i] and the wiring X2L[i], the circuit MP[i,j] supplies the first data w and the second data z to the wiring OL[j] and the wiring OLB[j]. That is, the circuit MP[i,j] is configured such that the circuit MCr and the circuit MC share the holding section HC with each other. w i (k-1) j (k) Here, the holding section HC holds the potential corresponding to the first data w and supplies the potential corresponding to the second data z i (k-1) to the wiring X1L[i] and the wiring X2L[i]. Thereby, the circuit MP[i,j] supplies the first data w and the second data z to the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k) And the second Data z i (k-1) can output a current corresponding to the product with. Note that the specific circuit configuration of FIG. 19C will be described in Embodiment 3. will be described in Embodiment 3.

[0321] The circuit MP[i,j] shown in FIG. 19D is a modification of the circuit MP[i,j] in FIG. 19A and is also a modification of the circuit MP[i,j] in FIG. 13C. Specifically, the circuit MP i,j] in FIG. 19D combines the wiring IL[j] and the wiring OL[j] into one wiring OL[j and combines the wiring ILB[j] and the wiring OLB[j] into one wiring OLB[j] . Therefore, for the circuit MP[i,j] in FIG. 19D , refer to the description of the circuit MP[i,j] in FIG. 13C.

[0322] The circuit MP[i,j] shown in FIG. 19E is a modification of the circuit MP[i,j] in FIG. 19A and is also a modification of the circuit MP[i,j] in FIG. 13D. Specifically, the circuit MP i,j] in FIG. 19D has a configuration in which the wiring IL[j] and the wiring ILB[j] are not provided in FIG. 13D . Therefore, for the circuit MP[i,j] in FIG. 19D, refer to the description of the circuit MP[i,j] in FIG. 13D.

[0323] Note that this embodiment can be appropriately combined with other embodiments shown in this specification .

[0324] (Embodiment 3) In this embodiment, a specific configuration example of the circuit MP described in Embodiment 1 and Embodiment 2 will be described. will be described.

[0325] Note that in Embodiment 1 and Embodiment 2, the symbol of the circuit MP is the position in the array unit ALP [1,1], [i,j], [m,n], etc. are appended to indicate the positions. In this embodiment, unless otherwise specified, the descriptions of [1,1], [i,j], [m,n], etc. for the circuit MP symbol are omitted.

[0326] <Configuration Example 1> First, an example of the circuit configuration applicable to the circuit MP in FIG. 13A will be described. The circuit MP shown in FIG. 20A is an example of the configuration of the circuit MP in FIG. 13A. The circuit MC included in the circuit MP in FIG. 20A has, as an example, a transistor M1, switches S2 to S5, and a capacitor C1. Note that, for example, the switch S2, the switch S5, and the capacitor C1 constitute a holding unit HC.

[0327] The switches S2 to S5 may be electrical switches or mechanical switches. Also, as the electrical switch, for example, a transistor may be used. That is, the switches S2 to S5 may be the same type of transistors as the transistor M1. In particular, for the switch S2, for the purpose of holding the potential at the first terminal of the capacitor C1 for a long time, it is preferable to apply an OS transistor with a very small off-current. Note that the OS transistor will be described in detail in Embodiment 5.

[0328] In the circuit MP in FIG. 20A, the circuit MCr has a circuit configuration substantially the same as that of the circuit MC. Therefore, to distinguish the circuit elements and the like of the circuit MCr from those of the circuit MC, the symbol "r" is appended.

[0329] The transistor M1 shown in FIG. 20A has, as an example, gates above and below the channel. It is an n-channel transistor with a multi-gate structure having, and transistor M1 is It has a first gate and a second gate. However, in this specification and the like, for convenience, as an example, the first gate may be referred to as the gate (which may be described as the front gate in some cases), and the second gate as the back gate. However, the first gate and the second gate can be interchanged with each other. Therefore, in this specification and the like, the phrase "gate" can be described by interchanging it with the phrase "back gate". Similarly, the phrase "back gate" can be described by interchanging it with the phrase "gate". As a specific example, "the gate is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring" This connection configuration can be replaced with the connection configuration of "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring". For example, as shown in FIG. 20 B, the back gate of transistor M1 may be electrically connected to the first terminal of capacitor C1 and the first terminal of switch S 2.

[0330] Also, the semiconductor device according to one aspect of the present invention does not depend on the connection configuration of the back gate of the transistor. In transistor M1 illustrated in FIG. 20A, the back gate is illustrated, and the connection configuration of the back gate is not illustrated, but the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, in order to increase the on-current of the transistor, the gate and the back gate may be electrically connected. That is, for example, the gate and the back gate of transistor M1 may be electrically connected. It may be connected pneumatically. Also, for example, in a transistor having a back gate, in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, a wiring electrically connected to an external circuit or the like may be provided to apply a potential to the back gate of the transistor by the external circuit or the like. Note that this applies not only to the transistor shown in Fig. 20A but also to the transistors described in other parts of the specification or the transistors shown in other drawings. In order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, a wiring electrically connected to an external circuit or the like may be provided to apply a potential to the back gate of the transistor by the external circuit or the like. Note that this applies not only to the transistor shown in Fig. 20A but also to the transistors described in other parts of the specification or the transistors shown in other drawings. Note that this applies not only to the transistor shown in Fig. 20A but also to the transistors described in other parts of the specification or the transistors shown in other drawings. Similarly, the same applies to the transistors described in other parts of the specification or the transistors shown in other drawings.

[0331] Also, the semiconductor device according to one aspect of the present invention is independent of the structure of the transistors included in the semiconductor device. For example, the transistor M1 shown in Fig. 20A may be configured not to have a back gate, that is, as a single-gate structure transistor as shown in Fig. 20C. Also, some transistors may have a configuration with a back gate, and another part of the transistors may have a configuration without a back gate. Note that this applies not only to the circuit diagram shown in Fig. 20A but also to the transistors described in other parts of the specification or the transistors shown in other drawings. Also, the semiconductor device according to one aspect of the present invention is independent of the structure of the transistors included in the semiconductor device. For example, the transistor M1 shown in Fig. 20A may be configured not to have a back gate, that is, as a single-gate structure transistor as shown in Fig. 20C. Also, the semiconductor device according to one aspect of the present invention is independent of the structure of the transistors included in the semiconductor device. For example, the transistor M1 shown in Fig. 20A may be configured not to have a back gate, that is, as a single-gate structure transistor as shown in Fig. 20C. Also, the semiconductor device according to one aspect of the present invention is independent of the structure of the transistors included in the semiconductor device. For example, the transistor M1 shown in Fig. 20A may be configured not to have a back gate, that is, as a single-gate structure transistor as shown in Fig. 20C. Also, some transistors may have a configuration with a back gate, and another part of the transistors may have a configuration without a back gate. Note that this applies not only to the circuit diagram shown in Fig. 20A but also to the transistors described in other parts of the specification or the transistors shown in other drawings. Similarly, the same applies to the transistors described in other parts of the specification or the transistors shown in other drawings.

[0332] Also, in this specification and the like, transistors with various structures can be used as the transistors. Therefore, there is no limitation on the type of transistor used. As an example of the transistor, a transistor having single-crystalline silicon, or a transistor having a non-single-crystalline semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used. Also, in this specification and the like, transistors with various structures can be used as the transistors. Therefore, there is no limitation on the type of transistor used. As an example of the transistor, a transistor having single-crystalline silicon, or a transistor having a non-single-crystalline semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used. As an example of the transistor, a transistor having single-crystalline silicon, or a transistor having a non-single-crystalline semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used. As an example of the transistor, a transistor having single-crystalline silicon, or a transistor having a non-single-crystalline semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used. Alternatively, it is possible to use a thin film transistor (TFT) in which those semiconductors are thinned, etc. When using a TFT, there are various advantages. For example, since it can be manufactured at a lower temperature than in the case of single crystal silicon, it is possible to reduce the manufacturing cost or avoid increasing the size of the manufacturing equipment. Since the manufacturing equipment can be made larger, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, it can be manufactured at a low cost. Or, since the manufacturing temperature is low, a substrate with weak heat resistance can be used. Therefore, transistors can be manufactured on a substrate having translucency. Or, light transmission in a display element can be controlled using a transistor on a substrate having translucency. Or, since the film thickness of the transistor is thin, a part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved.

[0333] As an example of the transistor, a transistor having a compound semiconductor (e.g., SiGe, GaAs, etc.), or an oxide semiconductor (e.g., Zn - O, In - Ga - Zn - O, In - Zn - O, In - Sn - O (ITO), Sn - O, Ti - O, Al - Zn - Sn - O (AZTO), In - Sn - Zn - O, etc.) can be used. Or, a thin film transistor in which these compound semiconductors or these oxide semiconductors are thinned can be used. By these, since the manufacturing temperature can be lowered, for example, it becomes possible to manufacture a transistor at room temperature. As a result, a transistor can be directly formed on a substrate with low heat resistance, such as a plastic substrate or a film substrate. Note that these compound semiconductors or oxide semiconductors are not only used for the channel portion of the transistor, but also They can also be used for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistor elements, pixel electrodes, or electrodes having translucency. Since they can be formed simultaneously with the transistor, the cost can be reduced.

[0334] As an example of the transistor, a transistor formed using an inkjet method or a printing method can be used. With these, manufacturing can be carried out at room temperature, at a low degree of vacuum, or on a large substrate. Therefore, since manufacturing can be carried out without using a mask (reticle), the layout of the transistor can be easily changed. Or, since manufacturing can be carried out without using a resist, the material cost is reduced and the number of processes can be reduced. Or, since it is possible to apply a film only to the necessary parts, it can be manufactured at low cost without wasting materials compared to the manufacturing method of etching after forming a film over the entire surface.

[0335] As an example of the transistor, a transistor having an organic semiconductor or a carbon nanotube can be used. With these, a transistor can be formed on a substrate that can be bent. A device using a transistor having an organic semiconductor or a carbon nanotube can be made resistant to impact.

[0336] In addition, as the transistor, transistors with various other structures can also be used. For example, as the transistor, a MOS transistor, a junction transistor, a bipolar transistor, etc. can be used. By using a MOS transistor as the transistor, the size of the transistor can be reduced. Therefore, a large number of transistors ... A transistor can be mounted. By using a bipolar transistor as the transistor, a large current can be passed. Therefore, the circuit can be operated at high speed. Note that a MOS transistor and a bipolar transistor may be formed mixed on one substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc. By using a bipolar transistor as the transistor, a large current can be passed. Therefore, the circuit can be operated at high speed. Note that a MOS transistor and a bipolar transistor may be formed mixed on one substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc. Note that a MOS transistor and a bipolar transistor may be formed mixed on one substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc. Note that a MOS transistor and a bipolar transistor may be formed mixed on one substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc.

[0337] As an example of the transistor, a transistor having a structure in which gate electrodes are disposed above and below the active layer can be applied. By adopting a structure in which gate electrodes are disposed above and below the active layer, a circuit configuration in which a plurality of transistors are connected in parallel is obtained. Therefore, since the channel formation region increases, the current value can be increased. Or, by adopting a structure in which gate electrodes are disposed above and below the active layer, a depletion layer is likely to be formed, so that the S value can be improved. As an example of the transistor, a transistor having a structure in which gate electrodes are disposed above and below the active layer can be applied. By adopting a structure in which gate electrodes are disposed above and below the active layer, a circuit configuration in which a plurality of transistors are connected in parallel is obtained. Therefore, since the channel formation region increases, the current value can be increased. As an example of the transistor, a transistor having a structure in which gate electrodes are disposed above and below the active layer can be applied. By adopting a structure in which gate electrodes are disposed above and below the active layer, a circuit configuration in which a plurality of transistors are connected in parallel is obtained. Therefore, since the channel formation region increases, the current value can be increased. Or, by adopting a structure in which gate electrodes are disposed above and below the active layer, a depletion layer is likely to be formed, so that the S value can be improved. As an example of the transistor, a transistor having a structure in which gate electrodes are disposed above and below the active layer can be applied. By adopting a structure in which gate electrodes are disposed above and below the active layer, a circuit configuration in which a plurality of transistors are connected in parallel is obtained. Therefore, since the channel formation region increases, the current value can be increased. Or, by adopting a structure in which gate electrodes are disposed above and below the active layer, a depletion layer is likely to be formed, so that the S value can be improved. As an example of the transistor, a transistor having a structure in which gate electrodes are disposed above and below the active layer can be applied. By adopting a structure in which gate electrodes are disposed above and below the active layer, a circuit configuration in which a plurality of transistors are connected in parallel is obtained. Therefore, since the channel formation region increases, the current value can be increased. Or, by adopting a structure in which gate electrodes are disposed above and below the active layer, a depletion layer is likely to be formed, so that the S value can be improved. As an example of the transistor, a transistor having a structure in which gate electrodes are disposed above and below the active layer can be applied. By adopting a structure in which gate electrodes are disposed above and below the active layer, a circuit configuration in which a plurality of transistors are connected in parallel is obtained. Therefore, since the channel formation region increases, the current value can be increased. Or, by adopting a structure in which gate electrodes are disposed above and below the active layer, a depletion layer is likely to be formed, so that the S value can be improved.

[0338] As an example of the transistor, a transistor having a structure in which a gate electrode is disposed above the active layer, a transistor having a structure in which a gate electrode is disposed below the active layer, a positive stagger structure, a reverse stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series can be used. Or, as the transistor, a planar type, a FIN type (fin type), a TRI-GATE type (trigate type), a top gate type, a bottom gate type, a double gate type (gates are disposed above and below the channel), etc. can have various configurations. As an example of the transistor, a transistor having a structure in which a gate electrode is disposed above the active layer, a transistor having a structure in which a gate electrode is disposed below the active layer, a positive stagger structure, a reverse stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series can be used. Or, as the transistor, a planar type, a FIN type (fin type), a TRI-GATE type (trigate type), a top gate type, a bottom gate type, a double gate type (gates are disposed above and below the channel), etc. can have various configurations. As an example of the transistor, a transistor having a structure in which a gate electrode is disposed above the active layer, a transistor having a structure in which a gate electrode is disposed below the active layer, a positive stagger structure, a reverse stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series can be used. Or, as the transistor, a planar type, a FIN type (fin type), a TRI-GATE type (trigate type), a top gate type, a bottom gate type, a double gate type (gates are disposed above and below the channel), etc. can have various configurations. As an example of the transistor, a transistor having a structure in which a gate electrode is disposed above the active layer, a transistor having a structure in which a gate electrode is disposed below the active layer, a positive stagger structure, a reverse stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series can be used. Or, as the transistor, a planar type, a FIN type (fin type), a TRI-GATE type (trigate type), a top gate type, a bottom gate type, a double gate type (gates are disposed above and below the channel), etc. can have various configurations. As an example of the transistor, a transistor having a structure in which a gate electrode is disposed above the active layer, a transistor having a structure in which a gate electrode is disposed below the active layer, a positive stagger structure, a reverse stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series can be used. Or, as the transistor, a planar type, a FIN type (fin type), a TRI-GATE type (trigate type), a top gate type, a bottom gate type, a double gate type (gates are disposed above and below the channel), etc. can have various configurations. As an example of the transistor, a transistor having a structure in which a gate electrode is disposed above the active layer, a transistor having a structure in which a gate electrode is disposed below the active layer, a positive stagger structure, a reverse stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series can be used. Or, as the transistor, a planar type, a FIN type (fin type), a TRI-GATE type (trigate type), a top gate type, a bottom gate type, a double gate type (gates are disposed above and below the channel), etc. can have various configurations. As an example of the transistor, a transistor having a structure in which a gate electrode is disposed above the active layer, a transistor having a structure in which a gate electrode is disposed below the active layer, a positive stagger structure, a reverse stagger structure, a structure in which the channel region is divided into a plurality of regions, ...

Claims

【Claim 1】 having a cell and a first circuit; the first circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a first integrating circuit, a second integrating circuit, and a second circuit; the first integrating circuit includes a first operational amplifier and a first load; the second integrating circuit includes a second operational amplifier and a second load; the cell is electrically connected to one terminal of the third switch via a first wiring; the cell is electrically connected to one terminal of the fourth switch via the first wiring; the cell is electrically connected to one terminal of the first load via the first wiring; the cell is electrically connected to one terminal of the seventh switch via a second wiring; the cell is electrically connected to one terminal of the eighth switch via the second wiring; the cell is electrically connected to one terminal of the second load via the first wiring; the other terminal of the third switch is electrically connected to a third wiring to which a constant voltage is supplied; the other terminal of the fourth switch is electrically connected to a first input terminal of the first operational amplifier; the other terminal of the first load is electrically connected to one terminal of the first switch; the second input terminal of the first operational amplifier is electrically connected to a fourth wiring; the output terminal of the first operational amplifier is electrically connected to one terminal of the first switch; the other terminal of the seventh switch is electrically connected to the third wiring; the other terminal of the eighth switch is electrically connected to a first input terminal of the second operational amplifier; the other terminal of the second load is electrically connected to one terminal of the fifth switch; the second input terminal of the second operational amplifier is electrically connected to a fifth wiring; the output terminal of the second operational amplifier is electrically connected to one terminal of the fifth switch; the other terminal of the first switch is electrically connected to one terminal of the first capacitor; the other terminal of the first switch is electrically connected to one terminal of the second switch; the other terminal of the fifth switch is electrically connected to the other terminal of the first capacitor; the other terminal of the fifth switch is electrically connected to one terminal of the sixth switch; the other terminal of the second switch is electrically connected to a sixth wiring to which a reference potential is supplied; The other terminal of the sixth switch is electrically connected to the second circuit. The fourth wiring and the fifth wiring have a function of supplying the same voltage or different voltages to each other. The cell has a function of holding first data, and when second data is input to the cell, a first current corresponding to the first data and the second data flows between the cell and the first wiring and a second current corresponding to the first data and the second data flows between the cell and the second wiring. The first integrating circuit has a function of outputting a first potential according to the first current input to the first integrating circuit. The second integrating circuit has a function of outputting a second potential according to the second current input to the second integrating circuit. The first capacitor has a function of holding a differential voltage between the first potential and the second potential. The second circuit is a semiconductor device having a function of outputting a signal according to the differential voltage. **Claim 2** In claim 1, The first load has a second capacitor. The second load is a semiconductor device having a third capacitor. **Claim 3** An electronic device having the semiconductor device according to claim 1 or claim 2 and a housing, wherein the semiconductor device performs neural network operations.

Images