Semiconductor devices and electronic equipment

Abstract

To provide semiconductor and electronic devices that can perform calculations with low power consumption. [Solution] The arithmetic circuit is a semiconductor device having an array unit ALP and a circuit AFP, wherein the array unit ALP has circuits MP[1,j] to MP[m,j]. The circuit AFP also has a circuit ACTF[j], which has a capacitor CRE, a circuit AC, terminal T1, and terminal T2. Each of the circuits MP[1,j] to MP[m,j] is electrically connected to wiring XLS[1] to wiring XLS[m]. Wiring OL[j] is electrically connected to terminal T1, terminal T1 is electrically connected to the first terminal of capacitor CRE, wiring OLB[j] is electrically connected to terminal T2, terminal T2 is electrically connected to the second terminal of capacitor CRE. The voltage (charge) stored in capacitor CRE is input to circuit AC, and the amount of voltage (charge) stored in capacitor CRE is sensed.

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices and electronic devices.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention is: Process, machine, manufacture, or composition of matter This relates to the technology of one aspect of the present invention disclosed more specifically herein. The fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, Memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, and A manufacturing method or inspection method thereof can be given as an example. [Background technology]

[0003] Currently, there is a lot of activity in developing integrated circuits that mimic the structure of the human brain. The pathway is an electronic circuit that incorporates the brain's structure, and the "neurons" and "s It has a circuit equivalent to a "naps." Therefore, such an integrated circuit is called a "neuromorph." It is sometimes called "Brainmorphic," "Brain-Inspired," or "Brain-Inspired." The integrated circuit has a non-von Neumann architecture, and its power consumption increases with increasing processing speed. Compared to the larger von Neumann architecture, it performs parallel processing with extremely low power consumption. It is expected to happen.

[0004] Information processing models that mimic neural networks with "neurons" and "synapses" are artificial This is called a neural network (ANN). For example, see Non-Patent Document 1 and Non-Patent Document For method 2, SRAM (Static Random Access Memory) is used. The document discloses a computing device that constitutes an artificial neural network. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-Patent Document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In artificial neural networks, the strength of synaptic connections between two neurons is The coefficient is calculated by multiplying the degree (sometimes called the weighting coefficient) by the signal transmitted between the two neurons. Calculations are performed. In particular, in hierarchical artificial neural networks, multiple first layers The synaptic connection strength between each neuron and one of the second neurons in layer 2, and the first Each signal input from multiple first neurons in the second layer to one of the second neurons in the second layer. It is necessary to multiply and add them together (perform a sum-of-products operation), and an artificial neural network is needed. Depending on the scale, for example, the number of such coupling intensities and the number of parameters indicating the signal are determined. In other words, artificial neural networks have a large number of layers, neurons, etc. The number of circuits corresponding to "neurons" and "synapses" increases accordingly, and the computational capacity The amount can also become enormous.

[0007] For example, neural network operations include not only multiply-accumulate operations but also activation function operations, etc. One example is the large size of the artificial neural network when calculating activation functions. The power consumption tends to be higher.

[0008] One aspect of the present invention is a semiconductor device in which a hierarchical artificial neural network is constructed. One of the objectives is to provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention is a semiconductor device with low power consumption. One of the objectives is to provide the following. Alternatively, one aspect of the present invention is a novel semiconductor device, etc. One of the objectives is to provide the above-mentioned semiconductor device. Alternatively, one aspect of the present invention relates to an electric device having the above-mentioned semiconductor device. One of the objectives is to provide sub-devices.

[0009] The problems addressed by one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other issues. These other issues are described in the following section. This is an issue not mentioned in the specification. Issues not mentioned in this section can be found in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention addresses at least one of the problems listed above and other problems. This invention solves the problems. One aspect of the present invention addresses the problems listed above, as well as other problems. You don't need to solve all of them. [Means for solving the problem]

[0010] (1) One aspect of the present invention comprises a cell and a first circuit, the first circuit comprising a first capacitor and a first input The cell has a terminal and a second input terminal, and the cell is electrically connected to the first input terminal via the first wiring. The cell is connected, and is electrically connected to the second input terminal via the second wiring, and the cell is connected to the first The function of retaining data, and the input of second data into the cell, which connects the cell and the first wiring. A first current corresponding to the first data and the second data is passed between them, and between the cell and the second wiring It has a function to supply a second current according to the first data and the second data, and the first capacitance is the first It has the function of maintaining the difference voltage between a first potential corresponding to the current and a second potential corresponding to the second current. It is a semiconductor device.

[0011] (2) Alternatively, in one aspect of the present invention, in the configuration of (1) above, the first circuit has a second circuit, The second circuit is a semiconductor circuit that has the function of acquiring the differential voltage and outputting a signal corresponding to the differential voltage. It is a body device.

[0012] (3) Alternatively, in one aspect of the present invention, in the configuration of (2) above, the first circuit is a first current-voltage converter The circuit, the second current-voltage conversion circuit, the first switch, the second switch, the third switch, It has a fourth switch, and the first input terminal is connected to the first terminal of the first switch, and the first current voltage variable The first terminal of the switching circuit is electrically connected to the second terminal of the second switch, and the second terminal of the first switch is electrically connected to the second terminal of the second switch. The first terminal is electrically connected to the first terminal of the first capacitor, and the second input terminal is connected to the third switch. The first terminal of the switch is electrically connected to the first terminal of the second current-voltage conversion circuit, and the third switch The second terminal of the switch is electrically connected to the first terminal of the fourth switch and the second terminal of the first capacitor. The second terminal of the fourth switch is electrically connected to the first terminal of the second circuit, and the first current voltage The conversion circuit, in accordance with the first current input to the first terminal of the first current-voltage conversion circuit, The second current-voltage conversion circuit has the function of setting the potential of the first terminal of the voltage conversion circuit to the first potential, and the second current-voltage conversion circuit is In response to the second current input to the first terminal of the second current-voltage conversion circuit, the second current-voltage conversion circuit This is a semiconductor device that has the function of changing the potential of the first terminal to the second potential.

[0013] (4) Alternatively, in one aspect of the present invention, in the configuration of (3) above, the second terminal of the second switch is The first circuit is electrically connected to the third wiring which provides a quasi-potential, and the first circuit consists of the first switch and the third switch. Turn the first capacitor ON, and the second and fourth switches OFF, The function of setting the first terminal of the capacitor to the first potential and the second terminal of the first capacitor to the second potential, and the first switch Then, turn the third switch and the fourth switch to the OFF position, and turn the second switch to the ON position. By changing the first terminal of the first capacitor from the first potential to the reference potential, capacitive coupling occurs. A function to change the second potential of the second terminal of the first capacitor to the third potential, a first switch, and a second switch Turn the switch and the third switch to the OFF position, and the fourth switch to the ON position, and activate the second circuit. A semiconductor device having a function to input a third potential corresponding to the differential voltage to the first terminal. .

[0014] (5) Alternatively, one aspect of the present invention comprises a cell and a first circuit, the first circuit comprising a first capacitance and a It has two capacitances, a first input terminal, and a second input terminal, and the cell is connected via the first wiring to the first The cell is electrically connected to the input terminal, and via the second wiring, it is electrically connected to the second input terminal. The cell has the function of holding the first data, and when the second data is entered into the cell... Then, a first current corresponding to the first data and the second data is passed between the cell and the first wiring, and the It has a function of passing a second current between the wire and the second wiring according to the first data and the second data. The first capacitance is the first potential corresponding to the first current, the second potential corresponding to the second current, and the first difference between them. It has a function to maintain voltage, and the second capacitor has a first potential corresponding to the first current and a second potential corresponding to the second current. This semiconductor device has the function of maintaining a second potential and a second differential voltage.

[0015] (6) Alternatively, in one aspect of the present invention, in the configuration of (5) above, the first circuit comprises the second circuit and the third The circuit has a first differential voltage with reference to the potential of the first terminal of the first capacitor. The third circuit has the function of acquiring and outputting a first signal corresponding to the first differential voltage, and the second capacitor The second differential voltage is obtained with the potential of the second terminal as the reference, and the second signal corresponding to the second differential voltage is obtained. This is a semiconductor device that has the function of outputting a number.

[0016] (7) Alternatively, in one aspect of the present invention, in the configuration of (6) above, the first circuit is a first current-voltage converter The circuit, the second current-voltage conversion circuit, the first switch, the second switch, the third switch, The 4th switch, the 5th switch, the 6th switch, the 7th switch, the 8th switch, The first input terminal has the first terminal of the first switch, the first terminal of the fifth switch, and the first The first terminal of the current-voltage conversion circuit is electrically connected to the second terminal of the first switch. The first terminal of the switch and the first terminal of the first capacitor are electrically connected, and the fifth terminal of the switch Terminal 2 is electrically connected to terminal 1 of switch 6 and terminal 1 of capacitor 2. The two input terminals are the first terminal of the third switch, the first terminal of the seventh switch, and the second current-voltage converter. The first terminal of the switching circuit is electrically connected to the second terminal of the third switch, and the second terminal of the third switch is electrically connected to the fourth switch. The first terminal is electrically connected to the second terminal of the first capacitor, and the second terminal of the seventh switch is connected to the eighth The first terminal of the switch and the second terminal of the second capacitor are electrically connected, and the fourth terminal of the switch Terminal 2 is electrically connected to terminal 1 of the second circuit, and terminal 2 of the sixth switch is connected to terminal 3 of the third The first terminal of the circuit is electrically connected, and the first current-voltage conversion circuit is the first current-voltage conversion circuit. In accordance with the first current input to terminal 1, the potential of terminal 1 of the first current-voltage conversion circuit is changed to the first current The second current-voltage conversion circuit has a function to set the position, and the input to the first terminal of the second current-voltage conversion circuit is A function that sets the potential of the first terminal of the second current-voltage conversion circuit to the second potential in accordance with the second current. This is a semiconductor device having [a certain feature].

[0017] (8) Alternatively, in one aspect of the present invention, in the configuration of (7) above, the second terminal of the second switch is The second terminal of the eighth switch is electrically connected to the third wiring which provides the reference potential. The third wiring is electrically connected, and the first circuit consists of the first switch and the third switch. Set to the ON state, turn off the second switch and the fourth switch, and turn off the first terminal of the first capacitor. The function of setting the first potential and the second terminal of the first capacitor to the second potential, the fifth switch and the seventh switch Turn the switch to the ON position, and the 6th switch and the 8th switch to the OFF position, and the 2nd switch The function sets the first terminal of the capacitor to the first potential and the second terminal of the second capacitor to the second potential, and the first switch Turn the first switch, the third switch, and the fourth switch to the OFF position, and turn the second switch to the ON position. By changing the first terminal of the first capacitor from the first potential to the reference potential, capacitive coupling is achieved. The first capacitor has a function to change the second potential of the second terminal to the third potential, and a fifth switch, Turn off the 6th switch and the 7th switch, and turn on the 8th switch, and then turn on the 2nd switch By changing the second terminal of the capacitance from the second potential to the reference potential, the first capacitance is coupled. A function to change the first potential of the first terminal of the quantity to the fourth potential, a first switch, and a second switch. And, by turning the third switch to the OFF position and the fourth switch to the ON position, the first of the second circuit A function to input a third potential corresponding to the first differential voltage to the terminal, a fifth switch, and a seventh switch. And, turn off the 8th switch and turn on the 6th switch, and the 1st of the 3rd circuit This is a semiconductor device having a function to input a fourth potential corresponding to a second differential voltage to a terminal.

[0018] (9) Alternatively, in one aspect of the present invention, in any one of the configurations (1) to (8) above, the cell is It has a first cell and a second cell, and the first cell has a first wiring, a second wiring, and a first input wiring The wire and the second input wiring are electrically connected, and the second cell is connected to the first wiring, the second wiring, and It is electrically connected to the first input wiring and the second input wiring, and the first input wiring and the second input wiring Each has the function of providing a potential corresponding to the second data, and the first cell is connected to the first input wiring. When the first input potential is input and the second input potential is input to the second input wiring, the first current The function is to send a current to the first wiring, and the second input potential is input to the first input wiring, and the second input wiring When the first input potential is applied, it has the function of flowing the second current through the second wiring, and the second current through the first input wiring. When an input potential is applied and the second input potential is applied to the second input wiring, the first cell and the second It has the function of making the connection between the first wiring and the second wiring non-conductive, and the second The cell is configured such that the first input potential is input to the first input wiring and the second input potential is input to the second input wiring. When power is applied, it has the function of flowing a second current to the second wiring and inputting the second input potential to the first input wiring. Furthermore, when the first input potential is input to the second input wiring, the function is to flow the first current through the first wiring. And the second input potential is input to the first input wiring, and the second input potential is input to the second input wiring. When this occurs, the connection between the second cell and the first wiring, and between the second cell and the second wiring, is made non-conductive. It is a semiconductor device that has the function of [doing something].

[0019] (10) Alternatively, in one aspect of the present invention, in the configuration of (9) above, the first cell is the first transistor And the 9th switch, the 10th switch, the 11th switch, the 12th switch, and the 3rd switch The second cell has a quantity and a second transistor, a thirteenth switch, and a fourteenth switch. It has a 15th switch, a 16th switch, and a 4th capacitor, and the first transistor The terminals are the first terminal of the 9th switch, the first terminal of the 10th switch, and the terminal of the 11th switch. The gate of the first transistor is electrically connected to terminal 1 of the third capacitor, The first terminal of the 12th switch is electrically connected to the second terminal of the 9th switch, and the second terminal of the 12th switch is electrically connected to the first terminal of the 9th switch. The second terminal of the switch is electrically connected, and the second terminal of the 10th switch is electrically connected to the first wiring. The control terminal of the 10th switch is electrically connected to the 1st input wiring, and the 11th switch is electrically connected to the 11th input wiring. The second terminal of the switch is electrically connected to the second wiring, and the control terminal of the 11th switch is the Electrically connected to the 2 input wiring, the first terminal of the second transistor is connected to the first terminal of the 13th switch. The terminal, the first terminal of the 14th switch, and the first terminal of the 15th switch are electrically connected. The gate of the second transistor is connected to the first terminal of the fourth capacitor and the first terminal of the sixteenth switch. , is electrically connected to the second terminal of the 13th switch, and the second terminal of the 16th switch is electrically connected to the second terminal of the 16th switch. The 14th switch is connected to the 2nd terminal, and the 14th switch is electrically connected to the 2nd wiring. The control terminal of the switch is electrically connected to the first input wiring, and the second terminal of the 15th switch is connected to the The control terminal of the 15th switch is electrically connected to the 2nd input wiring, and is electrically connected to the 1st input wiring. It is a semiconductor device.

[0020] (11) Alternatively, in one aspect of the present invention, in the configuration of (10) above, the 12th switch is the 3rd transistor The transistor has a third transistor having a metal oxide in the channel formation region, and the 16th transistor The switch has a fourth transistor, and the fourth transistor has a metal oxide in the channel formation region. It is a semiconductor device that contains an object.

[0021] (12) Alternatively, one aspect of the present invention comprises a semiconductor device from any one of (1) to (11) above, and a housing. It is an electronic device that has and performs neural network calculations using a semiconductor device.

[0022] In this specification, a semiconductor device is a device that utilizes semiconductor properties. Circuits containing structural elements (transistors, diodes, photodiodes, etc.), and circuits having the same This refers to devices, etc. It also refers to all devices that can function by utilizing semiconductor properties. For example, Integrated circuits, chips containing integrated circuits, and electronic components that house chips in a package are called semiconductors. This is an example of a device. Furthermore, storage devices, display devices, light-emitting devices, lighting devices, and electronic equipment are also examples. It is a semiconductor device in itself, and may have a semiconductor device.

[0023] Furthermore, if it is stated in this specification, etc., that X and Y are connected, then X and When Y is electrically connected, when X and Y are functionally connected, and when X and The case in which Y and are directly connected is disclosed in this specification, etc. Furthermore, the predetermined connection relationships, for example, the connection relationships shown in the diagram or text, are not limited to those shown in the diagram or text. Other connection relationships besides those shown are also disclosed in the diagram or text. X and Y are, Let's assume the object is (for example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.). .

[0024] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more (electrodes, display devices, light-emitting devices, loads, etc.) are connected between X and Y. It is possible to do so. Furthermore, the switch has a function that controls on / off. In other words, the switch can be in a conductive state (on state) or a non-conductive state (off state), and current flows. It has a function to control whether or not to release the fluid.

[0025] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc. ), voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0026] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are directly connected) This includes cases where the elements or other circuits are connected without any intervening elements.

[0027] Also, for example, "X and Y and the source (or first terminal, etc.) and drain of the transistor ( (or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor. (or the first terminal, etc.), the transistor drain (or the second terminal, etc.), and Y in that order. It can be expressed as, "It is electrically connected." Or, "The source of the transistor ( The first terminal (or the first terminal, etc.) is electrically connected to X, and the drain (or second terminal) of the transistor is connected to X. The terminals (or other terminals) are electrically connected to Y, and X is the source of the transistor (or the first terminal, etc.). The transistor's drain (or second terminal, etc.), Y, are electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X, via the drain (or second terminal, etc.) and X, The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal) (etc.), Y is provided in this connection order. By using a similar method of expression to specify the order of connections in the circuit configuration, Connect the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor. By distinguishing between them, the technical scope can be determined. Note that these expressions are just examples. However, it is not limited to these methods of expression. Here, X and Y are objects (e.g., devices, elements, (This refers to circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0028] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0029] Furthermore, in this specification, etc., "resistive element" refers, for example, to an element having a resistance value higher than 0Ω. It can be a circuit element, wiring, etc. Therefore, in this specification, etc., "resistive element "A wire has resistance, a transistor has current flowing between its source and drain, and a diode This includes components such as coils. Therefore, the term "resistor" is used to mean "resistor". It can be rephrased as terms such as "load" or "region with resistance," and conversely, "resistance," The terms "load" and "region having resistance" can be replaced with terms such as "resistive element." This can be done. As for the resistance value, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably It can be 5 mΩ or more and 5 Ω or less, more preferably 10 mΩ or more and 1 Ω or less. For example, 1Ω or more, 1 × 10 9 It may also be less than or equal to Ω.

[0030] Furthermore, in this specification, "capacitive element" refers to, for example, a capacitance value higher than 0F. Circuit elements having capacitance values, regions of wiring having capacitance values, parasitic capacitance, gate of a transistor Capacitance can be defined as a capacitance, etc. Therefore, in this specification, etc., "capacitance element" is defined as a pair of This includes not only circuit elements that include electrodes and dielectrics contained between the electrodes, but also wiring and wiring Parasitic capacitance that appears between the source or drain of a transistor and the gate. This includes gate capacitance and other related elements. Terms like "quantity" can be replaced with terms like "capacity," and conversely, "capacity" can be replaced with terms like "capacity." The term "capacitive element" can be replaced with terms such as "parasitic capacitance," "gate capacitance," etc. This is possible. Also, the term "a pair of electrodes" in "capacitance" is equivalent to "a pair of conductors" or "a pair of This can be rephrased as "conductive region," "pair of regions," etc. Furthermore, the capacitance value is... For example, it can be between 0.05 fF and 10 pF. Also, for example, 1 pF The capacitance may be set to 10 μF or less.

[0031] Furthermore, in this specification, a transistor is referred to as gate, source, and drain. It has three terminals. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as source or drain are the input and output terminals of the transistor. The input / output terminals specify the transistor's conductivity type (n-channel type, p-channel type) and the transistor's... Depending on the potential applied to the three terminals of the sta, one becomes the source and the other the drain. Therefore, in this specification, the terms source and drain may be rephrased. It shall be possible to do so. Furthermore, in this specification, when describing the connection relationships of transistors, "either the source or the drain" (or the first electrode or the first terminal), "either the source or the drain The notation "the other side" (or second electrode, or second terminal) is used. Note that the structure of a transistor Depending on the model, in addition to the three terminals mentioned above, there may be a back gate. In this specification, either the gate or the back gate of a transistor is referred to as the first gate. The other side of the transistor's gate or back gate is sometimes referred to as the second gate. Furthermore, within the same transistor, the terms "gate" and "back gate" are interchangeable. It may be possible to replace it. Also, if the transistor has 3 or more gates In this specification, etc., each gate is referred to as the first gate, the second gate, the third gate, etc. It is sometimes referred to as such.

[0032] Furthermore, in this specification, etc., a node has terminals, distributions, etc., depending on the circuit configuration and device structure. These can be rephrased as wire, electrode, conductive layer, conductor, impurity region, etc. Also, terminal, Wiring and other components can be referred to as nodes.

[0033] Furthermore, in this specification and other documents, "voltage" and "potential" may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential. For example, if the reference potential is ground... If we consider it as the ground potential, then "voltage" can be replaced with "potential." Round potential does not necessarily mean 0V. Also, potential is relative. The potential applied to the wiring, the potential applied to the circuit, etc., changes as the reference potential changes. The electric potential, including the potential output from circuits, also changes.

[0034] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction), for example, "electrical conduction of a positively charged body." The statement "conductivity is occurring" means "electrical conduction of a negatively charged body is occurring in the opposite direction." In other words, "electric current" means, unless otherwise specified. Here, it refers to the phenomenon of charge transfer associated with the movement of carriers (electrical conduction). A carrier is a system through which an electric current flows, and includes electrons, holes, anions, cations, complex ions, etc. The carrier differs depending on the environment (for example, semiconductors, metals, electrolytes, vacuum, etc.). Also, wiring In such cases, the "direction of the current" is defined as the direction in which the positive carriers move, and is expressed as a positive current quantity. In other words, the direction in which negative carriers move is opposite to the direction of the current, resulting in a negative current. It is expressed as a quantity. Therefore, in this specification, etc., the positive and negative (or direction of the current) of the current is not specified. Unless otherwise stated, descriptions such as "current flows from element A to element B" should be interpreted as "current flows from element B to element A This can be rephrased as "current flows through it" or similar. Also, "current is input to element A" Descriptions such as "is performed" can be rephrased as "current is output from element A," etc. do.

[0035] Furthermore, in this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to constituent elements. This was added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the components. For example, one of the embodiments described herein The components referred to as "first" in this invention may be used in other embodiments or claims. It may also be the component referred to in "Section 2". For example, in this specification, etc. In one embodiment, the component referred to as "first" may be used in other embodiments, or in other embodiments. It may be possible to omit certain details within the scope of the permitted claim.

[0036] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the same constituent elements. In some cases, the positional relationships of the officers are used for convenience when explaining them by referring to the diagram. Also, The relative positions of the constituent elements change appropriately depending on the direction in which each element is depicted. Therefore, the terminology used is not limited to what is explained in the specification, etc., but can be appropriately rephrased depending on the situation. Yes, it is possible. For example, in the expression "insulator located on the upper surface of the conductor," the orientation of the diagram shown is... By rotating it 180 degrees, it can be rephrased as "an insulator located on the underside of a conductor." It is possible.

[0037] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly connected. It does not limit what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be directly in contact with insulating layer A, and the insulating layer A and electrode B are not in direct contact. This does not exclude those that include other components in between.

[0038] Furthermore, in this specification, terms such as "membrane" and "layer" may be interchanged depending on the context. It is possible to change the term. For example, the term "conductive layer" can be changed to the term "conductive film." It may be possible to change it. Or, for example, change the term "insulating film" to "insulating layer". It may be possible to change the terminology to this. Or, depending on the circumstances, or depending on the situation. Therefore, it is possible to replace terms such as "membrane" and "layer" with other terms without using them. For example, changing the term "conductive layer" or "conductive film" to the term "conductor" It may be possible. Or, for example, the terms "insulating layer" and "insulating film" could be changed to "insulator". It may be possible to change the terminology to this.

[0039] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not functionally limit the elements. For example, "electrode" is used as part of "wiring". This can happen, and vice versa. Furthermore, the terms "electrode" and "wiring" can be multiple. This also includes cases where the "electrodes" and "wiring" are formed as a single unit. Furthermore, for example, The term "terminal" can be used as part of "wiring" or "electrodes," and vice versa. Furthermore, the term "terminal" refers to a combination of multiple "electrodes," "wiring," and "terminals." This includes cases where it is formed. For example, "electrode" is a "wiring" or "terminal". It can be a part of something, and for example, a "terminal" can be a part of a "wire" or an "electrode". This is possible. Also, terms such as "electrode," "wiring," and "terminal" can be used in some cases as "region." These terms may be replaced with other terms such as "[...]."

[0040] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be used in some cases. Therefore, or depending on the situation, they can be interchanged. For example, "wiring" In some cases, it is possible to change the term "signal line" to "signal line". Also, for example In some cases, the term "wiring" can be changed to terms such as "power lines." Conversely, terms such as "signal line" and "power line" are changed to the term "wiring." In some cases, this may be possible. Terms such as "power lines" should be changed to terms such as "signal lines." It is sometimes possible to do so. Conversely, terms like "signal line" can also be used for "power line." In some cases, it may be possible to change the terminology to terms such as the "potential" applied to the wiring. Depending on the situation, the term "signal" may be changed to a different term such as "traffic light." In some cases, this is possible. Conversely, terms like "signal" and "electric potential" are also possible. It may be possible to change the terminology.

[0041] In this specification, semiconductor impurities refer to, for example, components other than the main components that constitute the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. For example, when DOS (Density of States) is formed in a semiconductor... In some cases, this can lead to a decrease in carrier mobility or a decrease in crystallinity. If the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and elements other than the main component. These include transition metals, and in particular, for example, hydrogen (also found in water), lithium, sodium, These include silicon, boron, phosphorus, carbon, and nitrogen. Specifically, semiconductors are made up of silicon layers. In this case, impurities that alter the properties of semiconductors include, for example, Group 1 elements other than oxygen and hydrogen. These include elements from Group 2, Group 13, Group 15, and so on.

[0042] In this specification, a switch refers to a conductive state (on state) or a non-conductive state (off state). This refers to a device that has the function of controlling whether or not to allow current to flow when it enters a certain state. Alternatively, it can refer to a switch. A switch is a device that has the function of selecting and switching the path through which electric current flows. One example is... Electrical switches, mechanical switches, etc. can be used. In other words, switches are Any device capable of controlling the current will suffice; it is not limited to any specific device.

[0043] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is. Furthermore, when using a transistor as a switch, the "conductivity state" of the transistor... This refers to a state where the source and drain electrodes of a transistor can be considered to be electrically short-circuited. It refers to a state. Also, the "non-conductive state" of a transistor is when the source electrode and the drive of the transistor are not connected. This refers to a state in which the input electrode can be considered electrically isolated. Note that a transistor is not simply a transistor. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] One example of a mechanical switch is MEMS (Micro-Electro-Mechanical Systems). There are switches that use (STEM) technology. These switches are capable of being moved mechanically. It has electrodes, and operates by controlling the transition between conductivity and non-conductivity through the movement of these electrodes.

[0045] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" or "approximately parallel" means that two lines are positioned at an angle of -30° or more and 30° or less. It refers to a state in which two lines are aligned at an angle of 80° to 100°. This refers to the state in which something is placed. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "Approximately perpendicular" or "roughly perpendicular" means that two lines are positioned at an angle of 60° to 120°. This refers to a state of being in a certain condition. [Effects of the Invention]

[0046] According to one aspect of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed It can provide a place for, etc. Alternatively, according to one aspect of the present invention, a semiconductor with low power consumption. The present invention can provide devices, etc. Alternatively, one aspect of the present invention can provide novel semiconductor devices, etc. It can be provided. Alternatively, one aspect of the present invention provides an electronic device having the above-mentioned semiconductor device. It is possible.

[0047] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be described by those skilled in the art in the specification or This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention provides at least one of the effects listed above and other effects. It has the effect of... Therefore, one aspect of the present invention may, in some cases, have the effects listed above. They may not always be present. [Brief explanation of the drawing]

[0048] [Figure 1] Figures 1A and 1B illustrate a hierarchical neural network. [Figure 2] Figure 2A is a circuit diagram showing an example of the configuration of a semiconductor device, and Figures 2B and 2C are circuit diagrams showing an example of the configuration of a circuit included in a semiconductor device. [Figure 3] Figures 3A to 3C are circuit diagrams showing examples of semiconductor device configurations and operations. [Figure 4] Figures 4A and 4B are circuit diagrams showing examples of the configuration and operation of a semiconductor device. [Figure 5] Figure 5 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 6] Figures 6A to 6C are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 7] Figures 7A to 7C are circuit diagrams showing example configurations of circuits included in semiconductor devices. [Figure 8] Figure 8 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 9] Figure 9 is a timing chart illustrating an example of semiconductor device operation. [Figure 10] Figure 10 is a circuit diagram showing an example of the circuit configuration of a semiconductor device. [Figure 11] Figures 11A and 11B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 12] Figure 12 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 13] Figures 13A to 13D are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 14] Figures 14A to 14C are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 15] Figure 15 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 16]Figure 16 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 17] Figure 17 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 18] Figures 18A and 18B are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 19] Figures 19A to 19E are circuit diagrams showing examples of circuit configurations of semiconductor devices. [Figure 20] Figures 20A to 20C are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 21] Figures 21A and 21B are circuit diagrams showing examples of circuit configurations in semiconductor devices. [Figure 22] Figures 22A and 22B are circuit diagrams showing examples of circuit configurations in semiconductor devices. [Figure 23] Figures 23A to 23C are timing charts illustrating an example of semiconductor device operation. [Figure 24] Figures 24A to 24C are timing charts illustrating examples of semiconductor device operation. [Figure 25] Figures 25A to 25C are timing charts illustrating an example of semiconductor device operation. [Figure 26] Figures 26A to 26C are timing charts illustrating an example of semiconductor device operation. [Figure 27] Figures 27A and 27B are circuit diagrams showing examples of circuit configurations in semiconductor devices. [Figure 28] Figures 28A and 28B are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 29] Figures 29A to 29C are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 30] Figures 30A to 30C are circuit diagrams showing examples of circuit configurations of semiconductor devices. [Figure 31] Figures 31A to 31C are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 32]Figures 32A and 32B are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 33] Figure 33 is a schematic cross-sectional diagram illustrating an example of a semiconductor device configuration. [Figure 34] Figure 34 is a schematic cross-sectional diagram illustrating an example of the configuration of a semiconductor device. [Figure 35] Figures 35A to 35C are schematic cross-sectional diagrams illustrating an example of the configuration of a semiconductor device. [Figure 36] Figures 36A and 36B are schematic cross-sectional diagrams illustrating examples of transistor configurations. [Figure 37] Figure 37 is a schematic cross-sectional diagram illustrating an example of the configuration of a semiconductor device. [Figure 38] Figures 38A and 38B are schematic cross-sectional diagrams illustrating examples of transistor configurations. [Figure 39] Figure 39 is a schematic cross-sectional diagram illustrating an example of a semiconductor device configuration. [Figure 40] Figure 40A is a top view showing an example of the capacity configuration, while Figures 40B and 40C are cross-sectional perspective views showing an example of the capacity configuration. [Figure 41] Figure 41A is a top view showing an example of the capacity configuration, Figure 41B is a cross-sectional view showing an example of the capacity configuration, and Figure 41C is a cross-sectional perspective view showing an example of the capacity configuration. [Figure 42] Figure 42A illustrates the classification of IGZO crystal structures, Figure 42B illustrates the XRD spectrum of crystalline IGZO, and Figure 42C illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 43] Figure 43A is a perspective view showing an example of a semiconductor wafer, Figure 43B is a perspective view showing an example of a chip, and Figures 43C and 43D are perspective views showing examples of electronic components. [Figure 44] Figure 44 is a perspective view showing an example of an electronic device. [Figure 45] Figures 45A to 45C are perspective views showing an example of an electronic device. [Modes for carrying out the invention]

[0049] In artificial neural networks (hereinafter referred to as neural networks): The synaptic connection strength is determined by providing existing information to the neural network. It can change. In this way, by giving existing information to a neural network, The process of determining the overall strength is sometimes called "learning."

[0050] Furthermore, for a neural network that has undergone "learning" (where connection strengths have been defined), By providing that information, new information can be output based on the bond strength. Thus, in a neural network, based on the given information and connection strength... The process of outputting new information is sometimes called "inference" or "cognition."

[0051] Examples of neural network models include the Hopfield type and the hierarchical type. One example is a multi-layered neural network called a "deep neural network." It is called a "deep neural network" (DNN), and machine learning using deep neural networks is called It is sometimes referred to as "deep learning."

[0052] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called OS) They are classified into the following categories. For example, when a metal oxide is used in the active layer of a transistor, the metal acid These oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplification and rectification effects. and constitute a channel formation region of a transistor having at least one switching action. If possible, the metal oxide is used as a metal oxide semiconductor. It can be called an OS conductor, or simply OS. It can also be called an OS FET, or OS When referring to a transistor, it means a transistor having a metal oxide or oxide semiconductor. It can be rephrased as "sta".

[0053] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0054] Furthermore, in this specification, the configurations shown in each embodiment are different from the configurations shown in other embodiments. By combining them as appropriate, one embodiment of the present invention can be formed. If multiple configuration examples are provided, it is possible to combine them as appropriate.

[0055] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other details (even partial details) described in the form, and one or more other embodiments The content to be stated (even if only a part of it) should be applied to or combined with at least one other content. It is possible to replace or otherwise perform actions such as [doing something else].

[0056] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0057] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. In that embodiment, another figure (even if only a part of it) and one or more other figures For at least one of the diagrams (even if only a part of it) described in the form of the installation, the combination By doing so, even more diagrams can be constructed.

[0058] Embodiments described herein will be explained with reference to the drawings. However, implementation may be difficult. The form can be implemented in many different ways, and it does not deviate from the purpose and scope. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the form of application, the same reference numeral is used for identical parts or parts having similar functions. In some cases, explanations of repetitions used across different drawings may be omitted. Also, perspective drawings. In some cases, the description of certain components may be omitted in order to ensure clarity in the drawings. be.

[0059] In this specification, when the same reference numeral is used for multiple elements, it is particularly important to distinguish between them. When necessary, add identifying codes such as "_1", "[n]", or "[m,n]" to the code. It may be noted or written down.

[0060] Furthermore, in the drawings of this specification, the size, thickness of the layers, or the area may be exaggerated for clarity. In some cases, this may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawings are for reference only. This is a schematic representation of a hypothetical example and is not limited to the shapes or values ​​shown in the drawing. This can be due to variations in signals, voltages, or currents caused by noise, or to timing discrepancies. This can include variations in signals, voltages, or currents.

[0061] Also, regarding this specification and the like, "In:Ga:Zn = 4:2:3 or in the vicinity thereof" means that when In is 4 with respect to the total number of atoms, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 5:1:6 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also ,"In:Ga:Zn = 1:1:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, "In:Ga:Zn = 5:1:3 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is 0.5 or more and 1.5 or less( 0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 10:1:3 or in the vicinity thereof" means that when In is 10 with respect to the total number of atoms, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Zn = 2:1 or in the near vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.25 and less than 0.75 (0.25 < Zn ≤ 0.75). Also, "In:Zn = 5:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.12 and less than 0.25 (0 .12 < Zn ≤ 0.25). Also, "In:Zn = 10:1 or in the vicinity thereof" means that with respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and less than 0.12 (0.0 7 < Zn ≤ 0.12).

[0062] ​​​ (Embodiment 1) In this embodiment, an arithmetic circuit that performs neural network operations, which is a semiconductor device according to one aspect of the present invention, will be described. Perform the calculation.

[0063] <Hierarchical Neural Network> First, a hierarchical neural network will be described. As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in FIG. 1A shows an example thereof, and the neural network 100 has the first layer to the Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In FIG. 1A, the (k - 1)th layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted. layer and an output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in FIG. 1A shows an example thereof, and the neural network 100 has the first layer to the Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In FIG. 1A, the (k - 1)th layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted. layer and an output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in FIG. 1A shows an example thereof, and the neural network 100 has the first layer to the Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In FIG. 1A, the (k - 1)th layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted. layer to the Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In FIG. 1A, the (k - 1)th layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted. layer to the Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In FIG. 1A, the (k - 1)th layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted. layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted.

[0064] Each layer of the neural network 100 has one or more neurons. In FIG. 1A, the first layer has neurons N1 to neuron N (1) to neuron N p (1) (where p is an integer of 1 or more ). The (k - 1)th layer has neurons N1 (k-1) to neuron N m (k-1) (where m is an integer of 1 or more). The kth layer has neurons N1 ( k) to neuron N n (k) (where n is an integer of 1 or more). The Rth layer has Neuron N1 (R) Neuron N q (R) (Here, q is an integer greater than or equal to 1.) It has.

[0065] Note that Figure 1A shows neuron N1 (1) , Neuron N p (1) , neuron N1 ( k-1) , Neuron N m (k-1) , neuron N1 (k) , Neuron N n (k) , Neuron N1 (R) , Neuron N q (R) In addition, the (k-1) layer neurons N i (k-1) (Here, i is an integer between 1 and m, inclusive.) Neuron N of layer k j ( k) (Here, j is an integer between 1 and n, inclusive.) is also illustrated, as are other neurons The diagram for "n" has been omitted.

[0066] Next, the transmission of signals from neurons in the previous layer to neurons in the next layer, and each of the neurons This section describes the signals that are input and output in the ron. Note that in this explanation, the k-th layer of the neurons... N j (k) Let's focus on that.

[0067] Figure 1B shows the neurons N in layer k. j (k) And, neuron N j (k) The information entered No. and neuron N j (k) This shows the signal output from and .

[0068] Specifically, the (k-1) neuron N1 (k-1) Neuron N m (k-1 ) z1 is the output signal of each of the following: (k-1) ~z m (k-1) However, neuron N j ( k) It is outputting towards neuron N. j (k) is z1 (k-1) ~z m (k-1) z j (k) Generate z j (k) The (k+1)th is used as the output signal. Output is sent to each neuron in the layer (not shown in the diagram).

[0069] The signals that are input from neurons in the previous layer to neurons in the next layer are transmitted between those neurons. The strength of the synaptic connections (hereinafter referred to as the weighting coefficient) determines the transmission of signals. The degree is determined. In neural network 100, the output from the neurons of the previous layer The signal is multiplied by the corresponding weight coefficient and input to the neuron in the next layer. i is greater than or equal to m Let the following integers represent the (k-1)th neuron N i (k-1) and the k-th layer of neurons N j (k) The weight coefficient of the synapse between w i (k-1) j (k) When this is the case, the kth layer URON N j (k) The signal input to the device can be expressed by equation (1.1).

[0070]

number

[0071] That is, when signals are transmitted from each of neurons N1 (k-1) to N m (k-1) of the (k - 1)-th layer to neuron N of the k-th layer, for the signals z1 j (k) to z (k-1) m (k-1) respectively, corresponding weight coefficients (w1 (k-1 ) j (k) m to w (k-1) j (k) j ) are multiplied. Then, for neuron N (k) (k-1) of the k-th layer, w1 j (k) (k-1) ·z1 m to w (k-1) j (k) m · z (k-1) j are input. At this time, the sum u (k) j of the signals input to neuron N of the k-th layer is given by Equation (1.2). (k) (k-1)

[0072]

Equation

[0073] Also, the weight coefficients w1 (k-1) j (k) to w m (k-1) j (k) and the signal z1 (k-1) ~z m (k-1) The result of the sum of products of and is biased. It is also possible to do so. When the bias is b, equation (1.2) can be rewritten as follows: .

[0074]

number

[0075] Neuron N j (k) , u j (k) Depending on the output signal z j (k) Generates here. So. Neuron N j (k) Output signal z from j (k) We define it by the following formula.

[0076]

number

[0077] function f(u j (k) ) is an activation function in hierarchical neural networks. Step functions, linear ramp functions, sigmoid functions, etc. can be used. The tempering function may be the same for all neurons, or it may be different for all neurons. Therefore, the activation function of neurons may be the same or different in each layer.

[0078] By the way, the signal output by the neurons in each layer, the weight coefficient w, or the bias b is, It can be an analog value or a digital value. For example, a binary value. You can use that, or you can use a 3-value. You can even use a value with a larger number of bits. For example, For analog values, activation functions can include, for example, a linear ramp function or a sigmoid function. You can use it. In the case of a binary digital value, for example, the output can be -1 or 1, or 0 or A step function where < is 1 can be used. Also, the signals output by neurons in each layer are It is also acceptable to have three or more values. For example, an activation function that outputs three values ​​would have outputs of -1, 0, Alternatively, use a step function that sets the value to 1, or a step function that sets the value to 0, 1, or 2. It's fine if it's there. Also, for example, as an activation function that outputs 5 values, -2, -1, 0, 1, Alternatively, a step function of 2 may be used. The signals output by neurons in each layer, For the coefficient w or bias b, use a digital value for at least one of them. This allows for a reduction in circuit size, a decrease in power consumption, or an increase in processing speed. It is possible to speed up the process, etc. Also, the signals output by neurons in each layer, the weight coefficient w Alternatively, by using an analog value for at least one of the bias b values, This allows for improved calculation accuracy.

[0079] The neural network 100 is formed when an input signal is input to the first layer (input layer) So, in each layer from the first layer (input layer) to the last layer (output layer), the input is processed sequentially from the previous layer. Based on the applied signal, equations (1.1), (1.2) (or (1.3)), and (1.4) The system generates an output signal using this method and outputs that output signal to the next layer. The last layer (output The signal output from the power layer is calculated by the neural network 100. It corresponds to.

[0080] <Example of arithmetic circuit configuration 1> Here, in the neural network 100 described above, equation (1.2) (or equation (1 An example of an arithmetic circuit capable of performing the operations in equation (3)) and equation (1.4) will be described. In addition, in the said calculation circuit, as an example, the synaptic cycle of the neural network 100 The weight coefficient of the path can be a digital value with two or more values, or an analog value, and also, The activation function of the RON can be a step function or the like. Also, in this specification, etc. , weight coefficients and the values ​​of the signals input from the neurons in the previous layer to the neurons in the next layer (calculated values ​​and (They may be referred to as such) Of these, one will be called the first data and the other the second data. It is sometimes referred to as data. Furthermore, the weight of the synaptic circuits in neural network 100 The coefficients and calculated values ​​are not limited to digital values, and at least one of them may be an analog value. It is also possible to use it.

[0081] The calculation circuit 110 shown in Figure 2A includes, as an example, an array unit ALP and a circuit AFP. This is a semiconductor device. The arithmetic circuit 110 is, for example, the k-th layer in Figures 1A and 1B. Neuron N j (k) The signal input to the neuron N is processed by the neuron N j (k) Output from The signal z j (k) This is a circuit that generates [something]. However, one aspect of the present invention is not limited to this. No. The arithmetic circuit 110 can function, for example, as a memory device or memory circuit. Good. For example, the arithmetic circuit 110 may use DRAM, SRAM, or flash memory as one example. It may function as a memory. Alternatively, the arithmetic circuit 110 may, for example, function within a memory circuit. It can also function as a circuit that performs calculations, that is, as an in-memory computing circuit. .

[0082] The array section ALP has, for example, circuits MP[1,j] to MP[m,j]. Furthermore, circuit AFP has, for example, circuit ACTF[j], and further, circuit ACTF[ j] has a capacitance CRE, a circuit AC, terminal T1, and terminal T2.

[0083] Although the capacitance CRE may be realized using a conventional capacitive element, one aspect of the present invention is as follows: This is not limited to this. For example, the capacity CRE can be seen in Figure 2B or Figure 2C, for example. As shown, this may be implemented using the gate capacitance of a transistor. In this case, the transistor The st may use an N-channel type, a P-channel type, or both. They may be connected in parallel. Note that in Figures 2B and 2C, instead of the capacitance CRE, a transistor is used. It uses a CR5 CRET. An example of a transistor CRET is an OS transistor. A transistor can be applied. The OS transistor will be described in detail in Embodiment 5. In addition, other than OS transistors, for example, have silicon in the channel formation region. It can be a transistor (hereinafter referred to as a Si transistor), etc. Examples of silicon include single-crystal silicon, hydrogenated amorphous silicon, and microcrystalline silicon. Crystalline silicon or polycrystalline silicon can be used. Also, OS transistors, Examples of transistors other than Si transistors include transistors with Ge as the active layer. Activating compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe Layered transistors, transistors with carbon nanotubes as the active layer, organic semiconductors A transistor or the like with the active layer can be used.

[0084] Each of circuits MP[1,j] through MP[m,j] is connected to wiring OL[j] and wiring O LB[j] is electrically connected to and . Also, circuit MP[1,j] to circuit MP[m Each of the ,j] is electrically connected to wiring XLS[1] through wiring XLS[m]. Furthermore, wiring OL[j] is electrically connected to terminal T1, and terminal T1 is the first of the capacitance CRE Electrically connected to terminal 1, wiring OLB[j] is electrically connected to terminal T2, terminal T 2 is electrically connected to the second terminal of the capacitance CRE. Note that, for example, terminal T1 and the capacitance Between the first terminal of the quantity CRE and some element or circuit (for example, a switch, a transistor) A terminal (such as a st) may be connected. Similarly, for example, terminal T2 and the second terminal of capacitor CRE. Some kind of element or circuit (for example, a switch, transistor, etc.) is connected between the child and the other. It's fine if it is done.

[0085] Each of the wirings XLS[1] through XLS[m] is, for example, a neuron N1 (k-1) Neuron N m (k-1) The signal z1 is output from there. (k-1) ~z m ( k-1) It has the function of transmitting an electrical potential corresponding to the current state.

[0086] Circuit MP[1,j] is, for example, neuron N1 (k-1) and neuron N j (k ) Weight coefficient w1 between (k-1) j (k) A device that holds (referred to as the first data here) It has the ability, and similarly, the circuit MP[m,j] is, for example, neuron N m (k-1) and ni URON N j (k) Weight coefficient w between these two points m (k-1) j (k) It has the function of holding [something].

[0087] Furthermore, circuit MP[1,j] is, for example, neuron N1 (k-1) Output from signal z1 (k-1) (Here we will refer to this as the second data set) and the first data set w1 (k-1) j (k) It has the function of outputting the product of the following. Similarly, circuit MP[m,j] is, for example, a neuron N m (k-1) The signal z output from m (k-1) (Here we will refer to this as the second data) and the 1 data w m (k-1) j (k) It has the function of outputting the product of [the specified product].

[0088] As a specific example, the second data z is connected to circuit MP[1,j] via wiring XLS[1]. 1 (k-1) When a potential corresponding to is input, the circuit MP[1,j] receives the first data w1 (k-1) j (k) and second data z1 (k-1) Information corresponding to the product of (for example, electric current, electric current) The voltage (or similar) is output to wiring OL[j] and / or wiring OLB[j]. Similarly, a second data z is connected to circuit MP[m,j] via wiring XLS[m]. m (k-1)When a potential corresponding to is input, the circuit MP[m,j] is, first data w m (k-1) j (k) and the second data z m (k-1) Information corresponding to the product of (for example, electric current, electric current) The voltage (or similar) is output to wiring OL[j] and / or wiring OLB[j].

[0089] Therefore, for example, in wiring OL, circuits MP[1,j] to circuits MP[m,j] The information output from each (e.g., current, voltage, etc.) is added together. For example, in a wiring OLB, each of the circuits MP[1,j] to MP[m,j] The information output from there (for example, current, voltage, etc.) is then added together. Each of the line OL and wiring OLB has the first data w1 (k-1) j (k) Or maybe lol m (k -1) j (k) and second data z1 (k-1) ~z m (k-1) Information corresponding to the sum of products (example) For example, current, voltage, etc., flows. However, one aspect of the present invention is not limited thereto. For example, in at least one of the wiring OL or wiring OLB, some standard (e.g., Information such as current and voltage (e.g., reference, precharge, bias, etc.) is transmitted. It's okay.

[0090] The specific circuit configurations of circuits MP[1,j] through MP[m,j] will be discussed later. To state.

[0091] Circuit ACTF[j] is, for example, derived from wiring OL[j] and wiring OLB[j]. Information (e.g., current, voltage, etc.) is obtained based on the sum of products of the first and second data, and then New Ron N j (k) The signal z output from j (k) It functions as a circuit that generates [something]. Specifically The circuit AC included in circuit ACTF[j] determines binary and multi-valued information from that information. Which digital or analog value represents the output signal z j (k) (When it comes to calculated values) A certain is generated. In other words, circuit AC can be treated as an activation function circuit, for example. .

[0092] As an example of an AC circuit, consider an analog-to-digital conversion circuit (sometimes called a sense amplifier). In some cases, it can be done as follows. Specifically, circuit AC can be, for example, a sum of products When the result is less than or equal to "0", the output signal z j (k) A digital signal with the value "0" When the output signal z is positive, the output signal z j (k) As a "positive" digital It can be used as an analog-to-digital conversion circuit that outputs a value.

[0093] Furthermore, in this specification, etc., each of circuits MP[1,j] to MP[m,j] is If no distinction is made, it shall be written as circuit MP. Similarly, wiring XLS[1] to wiring If the XLS[m] dimensions are not distinguished, they shall be written as wiring XLS. The [j] in wiring OL[j] and wiring OLB[j] is omitted, and wiring OL and wiring It is sometimes written as OLB. Similarly, the [j] in the circuit ACTF[j] is sometimes omitted. The circuit is sometimes referred to as ACTF.

[0094] <Example of operation of the arithmetic circuit 1> Next, we will explain an example of the operation of the ACTF[j] circuit in Figure 2A. Each of these is a circuit diagram showing the sequence of operations for the ACTF[j] circuit.

[0095] In Figure 3A, the voltage between the first and second terminals of the capacitor CRE in circuit ACTF[j] is set to 0V. This shows an example of the initialization operation. Specifically, in the circuit of Figure 3A, the wiring OL[j] and Each of the OLB[j] wirings has an initialization potential, for example, V ini was given It is assumed that it is. ini One example is when current flows from wiring OL to circuit MP. In this case, it becomes VDD, and if current flows from circuit MP to wiring OL, it becomes VSS. This becomes GND.

[0096] In Figure 3B, the first data is generated by each of the circuits MP[1,j] through MP[m,j]. ta w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and second data z1 (k-1) No Toz m (k-1) Information corresponding to the sum of products (e.g., current, voltage, charge, etc.) is stored in the wiring OL[ The output is sent to [j] and wiring OLB[j], and the circuit ACTF[j] acquires this information. An example is shown. In this case, the potential V of the first terminal of the capacitance CRE is shown. ini This is the wiring from circuit MP. The potential V is based on the information input to the circuit ACTF[j] via OL[j]. OL It changed to Also, the potential V of the second terminal of the capacitance CRE ini This is from circuit MP via wiring OLB[j] Based on the information input to the ACTF[j] circuit, the potential V OLB It shall change to this. At this time, the voltage between the first and second terminals of the capacitor CRE is |V RD |(=|V OLB -V OL Let's assume this |V RD | is one example of the information flowing through wiring OL[j] This corresponds to the difference between the total amount and the total amount of information flowing through the wiring OLB[j]. As an example, If line OL[j] is the sum of positive values ​​and wiring OLB[j] is the sum of negative values, then , |V RD | represents the difference between the sum of positive values ​​and the sum of negative values. Therefore, |V RD | corresponds to the result of a sum-of-products operation. That is, circuit MP[1,j] to circuit MP[m,j] The first data w1 was collected using (k-1) j (k) Or maybe lol m (k-1) j (k) and second data z1 (k-1) ~z m (k-1) The sum of products of the product results in voltage |V RD |As capacity CRE It can be held between the first and second terminals.

[0097] In Figure 3C, as an example, the voltage (charge) stored in the capacitor CRE is input to the circuit AC. Then, the amount of voltage (charge) stored in the capacitance CRE is sensed. In this case, the potential V OL , and, potential V OLB Its potential changes significantly depending on the sum-of-products result. If this is input directly into the AC circuit, the circuit configuration of the AC circuit may become complex, or the circuit This can lead to disadvantages, such as a reduced operating range for AC power. As an example, electric potential V OL , and, potential V OLB Even if their sizes are different, is |V RD |(=|V OLB -V OL If the voltages are the same, then the AC circuit is It is desirable that the same voltage is input to the system. For example, potential V O L =1, potential V OLB Even when =2, the potential V OL =3, potential V OLB In the case of =4, either Ramo | V RD |=1, and |V RD | will be the same size. Therefore, it is desirable that the same voltage is input to the AC circuit. For example, at least one of the first and second terminals of the capacitance CRE is in an electrically floating state. Then, either the first terminal of the capacitance CRE or the second terminal of the capacitance CRE is used. A reference potential (here, as an example, the GND potential (0V). However, in one aspect of the present invention, However, it is not limited to this; the VDD potential, precharge potential, (VDD / 2) potential, etc., may also be used. (i)) is given. Then, either the first terminal of the capacitance CRE or the second terminal of the capacitance CRE The potential of the other is |V RD It can be expressed as |. In other words, potential V OL , and, electric potential V OLB Even if the sizes are different, |V RD If the | is the same, the same potential is applied to the AC circuit. It can be input. And the AC circuit, for example, senses the potential of the second terminal of the capacitor CRE. Single, voltage V RD The corresponding signal z j (k) It outputs the following: In other words, the operation shown in Figure 3C. As usual, the first data output by circuit MP[1,j] to circuit MP[m,j] The signal z is the result of the sum of products of the second data. j (k) The following will be output.

[0098] Here, we will explain a specific example of the above operation.

[0099] Data 1 w1 (k-1) j (k) Or maybe lol m (k-1) j (k) Each of these will provide an explanation. To simplify things, for example, take one of the values ​​"+1", "0", or "-1", and the second day Ta z1 (k-1) ~z m (k-1) Each of these is, for example, "+1", "0", "-1" It shall take one of the following values:

[0100] Furthermore, in the operation example in Figure 3A, the potential V applied to wiring OL and wiring OLB is also shown. ini It is assumed that it is pre-charged as a high-level potential.

[0101] Furthermore, in circuit MP, when the product of the first data and the second data is "+1", circuit M The connection between P and wiring OL becomes conductive, while the connection between circuit MP and wiring OLB becomes non-conductive. It is assumed that a current corresponding to "|+1|" flows from wiring OL to circuit MP. In addition, in circuit MP, when the product of the first data and the second data is "-1", The connection between path MP and wiring OL becomes non-conductive, while the connection between circuit MP and wiring OLB becomes conductive. Let it be so. And, a current corresponding to "|-1|" is sent from the wiring OLB to circuit MP (that is Assume that a current of the same magnitude as the current corresponding to "|+1|" flows through the circuit MP. In this case, when the product of the first data and the second data is "0", between circuit MP and wiring OL , and the circuit MP and the wiring OLB shall be in a non-conductive state. In other words, the wiring OL In the first case, a current equal to the sum of positive currents flows, while in the OLB wiring, a current equal to the absolute value of the sum of negative currents flows. It plays.

[0102] In this case, in the example of operation shown in Figure 3B, the potential V OL The size is the first data and the second data. It is determined by the number of circuit MPs whose product is "+1". Specifically, the first data and The more circuits MP have a product of "+1" in the second data set, the more circuits M can be connected from wiring OL. The total amount of current flowing through P[1,j] or circuit MP[m,j] increases. Also, wiring O L has a high-level potential, which is potential V. ini Because it is pre-charged, the circuit MP[1 The larger the total current flowing through the circuit MP[m,j], the greater the potential V of the wiring OL. i ni The voltage drop from there becomes larger. In other words, the product of the first data and the second data becomes "+1". The more circuit MPs there are, the higher the potential V OL It will decrease.

[0103] Similarly, potential V OLB The size is determined by the product of the first data and the second data being "-1". It is determined by the number of MP circuits. Specifically, the product of the first data and the second data is "-1". The more circuits MPs there are, the more circuits MP[1,j] or circuits M can be connected from the wiring OLB. The total current flowing through P[m,j] becomes larger. Also, the OLB wiring has a high-level potential. The potential V iniBecause it is pre-charged, circuit MP[1,j] or circuit MP[ The larger the total current flowing through [m,j], the higher the potential V of the wiring OLB. ini Voltage drop from The product of the first and second data is "-1" in the circuit MP. The more there are, the higher the potential V. OLB It will decrease.

[0104] From the above, the number of circuits MP where the product of the first data and the second data is "+1" is When the product of data 1 and data 2 is greater than the number of circuits MP where the product is "-1", Potential V of the first terminal of quantity CRE OL This is the potential V at the second terminal of the capacitance CRE. OLB Lower than In other words, the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and Day 2 Ta z1 (k-1) ~z m (k-1) When the sum of the products of is positive, the electric potential V OL The potential is V OLB It will be lower than that. Also, the circuit where the product of the first data and the second data is "-1" The number of MPs is less than the number of circuit MPs where the product of the first data and the second data is "+1". When it is also large, the potential V of the first terminal of capacitance CRE OL This is the potential V at the second terminal of the capacitance CRE. O LB It will be higher than the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and second data z1 (k-1) ~z m(k-1) When the sum of the products of is negative, Place V OL The potential is V OLB It will be higher than that.

[0105] Furthermore, the number of circuits MP where the product of the first data and the second data is "+1" is... When the number of circuits MP where the product of the first data and the second data is "-1" is equal, or In all MP[1,j] and circuits MP[m,j], the product of the first data and the second data is When it is "0", the potential V of the first terminal of the capacitance CRE. OL This is the second terminal of the capacitance CRE. Potential V OLB This is equivalent to the first data w1 (k-1) j (k) Or maybe lol m (k -1) j (k) and second data z1 (k-1) ~z m (k-1) The sum of products of becomes "0". At that time, the potential V OL and potential V OLB This means they will have the same potential. Furthermore, in all cases, the first When the product of the first data point and the second data point is "0", the potential V OL and potential V OLB That is, Place V ini It will remain as is.

[0106] Note: Data 1 w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and the second data z 1 (k-1) ~z m (k-1) The larger the absolute value of the sum of products, the greater the potential V. OL and potential V O LB The potential difference (the absolute value of the voltage between the first and second terminals of the first capacitor) increases.

[0107] Furthermore, in the above example of operation, the first data w1 (k-1) j (k) Or maybe lol m (k-1) j ( k) Each of these can take one of the following values, for example: "+1", "0", or "-1". As explained above, the operation of a semiconductor device according to one aspect of the present invention is not limited thereto. For example, Data 1 w1 (k-1) j (k) Or maybe lol m (k-1) j (k) The possible values ​​are “+2 It is also possible to have more than three values, such as ", "+1", "0", "-1", "-2", etc. It may also be represented as a binary value such as "+1", "-1", etc. Also, circuit MP[1,j] or circuit The amount of current flowing between MP[m,j] and wiring OL and / or wiring OLB is given by circuit MP[1 The first data w1 held in each of the circuits MP[m,j] or [m,j] (k-1) j (k) Or maybe lol m (k-1) j (k) It is determined by the result of the product of the possible values ​​of and the second data. That's all you need to do. Specifically, for example, the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) Each of them is one of the following: "+2", "+1", "0", "-1", "-2" For the second data z1(k-1) ~z m (k-1) Each of them is "+1", "0", Let's consider the case where it takes any value of "-1". Here, in circuit MP, the first data and When the product of the second data is "+1", the circuit MP and the wiring OL become conductive, and Assuming that the circuit MP and wiring OLB are in a non-conductive state, current flows from wiring OL to circuit MP. Quantity I ut Assume that a current of is flowing. Also, in circuit MP, the first data and the second data When the product of the two is "+2", the circuit MP and the wiring OL become conductive, and the circuit MP and wiring Assuming that the connection between wire OLB and the circuit is non-conductive, the current flowing from wiring OL to circuit MP is 2 × I u t It should be assumed that a current of is flowing. Also, the product of the first data and the second data is "-1". When this happens, the circuit MP and wiring OL become non-conductive, and the circuit MP and wiring OLB become non-conductive. Assuming a conductive state, a current I flows from the wiring OLB to the circuit MP. ut A device through which an electric current flows. This is sufficient, and when the product of the first data and the second data is "-2", the circuit MP and the distribution The connection between line OL becomes non-conductive, while the connection between circuit MP and wiring OLB becomes conductive. Then, the current 2 × I is drawn from the OLB wiring to the MP circuit. ut Let's assume that a current flows through it. Furthermore, when the product of the first data and the second data is "0", the circuit MP and the wiring OL are non-conductive. The circuit should be in a conductive state, and the connection between circuit MP and wiring OLB should be non-conductive.

[0108] Based on the above, by performing the operation example shown in Figure 3B, the power between the first terminal and the second terminal of the first capacitor can be measured. Pressure, 1st data w1 (k-1) j (k) Or maybe lolm (k-1) j (k) and second data z1 (k-1) ~z m (k-1) The potential V corresponds to the sum of products of OL and potential V OLB Potential difference (Voltage|V) RD It can be expressed as |).

[0109] Subsequently, as shown in the example operation in Figure 3C, for example, the second terminal of the capacitance CRE is electrically connected. After setting it to a floating state (the first terminal of the capacitance CRE may also be set to an electrically floating state), then, By setting the potential of the first terminal of the capacitor CRE to the GND potential, the potential of the second terminal of the capacitor CRE is V RD Make it so. 1st data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and the second ta z1 (k-1) ~z m (k-1) If the sum of products with is "positive", then the second of the capacity CRE Terminal potential V RD This results in a positive potential, and the first data w1 (k-1) j (k) Or maybe lol m (k- 1) j (k) and second data z1 (k-1) ~z m (k-1) The sum of products of is "negative" In total, the potential V of the second terminal of capacitance CRE. RD This results in a negative potential. Also, the first data w1 (k- 1) j (k) Or maybe lol m (k-1) j(k) and second data z1 (k-1) ~z m (k-1 ) If the sum of the products of is "0", the differential voltage between the first and second terminals of the capacitor CRE is approximately 0. Therefore, the potential V of the second terminal of the capacitance CRE RD This becomes the GND potential.

[0110] Then, by sensing the potential of the second terminal of the capacitor CRE using the AC circuit... And, voltage V RD Output signal z corresponding to j (k) It can output the following: Capacitance CR. The potential V of the first terminal of E OL And the potential V of the second terminal of the capacitance CRE OLB and are in a large field Even if combined, or the potential V of the first terminal of capacitance CRE OL And the potential V of the second terminal of the capacitance CRE O LB Even when both are small, the potential V OL and potential V OLB The difference voltage between each field If they are equal, the difference voltage is detected by capacitance CRE, and the voltages of the same magnitude are used. The same result is input to the AC circuit and output as the z signal. j (k) It can be output as that. As a result, the potential V OL and potential V OLB Obtain a more accurate sum-of-products result, independent of the size. It is possible.

[0111] In particular, in the case of hierarchical neural networks, the circuit AC is an activation function circuit and This is how you do it, and depending on the type of activation function, for example, the result of the sum of products of the first and second data. When z is less than or equal to "0", the output signal z j (k)Outputs a digital signal with the value "0". And, when the sum of the products of the first data and the second data is "positive", the output signal z j (k) and The circuit should be capable of outputting multiple "positive" values. Such a circuit would be: For example, an analog-to-digital conversion circuit (sense amplifier, etc.) capable of sensing only positive voltages. It is preferable to use an inflator or similar device.

[0112] In the above example, an example of use in a neural network was shown, but this is one aspect of the present invention. This is not limited to this. For example, the wiring OL receives signals from the memory cell to be read. It outputs a signal from the reference memory cell to the wiring OLB. It can also be used as a function to read information held in the memory cell being read. In other words, it can be used as DRAM, SRAM, or flash memory. For example Alternatively, it may be operated as a read operation for multi-value data. Or, as an example, memory cycle It can also be used as a circuit that performs calculations within the circuit, that is, as an in-memory computing circuit. good.

[0113] By the way, when the sum of the products of the first and second data is negative, the output signal z j (k) If you want to output multiple "negative" values, for example, in a circuit AC, you would add a positive voltage... Well, you can use an analog-to-digital conversion circuit that can also sense negative voltages. In Figure 3C, instead of setting the potential of the first terminal of the capacitance CRE to GND potential, the capacitance The potential of the first terminal of CRE may be set to (VDD / 2). In this way, the first data If the sum of products of the second data is "zero", then the circuit AC has (VDD / 2) power. It is entered in place. And, not only when the sum of the products of the first and second data is "positive", Even if it is negative, if its absolute value is small, the AC circuit will receive a positive potential input. As a result, only positive voltages can be sensed in the analog-to-digital conversion circuit. It becomes possible to use circuits (sense amplifiers, comparators, etc.). Digital conversion circuits (sense amplifiers, comparators, etc.) are designed for situations where the input voltage is only positive. In some cases, the circuit can be simplified. In other words, a negative power supply voltage is no longer required, This also allows for simplification of the power source circuit. Furthermore, it allows for a wider input voltage range, thus reducing noise. This allows for a larger margin for error, enabling more accurate processing.

[0114] Also, in a different case from the above, where the sum of the products of the first and second data is "negative", Output signal z j (k) One way to output multiple "negative" values ​​is, for example, the operation shown in Figure 2A. Circuit 110 can be changed to the calculation circuit 120 shown in Figure 4A. In other words, the individual capacitances CRE By increasing the number, even if the result of the sum-of-products operation is "negative", only positive voltages can be sensed. Use any available analog-to-digital conversion circuits (sense amplifiers, comparators, etc.). This becomes possible. For example, the calculation circuit 120 uses capacitance CREP and capacitance CREM, and It has a circuit ACP and a circuit ACM. The first terminal of capacitance CREP is electrically connected to terminal T1. The second terminal of capacitance CREP is electrically connected to terminal T2. The first terminal is electrically connected to terminal T1, and the second terminal of the capacitor CREM is electrically connected to terminal T2. They are connected. For example, terminal T1 and the first terminal of capacitance CREP (capacitance CREM) Between them, some kind of element or circuit (for example, a switch, transistor, etc.) is connected. It may also be the case that terminal T2 and the second terminal of capacitance CREP (capacitance CREM) Between the child and the other, some kind of element or circuit (for example, a switch, a transistor, etc.) is connected. It may be used. Also, circuits ACP and ACM were used in the calculation circuit 110 in Figure 2A. Similar to AC circuits, for example, it is possible to sense positive voltages and perform analog-to-digital conversion. This refers to the circuit (sense amplifier, comparator, etc.). Note that this is the same as the ACP circuit and ACM circuit. It is assumed that these are initialized before sensing, and the circuit ACP is the second of the capacitance CREP. The circuit ACM senses the potential of the terminals, and senses the potential of the first terminal of the capacitor CREM. In other words, the sensing terminal will be changed depending on whether the capacitance is CREP or CREM. ru.

[0115] The calculation circuit 120 in Figure 4A, similar to the operation examples in Figures 3A and 3B, calculates the potential of the wiring OL to V OL Let the potential of the wiring OL be V OLB As such, the power between the first and second terminals of the capacitance CREP The voltage and capacitance of CREP are defined as the voltage between the first and second terminals |V RE It can be done as follows: |

[0116] Here, as shown in the operation example in Figure 4B, the second terminal of capacitance CREP and the first terminal of capacitance CREM Each of these is made electrically detached (the first terminal of capacitance CREP and capacitance CREM) The second terminal may also be in an electrically floating state), and then the first terminal of the capacitance CREP and the The potential of the second terminal of the capacitance CREM and the other terminal are set to the GND potential. This makes the capacitance CR The potential of the second terminal of EP is V RD As a result, the potential of the first terminal of the capacitor CREM is -V RD This will be Data 1 w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and second data z1 (k -1) ~z m (k-1) When the sum of products of is positive, V RD A potential higher than 0 Therefore, the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and the second data z 1 (k-1) ~z m (k-1) When the sum of products of is negative, V RD is lower than 0 The potential becomes high. In other words, the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and second data z1 (k-1) ~z m (k-1) When the sum of products of is positive, The path ACM is at the potential -V of the first terminal of the capacitance CREM. RD Since it is negative, the power from the ACM circuit If no output is produced (or zero is output), the circuit ACP will output the second terminal of capacitance CREP. Child's potential V RD Since it is positive, sensing is performed and the potential V from the circuit ACP is taken. RD in response It outputs the potential. Also, the first data w1 (k-1) j (k) Or maybe lol m(k-1) j (k ) and second data z1 (k-1) ~z m (k-1) When the sum of the products of is negative, Circuit ACP is the potential V at the second terminal of capacitance CREP. RD Since it is negative, the power from the circuit ACP If no output is produced (or zero is output), the circuit ACM will output the first terminal of the capacitor CREM. Child's potential -V RD Since it is positive, sensing is performed and the potential V is taken from the circuit ACM. RD in response Outputs the potential. Note that the first data w1 (k-1) j (k) Or maybe lol m (k-1) j ( k) and second data z1 (k-1) ~z m (k-1) When the sum of products of is "0" Since the potential of the first terminal of the capacitor CREP is at GND potential, the circuit ACP is No potential output is produced (or zero is output), and the circuit ACM, capacitance CRE Since the potential of the second terminal of M is at the GND potential, no potential output is produced from the ACM circuit. Alternatively, zero will be output.

[0117] Here, the potential output from circuit ACP is assigned to multiple "positive" values, and the output from circuit ACM is... By assigning the applied potential to multiple "negative" values, it becomes possible to sense only positive voltages. When using analog-to-digital conversion circuits (sense amplifiers, comparators, etc.) However, even if the sum of the products of the first and second data is negative, the output signal z j (k) It can output multiple "negative" values. Note that in Figure 4, the AC circuit is An example has been shown of a case having circuit ACP and circuit ACM, but one aspect of the present invention relates to this Not limited. Circuit ACP and circuit ACM are both replaced with circuit AC only, and the AC circuit is used twice for sensing. It may also be possible to perform a time-division operation. In other words, the operation of the AC circuit is divided into two parts and operated in a time-division manner. This may be done. This will increase processing time, but it will reduce the size of the circuit. .

[0118] <Example of arithmetic circuit configuration 2> Next, we will explain an example of a specific circuit configuration of circuit ACTF[j]. Circuit ACTF[ j] can be configured as shown in Figure 5, for example. Figure 5 shows, as an example, the circuit configuration The signal z is input from line OL[j] and wiring OLB[j] according to the current. j (k) Generate This is a circuit. Specifically, Figure 5 shows the output signal, which is represented by multiple levels or analog values. z j (k) An example of an arithmetic circuit that outputs is shown. Therefore, the circuit ACTF[j] is For example, a structure that functions as an activation function circuit in a neural network. This can be achieved. Figure 5 shows the electrical relationship between circuit ACTF[j] and the surrounding circuits. To illustrate the connection configuration, the array unit ALP and the circuit AFP are also shown in the diagram.

[0119] The circuit ACTF[j] shown in Figure 5 is, as an example, a combination of switch SWR1 and switch SWR 1B, switch SWR2, switch SWR2B, circuit IVTR, circuit IVTRr It has a capacitance CRE and a circuit AC.

[0120] Switch SWR1, Switch SWR1B, Switch SWR2, and Switch SWR2B Examples of each include electrical switches such as analog switches and transistors. These can be applied. Note that switch SWR1, switch SWR1B, switch For example, a transistor can be applied to at least one of SWR2 and switch SWR2B. In this case, the transistor can be used as a transistor CRET. It is possible to do so. Furthermore, in addition to electrical switches, mechanical switches can also be used. stomach.

[0121] The IVTR circuit is electrically connected to terminal T1 and the first terminal of switch SWR1. Yes. The second terminal of switch SWR1 is connected to the first terminal of capacitor CRE, and the second terminal of switch SWR2. Terminal 1 is electrically connected to the other terminal. The second terminal of switch SWR2 is connected to wiring VCN3. They are electrically connected. Circuit IVTRr is connected to terminal T2 and the first terminal of switch SWR1B. The child is electrically connected to the second terminal of switch SWR1B. The second terminal of capacitor CRE is connected to the second terminal of capacitor CRE. The terminal is electrically connected to the first terminal of switch SWR2B. The second terminal of 2B is electrically connected to terminal mbt1 of circuit AC.

[0122] Wiring VCN3 functions as wiring that provides a constant voltage. This constant voltage can be, for example, It can be the ground potential (GND) or a low-level potential. Alternatively, as an example, VDD (High-level potential) can be achieved.

[0123] Circuit AC has terminal mbt1 and terminal mbt2. As for circuit AC, as described above... As shown above, one example is an analog-to-digital conversion circuit. Figure 5 shows The AC circuit senses the potential applied to terminal mbt1 and outputs it as a digital signal to the terminal Output signal z corresponding to the potential from mbt2 j (k) It has the function to output [something]. Therefore, For example, circuit AC is an analog-to-digital conversion circuit that converts a 1-bit digital signal. In this case, terminal mbt2 will be one, and for example, if circuit AC is k bits (where k is 2 or more integers), It is a number.) If it is an analog-to-digital conversion circuit that converts to a digital signal, terminal m There are k bt2s. Note that in Figure 5, terminal mbt2 is shown as multiple terminals. For example, circuit AC performs analog-to-digital conversion based on a predetermined set of potentials. Next, the analog potential (or multi-level digital value) of terminal mbt1 is converted into a digital signal. Then, output it.

[0124] In particular, the circuit ACTF[j] in Figure 5 is used in a hierarchical neural network. When applying Ron's activation function as a circuit, for example, to an analog-to-digital converter, circuit AC can be converted. In the exchange, if the potential of terminal mbt1 of circuit AC is lower than the potential supplied by wiring VCN3, If the sum of the products of the first and second data points is negative, then output that value. Instead, by configuring it to output zero, the circuit of the activation function is made a step function It can function as a circuit that outputs a value.

[0125] The IVTR circuit is a device that converts the current flowing through the wiring OL[j] into a voltage value (or charge). This is a circuit that has the ability to control the current flowing through the wiring OLB[j]. Furthermore, the circuit IVTRr controls the voltage. A circuit having the function of converting to a value (or charge quantity), with a configuration similar to that of the IVTR circuit. This is possible. As a result, in the circuit ACTF[j] in Figure 5, the circuit IVTR is Convert the current flowing through wiring OL[j] into a voltage value (or charge amount), and switch that voltage value. The first terminal of SWR1 can be supplied, and the circuit IVTRr flows into the wiring OLB[j]. The current is converted into a voltage value (or charge), and this voltage value is sent to the first terminal of switch SWR1B. It can be given to a child.

[0126] The IVTR circuit (IVTRr circuit) has the circuit configuration shown in Figures 6A to 6C, for example. This is possible. Note that to distinguish between circuit IVTR and circuit IVTRr, see Figures 6A to 6. In C, the symbols of circuit elements included in wiring OLB[j] and circuit IVTRr are indicated in parentheses. They are doing it.

[0127] The circuit IVTR (circuit IVTRr) shown in Figure 6A has a switch SWR3 (switch SWR 3B) and capacitive CRT (capacitive CRTB) are included. Wiring OL[j](Wiring OLB[j ]) is connected to the first terminal of switch SWR3 (switch SWR3B) and capacitance CRT (capacitance CR The first terminal of TB is electrically connected to the switch SWR3 (switch SWR3 The second terminal of B) is electrically connected to the second terminal of the capacitive CRT (capacitive CRTB) and to the wiring VCN4. It is connected.

[0128] Switch SWR3 and Switch SWR3B are, for example, the aforementioned switches Switch SWR1, Switch SWR1B, Switch SWR2, and Switch SWR2B are the same. Applicable switches can be used.

[0129] Wiring VCN4 functions, for example, as wiring that provides a constant voltage. This can be, for example, a high-level potential, ground potential, or a low-level potential. Therefore, wiring VCN4 may be given the same potential as wiring VSO, which will be described later. For example, wiring VCN4 may be electrically connected to wiring VSO. That is, Wiring VCN4 and wiring VSO can be combined into a single wire.

[0130] The circuit IVTR (circuit IVTRr) shown in Figure 6A has a switch SWR3 (switch SWR By turning on 3B), the wiring OL[j] (wiring OLB[j]) and wiring VCN4 The space between them can be made conductive, and wiring OL[j] (wiring OLB[j]) to wiring VCN4 A constant voltage can be applied. Wiring OL[j] (wiring OLB[j]) to wiring VCN4 The operation of applying a constant voltage involves obtaining information (current, electricity) from circuit MP[1,j] or circuit MP[m,j]. This corresponds to the initial operation for reading out (such as pressure). Alternatively, for a capacitive CRT (capacitive CRTB) This corresponds to the operation of initializing the accumulated charge. Also, the circuit IVTR(times) shown in Figure 6A By turning off switch SWR3 (switch SWR3B), The amount of current flowing through wiring OL[j] (wiring OLB[j]) is treated as charge at the first terminal of the capacitive CRT. It can be charged. In other words, the potential of the first terminal of the capacitive CRT is the wiring OL[j](distribution It is determined according to the amount of current flowing through the line OLB[j]).

[0131] Furthermore, the amount of current flowing through wiring OL[j] (wiring OLB[j]) is, for example, circuit MP [1,j] or circuit MP[m,j] and wiring OL[j] (wiring OLB[j]) flow It can be expressed as the sum of the currents. Therefore, circuit MP[1,j] to circuit MP[m,j] The current flowing between each of the ] and the wiring OL[j] (wiring OLB[j]) is measured over a certain period of time. By allowing the charge to flow through, the charge charged to the first terminal of the capacitive CRT is distributed through the wiring OL[j It is determined by the amount of current flowing through the wiring OLB[j] and the corresponding time. In other words, Circuit IVTRr (Circuit IVTRr) is the first terminal of switch SWR1 (Switch SWR1B) The voltage applied to the child is the amount of current flowing through each of the circuits MP[1,j] to MP[m,j]. It is determined by the time.

[0132] By the way, the parasitic resistance or capacitance related to the wiring OL[j] (wiring OLB[j]) When the current flowing through wiring OL[j] (wiring OLB[j]) is converted into a voltage, circuit I The VTR (circuit IVTRr) can have the circuit configuration shown in Figure 6B. In other words, Figure 6 In circuit IVTR (circuit IVTRr), the capacitance CRT (capacitance CRTB) is omitted. It is possible.

[0133] The circuit IVTR (circuit IVTRr) shown in Figure 6C is a switch SWR3 (switch SWR 3B) and resistor RRT (resistor RRTB) are included. Wiring OL[j](Wiring OLB[j ]) is connected to the first terminal of switch SWR3 (switch SWR3B) and resistor RRT (resistor RR The first terminal of TB is electrically connected to the switch SWR3 (switch SWR3 The second terminal of B) is electrically connected to the second terminal of resistor RRT (resistor RRTB) and to wiring VCN4. It is connected.

[0134] The circuit IVTR (circuit IVTRr) shown in Figure 6C is a switch SWR3 (switch SWR By turning on 3B), the wiring OL[j] (wiring OLB[j]) and wiring VCN4 The space between them can be made conductive, and wiring OL[j] (wiring OLB[j]) to wiring VCN4 A constant voltage can be applied. Wiring OL[j] (wiring OLB[j]) to wiring VCN4 The operation of applying a constant voltage involves obtaining information (current, electricity) from circuit MP[1,j] or circuit MP[m,j]. This corresponds to the initial operation for reading out (such as pressure). Also, the circuit shown in Figure 6C is an IVTR (circuit). IVTRr) is controlled by turning off switch SWR3 (switch SWR3B). The amount of current flowing through line OL[j] (wiring OLB[j]) is the switch SWR3 (switch SW The current flows through resistor RRT (resistor RRTB) to wiring VCN4, bypassing R3B. At that time, between the first and second terminals of resistor RRT (resistor RRTB), resistor RRT (resistor A voltage is generated corresponding to the resistance value of RRTB and the amount of current. In other words, the capacitance of the CRT The potential of terminal 1 is determined by the amount of current flowing through the wiring OL[j] (wiring OLB[j]) and the resistor RRT( The resistance value of resistor RRTB is determined accordingly. Note that switch SWR3 (switch S WR3B) does not necessarily have to be provided.

[0135] Next, we can apply this to the circuit ACTF[j] in Figure 2, which is different from the circuit ACTF[j] in Figure 5. Let's explain an example of a circuit configuration.

[0136] The circuit ACTF[j] shown in Figure 7A is a modified version of the circuit ACTF[j] shown in Figure 5. This is an example configuration. Specifically, the second terminal of switch SWR2 is connected to the terminal mbt of circuit AC. 1 is electrically connected, and the wiring VCN3 is electrically connected to the second terminal of switch SWR2B. In this respect, it differs from the circuit ACTF[j] in Figure 5.

[0137] Furthermore, an example of a circuit configuration that can be applied to the circuit ACTF[j] in Figure 2 is shown in Figure 7B. The circuit ACTF[j] in Figure 7B is a switch S WR2, switch SWR2B, switch SWR6, switch SWR6B, and switch SWR7, switch SWR7B, capacitance CRE, circuit IVTR, and circuit IVTRr It has a circuit AC and

[0138] The first terminal of switch SWR6 is electrically connected to terminal T1, and the second terminal of switch SWR6 The two terminals are the first terminal of switch SWR7 and the first terminal of switch SWR2, and the capacitor CRE. The first terminal of the switch SWR7 is electrically connected to the circuit IVT. R is electrically connected, and the second terminal of switch SWR2 is electrically connected to wiring VCN3. The first terminal of switch SWR6B is electrically connected to terminal T2, and switch SW The second terminal of R6B connects to the first terminal of switch SWR7B and the first terminal of switch SWR2B. The second terminal of the capacitor CRE is electrically connected to the second terminal of the switch SWR7B. The child is electrically connected to circuit IVTRr, and the second terminal of switch SWR2B is connected to circuit AC. They are electrically connected.

[0139] Switch SWR6, Switch SWR6B, Switch SWR7, and Switch SWR7B For example, each of these includes the aforementioned switch SWR1, switch SWR1B, and switch Switches that can be used in the same way as Switch SWR2 and Switch SWR2B can be used. .

[0140] For each of circuits AC, IVTR, and IVTRr, see Circuit AC in Figure 5. Refer to the descriptions of circuits AC, IVTR, and IVTRr included in TF[j]. ru.

[0141] Furthermore, a circuit configuration that can be applied to the ACTF[j] circuit in Figure 2A is, for example, shown in Figure 7C. The circuit ACTF[j] shown in Figure 7C can be represented as shown in Figure 7B. The ACTF[j] circuit is configured without switches SWR7 and SWR2B. In other words, in the circuit ACTF[j] in Figure 7C, the second terminal of switch SWR6 It is electrically connected to circuit IVTR, and terminal mbt1 of circuit AC is connected to the second terminal of capacitance CRE. The child, the second terminal of switch SWR6B, and the first terminal of switch SWR7B are electrically connected. It is connected.

[0142] Replace any one of the circuits ACTF[j] in Figures 7A to 7C with the circuit ACTF[j] in Figure 2. By applying this, the first data and the second data are similar to the ACTF[j] circuit in Figure 5. As a result of the sum of products, the signal z j (k) It can output.

[0143] <Example of operation of the arithmetic circuit 2> Next, we will explain an example of the operation of the ACTF[j] circuit in Figure 5. As an example, let's use the arithmetic circuit 110A shown in Figure 8. The arithmetic circuit 110A is shown in Figure 5. The circuits IVTR and IVTRr included in the circuit ACTF[j] shown are shown in Figure 6A. The configuration utilizes a circuit IVTR (circuit IVTRr).

[0144] Furthermore, Figure 8 shows, as an example, the switch SWR1 included in the circuit ACTF[J]. Switch SWR2, Switch SWR3, Switch SWR1B, Switch SWR2B, Switch As wiring for switching between the on and off states of each of the SWR3B switches, Wiring SRL1, SRL2-1, SRL2-2, and SRL3 are shown in the diagram. Specifically, wiring SRL1 connects to the control terminal of switch SWR1 and the control terminal of switch SWR1B. The terminals are electrically connected, and wiring SRL2-1 is electrically connected to the control terminal of switch SWR2. The wiring SRL2-2 is electrically connected to the control terminal of switch SWR2B. The wiring SRL3 connects to the control terminal of switch SWR3 and the control terminal of switch SWR3B. , are electrically connected. For example, switch SWR1, switch SWR2, Switch SWR3, Switch SWR1B, Switch SWR2B, or Switch SWR3 In some cases, or depending on the circumstances, parts of B may be omitted. In other words, for example, switch SWR1, switch SWR2, switch SWR1B, switch SWR2B has a circuit configuration in which some of those switches are always in the ON state. It is also fine to use another switch, for example, by using a different switch, switch SWR3 Switch SWR3B is used when some of those switches are always in the off state. It may be configured as a circuit. Or, for example, switch SWR1, switch SWR2, switch Switch SWR3, Switch SWR1B, Switch SWR2B, and Switch SWR3B are connected. It is also possible to change some of the configuration. For example, wiring SRL1, wiring SRL2- 1. Wiring SRL2-2, or wiring SRL3, may be used depending on the circumstances. Therefore, some of them can be omitted. For example, wiring SRL2-1 and wiring SRL2- You can combine the two into a single wire. Or, for example, switch SWR1 and switch By reversing the on / off polarity of switch SWR2 (switch SWR2B), the wiring SR You can combine L1 and wiring SRL2-1 (wiring SRL2-2) into a single wire. Yes. This allows you to control switch SWR1 and switch SWR2 (switch SWR 2B) can be turned on and off alternately.

[0145] Figure 8 also shows the first terminal of switch SWR1, the first terminal of capacitive CRT, and the switch Node n4 is shown as the electrical connection point between the first terminal of SWR3 and switch SWR1. The first terminal of B, the first terminal of capacitor CRTB, and the first terminal of switch SWR3B, Node n4r is shown as a target connection point. Also, the second terminal of switch SWR1 and The electrical connection point between the first terminal of capacitance CRE and the first terminal of switch SWR2 is, The diagram shows the second terminal of switch SWR1B, the second terminal of capacitor CRE, and the switch The first terminal of SWR2B is shown, and node n5r is shown as the electrical connection point.

[0146] Figure 9 shows an example of the operation of the ACTF[j] circuit of the calculation circuit 110A in Figure 8. This is a chart, and the timing chart covers the period from time T01 to time T08, and so on. In the vicinity of, wiring XLS[1] to wiring XLS[m], wiring SRL1, wiring SRL2 -1, wiring SRL2-2, wiring SRL3, node n4, node n4r, node n5, no This shows the potential fluctuation of n5r. Note that "high" shown in Figure 9 represents the high-level potential. This indicates a low potential, and "low" indicates a low-level potential.

[0147] Note that in this example of operation, switches SWR1, SWR2, and SWR1B are used. , and switch SWR2B each react when a high-level potential is input to the control terminal. The device will enter an "on" state and will turn off when a low-level potential is input to the control terminal.

[0148] Furthermore, the timing chart in Figure 9 summarizes the wiring XLS[1] to wiring XLS[m]. This is illustrated in the diagram. Also, in the timing chart of Figure 9, wiring XLS[1] to wiring XLS The hatching indicates the period during which the second data point is entered in [m].

[0149] In this example, current flows from wiring OL[j] to circuit MP, and wiring OLB[ Assume that current flows from [j] to circuit MP. Therefore, circuit MP has VSS (low level Wiring that provides a potential (for example, wiring VE and wiring VEr as described in Embodiment 2) (and can be done) are assumed to be electrically connected (not shown in Figure 8), and wiring VC Let VDD (high-level potential) be the constant voltage supplied by N4. Also, from wiring OL[j] to circuit M The amount of current flowing through P, and the amount of current flowing from wiring OLB[j] to circuit MP, are stored in circuit MP. It is determined by the first data that is held and the second data input from the XLS wiring. , the amount of current flowing from wiring OL[j] to circuit MP, and / or from wiring OLB[j] to circuit M The amount of current flowing through P may be zero. Also, the constant voltage supplied by wiring VCN3 is VS Let S be the correct term.

[0150] Before time T01, each of circuits MP[1,j] to MP[m,j] The first data is the weight coefficient w1 (k-1) j (k) Or maybe lol m(k-1) j (k) ga It is assumed that it is possessed.

[0151] Furthermore, prior to time T01, the wiring XLS[1] to wiring XLS[m] had low-level A bell potential is input to wiring SRL1, wiring SRL2-1, wiring SRL2-2, and wiring S A low-level potential is input to RL3. Also, nodes n4, n4r, and n Let VSS be the potentials of node 5 and node n5r, respectively.

[0152] Between time T01 and time T02, wiring SRL1 and wiring SRL3 have high A level potential is input. When a high level potential is input to wiring SRL1, the switch Switch SWR1 and switch SWR1B are in the ON state, and a high level potential is applied to wiring SRL3. When input is received, switches SWR3 and SWR3B are turned ON. .

[0153] Also, between time T01 and time T02, wiring SRL2-1 and wiring SR A low-level potential is input to L2-2. Low-level potential is input to wiring SRL2-1 and wiring SRL2-2. When a level potential is input, switches SWR2 and SWR2B become It enters a state of "F".

[0154] As a result, the first connection between wiring VCN4 and wiring OL[j], and between wiring VCN4 and capacitance CRE The connection between the terminal and the wire becomes conductive. Also, the connection between wiring VCN4 and wiring OLB[j] and wiring V The connection between CN4 and the second terminal of capacitance CRE, and between wiring VCN4 and terminal mbt1, are in a conductive state. Therefore, the connection between wiring VCN3 and the first terminal of capacitor CRE becomes non-conductive. The potentials of node n4, node n4r, node n5, and node n5r are VD The answer is D.

[0155] Between time T02 and time T03, a low-level potential was input to wiring SRL3. When a low-level potential is input to the wiring SRL3, the switch SWR3 and S Switch SWR3B is turned off. Therefore, the connection between wiring VCN4 and wiring OL[j] The circuit becomes non-conductive, and the connection between wiring VCN4 and wiring OLB[j] becomes non-conductive, and the node Nodes n4, n5, n4r, and n5r are in a floating state.

[0156] Between time T03 and time T04, the circuit MP[1,j] of the array unit ALP For each of the circuits MP[m,j], the neuron's signal z1 is used as the second data. (k -1) ~z m (k-1) It will be sent.

[0157] As a result, in circuit MP[i,j], the weight coefficient w i (k-1) j (k) and New - Ron's signal z1 (k-1) Depending on the situation, either wiring OL[j] or wiring OLB[j] is connected to the circuit. Current flows between circuit MC and the other side of wiring OL[j] or wiring OLB[j] and circuit MCr. A current flows between them. Here, each of circuits MP[1,j] to MP[m,j] and The sum of the currents flowing between the wiring OL[j] and the wiring is I. out Let [j] be the circuit MP[1,j] The sum of the currents flowing between each of the circuits MP[m,j] and the wiring OLB[j] is I Bo ut Let's call it [j].

[0158] At this time, the potentials of nodes n4 and n5 are determined by the current flowing through wiring OL[j]. The current decreases, and the potentials of nodes n4r and n5r also decrease, as does the current flowing through the wiring OLB[j]. It decreases due to this.

[0159] Note that in this example, I Bout I out Assume that [j] is large. Therefore, the potentials of nodes n4 and n5 between time T03 and time T04. The decrease in the potential of node n4r and node n5r is assumed to be greater than the decrease in the potential of node n4r. (Figure 9) In the timing chart, at time T04, the potentials of nodes n4 and n5 are V I out The potential V of nodes n4r and n5r decreases to this level. IBout Those that have decreased to that point That is what they say.

[0160] Furthermore, at time T04, a low-level potential is input to wiring SRL1. When a low-level potential is input to 1, switches SWR1 and SWR1B The circuit is turned off. As a result, the connection between the first terminal of the capacitor CRE and the wiring OL[j] is non-conductive. This results in a non-conductive state between the second terminal of the capacitance CRE and the wiring OLB[j]. Therefore, the potential drop at the first terminal (node ​​n5) of the capacitance CRE stops, and the second terminal (node ​​n5) of the capacitance CRE The potential drop at terminal 2 (node ​​n5r) stops. Also, the first terminal (node ​​n5r) of capacitance CRE stops. The voltage between node n5) and the second terminal of the capacitor CRE (node ​​n5r) is maintained. The potentials of node n4 and node n4r continue to decrease from before time T04.

[0161] Between time T05 and time T06, wiring XLS[1] to wiring XLS[m] A low-level potential is input to each of them. As a result, the circuit MP[1, The neuronal signal corresponding to the second data for each of the circuits MP[m,j], i.e., j[m,j] z1 (k-1) ~z m (k-1) The supply will be stopped. As a result, wiring OL[j] or The current flowing to circuit MP stops, and the current flowing from wiring OLB[j] to circuit MP also stops. To stop. Therefore, the decrease in potential at node n4 and node n4r stops.

[0162] Between time T06 and time T07, a high-level potential was applied to wiring SRL2-1. The switch SWR is affected. When a high-level potential is input to wiring SRL2-1, the switch SWR is affected. Terminal 2 is turned ON. As a result, there is electrical conductivity between the first terminal of the capacitor CRE and the wiring VCN3. As a result, the potential of the first terminal (node ​​n5) of the capacitance CRE becomes VSS.

[0163] By the way, the second terminal (node ​​n5r) of the capacitance CRE is in a floating state, The potential at the first terminal (node ​​n5) of the capacitance CRE is V Iout The change from VSS Therefore, the potential of the second terminal (node ​​n5r) of the capacitive CRE also changes due to capacitive coupling. The amount of change in potential due to capacitive coupling is determined according to the capacitive coupling coefficient, but in this specification, etc., a simplified To explain it simply, the potential of the first terminal of the capacitance CRE is V Iout When it changed from VSS The potential of the second terminal of the capacitance CRE is V IBout -(V Iout -VSS) (Tie in Figure 9) In the Ming chart, V OPIt shall change to (notation). In other words, this change in potential is This corresponds to the case where the capacitance CRE and the capacitive coupling coefficient, which are determined according to the surrounding circuit elements, are set to 1. .

[0164] Between time T07 and time T08, a high-level potential was applied to wiring SRL2-2. The switch SWR is affected. When a high-level potential is input to wiring SRL2-2, the switch SWR is affected. 2B is turned ON. Therefore, the second terminal (node ​​n5r) and terminal mbt of the capacitor CRE are connected. A conductive state is established between point 1 and point 1.

[0165] At this time, the potential at terminal mbt1 of circuit AC is the same as the potential at the second terminal (node ​​n5r) of capacitor CRE. V is OP The following is entered.

[0166] As a result, the AC circuit is connected to the potential V input to terminal mbt1. OP Digital signals corresponding to as z j (k) A signal with the value of [value] is output.

[0167] z j (k) The potential V corresponds to the amount of current flowing through the wiring OL[j]. Iout And, wiring OLB [j] has a potential V corresponding to the amount of current flowing through it. IBout The output value is based on the potential difference between the two. Yes, it exists. In other words, the electric potential V Iout , potential V IBout is, I out [j] and I Bout [ j] and the time during which switches SWR1 and SWR2 are ON (time T0 It is determined by the time from 3 to time T04. out [j] and I Bout [j] is the first held in each of the circuits MP[1,j] through MP[m,j] Data 1 w1 (k-1) j (k) Or maybe lol m (k-1) j (k) And, circuit M The value z1 of the signal, which is the second data input to P[1,j] or circuit MP[m,j] (k- 1) ~z m (k-1) And the result of the sum-of-products operation, that is, u in equation (1.2) j (k) in response This is the current. On the other hand, the potential V Iout , potential V IBout This is the switch SWR1 and the switch The duration for which the SWR2 switch is ON (the time from time T03 to time T04) Since this time changes over time, it is preferable that the time be set appropriately according to the circuit AC. .

[0168] In this example, the amount of current is I out [j] and I Bout Convert each of [j] to an electric potential. In exchange, the potential difference between them is input to the AC circuit, z j (k) The value is output. In other words, circuit AC is the activation function circuit in a hierarchical neural network. By doing so, z is output as a digital signal. j (k) The value of z is given by equation (1.4). j (k ) This can be set to a potential equivalent to [a certain value].

[0169] By the way, between time T07 and time T08, switch SWR2B was ON. At the stage where it has reached that point, strictly speaking, if we also consider the effects of parasitic resistance and parasitic capacitance, terminal mb The potential input to t1 is V OP It may fluctuate from this. In this case, the circuit AC is capacitance C. Considering the resistance of the wiring between the second terminal of RE and terminal mbt1, the input to terminal mbt1 is It is preferable that the design appropriately compensates for the potential.

[0170] Furthermore, in the above example of operation, I Bout I out Explain the case where [j] is large. I did. out I Bout If [j] is large, at time T04 , the potential V of node n5 Iout The potential V of node n5r is greater than IBout This becomes lower. Therefore, between time T06 and time T07, switch SWR2 was in the ON state. At that time, the potential at node n5r is lower than that at VSS due to the capacitive coupling of the capacitive CRE. And so, between time T07 and time T08, terminal mbt1 receives VSS A lower potential is input. In this case, the configuration of the AC circuit is, for example, terminal mbt2 output signal z j (k) It may also be configured to output a digital signal corresponding to 0. This is the activation function f(u) in a hierarchical neural network. j (k) ) but, u j (k ) This is equivalent to functioning as a ramp function that outputs 0 when the value is negative.

[0171] <Example of arithmetic circuit configuration 3> Furthermore, one aspect of the present invention is the circuit configuration of the circuit ACTF[j] in Figure 5, which is included in the arithmetic circuit. The invention is not limited to the present invention. For example, a figure included in a semiconductor device (arithmetic circuit) according to one aspect of the present invention. Circuit ACTF[j] in 5 should be changed to the circuit configuration shown in circuit ACTF[j] in Figure 10. This is possible. The circuit ACTF[j] in Figure 10 is a combination of switch SWR1 and switch SWR1B. Switch SWR2, Switch SWR2B, Switch SWR3, Switch SWR3 B, switch SWR4, switch SWR4B, load LE, load LEB, op-pair It has an op-amp OP, an op-amp OPB, and a circuit AC. Note that the circuit ACT shown in Figure 5 Explanations of parts that overlap with F[j] will be omitted.

[0172] Switch SWR3, Switch SWR3B, Switch SWR4, Switch SWR4B For example, switch SWR1, switch SWR1B, switch SWR2, It can also be used as a switch that can be applied in the same way as the SWR2B switch.

[0173] The first terminal of switch SWR3 is connected to terminal T1, the first terminal of switch SWR4, and the load L The first terminal of E is electrically connected to the second terminal of switch SWR3, which is connected to the wiring VC. It is electrically connected to N4. The non-inverting input terminal of the operational amplifier OP is wired to Vref1L. Electrically connected, the inverting input terminal of the op-amp OP is connected to the second terminal of switch SWR4. Electrically connected, the output terminal of the operational amplifier OP is connected to the second terminal of the load LE and the switch SW. It is electrically connected to the first terminal of R1.

[0174] The first terminal of switch SWR3B is connected to terminal T2, and the first terminal of switch SWR4B, and The first terminal of the load LEB is electrically connected to the first terminal of the switch SWR3B. It is electrically connected to wiring VCN4. The non-inverting input terminal of the op-amp OPB is connected to wiring V Electrically connected to ref2L, the inverting input terminal of op-amp OPB is switched SWR4 The second terminal of B is electrically connected, and the output terminal of the operational amplifier OPB is connected to the second terminal of the load LEB. The child is electrically connected to the first terminal of switch SWR1B.

[0175] Note that the wiring Vref1L and Vref2L here have the same voltage, or different voltages. It functions as wiring that supplies voltage. Therefore, wiring Vref1L, wiring Vref2 L can sometimes be combined into a single wire.

[0176] In the circuit shown in Figure 10, ACTF[j] is in the ON state when switch SWR3 (switch SWR3B) is ON. By turning switch SWR4 (switch SWR4B) to the OFF state, Figure 10 Similarly, the initial voltage applied to the wiring OL[j] (wiring OLB[j]) by wiring VCN4 It is possible to perform the work.

[0177] In the circuit ACTF[j] in Figure 10, the loads LE and LEB are, for example, resistors. This can be expressed as capacity, etc. In particular, capacity can be used as load LE and load LEB. Therefore, the integral between op-amp OP and load LE, and between op-amp OPB and load LEB, are each the number of integrals. It functions as a path. In other words, it turns off switches SWR3 and SWR3B, By turning on switch SWR4 and switch SWR4B, the wiring OL[j] Alternatively, depending on the amount of current flowing through the wiring OLB[j], the respective capacities (load LE, load LEB) Charge is stored in ). In other words, the current flowing from wiring OL[j] and OLB[j] is integral The circuit converts the voltage, and each voltage is then used by op-amp OP and op-amp OPB. It is output from the output terminal.

[0178] By making loads LE and LEB capacitances, the ACTF[j] circuit in Figure 10 is distributed The amount of charge flowing through line OL[j] is converted into a voltage value, and this voltage value is used for the first switch SWR1. It can be applied to the terminal, and the amount of charge flowing through the wiring OLB[j] can be converted into a voltage value. This voltage value can be applied to the first terminal of switch SWR1B.

[0179] Furthermore, the circuit ACTF[j] in Figure 5 has the same circuit configuration as shown in the circuit ACTF[j] in Figure 11A. It can be changed. The circuit ACTF[j] in Figure 11A is a switch SWR3 and a switch Switch SWR3B, Switch SWR4, Switch SWR4B, Switch SWR5, Negative It comprises a load LEA, a load LEAB, an operational amplifier OPA, and a circuit AC.

[0180] Switch SWR3, Switch SWR3B, Switch SWR4, Switch SWR4B, Each of the switches SWR5 is, for example, switch SWR1, switch SWR1B, It can be made into a switch that can be used in the same way as switch SWR2 and switch SWR2B. Cut.

[0181] The first terminal of switch SWR3 is connected to terminal T1, the first terminal of switch SWR4, and the load L The first terminal of EA is electrically connected to the second terminal of switch SWR3. It is electrically connected to CN4. The inverting input terminal of the op-amp OP is switched to SWR4. It is electrically connected to the second terminal of the load LEA. The second terminal of the switch SWR5 is connected to the second terminal of the switch SWR5. It is electrically connected to terminal 1. The first terminal of switch SWR3B is connected to terminal T2 and the switch The first terminal of the SWR4B switch is electrically connected to the first terminal of the LEAB load. The second terminal of switch SWR3B is electrically connected to wiring VCN4. Op-amp The non-inverting input terminal of OP is electrically connected to the second terminal of switch SWR4B. The second terminal of the load LEAB is electrically connected to the wiring VCN5. The output of the op-amp OP The power terminal is electrically connected to the second terminal of switch SWR5 and terminal mbt1 of circuit AC. It is being done.

[0182] Note that wiring VCN5 functions as wiring that provides a constant voltage. For example, this constant voltage is... For example, it can be the ground potential or a low-level potential.

[0183] In the circuit shown in Figure 11A, ACTF[j] is when switch SWR3 (switch SWR3B) is ON. Set the switch SWR4 (switch SWR4B) to the OFF position, and switch SWR5 By turning it off, the wiring OL[j] (wiring OLB[j]) will be affected, similar to Figure 10. The initial operation can be performed by applying a constant voltage to the wiring VCN4.

[0184] In the circuit ACTF[j] in Figure 11A, loads LEA and LEAB are, for example, These can be resistors, capacitors, etc. Furthermore, a subtraction circuit can be constructed using an operational amplifier (OPA). In this case, resistors can be used as load LEA and load LEAB. A. By making the load LEAB a resistor, the connection between the first and second terminals of the load LEA and the negative The operational amplifier outputs a voltage corresponding to the difference in current flowing between the first and second terminals of the load LEAB. It can be output from the OPA's output terminal. This allows for switch SWR3, switch Turn SWR3B to the OFF state, and turn on switches SWR4 and SWR4B. By turning switch SWR5 ON, the wiring OL[j] and wiring OLB[j] Output a voltage from the output terminal of the operational amplifier (OPA) corresponding to the difference in the current flowing through each component. It is possible.

[0185] Furthermore, the voltage output from the output terminal of the operational amplifier OPA is input to the input terminal of the circuit AC. This allows the analog voltage output from the output terminal of the operational amplifier OPA to be used in circuit A. It can be converted into a digital signal by C. Furthermore, this digital signal is New Ron's calculated value z j (k) Therefore, it can be output from the AC terminal mbt2 of the circuit. ru.

[0186] Furthermore, by changing the circuit configuration of the ACTF[j] circuit in Figure 11A, we obtain the ACTF circuit in Figure 11B. [j] may also be used. The circuit ACTF[j] in Figure 11B is the same as the circuit ACTF[j] in Figure 11A. This configuration does not include a circuit AC, and as a result, the output terminal of the operational amplifier OPA is The analog voltage output from the child is used to calculate the signal value z of the neuron. j (k) It is possible to do so Cut.

[0187] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0188] (Embodiment 2) In this embodiment, the calculation circuit 110 and calculation circuit 110A described in the above embodiment are used. This section will also describe the circuit configuration surrounding the arithmetic circuit 120 and provide an example of its operation. .

[0189] <Example of arithmetic circuit configuration 1> The calculation circuit 130 shown in Figure 12, for example, includes an array unit ALP, a circuit ILD, and a circuit This is a semiconductor device having a WLD, a circuit XLD, and a circuit AFP. The arithmetic circuit 130 is Neurons N1 in layer k in Figures 1A and 1B (k) Neuron N n (k) to Input signal z1 (k-1) ~z m (k-1) Process, neuron N1 (k) No Destination neuron N n (k) The signal z1 is output from each of them. (k) ~z n (k) generate This is a circuit that does that.

[0190] Furthermore, in the entirety or in part of the arithmetic circuit 130, a neural network or It may be used for purposes other than AI. For example, calculations for graphics or scientific calculations. In such cases, when performing multiply-accumulate operations or matrix operations, the entire arithmetic circuit 130, It is also possible to use a part of it to perform processing. In other words, not only calculations for AI, but also general calculations. For example, the entirety or a part of the arithmetic circuit 130 may be used for calculations. For example, if the entire or a part of the arithmetic circuit 130 is used for purposes such as a memory device That's good too.

[0191] Circuit ILD is, for example, a wiring IL[1] through wiring IL[n] and wiring ILB[1] The circuit WLD is electrically connected to the wiring ILB[n]. For example, the wiring WL It is electrically connected to S[1] or wiring WLS[m]. Circuit XLD is, for example, wiring It is electrically connected to XLS[1] or wiring XLS[m]. Circuit AFP is an example. And, wiring OL[1] to wiring OL[n] and wiring OLB[1] to wiring OLB[n], It is electrically connected to it.

[0192] <<Array Unit ALP>> The array unit ALP has, for example, m × n circuits MP. Within the ALP array section, they are arranged in an m x n matrix. In Figure 12, row i, column j (where i is an integer between 1 and m, and j is an integer between 1 and n, from 1 to n). The circuit MP located at (i,j) is an integer. (Note: Figure 1) In 2, the circuits MP[1,1], MP[m,1], MP[i,j], and MP[1 The circuit MP[m,n] is shown as an excerpt.

[0193] Circuit MP[i,j] is, for example, a combination of wiring IL[j], wiring ILB[j], and wiring W LS[i], wiring XLS[i], wiring OL[j], wiring OLB[j], and electrical Connected.

[0194] Circuit MP[i,j] is, for example, the circuit MP[1,j] described in the above embodiment. ] or has the same function as circuit MP[m,j]. Furthermore, circuit MP[i,j] has the same function as circuit M The weight coefficients (first data) held in P[i,j] are used for wiring IL[j] and wiring ILB[ It has the function of obtaining from j]. Note that in Figure 12, wiring IL[j] and wiring ILB[j An example of the case where [] is arranged has been shown, but one aspect of the present invention is not limited thereto. Either IL[j] or wiring ILB[j] may be present.

[0195] Further details regarding circuits MP[1,1] through MP[m,n] will be provided later. .

[0196] <<Circuit XLD>> The circuit XLD in Figure 12 is, for example, connected via wiring XLS[1] to wiring XLS[m] For each of the circuits MP[1,1] through MP[m,n], neuron N1 (k -1) Neuron N m (k) z1 is the calculated value output from (k-1) ~z m ( k-1) (This may be referred to as Data 1 or Data 2. Here, we will refer to it as Data 2.) It has the function of supplying . Specifically, circuit XLD has the function of supplying circuit MP[i,1] to circuit For MP[i,n], neuron N i (k-1) The second data z output from i (k -1) The corresponding information (e.g., potential, current value, etc.) is supplied by the wiring XLS[i]. The example shown is when wiring XLS[i] is present, but one aspect of the present invention is However, it is not limited to this. For example, in the arithmetic circuit 130 of Figure 12, the wiring XLS[i] Multiple wires may be used.

[0197] <<Circuit WLD>> The circuit WLD in Figure 12, as an example, uses the weight coefficients (first data) input from the circuit ILD. It may also be called the second data. Here, we will refer to it as the first data.) Information corresponding to (example) For example, it has a function to select the circuit MP to which the potential, resistance, current, etc., will be written. For example, circuits MP[i,1] to MP[i,n] located in the i-th row of the array ALP. When writing information (for example, potential, resistance, current, etc.) to the ], the WLD circuit will For example, the writing switching included in circuits MP[i,1] through MP[i,n] A signal to turn the element on or off is supplied to the wiring WLS[i], except for row i. The potential that turns off the writing switching element included in the circuit MP is connected to the wiring WLS. It is sufficient to supply it. Note that the example shown is for the case where wiring WLS[i] is present, but this invention... This is not limited to the above. In addition to the wiring WLS[i], for example, the wiring WLS[i] A separate wire may be provided to transmit an inverted signal of the signal input to the device. WLS[i] may be replaced with multiple wires. Note that circuit WLD and circuit XLD are It may be arranged as a separate circuit, but one aspect of the present invention is not limited thereto. Alternatively, circuit WLD may be an integrated circuit with circuit XLD.

[0198] <<Circuit AFP>> The circuit AFP in Figure 12, for example, can be used to connect circuits ACTF[1] to ACTF[n]. Circuits ACTF[1] to ACTF[n] are, for example, the above embodiment. The circuit ACTF[j] described above can be applied. This allows the circuit ACTF[1 Circuit ACTF[n], for example, receives input from wiring OL[j] and wiring OLB[j]. It is possible to generate signals corresponding to each piece of information (e.g., electric potential, current value, etc.). For example, the information input from wiring OL[j] and wiring OLB[j] is ( For example, it compares (potential, current value, etc.) and generates a signal according to the comparison result. is neuron N j (k) The signal z output from j(k) This corresponds to AC circuitry. TF[1] or the circuit ACTF[n] is, for example, the neural network described above. It functions as a circuit that performs calculations on the activation function.

[0199] <<Circuit MP>> Here, we will describe an example of the configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 130.

[0200] Figure 13A shows an example configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 130. Circuit MP[i,j] includes, for example, circuit MC and circuit MCr. And circuit MCr calculates the product of the first data and the second data in circuit MP. It is a path. Circuit MC may have the same configuration as circuit MCr, or a different configuration from circuit MCr. This is possible. Therefore, to distinguish the circuit MCr from the circuit MC, the sign "r" is added. Furthermore, the designation of the circuit elements included in the circuit MCr, which will be described later, is also given the letter "r". Yes, they are.

[0201] For example, a circuit MC has a retaining part HC, and a circuit MCr has a retaining part HCr. The retaining part HC and the retaining part HCr each contain information (e.g., potential, resistance, current, etc.). It has the function of holding the first data w set in circuit MP[i,j]. i (k -1) j (k) This refers to the information held in the retaining part HC and the retaining part HCr, respectively (for example) It is determined according to the potential, resistance, current, etc. Therefore, the holding part HC and the holding part H Each of Cr is the first data w i (k-1) j (k)Each piece of information corresponding to (for example, electric potential, Electrically connected to wiring OL[j] and wiring OLB[j] which supply resistance, current, etc. It is being done.

[0202] In Figure 13A, circuit MP[i,j] is connected to wiring VE[j] and wiring VEr[j], It is electrically connected to the wiring VE[j] and VEr[j]. It functions as a line. Also, wiring VE[j] can be connected to wiring OL via circuit MC, as an example. Current flows from there. Also, as an example, the wiring VEr[j] is connected via circuit MCr. Current flows from the OLB line.

[0203] The wiring WL[i] shown in Figure 13A corresponds to the wiring WLS[i] in Figure 12. The wire WL[i] is electrically connected to the holding part HC and the holding part HCr, respectively. The first data w is included in the retaining part HC and retaining part HCr in the path MP[i,j]. i (k-1) j (k) When writing information corresponding to the wiring WL (e.g., potential, resistance, current), By supplying a predetermined potential to [i], conductivity is established between the wiring OL[j] and the retaining part HC. Set the wiring to this state, and ensure electrical conductivity between the wiring OLB[j] and the retaining part HCr. Then, the wiring The first data w is assigned to each of IL[j] and ILB[j]. i (k-1) j (k) The corresponding electric potential By supplying such substances, the holding part HC and the holding part HCr are each supplied with the corresponding potential. This can be input. Then, a predetermined potential is supplied to the wiring WL[i], and the wiring IL[ The connection between [j] and the retaining part HC is made non-conductive, and the connection between the wiring ILB[j] and the retaining part HCr The first data w is set to a non-conductive state. Then, the first data w is set to the holding part HC and the holding part HCr respectively. i (k-1) j (k) Each corresponding current is maintained.

[0204] For example, the first data w i (k-1) j (k) The three values ​​are "-1", "0", and "1". Let's consider the case where we choose either one. First data w i (k-1) j (k) If it is "1", here is an example As a result, a current corresponding to "1" flows from wiring IL[j] through circuit MC to wiring VE[j]. To that end, a predetermined potential is maintained in the holding part HC, and the wiring ILB[j] is connected to the circuit MC. The potential V0 is maintained in the holding part HCr so that no current flows through the wiring VEr[j] via r. It will be done. Also, the first data w i (k-1) j (k) If it is "-1", for example, The holding part H prevents current from flowing from wiring IL[j] through circuit MC to wiring VE[j]. The potential V0 is maintained at C, and the wiring VEr[ from wiring ILB[j] through circuit MCr A predetermined potential is maintained in the holding part HCr so that a current corresponding to "-1" flows through [j]. And then, the first data w i (k-1) j (k) If it is "0", as an example, wiring I To prevent current from flowing from L[j] through circuit MC to wiring VE[j], the holding part HC is electrically controlled. Position V0 is maintained, and power is supplied from wiring ILB[j] to wiring VEr[j] via circuit MCr. The potential V0 is maintained in the holding part HCr to prevent flow. The potential V0 will be described later. In the explanation of Figure 14A, this can be considered the potential supplied by the wiring VCN.

[0205] As another example, consider the first data w i (k-1) j (k) This is an analog value, specifically, Consider the cases where it takes a “negative analog value”, “0”, or “positive analog value”. (First Data) taw i (k-1) j (k) If it is a "positive analog value", as an example, wiring IL[ From [j], via circuit MC, an analog current corresponding to a "positive analog value" is supplied to the wiring VE[j]. As if flowing, a predetermined potential is maintained in the holding part HC, and the wiring ILB[j] is connected to circuit M To prevent current from flowing through Cr to the wiring VEr[j], the potential V0 is maintained in the holding part HCr. It is held. Also, the first data w i (k-1) j (k) If it is a “negative analog value”, As an example, to prevent current from flowing from wiring IL[j] through circuit MC to wiring VE[j] Furthermore, the holding part HC maintains a potential V0, and the wiring ILB[j] is transmitted via the circuit MCr. The holding part H is configured such that an analog current corresponding to a "negative analog value" flows through the wiring VEr[j]. A predetermined potential is maintained in Cr. And the first data w i (k-1) j (k) is “0” In that case, for example, if current flows from wiring IL[j] through circuit MC to wiring VE[j] To prevent flow, the potential V0 is maintained in the holding part HC, and the circuit MC is connected to the wiring ILB[j]. The potential V0 is maintained in the holding part HCr so that no current flows through the wiring VEr[j] via r. The potential V0 is, as in the previous example, the wiring VC, as will be explained in the description of Figure 14A later. This can be considered the potential supplied by N.

[0206] As another example, the circuit MC stores information (for example, potential, resistance value) in the holding part HC. , or current, voltage, etc., according to the current value, etc., wiring OL[j] or wiring OLB[j The circuit MCr has the function of outputting to one of the ], and the information held in the holding part HCr (for example) Current, voltage, etc. (such as potential, resistance, or current value) are measured in the wiring OL[j] or It has the function of outputting to the other side of the wiring OLB[j]. For example, the first potential is held in the holding part HC. If this is the case, the circuit MC will send the first power from wiring OL[j] or wiring OLB[j] to wiring VE. Assuming that a current with a current value is flowing and a second potential is maintained in the holding part HC, the circuit MC This is a circuit that allows a current with a second current value to flow from wiring OL[j] or wiring OLB[j] to wiring VE. Similarly, when the first potential is held in the holding part HCr, the circuit MCr is the wiring OL[ A current with a first current value is passed from [j] or wiring OLB[j] to wiring VEr, and the current is held. When a second potential is maintained in part HCr, circuit MCr is either wiring OL[j] or wiring OLB [j] is to supply a current with a second current value to the wiring VE. Note that the first current value and the second current value are... The magnitude of each current value is given by the first data w i (k-1) j (k) Determined by the value For example, the first current value may be greater than or less than the second current value. Yes. Furthermore, as an example, one of the first current value or the second current value is zero current, i.e., current value It may also be 0. Or, the current is the difference between the current with the first current value and the current with the second current value. The direction of flow may also differ.

[0207] In particular, for example, the first data w i (k-1) j (k) The values ​​are "-1", "0", and "1". If either of these is chosen, the circuit MC will be configured such that either the first current value or the second current value becomes zero. It is preferable to configure the circuit MCr. Note that the first data w i (k-1) j (k) ga Ana When taking a logarithmic value, for example, a "negative analog value", "0", or a "positive analog value" For example, the first current value or the second current value can also take analog values. Cut.

[0208] By the way, from wiring OL[j] or wiring OLB[j] (from wiring IL[j]), circuit M The current flowing through C to wiring VE[j] and the current flowing from wiring OL[j] or wiring OLB[j] ( The current flowing from line ILB[j] through circuit MCr to wiring VEr[j] is equal to the current flowing from line ILB[j] to wiring VEr[j]. In such cases, the characteristics of the transistor may vary due to factors such as the manufacturing process of the transistor. Therefore, the potential held in circuit MC and the potential held in circuit MCr are not equal. Sometimes this is not the case. One embodiment of the present invention is a semiconductor device in which the characteristics of the transistors vary. However, from wiring OL[j] or wiring OLB[j] (from wiring IL[j]), via circuit MC The amount of current flowing through wiring VE[j] is determined from wiring OL[j] or wiring OLB[j] (wiring (From ILB[j]) the amount of current flowing through the circuit MCr to the wiring VEr[j] is approximately equal to It may be possible to do so.

[0209] Furthermore, in this specification and other documents, the information held in the retaining part HC and the retaining part HCr (for example, Current or voltage (such as potential, resistance, or current value) is a positive current or electric current. It may be expressed as pressure, negative current or voltage, or zero current or zero current. It could be expressed as pressure, or a mixture of positive, negative, and zero values.

[0210] Wiring X1L[i] and wiring X2L[i] shown in Figure 13A are the same as wiring X in Figure 12. This corresponds to LS[i]. Note that the second data z is input to circuit MP[i,j]. i (k-1 ) For example, the potentials of wiring X1L[i] and wiring X2L[i] are... It is determined by the current, etc. Therefore, for example, in circuit MC and circuit MCr, wiring X1 The second data z is transmitted via L[i] and wiring X2L[i]. i (k-1) Each potential corresponding to the input To be empowered.

[0211] Circuit MC and circuit MCr are, for example, connected to wiring X1L[i] and wiring X2L[i]. Depending on the input potential or current, the wiring OL[j] and wiring OLB[j] are subjected to the first Data w i (k-1) j (k) and the second data z i (k-1) Current or electricity corresponding to the product of Outputs values ​​such as position. Specific examples include the output destination of current from circuit MC and circuit MCr. This is determined by the potentials of wiring X1L[i] and wiring X2L[i]. For example, circuit M C and circuit MCr are such that the current output from circuit MC is from wiring OL[j] or wiring OLB[ The current flows through one side of [j], and the current output from circuit MCr is either wire OL[j] or wire OLB[j]. The circuit configuration is such that it flows to the other side of ]. In other words, from circuit MC and circuit MCr Each output current flows through different wiring, not the same wiring. For example, from circuit MC and circuit MCr, wiring OL[j] or wiring OLB[j] In some cases, no current may flow even if there is a misalignment.

[0212] For example, the second data z i (k-1) The value is one of the three values: "-1", "0", or "1". Let's consider the case where, as an example, the second data z i (k-1) If it is "1", then circuit MP This creates a conductive state between circuit MC and wiring OL[j], and between circuit MCr and wiring OLB[j] The connection between them is made conductive. Also, as an example, the second data z i (k-1) is "-1" In this case, circuit MP creates a conductive state between circuit MC and wiring OLB[j], and circuit MCr and wiring The connection between line OL[j] and the other line is made conductive. Also, as an example, the second data z i (k-1) but If "0", the current output by circuit MC and MCr respectively is used for wiring OL[j] and To prevent current from flowing through either of the OLB[j] circuits, circuit MP is connected to circuit MC and wiring The connection between OL[j] and the circuit MC and the wiring OLB[j] is made non-conductive, and the circuit M The connection between Cr and wiring OL[j], and between circuit MC and wiring OLB[j], is made non-conductive. do.

[0213] An example of combining the above actions is shown below. Data 1 w i (k-1) j (k) is "1" In this case, the wiring OL[j] or wiring OLB[j] is routed through circuit MC to wiring VE[j]. Current may flow through the circuit MCr, via the wiring OL[j] or wiring OLB[j] No current flows from the wiring VEr[j]. First data w i (k-1) j (k) is "-1" In this case, the wiring OL[j] or wiring OLB[j] is routed through circuit MC to wiring VE[j]. No current flows through ], and wiring is connected from wiring OL[j] or wiring OLB[j] via circuit MCr. Current may flow through VEr[j]. And the second data z i (k-1) is "1" In this case, between circuit MC and wiring OL[j], and between circuit MCr and wiring OLB[j] The area between them becomes conductive. Second data z i (k-1) If it is "-1", then the circuit MC and distribution Conduction occurs between the line OLB[j] and the circuit MCr and the wiring OL[j]. Based on the above, the first data w i (k-1) j (k) and the second data z i (k-1) The product of If the value is positive, current flows from wiring OL[j] to wiring VE[j] via circuit MCr. Or, current flows from wiring OL[j] to wiring VEr[j] via circuit MCr. On the other hand, this is the case. First data w i (k-1) j (k) and the second data z i (k-1) The product of is negative In the case of the value, current flows from wiring OL[j] to wiring VEr[j] via circuit MCr. Alternatively, current flows from wiring OLB[j] to wiring VE[j] via circuit MC. This is the result. First data w i (k-1) j (k) and the second data z i (k-1) The product of the two values ​​is zero. In this case, no current flows from wiring OL[j] or wiring OLB[j] to wiring VE[j]. No current flows from wiring OL[j] or wiring OLB[j] to wiring VEr[j].

[0214] To illustrate the above example with a concrete example, the first data w i (k-1) j (k) is “1” There is, the second data z i (k-1) If it is "1", for example, from circuit MC to wiring OL A current I1[i, j] with a first current value flows through [j], and the circuit MCr is connected to the OLB[j]. A current I2[i,j] with a second current value flows through it. At this time, the magnitude of the second current value is one For example, consider the case where the value is zero, meaning no current flows from the circuit MCr to the wiring OLB[j]. It is possible. First data w i (k-1) j (k) The second data z is "-1", and i (k-1) If it is "1", for example, the second current value is sent from circuit MC to wiring OL[j]. A current I1[i,j] flows, and a first current value is transmitted from the circuit MCr to the wiring OLB[j]. A current I2[i, j] flows. In this case, the magnitude of the second current value is, for example, zero. Furthermore, it can be assumed that no current flows from the circuit MC to the wiring OL[j]. Day 1 Ta lol i (k-1) j (k) The second data z is "0". i(k-1) is "1" In this case, a current I1[i,j] with a second current value flows from the circuit MC to the wiring OL[j], and the circuit A current I2[i,j] with a second current value flows from MCr to the wiring OLB[j]. The magnitude of the second current value is, for example, zero, that is, from circuit MC to wiring OL[j] Assuming no current flows, and that no current flows from circuit MCr to wiring OLB[j] It is possible.

[0215] Also, the first data w i (k-1) j (k) The second data z is "1", i (k-1 ) If it is "-1", then a current I1[ with the first current value is sent from the circuit MC to the wiring OLB[j] Currents i and j flow, and a second current I2[i, j] with a second current value is drawn from circuit MCr to wiring OL[j]. A current flows. At this time, the magnitude of the second current value is, for example, zero, that is, circuit MCr It can be assumed that no current flows from the wiring OL[j]. First data w i (k-1 ) j (k) The second data z is "-1", and i (k-1) If it is "-1", the circuit A current I1[i,j] with a second current value flows from MC to wiring OLB[j], and circuit MCr A current I2[i,j] with a first current value flows through the wiring OL[j]. At this time, the second current The magnitude of the value can be, for example, zero, meaning that current flows from circuit MC to wiring OLB[j]. It can be considered as something that cannot be done. First data w i (k-1) j (k) is "0", Data 2 z i (k-1) If it is "-1", then the second wire from circuit MC to OLB[j] A current I1[i, j] with a current value flows, and a second current value is transmitted from circuit MCr to wiring OL[j]. A current I2[i,j] flows. At this time, the magnitude of the second current value is, for example, ze (b) That is, no current flows from circuit MC to wiring OLB[j], and circuit MCr This allows for a configuration where no current flows through the wiring OL[j].

[0216] Also, the second data z i (k-1) If it is "0", one example is the circuit MC and wiring. The connection between OL[j] and the circuit MC and the wiring OLB[j] becomes non-conductive. Furthermore, between circuit MCr and wiring OL[j], and between circuit MCr and wiring OLB[j] It becomes non-conductive. Therefore, the first data w i (k-1) j (k) Whatever the value No current is output from circuits MC and MCr to wiring OL[j] and wiring OLB[j]. stomach.

[0217] Thus, as an example, the first data w i (k-1) j (k) and the second data z i (k -1) If the product of these two values ​​is positive, then either circuit MC or circuit MCr can be used. Current flows through wiring OL[j]. At this time, the first data w i (k-1) j (k) is a positive value In this case, current flows from circuit MC to wiring OL[j], and the first data w i(k-1) j ( k) If the value is negative, current flows from circuit MCr to wiring OL[j]. On the other hand, the first taw i (k-1) j (k) and the second data z i (k-1) When the product of these two values ​​takes a negative value In this case, current flows from either circuit MC or circuit MCr to wiring OLB[j]. At this time, the first data w i (k-1) j (k) If the value is positive, then the wiring O from circuit MC Current flows through LB[j], and the first data w i (k-1) j (k) If the value is negative, the circuit Current flows from MCr to wiring OLB[j]. Therefore, multiple connections to wiring OL[j] The sum of the currents output from the number of circuits MC or MCr flows through the wiring OL[j]. This means that in wiring OL[j], a current equal to the sum of positive values ​​flows. On the other hand, outputs are generated from multiple circuits MC or MCr connected to the wiring OLB[j]. The sum of the currents generated will flow through the wiring OLB[j]. In other words, wiring OLB[j] Then, a current will flow that is the sum of negative values. As a result of the above operation, The total current value flowing through wiring OL[j], that is, the sum of positive values, and the current flowing through wiring OLB[j] By using the total current value, that is, the sum of negative values, it is possible to perform a sum-of-accumulate operation. For example, the total current flowing through wiring OL[j] is greater than the total current flowing through wiring OLB[j]. If it is greater than the current value, we can conclude that the result of the sum-of-products operation will be a positive value. The total current flowing through wiring OL[j] is greater than the total current flowing through wiring OLB[j]. If the sum of the product is small, it can be determined that the result of the sum of products operation will be a negative value. The total current flowing through line OL[j] and the total current flowing through wiring OLB[j] are approximately the same value. In some cases, it can be determined that the result of the sum-of-products operation will be zero. If we consider that it also functions as an activation function, then the result of the sum-of-products operation will be negative. If it is determined that a value is to be taken, it may be output as a value of zero. That is, wiring OL[j] Only when the total current flowing through it and the total current flowing through the wiring OLB[j] are approximately the same value. Rather, the total current flowing through wiring OL[j] is greater than the total current flowing through wiring OLB[j]. Even if the sum of products is small, it is acceptable to conclude that the result of the sum of products operation will be zero.

[0218] Note that the second data z i (k-1) is one of the binary values ​​"-1", "0", or "1". For example, in the case of binary values ​​"-1" and "1", or in the case of binary values ​​"0" and "1", the same applies. It can be made to work in this way. Similarly, the first data w i (k-1) j (k) is "-1", If the binary value is either "0" or "1", for example, "-1" and "1", Alternatively, the same operation can be performed for binary values, "0" and "1".

[0219] Note that the first data w i (k-1) j (k) This refers to analog values, or multi-bit (multi-level) values. It may also take a digital value. For example, instead of "-1", you can use "negative analog". The value can be ", and a "positive analog value" can be taken instead of "1". In this case, circuit M The magnitude of the current flowing from C or circuit MCr is also, as an example, the first data w i (k-1 ) j (k) The value will be an analog value corresponding to the absolute value of the value.

[0220] Next, we will explain an example of a modified circuit MP[i,j] in Figure 13A. Note that circuit M Regarding the modified form of P[i,j], we will mainly explain the differences from the circuit MP[i,j] in Figure 13A. Therefore, we will omit the explanation of the parts that are common with the circuit MP[i,j] in Figure 13A. ru.

[0221] The circuit MP[i,j] shown in Figure 13B is the same as the circuit MP[i,j] in Figure 13A, with wiring The configuration combines IL[i] and wiring ILB[i] into wiring IL[j].

[0222] The wiring W1L[i] and W2L[i] shown in Figure 13B correspond to the wiring WLS[i] in Figure 12. This corresponds to ]. Wiring W1L[i] is electrically connected to the retaining part HC, and wiring W2L[i] is It is electrically connected to the holding part HCr.

[0223] Furthermore, the wiring IL[j] is electrically connected to the retaining part HC and the retaining part HCr. .

[0224] In the circuit MP[i,j] of Figure 13B, the holding part HC and the holding part HCr are different. When storing information (for example, voltage, resistance, current, etc.), the holding part HC and the holding part HCr The information retention operations should preferably be performed sequentially rather than simultaneously. For example, circuit MP[i, j]'s first data w i (k-1)j (k) The first information is in the retaining part HC, and the retaining part HCr is Let's consider the case where it can be represented by holding a second piece of information. First, wiring W1L[i] And a predetermined potential is applied to each of the wirings W2L[i], and the holding part HC and the wiring IL[j] The connection between them is made conductive, and the connection between the holding part HCr and the wiring IL[j] is made non-conductive. By supplying current, voltage, etc., corresponding to the first information to the wiring IL[j], the holding part HC The first piece of information can be provided. After that, the wiring W1L[i] and wiring W2L[i] By applying a predetermined potential to each, the connection between the holding part HC and the wiring IL[j] becomes non-conductive. Furthermore, electrical conductivity is established between the retaining part HCr and the wiring IL[j]. Then, wiring IL[j] By supplying current, voltage, etc., according to the second piece of information, the holding part HCr is given the second piece of information. This allows the circuit MP[i,j] to use w as the first data. i (k-1) j (k) You can set this.

[0225] Furthermore, the retaining part HC and the retaining part HCr each hold approximately equal amounts of information (for example, voltage, When dealing with resistance, current, etc. (the first data w of circuit MP[i,j]) i (k-1) j (k) However, this is achieved by holding approximately equal amounts of information in the holding part HC and the holding part HCr. (If this occurs), the holding part HC and the wiring IL[j] are made electrically conductive, and the holding part HCr and Wirings W1L[i] and W2L[i] are connected to wiring IL[j]. A predetermined potential is applied to each of them, and then the retaining part HC and retaining part H from the wiring IL[j]. You should supply the appropriate current, voltage, etc., to Cr according to that information.

[0226] The circuit MP[i,j] in Figure 13B has a holding part HC and a holding part HCr with the first data w i (k- 1) j (k) Maintain the potential corresponding to the second data z i (k-1) Wiring X1 to determine the appropriate potential By supplying L[i] and wiring X2L[i], the circuit MP[i,j] in Figure 13A Similarly, the first data w is set for wiring OL[j] and wiring OLB[j]. i (k-1) j (k) and the second data z i (k-1) It can output a current corresponding to the product of the two factors.

[0227] The circuit MP[i,j] shown in Figure 13C is a modified version of the circuit MP[i,j] in Figure 13A. The circuit MP[i,j] in Figure 13C is the same as the circuit MP[i,j] in Figure 13A, and the circuit MC It has circuit MCr and, however, circuit MP[i,j] in Figure 13C and circuit M in Figure 13A. P[i,j] has a different configuration of electrically connected wiring.

[0228] Specifically, circuit MP[i,j] in Figure 13C is the same as circuit MP[i,j] in Figure 13A. Therefore, wiring OL[j] and circuit MCr are not electrically connected, and wiring OLB[j] The circuit MC is not electrically connected to the MC. Therefore, Figure 13C The circuit MP[i,j] in Figure 13A has wiring X1L[i] and The configuration is such that wiring X2L[i] is replaced with wiring XL[i]. Note that wiring XL[ i) corresponds to the wiring XLS[i] in Figure 12, and is connected to circuit MC and circuit MCr, and electrical They are directly connected.

[0229] In Figure 13C, circuit MP[i,j] is electrically connected to wiring OL[j] and circuit MCr. Furthermore, because the wiring OLB[j] and circuit MC are not electrically connected, the input to circuit MP The second data (the value of the neuron's signal) is different from the circuit MP[i,j] in Figure 13A. There is a match. For example, when a high-level potential is applied to wiring XL, the second data (new When the value of Ron's signal is set to "+1" and a low-level potential is applied to wiring XL, the second The data (the value of the neuron's signal) can be set to "0".

[0230] The circuit MP[i,j] shown in Figure 13D is similar to Figure 13A, with wiring OL[j] and wiring O LB[j] contains the first data w i (k-1) j (k) and the second data z i (k-1) The product of This is a circuit capable of outputting a corresponding current. Note that the circuit MP[i,j] in Figure 13D is For example, it can be applied to the arithmetic circuit 130 in Figure 12.

[0231] The circuit MP[i,j] in Figure 13D consists of the circuit MC and the circuit MCr, in addition to the transistor It has a TaMZ.

[0232] The first terminal of transistor MZ is connected to the first terminal of circuit MC and the first terminal of circuit MCr. They are electrically connected. The second terminal of transistor MZ is electrically connected to wiring VL. The gate of transistor MZ is electrically connected to wiring XL[i].

[0233] Wiring VL is, for example, the wiring VE[j] shown in Figures 13A to 13C, and wiring Similar to VEr[j], it functions as a wire that provides a constant voltage. This constant voltage is applied to the circuit MP[ It is preferable to determine this by the configuration of i,j and the arithmetic circuit 130. For example, this includes VDD, which is a high-level potential, VSS, which is a low-level potential, and the ground potential. It is possible.

[0234] Furthermore, the wiring WL[i] shown in Figure 13D corresponds to the wiring WL in the calculation circuit 130 in Figure 12. This corresponds to S[i]. The wiring WL[i] is electrically connected to the retaining part HC and the retaining part HCr. It continues.

[0235] Furthermore, wiring OL[j] is electrically connected to the second terminal of circuit MC. OLB[j] is electrically connected to the second terminal of circuit MCr.

[0236] Furthermore, wiring IL[j] is electrically connected to the retaining part HC, and wiring ILB[j] is a retaining part. It is electrically connected to part HCr.

[0237] In the circuit MP[i,j] of Figure 13D, the first retaining part HC and retaining part HCr are each For the operation when maintaining a potential according to the data, see the circuit MP[i,j] in Figure 13A. Refer to the explanation of the operation that maintains the potential corresponding to the first data.

[0238] In circuit MP[i,j] in Figure 13D, circuit MC is connected to the first terminal of circuit MC via wiring VL. When a constant voltage is supplied, the current corresponding to the potential held in the holding part HC is supplied. It has the function of flowing between the first and second terminals of circuit MC. Also, circuit MCr is circuit M When a constant voltage is supplied to the first terminal of C by the wiring VL, the holding part HCr is held It has the function of flowing a current corresponding to the potential between the first and second terminals of the circuit MCr. In other words, the first data w is assigned to the holding part HC and the holding part HCr of the circuit MP[i,j]. i ( k-1) j (k) By maintaining a potential corresponding to the first and second terminals of the circuit MC, The amount of current flowing between and the first and second terminals of the circuit MCr is determined. This is possible. Furthermore, the constant voltage supplied by the wiring VL to the first terminal of circuit MC (circuit MCr) is If not supplied, the circuit MC (circuit MCr) is, for example, the circuit MC (circuit MCr) It is also possible to avoid passing current between the first and second terminals.

[0239] For example, the first data w is "1" for each of the retaining part HC and retaining part HCr. i (k-1) j (k) When the corresponding potential is maintained, the constant voltage supplied by the wiring VL is applied to the circuit MC. By doing so, the circuit MC flows a predetermined current between the first and second terminals of the circuit MC. Therefore, current flows between circuit MC and wiring OL. At this time, circuit MCr The circuit assumes that no current flows between the first and second terminals of the MCr. Therefore, the circuit No current flows between the MCr and the wiring OLB. Also, for example, the retaining part HC, retaining part HC The first data w is "-1" for each of r i (k-1) j (k) A corresponding potential is maintained. When a constant voltage is applied to the circuit MC by the wiring VL, the circuit MCr A predetermined current is passed between the first and second terminals of the circuit MCr. Therefore, the circuit MCr and Current flows between the wiring OLB. At this time, the circuit MC is connected to the first terminal of the circuit MC and the second terminal. No current is to flow between the two terminals. Therefore, no current flows between the circuit MC and the wiring OL. The flow does not flow. Also, for example, the first day of the holding part HC and the holding part HCr is "0". Ta lol i (k-1) j (k) When the corresponding potential is maintained, circuit MC and circuit MCr Regardless of whether a constant voltage is applied to the wiring VL, the circuit MC is connected to the first terminal of the circuit MC. No current flows between the first and second terminals of the circuit MCr. No current flows. In other words, no current flows between circuit MC and wiring OL, and between circuit MCr and wiring OL. No current flows between the line OLB and the circuit.

[0240] In addition, in the circuit MP[i,j] of Figure 13D, the holding part HC and the holding part HCr are held Ru, the first data w i (k-1) j (k) For specific examples of the potential corresponding to the turn, see Figure 10A. Refer to the description of circuit MP[i,j]. Also, in circuit MP[i,j] in Figure 13D, The holding part HC and the retaining part HCr, like the circuit MP[i,j] in Figure 10A, are currents, not potentials. It has a function to store information such as resistance values, and circuit MC and circuit MCr are powered according to that information. It may have a function to allow flow.

[0241] The wiring XL[i] shown in Figure 13D corresponds to the wiring XLS[i] in the calculation circuit 130 in Figure 12. This corresponds to ]. Note that the second data z input to circuit MP[i,j] i (k-1) is, For example, it is determined by the potential, current, etc. of the wiring XL[i]. Therefore, for the gate of the transistor MZ, for example, the second data z is input with a corresponding potential through the wiring XL[i]. i (k-1) to

[0242] For example, consider the case where the second data z i (k-1) takes either of the two values "0" or "1". For example, when the second data z is "1", assume that a high-level potential is applied to the wiring XL[i]. At this time, since the transistor MZ is in the on state, i (k-1) the circuit MP conducts between the wiring VL and the first terminal of the circuit MC, and conducts between the wiring VL and the first terminal of the circuit MCr. That is, when the second data z is "1", a constant voltage from the wiring VL is applied to the circuit MC and the circuit MCr. Also, for example, when the second data z is "0", assume that a low-level potential is applied to the wiring XL[i]. At this time, the circuit MP makes the circuit MC and the wiring OLB[j] non-conductive, and makes the circuit MCr and the wiring OL[j] non-conductive. That is, when the second data z i (k-1) is "0", no constant voltage from the wiring VL is applied to the circuit MC and the circuit MCr. For example, i (k-1) when the second data z is "0", the circuit MP makes the circuit MC and the wiring OLB[j] non-conductive, and makes the circuit MCr and the wiring OL[j] non-conductive. That is, when the second data z is "0", i (k-1) no constant voltage from the wiring VL is applied to the circuit MC and the circuit MCr.

[0243] Here, for example, when the first data w i (k-1) j (k) is "1" and the second data z i (k-1) ​​If it is "1", current flows between circuit MC and wiring OL, and circuit MC As a result, no current flows between r and the OLB wiring. Also, for example, the first data w i ( k-1) j (k) The second data z is "-1", and i (k-1) If it is "1", No current flows between circuit MC and wiring OL, and no current flows between circuit MCr and wiring OLB. The result will be a flow. Also, for example, the first data w i (k-1) j (k) is "0" , second data z i (k-1) If it is "1", then between circuit MC and wiring OL, and the circuit As a result, no current flows between the MCr and the OLB wiring. Also, for example, the second data z i (k-1) If it is "0", then the first data w i (k-1) j (k) is "-1", "0 Whether it is "" or "1", the connection between circuit MC and wiring OL, and between circuit MCr and wiring O As a result, no current flows between LB and the circuit board.

[0244] In other words, the circuit MP[i,j] in Figure 13D is similar to the circuit MP[i,j] in Figure 13C. For example, the first data w i (k-1) j (k) The three values ​​are "-1", "0", and "1". Take the difference and the second data z i (k-1) When it takes two values, "0" and "1", It can perform calculations. Also, similar to the circuit MP[i,j] in Figure 13C, the circuit in Figure 13D The path MP[i,j] is the first data w i (k-1) j (k) The values ​​are "-1", "0", and "1". In our case, either of the two values, for example, "-1" and "1", or "0" and "1" It can also be operated in the case of the binary value ". Note that the first data w i (k-1) j (k) This can take the form of an analog value or a multi-bit (multi-level) digital value. Specific examples and Therefore, instead of "-1", use a "negative analog value", and instead of "1", use a "positive analog value". You may also take the logarithmic value. In this case, it represents the magnitude of the current flowing from circuit MC or circuit MCr. For example, the first data w i (k-1) j (k) Analog value corresponding to the absolute value of the value This is the result.

[0245] <<Circuit ILD>> Circuit ILD is, for example, a wiring IL[1] through wiring IL[n] and wiring ILB[1] Through the wiring ILB[n], the same of circuit MP[1,1] to circuit MP[m,n] For each of these, the weight coefficient is the first data w1 (k-1) 1 (k) Or maybe lol m (k-1) n (k) It has a function to input corresponding information (e.g., electric potential, resistance value, current value, etc.). As a specific example, circuit ILD has a first weighting coefficient for circuit MP[i,j] Data w i (k-1) j (k) Corresponding information (e.g., electric potential, resistance, or current value) These are supplied via wiring IL[j] and wiring ILB[j].

[0246] Figure 14A shows an example of a circuit configuration for an ILD circuit that can be applied to the arithmetic circuit 130. Figure 14A illustrates the electrical connection between the ILD circuit and the ALP array section. Line OL[j] and wiring OLB[j] are also shown. Circuit ILD is connected to the current source circuit ISC. Switch SWIA, Switch SWIAB, Switch SWLA, Switch SWLA B has, and the wiring OL[j] is connected to the first terminal of switch SWIA and switch SWLA The first terminal of is electrically connected to and . Wiring OLB[j] is connected to switch SWIAB The first terminal is electrically connected to the first terminal of the switch SWLAB. Current source circuit ISC connects the second terminal of switch SWIA and the second terminal of switch SWIAB to electrical It is connected to the second terminal of switch SWLA and switch SWLAB. It is electrically connected to the second terminal of and .

[0247] The current source circuit ISC has, for example, one or more constant current sources, as shown in Figure 14A. As an example, consider multiple constant current sources, such as constant current source circuit ISC1 and constant current source circuit ISC2. It has a constant current source circuit ISC3. Furthermore, the current source circuit ISC may, for example, have multiple To select a constant current source, there are multiple switches, and in Figure 14A, there are multiple switches. The system includes switches SWC1, SWC2, and SWC3. Furthermore, if the current source circuit ISC has only one constant current source, the current source circuit ISC is a switch It is not necessary to have a constant current source circuit ISC1, a constant current source circuit ISC2, and When the current source circuit ISC3 and each have a function to control whether or not they output current. Switches SWC1, SWC2, and SWC3 are not provided. That's good too.

[0248] By the way, in any one of the circuits MP[1,j] to MP[m,j], the first data ( To maintain the weight coefficients, flow occurs in each of the wirings OL[j] and OLB[j]. The current is preferably generated by the same current source circuit ISC, as shown in Figure 14A. The current flowing through wiring OL[j] and wiring OLB[j] is generated by different current source circuits. In some cases, variations in the characteristics of the transistor caused by the manufacturing process of the transistor may occur. Because this can occur, differences in performance may appear between different current source circuits. On the other hand, When using the same current source circuit, the same large current is used for both wiring OL[j] and wiring OLB[j]. This allows for the passage of a larger current, thereby improving calculation accuracy.

[0249] Note that the switches SWIA, SWIAB, and SWLA are explained in Figure 14A. Switch SWLAB, Switch SWC1, Switch SWC2, Switch SWC3 For example, the aforementioned switches SWR1, SWR1B, and SW A switch that is applicable in the same way as R2 and switch SWR2B can be used.

[0250] Figures 14B and 14B show specific configuration examples of constant current source circuits ISC1 to ISC3. Figure 14C shows the constant current source circuit ISC1 (constant current source circuit ISC2, constant current source) shown in Figure 14B. Circuit ISC3) has a transistor PTr which is a p-channel type transistor. The first terminal of transistor PTr is electrically connected to the wiring VSO, and the second terminal of transistor PTr The terminal is electrically connected to the second terminal of switch SWC1 (switch SWC2, switch SWC3). It is connected to the gate of transistor PTr, and is electrically connected to the wiring VB. Figure 14C shows constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) ) has an n-channel transistor NTr, and the first of the transistor NTr Terminal 1 is electrically connected to wiring VSO, and terminal 2 of transistor NTr is a switch. Electrically connected to the second terminal of SWC1 (switch SWC2, switch SWC3), The gate of the inverter NTr is electrically connected to wiring VB. (Figures 14B and 14C) Each of the constant current source circuits ISC1 (constant current source circuits ISC2, constant current source circuits ISC3) In this configuration, wiring VB is used to input a bias voltage to the gate of each transistor. It functions as a wire. A pulse signal may also be supplied to the wire VB. This allows it to function as a wire. It is possible to control whether or not to output current from each constant current source circuit. In that case, Switches SWC1, SWC2, and SWC3 do not need to be provided. The analog voltage may be supplied to the wiring VB. This allows the constant current source circuit to supply an analog voltage. It can supply log current.

[0251] Wiring VSO is connected to each of the constant current source circuits ISC1 through ISC3. It functions as wiring that supplies a constant voltage. For example, from circuit ILD (wiring VSO) to wiring O When current flows through L or the OLB wiring, the constant voltage is a potential higher than the ground potential. For example, it is preferable to use VDD, and furthermore, the constant current source circuit ISC1 shown in Figure 14B It is preferable to use constant current source circuits (ISC2 and ISC3). Also, for example, When current flows from wiring OL or wiring OLB to circuit ILD (wiring VSO), the current In terms of voltage, a potential higher than the ground potential and lower than the high-level potential, the ground potential, and a negative potential. It is preferable to do the above, and furthermore, the constant current source circuit ISC1 (constant current source circuit I shown in Figure 14C) It is preferable to use SC2 and the constant current source circuit ISC3. The current flowing from circuit ILD to wiring OL or wiring OLB is sometimes described as a positive current. Therefore, the current flowing from wiring OL or wiring OLB to circuit ILD is described as a negative current. There are cases where this is the case.

[0252] By the way, the current that the constant current source circuit ISC1 supplies is I ut In that case, one example is constant power The current supplied by the current source circuit ISC2 is 2I. ut It is preferable that the constant current source circuit ISC3 flows The current is 4I ut It is preferable to have P current source circuits (ISC) (where P is 1 or more). If there is a constant current source of an integer (where p is an integer between 1 and P), then the p-th element (where p is an integer between 1 and P) The current supplied by the constant current source is 2 (p-1) ×I ut It is preferable to do so. In other words, switch By switching each of SWC1 through SWC3, etc., between the ON and OFF states, This allows you to change the magnitude of the current flowing from the current source circuit (ISC).

[0253] For example, let's assume the current source circuit ISC has 3 constant current sources (P=3). Wiring OL[j] I ut If you want to supply current, turn switch SWIA to ON, and switch SWIAB to After turning it off, turn on switch SWC1 and turn off switch SWC2 and switch SWC3. Also, if you want to pass a current of 5I through wiring OL[j], ut then turn on switches SWC1 and SWC3 and turn off switch SWC2. That is, the amount of current output from current source circuit ISC can be one of eight values (“0”, “I”, “2I”, “3I”, “4I”, “5I”, “6I”, “7I”). If you want to output a current with a value greater than the eight values, you can increase the number ut of constant current sources to four or more. Similarly, by turning off switch ut SWIA and turning on switch SWIAB, you can pass one of the eight values of ut current through wiring OLB[j]. If current source circuit ISC does not output ut current, you may leave switches SWC1 to SWC3 of current source circuit ISC ut on and turn off switches SWIA and SWIAB. By arranging a plurality of u t constant current sources in this way, a circuit that can generate a current ut with a multi-valued current amount can be easily realized. Note that you can also arrange only one current source circuit and operate it to change the output current value analogously. Wiring VCN functions as a wiring that supplies a constant voltage to wiring OL[j] and / or wiring OLB[j]. For example, when a current (positive current) flows from circuit ILD to wiring OL or wiring OLB, the constant voltage provided by wiring VCN is a low-level potential (e.g., VSS). By arranging a plurality of constant current sources in this way, a circuit that can generate a current with a multi-valued current amount can be easily

[0254] realized. Note that you can also arrange only one current source circuit and operate it to change the output current value analogously. For example, when a current (positive current) flows from circuit ILD to It is preferable to do the following: For example, from wiring OL or wiring OLB, circuit ILD When current (negative current) flows through it, the constant potential provided by the wiring VCN is the high-level potential and It is preferable to do so. Furthermore, as shown in Figures 20A to 20C, 21A, 21B, etc., described later. As such, capacitance C1 is electrically connected to the source terminal of transistor M1, and its source If the terminal is connected to a power line, etc., from circuit ILD, wiring OL or wiring OL When a positive current flows through B, the constant voltage supplied by the wiring VCN is the low-level potential (for example). It is preferable to use VSS, etc. In other words, when supplying a constant voltage from the wiring VCN, It is desirable to make the potential difference across the capacitor C1 close to zero. In other words, From the circuit MC, the potential at which current is no longer output is approximately the same as the potential supplied by the wiring VE. It is desirable to supply equal potential to the wiring VCN.

[0255] Here, we will explain the first data (weight coefficient) input to the circuit MP.

[0256] When you want to input a positive first data to circuit MP, the wiring OL[j] is configured according to that first data. Simply input the current and input the constant potential supplied by the wiring VCN to the wiring OLB[j]. Example This involves creating a conductive state between the current source circuit ISC and the wiring OL[j], and the current source circuit ISC The connection between the wiring OLB[j] is made non-conductive, and the connection between the wiring VCN and the wiring OL[j] is made non-conductive. To achieve this, the circuit should be made conductive between wiring VCN and wiring OLB[j]. Switch SWIA and switch SWLAB are turned ON, and switch SWIAB, Simply turn off each of the switches SWLA. This will allow the current source circuit ISC and Since there is conductivity between the wiring OL[j] and the current source circuit ISC, the wiring OL[j] Current can be supplied to circuit MP through this. By the way, the constant current source of the current source circuit ISC When the number of items is P, the current is 2 P It will be one of the following values ​​(excluding zero current) i) The positive weighting coefficient input to circuit MP is determined according to the current, therefore the weighting coefficient is 2 P It can be any one of the values ​​of -1. Also, wiring VCN and wiring OLB[j] Since the space between them becomes conductive, a constant voltage from the wiring VCN is input to the wiring OLB[j]. ru.

[0257] Furthermore, when you want to input a negative first data to circuit MP, input the first data to wiring OLB[j]. Simply input the current corresponding to the terminal, and input the constant potential supplied by wiring VCN to wiring OL[j]. One example is to make the connection between the current source circuit ISC and the wiring OL[j] non-conductive, and the current source circuit The circuit ISC and wiring OLB[j] are made conductive, and the wiring VCN and wiring OL[j] To do this, you should make the circuit conductive and the circuit between wiring VCN and wiring OLB[j] non-conductive. Next, turn on switches SWIA and SWLA, and switch SWIA and SW Simply turn off each of the LABs. This will allow the current source circuit ISC and the wiring OLB to function correctly. Since there is conductivity between [j] and the current source circuit ISC, current flows from the circuit via the wiring OLB[j]. This allows current to flow through circuit MP. By the way, the number of constant current sources in the current source circuit ISC When there are P units, the current is 2 P The value will be one of the following -1 values ​​(excluding zero current). The negative weighting coefficient input to circuit MP is determined according to the current, so the weighting coefficient is 2 P It can be any of the -1 values. Also, the connection between wiring VCN and wiring OL[j] is Since the circuit is open, a constant voltage from wiring VCN is input to wiring OL[j].

[0258] Also, when you want to input the first data of 0 to circuit MP, use wiring OL[j], wiring OLB[j For each of the ], you just need to input the constant potential supplied by the wiring VCN. One example is a current source circuit. The connection between ISC and wiring OL[j] is made non-conductive, and the current source circuit ISC and wiring OLB[j] The connection between them is made non-conductive, and the connection between wiring VCN and wiring OL[j] is made conductive, wiring VC The connection between N and the wiring OLB[j] should be made conductive. That is, switch SWLA, Turn on switch SWLAB, and then turn on switch SWIA and switch SWIAB respectively. It should be set to the OFF state. This will create a conductive state between wiring VCN and wiring OL[j]. Therefore, since there is conductivity between wiring VCN and wiring OLB[j], wiring OL[j], wiring A constant voltage from the wiring VCN is input to OLB[j].

[0259] In other words, by setting the number of constant current sources in the current source circuit ISC to P, the current enters the circuit MP. The number of possible weighting coefficients (the sum of positive weighting coefficients, negative weighting coefficients, and zero weighting coefficients) is 2. P+ 1 -1 item.

[0260] In addition, the above description explained that the ILD circuit has a configuration that includes a current source circuit ISC. One aspect of the present invention is not limited thereto. For example, without a current source circuit ISC, A voltage source circuit may be placed in between. Also, for example, the current source circuit ISC is connected to the wiring OL[j The circuit for ] and the circuit for the wiring OLB[j] are treated as separate circuits. They may be arranged one by one. Also, for example, as shown in Figure 14A, wiring For a set of wirings called OL[j] and wiring OLB[j], at least one electrical It may have a current source circuit ISC. Note that the circuit ILD is a separate circuit from the circuit AFP. While they may be arranged in this manner, one aspect of the present invention is not limited thereto. For example, circuit ILD This may be an integrated circuit with the AFP circuit.

[0261] <Example of operation of the arithmetic circuit> Next, we will explain an example of the operation of the arithmetic circuit 130 in Figure 12. As an example, the arithmetic circuit 130A shown in Figure 15 is used.

[0262] The calculation circuit 130A shown in Figure 15 is the same as the calculation circuit 130 in Figure 12, but with the circuit ACT shown in Figure 8 added. This is a diagram showing the application of F[j], and also the circuit located in the j-th column of the arithmetic circuit 130 in Figure 12. This is a diagram illustrating the focus. Therefore, the arithmetic circuit 130A in Figure 15 is the same as the one shown in Figure 1A. In neural network 100, Neuron N j (k) The neuron is input to the N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k -1) (This may be referred to as Data 1 or Data 2. Here, we will refer to it as Data 2.) ) and the weight coefficient w1 (k-1) j (k) Or maybe lol m (k-1) j (k) (First data or This is sometimes referred to as the second data. Here, it will be referred to as the first data.) and the sum-of-products operation This corresponds to a circuit that performs the calculation of an activation function using the result of the sum-of-products operation.

[0263] Furthermore, the circuit MP included in the array section ALP of the arithmetic circuit 130A in Figure 15 is shown in Figure 13 Circuit MP is applied to A, and wiring WLS[1] to wiring WLS[m] is used as wiring WL[ The diagram shows wiring X[1] to wiring WL[m], and wiring X[1] to wiring XLS[m] is shown. The diagram shows 1L[1] or wiring X1L[m] and wiring X2L[1] or wiring X2L[m]. It is also included in circuit ACTF[j] of the arithmetic circuit 130A in Figure 15. The VTR and circuit IVTRr are as shown in Figure 6A, and the circuit IVTR (circuit IVTRr) is used. It is being applied.

[0264] First, in the arithmetic circuit 130A, the number of circuits MP[1,j] to MP[m,j] 1 data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) This is set. First data w i (k-1) j (k) The method of setting this up is by using the circuit WLD, and wiring WLS[1] A predetermined potential is applied sequentially to the wiring WLS[m], and the circuit MP[1,j] to the circuit MP[ Select [m,j] in order, and then select the circuit MC and circuit MCR included in the selected circuit MP. With respect to the holding part HC and holding part HCr, from the circuit ILD, wiring OL[j], wiring OLB[ Through [j], the potential, current, etc. corresponding to the first data are supplied. After supply, the circuit WLD controls each of the circuits MP[1,j] to MP[m,j] By deselecting it, each of circuits MP[1,j] to MP[m,j] has The first data w1 is applied to the holding part HC of the circuit MC and the holding part HCR of the circuit MCr. (k-1) j (k) Or maybe lol m (k-1) j (k) It can maintain the appropriate potential, current, etc. One example is the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) any of If the value is positive, the holding unit HC will be input with a value corresponding to that positive value. A value equivalent to zero is entered in the holding unit HCr. Meanwhile, the first data w1 (k-1) j ( k) Or maybe lol m (k-1) j (k) If any of the values ​​are negative, then the holding part H For C, enter a value equivalent to zero, and for the holding unit HCr, enter a value corresponding to the absolute value of the negative value. To exert force. Also, the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) any of Regarding this, if the value is 0, the holding unit HC will be input with a value equivalent to zero and will be held. Enter a value in section HCr that corresponds to the absolute value of zero.

[0265] Next, the circuit XLD will route the wiring X1L[1] to wiring X1L[m], wiring X2L[1 ] or each of the wiring X2L[m], second data z1 (k-1) ~z m(k-1) of To supply. As a specific example, the second data to wiring X1L[i] and wiring X2L[i] z1 (k-1) It will be supplied.

[0266] The second data z1 is input to each of the circuits MP[1,j] through MP[m,j]. ( k-1) ~z m (k-1) Depending on the circuit, the contents of circuit MP[1,j] to circuit MP[m,j] are included. The conductivity between the circuit MC, circuit MCr and the wiring OL[j] and wiring OLB[j] is determined. As a specific example, circuit MP[i,j] is second data z i (k-1) In response, The circuit MC and the wiring OL[j] become conductive, and the circuit MCr and the wiring OLB[j] There are two modes: one where the space between them becomes conductive, and another where the space between the circuit MC and the wiring OLB[j] becomes conductive. There are two modes: one where circuit MCr and wiring OL[j] become conductive, and another where circuit MC and circuit M Cr is in a non-conductive state with the wiring OL[j] and OLB[j] respectively, or either Take one. For example, the second data z1 (k-1) If it takes a positive value In wiring X1L[1], there is a conductive state between circuit MC and wiring OL[j], and the rotation Enter a value that allows conductivity between the circuit MCr and the wiring OLB[j]. In wiring X2L[1], the connection between circuit MC and wiring OLB[j] becomes non-conductive, Enter a value that allows the circuit MCr and the wiring OL[j] to become non-conductive. Then, the second data z1 (k-1) If it takes a negative value, then the wiring X1L[1] This means that there is conductivity between circuit MC and wiring OLB[j], and circuit MCr and wiring OL Enter a value that allows conductivity between [j] and [j]. Then, connect the wire X2L[1] This means that the circuit MC and the wiring OL[j] are in a non-conductive state, and the circuit MCr and wiring OL Input a value that will result in a non-conductive state between B[j] and the second data z1. (k-1) If it takes a value of zero, then the wiring X1L[1] is connected to the circuit MC and wiring The connection between OLB[j] and the circuit MCr is non-conductive, and the connection between the circuit MCr and the wiring OL[j] is non-conductive. Enter a value that allows for a conductive state. Then, the wiring X2L[1] has circuit MC and The connection between wiring OL[j] and the circuit MCr and wiring OLB[j] is non-conductive. Enter a value that will cause it to become non-conductive.

[0267] The second data z is input to circuit MP[i,j] i (k-1) Depending on the circuit MP[i, Continuity between circuits MC and MCr included in [j] and wiring OL[j] and wiring OLB[j] The state is determined by the circuit MC, circuit MCr and wiring OL[j], wiring OLB[j] Current input and output occur between them. Furthermore, the amount of this current is set in circuit MP[i,j]. The first data was i (k-1) j (k) and / or second data z i (k-1) Decision made accordingly circle.

[0268] For example, in circuit MP[i,j], from wiring OL[j], circuit MC or circuit MCr Let I[i,j] be the current flowing through it, and let the current flow from wiring OLB[j] to circuit MC or circuit MCr. The current is I B Let [i,j] be the points. Then, flow from circuit ACTF[j] to wiring OL[j]. The current is I out Let [j] be the current flowing from the wiring OLB[j] to the circuit ACTF[j]. to I Bout If we set it to [j], then I out [j] and I Bout [j] can be expressed by the following formula: It is possible.

[0269]

number

[0270] In circuit MP[i,j], as an example, the first data w i (k-1) j (k) is “+ When it is 1”, there is I(+ 1) When the current flows, I(-1) flows between circuit MCr and the other of wiring OL[j] or wiring OLB[j]. ) is assumed to flow, and the first data w i (k-1) j (k) When is "-1", circuit M I(-1) flows between C and either wiring OL[j] or wiring OLB[j], and circuit MCr Between the other of wiring OL[j] or wiring OLB[j], I(+1) flows, and 1 data w i (k-1) j (k) When it is "0", the circuit MC and wiring OL[j] or wiring I(-1) flows between one end of line OLB[j], and circuit MCr and wiring OL[j] or wiring Assume that I(-1) flows between the other OLB[j].

[0271] Furthermore, the circuit MP[i,j] is given by the second data z i (k-1) When it is "+1", The circuit MC and the wiring OL[j] become conductive, and the circuit MCr and the wiring OLB[j] The space between them becomes conductive, and the space between circuit MC and wiring OLB[j] becomes non-conductive, and circuit MC The configuration is such that there is no conductivity between r and wiring OL[j], and the second data z i (k-1) When it is "-1", the circuit MC and the wiring OLB[j] become conductive, and the circuit The circuit between MCr and wiring OL[j] becomes conductive, and the circuit between MC and wiring OL[j] becomes non-conductive. The configuration is such that when the circuit MCr and the wiring OLB[j] are in a conductive state, the connection between them becomes non-conductive. , second data z i (k-1) When it is "0", the interval between circuit MC and wiring OL[j] Furthermore, the circuit MC and OLB[j] become non-conductive, and the circuit MCr and wiring OL The configuration is such that there is no conduction between [j] and the circuit MCr and OLB[j]. It shall be taken.

[0272] At this time, in circuit MP[i,j], from wiring OL[j], circuit MC or circuit MC The current I[i,j] flowing through r and the current flowing from the wiring OLB[j] to circuit MC or circuit MCr Current I B [i,j] are as shown in the table below. Note that in some cases, I(- The circuit MP[i,j] may be configured such that the current in 1) becomes 0. Note that the current I[ i,j] may be the current flowing from circuit MC or circuit MCr to wiring OL[j]. Similarly, current I B [i,j] represents the flow from circuit MC or circuit MCr to wiring OLB[j]. Electric current is also acceptable.

[0273] [Table 1]

[0274] Then, circuit ACTF[j] flows, for example, through wiring OL[j] and wiring OLB[j]. I out [j] and I Bout It generates a voltage corresponding to each of [j]. Then, I o ut [j] Voltage and I Bout Depending on the voltage difference corresponding to [j], neuron N j (k) The signal z that is sent to the (k+1)th layer neuron j (k) Outputs.

[0275] The operation of the ACTF[j] circuit is as shown in the calculation circuit 110A in Figure 8 of Embodiment 1. Refer to the explanation of the example operation.

[0276] <Example of arithmetic circuit configuration 2> Furthermore, the calculation circuit 130A shown in Figure 15 is I Bout I out [j] is large In case of (u j (k) (If the signal z is positive), then the circuit AC has a positive value. j (k) of Output, I out I Bout If [j] is large (u j (k) In a negative field In combination, the AC circuit outputs a digital signal of 0 z. j (k) The configuration will output However, the present invention is not limited thereto. For example, the arithmetic circuit 130A is I out I Bout If [j] is large (u j (k) If (is negative), then The path AC is a negative value for the output signal z. j (k) You may change the configuration to output the following:

[0277] An example of such an arithmetic circuit is shown in Figure 16. The arithmetic circuit 140 shown in Figure 16 is the same as the one in Figure 15. The configuration is a modified version of circuit ACTF[j] included in circuit AFP of calculation circuit 130A. Furthermore, the circuit configuration of the arithmetic circuit 140 is also an example of the arithmetic circuit 120 shown in Figure 4A. The circuit ACTF[j] consists of switch SWR1M, switch SWR1MB, and switch SWR1P, switch SWR1PB, switch SWR2M, switch SWR2MB And, switch SWR2P, switch SWR2PB, capacitor CREM, capacitor CREP It has circuits ACM, ACP, IVTR, and IVTRr. Circuit ACP has terminals mbt1p and mbt2p, and circuit ACM has terminal mb It has t1m and terminal mbt2m.

[0278] Note that the switch SWR1P and the switch included in the ACTF[j] circuit of the calculation circuit 140 Switch SWR 2P, Switch SWR 1PB, Switch SWR 2PB, Capacitance CREP, Circuit Each of the ACPs is included in the circuit ACTF[j] in Figure 15, switch SWR1, Switch SWR2, Switch SWR1B, Switch SWR2B, Capacitor CRE, Circuit AC It corresponds to the terminals mbt1p and mbt2p of the circuit ACP in Figure 16. These correspond to terminals mbt1 and mbt2 of circuit AC in Figure 15. Switch SWR1P, Switch SWR2P, Switch SWR1PB, Switch SWR2 Figure 15 shows the connection configurations and functions of each of the PB, CREP (capacitance), and ACP (circuit ACP). Refer to the explanation of the ACTF[j] circuit.

[0279] The first terminal of switch SWR1M is connected to circuit IVTR, terminal T1, and switch SWR1P The first terminal of the switch SWR1M is electrically connected to the capacitor CR. The first terminal of EM is electrically connected to the first terminal of switch SWR2MB. The second terminal of switch SWR2MB is electrically connected to terminal mbt1m of circuit ACM. The first terminal of switch SWR1MB is connected to circuit IVTRr, terminal T2, and switch SW The first terminal of R1PB is electrically connected to the second terminal of switch SWR1MB. The second terminal of the capacitor CREM and the first terminal of the switch SWR2M are electrically connected. Yes. The second terminal of switch SWR2M is electrically connected to wiring VCN3.

[0280] Circuit ACM has the same circuit configuration as, for example, circuit ACP, i.e., circuit AC in Figure 15. This is possible. Furthermore, the circuit ACP can set a predetermined potential (for example, GND potential) at terminal mbt1p. When a potential lower than ) is input, for example, a digital signal is output from terminal mbt2p. The configuration outputs a signal with a value of 0, and similarly, the circuit ACM outputs a predetermined power to terminal mbt1m. When a potential lower than the GND potential is input, for example, terminal mbt2 The configuration may also output a signal with a value of 0 as a digital signal from m.

[0281] Also, Switch SWR1M, Switch SWR2M, Switch SWR1MB, and Switch For example, the SWR2MB switches mentioned earlier are SWR1 and SW Use a switch that can be applied in the same way as R1B, switch SWR2, and switch SWR2B. It is possible to do so. Also, here, switch SWR1M, switch SWR2M, switch SWR1MB, Switch SWR2MB, Switch SWR1P, Switch SWR2P, Switch Switch SWR1PB and Switch SWR2PB each have a high-level potential at their control terminals. It turns on when input is received, and turns off when a low-level potential is input to the control terminal. This shall be the case.

[0282] Also, Switch SWR1M, Switch SWR1P, Switch SWR1MB, Switch S It is preferable that each control terminal of the WR1PB be electrically connected to the same wiring. Yes. In other words, switch SWR1M, switch SWR1P, switch SWR1MB, switch Each of the SWR1PB units operates to be either on or off simultaneously with each other. It is preferable to do so.

[0283] Furthermore, the control terminals of switch SWR2M and switch SWR2P are the same It is preferable that the wiring be electrically connected. That is, switch SWR2M, switch Each SWR2P operates in such a way that it can be either on or off simultaneously with the others. This is preferable.

[0284] Furthermore, the control terminals for switches SWR2MB and SWR2PB are identical. It is preferable that the wiring is electrically connected. That is, switch SWR2MB, switch Each of the SWR2PB units operates to be either on or off simultaneously with each other. It is preferable to do so.

[0285] Here, in the calculation circuit 140 of Figure 16, if circuit ACTF[j] is connected to wiring OL[j] I flow out[j], I flowing from the wiring OLB[j] Bout When reading [j] Consider the following: Switch SWR1M, Switch SWR1P, Switch SWR1MB, Each control terminal of switch SWR1PB is electrically connected to wiring SRL1, and the switch The control terminals of the SWR2M switch and the SWR2P switch are electrically connected to wiring SRL2-1. The control terminals of switch SWR2MB and switch SWR2PB are connected to the following: It is assumed that it is electrically connected to line SRL2-2.

[0286] current I out [j] is I Bout If it is greater than [j], then, as in the example of the operation mentioned above, At time T04, the potential V of the first terminal of capacitance CREP Iout This is the second end of the capacity CREP. Child's potential V IBout It will be lower than that. And between time T04 and time T05 And the voltage between the first and second terminals of the capacitance CREP is maintained from time T06 to time T Between 07 and 07, the capacitive coupling of the capacitive CREP causes the second terminal of the capacitive CREP to... The potential at this position becomes higher than the GND potential. After time T07, this potential is at the terminal of circuit ACP. Input to sub-mbt1p, and from terminal mbt2p of circuit ACP, a digital signal corresponding to the potential is received. A signal is output.

[0287] On the other hand, at time T04, the potential V of the first terminal of the capacitor CREM Iout is, capacity CRE The potential V of the second terminal of M IBout It will be lower than that. And from time T04 to time T05 During this time, the voltage between the first and second terminals of the capacitor CREM is maintained, at time T06 Between time T07, the capacitance coupling of the capacitance CREM occurs, The potential of terminal 1 becomes lower than the GND potential. After time T07, this potential is in the circuit Input to terminal mbt1m of ACM, and a digital signal of 0 is received from terminal mbt2m of circuit ACM. A TAL signal is output.

[0288] In other words, current I out [j] is I Bout When [j] is greater than the terminals of circuit ACP A digital signal corresponding to the potential of terminal mbt1p is transmitted from mbt2p. Z The following is output, and the circuit ACM A GND potential is output from terminal mbt2m. And the pair of those two digital signals The positive output signal z is output by the circuit ACTF[j]. j (k) It can be done this way.

[0289] Also, current I out [j] is I Bout If it is less than [j], the behavior example described above will be as follows. At time T04, the potential V of the first terminal of capacitance CREP Iout is the capacity CREP Potential V at the second terminal IBout It will be higher than that. And from time T04 to time T05 During this time, the voltage between the first and second terminals of the capacitor CREP is maintained from time T06. Between time T07 and the second end of the capacitive CREP, the capacitive coupling of the capacitive CREP The potential of this child becomes lower than the GND potential. After time T07, this potential is the AC of the circuit. Input to terminal mbt1p of P, and a digital value of 0 is received from terminal mbt2p of circuit ACP. A signal is output.

[0290] On the other hand, at time T04, the potential V of the first terminal of the capacitor CREM Iout is, capacity CRE The potential V of the second terminal of M IBoutIt will be higher than that. And from time T04 to time T05 During this time, the voltage between the first and second terminals of the capacitor CREM is maintained, at time T06 Between time T07, the capacitance coupling of the capacitance CREM occurs, The potential of terminal 1 becomes higher than the GND potential. After time T07, this potential is in the circuit The signal is input to terminal mbt1m of the ACM, and the corresponding potential is transmitted from terminal mbt2m of the ACM circuit. A digital signal is output.

[0291] In other words, current I out [j] is I Bout When [j] is less than the terminal of circuit ACP, mbt2p outputs a GND potential, and terminal mbt2m of circuit ACM outputs to terminal mbt1p A digital signal corresponding to the potential is output. Then, the pair of these two digital signals is... The negative output signal z produced by the ACTF[j] circuit. j (k) It can be done this way.

[0292] <Example of arithmetic circuit configuration 3> In addition, in the calculation circuit 130 shown in Figure 12, the wiring IL[j] is set for circuit MP[i,j]. ] and wiring ILB[j], wiring OL[j], and wiring OL[j] are electrically connected. However, the present invention is not limited thereto. For example, the arithmetic circuit 130 is connected to wiring I L[j] and wiring OL[j] are combined and designated as wiring OL[j], and wiring ILB[j] and wiring O LB[j] and OLB[j] can be combined into a single wiring configuration.

[0293] An example of the configuration of this arithmetic circuit is shown in Figure 17. The arithmetic circuit 150 shown in Figure 17 is the same as the arithmetic circuit 13 At 0, wiring IL[j] and wiring OL[j] are combined and designated as wiring OL[j], and wiring I The LB[j] and the wiring OLB[j] are combined into a single wiring OLB[j] configuration.

[0294] Furthermore, the arithmetic circuit 150 has switching circuits TW[1] to TW[n]. Each of the switching circuits TW[1] to TW[n] has terminal TSa and terminal TSaB It has terminals TSb, TSbB, TSc, and TScB. Sa is electrically connected to wiring OL[j], and terminal TSbB is electrically connected to circuit ILD. Terminal TSc is electrically connected to circuit ACTF[i]. Terminal TSaB is connected to wiring O LB[j] is electrically connected, terminal TSbB is electrically connected to circuit ILD, terminal T ScB is electrically connected to circuit ACTF[j].

[0295] The switching circuit TW[j] connects terminal TSa to either terminal TSb or terminal TSc. To create a conductive state, and to create a non-conductive state between terminal TSa and the other terminal TSb or terminal TSc. It has the function of having terminal TSaB and terminal TSbB or Connect one of terminals TScB to the other terminal, and connect terminal TSaB to terminal TSbB or terminal TS It has the function of making the connection between cB and the other side non-conductive.

[0296] In other words, the weight coefficient is set to one of the circuits MP[1,j] through MP[m,j]. 1 data w1 (k-1) 1 (k) Or maybe lol m (k-1) n (k) Information corresponding to (for example, If you want to input (potential, resistance, current, etc.), in the switching circuit TW[j], terminal The connection between TSa and terminal TSb is made conductive, and the connection between terminal TSaB and terminal TSbB is made conductive. By enabling the connection, the first data is transmitted from circuit ILD to wiring OL[j] and wiring OLB[j]. Ta w1 (k-1) 1 (k) Or maybe lol m (k-1) n (k) Corresponding information (e.g., electric potential, It can supply values ​​such as resistance and current.

[0297] Furthermore, circuit ACTF[j] is calculated by circuits MP[1,j] to MP[m,j]. We want to obtain the result of the sum of products (equation (1.2)) of the weight coefficients and the values ​​of the neuron's signals. In this case, in the switching circuit TW[j], the connection between terminal TSa and terminal TSc is made conductive. Furthermore, by creating a conductive state between terminal TSaB and terminal TScB, the wiring OL[j], and Information corresponding to the sum of products (for example, electricity) is transmitted from the wiring OLB[j] to the circuit ACTF[j]. It can supply (position, current value, etc.). Also, in the ACTF[j] circuit, the input The value of the activation function is calculated from the sum of products obtained, and for example, as the output signal of the neuron. signal z j (k) You can obtain this.

[0298] Next, regarding the switching circuit TW[j] and the circuit ILD included in the arithmetic circuit 150... Let me explain. Figure 18A shows a switching circuit TW[ that can be applied to the arithmetic circuit 150. Figure 18A shows an example configuration of the circuit ILD. Note that in Figure 18A, the switching circuit TW To show the electrical connection configuration of [j] and circuit ILD, wiring OL[j] and wiring O LB[j] and the AFP circuit are also shown in the diagram.

[0299] The switching circuit TW[j] is, for example, a switch SWI, a switch SWIB, and It has switch SWO, switch SWOB, switch SWL, and switch SWLB. ru.

[0300] The ILD circuit, as an example, includes a current source circuit ISC. The configuration can be the same as that of the current source circuit ISC of the circuit ILD in Figure 14A. Therefore, the current source circuit ISC in Figure 18A is included in the circuit ILD in Figure 14A. Please refer to the explanation provided by Road ISC.

[0301] Note that the switches SWI, SWIB, SWO, and SWIB are explained in Figure 18A. Switch SWOB, Switch SWL, and Switch SWLB are examples of the aforementioned switches. SWR1, switch SWR1B, switch SWR2, and switch SWR2B are all suitable. You can use any available switch.

[0302] In an example of a switching circuit TW[j], terminal TSa is connected to the first terminal of switch SWI. The first terminal of switch SWO and the first terminal of switch SWL are electrically connected. Terminal TSaB is connected to the first terminal of switch SWIB and the first terminal of switch SWOB. The first terminal of switch SWLB is electrically connected to the second terminal of switch SWI. It is electrically connected to terminal TSb1. The second terminal of switch SWIB is terminal TS It is electrically connected to bB1. The second terminal of switch SWO is electrically connected to terminal TSc. It is connected. The second terminal of switch SWOB is electrically connected to terminal TScB. The second terminal of switch SWL is electrically connected to terminal TSb2. The second terminal of the WLB is electrically connected to terminal TSbB2.

[0303] Terminals TSb1 and TSb2 shown in Figure 18A are the terminals shown in Figure 17. This corresponds to the child TSb. Also, terminals TSbB1 and TSbB shown in Figure 18A 2 corresponds to terminal TSbB shown in Figure 17.

[0304] Wiring VCN is similar to wiring VCN of circuit ILD in Figure 14A, as is wiring OL[j] and / or This functions as a wiring that supplies a constant voltage to the wiring OLB[j]. Therefore, Figure 18 For wiring VCN A, refer to the explanation of wiring VCN in Figure 14A.

[0305] The switching circuit TW[j] is a switch SWI, a switch SWIB, a switch SWO, etc. Switch SWOB, Switch SWL, and Switch SWLB can each be set to ON or OFF. Switching to this setting creates a circuit that is conductive with wiring OL[j] and wiring OLB[j]. It can be changed.

[0306] For example, when you want to input a positive weighting coefficient to circuit MP, you would input that weighting coefficient to wiring OL[j]. Simply input the appropriate current and then input the constant potential supplied by the wiring VCN to the wiring OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] are made conductive, and the current source circuit I The circuit SC and the wiring OLB[j] are made non-conductive, and the circuit AFP and the wiring OL[j] are made non-conductive. By making it non-conductive, the connection between circuit AFP and wiring OLB[j] is made non-conductive, and wiring VCN and The connection between wiring OL[j] and wiring VCN is made non-conductive, and the connection between wiring VCN and wiring OLB[j] is made conductive. This should be done. That is, in the switching circuit TW[j], the switch SWI and S Turn switch SWLB ON, switch SWIB, switch SWO, switch SWOB The current source circuit IS should be turned off. Since there is conduction between C and wiring OL[j], the current from the current source circuit ISC to wiring OL[j Current can be passed through the circuit MP via [ ]. Also, wiring VCN and wiring OLB[j] Since there is conductivity between them, a constant voltage from wiring VCN is input to wiring OLB[j]. It can be done.

[0307] Furthermore, for example, when you want to input a negative weighting coefficient to circuit MP, you input that weighting coefficient to wiring OLB[j]. If you input a current corresponding to the coefficient and input the constant potential supplied by wiring VCN to wiring OL[j], Good. As an example, the current source circuit ISC and the wiring OL[j] are made non-conductive, and the current The source circuit ISC and the wiring OLB[j] are made conductive, and the circuit AFP and the wiring OL[j] The connection between them is made non-conductive, and the connection between circuit AFP and wiring OLB[j] is made non-conductive, wiring V The connection between CN and wiring OL[j] is made conductive, and the connection between wiring VCN and wiring OLB[j] is made non-conductive. It should be in a conductive state. That is, in the switching circuit TW[j], switch SWIB , and switch SWL is turned ON, switch SWI, switch SWO, switch SW Simply turn off both OB and switch SWLB. This will turn off the current source circuit. Since there is conductivity between the circuit ISC and the wiring OLB[j], the current from the current source circuit ISC to the wiring Current can be passed through circuit MP via OLB[j]. Also, wiring VCN and wiring O Since there is conductivity between L[j] and the wiring OL[j], a constant voltage from wiring VCN is applied to wiring OL[j]. It will be entered.

[0308] Also, for example, when you want to input a weight coefficient of 0 to circuit MP, wiring OL[j], wiring OL Each of B[j] should be input to the constant potential supplied by the wiring VCN. One example is current The connection between the source circuit ISC and the wiring OL[j] is made non-conductive, and the connection between the current source circuit ISC and the wiring OLB The connection between [j] and the circuit AFP is made non-conductive, and the connection between the circuit AFP and the wiring OL[j] is made non-conductive. The circuit AFP and the wiring OLB[j] are made non-conductive, and the wiring VCN and wiring OL[j] The connection between them should be made conductive, and the connection between wiring VCN and wiring OLB[j] should also be made conductive. In other words, in the switching circuit TW[j], switch SWL and switch SWLB are turned ON. In this state, the switches SWI, SWIB, SWO, and SWOB Simply turn each of them off. This will create a connection between wiring VCN and wiring OL[j]. Since the circuit becomes conductive, the circuit between wiring VCN and wiring OLB[j] becomes conductive, so wiring OL[ A constant voltage from the wiring VCN is input to [j] and the wiring OLB[j].

[0309] Also, for example, information (e.g., potential, current, etc.) can be transmitted from circuit MP[i,j] to circuit AFP. When supplying current, for example, a non-conductive connection is made between the current source circuit ISC and the wiring OL[j]. In this state, the current source circuit ISC and the wiring OLB[j] are made non-conductive, and the circuit AFP and wiring The connection between line OL[j] and the circuit AFP is made conductive, and the connection between circuit AFP and wiring OLB[j] is made conductive. Then, the connection between wiring VCN and wiring OL[j] is made non-conductive, and wiring VCN and wiring OLB[j The connection between ] and should be made non-conductive. That is, in the switching circuit TW[j], Switch SWO and switch SWOB are turned ON, and switch SWI and switch SWIB Simply turn off switch SWL and switch SWLB. Therefore, since there is conduction between circuit AFP and circuit MP[i,j], circuit MP[i,j] Information (e.g., potential, current, etc.) can be supplied from there to the AFP circuit.

[0310] Furthermore, a switching circuit TW[j] and a rotation circuit that can be applied to the calculation circuit 150 of one aspect of the present invention are also available. The ILD is not limited to the circuit configuration shown in Figure 18A. The switching circuit TW[j] and the rotation Each circuit configuration of the ILD can be changed depending on the situation. For example, Figure 1 Add switch SWH and switch SWHB to the switching circuit TW[j] shown in 8A. A wiring VCN2 may be provided in the circuit ILD. An example of such a configuration is shown in Figure 18B.

[0311] In Figure 18B, the first terminal of switch SWH is electrically connected to wiring OL[j]. The second terminal of switch SWH is electrically connected to wiring VCN2. The first terminal of the switch SWHB is electrically connected to the wiring OLB[j], and the second terminal of the switch SWHB Terminal 2 is electrically connected to wiring VCN2.

[0312] Wiring VCN2 supplies a constant voltage to wiring OL[j] and / or wiring OLB[j]. It functions as wiring. For example, wiring from circuit ILD via switching circuit TW[j] When current (positive current) flows through line OL or wiring OLB, the constant voltage supplied by wiring VCN2 and Therefore, it is preferable to use a high-level potential (e.g., VDD). Also, for example, wiring Current (negative current) flows from OL or wiring OLB to circuit ILD via switching circuit TW[j]. When current flows, the constant potential provided by wiring VCN2 is the ground potential or the low-level potential ( It is preferable to use a voltage such as VSS. In particular, the voltage supplied by wiring VCN4 is as shown in Figure 6A and It is preferable to use the wiring VCN4 as explained in Figure 6C.

[0313] In the circuit configuration of Figure 18B, switch SWI, switch SWIB, switch SWO, Switch SWOB, Switch SWL, and Switch SWLB are turned OFF, and Switch S By turning on WH and switch SWHB, wiring OL[j] and wiring O The voltage supplied by the wiring VCN2 can be input to LB[J] and each of them. For example, the voltage supplied by wiring VCN2 is the same as that supplied by wiring VCN4 as explained in Figures 6A to 6C. When the voltage is set to the specified value, the time T01 to time T02 in the example operation of the timing chart in Figure 9 During this time, do not leave switches SWR3 and SWR3B in the ON state. By turning on switch SWH and switch SWHB, wiring OL[j] and wiring O The same voltage as that applied to wiring VCN4 can be applied to LB[j]. That is, the circuit shown in Figure 18B. By applying the configuration to the arithmetic circuit 140, the circuit IVTR (circuit) shown in Figures 6A to 6C is obtained. The switch SWR3 (switch SWR3B) shown in IVTRr) can be omitted. ru.

[0314] Here, we will describe an example configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 150.

[0315] Figure 19A shows an example configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 150. Specifically, the circuit MP[i,j] in Figure 19A has the same configuration as the circuit MP[i,j] in Figure 13A. The modified circuit is the wiring IL[j] and wiring OL[j] of circuit MP[i,j] in Figure 13A. A configuration that combines ] and into one, and also combines wiring ILB[j] and wiring OLB[j] into one. Therefore, for the circuit MP[i,j] in Figure 19A, the same applies to the circuit M in Figure 13A. Refer to the explanation of P[i,j].

[0316] Next, we will explain an example of a modification of the circuit MP[i,j] in Figure 19A. Note that circuit M Regarding the modified form of P[i,j], we will mainly explain the differences from the circuit MP[i,j] in Figure 19A. Therefore, we will omit the explanation of the parts that are common with the circuit MP[i,j] in Figure 19A. ru.

[0317] The circuit MP[i,j] shown in Figure 19B is the same as the circuit MP[i,j] in Figure 19A, with wiring This configuration replaces X1L[i] with wiring WX1L[i]. That is, Figure 19B In circuit MP[i,j], wiring WX1L[i] and wiring WL[i] are connected to wiring OL[j Switching between a conductive state and a non-conductive state between the ] and the retaining part HC, and the wiring OLB[j] and retaining A predetermined potential is supplied to switch between a conductive state and a non-conductive state between the holding part HCr and the other part. It functions as a supply wire. Also, in the circuit MP[i,j] in Figure 19B, wiring WX1 L[i] and the wiring X2L[i] are connected to the second data z input to circuit MP[i,j]. i (k- 1) It functions as wiring that provides current, voltage, etc. according to the conditions. Note that the specific conditions shown in Figure 19B The circuit configuration will be described in Embodiment 3.

[0318] Next, we will discuss an example of a modified circuit MP[i,j] in Figure 19A, which is different from Figure 19B. To clarify, the circuit MP[i,j] shown in Figure 19C is a modified version of the circuit MP[i,j] in Figure 19A. Therefore, the circuit MP[i,j] in Figure 19C is the same as the circuit MP[i,j] in Figure 19A. It has a path MC and a circuit MCr. However, the circuit MP[i,j] in Figure 19C is the circuit MC This differs from the circuit MP[i,j] in Figure 19A in that the retaining part HCr is not included in r.

[0319] Furthermore, since the circuit MCr does not have a retaining part HCr, the circuit MP[i,j] in Figure 19C The calculation circuit to which this is applied does not have wiring for supplying the potential to be held in the holding part HCr. Alternatively, the circuit MCr does not need to be electrically connected to the wiring WL[i].

[0320] In circuit MP[i,j] in Figure 19C, the retaining part HC included in circuit MC is part of circuit MC It is electrically connected to r. In other words, circuit MP[i,j] in Figure 19C is connected to circuit MCr. The circuit MC and the holding part HC are configured to share each other. One example is the holding part The inverted signal of the signal held by the holding unit HC is supplied from the holding unit HC to the circuit MCr. This makes it possible for circuit MC and circuit MCr to operate differently. This is how it works. Alternatively, the internal circuit configurations of circuit MC and circuit MCr can be different. As a result, for the same signal held by the holding unit HC, the output is generated by circuit MC and circuit MCr. It is also possible to make the magnitude of the current different. Here, the holding part HC receives the first data w i (k-1) j (k) Maintain the potential corresponding to the second data z i (k-1) The corresponding electric potential By supplying this to wiring X1L[i] and wiring X2L[i], the circuit MP[i,j] The first data w is applied to wiring OL[j] and wiring OLB[j]. i (k-1) j (k) and the second Data Z i (k-1) It can output a current corresponding to the product of the two. Note that the tool in Figure 19C The actual circuit configuration will be described in Embodiment 3.

[0321] The circuit MP[i,j] shown in Figure 19D is a modified version of the circuit MP[i,j] in Figure 19A. This is also a modified version of the circuit MP[i,j] in Figure 13C. Specifically, the circuit MP[ in Figure 19D i,j] is a single wiring OL[j] in Figure 13C, where wiring IL[j] and wiring OL[j] are connected by a single wiring OL[j Combine them as ], and combine wiring ILB[j] and wiring OLB[j] into a single wiring OLB[j] The configuration is as follows. Therefore, for the circuit MP[i,j] in Figure 19D, Refer to the explanation of the circuit MP[i,j] in Figure 13C.

[0322] The circuit MP[i,j] shown in Figure 19E is a modified version of the circuit MP[i,j] in Figure 19A. This is also a modified version of the circuit MP[i,j] in Figure 13D. Specifically, the circuit MP[ in Figure 19D i,j] is a configuration in Figure 13D where wiring IL[j] and wiring ILB[j] are not provided. Therefore, the circuit MP[i,j] in Figure 19D is the same as the circuit in Figure 13D. Refer to the explanation of MP[i,j].

[0323] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0324] (Embodiment 3) In this embodiment, the specific configuration of the circuit MP described in Embodiment 1 and Embodiment 2 Let me explain with an example.

[0325] In Embodiments 1 and 2, the symbol for circuit MP is the position within the array unit ALP. Although [1,1], [i,j], [m,n], etc. are added to indicate placement, in this embodiment in particular... Unless otherwise specified, the notation for the circuit MP should be [1,1], [i,j], [m,n], etc. Omitted.

[0326] <Configuration Example 1> First, we will describe an example of a circuit configuration that can be applied to circuit MP in Figure 13A. The circuit MP shown is an example of the configuration of the circuit MP in Figure 13A, and is included in the circuit MP in Figure 20A. The circuit MC, for example, consists of transistor M1 and switches S2 to S5. It has, and a capacity C1. For example, switch S2, switch S5, and capacity C1. The holding portion HC is formed by the above.

[0327] Switches S2 through S5 are either electrical switches or mechanical switches. It is also possible to use a transistor as an electrical switch. Furthermore, switches S2 through S5 are transistors similar to transistor M1. This is also good. In particular, the switch S2 is intended to maintain the potential at the first terminal of the capacitor C1 for a long time. Therefore, it is preferable to use an OS transistor with a very low off-current. The transistor will be described in detail in Embodiment 5.

[0328] In circuit MP in Figure 20A, circuit MCr has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of the circuit MCr are such that the circuit elements of the circuit MC are such that To distinguish it from the other, the symbol "r" is added.

[0329] The transistor M1 shown in Figure 20A, for example, has gates above and below the channel. It is an n-channel type transistor with a multi-gate structure having, and transistor M1 is It has a first gate and a second gate. However, for convenience, in this specification, etc., as an example, The first gate is called the gate (sometimes referred to as the front gate), and the second gate is called the back gate. Although they are described as separate gates, the first and second gates are interchangeable. Therefore, in this specification, the term "gate" is used instead of "backgate". The phrase "backgate" can be replaced with the same phrase. This can be replaced with the word "gate". For example, "gate The first wire is electrically connected, and the back gate is electrically connected to the second wire. The connection configuration is such that "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring." This can be replaced with the connection configuration "connected electrically". For example, Figure 20 As shown in B, the back gate of transistor M1 is connected to the first terminal of capacitor C1, and switch S The first terminal of 2 may be electrically connected to the other terminal.

[0330] Furthermore, a semiconductor device according to one aspect of the present invention depends on the connection configuration of the back gate of the transistor. No. Transistor M1 shown in Figure 20A has a back gate, and The connection configuration of the back gate is not shown in the diagram, but the electrical connection of the back gate The successor can be determined during the design phase. For example, a transistor with a back gate. In order to increase the on-current of the transistor, the gate and back gate are electrically They may be connected electrically. That is, for example, the gate and back gate of transistor M1 may be connected electrically. It may also be connected electrically. Also, for example, in a transistor having a back gate, To vary the threshold voltage of a transistor, or the off-current of that transistor. To reduce this, wiring is provided that is electrically connected to external circuits, etc. A potential may be applied to the back gate of the transistor by means of a circuit or the like. This refers to transistors described not only in Figure 20A, but also elsewhere in the specification, or other figures. The same applies to the transistors shown in the diagram.

[0331] Furthermore, the semiconductor device according to one aspect of the present invention has a structure of transistors included in the semiconductor device. It does not depend on. For example, the transistor M1 shown in Figure 20A is shown in Figure 20C. Furthermore, a configuration without a back gate, that is, a single-gate transistor and It is also possible to do so. In addition, some transistors have a back gate configuration, and another one The transistors in this section may be configured without back gates. This refers to the transistors described not only in the circuit diagram shown in Figure 20A, but also in other parts of the specification. The same applies to transistors shown in other drawings.

[0332] Furthermore, in this specification, transistors of various structures are used as transistors. This is possible. Therefore, there are no restrictions on the type of transistor used. An example of a transistor is... For example, transistors made of single-crystal silicon, or amorphous silicon, polycrystalline silicon N, microcrystals (also called nanocrystals or semi-amorphous silicon) Transistors having non-single-crystal semiconductor films, such as those represented by , can be used. Alternatively, thin-film transistors (TFTs) made by thinning these semiconductors can be used. Yes, it is possible. When using TFTs, there are various advantages. For example, compared to single-crystal silicon... Because it can be manufactured at a low temperature, it is possible to reduce manufacturing costs or to increase the size of the manufacturing equipment. It is possible. Because the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Therefore, many can be manufactured simultaneously. Because individual display devices can be manufactured, they can be produced at a low cost. Alternatively, because the manufacturing temperature is low. Therefore, substrates with poor heat resistance can be used. It is possible to manufacture transistors. Alternatively, transistors on a light-transmitting substrate can be used in display elements. Light transmission can be controlled. Or, because the transistor film thickness is thin, the transistor A portion of the film that forms the aperture can transmit light. Therefore, the aperture ratio can be improved. It is possible.

[0333] For example, a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having n-Sn-Zn-O, etc., can be used. These compound semiconductors, or thin-film transistors made by thinning these oxide semiconductors, etc. These can be used. This allows for lower manufacturing temperatures, so for example, at room temperature... This makes it possible to manufacture ZISTAS. As a result, substrates with low heat resistance, such as plastics, can be used. Transistors can be formed directly on a substrate or film substrate. Compound semiconductors or oxide semiconductors are used not only in the channel portion of transistors, but also They can also be used for other purposes. For example, these compound semiconductors or oxide semiconductors It can be used as wiring, resistive elements, pixel electrodes, or light-transmitting electrodes, etc. Since these can be deposited or formed simultaneously with the transistor, costs can be reduced.

[0334] As an example of a transistor, a transistor formed using an inkjet method or printing method is... Rangistas and the like can be used. These allow for manufacturing at room temperature, manufacturing at low vacuum levels, and It can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This makes it possible to easily change the layout of the transistors. Alternatively, since it is possible to manufacture without using resist, material costs are reduced and the number of processes is eliminated. It can be reduced. Or, it is possible to apply the film only to the necessary parts, so after forming a film over the entire surface... This method is less wasteful and more cost-effective than etching.

[0335] As an example of a transistor, there are transistors that have organic semiconductors or carbon nanotubes. Transistors and the like can be used. With these, transients can be applied to a bendable substrate. It is possible to form transistors using organic semiconductors or carbon nanotubes. Devices using this technology can be made more resistant to impact.

[0336] Furthermore, transistors with various other structures can also be used. For example, transistors include MOS type transistors, junction type transistors, and bipod type transistors. A transistor such as a MOS-type transistor can be used. By using this, the size of the transistor can be reduced. Therefore, a large number of transistors It can be equipped with a transistor. Bipolar transistors are used as transistors. This allows for the flow of a large current. Therefore, it is possible to operate the circuit at high speed. Yes, it is possible. Furthermore, MOS transistors and bipolar transistors can be mixed on a single substrate. It may be formed in this way. This will enable low power consumption, miniaturization, and high-speed operation. can.

[0337] One example of a transistor is a structure in which gate electrodes are arranged above and below the active layer. This transistor can be applied. The structure has gate electrodes positioned above and below the active layer. This results in a circuit configuration where multiple transistors are connected in parallel. Therefore, the channel formation region increases, making it possible to increase the current value. Alternatively, the active layer By arranging the gate electrodes at the top and bottom, a depletion layer is more likely to form. This allows for improvement of the S value.

[0338] For example, one transistor has a structure in which the gate electrode is placed on top of the active layer. Structures in which the gate electrode is positioned below the active layer, positive staggered structure, inverse staggered structure, channel Structures in which the region is divided into multiple regions, structures in which the active layers are connected in parallel, or structures in which the active layers are connected in series. A transistor with a structure such as the following can be used. Alternatively, as a transistor, Fin type, FIN type, TRI-GATE type, Top Gate Type, bottom gate type, double gate type (gates are located above and below the channel), It can take on a variety of configurations.

[0339] As an example of a transistor, the active layer (or part thereof) has source electrodes and drains. A transistor with an overlapping in electrode structure can be used. By creating a structure in which the source electrode and drain electrode overlap a part of the active layer, This prevents the device from becoming unstable due to the accumulation of electric charge.

[0340] As an example of a transistor, a structure with an LDD region can be applied. By creating a range, the off-current can be reduced, or the transistor's breakdown voltage can be improved (reliability can be improved). This can be achieved. Alternatively, by providing an LDD region, when operating in the saturation region... A voltage at which the drain current does not change much even when the voltage between the drain and source changes. Current characteristics can be obtained.

[0341] For example, in this specification, transistors can be formed using various substrates. Yes. The type of circuit board is not limited to a specific one. One example of such a circuit board is a semi-circular board. Conductive substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, stainless steel Substrate having a resin-steel foil, tungsten substrate, having a tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base film, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Examples include glass or soda-lime glass. Flexible substrates, laminated films, and base material films. Examples of materials include the following: For example, polyethylene terephthalate. PET, polyethylene naphthalate (PEN), polyethersulfone (PES) ), there are plastics such as polytetrafluoroethylene (PTFE). One example is synthetic resins such as acrylic. Alternatively, another example is polypropylene. Examples include polyester, polyvinyl fluoride, or polyvinyl chloride. Examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or Paper products are among them. In particular, semiconductor substrates, single crystal substrates, or SOI substrates are used for transients. By manufacturing the staves, variations in characteristics, size, and shape are minimized, and current capacity is reduced. It is possible to manufacture transistors that are powerful and small in size. By configuring the circuit using this method, it is possible to reduce the power consumption of the circuit or increase its integration. Cut.

[0342] Furthermore, a flexible substrate is used as the substrate, and transistors are formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After partially or completely completing a semiconductor device, it is separated from the circuit board and transferred to another circuit board. It can be used in this way. In this case, the transistor can be used on substrates with poor heat resistance or flexible substrates. It can be mounted. Furthermore, the aforementioned release layer may include, for example, an inorganic tungsten film and a silicon oxide film. This method utilizes a layered film structure or a configuration in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0343] In other words, a transistor is formed using one substrate, and then the transistor is placed on another substrate. The transistor may be transposed and placed on a different substrate. As an example, in addition to the substrates on which the transistors described above can be formed, paper substrates, cellophane Fan boards, aramid film boards, polyimide film boards, stone boards, wood boards, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) (or recycled fibers (acetate, cupro, rayon, recycled polyester, etc.)) These include leather substrates and rubber substrates. By using these substrates, a tiger with good characteristics can be produced. Formation of transistors, formation of low-power transistors, manufacturing of durable devices, heat resistance This allows for the addition of features, weight reduction, or thinning of the material.

[0344] Furthermore, all the circuits necessary to realize the specified function are placed on the same circuit board (for example, glass It can be formed on substrates such as stainless steel substrates, plastic substrates, single crystal substrates, or SOI substrates. Yes. In this way, costs are reduced by reducing the number of parts, or the number of connection points with circuit components is reduced. This can improve reliability.

[0345] Furthermore, it is not necessary to form all the circuits required to achieve a specific function on the same circuit board. It is possible. In other words, some of the circuits necessary to achieve a certain function can be formed on a certain circuit board. Another part of the circuitry necessary to achieve the predetermined function is formed on a separate substrate. It is possible that some of the circuits necessary to achieve a certain function are gas Another part of the circuitry, which is formed on the lath substrate and necessary to realize a predetermined function, is a single crystal base. It can be formed on a plate (or SOI substrate). And it can realize a predetermined function. A single-crystal substrate (also called an IC chip) on which another part of the necessary circuitry is formed is called COG (Chip On Glass) connects to a glass substrate, and its I It is possible to place a C chip. Alternatively, the IC chip can be placed in a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology, or using printed circuit boards, etc. It is possible to connect to a lath substrate. In this way, a part of the circuit is formed on the same substrate as the pixel section. This reduces costs by decreasing the number of components, or by reducing the connection points with circuit components. Reliability can be improved by reducing the number of components. In particular, in circuits where the drive voltage is high, Alternatively, circuits with high drive frequencies often consume a lot of power. Therefore, by forming such a circuit on a substrate separate from the pixel section (for example, a single-crystal substrate), the IC chip is formed. This constitutes the chip. By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0346] In circuit MP of Figure 20A, the first terminal of transistor M1 is electrically connected to wiring VE. The connection continues. The second terminal of transistor M1 is connected to the first terminal of switch S3, and switch S The first terminal of 4 is electrically connected to the first terminal of switch S5. The gate of M1 is electrically connected to the first terminal of capacitor C1 and the first terminal of switch S2. The second terminal of capacitor C1 is electrically connected to wiring VE. Switch S2 The second terminal is electrically connected to the second terminal of switch S5 and to wiring IL. The control terminal of switch S2 is electrically connected to wiring WL. The second terminal of switch S3 is The control terminal of switch S3 is electrically connected to wire OL and to wiring X1L. The second terminal of switch S4 is electrically connected to the wiring OLB, and the control of switch S4 The terminal is electrically connected to wiring X2L.

[0347] In circuit MCr, a different connection configuration from circuit MC will be described. Switch S3r The second terminal is electrically connected to wiring OLB, not wiring OL, and is the second terminal of switch S4r. The child is electrically connected to wiring OL, not wiring OLB. Terminal 1 and the first terminal of capacitance C1r are electrically connected to wiring VEr.

[0348] Note that the configuration of circuit MP in Figure 20A may be changed to the configuration of circuit MP in Figure 21A. Specifically, the first terminal of transistor M1 is electrically connected to another wire, Vem, instead of wire VE. It is connected to the first terminal of transistor M1r, and the first terminal is connected to another wire VEmr instead of wire VEr. It may also be electrically connected. Note that this applies not only to circuit MP in Figure 20A, but also to circuits in other drawings. In the circuit diagram, the first terminal of transistor M1 is connected to a different wire, Vem, instead of wire VE. A configuration in which they are electrically connected, and / or the first terminal of transistor M1r is connected to wiring V Alternatively, the configuration could be such that it is electrically connected to a different wiring, VEMr, instead of Er.

[0349] Furthermore, in the holding part HC shown in Figure 20A, the gate of transistor M1 and capacitor C1 The electrical connection point between the first terminal and the first terminal of switch S2 is defined as node n1.

[0350] The holding part HC, as described in Embodiment 1, for example, is an electric unit corresponding to the first data. It has the function of maintaining a position. The potential to the holding part HC included in the circuit MC in Figure 20A. The holding condition is maintained when switches S2 and S5 are turned ON, and a potential is supplied from wiring IL. This is done by forcing the data to be written to capacity C1, and then turning off switch S2. This allows the potential of node n1 to be maintained as the potential corresponding to the first data. At this time, a current is input from wiring OL, and a potential of a magnitude corresponding to the magnitude of that current is supplied. It can be held in quantity C1. Therefore, the variation in the current characteristics of transistor M1 is less noticeable. It can reduce resonance.

[0351] Furthermore, transistor M1 maintains the potential of node n1 for a long time, resulting in low off-current. It is preferable to use a transistor with low off-current. Examples of transistors with low off-current include For example, an OS transistor can be used. Also, as transistor M1, A transistor with a gate is applied, and a low-level potential is applied to the back gate, thereby reducing the threshold voltage. Alternatively, the voltage may be shifted to the positive side to reduce the off-current.

[0352] In the operation example described later, to briefly explain the current entering and leaving circuit MP, Figure Let one end of wiring IL shown in 20A be node ina, and the other end of wiring OL be node outa. One end of the ILB wiring is designated as node inb, and the other end of the OLB wiring is designated as node outb.

[0353] Wiring VE functions, for example, as wiring that supplies a constant voltage. Switch S3, Switch S3r, Switch S4, or Switch S4r are n channels In the case of a 1 / 2 type transistor, and / or given wiring VSO in Figures 14A to 14C When the potential is a high-level potential, for example, the VSS is a low-level potential, or the ground potential is low-level potential. Alternatively, it can be set to other low-level potentials. Also, wiring VEM, wiring VEr and wiring VEmr, like wiring VE, are voltage lines that supply a constant voltage. It functions, and as the constant voltage, it is a low-level potential VSS, a low-level potential other than VSS, This can be the ground potential, etc. Furthermore, the constant voltage can be a high-level potential such as VD. It may also be D. In this case, the circuit IVTR (circuit IVTRr) of the arithmetic circuit 110 is, When applying any of Figures 6A to 6C, circuit ACTF[1] to circuit ACTF The constant voltage supplied by wiring VCN4, which is electrically connected to [n], is given by wiring VE and wiring V It is preferable to set the potential higher than the potential VDD supplied by Er.

[0354] Furthermore, the constant power supplied by each of the wiring VE, wiring VEM, wiring VEr, and wiring VEMr The pressures may be different from each other, or some or all of them may be the same. If the voltage supplied by the wiring is the same, select those wirings and treat them as the same wiring. This is also fine. For example, the given values ​​for each of the wiring VE, wiring VEM, wiring VEr, and wiring VEMr When the constant voltage is approximately equal, the circuit MP in Figure 21B is as follows: wiring VEm, wiring VEr, wiring VEmr can be the same wiring as wiring VE. Or, for example, wiring VE, wiring If the constant voltage supplied by each of the VErs is approximately equal, then the wires VE and VEr are connected to a single wire. It can be a single wiring. Alternatively, in Figure 21A, for example, wiring VE and wiring V Treat Er as a single identical wire, and treat wires VEM and VEMr as a single identical wire. Alternatively, for example, wiring VE and wiring VEmr can be treated as a single identical wiring, and wiring V Em and wiring VEr may be treated as a single, identical wire (not shown in the diagram).

[0355] Furthermore, the configuration of circuit MP in Figure 20A can be changed depending on the situation. For example, As shown in Figure 22A, transistors M1 and M1r of circuit MP in Figure 20A These are p-channel transistors, transistor M1p and transistor M1pr. It may also be replaced with . In this case, the constant voltage provided by wiring VE and wiring VEr is high level It is preferable to set VDD to a potential of 0. In addition to this case, the circuit of the calculation circuit 110 Circuits IVTR and IVTRR included in ACTF[1] or circuit ACTF[n] If any of Figures 6A to 6C is applied, the constant voltage supplied by wiring VCN4 It is preferable to set the potential to ground potential or VSS. When the potential of the wiring is changed in this way... This also changes the direction in which the current flows.

[0356] Also, for example, as shown in Figure 22B, switch S3 and switch S of circuit MP in Figure 20A Switch 3r, Switch S4, and Switch S4r are each connected to Analog Switch AS3 and Analog Switch It may also be called Switch AS4, Analog Switch AS3r, and Analog Switch AS4r. Oh, Figure 22B shows analog switch AS3, analog switch AS4, analog switch To operate the AS3r and analog switch AS4r, wiring X1LB and X2LB is also shown in the diagram. It shows that wiring X1LB powers analog switch AS3 and analog switch AS3r. Connected electrically, wiring X2LB, analog switch AS4, analog switch AS4r It is electrically connected to wiring X1LB. Wiring X1LB receives the inverted signal of the signal input to wiring X1L. The signal is input, and the inverted signal of the signal input to wiring X2L is input to wiring X2LB. Furthermore, wiring X1L and wiring X2L are combined into a single wire, and wiring X1LB and X2LB These can be combined into a single wire (not shown in the diagram). For example, an analog switch... Switch AS3, Analog Switch AS4, Analog Switch AS3r, and Analog Switch The AS4r is a CMO that uses n-channel transistors and p-channel transistors. An S configuration is also acceptable.

[0357] Also, the switch S3 shown in Figures 20A to 20C, 21A, 21B, and 22A, When transistors are applied to switches S3r, S4, and S4r, It is preferable that the respective sizes, for example, the channel length and channel width, are equal to each other. By using a circuit configuration like this, it may be possible to lay out the circuit efficiently. The currents flowing through switch S3, switch S3r, switch S4, and switch S4r are equalized. It may be possible. Also, similarly, Figures 20A to 20C, 21A, and 21B It is preferable that the sizes of transistors M1 and M1r shown are equal. i. Also, similarly, switch S2 shown in Figures 20A to 20C, Figure 21A, and Figure 21B, And when transistors are applied to switch S2r, the size of each transistor is It is preferable that they are equal. <<Example of operation 1>> Next, an example of the operation of circuit MP shown in Figure 20A will be described. Figures 23A to 23C, Figures 24A to 24C and 25A to 25C show the timing of circuit MP's operation example. This is a chart, and each represents a wire WL, wire X1L, wire X2L, node n1, and node n This shows the potential fluctuation at 1r. Note that Figures 23A to 23C and 24A to 24C are shown. In Figures 25A to 25C, "high" indicates a high-level potential, and "low" indicates a low potential. This indicates a low-level potential. Also, in this example of operation, the wiring IL is connected from node ina. Alternatively, the amount of current input from wiring IL to node ina is I IL And node inb The amount of current input to the wiring ILB (or from the wiring ILB to node inb) is I ILB Also, from wiring OL to node outa (or from node outa to wiring OL) ) The amount of current output is I OL And, wiring from OLB to node outb (or node o The amount of current output from UTB to the OLB (wiring) is I OLB This is as stated in Figures 23A to 23. C, In the timing charts shown in Figures 24A to 24C and Figures 25A to 25C, the current Quantity I IL , I ILB , I OL , I OLB The change in [the variable] is also illustrated.

[0358] In this example, the constant power supplied by wiring VE, wiring VEM, wiring VEr, and wiring VEMr is The voltage is VSS (low level potential). In this case, in Figure 14A, the wiring VSO has a high level A bell potential is applied, and current flows from wiring VSO through wiring OL to wiring VE or wiring VER. This will flow. Similarly, from wiring VSO through wiring OLB, wiring VE or wiring V Current will flow through Er. Note that in the circuit configuration shown in Figure 14A, the wiring VCN is Let VSS be the applied potential. Conduction is maintained between the wiring VCN and the second terminal of transistor M1. By doing so, VSS is applied to the second terminal of transistor M1. More details will follow. As will be explained, at this time the gate potential of transistor M1 also becomes VSS, so the transistor Transistor M1 is in the OFF state. Similarly, the connection between the wiring VCN and the second terminal of transistor M1r By creating a conductive state, the potential between the second terminal and gate of transistor M1r becomes VSS. Therefore, transistor M1r is in the off state.

[0359] Furthermore, in this example, the circuit IVTR (circuit IVTRr) included in the circuit ACTF is Let's assume the circuit IVTR (circuit IVTRr) is shown in Figure 6A. Also, the circuit IVT shown in Figure 6A. In circuit IVTRr, let VDD be the potential supplied by wiring VCN4.

[0360] In the circuit MP shown in Figure 20A, when switches S2 and S5 are in the ON state, Transistor M1 is configured in a diode connection. Therefore, power is supplied from wiring OL to circuit MC. When current flows, the second terminal of transistor M1 and the gate of transistor M1, The potentials are approximately equal. This potential is determined by the amount of current flowing from wiring OL to circuit MC and the transistor. This is determined by the potential of the first terminal of the ZISTA M1 (VSS in this case), etc. The gate potential of inverter M1 is maintained at capacitance C1, and then switch S2 is turned off. By doing so, transistor M1 generates a current corresponding to the potential of the gate of transistor M1. It functions as a current source. Therefore, it is affected by variations in the current characteristics of transistor M1. It can be reduced.

[0361] For example, when switches S2 and S5 are ON, the wiring OL is connected to the circuit MC. When the current I1 flows through the wiring VE, the current at the gate (node ​​n1) of transistor M1 The position will be V1. Here, by turning off switch S2, V1 It is held by the retaining part HC. As a result, transistor M1 is held by transistor M1 The potential VSS at the first terminal and the current I, which corresponds to the potential V1 at the gate of transistor M1. 1 can be flowed between the source and drain of transistor M1. In this specification, etc., this Such an operation is described as "transistor M1 is the source of the electricity flowing between the source and drain of transistor M1." This is referred to as "the flow rate is set (programmed) to I1."

[0362] In this example, the amount of current flowing from wiring OL to circuit MC is set to three types: 0, I1, and I2. Therefore, the current set for transistor M1 can be of three types: 0, I1, and I2. For example, if the gate potential of transistor M1, which is held in the holding part HC, is VSS Furthermore, the potentials of the first and second terminals of transistor M1 are also VSS, therefore, If the threshold voltage of transistor M1 is higher than 0, transistor M1 will be in the off state. Therefore, no current flows between the source and drain of transistor M1, so transistor M It can be said that the amount of current flowing between the source and drain of circuit 1 is set to 0. For example, if the gate potential of transistor M1, which is held in the holding part HC, is V1 When this happens, if the threshold voltage of transistor M1 is lower than V1-VSS, the transistor M1 is in the ON state. At this time, let I1 be the amount of current flowing through transistor M1. Therefore, when the gate potential of transistor M1 is V1, the source of transistor M1 - It can be said that the amount of current flowing between the drains is set to I1. Also, for example When the gate potential of transistor M1, which is held in the holding part HC, is V2, If the threshold voltage of transistor M1 is lower than V2-VSS, transistor M1 turns on. This is the state. At this time, let I2 be the amount of current flowing through transistor M1. Therefore, When the gate potential of transistor M1 is V2, the source-drain voltage of transistor M1 It can be said that the amount of current flowing through it is set to I2.

[0363] The current in I1 is assumed to be greater than 0 and less than I2. Also, the potential V 1 is set to be higher than VSS and lower than V2. Also, the threshold of transistor M1 is The voltage value should be higher than 0 and lower than V1-VSS. Also, I1 is, for example, In the explanation of Figure 14A, the constant current source circuit ISC1 generates I ut It can be replaced with Furthermore, I2 is generated, for example, by the constant current source circuit ISC2 in the explanation of Figure 14A. 2I ut It can be replaced with this.

[0364] Also, before explaining the operation example, the first data held by circuit MP (for example, weights in this case) The coefficient is defined as follows: VSS is set at node n1 of the retaining part HC, and retaining part HCr When VSS is held in node n1r, circuit MP is the first data (weight coefficient) Assume that it holds "0". V1 is at node n1 of the holding part HC, and node n1 of the holding part HCr When VSS is held in code n1r, circuit MP uses “ as the first data (weighting coefficient) Assume that it holds +1”. V2 is at node n1 of the holding part HC, and node n1 of the holding part HCr When VSS is held in n1r, circuit MP has "+" as the first data (weight coefficient). Assume that 2" is being held. VSS is at node n1 of the holding part HC, and node n1 of the holding part HCr When V1 is held in n1r, the circuit MP has "-1" as the first data (weighting coefficient). It is assumed that it holds ". VSS is at node n1 of the holding part HC, and node of the holding part HCr When V2 is held in n1r, the circuit MP has "-2" as the first data (weighting coefficient). It is assumed that it holds [this value].

[0365] Also, the second data input to the circuit MP (for example, the value of the neuron's signal in this case) Let it be the calculated value. For example, define it as follows: High-level potential at wiring X1L, wiring X When a low-level potential is applied to 2L, the circuit MP receives the second data (the signal from the neuron). The value of the number is set to "+1". Wiring X1L has a low-level potential, and wiring X2L has a high-level potential. When a level potential is applied, the circuit MP receives the second data (the value of the neuron's signal). "-1" is input. Low level potential at wiring X1L, low level potential at wiring X2L When a value is applied, the circuit MP receives the second data (the value of the neuron's signal) as “ Assume that "0" is input. For example, high-level potentials include VDD, Alternatively, the potential should be 10% or more, or 20% or more, higher than VDD.

[0366] Furthermore, in this specification and elsewhere, transistors M1 and M1r are referred to as such unless otherwise specified. If not present, the ON state includes cases where it ultimately operates in the saturation region. The gate voltage, source voltage, and drain voltage of each of the transistors mentioned above are This includes cases where the voltage is properly biased to operate in the saturation region. However, the present invention is not limited thereto. It involves reducing the amplitude value of the supplied voltage. Therefore, transistors M1 and M1r may operate in the linear region. If the first data (weighting coefficient) is an analog value, then the magnitude of the first data (weighting coefficient) Depending on the circumstances, for example, transistor M1 and transistor M1r operate in the linear region. And it is acceptable for there to be a mix of cases where it operates in the saturation region and cases where it operates in the saturation region.

[0367] Furthermore, in this specification, etc., switch S2, switch S2r, switch S3, switch Switch S3r, Switch S4, Switch S4r, Switch S5, Switch S5r are not specifically noted. If not present, the control terminal will turn ON when a high-level potential is input, and the control The device will be in the off state when a low-level potential is input to the terminal.

[0368] In the following, we will refer to the first data (for example, the weight coefficient below) and the second data (for example In the following, we will discuss the possible combinations of values ​​for each of the neuron's signal values ​​(calculated values, etc.). For each section, we will explain an example of the operation of the MP circuit.

[0369] [Condition 1] First, as an example, if the first data (weight coefficient) is "0" and input to circuit MP Let's consider the case where the second data (the value of the neuron's signal (calculated value)) is "+1". Figure 2 3A is the timing chart for the circuit MP in that case.

[0370] Between time T11 and time T12, the holding part HC and holding part HCr have an initial potential The initial potential is maintained. In Figure 23A, for example, at node n1 and node n1r, Assuming that a potential higher than the potential VSS is maintained.

[0371] Furthermore, a low-level potential is applied to wiring WL, wiring X1L, and wiring X2L. Depending on the switch, switch S2, switch S2r, switch S3, switch S3r, switch S 4. The control terminals of switches S4r, S5, and S5r are low Since a level potential is input, switch S2, switch S2r, switch S3, switch S3r, switch S4, switch S4r, switch S5, and switch S5r It will be turned off.

[0372] Between time T12 and time T13, a high-level potential is applied to the wiring WL. This allows switches S2, S2r, S5, and S5r to be used. Since a high-level potential is input to each control terminal, switch S2, switch S2 r, switch S5, and switch S5r are all turned ON.

[0373] Also, although not shown in Figure 23A, the wiring IL and wiring ILB each have an initialization process. V as potential ini A voltage is applied. Switch S2, switch S2r, switch S5, and Since each of the switches S5r is in the ON state, node n1 of the holding part HC, The potentials of each node n1r in the holding part HCr are V ini This means that the time T12 or Between then and time T13, node n1 of the holding part HC and node n1r of the holding part HCr The initialization of each potential is performed.

[0374] Note that the initialization potential V ini For example, it is preferable to use the ground potential. V of the initialization potential ini For example, a potential higher than VSS or ground potential, or a potential higher than ground potential. The potential may also be low. Furthermore, the initialization potential V to be applied to wiring IL and wiring ILB, respectively, is also acceptable. ini The potentials of these two wires may be different from each other. Note that the initial potentials of wiring IL and wiring ILB are set to different potentials. potential V ini You do not need to enter this information. Also, it is not necessary to enter the time from T12 to T13. It is not necessary to set a period. Or, it is not necessarily required to set a period between time T12 and time T13. Therefore, initialization is not required. Note that the ILD circuit shown in Figure 14A has an initialization potential V ini A wire that provides electrical conductivity, and a wire that creates electrical conductivity between the wire, wire IL, and wire ILB. Although the switch is not shown in the diagram, in this example of operation, the circuit ILD shown in Figure 14A is the wiring IL and Initialization potential V in the wiring ILB ini It shall have the function of providing [something].

[0375] Between time T13 and time T14, a potential VSS is applied from wiring IL to circuit MC. The potential VSS is input from the wiring ILB to the circuit MCr. This is shown in Figure 14A. Then, turn on switches SWLA and SWLAB, and switch SWIA, switch This is done by turning off the SWIAB switch. Also, in Figure 6A, the switch This is done by turning off SWR3 (switch SWR3B). Therefore, the potential at node n1 of the holding part HC becomes VSS, and the potential at node n1r of the holding part HCr is This becomes VSS. As a result, in circuit MC, transistor M1 has a current of 0. Because it is set to allow current to flow, no current flows from wiring OL through circuit MC to wiring VE. Furthermore, in circuit MCr, transistor M1r is set to have a current of 0. Therefore, no current flows from the OLB wiring through the MCr circuit to the VEr wiring. In other words, Between time T13 and time T14, transistors M1 and M1r Since it is in the OFF state, the connection between wiring OL and wiring VE becomes non-conductive, and wiring OLB and wiring The connection with VEr becomes non-conductive.

[0376] Between time T14 and time T15, wiring WL and wiring X1L have low levels A potential is applied. This activates switches S2, S2r, S5, and S Since a low-level potential is input to each control terminal of switch S5r, switch S2 Switches S2r, S5, and S5r are all turned off. When switch S2 and switch S2r are turned off, node n1 of the holding part HC The potential VSS is maintained, and the potential VSS of node n1r of the holding part HCr is maintained. When switch S5 is turned off, the wiring IL is routed through circuit MC to wiring VE. No current flows through it. Similarly, when switch S5r is turned off, Current will no longer flow from wiring ILB through circuit MCr to wiring VEr. Note that this occurs at time T14. Between [time] and time T15, switch SWR3 and switch SWR3B shown in Figure 6A You may also turn on the ON state to initialize the potentials of wiring OL and wiring OLB. , and by initializing the potential of the wiring OLB, circuit M will be activated from time T15 onward. The current output from P changes the potential of wiring OL and wiring OLB. It is possible.

[0377] The operation from time T11 to time T15 determines the first data (weight coefficient) of circuit MP and Then "0" is set. Also, after the first data (weight coefficient) is set in circuit MP, In Figure 14A, switches SWIA, SWIAB, SWLA, and The SWLAB switch may be turned off. Note that after the weight coefficients are set for circuit MP. Turn on switches SWR3 and SWR3B shown in Figure 6A, and connect the wiring OL. The potentials of the wiring OL and wiring OLB may be initialized. You can also turn off switches SWR3 and SWR3B.

[0378] From time T15 onward, the input of the neuron signal (calculated value) "+1" to circuit MP and Then, a high-level potential is input to wiring X1L and a low-level potential is input to wiring X2L. At this time, A high-level potential is input to the control terminals of switch S3 and switch S3r, and the switches A low-level potential is input to the control terminals of both the switch S4 and the switch S4r. Therefore, Switch S3 and Switch S3r are both in the ON state, and Switch S4 and Switch S Each of the 4r switches to the OFF state. In other words, this operation affects the relationship between the circuit MC and the wiring OL. The circuit MCr and the wiring OLB become conductive, and the circuit MC and the wiring OLB The connection between circuit MCr and wiring OL becomes non-conductive. As a result, circuit MC and wiring OL become non-conductive. The circuit AFP becomes conductive, and the circuit MCr becomes conductive as well. .

[0379] Note that transistor M1 is in the off state (set to have a current of 0). (Because of this), in the MC circuit, current flows between wiring OL, wiring OLB and wiring VE. No current flows. Similarly, since transistor M1r is in the off state (the current is 0), (As it is set up this way), in circuit MCr, wiring OL, OLB to wiring VEr No current flows until that point. Therefore, the current I output from node outa of wiring OL is... OL , and the current I output from node outb of the wiring OLB OLB This is before time T15. It does not change later. Therefore, there is a current I between circuit AFP and wiring OL. OL It does not flow, and A current I flows between the circuit AFP and the wiring OLB. OLB It doesn't flow.

[0380] By the way, this condition sets the first data (weight coefficient) to "0", and the input to circuit MP is Since the two data points (the values ​​of the neuron's signals (calculated values)) are set to "+1", equation (1.1) Using this, the product of the first data (weight coefficient) and the second data (value of the neuron's signal) is “ The product of the first data (weight coefficient) and the second data (neuron signal value) is "0". The result is that in the operation of circuit MP, the current I OL and current I O LB This corresponds to the case where each of the following remains unchanged. Note that the first data (weight coefficient) and the second data The result where the product of t (the value of the neuron's signal) is "0" is shown in Figure 15 as the circuit AFP or ra signal z j (k) It will be output as follows.

[0381] Note that once the first data (e.g., weight coefficients) is entered, its value will not be updated. By changing only the second data (such as the value of the neuron's signal or the calculated value), Multiple sum-of-products operations may be performed. In this case, updating the first data (weight coefficient) is not possible. This is essential, and therefore power consumption can be reduced. Note: Update of the first data (weighting coefficient) In order to minimize this, it is necessary to retain the first data (weighting coefficients) for a long period of time. For example, by using an OS transistor, the low off-current can be utilized to obtain the first data ( This makes it possible to maintain the weighting coefficients for a long period of time.

[0382] [Condition 2] Next, as an example, if the first data (weighting coefficient) is "+1" and input to circuit MP Let's consider the case where the second data (the value of the neuron's signal (calculated value)) is "+1". Figure 2 3B is the timing chart for the circuit MP in that case.

[0383] For the operation between time T11 and time T13, condition 1 applies from time T11 to time T Since it is the same as the operation up to 13, the operation from time T11 to time T13 in condition 1 Please refer to the description of the work.

[0384] Between time T13 and time T14, current I flows from wiring IL to circuit MC. A value of 1 is input, and the potential VSS is input from the wiring ILB to the circuit MCr. This is shown in Figure 14. Next, turn on switch SWIA and switch SWLAB, and switch SWIA This is done by turning off B and switch SWLA. The potential at node n1 of part HC is V1, and the potential at node n1r of holding part HCr is VSS. This means that in the MC circuit, transistor M1 will flow I1 as current. Because it is set to this, current I1 flows from wiring IL through circuit MC to wiring VE. Furthermore, in circuit MCr, transistor M1r is set to allow a current of 0 to flow. Therefore, no current flows from the ILB wiring to the VEr wiring via the MCr circuit.

[0385] Between time T14 and time T15, a low-level potential is applied to the wiring WL. This allows switches S2, S2r, S5, and S5r to be used. Since a low-level potential is input to each control terminal, switch S2, switch S2 Switch r, switch S5, and switch S5r are all in the OFF state. Switch S2, and When switch S2r is turned off, the potential V1 at node n1 of the holding part HC is maintained. The potential VSS of node n1r of the holding part HCr is maintained. Also, switch S5 When it is turned off, no current flows from wiring OL through circuit MC to wiring VE. Yes. Also, similarly, when switch S5r is turned off, the wiring from OLB returns Current will no longer flow from circuit MCr to wiring VEr. Note that from time T14 to time T15 During this time, switch SWR3 and switch SWR3B shown in Figure 6A are turned ON. The potentials of wiring OL and wiring OLB may be initialized. By initializing the potential, the current output from circuit MP after time T15 This allows the potential of wiring OL and wiring OLB to be changed.

[0386] The operation from time T11 to time T15 determines the first data (weight coefficient) of circuit MP and Then "+1" is set. Also, after the first data (weight coefficient) is set for circuit MP, In Figure 14A, switch SWIA, switch SWIAB, switch SWLA, and The switch SWLAB may be set to the OFF state. Note that the first data (weighting coefficient) is set in circuit MP. After the settings are configured, turn on switches SWR3 and SWR3B, and then wire the connections. The potentials of OL and wiring OLB may be initialized. After the process is complete, switches SWR3 and SWR3B may be turned off.

[0387] From time T15 onward, the second data (the value of the neuron's signal (calculated value)) is sent to circuit MP. ) As an input of “+1”, a high-level potential is input to wiring X1L and a low-level potential is input to wiring X2L. At this time, high-level signals are sent to the control terminals of switch S3 and switch S3r. When an electric potential is input, a low-level electric potential is supplied to the control terminals of switch S4 and switch S4r. The position is entered. Therefore, both switch S3 and switch S3r are in the ON state. As a result, both switch S4 and switch S4r turn off. As a result, conductivity is maintained between circuit MC and wiring OL, and between circuit MCr and wiring OLB. In this state, the connection between circuit MC and wiring OLB, and between circuit MCr and wiring OL, becomes non-conductive. This creates a conductive state between circuit MC and circuit AFP, and also the circuit MCr A conductive state is established between the circuit AFP and the other component.

[0388] In circuit MC, switch S3 is in the ON state and transistor M1 is ON. Because it is in the state of (it is set to flow current I1), wiring O Current flows from L to wiring VE. Also, in circuit MC, switch S4 is off. Because of this condition, no current flows between the OLB wiring and the VE wiring. In MCr, switch S3r is ON, but transistor M1r is OFF. Because it is in that state (it is set to allow 0 current to flow), the OLB wiring No current flows between the switch and the wiring VEr. Also, in circuit MCr, switch S4r Since it is in the OFF state, no current flows between wiring OL and wiring VEr. Therefore, the current I output from node outa of wiring OL OL I The current I increases by 1 and is output from node outb of the wiring OLB. OLB This is before time T15. It does not change later. Therefore, the current I1 between circuit AFP and wiring OL OL but There is a current flow, and between the circuit AFP and the wiring OLB, current I OLB It doesn't flow.

[0389] By the way, this condition sets the first data (weighting coefficient) to "+1" and inputs it to circuit MP. Since the second data point (the value of the neuron's signal) is set to "+1", we use equation (1.1). The product of the first data (weight coefficient) and the second data (neuron signal value) is "+1". Yes. The product of the first data (weight coefficient) and the second data (neuron signal value) is "+1". The result is that in the operation of circuit MP, the current I OL I1 increases, Flow I OLB This addresses the case where the first data (weight coefficient) and the second data ( The result where the product of the neuron signal values ​​is "+1" is shown in Figure 15 from the circuit AFP. signal z j (k) It will be output as follows.

[0390] Furthermore, between time T13 and time T14 under these conditions, for example, from wiring OL By setting the current flowing through the circuit MC to I2 instead of I1, V2 can be held in the holding part HC. This allows the first data (weight coefficient) of the circuit MP to be set to "+2". The first data (weight coefficient) is set to "+2", and the signal of the neuron input to circuit MP is... By adding "+1", from equation (1.1), the first data (weight coefficient) and the second data ( The product of the neuron signal values ​​is "+2". (First data (weight coefficient) and second data) The result that the product of (the neuron's signal value) is "+2" is that in the operation of circuit MP, at time T1 Current I OL As I2 increases, the current I OLB This addresses the case where the value does not change. As shown above, the VSS is held in the holding part HCr in the circuit MCr, and the electric By setting a flow rate other than I1, the first data (weighting coefficient) of circuit MP will be something other than "+1". A positive value can be set for this.

[0391] [Condition 3] Next, as an example, if the first data (weighting coefficient) w is "-1", and the input to circuit MP is Let's consider the case where the second data (the value of the neuron's signal (calculated value)) is "+1". 23C is the timing chart for the circuit MP in that case.

[0392] For the o...

Claims

1. It has a cell and a first circuit, The first circuit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first load, a second load, an operational amplifier, and a second circuit. The cell is electrically connected to one terminal of the first switch via the first wiring. The cell is electrically connected to one terminal of the second switch via the first wiring. The cell is electrically connected to one terminal of the first load via the first wiring. The cell is electrically connected to one terminal of the third switch via the second wiring. The cell is electrically connected to one terminal of the fourth switch via the second wiring. The cell is electrically connected to one terminal of the second load via the second wiring. The other terminal of the first switch is electrically connected to the third wiring to which the first constant voltage is supplied. The other terminal of the second switch is electrically connected to the first input terminal of the operational amplifier. The other terminal of the first load is electrically connected to one terminal of the fifth switch. The other terminal of the third switch is electrically connected to the third wiring. The other terminal of the fourth switch is electrically connected to the second input terminal of the operational amplifier. The other terminal of the second load is electrically connected to the fourth wiring to which the second constant voltage is supplied. The output terminal of the operational amplifier is electrically connected to the other terminal of the fifth switch. The output terminal of the operational amplifier is electrically connected to the second circuit. The cell has a function of holding first data, and a function of, upon input of second data into the cell, of flowing a first current between the cell and the first wiring corresponding to the first data and the second data, and flowing a second current between the cell and the second wiring corresponding to the first data and the second data. The operational amplifier has the function of outputting the difference voltage between the first current and the second current. The second circuit is a semiconductor device that has the function of outputting a signal corresponding to the differential voltage.

2. A semiconductor device according to claim 1, and a housing, An electronic device that performs neural network calculations using the aforementioned semiconductor device.

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