Semiconductor device

Abstract

Provided is a semiconductor device capable of calculating an echo state network. The semiconductor device has first to fifth circuits and first to third cells. The first circuit has a function of transmitting a first value to the first cell and a function of transmitting a second value to the second cell. The second circuit has a function of transmitting a third value to the third cell. The third circuit has a function of transmitting a fourth value to the first cell. The first cell has a function of adding the product of the first value and the fourth value, as a current, to a first current flowing through an input terminal of the fourth circuit. The fourth circuit has a function of generating a fifth value corresponding to the first current, and a function of transmitting the fifth value to the second cell and the third cell. The second cell has a function of adding the product of the second value and the fifth value, as a current, to the first current flowing through an input terminal of the fifth circuit. The third cell has a function of adding the product of the third value and the fifth value, as a current, to a second current flowing through the input terminal of the fifth circuit.

Description

Semiconductor device 【0001】 One aspect of the present invention relates to a semiconductor device. 【0002】 Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operation method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, storage devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods. 【0003】 Currently, the development of integrated circuits that mimic the structure of the human brain is in full swing. The integrated circuit incorporates the structure of the brain as an electronic circuit and has circuits that mimic the "neurons" and "synapses" of the human brain. Therefore, such an integrated circuit may be called, for example, "neuromorphic", "brainomorphic", or "brain-inspired". The integrated circuit has a non-Neumann architecture and is expected to perform parallel processing with extremely low power consumption compared to the Neumann architecture, in which power consumption increases as the processing speed increases. 【0004】 A model of information processing that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN: Artificial Neural Network). As an example, Patent Document 1 discloses a semiconductor device configured with reservoir computing using an algorithm called an echo state network. Reservoir computing is one of the frameworks of machine learning suitable for time-series information processing, which aims to obtain an output using time-series data and has characteristics such as a short learning time and high energy efficiency. 【0005】 International Publication No. 2022 / 248963 【0006】 The use of an echo state network requires operations such as sum-of-products operations, activation function operations, operations on recursively input input values, weighted average operations, and the like. When performing the above operations using hardware and software, a large amount of data transfer occurs between the processor and the memory, so the power consumption required for data transfer tends to be high. Therefore, it is preferable that the above operations can be performed only by hardware without using software. 【0007】 One aspect of the present invention aims to provide a semiconductor device capable of performing operations of an echo state network. Or, one aspect of the present invention aims to provide a semiconductor device capable of performing weighted average operations. Or, one aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Or, one aspect of the present invention aims to provide a semiconductor device capable of stabilizing output results. Or, one aspect of the present invention aims to provide a semiconductor device with a reduced circuit area. Or, one aspect of the present invention aims to provide a novel semiconductor device. 【0008】 Note that the problems of one aspect of the present invention are not limited to the above problems. The above problems do not prevent the existence of other problems. Other problems are problems not mentioned in this item as described below. Problems not mentioned in this item can be derived by those skilled in the art from the description in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the above problems and other problems, and does not necessarily need to solve all of the above problems and other problems. 【0009】One aspect of the present invention, made in view of the above problems, is a semiconductor device having a first calculation cell that multiplies the weight coefficients and input values ​​between neurons in the input layer and neurons in the reservoir layer in an echo-state network, a second calculation cell that multiplies the weight coefficients and input values ​​between neurons in the reservoir layer, and a third calculation cell that multiplies the weight coefficients and input values ​​between neurons in the reservoir layer and neurons in the output layer. In particular, the calculation results between neurons in the reservoir layer are configured to be input not only to the third calculation cell but also again to the second calculation cell. A specific example of the configuration of a calculation device in a semiconductor device according to one aspect of the present invention will be described below. 【0010】 (1) One aspect of the present invention is a semiconductor device having a first to sixth circuit, a first drive cell, a second drive cell, a first to third calculation cell, and a selector. The selector has a first input terminal, a second input terminal, a first output terminal, and a control terminal. 【0011】The selector has the function of making the connection between either the first input terminal or the second input terminal and the first output terminal conductive, in accordance with the control signal input to the control terminal. The first circuit has the function of transmitting the first signal to the first calculation cell and the function of transmitting the second signal to the second calculation cell. The second circuit has the function of transmitting the third signal to the third calculation cell. The third circuit has the function of transmitting the first reference signal or the fourth signal to the first drive cell and the first calculation cell. The first drive cell has the function of maintaining a potential corresponding to the first reference signal and the function of maintaining the input potential and current when the fourth signal is input. The first calculation cell has the function of maintaining a potential corresponding to the first signal when the first reference signal is input and the function of adding the product of the value corresponding to the first signal and the value corresponding to the fourth signal as a current to the first current flowing through the input terminal of the fifth circuit. The fifth circuit has the function of generating a fifth signal corresponding to the first current, and the function of transmitting the fifth signal to the second drive cell, the second calculation cell, and the third calculation cell via the second input terminal and the first output terminal. The fourth circuit has the function of transmitting a second reference signal to the second drive cell, the second calculation cell, and the third calculation cell via the first input terminal and the first output terminal. The second drive cell has the function of holding a potential corresponding to the second reference signal, and the function of maintaining the input potential and current when the fifth signal is input. The second calculation cell has the function of holding a potential corresponding to the second signal when the second reference signal is input, and the function of adding the product of the value corresponding to the second signal and the value corresponding to the fifth signal as a current to the first current flowing through the input terminal of the fifth circuit. The third calculation cell has the function of holding a potential corresponding to the third signal when the second reference signal is input, and the function of adding the product of the value corresponding to the third signal and the value corresponding to the fifth signal as a current to the second current flowing through the input terminal of the sixth circuit. The sixth circuit has the function of generating a sixth signal corresponding to the second current, and the function of outputting the sixth signal to the output terminal of the sixth circuit. 【0012】 (2) Alternatively, in one aspect of the present invention, the fifth circuit in (1) above may have a function to adjust the timing of the output of the fifth signal by pipeline processing. 【0013】(3) Alternatively, in one aspect of the present invention, the configuration in (2) above may include a first switch, a second switch, a third switch, a seventh circuit, and an eighth circuit. 【0014】 In particular, it is preferable that the output terminal of the fifth circuit is electrically connected to the first terminal of the first switch, the second terminal of the first switch is electrically connected to the input terminal of the seventh circuit, the output terminal of the seventh circuit is electrically connected to the first terminal of the second switch, the second terminal of the second switch is electrically connected to the input terminal of the eighth circuit, and the output terminal of the eighth circuit is electrically connected to the first terminal of the third switch. 【0015】 Furthermore, it is preferable that the seventh circuit has the function of acquiring the fifth signal from the input terminal of the seventh circuit and outputting the fifth signal from the output terminal of the seventh circuit when the first switch and the third switch are ON, and the function of holding the fifth signal and outputting the fifth signal from the output terminal of the seventh circuit when the first switch and the third switch are OFF. Furthermore, it is preferable that the eighth circuit has the function of acquiring the fifth signal from the input terminal of the eighth circuit and outputting the fifth signal from the output terminal of the eighth circuit when the second switch is ON, and the function of holding the fifth signal and outputting the fifth signal from the output terminal of the eighth circuit when the second switch is OFF. 【0016】 (4) Alternatively, in one aspect of the present invention, in (3) above, the seventh circuit may have a first transistor, a second transistor, and a third transistor, and the eighth circuit may have a fourth transistor, a fifth transistor, and a sixth transistor. In particular, it is preferable that the first to third transistors and the fourth transistor each have a different polarity from the fifth transistor and the sixth transistor, respectively. 【0017】Furthermore, it is preferable that the input terminal of the seventh circuit is electrically connected to the first terminal of the first transistor and the first terminal of the second transistor, the second terminal of the first transistor is electrically connected to the gate of the second transistor and the gate of the third transistor, and the output terminal of the seventh circuit is electrically connected to the first terminal of the third transistor. Furthermore, it is preferable that the input terminal of the eighth circuit is electrically connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor, the second terminal of the fourth transistor is electrically connected to the gate of the fifth transistor and the gate of the sixth transistor, and the output terminal of the eighth circuit is electrically connected to the first terminal of the sixth transistor. 【0018】 (5) Alternatively, in one aspect of the present invention, in (4) above, the first transistor and the fourth transistor may each have an oxide semiconductor containing indium in the channel formation region. 【0019】 Furthermore, one aspect of the present invention is a semiconductor device equipped with two calculation cells that perform weighted average calculations used in echo-state networks. Below, a specific configuration example of a semiconductor device capable of performing weighted average calculations, which is one aspect of the present invention, will be described. 【0020】 (6) One aspect of the present invention is a semiconductor device having a first to third circuit, a first calculation cell, and a second calculation cell. The third circuit has a first input terminal, a first output terminal, and a second output terminal. 【0021】Furthermore, the first circuit has the function of transmitting the first coefficient to the first calculation cell. The first calculation cell has the function of holding the first value as the first potential, and the function of obtaining the first coefficient and flowing the second value, which is the result of multiplying the first value and the first coefficient, as the first current between the first calculation cell and the first input terminal. The third circuit has the function of holding the second potential corresponding to the current supplied to the first input terminal, flowing the third value corresponding to the second potential as the second current between the first output terminal and the second calculation cell, and outputting the third value as the third current to the second output terminal. The second circuit has the function of transmitting the second coefficient to the second calculation cell. The second calculation cell has the function of holding the third value as the third potential, and the function of obtaining the second coefficient and flowing the fourth value, which is the result of multiplying the third value and the second coefficient, as the fourth current between the second calculation cell and the first input terminal. It is preferable that the sum of the first coefficient and the second coefficient be 1. 【0022】 (7) Alternatively, in one aspect of the present invention, the configuration in (6) above may include a fourth circuit. In particular, it is preferable that the fourth circuit includes a second input terminal, a third input terminal, and a third output terminal. It is also preferable that the fourth circuit has the function of flowing a first value, corresponding to the difference between the current flowing through the second input terminal and the current flowing through the third input terminal, as a fifth current between the third output terminal and the first calculation cell. 【0023】 (8) Alternatively, in one aspect of the present invention, the configuration in (7) above may include a first to fifth switch. 【0024】In particular, it is preferable that the third output terminal is electrically connected to the first terminal of the first switch, and the second terminal of the first switch is electrically connected to the first calculation cell and the first terminal of the second switch. Furthermore, it is preferable that the second terminal of the second switch is electrically connected to the first terminal of the third switch and the first input terminal, the first output terminal is electrically connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is electrically connected to the second terminal of the third switch and the second calculation cell. Furthermore, it is preferable that the second output terminal is electrically connected to the first terminal of the fifth switch. In addition, it is preferable that the control terminals of the first switch, the fourth switch and the fifth switch are electrically connected to the first wiring, and the control terminals of the second switch and the third switch are electrically connected to the second wiring. 【0025】 (9) Alternatively, in one aspect of the present invention, the third circuit in (8) above may have a configuration in which the first to fourth transistors are present. 【0026】 Furthermore, it is preferable that one source or drain of the first transistor is electrically connected to one source or drain of the fourth transistor and to the first input terminal, and that the gate of the first transistor is electrically connected to the gate of the second transistor, the gate of the third transistor and to the other source or drain of the fourth transistor. Also, one source or drain of the second transistor is electrically connected to the first output terminal, and one source or drain of the third transistor is electrically connected to the second output terminal. 【0027】 (10) Alternatively, in one aspect of the present invention, in (9) above, the first circuit may be configured to have a fifth transistor having the same polarity as the fourth transistor. In particular, it is preferable that the source and drain of the fifth transistor are electrically connected to the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the other of the source or drain of the fourth transistor. 【0028】(11) Alternatively, in one aspect of the present invention, in (10) above, each of the first to third transistors may have silicon in the channel formation region, and each of the fourth and fifth transistors may have an oxide semiconductor containing indium in the channel formation region. 【0029】 (12) Alternatively, in one aspect of the present invention, in (11) above, the first arithmetic cell may have a sixth transistor, a seventh transistor, and a first capacitance element, and the second arithmetic cell may have an eighth transistor, a ninth transistor, and a second capacitance element. 【0030】 In particular, it is preferable that either the source or drain of the sixth transistor is electrically connected to the gate of the seventh transistor and the first terminal of the first capacitance element, and that the second terminal of the first capacitance element is electrically connected to the first circuit. Furthermore, it is preferable that either the source or drain of the eighth transistor is electrically connected to the gate of the ninth transistor and the first terminal of the second capacitance element, and that the second terminal of the second capacitance element is electrically connected to the second circuit. 【0031】 Furthermore, it is preferable that the sixth transistor and the first capacitance element have the function of maintaining the gate potential of the seventh transistor as a first potential. Furthermore, it is preferable that the eighth transistor and the first capacitance element have the function of maintaining the gate potential of the ninth transistor as a third potential. Furthermore, it is preferable that the seventh transistor has the function of allowing a first current to flow between its source and drain by applying a potential corresponding to a first coefficient to the second terminal of the first capacitance element. Furthermore, it is preferable that the ninth transistor has the function of allowing a fourth current to flow between its source and drain by applying a potential corresponding to a second coefficient to the second terminal of the second capacitance element. 【0032】 (13) Alternatively, in one aspect of the present invention, in (12) above, each of the sixth to ninth transistors may have an oxide semiconductor containing indium in the channel formation region. 【0033】The configuration described in (1) above enables multiplication of weight coefficients and input values ​​between neurons in the input layer and neurons in the reservoir layer, multiplication of weight coefficients and input values ​​between neurons in the reservoir layer and neurons in the output layer. In particular, since the calculation result of the second calculation cell is input back into the second calculation cell, recursive input in the reservoir layer can be realized. Furthermore, the configuration described in (2) above enables pipeline processing in the fifth circuit. This allows adjustment of the timing at which the calculation result of the second calculation cell is input to the third calculation cell, thereby stabilizing and converging the output result in the echo state network of the semiconductor device. In addition, the configuration described in (6) above enables weighted average calculation. Therefore, by applying the configuration described in (6) above to a semiconductor device that performs calculations in an echo state network, calculations using the Leaky Integrator model can be performed in the echo state network. 【0034】 According to one aspect of the present invention, a semiconductor device capable of performing echo-state network calculations can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device capable of performing weighted average calculations can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device capable of stabilizing output results can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with reduced circuit area can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. 【0035】Furthermore, the effects of one aspect of the present invention are not limited to the effects described above. The effects described above do not preclude the existence of other effects. Other effects are those described below, which are not mentioned in this section. Effects not mentioned in this section can be derived by those skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention has at least one of the effects described above and other effects. Accordingly, one aspect of the present invention may, in some cases, not have the effects listed above. 【0036】Figure 1 is a block diagram showing an example of the configuration of the arithmetic unit. Figure 2 is a circuit diagram showing an example of the configuration of the circuits included in the arithmetic unit. Figure 3 is a circuit diagram showing an example of the configuration of the circuits included in the arithmetic unit. Figure 4 is a circuit diagram showing an example of the configuration of the circuits included in the arithmetic unit. Figures 5A and 5B are circuit diagrams showing an example of the configuration of the circuits included in the arithmetic unit. Figures 6A, 6B, and 6C are timing charts showing an example of the operation of the circuits included in the arithmetic unit. Figures 7A and 7B are circuit diagrams showing an example of the configuration of the circuits included in the arithmetic unit. Figure 8 is a circuit diagram showing an example of the configuration of the circuits included in the arithmetic unit. Figure 9 is a circuit diagram showing an example of the configuration of the circuits included in the arithmetic unit. Figure 10 is a timing chart showing an example of the operation of the arithmetic unit. Figures 11A and 11B are block diagrams showing an example of the operation of the arithmetic unit. Figures 12A and 12B are block diagrams showing an example of the operation of the arithmetic unit. Figures 13A and 13B are circuit diagrams showing an example of the configuration of the circuits included in the arithmetic unit. Figures 14A and 14B are circuit diagrams showing an example of the configuration of the circuits included in the arithmetic unit. Figures 15A and 15B are circuit diagrams showing example configurations of circuits included in the arithmetic unit. Figure 16 is a timing chart showing an example of operation of the arithmetic unit. Figure 17 is a block diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 18 is a block diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 19 is a circuit diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 20 is a circuit diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 21 is a circuit diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 22 is a circuit diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 23 is a circuit diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 24 is a timing chart showing an example of operation of the arithmetic unit. Figures 25A and 25B are block diagrams showing examples of operation of the arithmetic unit. Figure 26 is a block diagram showing an example of operation of the arithmetic unit. Figure 27 is a block diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 28 is a circuit diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 29 is a circuit diagram showing an example of circuit configurations of circuits included in the arithmetic unit. Figure 30 is a timing chart showing an example of operation of the arithmetic unit. Figure 31 is a diagram illustrating the RC model.Figures 32A and 32B are schematic plan views showing an example of a circuit included in a computing device. Figure 33 is a schematic cross-sectional view showing an example of the configuration of a computing device. Figure 34 is a schematic cross-sectional view showing an example of the configuration of a transistor included in a computing device. Figures 35A and 35B are schematic cross-sectional views showing an example of the configuration of a transistor included in a computing device. Figure 36A is a schematic plan view showing an example of the configuration of a transistor included in a computing device, and Figures 36B and 36C are schematic cross-sectional views showing an example of the configuration of a transistor included in a computing device. Figure 37 is a schematic perspective view showing an example of the configuration of a transistor included in a computing device. Figures 38A, 38B, 38C, and 38D show examples of electronic components. Figure 39 shows an example of an information processing system. Figure 40 shows an example of space equipment. Figure 41 shows an example of a storage system applicable to a data center. Figures 42A1, 42A2, 42A3, 42A4, 42A5, 42A6, 42A7 and 42B1, 42B2, 42B3, 42B4, 42B5, and 42B6 are circuit diagrams illustrating electrical connections. 【0037】 (Notes relating to this specification) In this specification, a semiconductor device is a device that utilizes semiconductor properties, and refers to a circuit containing semiconductor elements (e.g., transistors, diodes, and photodiodes), or a device having such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor properties. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component in which a chip is housed in a package. Furthermore, for example, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may be semiconductor devices themselves or may have semiconductor devices. 【0038】 In this specification, "connection" includes, for example, "electrical connection." 【0039】Furthermore, when describing the connection relationships of circuit elements as physical objects, the term "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" means, for example, that A and B are connected without the use of circuit elements (e.g., transistors or switches; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers. 【0040】 Here, when we define "A and B are indirectly connected," it refers to the following type of connection, as an example: That is, assuming the circuit is operating, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then such a circuit can be defined as having "A and B indirectly connected" as a physical object. Even if there are times when no electrical signals are exchanged or potential interactions occur between A and B, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined as having "A and B indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a physical object. Therefore, for example, even if no power supply voltage is supplied to the circuit and the circuit is not operating, the circuit can still be defined as having "A and B indirectly connected" as a physical object (however, as an example, this is limited to cases where, when power supply voltage is supplied to the circuit and the circuit is operating, electrical signals are exchanged or potential interactions occur between A and B during the circuit's operation). 【0041】The following are specific examples of "indirect connections". First, an example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in Figures 42A1 and 42A2. Another example of a case where "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected", assuming the circuit is operating, one transistor between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. Note that when "A and B are indirectly connected", this includes a time when one transistor between A and B is in an OFF state or a non-conducting state. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state, either simultaneously or at different times. As another example, as shown in Figure 42A3, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected." 【0042】 Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in Figure 42A4. Another example of when A and B are connected via an insulator is when a transistor gate insulating film is interposed between A and B, as shown in Figure 42A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected." 【0043】Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, as shown in Figures 42A6 and 42A7, multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND. In this case, it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." In Figure 42A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, then the connection relationship is the same as in Figures 42A6 and 42A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected." 【0044】 As shown above, we have provided an example of "indirect connection." As an example, the provisions for "indirect connection" are included in the provisions for "electrical connection," so if "A and B are indirectly connected," then "A and B are electrically connected." 【0045】Next, we will show specific examples of "direct connection." An example of "A and B being directly connected" is when A and B are connected without any circuit elements in between, as shown in Figures 42B1, 42B2, and 42B3. Furthermore, as shown in Figures 42B4 and 42B5, when A and B are connected to a power source that supplies a constant potential V, or to GND, without any circuit elements in between, we can say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Furthermore, as shown in Figure 42B6, even when A (or B) is connected to a constant potential V via the source and drain of a transistor, we can say that "A and B are directly connected." Furthermore, since A and V, or B and V, are connected via the source and drain of a transistor, they cannot be said to be directly connected, and we can say that "A and V are indirectly connected," or "B and V are indirectly connected." 【0046】 As shown above, an example of "direct connection" has been given, but as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," if "A and B are directly connected," then "A and B are electrically connected." 【0047】Even if independent components are shown connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a "wire" also functions as an "electrode," a single conductive film possesses the functions of both a "wire" and an "electrode." Similarly, if part of a "wire" also functions as a "terminal," a single conductive film possesses the functions of both a "wire" and a "terminal." Therefore, it can be said that two or more components selected from "electrodes," "wires," and "terminals" are formed as a single unit. Furthermore, the terms "electrode," "wire," or "terminal" may be replaced with the term "region" depending on the context. Consequently, in this specification, connection includes cases where a single conductive film possesses the functions of multiple components. 【0048】 The switches described herein are described as having the function of being in an ON state or an OFF state and controlling whether or not to allow current to flow, or having the function of selecting and switching the path through which current flows. 【0049】 Furthermore, in this specification, "conductive state" means a state in which current can flow between two input / output terminals, and "non-conductive state" means a state in which the two input / output terminals can be considered electrically disconnected. Also, in this specification, the ON state of a switch falls under the category of "conductive state," and the OFF state of a switch falls under the category of "non-conductive state." For this reason, in this specification, "conductive state" and "ON state" are interchangeable with each other, and "non-conductive state" and "OFF state" are interchangeable with each other. 【0050】 Furthermore, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer, for example, to a state in which an electric current can flow between the conductive layers. 【0051】Furthermore, a switch may have two or more terminals for conducting current, in addition to its control terminals. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to a specific type, as long as it has the function of controlling current. 【0052】 Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. An example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and the movement of these electrodes controls the on and off states. 【0053】In this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the switching between the conductive and non-conductive states of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. In this specification, when describing the connection relationships of a transistor, the notations "one of the source and drain" and "the other of the source and drain" are used. In this specification, one of the source and drain may be referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other of the source and drain may be referred to as the "second electrode of the transistor" or "second terminal of the transistor." Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this specification, one of the gate or back gate of a transistor may be referred to as the first gate, and the other of the gate or back gate of a transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, if a transistor has three or more gates, each gate may be referred to as the first gate, second gate, third gate, and so on. 【0054】For example, one example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure where multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). Alternatively, the multi-gate structure allows for the acquisition of an Id-Vds characteristic where, when operating in the saturation region of the Id (source-drain current)-Vds (drain-source voltage) characteristic, the current between the drain and source does not change much even when the voltage between the drain and source changes, resulting in a flat slope. By utilizing the Id-Vds characteristic in this region, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized. 【0055】 Generally, the threshold voltage of a transistor is the voltage located between the subthreshold region (weak inversion region) and the strong inversion region, and can also be described as the voltage at which the switching between the subthreshold region and the strong inversion region occurs. One example of a method for measuring the threshold voltage is to use the Id (source-drain current) - Vgs (gate-source voltage) characteristic as a basis for measuring the Id １／２ - Plot the Vgs characteristics and Id １／２ -Id on the tangent line where the slope of the Vgs characteristic is maximum １／２ One method is to use the Vgs value where = 0 as the threshold voltage. Another example is an Id-Vgs characteristic with a drain potential of 1.2V, where Id = 1.0 × 10 −１２ One method is to use Vgs, which is A, as the threshold voltage. 【0056】Furthermore, in this specification, operation in the subthreshold region of a transistor includes cases where the gate-source voltage of the transistor is lower than the threshold voltage, and more preferably, cases where the drain current of the transistor increases exponentially with respect to the gate-source voltage. In this case, the gate potential, source potential, and drain potential supplied to the transistor include cases where the potentials supplied are appropriately within the range in which the transistor operates in the subthreshold region. 【0057】 Furthermore, in this specification, the subthreshold region refers to the region in the graph showing the Id-Vgs characteristic of a transistor where Vgs is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, deviating from the gradient dual-channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where Id increases exponentially with increasing Vgs. Alternatively, the subthreshold region includes regions that can be considered as the regions described in each of the above explanations. 【0058】 Furthermore, in this specification, the source-drain current when a transistor operates in the subthreshold region is referred to as the subthreshold current. The subthreshold current increases exponentially with respect to the gate-source voltage, regardless of the drain potential. 【0059】 Furthermore, generally speaking, the off-current in a transistor sometimes refers to the source-drain current that flows when the gate-source voltage Vgs is lower than the threshold voltage. For this reason, the off-current may include the subthreshold current. In this specification, since we are dealing with circuits driven by the subthreshold current, unless otherwise specified, the off-current will be described as a current smaller than the subthreshold current. 【0060】Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Nor do they limit the order of components, such as process order or layering order. In addition, even if a term in this specification does not have an ordinal number, an ordinal number may be added in the claims to avoid confusion of components. Also, even if a term in this specification has an ordinal number, a different ordinal number may be added in the claims. Furthermore, even if a term in this specification has an ordinal number, the ordinal number may be omitted in the claims. For example, a component that is designated with the ordinal number "first" in one embodiment of this specification may be designated with a different ordinal number such as "second," "third," etc., in another embodiment or in the claims. Also, for example, a component that is designated with the ordinal number "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. 【0061】 Furthermore, this specification may use timing charts to explain the operation of semiconductor devices. The timing charts used in this specification represent ideal operating examples, and the periods, magnitudes of signals (e.g., potential or current) and timings shown in the timing charts are not limited unless otherwise specified. Depending on the situation, the magnitudes and timings of the signals (e.g., potential or current) input to each wiring (including nodes) in the timing charts described herein may be modified. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may differ. Also, for example, even if one period is shown as longer and the other as shorter, the lengths of the two periods may be equal, or one period may be shorter and the other longer. Furthermore, in order to clearly illustrate the timing chart, for example, two or more overlapping signals may be intentionally offset in the illustration. 【0062】The embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be carried out in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In addition, in the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Furthermore, in drawings such as perspective views, the description of some components may be omitted in order to clearly show the components that are to be described. 【0063】 In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them. 【0064】 Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences. 【0065】 (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention. 【0066】<Example of Semiconductor Device Configuration> Figure 1 is a block diagram showing an example of the configuration of a computing device, which is a semiconductor device according to one embodiment of the present invention. The computing device CDV shown in Figure 1 is a computing device that can be applied to reservoir computing, and as an example, has a computing unit CA, a drive circuit WCD, a drive circuit XCD, a drive circuit WSD, a drive circuit SCD, and a drive circuit ITS. The computing device CDV can perform calculations of an echo state network (ESN) used in reservoir computing by the computing unit CA and these drive circuits. The ESN is assumed to have an input layer, a reservoir layer, and an output layer. Further details of the ESN will be described later in Embodiment 2. 【0067】 By using the arithmetic unit CDV shown in Figure 1, it becomes possible to perform multiplication of weight coefficients and input values ​​between neurons in the input layer and neurons in the reservoir layer of the ESN, multiplication of weight coefficients and input values ​​between neurons in the reservoir layer and neurons in the output layer. In particular, the arithmetic unit CDV shown in Figure 1 has a circuit configuration in which the result of calculations performed in the arithmetic unit CA is input to the arithmetic unit CA and calculations are performed again, thereby realizing recursive input in the reservoir layer. 【0068】 The arithmetic unit CA includes, for example, region CAi, region Car, region CAo, and region CAd. Region CAi contains arithmetic circuits CCi[1] to CCi[n] (where n is an integer of 1 or more), region Car contains arithmetic circuits CCr[1,1] to CCr[n,n], and region CAo contains arithmetic circuits CCo[1] to CCo[n]. In particular, region Car has n × n arithmetic circuits CCr arranged in an n x n matrix. 【0069】 Furthermore, each of the arithmetic circuits CCi, CCr, and CCo includes, for example, arithmetic cells MCp and MCn. Also, the region CAD includes, for example, a drive cell DCi and drive cells DCo[1] to DCo[n]. 【0070】The calculation unit CA has wiring WLip[1] to WLip[n], wiring WLin[1] to WLin[n], wiring WLop, and wiring WLon extending in the column direction. The calculation unit CA also has wiring XLi and wiring XLo[1] to XLo[n] extending in the row direction. The calculation unit CA also has wiring SLi and wiring SLo[1] to SLo[n] extending in the row direction. 【0071】 The wiring WLip[j] (where j is an integer between 1 and n) is connected to the arithmetic cell MCp contained in the arithmetic circuits CCi[j] and CCr[1,j] through CCr[n,j], respectively. The wiring WLin[j] is connected to the arithmetic cell MCn contained in the arithmetic circuits CCi[j] and CCr[1,j] through CCr[n,j], respectively. The wiring WLop is connected to the arithmetic cell MCp contained in the arithmetic circuits CCo[1] through CCo[n], respectively. The wiring WLon is connected to the arithmetic cell MCn contained in the arithmetic circuits CCo[1] through CCo[n], respectively. 【0072】 Wiring XLi is connected to the drive cell DCi and the calculation cells MCp and MCn contained in calculation circuits CCi[1] through CCi[n], respectively. Wiring XLo[h] (where h is an integer between 1 and n) is connected to the drive cell DCo[h] and the calculation cells MCp and MCn contained in calculation circuits CCr[h,1] through CCr[h,n] and CCo[h], respectively. 【0073】 Wiring SLi is connected to the drive cell DCi and the calculation cells MCp and MCn, which are included in calculation circuits CCi[1] through CCi[n], respectively. Wiring SLo[h] is connected to the drive cell DCo[h] and the calculation cells MCp and MCn, which are included in calculation circuits CCr[h,1] through CCr[h,n] and CCo[h], respectively. 【0074】The drive circuit WCD includes, for example, circuits WCDi[1] to WCDi[n] and circuit WCDo. The drive circuit XCD includes, for example, circuit XDi and circuits XDR[1] to XDR[n]. The drive circuit SCD includes, for example, selector SC[1] to selector SC[n]. The drive circuit ITS includes, for example, circuits ITSr[1] to ITSr[n] and circuit ITSo. 【0075】 Furthermore, circuit WCDi has an input terminal, a first output terminal, and a second output terminal. Furthermore, circuit WCDo has an input terminal, a first output terminal, and a second output terminal. Furthermore, selector SC has a first input terminal, a second input terminal, and an output terminal. Furthermore, circuit ITSr has a first input terminal, a second input terminal, and an output terminal. Furthermore, circuit ITSo has a first input terminal, a second input terminal, and an output terminal. 【0076】 The input terminal of circuit WCDi[j] is connected to wiring IWLi[j], the first output terminal of circuit WCDi[j] is connected to wiring WLip[j], and the second output terminal of circuit WCDi[j] is connected to wiring WLin[j]. Furthermore, the input terminal of circuit WCDo is connected to wiring IWLo, the first output terminal of circuit WCDo is connected to wiring WLop, and the second output terminal of circuit WCDo is connected to wiring WLon. Also, the input terminal of circuit XDi is connected to wiring IXLi, and the output terminal of circuit XDi is connected to wiring XLi. Additionally, the input terminal of circuit XDR[h] is connected to wiring RXL[h], and the output terminal of circuit XDR[h] is connected to the first input terminal of selector SC[h]. Furthermore, the first input terminal of circuit ITSr[j] is connected to wiring WLip[j], the second input terminal of circuit ITSr[j] is connected to wiring WLin[j], and the output terminal of circuit ITSr[j] is connected to the second input terminal of selector SC[j]. Also, the output terminal of selector SC[h] is connected to wiring XLo[h]. 【0077】The drive circuit WSD is connected to wiring SLi and wiring SLo[1] through SLo[n]. The control terminal of selector SC[h] is connected to wiring CLS. 【0078】 Wiring IWLi[j] functions, for example, as wiring for transmitting the weight coefficient Wi between the input layer neurons and the reservoir layer neurons, or the weight coefficient Wr between neurons within the reservoir layer, from outside the arithmetic unit CDV to the input terminal of circuit WCDi[j]. Wiring IWLo also functions, for example, as wiring for transmitting the weight coefficient Wo between the reservoir layer neurons and the output layer neurons from outside the arithmetic unit CDV to the input terminal of circuit WCDo. 【0079】 Wiring IXLi, for example, functions as wiring for transmitting input values ​​(sometimes called input data) U input to the input layer from outside the arithmetic unit CDV to the input terminal of circuit XDi. Wiring IXLi also functions as wiring for transmitting first reference values ​​(sometimes called first reference data) Rf1 used for multiplication in each of the arithmetic circuits CCi[1] to CCi[n] of region CAi from outside the arithmetic unit CDV to circuit XDi. 【0080】 Furthermore, the wiring RXL[h] also functions, for example, as wiring for transmitting a second reference value (sometimes called second reference data) Rf2 used for multiplication in the arithmetic circuits CCr[h,1] to CCr[h,n] located in the h row of region Car, and the arithmetic circuit CCo[h] in region CAo, from outside the arithmetic unit CDV to the input terminal of circuit XDR[h]. 【0081】 The drive circuit WCD has the function of acquiring the weight coefficients used in the ESN from outside the calculation unit CDV, converting the weight coefficients into a signal, and transmitting the signal to the calculation circuits CCi, CCr, and CCo. The signal can be either a current signal or a potential signal. 【0082】Specifically, the circuit WCDi[j] provided in the drive circuit WCD will be described. Here, the weight coefficient Wi input to the input terminal of circuit WCDi[j] can be represented, for example, as two variables Wip and Win. Circuit WCDi[j] has the function of converting Wip and Win into signals, transmitting the signal corresponding to Wip to wiring WLip[j] via the first output terminal, and transmitting the signal corresponding to Win to wiring WLiN[j] via the second output terminal. Furthermore, the weight coefficient Wr input to the input terminal of circuit WCDi[j] can be represented, for example, as two variables Wrp and Wrn. Similarly, circuit WCDi[j] has the function of converting Wrp and Wrn into signals, transmitting the signal corresponding to Wrp to wiring WLip[j] via the first output terminal, and transmitting the signal corresponding to Wrn to wiring WLiN[j] via the second output terminal. 【0083】 Next, the circuit WCDo provided in the drive circuit WCD will be described. Here, the weight coefficient Wo input to the input terminal of circuit WCDo can be expressed as, for example, two variables Wop and Won. Circuit WCDo has the function of converting Wop and Won into signals, transmitting the signal corresponding to Wop to wiring WLop via the first output terminal, and transmitting the signal corresponding to Won to wiring WLon via the second output terminal. 【0084】 The drive circuit WSD has a function to send a selection signal to one of the wiring SLi and wiring SLo[1] to SLo[n] selected from wiring SLi and wiring SLo[1] to wiring SLo[n] in order to select the arithmetic circuits CCi, CCr, and CCo located in the arithmetic unit CA to which the weight coefficients will be written. Furthermore, when writing weight coefficients sequentially to the arithmetic circuits of each row of the arithmetic unit CA, the drive circuit WSD may also have a function to sequentially send selection signals to wiring SLi and wiring SLo[1] to wiring SLo[n]. 【0085】The drive circuit XCD has the function of acquiring the input value input to the ESN from outside the arithmetic unit CDV, converting the input value into a signal, and transmitting the signal to the arithmetic circuit CCi. This signal can be a current signal or a potential signal. The drive circuit XCD also has the function of acquiring a first reference value used in the multiplication of the arithmetic circuit CCi from outside the arithmetic unit CDV, converting the first reference value into a signal, and transmitting the signal to the drive cell DCi and the arithmetic circuit CCi, respectively. The drive circuit XCD also has the function of acquiring a second reference value used in the multiplication of the arithmetic circuits CCr and CCo, respectively, from outside the arithmetic unit CDV, converting the second reference value into a signal, and transmitting the signal to the drive cell DCo, the arithmetic circuit CCr, and the arithmetic circuit CCo, respectively. 【0086】 Specifically, the circuit XDi provided in the drive circuit XCD will be described. Circuit XDi has the function of converting the input value U input to the input terminal of circuit XDi into a signal and transmitting the signal from the output terminal of circuit XDi to wiring XLi. Circuit XDi also has the function of converting the first reference value Rf1 input to the input terminal of circuit XDi into a signal and transmitting the signal to wiring XLi via the output terminal. 【0087】 Next, the circuit XDR[h] provided in the drive circuit XCD will be described. The circuit XDR[h] has the function of converting the second reference value Rf2 input to the input terminal of the circuit XDR[h] into a signal and transmitting the said signal from the output terminal of the circuit XDR[h] to the first input terminal of the selector SC[h]. 【0088】 The drive circuit ITS has the function of adding the signal output from the arithmetic circuit CCi contained in region CAi and the signal output from the arithmetic circuit CCr contained in region Car, assigning the sum of these values ​​as a variable to the activation function, and outputting the calculation result of the activation function as a signal. In addition, the drive circuit ITS has the function of acquiring the signal output from the arithmetic circuit CCo contained in region CAo, assigning the value corresponding to this signal as a variable to the activation function, and outputting the calculation result of the activation function as a signal to the wiring OL. 【0089】Next, the circuit ITSr[j] provided in the drive circuit ITS will be described. Circuit ITSr[j] has the function of acquiring the difference between the signal flowing through the first input terminal of circuit ITSr[j] and the signal flowing through the second input terminal of circuit ITSr[j], and the function of substituting the value corresponding to this difference as a variable into the activation function, and outputting the calculation result of the activation function as a signal to the output terminal of circuit ITSr[j]. Here, the value of the calculation result will be Xo. In particular, this activation function corresponds to the activation function in the neurons of the reservoir layer. 【0090】 Similarly, circuit ITSo has the function of acquiring the difference between the signal flowing through the first input terminal of circuit ITSo and the signal flowing through the second input terminal of circuit ITSo, and inputting a value corresponding to the said difference into an activation function, and outputting the calculation result of the activation function as a signal to the output terminal of circuit ITSo. Here, the value of the calculation result is denoted as Y. In particular, the said activation function corresponds to the activation function in the neuron of the output layer. Furthermore, since circuit ITSo transmits the output signal of the arithmetic unit CDV, it is preferable that the said output signal is a digital signal. For this reason, it is preferable that circuit ITSo includes an analog-to-digital conversion circuit. Alternatively, acquiring the difference between the signal flowing through the first input terminal of circuit ITSo and the signal flowing through the second input terminal of circuit ITSo, and converting that difference from analog to digital, may be considered as the calculation of the activation function. 【0091】 The drive circuit SCD functions as a circuit for selecting a signal to be transmitted to the wiring XLo[h] extending to the calculation unit CA. As described above, the drive circuit SCD has selectors SC[1] to SC[n], and each of selectors SC[1] to SC[n] has the function of making one of the first input terminals and the second input terminal conduct to the output terminal, and making one of the first input terminals and the second input terminal conduct to the output terminal, in accordance with the control signal input to its control terminal. 【0092】The wiring CLS functions as wiring for transmitting the control signal to selector SC[h]. For example, the wiring CLS can make the first input terminal and output terminal conductive and the second input terminal and output terminal non-conductive by applying a high-level potential as a control signal to the control terminal of selector SC[h]. Alternatively, for example, the wiring CLS can make the first input terminal and output terminal non-conductive and the second input terminal and output terminal conductive by applying a low-level potential as a control signal to the control terminal of selector SC[h]. 【0093】 By configuring the drive circuit SCD as described above, it is possible to select either the signal output by circuit XDR[h] or the signal output by circuit ITSr[h] as the signal to be applied to wiring XLo[h]. 【0094】 The arithmetic cells MCp, each contained within the arithmetic circuits CCi, CCr, and CCo, have the function of acquiring signals transmitted from the drive circuit WCD as weight coefficients (Wip, Wrp, or Wop) and holding potentials corresponding to those signals. The arithmetic cells MCp also have the function of outputting a signal to the wiring WLip or WLop, which is the product of the value corresponding to the held potential and the value corresponding to the potential applied to the wiring XLi or XLo. Similarly, the arithmetic cells MCn, each contained within the arithmetic circuits CCi, CCr, and CCo, have the function of acquiring signals transmitted from the drive circuit WCD as weight coefficients (Win, Wrn, or Won) and holding potentials corresponding to those signals. The arithmetic cells MCn have the function of outputting a signal to the wiring WLin or WLon, which is the product of the value corresponding to the held potential and the value corresponding to the potential applied to the wiring XLi or XLo. 【0095】The drive cells DCi and DCo have the function of acquiring a signal transmitted from the drive circuit XCD as a reference value (Rf1 or Rf2), for example, and maintaining a potential corresponding to that signal. Furthermore, after the drive cell DCi has maintained the potential, when a signal corresponding to the input value U is transmitted to the drive cell DCi, the drive cell DCi has the function of maintaining the input potential and current corresponding to that signal. Similarly, after the drive cell DCo has maintained the potential, when a signal corresponding to the calculation result Xo from the drive circuit ITS is transmitted to the drive cell DCo, the drive cell DCo has the function of maintaining the input potential and current corresponding to that signal. 【0096】 As described above, by providing a function to store weight coefficients in the calculation cell, it becomes unnecessary to transmit weight coefficients from an external device (e.g., a memory device) when the weight coefficients are not rewritten. If the weight coefficients are read from an external memory device of the calculation unit CDV each time a calculation is performed in the calculation cell, the power consumption related to data transfer between the calculation unit and the memory device tends to be high. In one aspect of the present invention, by providing a function to store weight coefficients in the calculation cell, the amount of data transferred can be greatly reduced, and as a result, power consumption can be reduced. 【0097】 <<Example Configuration of the Drive Circuit WCD>> Next, an example configuration of the drive circuit WCD will be explained. Figure 2 is a circuit diagram showing an example configuration of the drive circuit WCD, and in particular, it shows the specific configuration of circuits WCDi[1] to WCDi[n] and circuit WCDo that are provided in the drive circuit WCD. 【0098】 Circuits WCDi[j] and WCDo have the same connection configuration. Therefore, unless otherwise specified, the description of circuit WCDo can be referred to in the description of circuit WCDi[j]. 【0099】 Circuit WCDi[j] includes, for example, circuit WDp, circuit WDn, switch SAp, and switch SAN. 【0100】In circuit WCDi[j], the input terminal of circuit WDp is connected to wiring IWip[j], the output terminal of circuit WDp is connected to the first terminal of switch SAp, and the second terminal of switch SAp is connected to wiring WLip[j]. Furthermore, the input terminal of circuit WDn is connected to wiring IWin[j], the output terminal of circuit WDn is connected to the first terminal of switch SAN, and the second terminal of switch SAN is connected to wiring WLin[j]. Additionally, the control terminal of switch SAp and the control terminal of switch SAN are connected to wiring CLA. 【0101】 Furthermore, in circuit WCDo, the input terminal of circuit WDp is connected to wiring IWop, and the input terminal of circuit WDn is connected to wiring IWon. Also, the second terminal of switch SAp is connected to wiring WLop, and the second terminal of switch SAN is connected to wiring WLon. 【0102】 In the drive circuit WCD shown in Figure 2, the wirings IWip[j] and IWin[j] are included in the wiring IWLi[j]. Similarly, the wirings IWop and IWon are included in the wiring IWLo. Therefore, each of the wirings IWLi[j] and IWLo can be treated as a wiring group. 【0103】 When the weight coefficient Wi is transmitted to the wiring IWLi[j] from outside the arithmetic unit CDV, one of the two variables representing the weight coefficient Wi, Wip, is transmitted to the wiring IWip[j], and the other variable, Win, is transmitted to the wiring IWin[j]. Similarly, when the weight coefficient Wr is transmitted to the wiring IWLi[j] from outside the arithmetic unit CDV, one of the two variables representing the weight coefficient Wr, Wrp, is transmitted to the wiring IWip[j], and the other variable, Wrn, is transmitted to the wiring IWin[j]. 【0104】Furthermore, when the weight coefficient Wo is transmitted to the wiring IWLo from outside the arithmetic unit CDV, one of the two variables representing the weight coefficient Wo, Wop, is transmitted to the wiring IWop, and the other of the two variables representing the weight coefficient Wo, Won, is transmitted to the wiring IWon. 【0105】 Electrical switches such as analog switches and transistors can be applied to each of the switches, SAp and SAN. In particular, it is preferable that transistors containing an oxide semiconductor in the channel formation region (also called OS transistors) are used as electrical switches for each of the switches, SAp and SAN. In particular, if it is desired that a larger current flows when the switch is ON, it is even more preferable that transistors with indium oxide as the oxide semiconductor (also called IO transistors) are used for both the switches, SAp and SAN. Indium oxide will be described in detail in Embodiment 4. When electrical switches are used for each of the switches, SAp and SAN, the electrical switches can be other than OS transistors, such as transistors containing silicon in the channel formation region (also called Si transistors). In addition, mechanical switches may be applied to each of the switches, SAp and SAN. 【0106】 In this specification, both switch SAp and switch SAN are assumed to be ON when a high-level potential signal is applied to their control terminals, and OFF when a low-level potential signal is applied to their control terminals. 【0107】 For example, the CLA wiring functions as a wire that transmits signals to control the switching between the on and off states of switches SAP and SAN, respectively. 【0108】When the drive circuit WCD writes weight coefficients to the calculation circuits CCi, CCr, and CCo included in the calculation unit CA, it turns on switches SAp and SAN, respectively, and transmits the weight coefficients to wiring WLip[j], WLin[j], WLop, and WLon. When the drive circuit WCD does not write weight coefficients to the calculation circuits CCi, CCr, and CCo included in the calculation unit CA, it turns off switches SAp and SAN, respectively, and sets the first and second output terminals of circuit WCDi[j] and the first and second output terminals of circuit WCDo to high impedance. 【0109】 In circuit WCDi, circuit WDp has the function of converting Wip input to the input terminal into a signal and transmitting that signal to the calculation cell MCp included in the calculation circuit CCi. Circuit WDn has the function of converting Win input to the input terminal into a signal and transmitting that signal to the calculation cell MCn included in the calculation circuit CCi. Circuit WDp also has the function of converting Wir input to the input terminal into a signal and transmitting that signal to the calculation cell MCp included in the calculation circuit CCr. Circuit WDn also has the function of converting Wrn input to the input terminal into a signal and transmitting that signal to the calculation cell MCn included in the calculation circuit CCr. 【0110】 Furthermore, in circuit WCDo, circuit WDp has the function of converting Wop input to the input terminal into a signal and transmitting the signal to the calculation cell MCp included in each of the calculation circuits CCo. Also, circuit WDn has the function of converting Won input to the input terminal into a signal and transmitting the signal to the calculation cell MCn included in each of the calculation circuits CCo. 【0111】Circuits WDp and WDn can each be, for example, a digital voltage-analog current circuit (sometimes simply referred to as a current DAC or IDAC). Figure 3 shows the circuit diagrams when circuits WDp and WDn are each an example of an IDAC, specifically a K-bit current ladder-type DAC (where K is an integer of 1 or more) that outputs current. Hereafter, circuits WDp and WDn will be collectively referred to as circuit WD. Furthermore, when circuit WD is a digital voltage-analog current circuit, the above-mentioned Wip, Win, Wrp, Wrn, Wop, and Won can each be treated as digital signals, and the signal output from circuit WD can be treated as a current signal. 【0112】 Circuit WD has K current sources, namely current sources CS[0] to CS[K-1] and a current mirror circuit CRM. The current source CS[k] shown in Figure 3 (where k is an integer between 0 and K-1) has transistors Tr1[k] and Tr2[k]. The current source CS[k] also has terminals T1 and T2. The current mirror circuit CRM has terminal CTi, which functions as an input terminal, and terminal CTo, which functions as an output terminal. Note that OS transistors, Si transistors, etc., can be used for transistors Tr1[k] and Tr2[k]. 【0113】 In particular, when an OS transistor is used for transistor Tr2[k], the off-current can be lower than in the case of a Si transistor, thus preventing the current output from the circuit WD from deviating from the desired amount due to the off-current. Furthermore, by using an IO transistor as the OS transistor, the on-current can be increased, thereby increasing the drive speed of the circuit WD. 【0114】 The current source CS[k] in Figure 3 functions as a current sink circuit that, for example, supplies current from terminal T1 to wiring VS1 via transistors Tr1 and Tr2. 【0115】In the current source CS[k], the first terminal of transistor Tr1[k] is electrically connected to wiring VS1, the second terminal of transistor Tr1[k] is connected to the first terminal of transistor Tr2[k], and the gate of transistor Tr1[k] is connected to wiring BIS. The gate of transistor Tr2[k] is also connected to wiring D[k] via terminal T2. Furthermore, the second terminal of transistor Tr2[k] is mutually connected to terminal CTi of the current mirror circuit CRM, which will be described later, via terminal T1. 【0116】 Furthermore, the source, drain, and gate of transistor Tr1[k] are assumed to be appropriately biased so that a subthreshold current flows between the source and drain of transistor Tr1[k]. For this reason, it is preferable that wiring VS1 and wiring BIS are wires that provide an appropriate fixed potential so that transistor Tr1[k] flows a subthreshold current. In particular, it is preferable that the fixed potential provided by wiring VS1 be lower than the potential provided by wiring VD1, which will be described later. The fixed potential can also be the ground potential, a negative potential, etc. 【0117】 Furthermore, in Figure 3, when the channel width of transistor Tr1[0] is w[0], the channel width of transistor Tr1[1] is w[1], and the channel width of transistor Tr1[K-1] is w[K-1], the ratio of their respective channel widths is w[0]:w[1]:w[K-1] = 1:2:2 Ｋ−１ In particular, the subthreshold current flowing through transistor Tr1[k] is proportional to the channel width of transistor Tr1[k]. For example, if the current flowing between the source and drain of transistor Tr1[0] is Iut, then the current flowing between the source and drain of transistor Tr1[1] is 2Iut, and the current flowing between the source and drain of transistor Tr1[K-1] is 2 Ｋ−１ It becomes Iut. 【0118】In circuit WD, wiring D[0] to D[K-1] are wirings that are included in wiring IWip[j], wiring IWLin[j], wiring IWop, or wiring IWon in Figure 2. Therefore, wiring IWip[j], wiring IWin[j], wiring IWop, and wiring IWon can each be treated as a wiring group. 【0119】 Furthermore, wiring D[k] functions as wiring for controlling the switching between the ON and OFF states of transistor Tr2[k]. In particular, by turning on transistor Tr2[k], the current source CS[k] is directed to terminal T1, and the current flowing between the source and drain of transistor Tr1[k] is 2 ｋ Iut is obtained. In other words, wiring D[k] is 2 from the connected current source CS[k]. ｋ This wiring functions as a signaling circuit for transmitting a control signal to output a constant current to Iut. 【0120】 As a result, circuit WD can supply a current to terminal CTi of the current mirror circuit CRM corresponding to the K-bit data sent from wiring D[0] to wiring D[K-1]. Specifically, for example, when a high-level potential is applied to wiring D[0], a constant current of Iut flows through terminal CTi of the current mirror circuit CRM. Also, for example, when a high-level potential is applied to wiring D[1], a constant current of 2Iut flows through terminal CTi of the current mirror circuit CRM. Furthermore, for example, when high-level potentials are applied to both wiring D[0] and wiring D[1], a constant current of 3Iut flows through terminal CTi of the current mirror circuit CRM. As described above, circuits WDp and WDn shown in Figure 3 can output a current corresponding to a weighting coefficient by inputting K-bit digital data as a weighting coefficient to each of wiring D[0] to wiring D[K-1]. The current in question is the current that flows when each of the transistors M3d, M3p, and M3n shown in Figure 5A operates in the subthreshold region. 【0121】Next, the current mirror circuit CRM will be explained. As an example, the current mirror circuit CRM has the function of outputting a current to terminal CTo that is approximately equal in amount to the current flowing through terminal CTi. In particular, in circuit WD, the current mirror circuit CRM plays the role of converting the sink current generated by the current source CS[k] into an output current and outputting it to the output terminal of circuit WD. 【0122】 The current mirror circuit CRM includes p-channel transistors Tr5, Tr5m, Tr6, and Tr6m. Since these transistors are p-channel transistors, it is preferable to use Si transistors, which are easy to manufacture. Furthermore, because Si transistors have a high on-current, using them can speed up the operation of the circuit WD. Additionally, Si transistors can reduce the influence of random telegraph noise, thus reducing the noise contained in the source-drain current output by the Si transistors. In other words, using Si transistors stabilizes the output current of the current mirror circuit CRM. 【0123】 By applying Si transistors to transistors Tr5, Tr5m, Tr6, and Tr6m, when Si transistors are used for transistors Tr1[k] and Tr2[k] as described above, they can be fabricated simultaneously by the Si process along with transistors Tr5, Tr5m, Tr6, and Tr6m, thereby reducing the cycle time for fabricating the circuit WD. 【0124】The first terminal of transistor Tr5 is connected to terminal CTi, the gate of transistor Tr6, and the gate of transistor Tr6m. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr6. The gate of transistor Tr5 is connected to the gate of transistor Tr5m and wiring VE4. The second terminal of transistor Tr6 is connected to wiring VD1. The first terminal of transistor Tr5m is connected to terminal CTo. The second terminal of transistor Tr5m is connected to the first terminal of transistor Tr6m. The second terminal of transistor Tr6m is connected to wiring VD1. 【0125】 Wiring VD1 functions, for example, as wiring that provides a fixed potential. This fixed potential is preferably higher than the potential provided by wiring VS1, and is preferably a positive potential or a high-level potential. 【0126】 In the current mirror circuit CRM, the second terminals of transistors Tr6 and Tr6m are supplied with a potential from wiring VD1, and the gates of transistors Tr6 and Tr6m are supplied with the potential from terminal CTi. Therefore, ideally, approximately equal amounts of current flow between the source and drain of transistors Tr6 and Tr6m. 【0127】 Furthermore, transistor Tr5 functions as a clamp transistor cascode-connected to transistor Tr6. Similarly, transistor Tr5m functions as a clamp transistor cascode-connected to transistor Tr6m. For this reason, wiring VE4, which provides a desired bias potential, is connected to the gates of transistors Tr5 and Tr5m. Wiring VE4 functions, for example, as wiring that provides a fixed potential. This fixed potential can be a low-level potential, ground potential, negative potential, etc. Also, depending on the situation, this fixed potential may be a high-level potential, etc. 【0128】This prevents the potential of terminal CTi from being directly input to the first terminal of transistor Tr6. In other words, it prevents the potential of the first terminal of transistor Tr6 from fluctuating suddenly, and stabilizes the operation of the current mirror circuit CRM. Furthermore, transistors Tr5 and Tr5m prevent a decrease in threshold voltage caused by drain-induced barrier lowering (DIBL) in transistors Tr6 and Tr6m. 【0129】 <<Example of the configuration of the drive circuit XCD>> Next, an example of the circuit configuration of each of the circuits XDi and XDR[1] to XDR[n] provided in the drive circuit XCD will be explained using Figure 4. 【0130】 Circuit XDi has the function of converting the input value U input to the input terminal into a signal and transmitting the signal to the drive cell DCi and the calculation cells MCp and MCn included in the calculation circuit CCi. Circuit XDi also has the function of converting the first reference value Rf1 input to the input terminal into a first reference signal and transmitting the first reference signal to the drive cell DCi and the calculation cells MCp and MCn included in the calculation circuit CCi. 【0131】 Furthermore, circuit XDR[h] has the function of converting the second reference value Rf2 input to the input terminal into a second reference signal, and transmitting the second reference signal via the first input terminal-output terminal of selector SC[h] to the drive cell DCo[h], the calculation cells MCp and MCn included in the calculation circuit CCr located in the h row of region Car, and the calculation cells MCp and MCn included in the calculation circuit CCo[h]. 【0132】Circuit XDi and circuits XDR[1] through XDR[n] can each be an IDAC, for example, similar to circuit WD described above. Therefore, the K-bit current-type ladder DAC shown in Figure 3 can be used for each of circuits XDi and XDR[1] through XDR[n]. Specifically, each of circuits XDi and XDR[1] through XDR[n] can be configured as circuit XD shown in Figure 4. Hereafter, circuits XDi and XDR[1] through XDR[n] will be collectively referred to as circuit XD. 【0133】 In circuit XD, wirings D[0] to D[K-1] are wirings that are included in wiring IXLi or wiring RXL[h] in Figure 1. Therefore, wirings IXLi and RXL[h] can each be treated as a group of wirings. 【0134】 Furthermore, when the circuit XDi in Figure 1 is replaced with the circuit XD in Figure 4, the terminal CTo of the current mirror circuit CRM is connected to the wiring XLi. As a result, circuit XDi can supply current to wiring XLi corresponding to the input value U when K bits of digital data are input as input value U to each of the wirings D[0] to D[K-1]. In addition, circuit XDi can supply current to wiring XLi corresponding to the first reference value Rf1 when K bits of digital data corresponding to the first reference value Rf1 are input to each of the wirings D[0] to D[K-1]. 【0135】 Furthermore, when the circuit XDR[h] in Figure 1 is replaced with the circuit XD in Figure 4, the terminal CTo of the current mirror circuit CRM is connected to the first input terminal of the selector SC[h]. As a result, the circuit XDR[h] can supply a current corresponding to the second reference value Rf2 to the first input terminal of the selector SC[h] by inputting K bits of digital data as the second reference value Rf2 to each of the wirings D[0] to D[K-1]. 【0136】 <<Examples of configurations for drive cell DC and arithmetic circuit CC>> This section describes examples of configurations for drive cell DCi and drive cell DCo, and examples of configurations for arithmetic circuits CCi, CCr, and CCo. 【0137】 Figure 5A shows an example configuration of drive cell DCi and drive cell DCo, which is drive cell DCi, and an example configuration of arithmetic circuit CCi, arithmetic circuit CCr, and arithmetic circuit CCo, which is arithmetic circuit CC. In particular, Figure 5A shows example configurations of arithmetic cell MCp and arithmetic cell MCn included in arithmetic circuit CC. Also in Figure 5A, an example configuration is shown in which drive cell DCi and arithmetic circuit CC are connected to wiring XL and wiring SL on the same row. For this reason, the drive cell DC and arithmetic circuit CC in Figure 5A can be considered as a combination of drive cell DCi and arithmetic circuit CCi[j], a combination of drive cell DCo[h] and arithmetic circuit CCr[h,j], and a combination of drive cell DCo[h] and arithmetic circuit CCo[h]. 【0138】 Wiring XL corresponds to wiring XLi or wiring XLo[h] in Figure 1. Wiring SL corresponds to wiring SLi or wiring SLo[h] in Figure 1. Wiring WLp and wiring WLn correspond to wiring WLip[j] and wiring WLin[j], or wiring WLop and wiring WLon, in Figure 1. 【0139】 For example, the calculation cell MCp includes transistors M1p, M3p, M4p, and a capacitive element C1p. For example, the calculation cell MCn includes transistors M1n, M3n, M4n, and a capacitive element C1n. For example, the drive cell DC includes transistors M1d, M3d, M4d, and a capacitive element C1d. 【0140】In the drive cell DC, arithmetic cell MCp, and arithmetic cell MCn, each of transistors M1d, M1p, and arithmetic cell M1n functions, for example, as a switching transistor (also called a writing transistor or holding transistor). Furthermore, each of transistors M3d, M3p, and M3n functions, for example, as a transistor for outputting the multiplication result of a multiplier and a multiplicand (sometimes called an amplifying transistor). Transistor M4d functions, for example, as a clamping transistor to prevent a drop in the threshold voltage of transistor M3d due to DIBL. Similarly, transistor M4p functions, for example, as a clamping transistor to prevent a drop in the threshold voltage of transistor M3p due to DIBL. Also, transistor M4n functions, for example, as a clamping transistor to prevent a drop in the threshold voltage of transistor M3n due to DIBL. 【0141】 Unless otherwise specified, the operation of transistors M1d, M1p, and M1n to be ON includes the case where they ultimately operate in the linear region. That is, the operation of these transistors includes the case where the gate, source, and drain are appropriately biased with voltages that operate in the linear region. However, one aspect of the present invention is not limited thereto. For example, one or more selected transistors may operate in the saturation region when ON, or they may operate in a mixture of the linear region and the saturation region. 【0142】The operations of transistor M3d, transistor M3p, and transistor M3n shall include, unless otherwise specified, the case of operating in the subthreshold region (that is, when the gate-source voltage is lower than the threshold voltage in each of transistor M3p, transistor M3n, and transistor M3d, and more preferably, when the drain current increases exponentially with respect to the gate-source voltage). That is, the operations of these transistors shall include the case where appropriate voltages for operating in the subthreshold region are applied to the gate, source, and drain. For this reason, these transistors shall include the case of operating such that an off-current (sometimes called a leakage current) flows between the source and drain. 【0143】 In FIG. 5A, for each of transistor M1d, transistor M3p, transistor M4p, transistor M1p, transistor M3p, transistor M4p, transistor M1n, transistor M3n, and transistor M4n, transistors applicable to the above-described transistor T1[k] and transistor T2[k] can be used. 【0144】 For example, it is preferable to use an OS transistor for the transistors included in the drive cell DC and the arithmetic circuit CC. The OS transistor has a characteristic of extremely small off-current. In particular, it is preferable to use an IO transistor among the OS transistors. The IO transistor has a large on-current among the OS transistors. For this reason, the IO transistor has a characteristic that the ratio of the on-current to the off-current is 1.0×10 １７ or higher. By applying the IO transistor to the transistor, malfunction due to current leakage can be prevented, and the driving speed can be increased by the on-current. Indium oxide will be described in detail in Embodiment 4. 【0145】 Also, as an example, the range of the subthreshold current per 1-μm channel width of the IO transistor is 1 aA (1×10 −１８ A) or more and 0.1 A or less, or 1 zA (1×10 −２１A) More than 0.1mA (1×10 −４ A) Since the above is true, by using an IO transistor in the arithmetic circuit CC, the range of current that can be output as a result of multiplication in the arithmetic circuit CC can be widened. More precisely, within the above subthreshold current range, the range in which the drain current increases exponentially with respect to the gate-source voltage is the range of current that can be output as a result of multiplication in the arithmetic circuit CC. 【0146】 For example, if the multiplier and multiplicand are both between 0 and 255, and the current when either the multiplier or multiplicand is 1 is 0.01 nA, then the range of the output current that the transistor must maintain as a result of multiplication will be between 0 and 650.25 nA, which can be kept within the above-mentioned subthreshold current range. 【0147】 Furthermore, in addition to OS transistors, Si transistors can be used for the transistors included in the drive cell DC and the arithmetic circuit CC. As mentioned above, Si transistors can reduce the effects of random telegraph noise, and therefore can reduce the noise contained in the source-drain current output by Si transistors. In other words, by using Si transistors for these transistors, the output current of the drive cell DC or the arithmetic circuit CC can be stabilized. 【0148】 Furthermore, drive circuits WCD, XCD, WSD, SCD, and ITS can be configured as CMOS (Complementary MOS) circuits using Si transistors to reduce circuit area and increase drive speed. In this case, these drive circuits are formed on a semiconductor substrate made of silicon. By using Si transistors for the transistors included in the drive cell DC and arithmetic circuit CC, they can be manufactured simultaneously with the drive circuits, thereby shortening the cycle time of the semiconductor device. 【0149】Since transistors M1p, M1n, and M1d are switching transistors, it is preferable that their off-currents are small. By reducing these off-currents, the data retention time held by the arithmetic cells MCp, MCn, and DC can be increased, and the number of data refreshes can be reduced. This reduces the power consumption of the arithmetic unit CDV. Since OS transistors have the characteristic of having extremely small off-currents, it is preferable to use OS transistors for these transistors. 【0150】 Furthermore, since transistors M3p, M3n, and M3d are all amplifying transistors, it is preferable that the on-current in these transistors is large. By increasing the on-current, the current flowing through the wiring increases, and the rate at which charge accumulates in the wiring, terminals, etc., can be increased. By increasing the rate at which charge accumulates in the wiring, terminals, etc., the drive speed of the arithmetic unit CDV can be increased. Since I / O transistors have the characteristic of having a large on-current, it is preferable to use I / O transistors in each of these transistors. 【0151】In Figure 5A, transistors M1d, M3d, M4d, M1p, M3p, M4p, M1n, M3n, and M4n are shown as n-channel transistors, but they may be changed to p-channel transistors depending on the situation. In this case, the potentials supplied to the calculation cells MCp, MCn, and DC may differ from those in the case of n-channel transistors. It should also be noted that when these transistors are n-channel, the calculation cells MCp, MCn, and DC each function as current-drawing circuits, but when these transistors are p-channel, the calculation cells MCp, MCn, and DC each function as current-discharge circuits. In this specification, unless otherwise specified, each of these transistors is described as an n-channel transistor. 【0152】 The first terminal of transistor M1p is connected to the gate of transistor M3p and the first terminal of capacitive element C1p, and the first terminal of transistor M3p is connected to the first terminal of transistor M4p. The second terminal of transistor M3p is connected to wiring VLE, ​​and the gate of transistor M4p is connected to wiring VBE. The second terminal of transistor M1p and the second terminal of transistor M4p are connected to wiring WLp. The second terminal of capacitive element C1p is connected to wiring XL. The gate of transistor M1p is connected to wiring SL. 【0153】Furthermore, the first terminal of transistor M1n is connected to the gate of transistor M3n and the first terminal of capacitive element C1n, and the first terminal of transistor M3n is connected to the first terminal of transistor M4n. Also, the second terminal of transistor M3n is connected to wiring VLE, ​​and the gate of transistor M4n is connected to wiring VBE. Furthermore, the second terminal of transistor M1n and the second terminal of transistor M4n are connected to wiring WLn. Also, the second terminal of capacitive element C1n is connected to wiring XL. Also, the gate of transistor M1n is connected to wiring SL. 【0154】 Furthermore, the first terminal of transistor M1d is connected to the gate of transistor M3d and the first terminal of capacitive element C1d, and the first terminal of transistor M3d is connected to the first terminal of transistor M4d. Also, the second terminal of transistor M3d is connected to wiring VLE, ​​and the gate of transistor M4d is connected to wiring VBE. Furthermore, the second terminal of transistor M1d, the second terminal of transistor M4d, and the second terminal of capacitive element C1d are connected to wiring XL. Also, the gate of transistor M1d is connected to wiring SL. 【0155】 In this specification, the connection point between the first terminal of transistor M1p, the gate of transistor M3p, and the first terminal of capacitive element C1p is referred to as node Np, the connection point between the first terminal of transistor M1n, the gate of transistor M3n, and the first terminal of capacitive element C1n is referred to as node Nn, and the connection point between the first terminal of transistor M1d, the gate of transistor M3d, and the first terminal of capacitive element C1d is referred to as node Nd. 【0156】The VLE wiring, as an example, functions as wiring that provides a fixed potential. Specifically, the VLE wiring functions as wiring that provides the fixed potential to the second terminals of transistors M3d, M3p, and M3n. In particular, the fixed potential is the potential that drives each of transistors M3d, M3p, and M3n in the subthreshold region. The fixed potential can be, for example, a low-level potential, ground potential, or negative potential. Furthermore, the fixed potential may be equal to the fixed potential provided by wiring VS1. In this case, the VLE wiring can be grouped together with wiring VS1 as the same wiring. Depending on the situation, the fixed potential provided by the VLE wiring can be a high-level potential, a positive potential, or the like. 【0157】 The VBE wiring, for example, functions as wiring that provides a fixed potential. This fixed potential can be, for example, a high-level potential or a positive potential. Depending on the situation, the fixed potential provided by the VBE wiring can be a low-level potential, ground potential, a negative potential, or the like. 【0158】 In Figure 5A, if the effect of DIBL is small for each of transistors M3d, M3p, and M3n, then it is not necessary to provide transistor M4d in the drive cell DC, transistor M4p in the calculation cell MCp, and transistor M4n in the calculation cell MCn. The drive cell DC and calculation circuit CC shown in Figure 5B are modified versions of Figure 5A, in which transistor M4d is not provided in the drive cell DC, and transistors M4p and M4n are not provided in the calculation circuit CC. In other words, in the drive cell DC and calculation circuit CC of Figure 5B, the first terminal of transistor M3d is directly connected to the second terminal of transistor M1d and wiring XL, the first terminal of transistor M3p is directly connected to the second terminal of transistor M1p and wiring WLp, and the first terminal of transistor M3n is directly connected to the second terminal of transistor M1n and wiring WLn. 【0159】The drive cell DC and arithmetic circuit CC in Figure 5B have fewer circuit elements than the drive cell DC and arithmetic circuit CC in Figure 5A. Therefore, the drive cell DC and arithmetic circuit CC in Figure 5B can have a smaller circuit area than the drive cell DC and arithmetic circuit CC in Figure 5A. 【0160】 [Example of operation of the drive cell DC and arithmetic circuit CC] Next, an example of the arithmetic operation by the drive cell DC and arithmetic circuit CC shown in Figure 5A will be explained. 【0161】 Figures 6A to 6C are timing charts showing an example of the calculation operation of the drive cell DC and the arithmetic circuit CC in Figure 5A. Figure 6A is the timing chart when the weight coefficient written to the arithmetic circuit CC is a positive value, Figure 6B is the timing chart when the weight coefficient written to the arithmetic circuit CC is a negative value, and Figure 6C is the timing chart when the weight coefficient written to the arithmetic circuit CC is 0. 【0162】 The timing charts in Figures 6A to 6C show the time evolution of the source-drain currents IM3p, IM3n, and IM3d of transistors M3p, M3n, and M3d, respectively, from time T01 to time T07 and in the vicinity of those times. Each timing chart also shows the potential change of the wiring SL. 【0163】 Furthermore, in the timing charts of Figures 6A to 6C, the name of the current and the type of wiring are listed on the left side, and the magnitude of the current and the potential height are listed on the right side. In particular, "High" in these timing charts means a high-level potential in that wiring, and "Low" means a low-level potential in that wiring. The same applies to the timing charts of Figures 10 and 16, which will be described later. 【0164】At time T01, a high-level potential is applied to wiring SL. As a result, transistors M1d, M1p, and M1n are all turned on. Also at time T01, drive circuit WCD does not supply current to wiring WLp and WLn, and drive circuit XCD does not supply current to wiring XL. 【0165】 At time T02, the drive circuit XCD, for example, using the circuit XD shown in Figure 4, sends a current Rf × Iut as a signal to the wiring XL, corresponding to a reference value Rf (for example, Rf is an integer of 1 or more). The reference value Rf corresponds to the first reference value Rf1 or the second reference value Rf2 mentioned above. As a result, the source-drain current of transistor M3d becomes Rf × Iut. Also, at time T02, the gate of transistor M3d is conducting to the first terminal, so the potential of the gate of transistor M3d is determined accordingly so that the source-drain current IM3d is Rf × Iut. Specifically, the gate-source voltage of transistor M3d is determined so that the source-drain current IM3d of transistor M3d is Rf × Iut. Rf × Iut is the current that flows when transistor M3d is operating in the subthreshold region. 【0166】 Here, the gate potential of transistor M3d and the potential of wiring XL are set to V. ｇｍ Let (Rf) be the potential of the wiring VLE. Ｎ In this case, Rf × Iut can be expressed as shown in equation (1.1) below. 【0167】 【0168】 Note V ｔｈ is the threshold voltage of transistor M3d, and I ａ V is the gate-source voltage of transistor M3d. ｇｍ (Rf)-V Ｎ ga V ｔｈ This is the current that flows when it is equal to [a certain value]. 【0169】 Furthermore, by defining Iut as shown in equation (1.2), Rf can be expressed as shown in equation (1.3). 【0170】 【0171】 At time T03, for example, the drive circuit WCD performs an operation to write the weight coefficient to the calculation circuit CC. The weight coefficient can be a positive value, zero, or a negative value, and the data writing operation to calculation cells MCp and MCn differs depending on the case. 【0172】 When the weighting coefficient is a positive value W (for example, W is an integer greater than or equal to 1) (as in Figure 6A), the drive circuit WCD, using the circuit WD shown in Figure 3, sends a current W × Iut corresponding to W through the wiring WLp as a signal, and does not send current through the wiring WLn. As a result, the source-drain current IM3p of transistor M3p becomes W × Iut. Also, at time T03, since the gate of transistor M3p and the first terminal are conducting, the potential of the gate of transistor M3p is determined accordingly so that the source-drain current IM3p becomes W × Iut. Specifically, the gate-source voltage of transistor M3p is determined so that the source-drain current IM3p of transistor M3p becomes W × Iut. Note that W × Iut is the current that flows when transistor M3p operates in the subthreshold region. 【0173】 Here, the gate potential of transistor M3p is V. ｇ When (W) is denoted as such, W × Iut can be expressed as shown in equation (1.4) below. 【0174】 【0175】 For the sake of simplicity, let's look at I shown in equation (1.2). ａ , V Ｎ and V ｔｈ Each of these is I shown in equation (1.1) ａ , V Ｎ and V ｔｈ Assume that it is equal to . 【0176】 Furthermore, by using equation (1.2), W can be expressed as shown in equation (1.5). 【0177】 【0178】 Similarly, since there is conduction between the gate and the first terminal of transistor M3n, the potential of the gate of transistor M3n is set such that the source-drain current IM3n is 0A. 【0179】 Furthermore, when the weighting coefficient is a negative value -W (as in Figure 6B), the drive circuit WCD, using the circuit WD shown in Figure 3, sends a current W × Iut corresponding to -W through the wiring WLn as a signal, and does not send current through the wiring WLp. As a result, the source-drain current IM3n of transistor M3n becomes W × Iut. Also, at time T03, since there is conduction between the gate and the first terminal of transistor M3n, the potential of the gate of transistor M3n is determined so that the source-drain current IM3n becomes Iw. Specifically, the gate-source voltage of transistor M3n is determined so that the source-drain current IM3n of transistor M3n becomes W × Iut. Note that W × Iut is the current that flows when transistor M3n operates in the subthreshold region. Also, W × Iut can be expressed as shown in equation (1.4) above. 【0180】 Similarly, since there is conduction between the gate and the first terminal of transistor M3p, the potential of the gate of transistor M3p is set such that the source-drain current IM3p is 0A. 【0181】 Furthermore, when the weighting coefficient is 0 (as in Figure 6C), the drive circuit WCD does not supply current to wiring WLp and wiring WLn. As a result, the source-drain current of transistors M3p and M3n becomes 0A. At this time, the gate potentials of transistors M3p and M3n are set so that the source-drain current becomes 0A. 【0182】At time T04, a low-level potential is applied to the wiring SL. This causes transistors M1d, M1p, and M1n to turn off. As a result, the gates of transistors M3d, M3p, and M3n become floating. In particular, the gate potential V of transistor M3d corresponds to the reference value Rf. ｇｍ (Rf) is held by the capacitive element C1d, and the gate potential of transistor M3p corresponding to the weighting coefficient is held by the capacitive element C1p, and the gate potential of transistor M3n corresponding to the weighting coefficient is held by the capacitive element C1n. 【0183】 At time T05, the signal output (current supply) from the drive circuit XCD to wiring XL stops. Also, the signal output (current supply) from the drive circuit WCD to wirings WLp and WLn stops. At this time, the potential of wiring XL becomes lower than when the current Rf × Iut was flowing through wiring XL. Furthermore, since the gate of transistor M3d is in a floating state, the capacitive coupling by the capacitive element C1d causes the gate potential of transistor M3d to decrease as the potential of wiring XL decreases. As a result, the current IM3d flowing between the source and drain of transistor M3d is assumed to be 0A. 【0184】 Similarly, since the gates of transistors M3p and M3n are also floating, the capacitive coupling by capacitive elements C1p and C1n causes the gate potentials of transistors M3p and M3n to decrease as the potential of wiring XL decreases. As a result, the source-drain current IM3p of transistor M3p and the source-drain current IM3n of transistor M3n become 0A. 【0185】At time T06, a current X × Iut, corresponding to the input value X (a positive number for example), is sent as a signal from the output terminal of the drive circuit XCD or the output terminal of the drive circuit ITS to the wiring XL. As the current X × Iut flows through the wiring XL, the potential of the wiring XL changes. Also, since the gate of transistor M3d is in a floating state, the potential of the gate of transistor M3d changes in accordance with the change in the potential of the wiring XL due to capacitive coupling by the capacitive element C1d. Furthermore, the potential of the gate of transistor M3d is set so that the source-drain current IM3d of transistor M3d is X × Iut. In other words, drive cells DC and DCo maintain the current X × Iut flowing from the output terminal of the drive circuit XCD or the output terminal of the drive circuit ITS to the wiring XL. Also, since the current flowing through the wiring XL is maintained at X × Iut, the potential of the wiring XL is also maintained at a height corresponding to that current. Note that X × Iut is the current that flows when transistor M3d operates in the subthreshold region. 【0186】 Here, the potential of the wiring XL is V ｇｍ When (X) is the value, X × Iut can be expressed as shown in equation (1.6) below. 【0187】 【0188】 Furthermore, by using equations (1.1) and (1.6), we can derive equation (1.7) below. 【0189】 【0190】 Furthermore, since the gate of transistor M3p is also floating, the capacitive coupling of the capacitive element C1p causes the gate potential of transistor M3p to change in accordance with the change in the potential of wiring XL. Similarly, since the gate of transistor M3n is also floating, the capacitive coupling of the capacitive element C1n causes the gate potential of transistor M3n to change in accordance with the change in the potential of wiring XL. Specifically, the potential of wiring XL changes from time T04 to V ｇｍ (X) - V ｇｍSince only (Rf) changes, the gate potentials of transistors MN3p and MN3n also change to V. ｇｍ (X) - V ｇｍ Only (Rf) changes. 【0191】 In particular, when a positive weighting coefficient W is written to the arithmetic circuit CC (as in Figure 6A), the source-drain current IM3p of transistor M3p changes as shown in equation (1.8) below, due to the change in the gate potential of transistor M3p. 【0192】 【0193】 By using equations (1.5) and (1.7), equation (1.8) can be transformed into equation (1.9) below. 【0194】 【0195】 In other words, as shown in equation (1.9), the current IM3p flowing between the source and drain of transistor M3p is proportional to W・X / Rf. Furthermore, by setting Rf = 1, the product of W and X can be obtained from the current IM3p. 【0196】 Furthermore, from time T06 to time T07, the gate potential of transistor MN3n was also V ｇｍ (X) - V ｇｍ Even if only (Rf) changes, the source-drain current IM3n of transistor M3n remains unchanged at 0A. 【0197】 Furthermore, if a negative weighting coefficient -W is written to the arithmetic circuit CC (as in Figure 6B), the change in the potential of the gate of transistor M3n due to the change in the potential of the wiring XL causes the source-drain current IM3n of transistor M3n to be (W・X / Rf) × Iut, similar to equation (1.9). Also, the source-drain current IM3p of transistor M3p is assumed to remain unchanged at 0A. 【0198】Furthermore, if a weight coefficient of 0 is written to the arithmetic circuit CC (as in Figure 6C), the source-drain current IM3p of transistor M3p and the source-drain current IM3n of transistor M3n will remain unchanged at 0A due to the change in the gate potential of transistors M3p and M3n, respectively, caused by the change in the potential of the wiring XL. 【0199】 Furthermore, although not shown in the timing charts of Figures 6A to 6C, when the input value X is 0, for example, at time T06, no current can be supplied to the wiring XL from the output terminal of the drive circuit XCD or the output terminal of the drive circuit ITS. As a result, the potential of the wiring XL remains the same from time T05 to time T06, and the source-drain current IM3p of transistor M3p and the source-drain current IM3n of transistor M3n can each be set to 0A. 【0200】 Between time T06 and time T07, current flows from the arithmetic circuit CC to the wires WLp and WLn according to the result of the multiplication. Furthermore, the result of the multiplication can be read by taking the difference between the currents flowing through the wires WLp and WLn, respectively, using the circuit ITSr or circuit ITSo described later. 【0201】 Furthermore, by arranging multiple arithmetic circuits CC in a column direction as shown in the arithmetic unit CA in Figure 1, the results of multiplication performed by each of the multiple arithmetic circuits CC can be added together as current. In other words, the arithmetic unit CA can perform a sum-of-products operation. For this reason, it can be said that the arithmetic cells MCp and MCn included in the arithmetic circuit CC have the function of adding the current flowing to the input terminals of circuit ITSr or circuit ITSo. 【0202】 At time T07, the signal output (current supply) from the drive circuit XCD to the wiring XL stops. This allows the input of the input value X to be stopped, and the multiplication operation in the arithmetic circuit CC can be stopped. Alternatively, a different value can be input as X after this point, and another multiplication operation may be performed. 【0203】<<Example Configuration of the Drive Circuit ITS>> Next, an example of the circuit configuration of circuits ITSr[1] to ITSr[n] and circuit ITSo shown in Figure 1 will be described. Figure 7A is a circuit diagram showing an example configuration of the drive circuit ITS, and in particular, it shows the specific configuration of circuits ITSr[1] to ITSr[n] and circuit ITSo provided in the drive circuit ITS. 【0204】 Circuit ITSr[j], for example, includes circuit RL, switch SBp, and switch SBn. Similarly, circuit ITSo, for example, includes circuit RLC, switch SBp, and switch SBn. Circuit ITSr[j], for example, has the function of transmitting the results calculated in the reservoir layer to the reservoir layer and the output layer, and circuit ITSo, for example, has the function of converting the results calculated in the output layer from analog to digital. 【0205】 Note that circuit ITSo may have the same circuit configuration as circuit ITSr[j]. In this case, the circuit configuration of circuit ITSo can be described by referring to the explanation of circuit ITSr[j]. 【0206】 In circuit ITSr[j], the first terminal of switch SBp is connected to wiring WLip[j], and the second terminal of switch SBp is connected to the first input terminal of circuit RL. Also, the first terminal of switch SBn is connected to wiring WLin[j], and the second terminal of switch SBn is connected to the second input terminal of circuit RL. Furthermore, the output terminal of circuit RL is connected to the second input terminal of selector SC[j] as the output terminal of circuit ITSr[j], as shown in Figure 1 (not shown in Figure 7A). In addition, the control terminal of switch SBp and the control terminal of switch SBn are connected to wiring CLB. 【0207】 Furthermore, in circuit ITSo, the first terminal of switch SBp is connected to wiring WLop, and the first terminal of switch SBn is connected to wiring WLon. Also, the output terminal of circuit RL is connected to wiring OL as the output terminal of circuit ITSo. 【0208】For switches SBp and SBn, refer to the descriptions of switches SAP and SAN above. Therefore, each of switches SBp and SBn can be a switch that is applicable to switch SAP or switch SAN as described above. 【0209】 For example, wiring CLB, similar to wiring CLA, functions as wiring that transmits signals to control the switching between the on and off states of switches SBp and SBn, respectively. 【0210】 Circuit ITSr[j] has a circuit RL that performs calculations on an activation function as a function system (for example, a nonlinear function system). In particular, it is preferable that the circuit RL that performs calculations on the function system has the function of performing calculations on the function system with a value corresponding to the input current as a variable, and outputting a signal (current signal or potential signal) according to the result of the calculation. Examples of activation functions include nonlinear functions such as the sigmoid function, tanh function, softmax function, ReLU function, or threshold function. 【0211】 For example, circuit RL has the function of acquiring the difference between the current flowing through the first input terminal and the current flowing through the second input terminal, inputting a value corresponding to that difference into an activation function, and outputting the calculation result of the activation function as a signal to the output terminal of circuit RL. 【0212】 Furthermore, the circuit RL acquires the difference by turning on switches SBp and SBn. For example, when switch SBp is turned on, conduction occurs between the first input terminal of circuit RL and the wiring WLip[j], and the current flowing through wiring WLip[j] flows to the first input terminal of circuit RL. Similarly, when switch SBn is turned on, conduction occurs between the second input terminal of circuit RL and the wiring WLin[j], and the current flowing through wiring WLin[j] flows to the second input terminal of circuit RL. When circuit RL is not acquiring the difference, switches SBp and SBn are turned off, and the first and second input terminals of circuit ITSr[j] are set to high impedance. 【0213】 If the activation function calculated by circuit RL is the ReLU function, then circuit RL can have the circuit configuration shown in Figure 7B. 【0214】 The circuit RL shown in Figure 7B includes, as an example, transistors MP1i, MP1o, MP2i, MP2o, MP3i, MP3o, MP4i, MP4o, MN1i, MN1o, MN2i, and MN2o. 【0215】 In the circuit RL shown in Figure 7B, a first current mirror circuit is formed by p-channel transistors MP1i, MP2i, MP1o, and MP2o. A second current mirror circuit is formed by n-channel transistors MN1i, MN2i, MN1o, and MN2o. A third current mirror circuit is formed by p-channel transistors MP3i, MP4i, MP3o, and MP4o. Since the circuit RL includes the first through third current mirror circuits, it is sometimes called a three-stage current mirror circuit. In addition, the circuit RL in Figure 7B is configured so that discharge current flows through both the input and output terminals. 【0216】 Furthermore, the p-channel transistors included in the circuit RL of Figure 7B can be Si transistors, similar to transistors Tr5, Tr5m, Tr6, and Tr6m included in the current mirror circuit CRM of Figure 4. In this case, it is preferable to use Si transistors for the p-channel transistors included in the circuit RL as well. By using Si transistors for the aforementioned transistors included in the circuit RL, they can be manufactured simultaneously using the Si process, thereby reducing the cycle time required to manufacture the circuit RL. 【0217】 In addition, depending on the circumstances, an OS transistor may be used for the n-channel transistor included in circuit RL. For example, an OS transistor may be used for the n-channel transistor included in circuit RL, and a Si transistor may be used for the p-channel transistor. 【0218】 The drain of transistor MP1i is connected to the first input terminal of circuit RL, the drain of transistor MP1o is connected to the drain of transistor MN2i, the drain of transistor MN2o is connected to the drain of transistor MP3i, and the drain of transistor MP3o is connected to the output terminal of circuit RL. 【0219】 The first current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor MP2o as the source and drain current corresponding to the gate-source potential of transistor MP2i. Similarly, the second current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor MN1o as the source and drain current corresponding to the gate-source potential of transistor MN1i. Similarly, the third current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor NP4o as the source and drain current corresponding to the gate-source potential of transistor MP4i. 【0220】 In the first current mirror circuit, transistor MP1i functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2i due to DIBL. Similarly, transistor MP1o also functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2o due to DIBL. Therefore, wiring VE1, which provides a desired bias potential, is connected to the gates of transistors MP1i and MP1o, respectively. 【0221】In the second and third current mirror circuits, each of the transistors MN2i, MN2o, MP3i, and MP3o also functions as a clamp transistor to prevent a drop in the threshold voltage of the transistors connected in series by DIBL. In this case, each of the wires VE2 and VE3 functions as a wire that provides a desired bias potential. 【0222】 Furthermore, the bias potentials provided by wiring VE1 and wiring VE3 can be made equal to each other. Therefore, wiring VE1 and wiring VE3 can be the same wiring. 【0223】 Furthermore, transistors MP1i and MP1o can each function as switching transistors. In this case, it is preferable that wiring VE1 functions as wiring for controlling the switching between the on and off states of these transistors. Also, by turning these transistors off, the first current mirror circuit can be stopped, thereby reducing the power consumption in circuit RL. The same applies to transistors MN2i and MN2o of the second current mirror circuit and transistors MP3i and MP3o of the third current mirror circuit. 【0224】 In the first current mirror circuit, the source of transistor MP2i and the source of transistor MP2o are connected to wiring VD2. Since the first current mirror circuit is composed of p-channel transistors, it also functions as a current source circuit. Therefore, wiring VD2 functions as wiring that provides a high-level potential, acting as a high-power supply potential for the first current mirror circuit. Similarly, the third current mirror circuit also functions as a current source circuit, and therefore the high-level potential provided by wiring VD2 also functions as a high-power supply potential for the third current mirror circuit. Note that the high-level potential provided by wiring VD2 may be equal to the high-level potential provided by wiring VD1 described above. In this case, wiring VD1 and wiring VD2 can be combined as the same wiring. 【0225】 In the second current mirror circuit, the source of transistor MN1i and the source of transistor MN1o are connected to wiring VS2. Since the second current mirror circuit is composed of n-channel transistors, it also functions as a current sink circuit. Therefore, wiring VS2 functions as wiring that provides a low-level potential as the low power supply potential of the second current mirror circuit. The low-level potential provided by wiring VS2 may be equal to the low-level potential provided by wiring VS1 described above. In this case, wirings VS1 and VS2 can be combined into a single wiring. 【0226】 When a high-level potential is applied to the wiring CLB, switches SBp and SBn are both in the ON state. At this time, current Isp flows from wiring WLp to the first input terminal of circuit RL, and current Isn flows from wiring WLn to the second input terminal of circuit RL. Since current Isp flows between the source and drain of transistor MP2i, ideally, the amount of current Isp equal to the current flowing between the source and drain of transistor MP2o flows between the source and drain of transistor MP2i. 【0227】 Furthermore, if Isp is greater than Isn, then according to Kirchhoff's current law, the current Is flowing between the source and drain of transistor MN1i is Isp - Isn. Therefore, ideally, the currents flowing between the source and drain of transistors MN1o, MP4i, and MP4o are also Is. As a result, circuit RL can output the difference between the current Isp flowing through the first input terminal and the current Isn flowing through the second input terminal as Is at the output terminal. 【0228】 Furthermore, when Isp is less than or equal to Isn, the current flowing between the source and drain of transistor MP2o becomes Isn, and therefore no current flows between the source and drain of transistor MN1i. Consequently, no current is output from the output terminal of circuit RL. 【0229】Therefore, by using the circuit RL in Figure 7B, it is possible to perform calculations on the ReLU function with the difference current between the first input terminal and the second input terminal substituted as a variable. 【0230】 Next, we will describe an example of the configuration of the RLC circuit when the circuit ITSo includes an analog-to-digital conversion circuit. 【0231】 Figure 8 shows an example of the circuit configuration of circuit RLC when circuit ITSo includes an analog-to-digital conversion circuit. The circuit RLC shown in Figure 8 is configured as a successive approximation register (SAR) type analog-to-digital conversion (ADC) circuit and includes a current mirror circuit CMRp, a current mirror circuit CMRn, a current comparator CPR, a digital-to-analog conversion (DAC) circuit DTAp, a DAC circuit DTAn, and a logic circuit LGC. In particular, the DAC circuits DTAp and DTAn can be current-draw type current DACs. 【0232】 Figure 8 also shows the connection configuration around the RLC circuit, including switches SBp and SBn, wiring WLop and WLon. 【0233】 The second terminal of switch SBp is connected to the input terminal of current mirror circuit CMRp and the output terminal of DAC circuit DTAp. The second terminal of switch SBn is connected to the input terminal of current mirror circuit CMRn and the output terminal of DAC circuit DTAn. The output terminal of current mirror circuit CMRp is connected to the first input terminal of current comparator CPR, and the output terminal of current mirror circuit CMRn is connected to the second input terminal of current comparator CPR. The output terminal of current comparator CPR is connected to the input terminal of logic circuit LGC. The terminal LFTp of logic circuit LGC is connected to the input terminal of DAC circuit DTAp, and the terminal LFTn of logic circuit LGC is connected to the input terminal of DAC circuit DTAn. The output terminal of logic circuit LGC is connected to wiring OL. 【0234】 The RLC circuit shown in Figure 8 converts the difference between the current flowing through wiring WLop and the current flowing through wiring WLon into a digital signal, and outputs this digital signal to wiring OL. 【0235】 Specifically, for example, if we want to calculate the difference between Iop and Ion, with Ion as the reference, by letting Iop be the current flowing through wiring WLop and Ion be the current flowing through wiring WLon, we first operate the DAC circuit DTAp and stop the DAC circuit DTAn. Also, if we let Icp be the current flowing from the output terminal of the current mirror circuit CMRp and Icn be the current flowing from the output terminal of the current mirror circuit CMRn, then in the initial state, Icp = Iop and Icn = Ion hold true. Here, the current comparator CPR compares the magnitude relationship between Icp and Icn and transmits the comparison result to the logic circuit LGC. The logic circuit LGC transmits a signal corresponding to the comparison result from terminal LFTp to the DAC circuit DTAp, generates a current Ifp based on this signal, and draws the current Ifp from current Iop to the output terminal of the DAC circuit DTAp. At this point, Icp = Iop - Ifp and Icn = Ion. The current comparator CPR compares the magnitudes of Icp and Icn again and transmits the comparison result to the logic circuit LGC. This process is repeated to sequentially change Ifp until Icp = Icn. When the DAC circuit DTAp generates a current Ifp such that Icp = Icn using the digital signal output from terminal LFTp of the logic circuit LGC, the value of this digital signal corresponds to the difference with Iop based on Ion. Thus, the logic circuit LGC can generate a digital signal corresponding to the difference with Iop based on Ion. This digital signal is then output to wiring OL by the logic circuit LGC. 【0236】 As a result of the above, the result of the sum-of-accumulate operation in region CAo of the arithmetic unit CA can be converted into a digital signal and output to the outside of the arithmetic unit CDV. 【0237】<<Example Configuration of Drive Circuit SCD>> Next, an example configuration of the drive circuit SCD will be described. Figure 9 is a circuit diagram showing an example configuration of the drive circuit SCD, and in particular, it shows the specific configuration of selectors SC[1] to SC[n] provided in the drive circuit SCD. 【0238】 Selector SC[h] includes, for example, switch STp and switch STn. For details on switches STp and STn, please refer to the descriptions of switches SAp and SAN above. Therefore, each of switches STp and STn can be replaced with a switch applicable to either switch SAp or switch SAN as described above. 【0239】 In selector SC[h], the first terminal of switch STp is connected to the output terminal of circuit XDR[j] (not shown in Figure 9) provided in drive circuit XCD. Also, the first terminal of switch STn is connected to the output terminal of circuit ITSr[h] (not shown in Figure 9) provided in drive circuit ITS. Furthermore, the second terminal of switch STp and the second terminal of switch STn are connected to wiring XLo[h]. In addition, the control terminal of switch STp is connected to wiring CLSp, and the control terminal of switch STn is connected to wiring CLSn. 【0240】 In the drive circuit SCD shown in Figure 9, wiring CLSp and wiring CLSn are wirings included in wiring CLS. Therefore, wiring CLS can be treated as a group of wirings. 【0241】Wiring CLSp and CLSn function as a signal line pair for transmitting signals with their logic inverted relative to each other. These signals can be control signals transmitted from wiring CLS to the control terminal of selector SC[h]. For example, when a high-level potential is applied to wiring CLSp, a low-level potential is applied to wiring CLSn, and in this case, switch STp is ON and switch STn is OFF in selector SC[h]. Conversely, when a low-level potential is applied to wiring CLSp, a high-level potential is applied to wiring CLSn, switch STp is OFF and switch STn is ON. 【0242】 When a high-level potential is applied to wiring CLSp and a low-level potential is applied to wiring CLSn, the connection between wiring XLo[h] and the output terminal of circuit XDR[h] in drive circuit XCD becomes conductive, and the connection between wiring XLo[h] and the output terminal of circuit ITSr[h] in drive circuit ITS becomes non-conductive. Furthermore, when a low-level potential is applied to wiring CLSp and a high-level potential is applied to wiring CLSn, the connection between wiring XLo[h] and the output terminal of circuit XDR[h] in drive circuit XCD becomes non-conductive, and the connection between wiring XLo[h] and the output terminal of circuit ITSr[h] in drive circuit ITS becomes conductive. 【0243】 <Example of Semiconductor Device Operation> An example of operation in which ESN calculations are performed using the arithmetic unit CDV of Figure 1 will be explained using the timing chart of Figure 10 and the block diagrams of Figures 11A to 12B. It is assumed that the arithmetic unit CDV used in this operation example uses the drive circuit WCD of Figure 2, the circuit WD of Figure 3, the circuit XD of Figure 4, the drive cell DC and arithmetic circuit CC of Figure 5A, the drive circuit ITS of Figure 7A, and the circuit RL of Figure 7B. 【0244】The timing chart in Figure 10 shows the changes in potential of wiring CLA, wiring CLB, wiring CLSp, wiring SLi, wiring SLo[1], and wiring SLo[n] at times T11 to T19 and in the vicinity thereof. The timing chart also shows the changes in the values ​​of the signals input to wiring WLip[1], wiring WLiN[1], wiring WLip[n], wiring WLiN[n], wiring WLop, wiring WLon, wiring XLi, wiring XLo[1], wiring XLo[n], and wiring OL. 【0245】 In the block diagrams of Figures 11A to 12B, the blocks of the circuits that are the main components of the operation are hatched with diagonal lines. Furthermore, since the arithmetic unit CDV performs recursive input, two blocks are shown for convenience in circuits ITSr[1] and ITSr[n]. Specifically, the lower block shows the result of the calculation of the activation function of circuit RL which is input to the drive circuit SCD, and the upper block shows the result of the calculation when the result of the said calculation and the sum-of-products calculation using weight coefficients are input to the activation function. 【0246】 [Time T11] At time T11, a high potential is applied to wiring CLA. As a result, switches SAP and SAN in the drive circuit WCD in Figure 2 are turned ON. Also at time T11, a high potential is applied to wiring CLS. As a result, in the drive circuit SCD, selectors SC[1] to SC[n] become conductive between their first input terminal and output terminal. Note that in Figures 11A to 12A, the first input terminal and output terminal of selector SC are connected by a dotted line to show that they are conductive. 【0247】Furthermore, at time T11, a low-level potential is applied to wiring CLB. As a result, switches SBp and SBn in the drive circuit ITS in Figure 7A are turned off. Also at time T11, a low-level potential is applied from the drive circuit WSD to wiring SLi and wiring SLo[1] through SLo[n]. As a result, in the calculation unit CA, a low-level potential is applied to the gates of transistor M1d in drive cell DC, transistor M1 in calculation cell MCp, and transistor M1n in calculation cell MCn, causing these transistors to turn off. 【0248】 [Time T12] At time T12, as shown in the block diagram of Figure 11A, the weight coefficients Wi between the neurons in the input layer and the neurons in the reservoir layer are written to the arithmetic circuit CCi in region CAi. Note that Wi can be a matrix containing Wi[1] to Wi[n]. 【0249】 Specifically, a high-level potential is applied from the drive circuit WSD to the wiring SLi, causing transistor M1d in the drive cell DCi, transistor M1p in the calculation cell M1p in region CAi, and transistor M1n in the calculation cell M1n in region CAi to turn ON. Although the application of the high-level potential from the drive circuit WSD to the wiring SLi ends at time T13, it may actually end before time T13 is reached. 【0250】At this time, the drive circuit WCD in Figure 2 transmits a signal (current signal or potential signal) corresponding to the weight coefficient Wi to each of the arithmetic circuits CCi[1] to CCi[n]. For example, in order to write the weight coefficient Wi[1] to the arithmetic circuit CCi[1], Wip[1] corresponding to Wi[1] is transmitted to the wiring WLip[1], and Win[1] corresponding to Wi[1] is transmitted to the wiring WLin[1]. For example, Figure 11A shows an example where Wi[1] = 32 is set, Wip[1] = 32 is written to the arithmetic cell MCp of the arithmetic circuit CCi[1], and Win[1] = 0 is written to the arithmetic cell MCn. Similarly, in order to write the weight coefficient Wi[n] to the arithmetic circuit CCi[n], Wip[n] corresponding to Wi[n] is transmitted to the wiring WLip[n], and Win[n] corresponding to Wi[n] is transmitted to the wiring WLin[n]. For example, Figure 11A shows an example where Wi[n] = -32 is set, Wip[n] = 0 is written to the calculation cell MCp of the arithmetic circuit CCi[n], and Win[n] = 32 is written to the calculation cell MCn. 【0251】 Furthermore, at time T12, the drive circuit XCD outputs a signal (current signal or potential signal) corresponding to the reference value Rf from circuit XD to wiring XLi. 【0252】 [From time T13 to time T16] Between time T13 and time T16, as shown in the block diagrams of Figures 11B and 12A, the weight coefficients Wr between neurons in the reservoir layer are written to the arithmetic circuit CCr of region Car, and the weight coefficients Wo between neurons in the reservoir layer and neurons in the output layer are written to the arithmetic circuit CCo of region CAo. Note that Wr can be a matrix containing Wr[1,1] to Wr[n,n], and Wo can be a matrix containing Wo[1] to Wo[n]. 【0253】Specifically, at time T13, a high-level potential is applied from the drive circuit WSD to the wiring SLo[1], causing transistor M1d in the drive cell DCo[1], transistors M1p and M1n in the first row of the calculation circuits CCr[1,1] to CCr[1,n] in region Car, and transistors M1p and M1n in the calculation circuit CCo[1] to each of these to turn ON. Note that the application of the high-level potential from the drive circuit WSD to the wiring SLo[1] ends at time T14, but in reality, it may end before time T14 is reached. 【0254】 At this time, the drive circuit WCD in Figure 2 transmits a signal (current signal or potential signal) corresponding to the weight coefficient Wr to each of the arithmetic circuits CCr[1,1] to CCr[1,n]. In order to write the weight coefficient Wr[1,1] to the arithmetic circuit CCr[1,1], Wrp[1,1] corresponding to Wr[1,1] is transmitted to the wiring WLip[1], and Wrn[1,1] corresponding to Wr[1,1] is transmitted to the wiring WLin[1]. For example, Figure 11B shows an example in which Wr[1,1] = -1 is set, Wrp[1,1] = 0 is written to the arithmetic cell MCp of the arithmetic circuit CCr[1,1], and Wrn[1,1] = 1 is written to the arithmetic cell MCn. 【0255】 Similarly, in order to write the weight coefficient Wr[1,n] to the arithmetic circuit CCr[1,n], Wrp[1,n] corresponding to Wr[1,n] is sent to the wiring WLip[n], and Wrn[1,n] corresponding to Wr[1,n] is sent to the wiring WLin[n]. For example, Figure 11B shows an example where Wr[1,n]=0 is set, Wrp[1,n]=0 is written to the arithmetic cell MCp of the arithmetic circuit CCr[1,n], and Wrn[1,n]=0 is written to the arithmetic cell MCn. 【0256】Furthermore, the drive circuit WCD in Figure 2 transmits the weight coefficient Wo[1] as a signal to the arithmetic circuit CCo[1]. Specifically, in order to write the weight coefficient Wo[1] to the arithmetic circuit CCo[1], Wop[1] corresponding to Wo[1] is transmitted to the wiring WLop, and Won[1] corresponding to Wo[1] is transmitted to the wiring WLon. For example, Figure 11B shows an example where Wo[1] = -7 is set, Wop[1] = 0 is written to the arithmetic cell MCp of the arithmetic circuit CCo[1], and Won[1] = 7 is written to the arithmetic cell MCn. 【0257】 Furthermore, at time T13, the drive circuit XCD outputs a signal (current signal or potential signal) corresponding to the reference value Rf from circuit XDR[1] to wiring XLo[1] via selector SC[1]. 【0258】 Furthermore, between time T14 and time T15, the weight coefficients Wr are written to the arithmetic circuits CCr from the second row to the (n-1)th row of region Car, and the weight coefficients Wo are written to the arithmetic circuits CCo[2] to CCo[n-1] of region CAo, similar to the operation between time T13 and time T14 described above. 【0259】 At time T15, a high-level potential is applied from the drive circuit WSD to the wiring SLo[n], causing transistor M1d in the drive cell DCo[n], transistors M1p and M1n in the nth row of the arithmetic circuits CCr[n,1] to CCr[n,n] in region Car, and transistors M1p and M1n in the arithmetic circuit CCo[n] to each of these to turn ON. Note that the application of the high-level potential from the drive circuit WSD to the wiring SLo[n] ends at time T16, but in reality, it may end before time T16 is reached. 【0260】At this time, the drive circuit WCD in Figure 2 transmits the weight coefficients Wr[n,1] to Wr[n,n] as signals to each of the arithmetic circuits CCr[n,1] to CCr[n,n]. For example, Figure 12A shows an example where Wr[n,1]=0 is set, writing Wrp[n,1]=0 to the arithmetic cell MCp of the arithmetic circuit CCr[n,1], and writing Wrn[n,1]=0 to the arithmetic cell MCn. Also, for example, Figure 12A shows an example where Wr[n,n]=64 is set, writing Wrp[n,n]=64 to the arithmetic cell MCp of the arithmetic circuit CCr[n,n], and writing Wrn[n,n]=0 to the arithmetic cell MCn. 【0261】 Furthermore, the drive circuit WCD in Figure 2 transmits the weight coefficient Wo[n] as a signal to the arithmetic circuit CCo[n]. For example, Figure 12A shows an example where Wo[n] = 17 is written to the arithmetic cell MCp of the arithmetic circuit CCo[n], and Won[n] = 0 is written to the arithmetic cell MCn. 【0262】 Furthermore, at time T15, the drive circuit XCD outputs a signal (current signal or potential signal) corresponding to the reference value Rf from circuit XDR[n] to wiring XLo[n] via selector SC[n]. 【0263】 [Time T17] At time T17, a low-level potential is applied to the wiring CLA. This causes switches SAP and SAN in the drive circuit WCD in Figure 2 to turn off. With this operation, the writing of weight coefficients to each of the calculation circuits CC by the calculation unit CA is completed. 【0264】 [Time T18] At time T18, a high-level potential is applied to the wiring CLS. As a result, in the drive circuit SCD, each of the selectors SC[1] to SC[n] becomes conductive between the second input terminal and the output terminal. In Figure 12B, the second input terminal and the output terminal of selector SC are connected by a dotted line to show that they are conductive. 【0265】Furthermore, at time T18, a high-level potential is applied to the wiring CLB. As a result, switches SBp and SBn in the drive circuit ITS in Figure 7A are turned ON. Also, because switches SBp and SBn in the drive circuit ITS are turned ON, the first terminals of transistors M3p and M3n, which are included in the respective calculation circuits CC of the calculation unit CA, are supplied with a potential from circuit RL. 【0266】 Furthermore, at time T18, the input value U(t) is supplied from circuit XD of the drive circuit XCD to wiring XLi. Note that t is a time between time T18 and time T19. Also, the value of U(t) is assumed to change depending on time t. In addition, the input value U(t) is input to each of the arithmetic circuits CCi[1] to CCi[n] in region CAi, so each of the arithmetic circuits CCi[1] to CCi[n] performs multiplication of the weight coefficient Wi and the input value U(t). For example, in arithmetic circuit CCi[j], the calculation Wi[j] × U(t) is performed. 【0267】 Furthermore, at time T18, the circuit ITSr[h] in Figure 7A outputs Xo[h](t-s) from its output terminal as a value corresponding to time t-s. Note that time t-s is a time before time t, and s indicates the time difference. Xo[h](t-s) is a value corresponding to the difference between the current flowing through wiring WLip[h] and the current flowing through wiring WLin[h]. Also, Xo[h](t-s) is input as current to wiring XLo[h] via selector SC[h]. For example, Xo[1](t-s) is output from the output terminal of circuit ITSr[1], and Xo[1](t-s) is input to wiring XLo[1] via selector SC[1]. Similarly, Xo[n](t-s) is output from the output terminal of circuit ITSr[n], and Xo[n](t-s) is input to wiring XLo[n] via selector SC[n]. 【0268】Therefore, in the arithmetic circuits CCr[h,1] through CCr[h,n] of the h row of region Car, the multiplication of the weight coefficient Wr by Xo[h](t-s) is performed. For example, in the arithmetic circuit CCi[h,j], the calculation Wr[h,j] × Xo[h](t-s) is performed. 【0269】 Furthermore, focusing on the j-th column of region Car, the multiplication results of each arithmetic circuit CCr[1,j] through CCr[n,j] are all added together and input to the drive circuit ITS. The summation result of all multiplications in region Car is expressed as ΣWr[h,j] × Xo[h](t-s). Here, Σ indicates the summation for the cases where h is from 1 to n. 【0270】 Therefore, at time t, the result of the calculation performed from wiring WLip[j] and WLin[j] to circuit ITSr[j] in Figure 7A, Xo[j](t), is as shown in equation (1.10) below. 【0271】 【0272】 Note that f[x] is the activation function in the circuit RL, with x as the variable. 【0273】 Furthermore, at time T18, in the arithmetic circuits CCo[1] to CCo[n] included in region CAo, the weight coefficient Wo is multiplied by Xo[j](t-s) output from the drive circuit ITS. For example, in the arithmetic circuit CCo[h], the weight coefficient Wo[h] is multiplied by Xo[h](t-s) input to the wiring XLo[h]. 【0274】 Therefore, at time t, the result Y(t) of the calculation performed from wiring WLop and wiring WLon to circuit ITSo in Figure 7A is as shown in equation (1.11) below. 【0275】 【0276】 The calculation unit CDV in Figure 1 can perform ESN calculations by operating according to Figures 10 to 12B. 【0277】<Example of modification of semiconductor device 1> Next, as an example of modification of the drive circuit ITS shown in Figure 7A, we will describe an example of a drive circuit ITS related to a semiconductor device according to one aspect of the present invention. 【0278】 The drive circuit ITS shown in Figure 13A is an example of a modified circuit configuration of the drive circuit ITS in Figure 7A, and the timing of the signal output from circuit ITSr to drive circuit SCD can be adjusted by pipeline processing. 【0279】 By performing pipeline processing in the drive circuit ITS, the calculation results can be transmitted stepwise from the drive circuit ITS to the calculation unit CA via the drive circuit SCD. This allows the sum-of-products calculation between the recursively input calculation results and the weight coefficients in the calculation unit CA to converge stepwise. In particular, by adjusting the delay time (also called the time constant) until the calculation result is output to the output terminal of the drive circuit ITS, the calculations performed by the calculation device CDV can be stabilized and converged, bringing the calculation result output by the calculation device CDV to the wiring OL closer to the expected value. 【0280】 The drive circuit ITS in Figure 13A has a configuration in which switches AS1 to AS3, circuits SHN and SHP are added to the circuit ITSr[j] provided in the drive circuit ITS in Figure 7A. Note that the drive circuit SCD is also shown in Figure 13A to illustrate the connection configuration with the drive circuit ITS. 【0281】 Furthermore, the circuit ITSo included in the drive circuit ITS in Figure 13A can be described by referring to the explanation of circuit ITSo shown in Figure 7A. 【0282】In the drive circuit ITS in Figure 13A, the calculation result is transmitted from circuit ITSo to wiring OL, but pipeline processing may also be performed on the calculation result to output data in stages. In the drive circuit ITS in Figure 13B, circuit ITSo has the same configuration as circuit ITSr[j], and the calculation result output from circuit ITSo can be output in stages by pipeline processing. Also, wiring OL in Figures 13A and 13B may be connected to calculation circuit CCr included in area Car of calculation unit CA for, for example, transmitting output results to the reservoir layer. In the following explanation, it will be assumed that the drive circuit ITS of calculation device CDV in Figure 1 is the drive circuit ITS of Figure 13A. 【0283】 For switches AS1 to AS3, refer to the above descriptions of switches SAP and SAN. Therefore, each of switches AS1 to AS3 can be a switch that is applicable to switch SAP or switch SAN as described above. 【0284】 Circuits SHN and SHP each have, for example, the function of holding a value corresponding to a signal input to an input terminal and the function of outputting a signal corresponding to that value to an output terminal. In other words, circuits SHN and SHP each function as a sample-and-hold circuit. 【0285】 In circuit ITSr[j], the first terminal of switch AS1 is connected to the output terminal of circuit RL, and the second terminal of switch AS1 is connected to the input terminal of circuit SHN. Also, the first terminal of switch AS2 is connected to the output terminal of circuit SHN, and the second terminal of switch AS2 is connected to the input terminal of circuit SHP. Furthermore, the first terminal of switch AS3 is connected to the output terminal of circuit SHP, and the second terminal of switch AS3 is connected to the drive circuit SCD. In addition, the control terminal of switch AS1 and the control terminal of switch AS3 are connected to wiring PCK1, and the control terminal of switch AS2 is connected to wiring PCK2. 【0286】Wiring PCK1 and wiring PCK2 each function as wiring that transmits control signals to operate switches AS1 to AS3, circuits SHN and SHP, respectively. In circuit ITSr[j] in Figure 13A, since data is transmitted in stages by pipeline processing, it is preferable that wiring PCK1 and wiring PCK2 are input to clock signals with their logic inverted relative to each other. For example, when either a high-level potential or a low-level potential is applied to wiring PCK1, it is preferable that the other high-level potential or low-level potential is applied to wiring PCK2. 【0287】 Figure 14A shows an example of a specific circuit configuration of circuit ITSr[j] in Figure 13A. Circuit ITSa shown in Figure 14A is an example of a circuit configuration of circuit ITSr[j] in Figure 13A, in which analog switches are applied to each of switches AS1 to AS3, and current-type sample-and-hold circuits are applied to circuits SHN and SHP, respectively. However, in Figure 14A, circuit SHN shows a current-drawing type sample-and-hold circuit configuration, and circuit SHP shows a current-discharge type sample-and-hold circuit configuration. 【0288】 In Figure 14A, each of switches AS1 to AS3 has a transistor Tr9p and a transistor Tr9n. Transistor Tr9p is a p-channel type transistor, and transistor Tr9n is an n-channel type transistor. In this case, both transistors Tr9p and Tr9n can be Si transistors. In this case, since transistors Tr9p and Tr9n can be manufactured simultaneously using the Si process, the cycle time for manufacturing switches AS1 to AS3 can be reduced. 【0289】In each of the analog switches AS1 through AS3, the first terminal of transistor Tr9p and the first terminal of transistor Tr9n correspond to the first terminal of the analog switch. Furthermore, the second terminal of transistor Tr9p and the second terminal of transistor Tr9n correspond to the second terminal of the analog switch. The gates of transistor Tr9p and Tr9n correspond to the control terminals of the analog switch. 【0290】 In switch AS1, the first terminal of transistor Tr9p and the first terminal of transistor Tr9n are connected to the output terminal of circuit RL. The second terminal of transistor Tr9p and the second terminal of transistor Tr9n are connected to the input terminal of circuit SHN. The gate of transistor Tr9p is connected to wiring PCKn, and the gate of transistor Tr9n is connected to wiring PCKp. In this specification, the connection point between the first terminal of transistor Tr9p, the first terminal of transistor Tr9n, and the output terminal of circuit RL is referred to as node A1Ti. 【0291】 Furthermore, in switch AS2, the first terminal of transistor Tr9p and the first terminal of transistor Tr9n are connected to the output terminal of circuit SHN. Also, the second terminal of transistor Tr9p and the second terminal of transistor Tr9n are connected to the input terminal of circuit SHP. In addition, the gate of transistor Tr9p is connected to wiring PCKp, and the gate of transistor Tr9n is connected to wiring PCKn. 【0292】Furthermore, in switch AS3, the first terminal of transistor Tr9p and the first terminal of transistor Tr9n are connected to the output terminal of circuit SHP. Also, the second terminal of transistor Tr9p and the second terminal of transistor Tr9n are connected to the drive circuit SCD (not shown in Figures 14A and 14B) via the output terminal of circuit ITSa. In addition, the gate of transistor Tr9p is connected to wiring PCKn, and the gate of transistor Tr9n is connected to wiring PCKp. In this specification, the connection point between the second terminal of transistor Tr9p and the second terminal of transistor Tr9n is referred to as node A3To. 【0293】 Circuit SHN is a sample-and-hold circuit consisting of an n-channel current mirror circuit with a writing transistor (also called a holding transistor), transistor MN7. Specifically, circuit SHN has n-channel transistors MN6i, MN6o, and MN7. The first terminals of transistor MN6i and MN7 correspond to the input terminals of circuit SHN, and the first terminal of transistor MN6o corresponds to the output terminal of circuit SHN. The gate of transistor MN7 can also be used as a control terminal for circuit SHN. 【0294】The first terminal of transistor MN6i and the first terminal of transistor MN7 are connected to the second terminal of transistor Tr9p and the second terminal of transistor Tr9n, which are included in switch AS1. The second terminal of transistor MN7 is connected to the gate of transistor MN6i and the gate of transistor MN6o. The second terminal of transistor MN6o is connected to the first terminal of transistor Tr9p and the first terminal of transistor Tr9n, which are included in switch AS2. The second terminal of transistor MN6i and the second terminal of transistor MN6o are connected to wiring VS3. The gate of transistor MN7 is connected to wiring PCKp. The gate of transistor MN7 is also connected to wiring GTLn. In this specification, the connection point between the gate of transistor MN6i, the gate of transistor MN6o, and the second terminal of transistor MN7 is referred to as node SN1. 【0295】 Furthermore, by using Si transistors for transistors MN6i, MN6o, and MN7 in the SHN circuit, the manufacturing process can be standardized. This reduces the cycle time required to manufacture the SHN circuit. Also, for example, transistors MN6i, MN6o, and MN7 can each be replaced with OS transistors instead of Si transistors. OS transistors have the characteristic of having a small off-current, so by using an OS transistor, especially for transistor MN7, fluctuations in the potential of node SN1 due to the off-current can be suppressed. This stabilizes the operation of the SHN circuit. 【0296】Circuit SHP is a sample-and-hold circuit consisting of a p-channel current mirror circuit with a writing transistor (also called a holding transistor), transistor MN8. Specifically, circuit SHP has p-channel transistors MP6i and MP6o, and an n-channel transistor, transistor MN8. The first terminal of transistor MP6i and the first terminal of transistor MN8 correspond to the input terminals of circuit SHP, and the first terminal of transistor MP6o corresponds to the output terminal of circuit SHP. The gate of transistor MN8 can also be used as a control terminal for circuit SHP. 【0297】 The first terminal of transistor MP6i and the first terminal of transistor MN8 are connected to the second terminal of transistor Tr9p and the second terminal of transistor Tr9n, which are included in switch AS2. The second terminal of transistor MN8 is connected to the gate of transistor MP6i and the gate of transistor MP6o. The second terminal of transistor MP6o is connected to the first terminal of transistor Tr9p and the first terminal of transistor Tr9n, which are included in switch AS3. The second terminal of transistor MP6i and the second terminal of transistor MP6o are connected to wiring VD3. The gate of transistor MN8 is connected to wiring PCKn. The gate of transistor MN8 is also connected to wiring GTLp. In this specification, the connection point between the gate of transistor MP6i, the gate of transistor MP6o, and the second terminal of transistor MP7 is referred to as node SN2. 【0298】Furthermore, by making transistors MP6i, MP6o, and MN8 of the circuit SHP into Si transistors, the manufacturing process can be standardized. This reduces the cycle time required to manufacture the circuit SHP. In this case, transistor MN8 may also be a p-channel transistor with the same polarity as transistors MP6i and MP6o. Alternatively, for example, transistors MP6i and MP6o may be Si transistors, and transistor MN8 may be an OS transistor. Since OS transistors have the characteristic of having a small off-current, using an OS transistor, in particular, for transistor MN8 can suppress fluctuations in the potential of node SN2 due to the off-current. This stabilizes the operation of the circuit SHP. 【0299】 Furthermore, in Figure 14A, transistors MN6i and MN6o are n-channel transistors, and transistors MP6i and MP6o are p-channel transistors, but the polarity of these transistors may be changed. For example, transistors MN6i and MN6o may be p-channel transistors, and transistors MP6i and MP6o may be n-channel transistors. In this case, circuit SHN becomes a current-discharging sample-and-hold circuit, and circuit SHP becomes a current-drawing sample-and-hold circuit. In this case, it is important to note that circuit RL must be configured so that a draw-in current flows to the output terminal. 【0300】Wiring PCKp and PCKn correspond to wiring PCK1 and PCK2 shown in Figure 13A, and function as wiring that transmits control signals to operate switches AS1 to AS3, respectively. Specifically, wiring PCKp in Figure 14A can be wiring PCK1 in Figure 13A, and wiring PCKn in Figure 14A can be wiring PCK2 in Figure 13A. Since switches AS1 to AS3 are analog switches, wiring PCKp and PCKn in Figure 14A are a wiring pair that transmits signals that are in opposite phases to each other (signals whose phases are inverted to each other). For example, in Figure 14A, by inputting clock signals with inverted logic to each other to the wiring pair of wiring PCKp and PCKn, pipeline processing becomes possible in circuit ITSa. Furthermore, the speed of the pipeline processing can be adjusted by changing the frequency of the clock signal. 【0301】 Wirings GTLn and GTLp function as wiring that transmits control signals to operate circuits SHN and SHP, respectively. For example, by inputting control signals (which can be pulse voltages, for example) to wirings GTLn and GTLp at appropriate timings, circuits SHN and SHP can maintain a potential corresponding to the input value and output a current corresponding to that potential. 【0302】 Wirings GTLn and GTLp may be combined with wirings PCKp and PCKn. For example, circuit ITSa shown in Figure 15A is configured in the same way as circuit ITSa in Figure 14A, with the gate of transistor MN7 connected to wiring PCKp and the gate of transistor MN8 connected to wiring PCKn. In other words, wirings PCKp and PCKn may be used to transmit control signals for operating circuits SHN and SHP, respectively. By combining the wiring in this way, the circuit area can be reduced. 【0303】Wiring VS3 can, for example, function as a low-level potential wire, similar to wiring VS1 or wiring VS2 described above, as a low power supply potential. Furthermore, if the potential provided by wiring VS3 is equal to the potential provided by one or both of wiring VS1 and wiring VS2, wiring VS3 can be combined with one or both of wiring VS1 and wiring VS2. Similarly, wiring VD3 can, for example, function as a high-level potential wire, similar to wiring VD1 or wiring VD2 described above, as a high power supply potential. Furthermore, if the potential provided by wiring VD3 is equal to the potential provided by one or both of wiring VD1 and wiring VD2, wiring VD3 can be combined with one or both of wiring VD1 and wiring VD2. 【0304】 Next, an example of the operation of circuit ITSa in Figure 14A will be described. Figure 16 is a timing chart showing an example of the operation of circuit ITSa, and shows the changes in potential at wiring CLB, wiring PCKp, wiring PCKn, wiring GTLn, and wiring GTLp at times T21 to T27m and in the vicinity thereof. The timing chart also shows the values ​​of the signals supplied to nodes A1Ti, SN1, SN2, and A3To. 【0305】 When the circuit ITSa shown in Figure 14A is applied to the circuits ITSr[j] and ITSoso, respectively, which are included in the drive circuit ITS of the computing device CDV in Figure 1, the operations at times T21 to T27m and their vicinity shown in the timing chart of Figure 16 can be made to be operations that occur between times T18 and T19 in the timing chart of Figure 10. 【0306】 Between time T21 and time T27m, a high potential is constantly applied to wiring CLB. As a result, switches SBp and SBn included in circuit ITSa are turned ON, and the result of the sum-of-products calculation performed in calculation unit CA is input to circuit RL. 【0307】Furthermore, circuit RL calculates the value X of the activation function obtained by substituting the result as a variable, and outputs the value X to the output terminal. Therefore, node A1Ti is supplied with a signal corresponding to the value X. In reality, the value X changes continuously with the passage of time, but for the sake of simplicity in this operation example, the timing chart in Figure 16 shows the values ​​X supplied to node A1Ti at times T21, T22, T23, T24, T25, T26, and T27m as X(T21) to X(T27). Furthermore, in the timing chart of Figure 16, it is assumed that time T22m occurs between time T22 and time T23, time T23m occurs between time T23 and time T24, time T24m occurs between time T24 and time T25, time T25m occurs between time T25 and time T26, time T26m occurs between time T26 and time T27, and time T27m occurs after time T27. 【0308】 At times T22, T24, and T26, a high-level potential is applied to wiring PCKp and a low-level potential is applied to wiring PCKn. As a result, switches AS1 and AS3 are turned ON, and switch AS2 is turned OFF. 【0309】 Furthermore, at times T21, T23, T25, and T27, a low-level potential is applied to wiring PCKp and a high-level potential is applied to wiring PCKn. As a result, switches AS1 and AS3 are turned off, and switch AS2 is turned on. 【0310】Furthermore, a high-level potential is applied to the GTLn wiring at times T22m, T24m, and T26m. This causes transistor MN7 to turn on in circuit SHN, allowing circuit SHN to acquire the signal input to the input terminal. Additionally, a low-level potential is applied to the GTLn wiring at times T23, T25, and T27. This causes transistor MN7 to turn off in circuit SHN, allowing it to retain the value input to the input terminal just before turning off and output a signal corresponding to that value to the output terminal. 【0311】 Furthermore, at times T23m, T25m, and T27m, a high-level potential is applied to the wiring GTLp. This causes transistor MN8 in circuit SHP to turn on, allowing it to acquire the signal input to the input terminal. At times T24 and T26, a low-level potential is applied to the wiring GTLp. This causes transistor MN8 in circuit SHP to turn off, so it holds the value input to the input terminal just before it turned off and outputs a signal corresponding to that value to the output terminal. 【0312】 By operating circuit ITSa according to the timing chart shown in Figure 16, for example, at time T22, circuit RL outputs X(T22) as a signal from its output terminal. X(T22) is also supplied to circuit SHN via switch AS1. At time T22m, circuit SHN acquires X(T22) output from circuit RL. At time T23, circuit SHN holds X(T22) and transmits X(T22) to circuit SHP via switch AS2. At time T23m, circuit SHP acquires X(T22). At time T24, circuit SHP holds X(T22) and transmits X(T22) to drive circuit SCD via switch AS3. 【0313】Furthermore, circuit SHN transmits signals X(T24) and X(T26), which are output signals from circuit RL, at the timings of time T24 and time T26, respectively. Also, X(T24) and X(T26), as in the case of X(T22) described above, can be sequentially transitioned in the order of circuit SHN, circuit SHP, and drive circuit SCD by clock signals transmitted to wiring PCKp and PCKn, and control signals transmitted to wiring GTLn and GTLp. 【0314】 By using the drive circuit ITS shown in Figure 13A, pipeline processing can be performed on the calculation result output from circuit RL according to the respective frequencies of the clock signal and control signal. In other words, by varying the frequencies of the clock signal and control signal, the calculation result can be transitioned stepwise through circuit SHN, circuit SHP, and drive circuit SCD, thereby adjusting the delay time (time constant) from when the calculation result performed in circuit RL is output to the output terminal of drive circuit ITS. 【0315】 By adjusting the time constant from the time the calculation result performed in circuit RL is output to the output terminal of drive circuit ITS, the convergence time of the calculation result output by the calculation unit CDV to wiring OL can be shortened or lengthened, thereby stabilizing the calculation performed by the calculation unit CDV. This allows the value of the calculation result to be brought closer to the expected value. 【0316】 Furthermore, the circuits ITSr[j] and ITSo according to one aspect of the present invention are not limited to the configuration of circuit ITSa shown in Figure 14A. For example, the circuit configuration of circuit ITSb shown in Figure 14B can be applied to circuits ITSr[j] and ITSo. 【0317】The circuit ITSb shown in Figure 14B is a modified version of the circuit configurations of circuits SHN and SHP present in the circuit ITSa in Figure 14A. Specifically, the circuit SHN in Figure 14B has the same configuration as the circuit SHN in Figure 14A, but with the addition of transistors MN5i, MN5o, MN9, and a capacitive element C9. Similarly, the circuit SHP in Figure 14B has the same configuration as the circuit SHP in Figure 14A, but with the addition of transistors MP5i, MP5o, MN10, and a capacitive element C10. 【0318】 In circuit SHN, transistor MN5i is cascode-connected to transistor MN6i. Specifically, the first terminal of transistor MN5i is connected to the first terminal of transistor MN7, and the second terminal of transistor MN5i is connected to the first terminal of transistor MN6i. Also, transistor MN5o is cascode-connected to transistor MN6i. Specifically, the first terminal of transistor MN5o is connected to the first terminals of transistors Tr9p and Tr9n of switch AS2, and the second terminal of transistor MN5o is connected to the first terminal of transistor MN6i. 【0319】 Furthermore, the gates of transistors MN5i and MN5o are connected to wiring VE5. The first and second terminals of transistor MN9 are connected to the second terminal of transistor MN7. The gate of transistor MN9 is connected to wiring GTLnb. The first terminal of capacitive element C9 is connected to the gates of transistors MN6i and MN6o, and the second terminal of capacitive element C9 is connected to wiring VS3. 【0320】 The wiring GTLnb functions as a wire that supplies potential to the gate of transistor MN9 in order to raise the potential of node SN1 through capacitive coupling when transistor MN7 is in the off state, that is, when node SN1 is in a floating state. 【0321】Furthermore, wiring GTLnb may function as a wiring pair with wiring GTLn, and as a wiring that transmits a signal whose logic is inverted from the signal supplied to wiring GTLn. 【0322】 Transistor MN5i functions as a clamp transistor to prevent a drop in the threshold voltage due to DIBL in transistor MN6i. Similarly, transistor MN5o functions as a clamp transistor to prevent a drop in the threshold voltage due to DIBL in transistor MN6o. For this reason, it is preferable that wiring VE5 be used to provide an arbitrary fixed potential to the gates of transistors MN5i and MN5o, respectively. Since transistors MN5i and MN5o are n-channel transistors, if the fixed potential is equal to the fixed potential provided by wiring VE2, wiring VE5 and wiring VE2 can be combined into the same wiring. 【0323】 Furthermore, transistor MN9 functions as a capacitive element with its gate capacitance as its capacitance. It is preferable that the gate capacitance of transistor MN9 be equal to that of transistor MN7. Therefore, it is preferable that the structure and size of transistor MN9 be the same as those of transistor MN7. 【0324】 Transistor MN9 is provided to prevent fluctuations in the potential of node SN1 due to the potential applied to the gate of transistor MN7. For example, in the circuit configuration of SHN shown in Figure 15A, when the gate potential of transistor MN7 changes from a high level potential to a low level potential, the potential of node SN1 may decrease due to capacitive coupling at the gate capacitance of transistor MN7. On the other hand, in the SHN circuit shown in Figure 15B, by changing the gate potential of transistor MN7 from a high level potential to a low level potential, and changing the gate potential of transistor MN9 from a low level potential to a high level potential, the change in the potential of node SN1 due to such capacitive coupling can be largely canceled out. 【0325】In addition, for the SHN circuit, a capacitive element with approximately equal gate capacitance and capacitance to transistor MN7 may be used instead of transistor MN9. 【0326】 Capacitive element C9 functions as a capacitive element for maintaining the gate-source voltages of transistors MN6i and MN6o, respectively. By providing capacitive element C9, fluctuations in the potential of node SN1 due to the off-current of transistor MN7, or leakage current between the gate of transistor MN9 and the first or second terminal, can be prevented. 【0327】 In circuit SHP, transistor MP5i is cascode-connected to transistor MP6i. Specifically, the first terminal of transistor MP5i is connected to the first terminal of transistor MN8, and the second terminal of transistor MP5i is connected to the first terminal of transistor MP6i. Also, transistor MP5o is cascode-connected to transistor MP6i. Specifically, the first terminal of transistor MP5o is connected to the first terminals of transistors Tr9p and Tr9n of switch AS3, and the second terminal of transistor MP5o is connected to the first terminal of transistor MP6i. 【0328】 Furthermore, the gates of transistor MP5i and transistor MP5o are connected to wiring VE6. The first and second terminals of transistor MN10 are connected to the second terminal of transistor MN8. The gate of transistor MN10 is connected to wiring GTLpb. The first terminal of capacitive element C10 is connected to the gates of transistor MP6i and transistor MP6o, and the second terminal of capacitive element C10 is connected to wiring VD3. 【0329】 The wiring GTLpb functions as a wire that supplies potential to the gate of transistor MN10 in order to raise the potential of node SN2 through capacitive coupling when transistor MN8 is in the off state, that is, when node SN2 is in a floating state. 【0330】Furthermore, wiring GTLpb may function as a wiring pair with wiring GTLp, and as wiring that transmits a signal whose logic is inverted from the signal supplied to wiring GTLp. 【0331】 Each of transistors MP5i and MP5o functions as a clamp transistor, similar to transistors MN5i and MP5o described above. Therefore, it is preferable that wiring VE6, similar to wiring VE5, be used to provide an arbitrary fixed potential to the gates of each of transistors MP5i and MP5o. Since transistors MP5i and MP5o are n-channel transistors, if the fixed potential is equal to the fixed potential provided by wiring VE1 or wiring VE3, wiring VE6 and one or both of wiring VE1 and wiring VE3 can be combined as the same wiring. 【0332】 Furthermore, transistor MN10, like transistor MN9 described above, is a circuit element that prevents fluctuations in the potential of node SN2 due to changes in the gate potential of transistor MN8. For this reason, the explanation of transistor MN9 can be used to describe transistor MN10. 【0333】 Capacitive element C10 functions as a capacitive element for maintaining the gate-source voltages of transistors MP6i and MP6o, respectively. By providing capacitive element C10, fluctuations in the potential of node SN2 due to the off-current of transistor MN8, or leakage current between the gate of transistor MN10 and the first or second terminal, can be prevented. 【0334】Furthermore, wiring GTLnb and GTLpb may be grouped together with wiring PCKp and PCKn, along with wiring GTLn and GTLp, similar to circuit ITSa shown in Figure 15A. For example, circuit ITSb shown in Figure 15B is configured in the same way as circuit ITSb in Figure 14B, with the gate of transistor MN9 connected to wiring PCKn and the gate of transistor MN10 connected to wiring PCKp. In other words, wiring GTLnb and GTLpb may be supplied with the clock signal provided by wiring PCKp and PCKn as control signals to circuits SHN and SHP. 【0335】 By applying circuit ITSb to circuits ITSr[j] and ITSo of the drive circuit ITS in Figure 13A, the operation of the drive circuit ITS can be stabilized. This allows for higher calculation accuracy in the arithmetic unit CDV. 【0336】 <Example of modification of semiconductor device 2> Next, as a drive circuit ITS related to one aspect of the present invention, an example of a modification of the circuit configuration of the drive circuit ITS shown in Figure 7A, which is different from the drive circuit ITS shown in Figure 13A, will be described. 【0337】 The drive circuit ITS shown in Figure 17 is an example of a modified circuit configuration of the drive circuit ITS in Figure 7A, and can perform Leaky Integrator model calculations in ESN. The Leaky Integrator model is a calculation model that holds the signals output from the neurons in the reservoir layer as past internal states and performs a weighted average of the newly output signals from the neurons in the reservoir layer and the said past internal states. By performing this weighted average calculation, it is possible to prevent the past internal information from the neurons in the reservoir layer from being instantly overwritten, and the influence of the said past internal information can be retained in the newly output signals from the neurons in the reservoir layer. In other words, by using the calculation unit CDV equipped with the drive circuit ITS of Figure 17, it is possible to perform ESN that reflects the influence of past internal information. 【0338】Furthermore, the drive circuit ITS in Figure 17 is configured to perform pipeline processing, similar to the drive circuit ITS in Figure 13A, and this pipeline processing allows for adjustment of the timing of the signal output from circuit ITSr to drive circuit SCD. 【0339】 The drive circuit ITS in Figure 17 has a configuration in which, in addition to the circuit ITSr[j] provided in the drive circuit ITS of Figure 7A, switches AS1, AS5 to AS8, calculation cell MCf, calculation cell MCb, and circuit SHD are added. Furthermore, the drive circuit ITS in Figure 17 has circuits XCDL and WSDL for driving circuit ITSr[j], and drive cells DCf and DCb. Figure 17 also shows the drive circuit SCD to illustrate the connection configuration with the drive circuit ITS. 【0340】 Furthermore, the circuit ITSo included in the drive circuit ITS in Figure 17 can be described by referring to the explanation of circuit ITSo shown in Figure 7A. 【0341】 In the drive circuit ITS of Figure 17, the calculation result is transmitted from circuit ITSo to wiring OL. However, the Leaky Integrator model calculation may also be performed on the calculation result and transmitted again to the reservoir layer. For example, the drive circuit ITS of Figure 18 may be applied as the drive circuit ITS of a semiconductor device according to one aspect of the present invention. The drive circuit ITS of Figure 18 has the same configuration as circuit ITSr[j] for circuit ITSo, and is configured to perform the Leaky Integrator model calculation in circuit ITSo as well. Furthermore, the wiring OL of Figure 18 may be connected to the calculation circuit CCr included in the region Car of the calculation unit CA for transmitting the output result to the reservoir layer, for example. In the following description, it will be assumed that the drive circuit ITS of Figure 17 is applied to the calculation device CDV of Figure 1. 【0342】For switches AS1 and AS5 to AS8, the descriptions of switches SAP and SAN above can be found in the same way as for switches AS1 to AS3 shown in Figure 13A. Therefore, each of switches AS1 and AS5 to AS8 can be a switch that can be applied to switch SAP or switch SAN as described above. 【0343】 In the circuit ITSr[j] of Figure 17, the first terminal of switch AS1 is connected to the output terminal of circuit RL, and the second terminal of switch AS1 is connected to the calculation cell MCf and the first terminal of switch AS5. The first terminal of switch AS6 is connected to the calculation cell MCb and the first terminal of switch AS8. The second terminal of switch AS5 is connected to the second terminal of switch AS6 and the input terminal of circuit SHD. One of the two output terminals of circuit SHD is connected to the second terminal of switch AS8, and the other of the two output terminals of circuit SHD is connected to the first terminal of switch AS7. The control terminals of switch AS1, switch AS7, and switch AS8 are each connected to wiring PCK1. The control terminals of switch AS5, switch AS6, and circuit SHD are connected to wiring PCK2. 【0344】 Furthermore, circuit XDf, drive cell DCf, and calculation cell MCf included in circuits ITSr[j] and ITSo, respectively, are connected to wiring XLf. Also, circuit XDb, drive cell DCb, and calculation cell MCb included in circuits ITSr[j] and ITSo, respectively, are connected to wiring XLb. Furthermore, circuit WSDL, drive cells DCf and DCb, and calculation cells MCf and MCb included in circuits ITSr[j] and ITSo, respectively, are connected to wiring SLbf. 【0345】 Furthermore, in the circuit ITSr[j] shown in Figure 17, the second terminal of switch AS7 is connected to the drive circuit SCD. 【0346】In Figure 17, wiring PCK1 and wiring PCK2 each function as wiring that transmits control signals to operate switches AS1 and AS5 to AS8, and the circuit SHD, respectively. In the drive circuit ITS in Figure 17, data can be transmitted stepwise by pipeline processing, similar to the drive circuit ITS in Figure 13A. Therefore, it is preferable that wiring PCK1 and wiring PCK2 are input to clock signals with their logic inverted relative to each other. 【0347】 Circuit RL, as an example, similar to the circuit RL shown in Figure 7 or Figure 13A, has the function of acquiring the difference between the current flowing through the first input terminal and the current flowing through the second input terminal, inputting a value corresponding to this difference into an activation function, and outputting the calculation result of the activation function as a signal to the output terminal of circuit RL. For example, when the input value U(t) from wiring IXLi is input to the arithmetic unit CDV at time t, the calculation result output from the output terminal of circuit RL is expressed as the value ΔXo[j](t) as shown in equation (1.12) below, using equation (1.10). 【0348】 【0349】 Circuit SHD, for example, functions as a sample-and-hold circuit, similar to circuit SHP shown in Figure 13A. Therefore, circuit SHD has the function of holding a value corresponding to a signal input to the input terminal, and the function of outputting a signal corresponding to that value to the output terminal in response to a control signal input to the control terminal. Furthermore, circuit SHD differs from circuit SHP in that it has two output terminals and outputs a signal corresponding to the held value to each output terminal. For example, at time t, when the input value U(t) from wiring IXLi is input to the arithmetic unit CDV, the value Xo[j](t-s) is held in circuit SHD. Furthermore, while circuit SHD is holding the value Xo[j](t-s), circuit SHD will output a signal corresponding to the value Xo[j](t-s) from each of its two output terminals. 【0350】The calculation cell MCf has the function of acquiring a signal indicating the value ΔXo[j](t) output from circuit RL, for example, and holding the potential corresponding to the value ΔXo[j](t). The calculation cell MCf also has the function of outputting a signal which is the product of the value ΔXo[j](t) corresponding to the held potential and the value corresponding to the potential applied to wiring XLf. Here, for example, if the value corresponding to the potential applied to wiring XLf is denoted as the leakage rate (also called the forgetting rate) δ, the calculation cell MCf will output a signal corresponding to δΔXo[j](t). In this specification, the leakage rate δ may be referred to as the first coefficient in the weighted average, etc. 【0351】 Similarly, the arithmetic cell MCb has the function of acquiring a signal indicating the value Xo[j](t-s) output from, for example, one of the two output terminals of the circuit SHD, and holding the potential corresponding to the value Xo[j](t-s). The value Xo[j](t-s) held in the arithmetic cell MCb represents the past internal state in the Leaky Integrator model. The arithmetic cell MCb also has the function of outputting a signal which is the product of the value Xo[j](t-s) corresponding to the held potential and the value corresponding to the potential applied to the wiring XLb. Here, for example, if the memory rate ζ is the value corresponding to the potential applied to the wiring XLb, the arithmetic cell MCb will output a signal corresponding to ζXo[j](t-s). In this specification, the memory rate ζ may be referred to as the second coefficient in the weighted average, etc. 【0352】 The leakage rates δ and ζ are real numbers greater than 0 and less than or equal to 1. In particular, it is preferable that δ + ζ = 1. That is, it is preferable that ζ = 1 - δ. However, depending on the situation, the leakage rate δ and the memory rate ζ do not have to satisfy δ + ζ = 1. Also, for example, the leakage rates δ and ζ may be real numbers greater than or equal to 0, or they may be greater than 1. Also, for example, δ + ζ < 1 or δ + ζ > 1 may be set. 【0353】The drive cell DCf, like the drive cells DCi and DCo described above, has the function of acquiring a signal transmitted from circuit XCDL as a reference value R1, for example, and maintaining a potential corresponding to the reference value R1. Furthermore, after the drive cell DCf has maintained the potential, when a signal corresponding to the leakage rate δ is transmitted to the drive cell DCf, the drive cell DCf has the function of maintaining the input potential and current corresponding to the leakage rate δ. Similarly, the drive cell DCb has the function of acquiring a signal transmitted from circuit XCDL as a reference value R2, for example, and maintaining a potential corresponding to the reference value R2. Furthermore, after the drive cell DCb has maintained the potential, when a signal corresponding to the memory rate ζ(=1-δ) is transmitted to the drive cell DCb, the drive cell DCf has the function of maintaining the input potential and current corresponding to the memory rate ζ(=1-δ). 【0354】 Circuit XCDL includes, as an example, circuit XDf and circuit XDb. Circuit XDf, like circuits XDi and XDR[j] described above, has the function of converting the reference value R1 into a reference signal and transmitting it to the drive cell DCf and the calculation cell MCf via wiring XLf. Circuit XDf also has the function of converting the leakage rate δ into a signal and transmitting the signal to the drive cell DCf and the calculation cell MCf via wiring XLf. Similarly, circuit XDb has the function of converting the reference value R2 into a reference signal and transmitting it to the drive cell DCb and the calculation cell MCb via wiring XLb. Circuit XDb also has the function of converting the memory rate ζ (= 1 - δ) into a signal and transmitting the signal to the drive cell DCb and the calculation cell MCb via wiring XLb. 【0355】 Circuit WSDL has a function to send a selection signal to wiring SLbf when, for example, it writes the calculation result ΔXo[j](t) output from circuit RL to calculation cell MCf, and writes the value Xo[j](t-s) output from one side of circuit SHD to calculation cell MCb. In addition, circuit WSDL has a function to send a non-selection signal to wiring SLbf when no value is written to calculation cell MCf or calculation cell MCb. 【0356】When the calculation cell MCf outputs a signal corresponding to the product δΔXo[j](t) of the value ΔXo[j](t) and the leakage rate δ, and the calculation cell MCb outputs ζXo[j](t-s) of the product ζXo[j](t-s) of the value Xo[j](t-s) and the memory rate ζ (=1-δ), the sum of these signals is input to the input terminal of the circuit SHD. In other words, the result of a weighted average processing of ΔXo[j](t) corresponding to the signal newly output from the neurons in the reservoir layer and the value Xo[j](t-s) of the past internal state is input to the input terminal of the circuit SHD. Specifically, the circuit SHD receives a signal corresponding to ζXo[j](t-s) + δΔXo[j](t) as a value. Here, Xo[j](t) is defined as shown in equation (1.13) below. 【0357】 【0358】 At this time, the circuit SHD is assumed to hold the value Xo[j](t). Furthermore, since the circuit SHD holds the value Xo[j](t), it outputs a signal corresponding to the value Xo[j](t) from each of its two output terminals. As a result, the drive circuit ITS in Figure 17 can transmit the output signal from the reservoir layer neurons, including the influence of past internal states, as the value Xo[j](t) to the drive circuit SCD. The value Xo[j](t) transmitted to the drive circuit SCD is then recursively provided to the j-th row of the arithmetic unit CA, as described in the explanation of the drive circuit SCD in Figure 1. Therefore, by using the drive circuit ITS in Figure 17, the arithmetic unit CDV can perform ESN calculations employing the Leaky Integrator model. 【0359】 <<Examples of drive cell and calculation cell configurations>> Next, we will explain the configuration examples of the drive cell DCf, drive cell DCb, calculation cell MCf, and calculation cell MCb shown in Figure 17. 【0360】 For example, the drive cell DC shown in Figures 5A and 5B can be applied to the drive cell DCf and drive cell DCb in Figure 17, respectively. Also, for example, the calculation cell MCp or calculation cell MCn shown in Figures 5A and 5B can be applied to the calculation cell MCf and calculation cell MCb in Figure 17, respectively. 【0361】 Figure 19 is a circuit diagram showing a circuit configuration in which the drive cell DC shown in Figure 5A is applied to the drive cell DCf and the drive cell DCb, respectively, and the calculation cell MCp shown in Figure 5A is applied to the calculation cell MCf and the calculation cell MCb, respectively. In addition, Figure 19 also shows switches AS1, AS5 to AS8, and circuit SHD to explain the connection configuration around the drive cell DCf, the drive cell DCb, the calculation cell MCf, and the calculation cell MCb. 【0362】 The drive cell DCf has transistor M1df, transistor M3df, transistor M4df, and capacitive element C1df. The drive cell DCb has transistor M1db, transistor M3db, transistor M4db, and capacitive element C1db. Transistors M1df and M1db each correspond to transistor M1d of the drive cell DC in Figure 5A, transistors M3df and M3db each correspond to transistor M3d of the drive cell DC in Figure 5A, transistors M4df and M4db each correspond to transistor M4d of the drive cell DC in Figure 5A, and capacitive elements C1df and C1db each correspond to capacitive element C1d of the drive cell DC in Figure 5A. 【0363】 The calculation cell MCf includes transistor M1f, transistor M3f, transistor M4f, and capacitive element C1f. The calculation cell MCb includes transistor M1b, transistor M3b, transistor M4b, and capacitive element C1b. Transistors M1f and M1b each correspond to transistor M1p of the calculation cell MCp in Figure 5A, transistors M3f and M3b each correspond to transistor M3p of the calculation cell MCp in Figure 5A, transistors M4f and M4b each correspond to transistor M4p of the calculation cell MCp in Figure 5A, and capacitive elements C1f and C1b each correspond to capacitive element C1 of the calculation cell MCp in Figure 5A. 【0364】For the connection configurations of the drive cell DCf, drive cell DCb, arithmetic cell MCf, and arithmetic cell MCb, please refer to the explanation of the connection configuration in the circuit diagram of Figure 5A. Therefore, a connection configuration different from that in Figure 5A will be described here. 【0365】 In drive cell DCf, the second terminal of transistor M1df, the second terminal of transistor M4df, and the second terminal of capacitive element C1df are connected to wiring XLf. In drive cell DCb, the second terminal of transistor M1db, the second terminal of transistor M4db, and the second terminal of capacitive element C1db are connected to wiring XLb. 【0366】 Furthermore, in the calculation cell MCf, the second terminal of transistor M1f and the second terminal of transistor M4f are connected to the second terminal of switch AS1 and the first terminal of switch AS5, and the second terminal of capacitive element C1f is connected to wiring XLf. Furthermore, in the calculation cell MCb, the second terminal of transistor M1b and the second terminal of transistor M4b are connected to the first terminal of switch AS6 and the first terminal of switch AS8, and the second terminal of capacitive element C1b is connected to wiring XLb. 【0367】 Furthermore, the gates of transistors M1f, M1b, M1df, and M1db are connected to the wiring SLbf. 【0368】 In Figure 19, the connection point between the first terminal of transistor M1f, the gate of transistor M3f, and the first terminal of capacitive element C1f is defined as node Nf. Similarly, the connection point between the first terminal of transistor M1b, the gate of transistor M3b, and the first terminal of capacitive element C1b is defined as node Nb. 【0369】 <<Example Configuration of Circuit SHD and Switches AS1 and AS5 to AS8>> Next, an example configuration of Circuit SHD, Switch AS1, and Switches AS5 to AS8 shown in Figure 17 will be described. 【0370】Figure 20 shows an example of a specific circuit configuration of circuit ITSr[j], which includes circuit SHD from Figure 17, switch AS1, and switches AS5 to AS8. The circuit ITSc shown in Figure 20 is an example of the configuration of circuit ITSr[j] from Figure 17. Furthermore, the circuit SHD shown in Figure 20 is a modified version of the circuit SHP shown in Figure 14A, with the addition of a p-channel transistor, transistor MP6m, to circuit SHP. 【0371】 The circuit SHD in Figure 20 is a sample-and-hold circuit with a p-channel current mirror circuit and a writing transistor MN8, similar to the circuit SHP in Figure 14A. The circuit SHD in Figure 20 is also similar to the circuit SHP in Figure 14A in that the first terminal of transistor MP6i and the first terminal of transistor MN8 correspond to the input terminals of the circuit SHD, and the gate of transistor MN8 is the control terminal of the circuit SHD. The circuit SHD in Figure 20 differs from the circuit SHP in Figure 14A in that the first terminal of transistor MP6m corresponds to one of the two output terminals of the circuit SHD, and the first terminal of transistor MP6o corresponds to the other of the two output terminals of the circuit SHD. 【0372】 Furthermore, since the calculation cells MCf and MCb in Figure 20 have a current-drawing configuration, the circuit SHD has a current-discharging configuration. For this reason, it is preferable that the polarities of transistors M1f, M3f, M4f, M1b, M3b, and M4b contained in calculation cells MCf and MCb are different from the polarities of transistors MP6i and MP6o contained in the circuit SHD. 【0373】 Furthermore, in the circuit diagram of circuit ITSc in Figure 20, the same configuration as that of the analog switches AS1 to AS3 shown in Figure 13 is applied to each of switches AS1 and AS5 to AS8. Therefore, the connection configuration of switches AS1 and AS5 to AS8 in Figure 20 can be explained in Figure 13. 【0374】 The first terminal of transistor Tr9p and the first terminal of transistor Tr9n of switch AS1 are connected to the output terminal of circuit RL. In addition, the second terminal of transistor Tr9p and the first terminal of transistor Tr2n of switch AS1 are connected to the second terminal of transistor M1f and the second terminal of transistor M4f of arithmetic cell MCf, and to the first terminal of transistor Tr9p and the first terminal of transistor Tr9n of switch AS5. 【0375】 In Figure 20, as in Figure 14A, the connection point between the first terminal of transistor Tr9p and the first terminal of transistor Tr9n of switch AS1 and the output terminal of circuit RL is referred to as node A1Ti. 【0376】 The first terminal of transistor Tr9p and the first terminal of transistor Tr9n of switch AS6 are connected to the second terminal of transistor M1b and the second terminal of transistor M4b of arithmetic cell MCb, and to the first terminal of transistor Tr9p and the first terminal of transistor Tr9n of switch AS8. 【0377】 In the circuit SHD of Figure 20, the first terminal of transistor MP6i and the first terminal of transistor MN8 are connected to the second terminal of transistor Tr9p and the second terminal of transistor Tr9n of switch AS5, and to the second terminal of transistor Tr9p and the second terminal of transistor Tr9n of switch AS6. The gate of transistor MP6m is connected to the gate of transistor MP6i, the gate of transistor MP6o, and the second terminal of transistor MN8. The first terminal of transistor MP6m is connected to the second terminal of transistor Tr9p and the second terminal of transistor Tr9n of switch AS8. The second terminal of transistor MP6m is connected to wiring VD3. The first terminal of transistor MP6o is connected to the first terminal of transistor Tr9p and the first terminal of transistor Tr9n of switch AS7. 【0378】In Figure 20, the connection point between the gate of transistor MP6i, the gate of transistor MP6o, the gate of transistor MP6m, and the second terminal of transistor MN8 is referred to as node SN2, as in Figure 14A. Also in Figure 20, the connection point between the second terminal of transistor Tr9p and the second terminal of transistor Tr9n of switch AS7 is referred to as node A3To, as in Figure 14A. 【0379】 Furthermore, in switches AS1, AS7, and AS8, the gate of transistor Tr9p is connected to wiring PCKn, and the gate of transistor Tr9n is connected to wiring PCKp. Also, in switches AS5 and AS6, the gate of transistor Tr9p is connected to wiring PCKp, and the gate of transistor Tr9n is connected to wiring PCKn. 【0380】 Wiring PCKp and PCKn correspond to wiring PCK1 and PCK2 shown in Figure 17, and, similar to circuit ITSa in Figure 14A, they function as wiring that transmits control signals to operate switches AS1 and switches AS5 to AS8, respectively. Specifically, wiring PCKp in Figure 20 can be wiring PCK1 in Figure 17, and wiring PCKn in Figure 20 can be wiring PCK2 in Figure 17. Since switches AS1 and AS5 to AS8 are analog switches, wiring PCKp and PCKn in Figure 20 are a wiring pair that transmits signals that are in opposite phase to each other. For example, in Figure 20, by inputting clock signals with inverted logic to each other to the wiring pair of wiring PCKp and PCKn, pipeline processing becomes possible in circuit ITSc, similar to circuit ITSa in Figure 14A. Furthermore, the speed of the pipeline processing can be adjusted by changing the frequency of the clock signal. 【0381】Furthermore, the gate of transistor MN8 is connected to wiring GTLp. Wiring GTLp corresponds to wiring GTLp shown in Figure 14A, and, similar to circuit ITSa in Figure 14A, it functions as wiring that transmits control signals for controlling circuit SHD. 【0382】 As shown in the change in the circuit configuration of circuit ITSa from Figure 14A to Figure 15A, the wiring GTLp in Figure 20 may be combined with the wiring PCKn. The circuit ITSc shown in Figure 21 is configured in the same way as circuit ITSc in Figure 20, but with the gate of transistor MN8 connected to the wiring PCKn. In other words, the wiring PCKn may be used to transmit control signals for operating circuit SHD. 【0383】 Note that the circuit ITSr[j] in Figure 17, according to one aspect of the present invention, is not limited to the configuration of the circuit ITSc shown in Figure 20. For example, the circuit configuration of the circuit ITSd shown in Figure 22 can be applied to the circuit ITSr[j]. 【0384】 The circuit ITSd shown in Figure 22 is a modified version of the circuit SHD found in the circuit ITSc in Figure 20. Specifically, the circuit SHD in Figure 22 has the addition of transistors MP5i, MP5o, MP5m, MN10, and capacitive element C10 to the circuit SHD in Figure 20. Some of the configuration of the circuit SHD in Figure 22 can be referenced from the configuration of the circuit SHP in Figure 14B. 【0385】In circuit SHD, transistor MP5i is cascode-connected to transistor MP6i, similar to transistor MP5i in circuit SHP in Figure 15B. Similarly, transistor MP5o is cascode-connected to transistor MP6o, similar to transistor MP6o in circuit SHP in Figure 15B, and transistor MP5m is cascode-connected to transistor MP6m. Specifically, the first terminal of transistor MP5m is connected to the first terminals of transistors Tr9p and Tr9n of switch AS8. Furthermore, the second terminal of transistor MP5m is connected to the first terminal of transistor MP6m, and the gate of transistor MP5m is connected to wiring VE5. 【0386】 Furthermore, the first terminal of the capacitive element C10 is connected to the gates of transistors MP6i, MP6o, and MP6m, respectively. Also, the first and second terminals of transistor MN10 are connected to the second terminal of transistor MN8, and the gate of transistor MN10 is connected to the wiring GTLpb. 【0387】 Wiring GTLpb is the wiring corresponding to wiring GTLpb shown in Figure 14B, and, similar to circuit ITSa in Figure 14B, it functions as wiring that transmits a signal inverted in logic of the control signal transmitted to wiring GTLp. 【0388】 Circuit SHD, like circuit SHP in Figure 14B, includes transistors MP5i, MP5o, and MP5m, which function as clamp transistors. This allows transistors MP6i, MP6o, and MP6m to prevent threshold voltage fluctuations caused by DIBL. 【0389】 Furthermore, circuit SHD, like circuit SHP in Figure 14B, includes transistor MN10 to prevent fluctuations in the potential of node SN2. This prevents fluctuations in the potential of node SN2 caused by changes in the gate potential of transistor MN8. 【0390】Furthermore, circuit SHD, like circuit SHP in Figure 14B, includes capacitive elements C10 for maintaining the gate-source voltages of transistors MP6i, MP6o, and MP6m. This prevents fluctuations in the potential of node SN2 due to the off-current of transistor MN8 or leakage current between the gate of transistor MN10 and the first or second terminal. 【0391】 Furthermore, as shown in the change in the circuit configuration of circuit ITSa from Figure 14B to Figure 15B, the wiring GTLp and GTLpb in Figure 22 may be combined with wiring PCKp and PCKn. The circuit ITSc shown in Figure 23 is configured in the same way as circuit ITSc in Figure 22, but with the gate of transistor MN8 connected to wiring PCKn and the gate of transistor MN10 connected to wiring PCKp. In other words, wiring PCKp and wiring PCKn may each be used to transmit control signals for operating circuit SHD. 【0392】 By applying circuit ITSd to circuit ITSr[j] of the drive circuit ITS in Figure 17, the operation of the drive circuit ITS can be stabilized. This allows for higher calculation accuracy in the arithmetic unit CDV. 【0393】 <<Example of Circuit ITSc Operation>> Next, an example of the operation of Circuit ITSr[j] in Figure 17 will be explained using the timing chart in Figure 24 and the block diagrams in Figures 25A to 26. Note that the Circuit ITSr[j] dealt with in this example of operation is assumed to be Circuit ITSc in Figure 20. Furthermore, in this example of operation, Circuit ITSc in Figure 20 will be explained as being applied to Circuit ITSr[j] of the arithmetic unit CDV in Figure 1. 【0394】The timing chart in Figure 24 shows the changes in potential of wiring CLB, wiring PCKp, wiring PCKn, wiring SLbf, and wiring GTLp at and around times T31 to T44. The timing chart also shows the changes in the values ​​of the signals input to node A1Ti, wiring XLf, wiring XLb, node Nf, node SN2, node Nb, and node A3To. Furthermore, the timing chart in Figure 24 includes time T35m between times T35 and T36, time T36m between times T36 and T37, time T41m between times T41 and T42, and time T42m between times T42 and T43. 【0395】 When the circuit ITSc shown in Figure 17 is applied to the drive circuit ITS of the arithmetic unit CDV in Figure 1, the operations at times T31 to T44 and their vicinity shown in the timing chart of Figure 24 can be made to be operations that occur between times T18 and T19 in the timing chart of Figure 10. 【0396】 Between time T31 and time T44, a high-level potential is constantly applied to wiring CLB. As a result, switches SBp and SBn included in circuit ITSc are turned ON, and the result of the sum-of-products calculation performed in arithmetic unit CA is input to circuit RL. 【0397】 Furthermore, circuit RL calculates ΔXo, given by equation (1.12) above, as the value of the activation function obtained by substituting the result as a variable, and outputs the value ΔXo to the output terminal. Therefore, node A1Ti is supplied with a signal corresponding to the value ΔXo. In reality, the value ΔXo changes continuously with the passage of time, but for the sake of simplicity in this example, the values ​​of ΔXo supplied to node A1Ti at each timing from time T31 to time T44 are described as ΔXo(T31) to ΔXoX(T44). In particular, in the timing chart of Figure 24, ΔXo(T31), ΔXo(T33), ΔXo(T36), and ΔXo(T39) are shown as extracted values ​​of the signal supplied to node A1Ti. 【0398】Furthermore, the block diagrams of each circuit ITSc in Figures 25A to 26 show the result of the sum-of-accumulate operation output from the calculation unit CA, the value of the signal output by circuit RL, the value of the reference value R2 output by circuit XDb, the value of the reference value R1 output by circuit XDf, the value corresponding to the potential held by calculation cell MCf, the value corresponding to the potential held by calculation cell MCb, and the value corresponding to the potential held by circuit SHD. In particular, the block diagram of Figure 25A shows the operating state of circuit ITSc at times T33 to T35 in the timing chart of Figure 24. The block diagram of Figure 25B shows the operating state of circuit ITSc at time T36 in the timing chart of Figure 24. The block diagram of Figure 26 shows the operating state of circuit ITSc at times T39 to T41 in the timing chart of Figure 24. 【0399】 The "X" marks shown in Figures 25A to 26 indicate that signal transmission between circuits has stopped. In other words, the "X" marks indicate that the switch at that location is in the "off" state. Also, the drive circuit SCD is omitted from Figures 25A to 26. 【0400】 [Between time T31 and time T35] Between time T31 and time T35, the following operations occur: the value ΔXo output from circuit RL is written to calculation cell MCf, and the value Xo output from circuit SHD is written to calculation cell MCb. For the operation of writing values ​​to calculation cell MCf or calculation cell MCb, refer to the operation examples in the timing charts of Figures 6A and 6B. 【0401】 Between time T31 and time T35, a high-level potential is applied to wiring PCKp and a low-level potential is applied to wiring PCKn. As a result, switches AS1, AS7, and AS8 are turned ON, and switches AS5 and AS6 are turned OFF. 【0402】At time T31, the circuit RL outputs a signal corresponding to the value ΔXo(T31), which is the result of the activation function operation substituting the result of the sum-of-products operation performed by the arithmetic unit CA as a variable, to the output terminal. Also, since the switch AS1 is in the on state, the signal reaches the second terminals of the transistor M1f and the transistor M4f of the arithmetic cell MCf, and the first terminal of the switch AS5. 【0403】 Also, in the circuit SHD, since a low-level potential is applied to the wiring PCKn, the transistor MN8 is in the off state. Therefore, the circuit SHD holds the value input to the input terminal immediately before the transistor MN8 turns off, and outputs a signal corresponding to the value to both of the two output terminals. 【0404】 Note that before time T31, it is assumed that the value Xo(TP) is input to the input terminal of the circuit SHD, and between time T31 and time T35, the transistor MN8 is in the off state and the circuit SHD holds the value Xo(TP). Thereby, the circuit SHD outputs a signal corresponding to the value Xo(TP) from both of the two output terminals. In particular, since the switch AS7 is in the on state, a signal corresponding to the value Xo(TP) is applied to the node A3To. Also, since the switch AS8 is in the on state, a signal corresponding to the value Xo(TP) is also applied to the second terminals of the transistor M1b and the transistor M4b of the arithmetic cell MCb, and the first terminal of the switch AS6. Also, in the case of the circuit ITSc in FIG. 20, the signal is treated as a current corresponding to the value Xo(TP). 【0405】 Also, a signal corresponding to the value Xo(TP) output from the other of the two output terminals of the circuit SHD is input to the arithmetic unit CA. Therefore, the result of the sum-of-products operation performed by the arithmetic unit CA at time T31 is WiU(T31) + ΣWr × Xo(TP). Here, Σ indicates the summation for the rows of the region CAr of the arithmetic unit CA. 【0406】At time T32, as an example, a signal with a reference value R1 = 1 is transmitted from circuit XDf included in circuit XCDL to wiring XLf. Also, at time T32, as an example, a signal with a reference value R2 = 1 is transmitted from circuit XDb included in circuit XCDL to wiring XLb. 【0407】 At time T33, a high-level potential is applied from circuit WSDL to wiring SLbf. As a result, the transistors M1df of drive cell DCf and the transistor M1db of drive cell DCb are turned on. Therefore, a signal corresponding to the reference value R1 = 1 is applied to the gate of the transistor M3df of drive cell DCf, and a signal corresponding to the reference value R2 = 1 is applied to the gate of the transistor M3db of drive cell DCb. Also, as this signal, the source-drain current between each of the transistors M3df and M3db becomes Iut from the above formula (1.1). Note that Rf = R1 = R2 = 1. 【0408】 Also, at time T33, a high-level potential is applied from circuit WSDL to wiring SLbf. As a result, each of the transistors M1f of arithmetic cell MCF and the transistor M1b of arithmetic cell MCB is turned on. Therefore, a signal corresponding to the value ΔXo(T33) output from the output terminal of circuit RL is applied to node Nf of arithmetic cell MCF, and a signal corresponding to the value Xo(TP) output from one of the two output terminals of circuit SHD is applied to node Nb of arithmetic cell MCB. Also, the source-drain current of transistor M3f becomes an amount corresponding to the value ΔXo(T33), and the source-drain current of transistor M3b becomes an amount corresponding to the value Xo(TP). Also, the potential of the gate of transistor M3f becomes a height corresponding to the value ΔXo(T33), and the potential of the gate of transistor M3b becomes a height corresponding to the value Xo(TP). 【0409】At time T33, the arithmetic unit CA receives a signal corresponding to the value Xo(TP) output from the other of the two output terminals of circuit SHD. Therefore, the result of the sum-of-products calculation performed by the arithmetic unit CA at time T33 is WiU(T33) + ΣWr × Xo(TP). The result of this sum-of-products calculation is also input to the input terminal of circuit RL, and circuit RL outputs a signal to its output terminal corresponding to the value ΔXo(T33) = f[WiU(T33) + ΣWr × Xo(TP)], which is the result of the activation function in which the result of this sum-of-products calculation is substituted as a variable (see Figure 25A). 【0410】 At time T34, a low-level potential is applied from circuit WSDL to wiring SLbf. This turns off transistor M1df of drive cell DCf and transistor M1db of drive cell DCb. As a result, a potential corresponding to the reference value R1=1 is maintained at the gate of transistor M3df of drive cell DCf, and a potential corresponding to the reference value R2=1 is maintained at the gate of transistor M3db of drive cell DCb. 【0411】 Furthermore, at time T34, a low-level potential is applied from circuit WSDL to wiring SLbf, causing transistor M1f of calculation cell MCf and transistor M1b of calculation cell MCb to also turn off. As a result, node Nf maintains a potential corresponding to the value ΔXo (T33), and node Nb maintains a potential corresponding to the value Xo (TP) (see Figure 25A). 【0412】 With the above steps completed, the operation of writing the value ΔXo(T33) output from circuit RL to calculation cell MCf and the operation of writing the value Xo(TP) output from circuit SHD to calculation cell MCb are completed. 【0413】[Between time T35 and time T37] Between time T35 and time T37, the calculation cell MCf performs the operation of multiplying the held value ΔXo (T33) by the leakage rate δ transmitted from circuit XDf. Also, the calculation cell MCb performs the operation of multiplying the held value Xo (TP) by the memory rate ζ (= 1 - δ) transmitted from circuit XDb. For the multiplication operation of calculation cell MCf or calculation cell MCb, refer to the operation examples in the timing charts of Figures 6A and 6B. 【0414】 Between time T35 and time T37, a low potential is applied to wiring PCKp and a high potential is applied to wiring PCKn. As a result, switches AS1, AS7, and AS8 are turned off, and switches AS5 and AS6 are turned on. 【0415】 At time T35m, a high-level potential is applied to the wiring GTLp. This turns on transistor MN8. Therefore, at time T35m, a source-drain current of transistor M3f, corresponding to the value ΔXo(T33) held in the calculation cell MCf, flows through switch AS5 to the input terminal of circuit SHD. Also, a source-drain current of transistor M3b, corresponding to the value Xo(TP) held in the calculation cell MCb, flows through switch AS6 to the input terminal of circuit SHD. At this time, a current corresponding to the value Xo(TP) + ΔXo(T33) flows through the input terminal of circuit SHD, and a potential corresponding to the value Xo(TP) + ΔXo(T33) is applied to node SN2 of circuit SHD. 【0416】 At time T36, a signal representing the leakage rate δ is transmitted from circuit XDf, which is included in circuit XCDL, to wiring XLf. As a result, the calculation cell MCf multiplies the held value ΔXo(T33) by the leakage rate δ, and the potential of node Nf becomes a height corresponding to δΔXo(T33). Consequently, the source-drain current of transistor M3f flowing to the input terminal of circuit SHD changes to an amount corresponding to the value δΔXo(T33). 【0417】Furthermore, at time T36, a signal with a memory retention rate ζ (= 1 - δ) is transmitted from circuit XDb, which is included in circuit XCDL, to wiring XLb. As a result, the arithmetic cell MCb performs a multiplication of the held value Xo(TP) and the memory retention rate ζ (= 1 - δ), and the potential of node Nb becomes a height corresponding to ζXo(TP). Consequently, the source-drain current of transistor M3d flowing to the input terminal of circuit SHD changes to an amount corresponding to the value ζXo(TP). 【0418】 Therefore, at time T36, the current input to circuit SHD changes from an amount corresponding to the value Xo(TP) + ΔXo(T33) to an amount corresponding to the value ζXo(TP) + δΔXo(T33). From here on, we assume that ζXo(TP) + δΔXo(T33) = Xo(T33). Therefore, node SN2 of circuit SHD is given a potential corresponding to the value Xo(T33) (see Figure 25B). 【0419】 Furthermore, at time T36m, a low-level potential is applied to the wiring GTLp. This causes transistor MN8 of circuit SHD to turn off, and circuit SHD retains the value Xo (T33) that was input to the input terminal just before transistor MN8 turned off. 【0420】 With the above steps, the multiplication operation in each of the calculation cells MCf and MCb is completed. 【0421】 Furthermore, between time T35 and time T37, switch AS7 is in the off state, so no signal is transmitted from the other of the two output terminals of circuit SHD to arithmetic unit CA. Therefore, no multiply-accumulate calculation is performed in arithmetic unit CA, and no activation function calculation is performed in circuit RL. 【0422】 [Between time T37 and time T41] Between time T37 and time T41, the circuit SHD maintains a potential corresponding to the value Xo(T33) given to node SN2, and outputs a current corresponding to the value Xo(T33) to both output terminals of the circuit SHD. 【0423】Between time T37 and time T41, a high-level potential is applied to wiring PCKp and a low-level potential is applied to wiring PCKn. As a result, switches AS1, AS7, and AS8 are turned ON, and switches AS5 and AS6 are turned OFF. 【0424】 Furthermore, when switches AS7 and AS8 are turned ON, the circuit SHD outputs a signal corresponding to the held value Xo(T33) to both output terminals. 【0425】 Therefore, a signal corresponding to the value Xo(T33) is supplied to node A3To. In addition, signals corresponding to the value Xo(T33) are supplied to the second terminal of transistor M1b and the second terminal of transistor M4b of the arithmetic cell MCb, and to the first terminal of switch AS6. 【0426】 Furthermore, the arithmetic unit CA receives a signal corresponding to the value Xo (T39) output from the other of the two output terminals of the circuit SHD. Therefore, the result of the sum-of-products calculation performed by the arithmetic unit CA at time T37 is WiU (T37) + ΣWr × Xo (T33). 【0427】 Based on the above, the circuit ITSc can perform operations from time T31 to time T41 in the timing chart shown in Figure 24, thereby applying the Leaky Integrator model calculation to the activation function value ΔXo(T33) output from the circuit RL at time T33, and outputting the value Xo(T33) as a result of this calculation between time T37 and time T41. 【0428】 Furthermore, between time T37 and time T41, the same operations as between time T31 and time T35 occur: the value ΔXo output from circuit RL is written to calculation cell MCf, and the value Xo output from circuit SHD is written to calculation cell MCb. 【0429】Specifically, at time T37, similar to time T31, circuit RL outputs a signal to the output terminal corresponding to the value ΔXo(T37), which is the result of the activation function calculation obtained by substituting the sum-of-products calculation result WiU(T37) + ΣWr×Xo(T33) performed in the calculation unit CA as a variable. The signal corresponding to the value ΔXo(T37) is supplied to the second terminal of transistor M1f and the second terminal of transistor M4f of calculation cell MCf via switch AS1. Also, at time T38, similar to time T32, as an example, a signal with reference value R1=1 is transmitted from circuit XDf, which is included in circuit XCDL, to wiring XLf. Also, at time T32, as an example, a signal with reference value R2=1 is transmitted from circuit XDb, which is included in circuit XCDL, to wiring XLb. 【0430】 Furthermore, at time T39, similar to time T33, a high-level potential is supplied from circuit WSDL to wiring SLbf. As a result, a signal corresponding to the reference value R1=1 is supplied to the gate of transistor M3df of drive cell DCf, and a signal corresponding to the reference value R2=1 is supplied to the gate of transistor M3db of drive cell DCb. 【0431】 Furthermore, at time T39, the result of the sum-of-products operation performed by the arithmetic unit CA is WiU(T39) + ΣWr × Xo(T33). The circuit RL outputs a signal to its output terminal corresponding to the value ΔXo(T39), which is the result of the activation function operation in which the sum-of-products operation result WiU(T39) + ΣWr × Xo(T33) performed by the arithmetic unit CA is substituted as a variable. As a result, node Nf of the arithmetic cell MCf is given a signal corresponding to the value ΔXo(T39) output from circuit RL, and node Nb of the arithmetic cell MCb is given a signal corresponding to the value Xo(T33) output from one of the two output terminals of circuit SHD (see Figure 26). 【0432】Furthermore, at time T40, a low-level potential is applied from circuit WSDL to wiring SLbf. This causes transistor M1df of drive cell DCf and transistor M1db of drive cell DCb to turn off. As a result, a potential corresponding to the reference value R1=1 is maintained at the gate of transistor M3df of drive cell DCf, and a potential corresponding to the reference value R2=1 is maintained at the gate of transistor M3db of drive cell DCb. 【0433】 Furthermore, when a low-level potential is applied from circuit WSDL to wiring SLbf, transistor M1f of calculation cell MCf and transistor M1b of calculation cell MCb are both turned off. As a result, node Nf maintains a potential corresponding to the value ΔXo(T39), and node Nb maintains a potential corresponding to the value Xo(T33) (see Figure 26). 【0434】 This completes the process of writing the value ΔXo(T39) output from circuit RL at time T39 to calculation cell MCf, and the process of writing the value Xo(T33) output from circuit SHD to calculation cell MCb. 【0435】 [Between time T41 and time T43] Between time T41 and time T43, the calculation cell MCf performs the operation of multiplying the held value ΔXo (T39) by the leakage rate δ transmitted from circuit XDf. Also, the calculation cell MCb performs the operation of multiplying the held value Xo (T33) by the memory rate ζ (= 1 - δ) transmitted from circuit XDb. 【0436】 Between time T41 and time T43, a low potential is applied to wiring PCKp and a high potential is applied to wiring PCKn. As a result, switches AS1, AS7, and AS8 are turned off, and switches AS5 and AS6 are turned on. 【0437】Therefore, regarding the operation from time T41 to time T43, reference can be made to the description of the operation from time T35 to time T37 in the timing chart of FIG. 24. For example, in the description of the operation from time T35 to time T37 in the timing chart of FIG. 24, by replacing the value ΔXo(T33) with the value ΔXo(T39) and replacing the value Xo(TP) with the value Xo(T33), the operation from time T41 to time T43 can be described. 【0438】 From the above, at time T41, a current corresponding to Xo(T33)+ΔXo(T39) as a value flows through the input terminal of circuit SHD, and a potential corresponding to Xo(T33)+ΔXo(T39) as a value is applied to node SN2 of circuit SHD. Also, at time T42, the current input to circuit SHD changes from an amount corresponding to the value Xo(T33)+ΔXo(T39) to an amount corresponding to the value ζXo(T33)+δΔXo(T39). In FIG. 24, at node SN2, ζXo(T33)+δΔXo(T39)=Xo(T39) is set. Therefore, a potential corresponding to Xo(T39) as a value is applied to node SN2 of circuit SHD. 【0439】 [Between time T43 and time T44] Between time T43 and time T44, an operation is performed to hold the potential corresponding to the value Xo(T39) applied to node SN2 of circuit SHD and output the current corresponding to the value Xo(T39) to both of the two output terminals of circuit SHD. 【0440】 Specifically, similar to the operation from time T37 to time T38, a high-level potential is applied to wiring PCKp and a low-level potential is applied to wiring PCKn. As a result, switch AS1, switch AS7, and switch AS8 are turned on, and switch AS5 and switch AS6 are turned off. 【0441】Furthermore, in circuit SHD, a low potential is applied to the wiring PCKn, causing transistor MN8 to be in the off state. Therefore, circuit SHD holds the value Xo(T39) input to the input terminal just before transistor MN8 turns off, and outputs a signal corresponding to the value Xo(T39) to both output terminals. 【0442】 In particular, since switch AS7 is ON, a signal corresponding to the value Xo(T39) is supplied to node A3To. Also, since switch AS8 is ON, signals corresponding to the value Xo(T39) are supplied to the second terminal of transistor M1b and the second terminal of transistor M4b of arithmetic cell MCb, and to the first terminal of switch AS6. 【0443】 As a result, circuit ITSc performs operations from time T37 to time T44, similar to its operations from time T31 to time T41, thereby performing calculations using the Leaky Integrator model on the activation function value ΔXo(T39) output from circuit RL at time T39, and outputting the value Xo(T39) as a result of these calculations from time T43 onward. 【0444】 By performing the above operation example using the drive circuit ITS in Figure 17, the arithmetic unit CDV in Figure 1 can perform ESN calculations employing the Leaky Integrator model. This allows for weighted averaging of signals output from the neurons in the reservoir layer and past internal states, and enables the arithmetic unit CDV to output calculation results that include the influence of the past internal information. This improves the accuracy of ESN calculations. 【0445】 <Example 3 of modifications to the semiconductor device> Next, we will explain an example of a modification to the circuit configuration of the drive circuit ITS in Figure 17. 【0446】The drive circuit ITS shown in Figure 27 has fewer circuit elements than the drive circuit ITS shown in Figure 17. Specifically, the circuit ITSr of the drive circuit ITS in Figure 27 differs from the circuit ITSr of the drive circuit ITS in Figure 17 in that it does not include the switch AS8 and the circuit SHD has been changed to SHE. In the following, the parts of the drive circuit ITS shown in Figure 27 that differ from the circuit ITSr of the drive circuit ITS in Figure 17 will be explained, and for parts that are common to the circuit ITSr of the drive circuit ITS in Figure 17, refer to the explanation in Figure 17. 【0447】 The circuit SHE in Figure 27 has input / output terminals and an output terminal. The input / output terminals of circuit SHE are connected to the second terminal of switch AS5 and the second terminal of switch AS6. The output terminal of circuit SHE is connected to the first terminal of switch AS7. 【0448】 Furthermore, wiring PCK3 is connected to the control terminal of switch AS6. Wiring PCK3, like wiring PCK1 and wiring PCK2, functions as wiring to control the switching between the ON and OFF states of switch AS6. 【0449】 The circuit ITSe shown in Figure 28 is an example configuration of the circuit ITSr of the drive circuit ITS in Figure 27, and is also a modified example of the circuit ITSc shown in Figure 20. Therefore, the following will explain the parts of the circuit ITSe shown in Figure 28 that differ from the circuit ITSc in Figure 20, and refer to the explanation of Figure 20 for parts that are common with the circuit ITSc in Figure 20. 【0450】 Circuit SHE includes transistors MP6i, MP6o, and MN8, and unlike circuit SHD, it does not include transistor MP6m. The first terminal of transistor MP6i and the first terminal of transistor MN8 are connected to the input / output terminals of circuit SHE. The output terminal of circuit SHE is connected to the first terminal of switch AS7. 【0451】The second terminal of transistor Tr9p and the second terminal of transistor Tr9n of switch AS5, and the second terminal of transistor Tr9p and the second terminal of transistor Tr9n of switch AS6 are connected to the input / output terminals of circuit SHE. In addition, the gate of transistor Tr9p of switch AS6 is connected to wiring PCK3n, and the gate of transistor Tr9n of switch AS6 is also connected to wiring PCK3p. 【0452】 Wiring PCK3p and PCK3n in Figure 28 correspond to wiring PCK3 shown in Figure 27, and function as wiring that transmits control signals to operate switch AS3. In Figure 28, since switch AS3 is an analog switch, wiring PCK3p and PCK3n are a pair of wires that transmit signals that are in opposite phase to each other. 【0453】 Circuit SHD was configured to output the source-drain current of transistor MP6m from one of its two output terminals and supply it to the calculation cell MCb, whereas Circuit SHE is configured to output the source-drain current of transistor MP6i from its input / output terminals and supply it to the calculation cell MCb. 【0454】 As shown in Figure 28, circuit ITSe has fewer circuit elements than circuit ITSc, and as a result, the circuit area of ​​the drive circuit ITS can be reduced. 【0455】 Note that the circuit ITSr[j] in Figure 27, according to one aspect of the present invention, is not limited to the configuration of the circuit ITSe shown in Figure 28. For example, the circuit configuration of the circuit ITSf shown in Figure 29 can be applied to the circuit ITSr[j]. 【0456】 The circuit ITSf shown in Figure 29 is a modified version of the circuit SHE present in the circuit ITSe in Figure 28. Specifically, the circuit SHE in Figure 29 has the addition of transistors MP5i, MP5o, MN10, and capacitive element C10 to the circuit SHE in Figure 28. Some of the configuration of the circuit SHE in Figure 29 can be referenced from the configuration of the circuit SHP in Figure 14B. 【0457】Circuit SHE, like circuit SHP in Figure 14B, includes transistors MP5i and MP5o that function as clamp transistors. This prevents fluctuations in the threshold voltage due to DIBL for transistors MP6i and MP6o, respectively. Also, like circuit SHP in Figure 14B, circuit SHE includes transistor MN10 to prevent fluctuations in the potential of node SN2. This prevents fluctuations in the potential of node SN2 due to changes in the gate potential of transistor MN8. Furthermore, like circuit SHP in Figure 14B, circuit SHE includes capacitive elements C10 to maintain the gate-source voltages of transistors MP6i and MP6o, respectively. This prevents fluctuations in the potential of node SN2 due to the off-current of transistor MN8, or leakage current between the gate of transistor MN10 and the first or second terminal. 【0458】 Next, an example of the operation of circuit ITSr[j] in Figure 27 will be explained using the timing chart in Figure 30. Note that the circuit ITSr[j] used in this example is assumed to be the same as the circuit ITSe in Figure 28. Furthermore, in this example, circuit ITSe in Figure 28 will be explained as being applied to circuit ITSr[j] of the arithmetic unit CDV in Figure 1. 【0459】 Furthermore, the timing chart in Figure 30 is a modified example of the timing chart in Figure 24, and additionally shows the potential changes in wiring PCK3p and PCK3n. Also, it is assumed that there is a time T34m between time T34 and time T35, a time T36ma between time T36m and time T37, a time T40m between time T40 and time T41, and a time T42ma between time T42m and time T43. In this example of operation, only the parts that differ from the timing chart in Figure 24 will be explained, and for parts that are common with the timing chart in Figure 24, please refer to the explanation of the timing chart in Figure 24. 【0460】At time T31, a high-level potential is applied to wiring PCK3p, and a low-level potential is applied to wiring PCK3n. As a result, switch AS6 is turned on, and conduction occurs between the input / output terminals of circuit SHE and the calculation cell MCb. 【0461】 At time T33, a high-level potential is applied to the wiring SLbf, causing the transistor M1b of the calculation cell MCb to turn ON. In particular, a current corresponding to the value Xo(TP) held at node SN2 of circuit SHE flows through the calculation cell MCb, and the potential at node Nb of the calculation cell MCb is set to a potential corresponding to the value Xo(TP). Subsequently, at time T34, a low-level potential is applied to the wiring SLbf, causing the transistor M1b of the calculation cell MCb to turn OFF, and a potential corresponding to the value Xo(TP) is held at node Nb of the calculation cell MCb. 【0462】 At time T34m, a low-level potential is applied to wiring PCK3p, and a high-level potential is applied to wiring PCK3n. As a result, switch AS6 is turned off, and there is no conduction between the input / output terminals of circuit SHE and the calculation cell MCb. This stops the through-current flowing between wiring VD3 and wiring VLE, ​​thereby reducing power consumption. 【0463】 At time T35, a high-level potential is applied to wiring PCK3p and a low-level potential is applied to wiring PCK3n, causing switch AS6 to turn ON. Also, a high-level potential is applied to wiring PCKp and a low-level potential is applied to wiring PCKn, causing switch AS5 to turn ON. As a result, conduction occurs between the input / output terminals of circuit SHE and calculation cell MCb, and also between the input / output terminals of circuit SHE and calculation cell MCf. 【0464】 For the operation between time T35 and time T36m, please refer to the explanation of the timing chart in Figure 24. In particular, between time T36 and time T36m, the potential of node SN2 of circuit SHE changes to a potential corresponding to the value Xo(T33) = ζXo(TP) + δΔXo(T33). 【0465】At time T36m, similar to time T34m, a low potential is applied to wiring PCK3p and a high potential is applied to wiring PCK3n. As a result, switch AS6 is turned off, and there is no conduction between the input / output terminals of circuit SHE and the calculation cell MCb. 【0466】 At time T37, a high-level potential is applied to wiring PCKp and a low-level potential is applied to wiring PCKn, causing switch AS7 to turn ON. As a result, circuit SHE outputs a current corresponding to the value Xo (T33) from its output terminal to wiring OL (node ​​A3To). 【0467】 By applying the circuit ITSe in Figure 28 to the drive circuit ITSr[j] in Figure 17, and performing the above example of operation, the arithmetic unit CDV in Figure 1 can perform ESN calculations using the Leaky Integrator model. This allows for weighted averaging of signals output from the neurons in the reservoir layer and past internal states, and enables the arithmetic unit CDV to output calculation results that include the influence of the past internal information. This improves the accuracy of ESN calculations. 【0468】 This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments. 【0469】 (Embodiment 2) A semiconductor device according to one aspect of the present invention will be described. 【0470】 First, let's explain reservoir computing. Known algorithms used in reservoir computing (also called RC), known as "RC models," include LSM (Liquid State Machine), ESN, and FORCE (First Order Reduced and Controlled Error). 【0471】 Figure 31 shows an example configuration of an ESN as the RC model 10. The RC model 10 consists of an input layer 11, a reservoir layer 12, and an output layer 13. The reservoir layer 12 is also called a hidden layer. 【0472】 The input layer 11 comprises nodes 21 (also called neurons). The data u(t) represents the value of node 21 at time t. Although Figure 31 shows one node 21, the input layer 11 may comprise multiple nodes 21. For example, the input layer 11 may comprise M nodes 21 (where M is an integer greater than or equal to 1). 【0473】 The reservoir layer 12 comprises multiple nodes 22. Data x(t) represents the value of node 22 at time t. Although Figure 31 shows six nodes 22, the number of nodes 22 is not limited to these. For example, the reservoir layer 12 may comprise N nodes 22 (where N is an integer greater than or equal to 2). 【0474】 The output layer 13 includes a node 23. The data y(t) represents the value of node 23 at time t. Although Figure 31 shows one node 23, the output layer 13 may have multiple nodes 23. For example, the output layer 13 may have K nodes 23 (where K is an integer greater than or equal to 1). 【0475】 Furthermore, in Figure 31, the weight of the connection between node 21 and node 22 is shown as the "weight coefficient Wi". Also, the weight of the connection between node 22 and node 23 is shown as the "weight coefficient Wo". In addition, the N nodes 22 in the reservoir layer 12 are randomly connected to each other. In Figure 31, the weight of the connections between nodes 22 is shown as the "weight coefficient Wr". 【0476】 Node 21 is connected to multiple nodes 22. In this case, in the RC model 10 shown in Figure 31, each weight coefficient Wi is determined to be an irregular positive or negative value or 0 and fixed. Also, the value obtained by multiplying the data u(t) and the weight coefficient Wi is supplied to node 22. 【0477】Furthermore, in the reservoir layer 12, the weight coefficient Wr for the connections between nodes 22 is determined to be an irregular positive or negative value or 0, and is fixed. Therefore, the data supplied from the reservoir layer 12 to the output layer 13 becomes nonlinear data. In the connections between nodes 22, the value obtained by multiplying the data x(t) of the data-supplying node 22 by the weight coefficient Wr is supplied to the node 22 receiving the data. 【0478】 In a recurrent neural network (RNN), the weight coefficients Wi, Wr, and Wo are determined using backpropagation, requiring a large amount of training data and a significant amount of training time. Therefore, RNNs are computationally expensive. On the other hand, in an RC model, the weight coefficients Wi and Wr are fixed, and only the weight coefficient Wo is trained (optimized). Therefore, the optimization of the weight coefficient Wo can be completed with less training data and less training time. Consequently, RC models consume less power during training and are more computationally expensive than RNNs. 【0479】 The RC model 10 shown in Figure 31 can be expressed by equations (2.1) to (2.3). Equation (2.1) is a mathematical formula relating to the data x(t) represented by the Leaky Integrator model. Equation (2.2) is a mathematical formula for calculating the weight coefficient Wo. Equation (2.3) is a mathematical formula for calculating the data y(t). 【0480】 【0481】 【0482】 【0483】 f represents the activation function. δ represents the leakage rate. T represents the transpose matrix. I represents the identity matrix. Y ｔａｒｇｅｔ This indicates the training data. 【0484】For example, when analyzing time-series changes in images captured by an image sensor, such as detecting eye blinks, RNNs are computationally expensive and difficult to implement in hardware due to their complex layer structure. By incorporating at least a part of the RC algorithm into an image sensor or processor, computational processing can be performed with low power consumption. 【0485】 This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments. 【0486】 (Embodiment 3) In this embodiment, an example of a schematic plan view of the semiconductor device described in the above embodiment and an example of a cross-sectional configuration will be described. 【0487】 <Example of semiconductor device layout> Figure 32A is a schematic plan view showing an example of the circuit configuration of the arithmetic cell MCp shown in Figure 5A, which is included in the arithmetic device CDV, which is a semiconductor device described in the above embodiment. 【0488】 Although the schematic diagram in question describes the calculation cell MCp, the calculation cell MCn and the drive cell DC, which have similar circuit configurations, can sometimes be described in the same way. In that case, the transistors M1p, M3p, M4p, and capacitive element C1p used in the description can be replaced with transistors M1n, M3n, M4n, and capacitive element C1n as appropriate, or with transistors M1d, M3d, M4d, and capacitive element C1d as appropriate. 【0489】 The schematic plan view of Figure 32A shows an example of a circuit layer including the arithmetic cell MCp, which includes a conductive layer 232, a conductive layer 233, a conductive layer 234, a conductive layer 235, and a semiconductor layer 251. Note that, in order to clearly show the schematic plan view, the insulating layer included in the circuit layer is not shown in Figure 32A. 【0490】 Each of the transistors M1p, M3p, and M4p shown in Figure 32A has an island-shaped insulating layer, a semiconductor layer 251 formed on the insulating layer, a conductive layer 232 formed on the semiconductor layer 251, a gate insulating film formed on the semiconductor layer 251, and a conductive layer 233 formed on the gate insulating film. These transistors can also have a GL (Gate Last) structure (also known as a TGSA (Trench Gate Self Align or Top Gate Self Align) structure), which will be described later. 【0491】 For example, the semiconductor layer 251 is located below the conductive layers 232 and 233, and the conductive layer 234 is located above the conductive layers 232 and 233. The conductive layer 235 is located above the conductive layer 234. The formation order can be the semiconductor layer 251 first, the conductive layer 232 second, the conductive layer 233 third, the conductive layer 234 fourth, and the conductive layer 235 fifth. 【0492】 In the schematic plan view of Figure 32A, a portion of the conductive layer 232 functions, for example, as the source or drain of transistors M1p, M3p, and M4p, respectively. A portion of the conductive layer 233 functions, for example, as the gate of these transistors. Furthermore, the conductive layer 234 functions, for example, as wiring to connect either conductive layer 232 or conductive layer 233 with conductive layer 235. For this reason, conductive layer 234 is sometimes referred to as a contact plug. 【0493】 Furthermore, in the schematic plan view of Figure 32A, a portion of the conductive layer 233 functions, for example, as one of the pair of electrodes of the capacitive element C1p. Also, a portion of the conductive layer 235 functions, for example, as the other of the pair of electrodes of the capacitive element C1p. 【0494】Furthermore, in the schematic plan view of Figure 32A, each of the conductive layer 233 and conductive layer 235 has a portion that functions as wiring. For example, a portion of the conductive layer 233 is provided as wiring XL and wiring SL, extending in the left-right direction of the drawing. Also, for example, a portion of the conductive layer 235 is provided as wiring VLE, ​​wiring WLp, and wiring VBE, extending in the up-down direction of the drawing. For this reason, it is preferable to use a material with high conductivity for each of the conductive layer 233 and conductive layer 235. 【0495】 Furthermore, each of the conductive layers described above can be formed, for example, using lithography. Specifically, for example, when forming the conductive layer 232, the conductive material that will become the conductive layer 232 can be formed using one or more methods selected from sputtering, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition), and then the desired pattern can be formed by lithography. In addition, conductive layers other than the conductive layer 232, semiconductor layers, and insulating layers can also be formed by the same methods as described above. 【0496】 In this specification, lithography includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting. 【0497】 Furthermore, an insulating layer can be provided between the conductive layer 233 and the conductive layer 235. In particular, in the region where the capacitive element C1p is provided, it is preferable that the insulating layer formed to overlap the conductive layer 233 and the conductive layer 235 is an insulating layer that functions as a dielectric in the capacitive element C1p. 【0498】 As shown in Figure 32A, the capacitive element C1p has a parallel plate structure. Furthermore, the capacitive element C1p can be installed in the region where the wiring XL extends. This makes it easy to secure the area for the capacitive element C1p, thereby reducing the circuit area of ​​the calculation cell MCp. 【0499】 Furthermore, in Figure 32A, the width d1 of the conductive layer 235 covering the other region of the pair of electrodes of the capacitive element C1p is shorter than the width d2 of the conductive layer 233 covering one region of the pair of electrodes of the capacitive element C1p. When an insulating layer having dielectric function is formed on the conductive layer 233, defects in the formation of the insulating layer may occur at the edge or surrounding region of the conductive layer 233. Specifically, the film-forming properties of the insulating layer formed at the edge or surrounding region of the conductive layer 233 may be low. In this case, if the width d1 is longer than the width d2, the edge or surrounding region of the conductive layer 233 and the overlapping region of the conductive layer 235 may come into contact with each other and short-circuit. For this reason, it is preferable that the width d1 is shorter than the width d2. 【0500】 Conversely, if the coating properties of the insulating layer formed on the edge or surrounding region of the conductive layer 233 can be increased, it is preferable to make the width d1 longer than the width d2. Specifically, since the capacitance value of a capacitive element is proportional to the area of ​​the region where one electrode of the pair and the dielectric overlap with the other electrode of the pair, it is preferable to increase the area of ​​this region if the capacitance value is to be increased. Therefore, by making the width d1 longer than the width d2, the width of this region can be increased from d1 to d2. As a result, the conductive layer 235 is formed above the edge of the conductive layer 233, so the area of ​​the other electrode of the pair of electrodes of the capacitive element C1p increases, and the capacitance value of the capacitive element C1p can be increased. 【0501】 Furthermore, in Figure 7, since transistors M3p and M4p are connected in series, as shown in the schematic plan view of the arithmetic cell MCp in Figure 32A, transistors M3p and M4p can be formed to share island-shaped semiconductor layers 251 with each other. This reduces the formation area of ​​the arithmetic cell MCp, and as a result, the cell density of the arithmetic cell MCp can be increased, and the circuit area of ​​the arithmetic unit CDV can be reduced. 【0502】Furthermore, as shown in Figure 32B, by arranging transistors M1p and M4p so that they are aligned in the vertical direction of the drawing, it becomes easy to provide wiring that functions as a back gate electrode for each of transistors M1p and M4p. For example, as shown in Figure 32B, a conductive layer 231 can be extended below the semiconductor layer 251 containing the channel formation regions of transistors M1p and M4p, as wiring BGL. The conductive layer 231 can also be provided below the semiconductor layer 251 containing the channel formation region of transistor M3p. This makes it easier to route the wiring BGL, shortens the wiring distance, reduces parasitic resistance, and lowers power consumption. 【0503】 Note that the schematic plan view of a semiconductor device according to one embodiment of the present invention is not limited to Figures 32A and 32B. The schematic plan view of an arithmetic circuit according to one embodiment of the present invention can be modified as appropriate depending on the circumstances, as shown in Figures 32A and 32B. 【0504】 Furthermore, in the schematic planar diagrams of Figures 32A and 32B, the sizes (including channel length and channel width) of transistors M1p, M3p, and M4p are shown to be equal to each other, but the sizes of transistors M1p, M3p, and M4p may be different from each other. 【0505】For example, it is preferable that the channel width of a switching transistor be shorter than the channel width of an amplifying transistor. Specifically, in Figures 32A and 32B, it is preferable that the channel width d3 of transistor M1p be shorter than the channel width d5 ​​of transistor M3p. By shortening the channel width d3 of transistor M1p, which functions as a switching transistor, the off-current of transistor M1p can be reduced, thereby allowing the gate potential of transistor M3p to be maintained for a longer period of time. Also, for example, it is preferable that the channel length of a switching transistor be longer than the channel length of an amplifying transistor. Specifically, in Figures 32A and 32B, it is preferable that the channel length d4 of transistor M1p be longer than the channel length d6 of transistor M3p. By lengthening the channel length d4 of transistor M1, which functions as a switching transistor, the off-current of transistor M1p can also be reduced. 【0506】 Furthermore, for example, it is preferable that the channel width of an amplifying transistor be longer than the channel width of a switching transistor. Specifically, it is preferable that the channel width d5 ​​of transistor M3p be shorter than the channel width d3 of transistor M1p. By shortening the channel width d5 ​​of transistor M3p, which functions as an amplifying transistor, the on-current of transistor M3p can be increased. Furthermore, for example, it is preferable that the channel length of an amplifying transistor be shorter than the channel length of a switching transistor. Specifically, it is preferable that the channel length d6 of transistor M3p be shorter than the channel length d4 of transistor M1p. By shortening the channel length d6 of transistor M3p, which functions as an amplifying transistor, the on-current of transistor M3p can also be increased. 【0507】Furthermore, since transistor M4p functions as a clamp transistor, it is preferable that the channel length d10 of transistor M4p be longer than the channel length d6 of transistor M3p. By making the channel length d10 of transistor M4p longer than the channel length d6 of transistor M3p, DIBL of transistor M3p can be prevented. In addition, even if the channel length d10 of transistor M4p is less than or equal to the channel length d6 of transistor M3p, DIBL of transistor M3p may still be prevented. Furthermore, in order to prevent a decrease in the current flowing between the source and drain of transistor M3p, it is preferable that the channel width d9 of transistor M4p be longer than the channel width d5 ​​of transistor M3p. In addition, even if the channel width d9 of transistor M4p is less than or equal to the channel length d5 ​​of transistor M3p, a decrease in the current flowing between the source and drain of transistor M3p may still be prevented. 【0508】 <Example of Cross-Sectional Device Configuration> Figure 33 is a schematic cross-sectional view showing an example of the configuration of the computing device CDV described in the above embodiment. In Figure 33, the computing device CDV includes, as an example, a circuit layer PHRL and a circuit layer OMAL located above the circuit layer PHRL. 【0509】 Note that in Figure 33, transistor M1p is located above transistors M3p and M4p. Therefore, the cross-sectional schematic diagram in Figure 33 has a different configuration from the plan schematic diagrams shown in Figures 32A and 32B. 【0510】 Furthermore, the following cross-sectional configuration example describes an example where the circuit layer OMAL includes the arithmetic cell MCp. Note that the following cross-sectional configuration example can also be applied to the arithmetic cell MCn and the drive cell DC, which have a circuit configuration similar to that of the arithmetic cell MCp. 【0511】The circuit layer PHRL can be constructed, for example, by providing circuit elements such as transistors and capacitive elements on a substrate. A semiconductor substrate (for example, a single-crystal substrate made of silicon or germanium) can be used as the substrate. Other substrates that can be used include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base films. In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate containing silicon. 【0512】 By using a silicon semiconductor substrate as the substrate included in the circuit layer PHRL, the transistors included in each of the drive circuits WCD, XCD, WSD, ITS, and ITS shown in Figure 1 can be formed on the semiconductor substrate. In this case, the transistors are Si transistors. Since Si transistors have high field-effect mobility, they can carry large on-currents. This makes it possible to increase the driving speed of each of the drive circuits listed above, widen the signal range, and so on. 【0513】 In Figure 33, transistor 100, which is part of the circuit layer PHRL, is shown as an example of a Si transistor. By using a Si transistor for transistor 100, a CMOS circuit can be configured in the circuit layer PHRL that includes both a p-channel transistor and an n-channel transistor. In particular, since the drive circuit described in the above embodiment includes both p-channel and n-channel transistors, it is preferable that the drive circuit be formed in the circuit layer PHRL as a CMOS circuit. 【0514】Furthermore, the laminated structure of circuit layer PHRL and circuit layer OMAL can be fabricated by directly forming circuit layer OMAL on top of circuit layer PHRL. Alternatively, circuit layer OMAL can be fabricated by mounting the substrate on top of circuit layer PHRL, with circuit elements such as transistors and capacitive elements provided on the substrate. When circuit layer OMAL is directly formed on top of circuit layer PHRL, it is preferable that circuit layer OMAL includes an OS transistor. An I / O transistor can be used as the OS transistor. Since the OS transistor can be formed on a substrate such as a semiconductor substrate, an insulating substrate, or a conductive substrate, or on a film such as a conductive film, an insulating film, or a semiconductor film, it can be easily provided on a semiconductor substrate (on circuit layer PHRL) on which a Si transistor is formed. 【0515】 Alternatively, p-channel transistors may be provided as Si transistors in the PHRL circuit layer, and n-channel transistors may be provided as OS transistors in the OMAL circuit layer. Specifically, for example, transistors M1p, M3p, and M4p shown in Figure 5A can be provided in the OMAL circuit layer. 【0516】 Furthermore, when forming circuit elements such as transistors and capacitive elements on a substrate as the circuit layer OMAL, and mounting the substrate on the circuit layer PHRL, a flip-chip bonding method or a wire bonding method can be used. Alternatively, the circuit layer OMAL may be mounted on the circuit layer PHRL by providing a first bonding layer on the circuit layer PHRL side, providing a second bonding layer on the circuit layer OMAL substrate, and bonding the first bonding layer and the second bonding layer using either or both of the surface activation bonding method and the hydrophilic bonding method. In particular, a bonding method in which copper (Cu) is used as the conductor in both the first and second bonding layers, and the copper is bonded to each other, is called Cu-Cu (copper-copper) direct bonding. 【0517】The transistor 100 is provided on a substrate 101 and includes a conductive layer 131 that functions as a gate, an insulating layer 161 and an insulating layer 111 that functions as a gate insulating film, a semiconductor region 171 that includes a part of the substrate 101, and a low-resistance region 172a and a low-resistance region 172b that include a part of the substrate and function as a source region or drain region. 【0518】 Furthermore, the semiconductor region 171, the low-resistance region 172a, and the low-resistance region 172b shown in Figure 33 are each formed by providing an element isolation layer 102 on the substrate 101. It can also be said that the element isolation layer 102 is provided to separate the multiple transistors formed on the substrate 101. The element isolation layer 102 can be formed, for example, using the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method. 【0519】 Furthermore, the transistor 100 shown in Figure 33 may, as an example, have a convex shape in the semiconductor region 171 (part of the substrate 101) where the channel is formed, as shown in the schematic cross-sectional view of Figure 34. Figure 34 is a schematic cross-sectional view of the transistor 100 in the channel width direction. The side and top surfaces of the semiconductor region 171 are covered by a conductive layer 131 via an insulating layer 161. The conductive layer 131 may be made of a material that adjusts the work function. Such a transistor 100 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulating layer that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. In addition, although the case of forming the convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate. 【0520】 Furthermore, in Figure 34, a conductive layer 136 is provided so as to be in contact with the conductive layer 131 and to fill the opening formed in the insulating layer 112. The conductive layer 136 functions as a contact plug or wiring. 【0521】Note that the transistor 100 shown in Figures 33 and 34 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method. 【0522】 The computing unit CDV may be provided with a wiring layer having an interlayer film, wiring, and a plug. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plug connected to the wiring may be a single integrated unit. That is, there may be cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug. 【0523】 For example, on the transistor 100, insulating layers 112, 181, and 113 are sequentially stacked as interlayer films. A conductive layer 132 is embedded in the insulating layer 112. A conductive layer 133 is embedded in the insulating layer 181 and the insulating layer 113. The conductive layers 132 and 133 function as contact plugs or wiring. 【0524】 Furthermore, the insulating layer, which functions as an interlayer film, may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 112 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) to improve its flatness. 【0525】 Wiring layers may be provided on the insulating layer 113 and the conductive layer 133. For example, in Figure 33, insulating layers 182, 114, 115, and 116 are sequentially laminated on the insulating layer 113 and the conductive layer 133. Furthermore, conductive layers 134 are formed on insulating layers 182, 114, and 115. The conductive layer 134 functions as a contact plug or wiring. 【0526】 An insulating layer 281 is provided on the insulating layer 116. Preferably, contact plugs or wiring for connecting to an upper circuit (for example, a circuit element included in a circuit included in the circuit layer OMAL) are embedded in the insulating layer 116 and the insulating layer 281. 【0527】Next, we will describe an example of the configuration of the arithmetic cells included in the circuit layer OMAL shown in Figure 33. 【0528】 In the circuit layer OMAL of Figure 33, transistors M3p and M4p are formed on the insulating layer 281. Transistor M1p is formed on the insulating layer 284. Capacitive element C1p is formed on the insulating layer 287. The insulating layer 287 is located above the insulating layer 284, and the insulating layer 284 is located above the insulating layer 281. Therefore, it can be said that the capacitive element C1p is located above transistor M1p, and transistor M1p is located above transistors M3p and M4p. 【0529】 Furthermore, it is preferable that each of the insulating layers 181, 182, 281 to 287 shown in Figure 33 functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, insulating layers 181, 182, 281 to 287 contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ２ O, NO, or NO ２ It is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as ) and copper atoms (i.e., the above impurities do not easily permeate). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (for example, oxygen atoms and oxygen molecules, or both) (i.e., the above oxygen does not easily permeate). For materials that can be applied to insulating layer 181, insulating layer 182, insulating layer 281 to insulating layer 287, refer to the description of the insulating layer of the transistor constituent materials. 【0530】Furthermore, a conductive layer that forms the wiring VLE is connected to either the source or drain of transistor M3p via a conductive layer 234_1 which functions as a contact plug. The other source or drain of transistor M3p is formed to be shared with either the source or drain of transistor M4p. Furthermore, either the source or drain of transistor M1p is connected to the other source or drain of transistor M4p via conductive layers 234_2, 235_2, and 235_4 which function as contact plugs. In Figure 33, as an example, a conductive layer that forms the wiring WLp is provided between conductive layer 234_2 and conductive layer 235_2. 【0531】 Furthermore, the gate electrode of transistor M1p extends, for example, as a conductive layer that forms the wiring SL, along the direction from front to back in Figure 33. 【0532】 Furthermore, the gate electrode of transistor M3 is connected to the other source or drain electrode of transistor M1 via conductive layers 234_3, 235_1, and 235_2, which function as contact plugs. In Figure 33, as an example, a conductive layer is provided between conductive layer 234_1 and conductive layer 235_3, which is one of the pair of electrodes of the capacitive element C1p. 【0533】 A conductive layer that functions as one of the pair of electrodes of the capacitive element C1p is formed to be embedded in an insulating layer 219 on an insulating layer 287. Above the conductive layer that is one of the pair of electrodes of the capacitive element C1p, an insulating layer 441 that functions as the dielectric of the capacitive element C1p is provided. Above the insulating layer 441, a conductive layer that forms the wiring XL is provided. The region of the conductive layer that forms the wiring XL that overlaps with the conductive layer that is one of the pair of electrodes of the capacitive element C1p functions as the other of the pair of electrodes of the capacitive element C1p. 【0534】By embedding the conductive layer, which functions as one of the pair of electrodes of the capacitive element C1p, into the insulating layer 219, the conductive layer and the insulating layer 219 can be made flush and planar. As a result, the insulating layer, which functions as a dielectric, and the conductive layer, which functions as the other of the pair of electrodes of the capacitive element C1p, can be formed with good flatness on the upper surfaces of the conductive layer and the insulating layer 219, which have good flatness. By improving the flatness of both of the pair of electrodes of the capacitive element C1p and the insulating layer, which functions as a dielectric, localized electric field concentration can be suppressed, and as a result, leakage current between the pair of electrodes of the capacitive element C1p can be prevented. Furthermore, one of the pair of electrodes of the capacitive element C1p (here, the lower electrode) is provided in a smaller area than the other of the pair of electrodes of the capacitive element C1p (here, the upper electrode). This configuration makes it possible to suppress localized electric field concentration that can be applied to the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitive element C1p, thereby enabling the realization of a highly reliable semiconductor device. 【0535】 For example, in the calculation cell MCp shown in Figure 5A, by configuring the capacitive element C1p as described above, leakage current between the pair of electrodes of the capacitive element C1p that occurs between the gate of transistor M3p and the wiring XL can be prevented. Therefore, in the calculation cell MCp, fluctuations in the gate potential of transistor M3p due to this leakage current can be prevented, and the potential can be maintained for a long period of time. In addition, localized electric field concentration can be suppressed with respect to the dielectric of the capacitive element C1p, thereby increasing the reliability of the calculation cell MCp. 【0536】 Furthermore, in the configuration example shown in Figure 33, the conductive layer functioning as wiring XL and the conductive layer functioning as wiring SL each extend along the direction from the front to the back of Figure 33. 【0537】As shown in Figure 33, a conductive layer functioning as a back gate may be provided below the island-shaped semiconductor layer of each transistor M1p, M3p, and M4p. By providing a back gate for each transistor and changing the potential of the back gate, the threshold voltage of that transistor can be changed. For example, by providing a back gate for each of transistors M1p, M3p, and M4, the influence of the external electric field is reduced, and the off state can be stably maintained. Therefore, the data written to the capacitive element C1p can be stably held. In this way, by providing a back gate, the operation of the arithmetic cell MCp is stabilized, and the reliability of the circuit layer OMAL including the arithmetic cell MCp can be improved. 【0538】 Furthermore, when a back gate is provided in a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid the formation of parasitic capacitance with the back gate. 【0539】 It is preferable that each of the transistors M1p, M3p, and M4p is an OS transistor in which an oxide semiconductor, a type of metal oxide, is used in the semiconductor layer where the channel is formed. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the arithmetic cell can be reduced. Therefore, the power consumption of the arithmetic unit CDV, which includes the arithmetic cell MCp, can be reduced. 【0540】 Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even in environments between room temperature (e.g., 25°C) and 200°C. Also, the on-current does not easily decrease even in high-temperature environments. In addition, the arithmetic cell shown in Figure 33 can hold the first data, thus also functioning as a memory device. For this reason, the arithmetic cell operates stably even in high-temperature environments, resulting in high reliability. 【0541】In particular, by using indium oxide for the oxide semiconductor mentioned above, that is, by making transistors M1p, M3p, and M4p I / O transistors, it is possible to create transistors with low off-current and high on-current. This can sometimes lead to the realization of a computing device that combines high reliability with high operating speed. 【0542】 <<Transistor Configuration Example 1>> Next, we will explain a specific configuration example of a transistor called a GL structure that can be applied to transistors M1p, M3p, and M4p shown in Figure 33. Transistor 200 shown in Figures 35A and 35B is an example of a GL structure transistor. 【0543】 In particular, Figure 35A shows a schematic cross-sectional view of transistor 200 in the channel length direction, and Figure 35B shows a schematic cross-sectional view of transistor 200 in the channel width direction. 【0544】 As shown in Figures 35A and 35B, the transistor 200 includes, for example, a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231, a conductive layer 232a, a conductive layer 232b, a conductive layer 233, insulating layers 261 to 264, insulating layers 281 to 283, and insulating layers 212 to 214. However, the transistor 200 may not have all of the above-mentioned components. For example, although the conductive layer 231 functions as a back gate electrode in the transistor 200, the transistor 200 can also be configured without the conductive layer 231. 【0545】The conductive layer 231 (conductive layer 231a and conductive layer 231b) and the insulating layer 212 are arranged on top of the substrate (not shown). In particular, it is preferable that the conductive layer 231 is embedded in the insulating layer 212. Specifically, it is preferable that the conductive layer 231a is provided in contact with the bottom surface and side wall of an opening provided in the insulating layer 212. It is also preferable that the conductive layer 231b is provided so as to be embedded in a recess formed in the conductive layer 231a. In the transistor 200 shown in Figures 35A and 35B, the height of the upper surface of the conductive layer 231b is approximately the same as the height of the upper surface of the conductive layer 231a and the height of the upper surface of the insulating layer 212. 【0546】 The insulating layer 212, for example, functions as a planarizing film that flattens steps caused by plugs and the like, similar to the insulating layer 112. Therefore, the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112. 【0547】 Furthermore, by using a material with a low dielectric constant for the insulating layer 212, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide nitride, or silicon nitride can be used for the insulating layer 212. Alternatively, for example, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or porous silicon oxide can be used for the insulating layer 212. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating. Alternatively, for example, resin can be used for the insulating layer 212. The material used for the insulating layer 212 may also be an appropriate combination of the insulating materials described above. 【0548】In this specification, "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content. 【0549】 Furthermore, the semiconductor layer 251 and the conductive layer 233 are arranged in a region that overlaps with the conductive layer 231. The semiconductor layer 251b is arranged on top of the semiconductor layer 251a. The conductive layers 232a and 232b are arranged on top of the semiconductor layer 251b, spaced apart from each other. The insulating layer 213 is arranged on top of the conductive layers 232a and 232b. In particular, the insulating layer 213 has an opening formed in the region between the conductive layers 232a and 232b. The conductive layer 233 is arranged within this opening. The insulating layer 264 is arranged between the semiconductor layer 251b, the conductive layer 232a, the conductive layer 232b, the insulating layer 213, and the conductive layer 233. Here, as shown in Figures 35A and 35B, it is preferable that the upper surface of the conductive layer 233 substantially coincides with the upper surface of the insulating layer 264 and the insulating layer 213. In the following, conductive layers 231a and 231b may be collectively referred to as conductive layer 231. Also, semiconductor layers 251a and 251b may be collectively referred to as semiconductor layer 251. Furthermore, conductive layers 232a and 232b may be collectively referred to as conductive layer 232. 【0550】 Furthermore, as shown in Figure 35A, a low-resistance region 271a may be formed at and near the interface of the semiconductor layer 251b with the conductive layer 232a. Similarly, a low-resistance region 271b may be formed at and near the interface of the semiconductor layer 251b with the conductive layer 232b. In this case, region 271a functions as either a source region or a drain region, and region 271b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between region 271a and region 271b. 【0551】For the semiconductor layer 251, it is preferable to use a metal oxide that functions as an oxide semiconductor and includes a channel formation region. In particular, indium oxide, as described in Embodiment 4, is preferred as the metal oxide. In addition to indium oxide, various other metal oxides that form the channel formation region of the transistor 200 will also be described below. 【0552】 As the metal oxide that forms the channel formation region of the transistor 200, it is preferable to use one with a band gap of 2 eV or more, preferably 2.5 eV or more. Specifically, for example, in the case of the transistor 200 shown in Figures 35A and 35B, it is preferable to use a metal oxide that functions as an oxide semiconductor for the semiconductor layer 251. 【0553】 Metal oxide structures can be classified into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include CAAC (c-axis aligned crystalline) structures, polycrystalline structures, nanocrystalline structures, a-like (amorphous-like) structures, and amorphous structures. The structure of the metal oxide in one aspect of the present invention is not particularly limited, and any of the above structures may be used. However, using crystalline metal oxides such as CAAC structures and nc structures is preferable because it allows for the creation of highly reliable semiconductor devices. 【0554】Furthermore, it is preferable that the above metal oxide contains at least indium. It may also contain indium and zinc. In addition to these, it may also contain element M. Element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, element M can be one or more selected from aluminum, gallium, yttrium, or tin. It is even more preferable that element M contains either or both gallium and tin. 【0555】 As the above metal oxides, indium oxide (also called indium oxide), gallium oxide, zinc oxide, indium zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, etc. can be used. Alternatively, indium tin oxide, gallium tin oxide, aluminum tin oxide, etc. containing silicon can be used. 【0556】 As described above, the metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as the metal oxide. Crystalline indium oxide is particularly preferable. 【0557】Metal oxides can be suitably formed using sputtering or ALD (Advanced Laser Deposition). When metal oxides are formed by sputtering, films with high crystallinity or high film density can be formed. When metal oxides are formed using ALD, atoms can be deposited layer by layer, resulting in film formation with fewer defects such as pinholes, excellent coverage, and the ability to form films at low temperatures. Furthermore, it is preferable to perform an impurity removal treatment after the formation of the metal oxide to remove impurities (typically water, hydrogen, carbon, nitrogen, etc.) from the metal oxide film. Examples of impurity removal treatments include plasma treatment and heat treatment. Microwave plasma treatment is an example of plasma treatment. 【0558】 In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing. 【0559】 In the transistor 200, a configuration is shown in which two semiconductor layers, semiconductor layer 251a and semiconductor layer 251b, are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity. However, the present invention is not limited to this. For example, a single-layer structure of semiconductor layer 251b or a stacked structure of three or more layers may be provided. Furthermore, each of semiconductor layer 251a and semiconductor layer 251b may have a stacked structure of two or more layers. 【0560】The conductive layer 233 functions as the first gate electrode of the transistor (sometimes referred to as the top gate electrode or front gate electrode), and as described above, the conductive layers 232a and 232b function as the source electrode or drain electrode, respectively. As described above, the conductive layer 233 is formed to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layers 232a and 232b. Here, the arrangement of the conductive layer 233, conductive layer 232a, and conductive layer 232b is formed in a self-aligned manner with respect to the opening of the insulating layer 213. In other words, in the transistor 200, the first gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductive layer 233 can be formed without providing a positional margin, the occupied area of ​​the transistor 200 can be reduced. This makes it possible to increase the density of arithmetic cells in the arithmetic unit. 【0561】 The transistor 200 can be formed by first forming an island-shaped laminate on an insulating layer 262 (described later), including an insulating layer 263 (described later), a semiconductor layer 251, and conductive layers that will become conductive layers 232a and 232b; then, stacking insulating layers 282 and 213 (collectively referred to here as the interlayer film) above the island-shaped laminate and above the insulating layer 262 in that order; and then, forming an opening in the region of the interlayer film that overlaps the island-shaped laminate, and providing an insulating layer 264 and a conductive layer 233 in that order in the opening. In particular, it is preferable to form the conductive layers 232a and 232b simultaneously by forming an opening in the interlayer film. In this specification, a transistor structure in which, after the formation of the island-shaped laminate and the interlayer film, an opening reaching the island-shaped laminate is provided in the interlayer film, and a conductive layer that will become the first gate electrode of the transistor is provided to fill the opening, is referred to as the GL structure. This type of structure is sometimes also called a TGSA structure. 【0562】In Figures 35A and 35B, the conductive layer 233 is shown as a two-layer structure. Here, it is preferable that the conductive layer 233 has a conductive layer 233a and a conductive layer 233b disposed on top of the conductive layer 233a. For example, it is preferable that the conductive layer 233a is arranged to enclose the bottom and sides of the conductive layer 233b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 233a. 【0563】 It is preferable to use a conductive material for the conductive layer 233a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen. Furthermore, by having the function of suppressing the diffusion of oxygen in the conductive layer 233a, it is possible to suppress the oxidation of the conductive layer 233b by oxygen contained in the insulating layer 213, etc., which reduces the conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. 【0564】 Furthermore, it is preferable to use a conductive layer with high conductivity for the conductive layer 233b. For example, the conductive layer 233b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 233b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material. 【0565】For conductive layers 232a and 232b, it is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductive layers 232a and 232b. When conductive materials containing metal and nitrogen are used as conductive layers 232a and 232b, conductive layers 232a and 232b become conductive layers having at least a metal and nitrogen. For example, as materials to be applied to conductive layers 232a and 232b, conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen can be selected from the materials that can be applied to conductive layers 233a and 233b respectively as described above. 【0566】 Conductive layers 235a and 235b can be made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, conductive layers 235a and 235b can have a laminated structure having multiple layers. In particular, it is preferable that the laminated structure consists of a conductive material having the function of suppressing the permeation of impurities such as water and hydrogen, and a highly conductive material, laminated together. 【0567】 Furthermore, the conductive layer 231 may function as a second gate electrode (sometimes referred to as a bottom gate electrode or back gate electrode). In this case, by independently changing the potential applied to the conductive layer 231, separate from the potential applied to the conductive layer 233, the threshold voltage V of the transistor 200 can be controlled. ｔｈ This can be controlled. In particular, by applying a negative potential to the conductive layer 231, the V of the transistor 200 can be controlled. ｔｈ This makes it possible to increase the voltage and decrease the off-current. Therefore, applying a negative potential to the conductive layer 231 reduces the drain current when the potential applied to the conductive layer 233 is 0V compared to when no potential is applied. 【0568】The conductive layer 231 should be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Figure 35B, it is preferable that the conductive layer 231 extends as wiring even in the region outside the edge that intersects with the channel width direction of the semiconductor layer 251. That is, it is preferable that the conductive layer 231 and the conductive layer 233 are superimposed on the outside of the side surface in the channel width direction of the semiconductor layer 251, with an insulating layer in between. 【0569】 As shown in Figure 35A, the conductive layer 233 preferably has a conductive layer 233a provided inside the insulating layer 264 and a conductive layer 233b provided so as to be embedded inside the conductive layer 233a. Although Figures 35A and 35B show the conductive layer 233 as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductive layer 233 may be a single-layer structure or a laminated structure of three or more layers. 【0570】 For the conductive layer 231 and conductive layer 233, for example, materials applicable to conductive layer 233a and conductive layer 233b described above can be selected and used. 【0571】 As shown in Figures 35A and 35B, the transistor 200 preferably includes an insulating layer 211 placed on a substrate (not shown), an insulating layer 281 placed on the insulating layer 211, an insulating layer 212 placed on the insulating layer 281, a conductive layer 231 placed so as to be embedded in the insulating layer 212, an insulating layer 261 placed on the insulating layer 212 and the conductive layer 231, an insulating layer 262 placed on the insulating layer 261, and an insulating layer 263 placed on the insulating layer 262. It is preferable that a semiconductor layer 251a is placed on the insulating layer 263. 【0572】Furthermore, as shown in Figures 35A and 35B, it is preferable that an insulating layer 282 is placed between the insulating layer 262, insulating layer 263, semiconductor layer 251a, semiconductor layer 251b, conductive layer 232a, conductive layer 232b, and insulating layer 213. Here, as shown in Figures 35A and 35B, it is preferable that the insulating layer 282 is in contact with the side surface of the insulating layer 264, the top and side surface of the conductive layer 232a, the top and side surface of the conductive layer 232b, the semiconductor layer 251a, semiconductor layer 251b, the side and top surface of the insulating layer 263, and the top surface of the insulating layer 262. 【0573】 Furthermore, insulating layer 264 functions as a first gate insulating film in transistor 200. In addition, insulating layers 261 to 263 function as second gate insulating films. For these gate insulating films, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies can be used. In addition, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO) can be used. ３ ) or (Ba, Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) can be used in a single layer or a multilayer configuration. Furthermore, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulating layer material. Alternatively, these insulating layers may be subjected to nitriding treatment. 【0574】 Preferably, insulating layers 283 and 214, which function as interlayer films, are arranged on the transistor 200. Here, it is preferable that the insulating layer 283 is arranged in contact with the upper surfaces of the conductive layer 233, the insulating layer 264, and the insulating layer 213. In this case, it is preferable that the upper surface of the insulating layer 213 is flattened. 【0575】It is preferable that a conductive layer 235 (conductive layer 235a and conductive layer 235b) is provided, which connects to the transistor 200 and functions as a plug. For this reason, the conductive layer 235 is provided in contact with the inner wall of the opening of the insulating layer 282, insulating layer 213, insulating layer 283, and insulating layer 214. In particular, a first conductive layer of the conductive layer 235 may be provided in contact with the inner wall, and a second conductive layer of the conductive layer 235 may be provided on the side surface of the first conductive layer. Here, the height of the upper surface of the conductive layer 235 and the height of the upper surface of the insulating layer 214 can be made to be approximately the same. 【0576】 Specifically, for example, a first conductive layer of conductive layer 235a is provided in contact with one inner wall of two openings in insulating layer 214, insulating layer 283, insulating layer 213 and insulating layer 282, and a second conductive layer of conductive layer 235a is formed in contact with its side surface. A conductive layer 232a is located in a part of the bottom of the opening, and conductive layer 235a is in contact with conductive layer 232a. Similarly, for example, a first conductive layer of conductive layer 235b is provided in contact with the other inner wall of two openings in insulating layer 214, insulating layer 283, insulating layer 213 and insulating layer 282, and a second conductive layer of conductive layer 235b is formed in contact with its side surface. A conductive layer 232b is located in a part of the bottom of the opening, and conductive layer 235b is in contact with conductive layer 232b. 【0577】 Although the transistor 200 shows a configuration in which the first conductive layer and the second conductive layer of the conductive layer 235 are stacked, the present invention is not limited thereto. For example, the conductive layer 235 may be provided as a single layer or as a stacked structure of three or more layers. 【0578】 As shown in Figure 35B, in the region of the semiconductor layer 251b that does not overlap with the conductive layer 232, in other words, in the channel formation region of the semiconductor layer 251, the side surface of the semiconductor layer 251 is covered by the conductive layer 233. This makes it easier to apply the electric field of the conductive layer 233, which functions as the first gate electrode, to the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 233. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. 【0579】 For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. Therefore, as a material with a low dielectric constant, the insulating layer 213 can be made from a material that can be used for the insulating layer 212. 【0580】 <<Transistor Configuration Example 2>> In the schematic cross-sectional view of Figure 33, which shows an example of the configuration of a computing device, which is a semiconductor device according to one aspect of the present invention, transistors M1p, M3p, and M4p are each described as having a GL structure. However, the structures of transistors M1p, M3p, and M4p according to one aspect of the present invention are not limited to this. As an alternative to the GL structure, each of transistors M1p, M3p, and M4p according to one aspect of the present invention can be, for example, the structure of a vertical channel type transistor described below. 【0581】 Figures 36A to 36C show examples of the configuration of a vertical channel transistor. In a vertical channel transistor, the source electrode and drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction). 【0582】 The transistors shown in Figures 36A to 36C may also be called VFETs (Vertical Field Effect Transistors), vertical transistors, or vertical channel transistors, in addition to being vertical channel transistors. Furthermore, in this specification, in vertical channel transistors, one of the source electrode or drain electrode located at the bottom may be referred to as the bottom electrode. Also, the other of the source electrode or drain electrode located at the top may be referred to as the top electrode. 【0583】In particular, Figure 36A shows a schematic plan view of an example of a vertical channel type transistor 300, and Figures 36B and 36C show schematic cross-sectional views of the transistor 300. Figure 36B is a schematic cross-sectional view along the dashed line A1-A2 shown in Figure 36A, and Figure 36C is a schematic cross-sectional view along the dashed line A3-A4 shown in Figure 36A. Figure 37 shows a schematic perspective view of the transistor 300 and its surrounding wiring as shown in Figures 36A to 36C. 【0584】 The transistor 300 shown in Figures 36A to 36C and Figure 37 includes, as an example, a conductive layer 331 that functions as wiring or an electrode, a conductive layer 332 that functions as wiring or an electrode, a semiconductor layer 351 that is the active layer of the transistor 300, an insulating layer 361 that functions as the gate insulating film of the transistor 300, a conductive layer 333 that functions as the gate of the transistor 300, and a conductive layer 334 that functions as wiring. 【0585】 The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer film. Furthermore, since the conductive layer 331 functions as wiring, it extends along the dashed line A3-A4 in the schematic plan view of Figure 36A. 【0586】 For example, the conductive layer 331 can be a conductive layer applicable to transistors M1p, M3p, and M4p as described above. The same applies to conductive layers 332 to 334, which will be described later. 【0587】 An insulating layer 312 and a conductive layer 332, which function as an interlayer film, are formed in this order on the insulating layer 311 and the conductive layer 331. In Figure 36B, the insulating layer 312 has a three-layer structure consisting of two barrier insulating films that suppress the diffusion of impurities and an interlayer film sandwiched between these barrier insulating films. Preferably, the barrier insulating films have a function to suppress the diffusion of oxygen to prevent oxidation of the conductive layer 331 or the conductive layer 332. Furthermore, since the conductive layer 332 functions as wiring, it extends along the direction of the dashed line A1-A2 in the schematic plan view of Figure 36A. 【0588】 Furthermore, the insulating layer 312 and the conductive layer 332 have openings that reach the conductive layer 331 in the region overlapping with the conductive layer 331. Semiconductor layers 351 are formed on the sides and bottom of these openings. In other words, the semiconductor layer 351 is formed on the upper surface of the conductive layer 331, the side surface of the insulating layer 312, and the side surface of the conductive layer 332. The semiconductor layer 351 is also formed on a part of the upper surface of the conductive layer 332. The insulating layer 361 is provided so as to be in contact with the conductive layer 332, the semiconductor layer 351, and the insulating layer 312 both inside and outside the openings. Furthermore, conductive layers 333 are formed on the upper and side surfaces of the insulating layer 361 so as to fill the openings. 【0589】 Furthermore, an insulating layer 313, which functions as an interlayer film, is formed on the upper surface of the insulating layer 361 and the upper surface of the conductive layer 333. In addition, an opening that reaches the conductive layer 333 is formed in the region of the insulating layer 313 that overlaps with the conductive layer 333. Conductive layers 334 are embedded in the sides and bottom of the opening. A portion of the conductive layer 334 may be formed on the upper surface of the insulating layer 313. Furthermore, an insulating layer 314, which functions as an interlayer film, is formed on both the insulating layer 313 and the conductive layer 334. 【0590】 Furthermore, since the conductive layer 334 functions as wiring, it extends along the dashed line A3-A4 in the schematic plan view of Figure 36A. 【0591】 For insulating layers 311 to 314, it is preferable to use an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity as the interlayer film, parasitic capacitance occurring between wiring can be reduced. For this reason, each of the insulating layers 311 to 314 can be made from a material applicable to the insulating layer 212 or insulating layer 213 described above. 【0592】 Furthermore, since the insulating layer 361 functions as a gate insulating film, the insulating layer 361 can be made of a material that can be used for the insulating layer 264, for example. 【0593】A portion of the conductive layer 331 functions as either the source electrode or the drain electrode in the transistor 300. A portion of the conductive layer 332 functions as the other source electrode or drain electrode in the transistor 300. Furthermore, a portion or all of the conductive layer 333 functions as the gate electrode in the transistor 300. 【0594】 As described above, by forming an insulating layer, a conductive layer, and a semiconductor layer, a vertical channel transistor can be formed in which the channel length has a component in the height direction (vertical direction). Furthermore, the channel length of transistor 300 depends on the thickness of the insulating layer 312; the thinner the insulating layer 312, the shorter the channel length, and thus the on-current of transistor 300 can be increased. On the other hand, the thicker the insulating layer 312, the longer the channel length, and thus the off-current of transistor 300 can be decreased. 【0595】 Furthermore, the wiring connecting the source, drain, or gate of the vertical channel transistor is not formed by the same process, but by different processes. As a result, the wiring connecting the source, drain, or gate of the vertical channel transistor has overlapping regions in a plan view. Since the wiring connecting the source, drain, or gate of the vertical channel transistor is provided at different heights, the parasitic capacitance generated in each wiring can be reduced. This allows the drive frequency of the transistor 300 to be increased, and the drive speed of the arithmetic unit CDV and other components to be increased. 【0596】 This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments. 【0597】(Embodiment 4) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention. 【0598】 In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide. 【0599】 Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide. 【0600】 This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO. 【0601】 IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals. 【0602】 The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example...

Claims

It has a first circuit through a sixth circuit, a first drive cell, a second drive cell, a first calculation cell through a third calculation cell, and a selector. The selector has a first input terminal, a second input terminal, a first output terminal, and a control terminal. The selector has a function of making the connection between either the first input terminal or the second input terminal and the first output terminal conductive in response to a control signal input to the control terminal. The first circuit has the function of transmitting a first signal to the first calculation cell and the function of transmitting a second signal to the second calculation cell. The second circuit has the function of transmitting the third signal to the third calculation cell. The third circuit has the function of transmitting a first reference signal or a fourth signal to the first drive cell and the first calculation cell. The first drive cell has the function of maintaining a potential corresponding to the first reference signal and the function of maintaining the input potential and current when the fourth signal is input. The first calculation cell has the function of holding a potential corresponding to the first signal when the first reference signal is input, and the function of adding the product of the value corresponding to the first signal and the value corresponding to the fourth signal as a current to the first current flowing to the input terminal of the fifth circuit. The fifth circuit has the function of generating a fifth signal corresponding to the first current, and the function of transmitting the fifth signal to the second drive cell, the second calculation cell, and the third calculation cell via the second input terminal and the first output terminal. The fourth circuit has the function of transmitting a second reference signal to the second drive cell, the second calculation cell, and the third calculation cell via the first input terminal and the first output terminal. The second drive cell has the function of maintaining a potential corresponding to the second reference signal and the function of maintaining the input potential and current when the fifth signal is input. The second calculation cell has the function of holding a potential corresponding to the second signal when the second reference signal is input, and the function of adding the product of the value corresponding to the second signal and the value corresponding to the fifth signal as a current to the first current flowing to the input terminal of the fifth circuit. The third calculation cell has the function of holding a potential corresponding to the third signal when the second reference signal is input, and the function of adding the product of the value corresponding to the third signal and the value corresponding to the fifth signal as a current to the second current flowing to the input terminal of the sixth circuit. The sixth circuit has the function of generating a sixth signal corresponding to the second current and the function of outputting the sixth signal to the output terminal of the sixth circuit. Semiconductor equipment. 　 In claim 1, The fifth circuit has a function to adjust the timing of the output of the fifth signal by pipeline processing. Semiconductor equipment. 　 In claim 2, It has a first switch, a second switch, a third switch, a seventh circuit, and an eighth circuit. The output terminal of the fifth circuit is electrically connected to the first terminal of the first switch. The second terminal of the first switch is electrically connected to the input terminal of the seventh circuit. The output terminal of the seventh circuit is electrically connected to the first terminal of the second switch. The second terminal of the second switch is electrically connected to the input terminal of the eighth circuit. The output terminal of the eighth circuit is electrically connected to the first terminal of the third switch. The seventh circuit has the function of acquiring the fifth signal from the input terminal of the seventh circuit and outputting the fifth signal from the output terminal of the seventh circuit when the first switch and the third switch are ON, and the function of holding the fifth signal and outputting the fifth signal from the output terminal of the seventh circuit when the first switch and the third switch are OFF. The eighth circuit has the function of acquiring the fifth signal from the input terminal of the eighth circuit and outputting the fifth signal from the output terminal of the eighth circuit when the second switch is ON, and the function of holding the fifth signal and outputting the fifth signal from the output terminal of the eighth circuit when the second switch is OFF. Semiconductor equipment. 　 In claim 3, The seventh circuit comprises a first transistor, a second transistor, and a third transistor. The eighth circuit includes a fourth transistor, a fifth transistor, and a sixth transistor. Each of the first to third and fourth transistors has a different polarity from each of the fifth and sixth transistors. The input terminal of the seventh circuit is electrically connected to the first terminal of the first transistor and the first terminal of the second transistor. The second terminal of the first transistor is electrically connected to the gate of the second transistor and the gate of the third transistor. The output terminal of the seventh circuit is electrically connected to the first terminal of the third transistor. The input terminal of the eighth circuit is electrically connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor. The second terminal of the fourth transistor is electrically connected to the gate of the fifth transistor and the gate of the sixth transistor. The output terminal of the eighth circuit is electrically connected to the first terminal of the sixth transistor. Semiconductor equipment. 　 In claim 4, Each of the first and fourth transistors has an oxide semiconductor containing indium in its channel formation region. Semiconductor equipment. 　 It has a first circuit through a third circuit, a first calculation cell, and a second calculation cell, The third circuit has a first input terminal, a first output terminal, and a second output terminal. The first circuit has the function of transmitting a first coefficient to the first calculation cell. The first calculation cell has the function of holding a first value as a first potential, and the function of obtaining a first coefficient and flowing a second value, which is the result of multiplying the first value and the first coefficient, as a first current between the first calculation cell and the first input terminal. The third circuit has the function of holding a second potential corresponding to the current supplied to the first input terminal, the function of flowing a third value corresponding to the second potential as a second current between the first output terminal and the second calculation cell, and the function of outputting the third value as a third current to the second output terminal. The second circuit has the function of transmitting the second coefficient to the second calculation cell. The second calculation cell has the function of holding the third value as the third potential, and the function of obtaining the second coefficient and flowing the fourth value, which is the result of multiplying the third value and the second coefficient, as the fourth current between the second calculation cell and the first input terminal. Semiconductor equipment. 　 In claim 6, It has a fourth circuit, The fourth circuit has a second input terminal, a third input terminal, and a third output terminal. The fourth circuit has the function of flowing a fifth current, which is a first value corresponding to the difference between the current flowing through the second input terminal and the current flowing through the third input terminal, between the third output terminal and the first calculation cell. Semiconductor equipment. 　 In claim 7, It has a first switch to a fifth switch, The third output terminal is electrically connected to the first terminal of the first switch. The second terminal of the first switch is electrically connected to the first calculation cell and the first terminal of the second switch. The second terminal of the second switch is electrically connected to the first terminal of the third switch and the first input terminal. The first output terminal is electrically connected to the first terminal of the fourth switch. The second terminal of the fourth switch is electrically connected to the second terminal of the third switch and to the second calculation cell. The second output terminal is electrically connected to the first terminal of the fifth switch. The control terminals of the first switch, the fourth switch, and the fifth switch are electrically connected to the first wiring. The control terminals of the second switch and the third switch are electrically connected to the second wiring. Semiconductor equipment. 　 In claim 8, The third circuit has a first transistor to a fourth transistor, Either the source or drain of the first transistor is electrically connected to either the source or drain of the fourth transistor and to the first input terminal. The gate of the first transistor is electrically connected to the gate of the second transistor, the gate of the third transistor, and the other of the source or drain of the fourth transistor. Either the source or the drain of the second transistor is electrically connected to the first output terminal. Either the source or the drain of the third transistor is electrically connected to the second output terminal. Semiconductor equipment. 　 In claim 9, The first circuit has a fifth transistor having the same polarity as the fourth transistor. The source and drain of the fifth transistor are electrically connected to the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the other of the source or drain of the fourth transistor. Semiconductor equipment. 　 In claim 10, Each of the first to third transistors has silicon in the channel formation region. Each of the fourth and fifth transistors has an oxide semiconductor containing indium in its channel formation region. Semiconductor equipment. 　 In claim 11, The first arithmetic cell includes a sixth transistor, a seventh transistor, and a first capacitance element. The second calculation cell comprises an eighth transistor, a ninth transistor, and a second capacitance element. The polarity of each of the sixth to ninth transistors is different from the polarity of each of the first to third transistors. Either the source or drain of the sixth transistor is electrically connected to the gate of the seventh transistor and the first terminal of the first capacitive element. The second terminal of the first capacitive element is electrically connected to the first circuit. Either the source or drain of the eighth transistor is electrically connected to the gate of the ninth transistor and the first terminal of the second capacitance element. The second terminal of the second capacitive element is electrically connected to the second circuit. The sixth transistor and the first capacitance element have the function of maintaining the gate potential of the seventh transistor as the first potential. The eighth transistor and the first capacitance element have the function of maintaining the gate potential of the ninth transistor as the third potential. The seventh transistor has the function of flowing the first current between the source and drain of the seventh transistor by applying a potential corresponding to the first coefficient to the second terminal of the first capacitive element. The ninth transistor has the function of allowing the fourth current to flow between the source and drain of the ninth transistor when a potential corresponding to the second coefficient is applied to the second terminal of the second capacitance element. Semiconductor equipment. 　 In claim 12, Each of the sixth to ninth transistors has an oxide semiconductor containing indium in its channel formation region. Semiconductor equipment.

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