Semiconductor devices and electronic devices

Abstract

To provide a semiconductor device with a hierarchical artificial neural network being constructed, a semiconductor device with low power consumption, and an electronic apparatus comprising such a semiconductor device.SOLUTION: A hierarchical artificial neural network 100 has a first layer comprising neurons N1(1) to Np(1) (where p is an integer of 1 or greater), a (k-1)th layer comprising neurons N1(k-1) to neuron Nm(k-1) (where m is an integer of 1 or greater), the k-th layer has neurons N1(k) to neuron Nn(k) (where n is an integer of 1 or greater). The R-th layer has neurons N1(R) to Nq(R) (where q is an integer of 1 or greater).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the technology of one embodiment of the present invention disclosed in this specification more specifically relates to the above. Fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, signal processing device, processor, electronic device, system, driving method thereof, Examples of the manufacturing method and the inspection method thereof are as follows. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is progressing vigorously. The brain's mechanisms are incorporated as electronic circuits, and the brain's "neurons" and "systems" are connected. Therefore, such an integrated circuit is called a "neuromorph." It is also sometimes called "brain-morphic," "brain-inspired," or "brain-morphic." The integrated circuit has a non-von Neumann architecture, and power consumption decreases as processing speed increases. Compared to the larger von Neumann architecture, parallel processing can be performed with extremely low power consumption. It is expected that this will be possible.

[0004] The information processing model that mimics a neural network with "neurons" and "synapses" is called artificial neural network. These are called neural networks (ANNs). For example, see Non-Patent Document 1 and Non-Patent Document 2 uses SRAM (Static Random Access Memory) The document discloses a computing device that configures an artificial neural network. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-patent document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In artificial neural networks, the strength of the synapse that connects two neurons is called the The weighting coefficient is a function of the signal transmitted between two neurons. In particular, in a hierarchical artificial neural network, multiple first neural networks in the first layer are the strength of each synapse between the first neuron and one of the second neurons in layer 2, Each signal input from the first neurons of the layer to one of the second neurons of the second layer It is necessary to multiply and add (perform a product-sum operation) the artificial neural network For example, the number of coupling strengths and the number of parameters representing the signal are determined depending on the scale of the signal. In other words, the number of layers and neurons in an artificial neural network increases. The more neurons and synapses there are, the greater the computational complexity. can also be enormous.

[0007] For example, neural network operations include not only multiplication and accumulation but also activation function operations. The calculation of activation functions increases the size of the artificial neural network. The more the power consumption increases, the higher the power consumption tends to be.

[0008] One aspect of the present invention is a semiconductor device in which a hierarchical artificial neural network is constructed. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a novel semiconductor device, etc. Another object of one embodiment of the present invention is to provide an electric device including the semiconductor device. One of the objectives is to provide a sub-device.

[0009] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0010] (1) One aspect of the present invention includes a cell and a first circuit, the first circuit including a first capacitance and a first input a first input terminal and a second input terminal, and the cell is electrically connected to the first input terminal via a first wiring. The cell is electrically connected to the second input terminal via the second wiring, and the cell is The function of retaining data and inputting second data into the cell allows the cell and the first wiring a first current corresponding to the first data and the second data is passed between the cell and the second wiring; and a function of causing a second current to flow according to the first data and the second data, and the first capacitance is The differential voltage between the first potential corresponding to the current and the second potential corresponding to the second current is maintained. This is a semiconductor device.

[0011] (2) Alternatively, one aspect of the present invention is the above-described configuration (1), wherein the first circuit includes a second circuit, The second circuit is a semiconductor device having a function of acquiring a differential voltage and outputting a signal corresponding to the differential voltage. It is a body device.

[0012] (3) Alternatively, in one aspect of the present invention, in the configuration (2), the first circuit is a first current-voltage conversion a circuit, a second current-voltage conversion circuit, a first switch, a second switch, and a third switch; a fourth switch, the first input terminal of which is connected to a first terminal of the first switch and a first current-to-voltage converter; The second terminal of the first switch is electrically connected to the first terminal of the switching circuit. The first terminal is electrically connected to the first terminal of the first capacitor, and the second input terminal is electrically connected to the third switch. a third switch electrically connected to the first terminal of the first current-voltage conversion circuit and the first terminal of the second current-voltage conversion circuit; The second terminal of the fourth switch is electrically connected to the first terminal of the fourth switch and the second terminal of the first capacitor. The second terminal of the fourth switch is electrically connected to the first terminal of the second circuit, and the first current and voltage The conversion circuit converts the first current into a voltage in response to the first current input to the first terminal of the first current-voltage conversion circuit. The second current-voltage conversion circuit has a function of setting the potential of the first terminal of the voltage conversion circuit to a first potential, In response to the second current input to the first terminal of the second current-voltage conversion circuit, The semiconductor device has a function of setting the potential of the first terminal to the second potential.

[0013] (4) Alternatively, in one aspect of the present invention, in the configuration (3), the second terminal of the second switch is The first circuit is electrically connected to a third wiring that provides a semi-potential, and the first circuit includes a first switch and a third switch. The first switch and the fourth switch are turned on, and the second switch and the fourth switch are turned off. the first terminal of the first capacitor to a first potential, and the second terminal of the first capacitor to a second potential; The third switch and the fourth switch are turned off, and the second switch is turned on. , by changing the first terminal of the first capacitance from the first potential to the reference potential, a function of changing the second potential of the second terminal of the first capacitance to a third potential; a first switch; and a second switch. The second circuit is turned on by turning on the third switch and the fourth switch. and a function of inputting a third potential according to the differential voltage to the first terminal of the semiconductor device. .

[0014] (5) Alternatively, one aspect of the present invention includes a cell and a first circuit, the first circuit including a first capacitance and a The cell has two capacitors, a first input terminal, and a second input terminal, and the cell is connected to the first The cell is electrically connected to the input terminal, and the cell is electrically connected to the second input terminal via a second wiring. The cell has the function of holding the first data and the function of inputting the second data into the cell. A first current corresponding to the first data and the second data is passed between the cell and the first wiring, and and a function of passing a second current between the first wiring and the second wiring in accordance with the first data and the second data. The first capacitance is a first difference between a first potential corresponding to the first current and a second potential corresponding to the second current. The second capacitor has a function of holding a voltage, and the second capacitor has a first potential corresponding to the first current and a second potential corresponding to the second current. The semiconductor device has a function of holding a second differential voltage between the second potential and the second potential.

[0015] (6) Alternatively, one aspect of the present invention is the above-described configuration (5), wherein the first circuit is a second circuit and a third circuit. a first differential voltage referenced to the potential of the first terminal of the first capacitance; and outputting a first signal corresponding to the first differential voltage. A second differential voltage is obtained based on the potential of the second terminal of the second amplifier, and a second signal corresponding to the second differential voltage is generated. The semiconductor device has a function of outputting a signal.

[0016] (7) Alternatively, in one aspect of the present invention, in the configuration (6), the first circuit is a first current-voltage conversion a circuit, a second current-voltage conversion circuit, a first switch, a second switch, and a third switch; a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; the first input terminal is connected to a first terminal of the first switch, a first terminal of the fifth switch, and a first The second terminal of the first switch is electrically connected to the first terminal of the current-voltage conversion circuit. a third terminal of the fifth switch electrically connected to the first terminal of the switch and the first terminal of the first capacitor; The second terminal is electrically connected to the first terminal of the sixth switch and the first terminal of the second capacitor. The two input terminals are the first terminal of the third switch, the first terminal of the seventh switch, and the second current-voltage converter. The second terminal of the third switch is electrically connected to the first terminal of the switching circuit. The first terminal of the seventh switch is electrically connected to the second terminal of the first capacitor, and the second terminal of the seventh switch is electrically connected to the first terminal of the eighth capacitor. a fourth switch electrically connected to the first terminal of the switch and the second terminal of the second capacitor; The second terminal of the sixth switch is electrically connected to the first terminal of the second circuit, and the second terminal of the sixth switch is electrically connected to the first terminal of the third circuit. a first terminal of the first current-voltage conversion circuit; The potential of the first terminal of the first current-to-voltage converter circuit is converted to the first voltage in accordance with the first current input to the first terminal. The second current-voltage conversion circuit has a function of converting the voltage to a value input to the first terminal of the second current-voltage conversion circuit. a function of setting the potential of the first terminal of the second current-to-voltage conversion circuit to a second potential in accordance with the second current that is input; The semiconductor device has the following features.

[0017] (8) Alternatively, in one aspect of the present invention, in the configuration (7), the second terminal of the second switch is The second terminal of the eighth switch is electrically connected to the third wiring that provides the reference potential. The first circuit is electrically connected to a third wiring that connects the first switch and the third switch. The first terminal of the first capacitor is turned on, the second switch and the fourth switch are turned off, and a function of setting the second terminal of the first capacitor to a first potential and setting the second terminal of the first capacitor to a second potential; The sixth switch and the eighth switch are turned on, the sixth switch and the eighth switch are turned off, and the second switch is turned on. The first terminal of the capacitor is set to the first potential, and the second terminal of the second capacitor is set to the second potential. The first switch, the third switch, and the fourth switch are turned off, and the second switch is turned on. Then, by changing the first terminal of the first capacitor from the first potential to the reference potential, a function of changing the second potential of the second terminal of the first capacitor to a third potential; a fifth switch; The sixth switch and the seventh switch are turned off, and the eighth switch is turned on. By changing the second terminal of the capacitor from the second potential to the reference potential, the first capacitor a function of changing a first potential of a first terminal of the amount to a fourth potential; a first switch; and a second switch. and the third switch are turned off, and the fourth switch is turned on, so that the first a function of inputting a third potential corresponding to the first differential voltage to a terminal; a fifth switch; and a seventh switch. and the eighth switch are turned off, and the sixth switch is turned on, so that the first and a function of inputting a fourth potential corresponding to the second differential voltage to the terminal.

[0018] (9) Alternatively, in one embodiment of the present invention, in any one of the above structures (1) to (8), the cell , a first cell, and a second cell, and the first cell has a first wiring, a second wiring, and a first input wiring. The second cell is electrically connected to the first wiring, the second wiring, and the third input wiring. The first input wiring and the second input wiring are electrically connected to each other. Each of them has a function of applying a potential according to the second data, and the first cell is connected to the first input wiring. When the first input potential is input and the second input potential is input to the second input wiring, the first current The function of passing the voltage to the first wiring, and the function of inputting the second input potential to the first input wiring and When the first input potential is input, the second current flows through the second wiring, and the second current flows through the first input wiring. When the input potential is input and the second input potential is input to the second input wiring, and a function of making the first cell and the first wiring non-conductive, and the second cell and the second wiring non-conductive. The cell receives a first input potential on the first input wire and a second input potential on the second input wire. When a second input potential is input to the first input wire, the second current flows through the second wire. When the first input potential is input to the second input wiring, the first current flows through the first wiring. When the first input wiring is turned on, the second input potential is input to the first input wiring, and the second input potential is input to the second input wiring. When the second cell is turned on, the second cell and the first wiring are electrically disconnected from each other, and the second cell and the second wiring are electrically disconnected from each other. The semiconductor device has the function of

[0019] (10) Alternatively, in one aspect of the present invention, in the configuration (9), the first cell is a first transistor , the ninth switch, the tenth switch, the eleventh switch, the twelfth switch, and the third capacitor the second cell has a second transistor, a thirteenth switch, and a fourteenth switch; , a fifteenth switch, a sixteenth switch, and a fourth capacitor; The terminals are the first terminal of the ninth switch, the first terminal of the tenth switch, and the third terminal of the eleventh switch. a gate of the first transistor electrically connected to a first terminal of the third capacitor; The first terminal of the ninth switch is electrically connected to the first terminal of the twelfth switch. the second terminal of the tenth switch is electrically connected to the first wiring; a control terminal of the tenth switch electrically connected to the first input wiring; and a control terminal of the eleventh switch electrically connected to the first input wiring. The second terminal of the switch is electrically connected to the second wiring, and the control terminal of the eleventh switch is The first terminal of the second transistor is electrically connected to the first input wiring of the thirteenth switch. a terminal electrically connected to the first terminal of the fourteenth switch and the first terminal of the fifteenth switch; The gate of the second transistor is connected to the first terminal of the fourth capacitor and the first terminal of the sixteenth switch. , and the second terminal of the thirteenth switch is electrically connected to the second terminal of the sixteenth switch. The second terminal of the fourteenth switch is electrically connected to the second wiring, and the second terminal of the fourteenth switch is electrically connected to the second wiring. The control terminal of the switch is electrically connected to the first input wiring, and the second terminal of the fifteenth switch is electrically connected to the The control terminal of the 15th switch is electrically connected to the first wiring, and the control terminal of the 15th switch is electrically connected to the second input wiring. This is a semiconductor device.

[0020] (11) Alternatively, in one aspect of the present invention, in the configuration (10), the twelfth switch is a third transistor. the third transistor has a metal oxide in a channel formation region; The fourth transistor has a metal oxide layer in a channel forming region. The semiconductor device has a

[0021] (12) Another embodiment of the present invention is a semiconductor device according to any one of (1) to (11) above, and a housing and an electronic device that performs neural network calculations using a semiconductor device.

[0022] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. It may itself be a semiconductor device and may contain a semiconductor device.

[0023] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0024] An example of the case where X and Y are electrically connected is The elements that function as One or more devices (diode, display device, light-emitting device, load, etc.) are connected between X and Y. The switch has a function to control on / off. This means that the switch is either in a conducting state (ON state) or a non-conducting state (OFF state), and the current It has the function of controlling whether or not to let water flow.

[0025] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if X is transmitted to Y.

[0026] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are directly connected (i.e., there is no other This includes cases where the device is connected without any element or other circuit in between.

[0027] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and is not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0029] In this specification, the term "resistance element" refers to a resistor having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the term "resistance element" can be used as a circuit element, wiring, etc. " refers to wiring with resistance, transistors with current flowing between the source and drain, and diodes. Therefore, the term "resistive element" is used to refer to "resistor," "Load" or "area with a resistance value" and conversely, "resistance" or The terms "load" and "area having a resistive value" can be replaced with terms such as "resistive element." The resistance value is preferably, for example, 1 mΩ or more and 10 Ω or less, and more preferably The resistance can be set to 5 mΩ or more and 5 Ω or less, and more preferably 10 mΩ or more and 1 Ω or less. , for example, 1 Ω or more, 1×10 9 It may be set to Ω or less.

[0030] In this specification, the term "capacitance element" refers to a capacitance element having a capacitance value higher than 0 F. a circuit element having a capacitance value, a wiring area having a capacitance value, a parasitic capacitance, a gate of a transistor Therefore, in this specification, a "capacitive element" refers to a pair of Not only circuit elements including electrodes and dielectrics included between the electrodes, but also wiring and wiring The parasitic capacitance that appears between the gate and either the source or drain of the transistor. Also, the term "capacitance element," "parasitic capacitance," and "gate capacitance" are included. Terms such as "amount" can be replaced with terms such as "capacity" and vice versa. The term "capacitance element," "parasitic capacitance," "gate capacitance," etc. Also, the term "pair of electrodes" in "capacitance" can be used to refer to "pair of conductors" or "pair of The capacitance can be expressed as a "pair of conductive regions" or "pair of regions". For example, the capacitance can be set to 0.05 fF or more and 10 pF or less. It may be set to 10 μF or more.

[0031] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain can be interchanged. In addition, in this specification and the like, when describing the connection relationship of a transistor, "One of the source and drain" (or first electrode, or first terminal), "the source or drain The term "second electrode" or "second terminal" is used. In some cases, a back gate is provided in addition to the three terminals described above. In this specification, either the gate or the back gate of a transistor is referred to as a first gate. The other of the gate or back gate of the transistor is sometimes called the second gate. Furthermore, the terms "gate" and "backgate" are interchangeable for the same transistor. In addition, if a transistor has three or more gates, In this specification, each gate is referred to as a first gate, a second gate, a third gate, etc. It is sometimes called.

[0032] In this specification, a node may be a terminal, a wiring, or the like depending on the circuit configuration, device structure, etc. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0033] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the earth potential (ground potential), then "voltage" can be rephrased as "potential." Round potential does not necessarily mean 0V. Also, potential is relative. By changing the reference potential, the potential applied to the wiring, the potential applied to the circuit, etc. The potential, the potential output from the circuit, etc. also changes.

[0034] "Current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the electric conduction of a positively charged The statement "electrical conduction is occurring in the opposite direction" should be interpreted as "electrical conduction is occurring in the negatively charged body." Therefore, in this specification, unless otherwise specified, the term "current" is used. This refers to the phenomenon of charge transfer (electrical conduction) that accompanies the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the system through which current flows. (For example, semiconductor, metal, electrolyte, vacuum, etc.) The "direction of current" in the above cases is the direction in which positive carriers move, and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of the current, and negative current Therefore, in this specification, the positive and negative currents (or the direction of the current) Unless otherwise specified, statements such as "current flows from element A to element B" should be interpreted as "current flows from element B to element A." This can be rephrased as "current flows into element A" or "current flows into element B". The description "a current is output from element A" can be rephrased as "a current is output from element A" do.

[0035] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0036] In addition, in this specification, the terms "above" and "below" that indicate the arrangement of the components are the same. The positional relationship of the two is sometimes used for convenience in explaining with reference to the drawings. The relative positions of the elements change depending on the direction in which each element is depicted. Therefore, the terminology is not limited to that explained in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on top of conductor" is By rotating it 180 degrees, it can be rephrased as "insulator located on the underside of a conductor." can be done.

[0037] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0038] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to

[0039] In addition, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not limit the function of the element. For example, "electrode" is used as part of "wiring." Furthermore, the terms "electrode" and "wiring" may be used interchangeably, and vice versa. This also includes cases where the "electrodes" and "wiring" are integrally formed. "Terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" refers to a combination of multiple "electrodes," "wiring," "terminals," etc. For example, "electrode" is a "wiring" or "terminal." For example, a "terminal" can be a part of a "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be used interchangeably with "area." " may be replaced with terms such as "

[0040] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" have been changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". In addition, the opposite is also true, and terms such as "signal line" can be used to refer to "power line". In some cases, it may be possible to change the term to "potential" or "voltage" applied to the wiring. In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change the term to something like this.

[0041] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. This can result in the formation of DOS (Density of States) in semiconductors. In some cases, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, other than the main component Transition metals, especially hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, if the semiconductor is a silicon layer, In this case, impurities that change the properties of the semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 1, Group 2, Group 13, and Group 15.

[0042] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0043] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the input electrode can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction.

[0045] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" or "approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Almost perpendicular" or "roughly perpendicular" means that two straight lines are arranged at an angle of 60° or more and 120° or less. This refers to a state in which something is happening. [Effects of the Invention]

[0046] According to one aspect of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed is provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Another embodiment of the present invention is to provide a novel semiconductor device or the like. Another embodiment of the present invention is to provide an electronic device including the semiconductor device. It is possible.

[0047] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, it may not have [Brief explanation of the drawings]

[0048] [Figure 1] 1A and 1B are diagrams illustrating a hierarchical neural network. [Figure 2] FIG. 2A is a circuit diagram showing an example of the configuration of a semiconductor device, and FIGS. 2B and 2C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 3] 3A to 3C are circuit diagrams showing examples of the configuration and operation of a semiconductor device. [Figure 4] 4A and 4B are circuit diagrams showing an example of the configuration and operation of a semiconductor device. [Figure 5] FIG. 5 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 6] 6A to 6C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 7] 7A to 7C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] FIG. 9 is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 11] 11A and 11B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 13] 13A to 13D are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 14] 14A to 14C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 16]FIG. 16 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 18] 18A and 18B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 19] 19A to 19E are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 20] 20A to 20C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 22] 22A and 22B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 23] 23A to 23C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 24] 24A to 24C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 25] 25A to 25C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 26] 26A to 26C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 27] 27A and 27B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 28] 28A and 28B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 29] 29A to 29C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 30] 30A to 30C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 31] 31A to 31C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 32]32A and 32B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 33] FIG. 33 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 34] FIG. 34 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 35] 35A to 35C are cross-sectional views illustrating examples of the configuration of a semiconductor device. [Figure 36] 36A and 36B are cross-sectional views illustrating examples of the structure of a transistor. [Figure 37] FIG. 37 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 38] 38A and 38B are cross-sectional views illustrating examples of the structure of a transistor. [Figure 39] FIG. 39 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 40] FIG. 40A is a top view showing an example of the configuration of a capacitor, and FIGS. 40B and 40C are cross-sectional perspective views showing an example of the configuration of a capacitor. [Figure 41] FIG. 41A is a top view showing an example of the configuration of a capacitor, FIG. 41B is a cross-sectional view showing the example of the configuration of a capacitor, and FIG. 41C is a cross-sectional perspective view showing the example of the configuration of a capacitor. [Figure 42] FIG. 42A is a diagram illustrating the classification of IGZO crystal structures, FIG. 42B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 42C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 43] FIG. 43A is a perspective view showing an example of a semiconductor wafer, FIG. 43B is a perspective view showing an example of a chip, and FIGS. 43C and 43D are perspective views showing an example of an electronic component. [Figure 44] FIG. 44 is a perspective view showing an example of an electronic device. [Figure 45] 45A to 45C are perspective views showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0049] In artificial neural networks (hereafter referred to as neural networks), ,The connection strength of the synapses is determined by providing existing information to the neural ,network. In this way, we can feed the neural network with existing information and generate results. The process of determining the combined strength is sometimes called "learning."

[0050] In addition, no action is taken against the neural network that has undergone "learning" (the connection weights have been determined). By providing some information, new information can be output based on the connection strength. In this way, neural networks make decisions based on the given information and connection strengths. The process of generating new information through neural networks is sometimes called "inference" or "cognition."

[0051] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are called "deep neural networks." They call machine learning using deep neural networks "DNNs" and call machine learning using deep neural networks " It is sometimes called "deep learning."

[0052] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have amplifying, rectifying, and and forming a channel forming region of a transistor having at least one of a switching function and a If possible, the metal oxide is referred to as a metal oxide semiconductor. It can also be called OS FET or OS When referring to a transistor, it refers to a transistor having a metal oxide or oxide semiconductor. This can be rephrased as sta.

[0053] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0054] In addition, in this specification and the like, the configurations shown in each embodiment may be interchangeable with the configurations shown in other embodiments. The above-described embodiments can be combined appropriately to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0055] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0056] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0057] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0058] The embodiments described in this specification will be described with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are designated by the same reference numerals. The same elements are used in different drawings, and repeated explanations may be omitted. In some cases, in order to ensure clarity of the drawings, some components may be omitted. be.

[0059] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0060] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely conceptual examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing errors This can include variations in signal, voltage, or current.

[0061] Also, for this specification and the like, "In:Ga:Zn = 4:2:3 or in the vicinity thereof" means that when In is 4 with respect to the total number of atoms, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 5:1:6 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, "In:Ga:Zn = 1:1:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, "In:Ga:Zn = 5:1:3 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 10:1:3 or in the vicinity thereof" means that when In is 10 with respect to the total number of atoms, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Zn = 2:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.25 and 0.75 or less (0.25 < Zn ≤ 0.75). Also, "In:Zn = 5:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.12 and 0.25 or less (0.12 < Zn ≤ 0.25). Also, "In:Zn = 10:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12). For the total number of atoms, when In is 4, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 5:1:6 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). For the total number of atoms, when In is 5, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, "In:Ga:Zn = 1:1:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). For the total number of atoms, when In is 1, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). For the total number of atoms, when In is 1, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, "In:Ga:Zn = 5:1:3 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). For the total number of atoms, when In is 5, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and .1 or less (2 ≤ Zn ≤ 4.1). For the total number of atoms, when In is 5, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Ga:Zn = 10:1:3 or in the vicinity thereof" means that when In is 10 with respect to the total number of atoms, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). For the total number of atoms, when In is 10, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, "In:Zn = 2:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.25 and 0.75 or less (0.25 < Zn ≤ 0.75). For the total number of atoms, when In is 1, Zn is greater than 0.25 and 0.75 or less (0.25 < Zn ≤ 0.75). Also, "In:Zn = 5:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.12 and 0.25 or less (0.12 < Zn ≤ 0.25). For the total number of atoms, when In is 1, Zn is greater than 0.12 and 0.25 or less (0.12 < Zn ≤ 0.25). Also, "In:Zn = 10:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12). For the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12). For the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12).

[0062] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention is a neural network processor. The arithmetic circuit that performs the calculation will be described.

[0063] <Hierarchical neural network> First, we will explain about hierarchical neural networks. For example, the network has one input layer, one or more intermediate layers (hidden layers), and one output layer. The hierarchical neural network shown in Figure 1A has three or more layers. Neural network 100 is an example of such a network. The layer has R layers (where R can be an integer of 4 or greater). The first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In addition, in FIG. 1A, the (k-1)th layer and the kth layer (where k is 3 or more, R-1) are shown as intermediate layers. The following integers are used.) are shown in the figure, and other intermediate layers are omitted from the illustration. .

[0064] Each layer of the neural network 100 has one or more neurons. In this case, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is 1 or more ) and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 ( k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer is Neuron N1 (R) Neuron N q (R) (where q is an integer greater than or equal to 1.) It has.

[0065] In addition, in Figure 1A, neuron N1 (1) , neuron N p (1) , neuron N1 ( k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , Neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j ( k) (where j is an integer between 1 and n) are also shown. The illustration of the .

[0066] Next, the transmission of signals from the neurons in the previous layer to the neurons in the next layer, and the In this explanation, we will explain the signals input and output in the k-th layer of the neural network. N j (k) Focus on.

[0067] Figure 1B shows the k-th layer neuron N j (k) and neuron N j (k) The signal input to No. and Neuron N j (k) 10 shows the signal output from the

[0068] Specifically, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1 ) The output signal z1 (k-1) ~z m (k-1) But neuron N j ( k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is used as the output signal The output is directed to each neuron in the layer (not shown).

[0069] The signals input from the neurons in the previous layer to the neurons in the next layer are transmitted between those neurons. The strength of the synapse (hereafter referred to as the weighting coefficient) that connects the In the neural network 100, the output from the previous layer neuron is The signal is multiplied by the corresponding weighting coefficient and input to the neuron in the next layer. The (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer Newron N j (k) The signal input to can be expressed by equation (1.1).

[0070]

number

[0071] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) of From each, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1 ) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) · z m (k-1) is input. At this time, the k-th layer neuron N j (k) The signal input to The sum of the numbers j (k) is expressed as equation (1.2).

[0072]

number

[0073] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and neurons signal z1 (k-1) ~z m (k-1) The result of the sum of products of and is biased. When the bias is b, equation (1.2) can be rewritten as .

[0074]

number

[0075] Neuron N j (k) u j (k) Depending on j (k) Generates In. Neuron N j (k) Output signal z from j (k) is defined as follows:

[0076]

number

[0077] The function f(u j (k) ) is the activation function in a hierarchical neural network , step function, linear ramp function, sigmoid function, etc. The activation function may be the same for all neurons or may be different. Therefore, the activation functions of neurons in each layer may be the same or different.

[0078] By the way, the signal output by the neuron in each layer, the weight coefficient w, or the bias b is The value may be an analog value or a digital value. For example, the digital value may be a binary value. It may be a ternary value, or a value with an even larger number of bits. For analog values, the activation function can be, for example, a linear ramp function or a sigmoid function. In the case of binary digital values, for example, the output can be set to -1 or 1, or 0 or A step function with a value of 1 or less can be used. The signal output by the neurons in each layer is Three or more values ​​may be used. For example, an activation function that outputs three values ​​may have outputs of -1, 0, or 1, or a step function with 0, 1, or 2. For example, an activation function that outputs five values ​​can be -2, -1, 0, 1, and Alternatively, a step function with a factor of 2 may be used. Use a digital value for at least one of the weighting coefficient w or bias b. This reduces the circuit size, reduces power consumption, or improves the processing speed. Also, the signals output by the neurons in each layer, the weight coefficients w , or for bias b, by using analog values ​​for at least one This makes it possible to improve the accuracy of calculations.

[0079] The neural network 100 receives an input signal at the first layer (input layer). Therefore, in each layer from the first layer (input layer) to the last layer (output layer), the input from the previous layer is sequentially Based on the input signal, equation (1.1), equation (1.2) (or equation (1.3)), equation (1.4) The output signal is generated using the , and the output signal is output to the next layer. The signal output from the input layer is converted into the result calculated by the neural network 100. Equivalent.

[0080] <Configuration example 1 of an arithmetic circuit> Here, in the above-described neural network 100, the equation (1.2) (or the equation (1 .3)) and an example of an arithmetic circuit that can perform the calculation of equation (1.4) will be described. In the arithmetic circuit, as an example, the synaptic circuit of the neural network 100 The weighting coefficient of the path can be a digital value of two or more values ​​or an analog value. The activation function of the phonon can be a step function or the like. , weight coefficients, and the value of the signal input from the neuron in the previous layer to the neuron in the next layer (calculated value and One of them will be referred to as the first data and the other as the second data. The neural network 100 may be referred to as a synaptic circuit. The calculation coefficient and the calculation value are not limited to digital values, and at least one of them can be an analog value. It is also possible to use

[0081] The arithmetic circuit 110 shown in FIG. 2A includes, for example, an array portion ALP and a circuit AFP. The arithmetic circuit 110 is, for example, a semiconductor device that includes the k-th layer in FIGS. 1A and 1B. Neuron N j (k) The signal input to the neuron N j (k) Output from Signal z j (k) However, one embodiment of the present invention is not limited to this. The arithmetic circuit 110 may function as a storage device or a memory circuit, for example. For example, the arithmetic circuit 110 may be implemented using a DRAM, an SRAM, or a flash memory. Alternatively, the arithmetic circuit 110 may function as a memory circuit. It may function as a circuit that performs calculations on .

[0082] The array unit ALP includes, for example, circuits MP[1,j] to MP[m,j]. In addition, the circuit AFP includes, for example, a circuit ACTF[j], and further includes a circuit ACTF[ j] has a capacitance CRE, a circuit AC, a terminal T1, and a terminal T2.

[0083] The capacitance CRE may be realized using a normal capacitance element. This is not limiting. For example, the capacitance CRE may be, for example, as shown in FIG. 2B or FIG. 2C. As shown in the figure, this may be realized by using the gate capacitance of a transistor. The transistor may be of N-channel type, P-channel type, or both. 2B and 2C, a transformer may be connected in place of the capacitor CRE. The transistor CRET is, for example, an OS transistor. Note that the OS transistor will be described in detail in Embodiment 5. In addition to the OS transistor, for example, a transistor having silicon in a channel formation region is also available. The transistor may be a silicon transistor (hereinafter referred to as a silicon transistor). The silicon may be, for example, single crystal silicon, hydrogenated amorphous silicon, or finely crystalline silicon. Crystalline silicon, polycrystalline silicon, or the like can be used. As a transistor other than a Si transistor, for example, a transistor with a Ge active layer is used. Activates compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe. transistors with carbon nanotubes as active layers, transistors with carbon nanotubes as active layers, organic semiconductors A transistor having an active layer formed of the silicon dioxide can be used.

[0084] Each of the circuits MP[1,j] to MP[m,j] includes a wiring OL[j] and a wiring O LB[j] and the circuits MP[1,j] to MP[m , j] are electrically connected to the wiring XLS[1] to the wiring XLS[m]. In addition, the wiring OL[j] is electrically connected to the terminal T1, and the terminal T1 is the first terminal of the capacitance CRE. The wiring OLB[j] is electrically connected to the terminal T1, and the wiring OLB[j] is electrically connected to the terminal T2. 2 is electrically connected to the second terminal of the capacitor CRE. Between the first terminal of the capacitance CRE and the Similarly, for example, the terminal T2 and the second terminal of the capacitor CRE may be connected to each other. Between the child and the other, some element or circuit (for example, a switch, transistor, etc.) is connected. It may be done.

[0085] Each of the wires XLS[1] to XLS[m] is, for example, a neuron N1 (k-1) Neuron N m (k-1) The signal z1 output from (k-1) ~z m ( k-1) It has the function of transmitting a potential according to the

[0086] The circuit MP[1,j] is, for example, a neuron N1 (k-1) and neuron N j (k ) Weighting coefficient w1 between (k-1) j (k) (Here, the first data) Similarly, a circuit MP[m,j] may have, for example, neurons N m (k-1) Toni Newron N j (k) The weighting factor w between m (k-1) j (k) It has the function of retaining the

[0087] Also, the circuit MP[1,j] is, for example, a neuron N1 (k-1) is output from signal z1 (k-1) (Here, we will call this the second data) and the first data w1 (k-1) j (k) Similarly, the circuit MP[m,j] has the function of outputting the product of N m (k-1) The signal z output from m (k-1) (Here, we will call this the second data) and 1 data w m (k-1) j (k) It has the function of outputting the product of

[0088] As a specific example, the circuit MP[1,j] is connected to the second data z 1 (k-1) By inputting a potential according to the first data w1 (k-1) j (k) and the second data z1 (k-1) Information according to the product of The voltage (voltage, etc.) is output to the wiring OL[j] and / or wiring OLB[j]. As an example, similarly, the second data z m (k-1)By inputting a potential according to the first data w m (k-1) j (k) and the second data z m (k-1) Information according to the product of The output voltage (voltage, etc.) is output to the wiring OL[j] and / or wiring OLB[j].

[0089] For example, in the wiring OL, the circuits MP[1,j] to MP[m,j] The information output from each (for example, current, voltage, etc.) is added together. For example, in the wiring OLB, each of the circuits MP[1,j] to MP[m,j] The information output from these (for example, current, voltage, etc.) is summed up. The first data w1 (k-1) j (k) Or even w m (k -1) j (k) and the second data z1 (k-1) ~z m (k-1) Information according to the sum of products (e.g. However, one embodiment of the present invention is not limited to this. For example, in at least one of the wiring OL and the wiring OLB, some reference (e.g., The information (e.g., current, voltage, etc.) that is the reference, precharge, bias, etc. This may also be done.

[0090] The specific circuit configurations of the circuits MP[1,j] to MP[m,j] will be described later. Describe.

[0091] For example, the circuit ACTF[j] is a first circuit formed from the wiring OL[j] and the wiring OLB[j]. The information (e.g., current, voltage, etc.) corresponding to the sum of the products of the first data and the second data is acquired, and the Ron N j (k) The signal z output from j (k) It functions as a circuit that generates is generated from the information by the circuit AC included in the circuit ACTF[j], such as binary or multi-valued. What digital or analog value represents the output signal z? j (k) (The calculated value is sometimes called In other words, the circuit AC is treated as an activation function circuit, for example. .

[0092] The circuit AC may be, for example, an analog-to-digital conversion circuit (also called a sense amplifier, etc.) ) can be used. Specifically, the circuit AC can be, for example, a product-sum When the result is less than or equal to "0", the output signal z j (k) A digital signal with a value of "0" is generated. When the result of the sum of products is "positive", the output signal z j (k) As a "positive" digital It may be an analog-to-digital conversion circuit that outputs a value.

[0093] In this specification, each of the circuits MP[1,j] to MP[m,j] is When there is no need to distinguish between them, they will be referred to as the circuit MP. When there is no need to distinguish between XLS[m], it will be written as wiring XLS. The [j] in each of wiring OL[j] and wiring OLB[j] is omitted. Similarly, the [j] in the circuit ACTF[j] can be omitted and written as OLB. It may be referred to as circuit ACTF.

[0094] <Operation example 1 of the arithmetic circuit> Next, an example of the operation of the circuit ACTF[j] in FIG. 2A will be described. Each of these is a circuit diagram showing the sequence of an example of the operation of the circuit ACTF[j].

[0095] In Figure 3A, the voltage between the first and second terminals of the capacitor CRE in the circuit ACTF[j] is set to 0V. Specifically, in the circuit of FIG. 3A, the wiring OL[j] and For example, V ini is given V ini As an example, current flows from wiring OL to circuit MP. When current flows from the circuit MP to the wiring OL, it becomes VDD. or GND.

[0096] In FIG. 3B, the first data is generated by each of the circuits MP[1,j] to MP[m,j]. Data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) No Toz m (k-1) The information (e.g., current, voltage, charge, etc.) according to the sum of products of j] and wiring OLB[j], and the circuit ACTF[j] acquires the information. In this example, the potential V of the first terminal of the capacitor CRE ini is wired from the circuit MP Based on the information input to the circuit ACTF[j] via OL[j], the potential V OL Changed to , and the potential V of the second terminal of the capacitance CRE ini is transmitted from the circuit MP via the wiring OLB[j]. Based on the information input to the circuit ACTF[j], the potential V OLB It is assumed that the value changes to At this time, the voltage between the first and second terminals of the capacitor CRE is |V RD |(=|V OLB -V OL |) and this |V RD For example, | is the information flowing through the wiring OL[j]. This corresponds to the difference between the total amount of information flowing through the wiring OLB[j] and the total amount of information flowing through the wiring OLB[j]. If the line OL[j] is the sum of positive values ​​and the line OLB[j] is the sum of negative values, , |V RD | corresponds to the difference between the sum of positive values ​​and the sum of negative values. Therefore, |V RD | corresponds to the result of the sum-of-products operation. That is, circuits MP[1,j] to MP[m,j] The first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) The sum of products is the voltage |V RD |As, capacity CRE The resistor can be held between the first terminal and the second terminal.

[0097] In Figure 3C, as an example, the voltage (charge) stored in the capacitor CRE is input to the circuit AC. In this case, the potential V OL , and potential V OLB changes significantly depending on the result of the sum of products. If you input it directly into the AC circuit, the circuit configuration of the AC circuit may become complicated, or There may be disadvantages such as the AC operating range being smaller. As an example, the potential V OL , and potential V OLB Even if the magnitudes of the is |V RD |(=|V OLB -V OL If |) are at the same voltage, then the AC It is desirable that the same voltage is input. For example, the potential V O L =1, potential V OLB Even in the case of =2, the potential V OL =3, potential V OLB In the case of =4, either Ramo|V RD |=1, and |V RD | will be the same size. It is desirable that the same voltage is input to the AC circuit. For example, at least one of the first terminal and the second terminal of the capacitor CRE is electrically floating. Then, either the first terminal of the capacitor CRE or the second terminal of the capacitor CRE The reference potential (here, as an example, the GND potential (0V)) is set to However, it is not limited to this, and may be a VDD potential, a precharge potential, a potential of (VDD / 2), etc. Then, either the first terminal of the capacitance CRE or the second terminal of the capacitance CRE The potential of either one is |V RD That is, the potential V OL , and potential V OLB Even if the magnitude of |V RD If | is the same, the same potential is applied to the circuit AC The circuit AC can then sense the potential of the second terminal of the capacitor CRE, for example. Singing, voltage V RD signal z according to j (k) In other words, the operation shown in Figure 3C As an example, the first data output by the circuits MP[1,j] to MP[m,j] and the second data, the signal z j (k) will be output.

[0098] Here, a specific example of the above operation will be described.

[0099] First data w1 (k-1) j (k) Or even w m (k-1) j (k) Each of the following has an explanation: For simplicity, for example, the second data can take the value "+1", "0", or "-1". Ta z1 (k-1) ~z m (k-1) Each of these can be, for example, "+1", "0", "-1" ".

[0100] In the operation example of FIG. 3A, the potential V ini is assumed to be precharged to a high level potential.

[0101] In addition, in the circuit MP, when the product of the first data and the second data is "+1", the circuit M Conduction occurs between P and wiring OL, and non-conduction occurs between circuit MP and wiring OLB. Then, a current corresponding to "|+1|" flows from the wiring OL to the circuit MP. In addition, in the circuit MP, when the product of the first data and the second data is "-1", The circuit MP and the wiring OL are in a non-conductive state, and the circuit MP and the wiring OLB are in a conductive state. Then, a current corresponding to "|-1|" flows from the wiring OLB to the circuit MP (i.e. , a current of the same magnitude as the current corresponding to "|+1|" flows. In this case, when the product of the first data and the second data is "0", , and the circuit MP and the wiring OLB are in a non-conductive state. In the wiring OLB, a current of the magnitude of the positive sum flows. is playing.

[0102] At this time, in the operation example of FIG. 3B, the potential V OL The size of the first data and the second data It is determined by the number of circuits MP whose product is "+1". The more circuits MP whose product of the second data is "+1", the more the number of circuits MP from the wiring OL to the circuit M The total amount of current flowing through the wiring O[1,j] to the circuit MP[m,j] increases. L is connected to a high-level potential V ini is precharged, so the circuit MP[1 , j] to the circuit MP[m, j], the larger the total amount of current flowing through the wiring OL, the greater the potential V i ni In other words, the product of the first data and the second data is "+1." The more circuits MP are connected, the greater the potential V OL will be lower.

[0103] Similarly, the potential V OLB The magnitude of the first data and the second data is "-1". Specifically, the product of the first data and the second data is "-1". The more circuits MP[1,j] are connected to the wiring OLB, the more The total amount of current flowing through P[m,j] increases. Also, the wiring OLB has a high-level potential. The potential V iniare precharged, the circuits MP[1,j] to MP[ The larger the total current flowing through the wiring OLB, the greater the potential V ini Voltage drop from In other words, the product of the first data and the second data is "-1" in the circuit MP. The greater the number, the greater the potential V OLB will be lower.

[0104] From the above, the number of circuits MP where the product of the first data and the second data is "+1" is When the product of the first data and the second data is greater than the number of circuits MP that are "-1", The potential V of the first terminal of the quantity CRE OL is the potential V of the second terminal of the capacitance CRE OLB Lower than That is, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and Day 2 Ta z1 (k-1) ~z m (k-1) When the sum of the products is positive, the potential V OL is the potential V OLB In addition, the product of the first data and the second data is "-1". The number of MPs is less than the number of circuit MPs where the product of the first data and the second data is "+1". When the potential V of the first terminal of the capacitance CRE is also large, OL is the potential V of the second terminal of the capacitance CRE O LB That is, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m(k-1) When the sum of the products is negative, Place V OL is the potential V OLB It will be higher than.

[0105] In addition, the number of circuits MP where the product of the first data and the second data is "+1" is When the product of the first data and the second data is equal to the number of circuits MP that are "-1", or when the product of the second data and the second data is equal to the number of circuits MP that are "-1", In all of the circuits MP[1,j] to MP[m,j], the product of the first data and the second data is When it is set to "0", the potential V of the first terminal of the capacitor CRE OL is the second terminal of the capacitor CRE potential V OLB That is, the first data w1 (k-1) j (k) Or even w m (k -1) j (k) and the second data z1 (k-1) ~z m (k-1) The sum of products with this is "0" When the potential V OL and potential V OLB Furthermore, in all cases, the first When the product of the first data and the second data is "0", the potential V OL and potential V OLB That is, Place V ini It will remain as it is.

[0106] In addition, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z 1 (k-1) ~z m (k-1) The larger the absolute value of the sum of the products, the greater the potential V OL and potential V O LB The potential difference (absolute value of the voltage between the first terminal and the second terminal of the first capacitance) becomes large.

[0107] In the above example, the first data w1 (k-1) j (k) Or even w m (k-1) j ( k) Each of these can take the values ​​"+1", "0", or "-1". However, the operation of the semiconductor device of one embodiment of the present invention is not limited thereto. First data w1 (k-1) j (k) Or even w m (k-1) j (k) The possible values ​​of "+2 It may be multi-valued, with more than three values, such as "+1", "0", "-1", "-2", etc. , "+1", "-1", etc. The amount of current flowing between MP[m,j] and wiring OL and / or wiring OLB is , j] to the circuit MP[m, j]. (k-1) j (k) Or even w m (k-1) j (k) The value is determined based on the product of the possible values ​​of the second data. Specifically, for example, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) Each of these is either "+2", "+1", "0", "-1" or "-2". Take the second data z1(k-1) ~z m (k-1) are "+1", "0", Here, in the circuit MP, the first data and When the product of the second data is "+1", the circuit MP and the wiring OL are in a conductive state, and the circuit Assuming that there is no conduction between the circuit MP and the wiring OLB, current flows from the wiring OL to the circuit MP. Quantity I ut In the circuit MP, the first data and the second data When the product of these is "+2", the circuit MP and the wiring OL are in a conductive state, and the circuit MP and the wiring OL are in a conductive state. Assuming that there is no conduction between the wire OLB and the circuit MP, the current amount from the wire OL to the circuit MP is 2 × I u t In addition, if the product of the first data and the second data is "-1", When this occurs, the circuit MP and the wiring OL are in a non-conductive state, and the circuit MP and the wiring OLB are in a non-conductive state. Assuming that the circuit is in a conducting state, the current amount I ut A current of When the product of the first data and the second data is "-2", the circuit MP and the The circuit MP and the wiring OLB are in a non-conductive state, and the circuit MP and the wiring OLB are in a conductive state. Then, the current amount from wiring OLB to circuit MP is 2 × I ut It is sufficient to assume that a current of When the product of the first data and the second data is "0", there is no conduction between the circuit MP and the wiring OL. The conduction state may be such that the circuit MP and the wiring OLB are not in a conducting state.

[0108] As described above, by performing the operation example of FIG. 3B, the voltage between the first terminal and the second terminal of the first capacitor The pressure is the first data w1 (k-1) j (k) Or even wm (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) The potential V OL and potential V OLB potential difference with (Voltage | V RD |).

[0109] Then, as shown in the operation example of FIG. 3C, for example, the second terminal of the capacitor CRE is electrically connected to Put it in a floating state (the first terminal of the capacitor CRE may also be electrically floating), and then By setting the potential of the first terminal of the capacitor CRE to the GND potential, the potential of the second terminal of the capacitor CRE is V RD First data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second Data z1 (k-1) ~z m (k-1) If the sum of the products is positive, the second Terminal potential V RD becomes a positive potential, and the first data w1 (k-1) j (k) Or even w m (k- 1) j (k) and the second data z1 (k-1) ~z m (k-1) If the sum of products with In this case, the potential V of the second terminal of the capacitor CRE RD becomes a negative potential. (k- 1) j (k) Or even w m (k-1) j(k) and the second data z1 (k-1) ~z m (k-1 ) When the sum of the products is "0", the differential voltage between the first terminal and the second terminal of the capacitance CRE is approximately 0 Therefore, the potential of the second terminal of the capacitance CRE is V RD becomes the GND potential.

[0110] Then, by sensing the potential of the second terminal of the capacitor CRE by the circuit AC, and voltage V RD Output signal z according to j (k) In other words, the capacitance CR The potential V of the first terminal of E OL and the potential V of the second terminal of the capacitance CRE OLB When both are large, Even in this case, the potential V of the first terminal of the capacitor CRE OL and the potential V of the second terminal of the capacitance CRE O LB Even if and are small, the potential V OL and potential V OLB In each case, the differential voltage If they are equal, the differential voltage is detected by the capacitance CRE and a voltage of the same magnitude is generated. is input to the circuit AC, and the same result is obtained as the output signal z j (k) It can be output as As a result, the potential V OL and potential V OLB Obtain more accurate sum-of-products results independent of the magnitude of It is possible.

[0111] In particular, in the case of a hierarchical neural network, the AC circuit is an activation function circuit. Depending on the type of activation function, for example, the result of multiplying the first data and the second data When is less than or equal to "0", the output signal z j (k)outputs a digital signal with a value of "0" When the result of the multiplication and accumulation of the first data and the second data is "positive", the output signal z j (k) and A circuit that can output multiple "positive" values ​​is sufficient. For example, an analog-to-digital conversion circuit (sense amplifier, It is preferable to use a filter such as a filter divider.

[0112] In the above example, an example of use in a neural network is shown. For example, the signal from the memory cell to be read is transmitted to the wiring OL. The signal from the reference memory cell is output to the wiring OLB. Therefore, it may be used as a function to read out information stored in the memory cell to be read. That is, it can be used as DRAM, SRAM, or flash memory. For example, it may be operated as a readout of multi-value data. It can also be used as a circuit that performs calculations within the circuit, i.e., an in-memory computing circuit. good.

[0113] By the way, when the result of the sum of the products of the first data and the second data is "negative", the output signal z j (k) For example, if you want to output a "negative" multi-value as a circuit AC, Therefore, it is possible to use an analog-to-digital conversion circuit that can also sense negative voltages. In FIG. 3C, the potential of the first terminal of the capacitor CRE is not set to the GND potential, but the capacitor The potential of the first terminal of the CRE may be set to (VDD / 2). When the result of the sum of the first and second data is "zero", the circuit AC is supplied with a voltage of (VDD / 2). The result of the sum of the first and second data is not only "positive" but also Even if the voltage is very negative, if its absolute value is small, the AC circuit will be input with a positive potential. As a result, an analog-to-digital conversion circuit that can sense only positive voltages is created. It is possible to use circuits (sense amplifiers, comparators, etc.). Digital conversion circuits (sense amplifiers, comparators, etc.) operate in a manner that allows only positive input voltages. In this case, the circuit can be simplified. In other words, a negative power supply voltage is no longer required, so the voltage It is also possible to simplify the power supply circuit. In addition, a wider range of input voltage can be used, which reduces noise. This allows for a large margin for noise, enabling accurate processing.

[0114] Also, different from the above, when the result of the sum of the products of the first data and the second data is "negative", Output signal z j (k) As a method for outputting a "negative" multi-value, for example, the calculation of FIG. The circuit 110 can be changed to the calculation circuit 120 shown in FIG. By increasing the number of inputs, even if the result of the multiplication and accumulation operation is negative, only positive voltages can be sensed. Use analog-to-digital conversion circuits (sense amplifiers, comparators, etc.) where possible As an example, the arithmetic circuit 120 may be configured to calculate the capacitance CREP, the capacitance CREM, and the circuit The first terminal of the capacitor CREP is electrically connected to the terminal T1. The second terminal of the capacitor CREP is electrically connected to the terminal T2. The first terminal is electrically connected to terminal T1, and the second terminal of capacitor CREM is electrically connected to terminal T2. For example, the terminal T1 and the first terminal of the capacitance CREP (capacitance CREM) are connected. Between them, some element or circuit (for example, switch, transistor, etc.) is connected. Similarly, for example, the terminal T2 and the second terminal of the capacitance CREP (capacitance CREM) may be connected to each other. Between the terminals, some element or circuit (e.g., switch, transistor, etc.) is connected. The circuit ACP and the circuit ACM may be the same as those used in the arithmetic circuit 110 of FIG. As with AC circuits, for example, it is possible to sense positive voltages and perform analog-to-digital conversion. Circuits (sense amplifiers, comparators, etc.) are used. It is assumed that they are initialized before sensing, and the circuit ACP is the second capacitance of the capacitance CREP. The circuit ACM senses the potential of the first terminal of the capacitor CREM. In other words, the sensing terminal is changed depending on whether the capacitance is CREP or CREM. do.

[0115] 4A, the arithmetic circuit 120 changes the potential of the wiring OL to V OL and the potential of the wiring OL is V OLB As a result, the voltage between the first and second terminals of the capacitance CREP is and the voltage between the first and second terminals of the capacitor CREP is |V RE | can be used.

[0116] Here, as shown in the operation example of Figure 4B, the second terminal of the capacitance CREP and the first terminal of the capacitance CREM The first terminal of the capacitor CREP and the second terminal of the capacitor CREM are electrically floating. The second terminal may also be electrically floating), then the first terminal of the capacitor CREP and the The second terminal of the capacitor CREM and the second terminal of the capacitor CR are set to the GND potential. The potential of the second terminal of the EP is V RD The potential of the first terminal of the capacitor CREM becomes -V RD becomes First data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k -1) ~z m (k-1) When the result of the sum of products is "positive", V RD is a potential higher than 0 The first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z 1 (k-1) ~z m (k-1) When the result of the sum of products is negative, V RD is lower than 0 In other words, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the result of the sum of products is "positive", The potential of the first terminal of the capacitor CREM is -V RD is negative, so the current is No value is output (or zero is output), and the circuit ACP is connected to the second terminal of the capacitance CREP. potential V RD is positive, sensing is performed to transfer the potential V RD Depending on The first data w1 (k-1) j (k) Or even w m(k-1) j (k ) and the second data z1 (k-1) ~z m (k-1) When the result of the sum of products is negative, The circuit ACP is connected to the second terminal of the capacitor CREP at the potential V RD is negative, so the current is No output is made (or zero is output), and the circuit ACM is connected to the first terminal of the capacitor CREM. Potential of the electron -V RD Since is positive, sensing is performed to transfer the potential V RD In response The first data w1 (k-1) j (k) Or even w m (k-1) j ( k) and the second data z1 (k-1) ~z m (k-1) When the result of multiplying and accumulating is "0" , the potential of the first terminal of the capacitance CREP is the GND potential, so No potential is output (or zero is output) from the circuit ACM, and the capacitance CRE Since the potential of the second terminal of M is the GND potential, no potential is output from the circuit ACM ( otherwise, zero is printed).

[0117] Here, the potential output from the circuit ACP corresponds to the "positive" multi-value, and the potential output from the circuit ACM corresponds to the "positive" multi-value. By making the input potential correspond to multiple negative values, it is possible to sense only positive voltages. When using analog-to-digital conversion circuits (sense amplifiers, comparators, etc.), However, even if the result of the sum of the first and second data is negative, the output signal z j (k) As for the circuit AC, in Fig. 4, , an example in which the circuit ACP and the circuit ACM are included has been shown, but one aspect of the present invention is to The circuit ACP and the circuit ACM are only the circuit AC, and the circuit AC is sensed twice. In other words, the operation of the circuit AC may be divided into two parts and operated in a time-division manner. This increases the processing time, but reduces the circuit size. .

[0118] <Configuration example 2 of arithmetic circuit> Next, a specific example of the circuit configuration of the circuit ACTF[j] will be described. j] can have the circuit configuration shown in FIG. 5 as an example. The signal z is generated according to the current input from the line OL[j] and the wiring OLB[j]. j (k) Generate Specifically, FIG. 5 shows a circuit that outputs a multi-valued or analog signal. z j (k) This shows an example of an arithmetic circuit that outputs the following. Therefore, the circuit ACTF[j] is As an example, a structure having a function as an activation function circuit in a neural network is In addition, in FIG. 5, the electrical connection between the circuit ACTF[j] and the surrounding circuits is shown. To show the connection configuration, the array portion ALP and the circuit AFP are also shown.

[0119] The circuit ACTF[j] shown in FIG. 5 is, for example, a switch SWR1 and a switch SWR 1B, switch SWR2, switch SWR2B, circuit IVTR, and circuit IVTRR. , a capacitance CRE, and a circuit AC.

[0120] Switch SWR1, switch SWR1B, switch SWR2, and switch SWR2B For example, each of these can be an electrical switch such as an analog switch or a transistor. The switches SWR1, SWR1B, and At least one of the switches SWR2 and SWR2B may be implemented by, for example, a transistor. In this case, the transistor can be used as a CRET transistor. In addition to the electrical switch, a mechanical switch may also be used. stomach.

[0121] The circuit IVTR is electrically connected to the terminal T1 and to the first terminal of the switch SWR1. The second terminal of the switch SWR1 is connected to the first terminal of the capacitor CRE and the first terminal of the switch SWR2. The second terminal of switch SWR2 is electrically connected to wiring VCN3. The circuit IVTRr is electrically connected between the terminal T2 and the first terminal of the switch SWR1B. The second terminal of the switch SWR1B is electrically connected to the second terminal of the capacitor CRE. The switch SWR2B is electrically connected to the terminal and the first terminal of the switch SWR2B. The second terminal of 2B is electrically connected to terminal mbt1 of circuit AC.

[0122] The wiring VCN3 functions as a wiring that applies a constant voltage. The constant voltage may be, for example, It can be a ground potential GND or a low level potential. (high level potential).

[0123] The circuit AC has a terminal mbt1 and a terminal mbt2. As shown in FIG. 5, an example of the circuit is an analog-to-digital converter. The circuit AC senses the potential applied to the terminal mbt1 and outputs it as a digital signal to the terminal The output signal z from mbt2 corresponds to the potential. j (k) Therefore, For example, the circuit AC is an analog-to-digital converter that converts a signal into a 1-bit digital signal. In this case, there is one terminal mbt2, and for example, the circuit AC is k-bit (k is an integer greater than or equal to 2). ) is converted into a digital signal, terminal m The number of bt2 is k. Note that in FIG. 5, the terminal mbt2 is illustrated as a plurality of terminals. As an example, the circuit AC performs analog-to-digital conversion based on a plurality of predetermined potentials. The analog potential (or multi-level digital value) of the terminal mbt1 is converted into a digital signal. and output it.

[0124] In particular, the circuit ACTF[j] in Fig. 5 is a neural network When applying the activation function of Ron as a circuit, for example, the circuit AC is converted into an analog-to-digital converter. In the case where the potential of the terminal mbt1 of the circuit AC is lower than the potential given by the wiring VCN3, If the result of multiplying the first data and the second data is negative, the value is output. By configuring the circuit to output zero instead of the step function, It can operate as a circuit that outputs a value.

[0125] The circuit IVTR converts the current flowing through the wiring OL[j] into a voltage value (or charge amount). The circuit IVTRr converts the current flowing through the wiring OLB[j] into a voltage A circuit having a function of converting a voltage into a value (or charge amount) and having the same configuration as the circuit IVTR. As a result, in the circuit ACTF[j] of FIG. 5, the circuit IVTR The current flowing through the wiring OL[j] is converted into a voltage value (or charge amount), and the voltage value is switched. The first terminal of the SWR1 can be connected to the circuit IVT R, and the current flows to the wiring OLB[j]. The current flowing through the switch SWR1B is converted into a voltage value (or charge amount), and the voltage value is applied to the first terminal of the switch SWR1B. can be given to a child.

[0126] The circuit IVTR (circuit IVTRr) has the circuit configuration shown in, for example, FIGS. 6A to 6C. In order to distinguish between the circuit IVTR and the circuit IVTRr, the circuit In C, the symbols for the wiring OLB[j] and the circuit elements included in the circuit IVTRr are written in parentheses. is doing.

[0127] The circuit IVTR (circuit IVTRr) shown in FIG. 6A is a switch SWR3 (switch SWR 3B) and a capacitance CRT (capacitance CRTB). ]) is connected between the first terminal of the switch SWR3 (switch SWR3B) and the capacitor CRT (capacitor CR TB) and the first terminal of switch SWR3 (switch SWR3 The second terminal of B) is electrically connected to the second terminal of the capacitor CRT (capacitor CRTB) and the wiring VCN4. is connected.

[0128] The switches SWR3 and SWR3B may be, for example, the switches Switch SWR1, Switch SWR1B, Switch SWR2, and Switch SWR2B Any applicable switch can be used.

[0129] The wiring VCN4 functions as a wiring that applies a constant voltage, for example. can be, for example, a high level potential, a ground potential, or a low level potential. In other words, the wiring VCN4 may be given the same potential as that of a wiring VSO, which will be described later. For example, the wiring VCN4 may be electrically connected to the wiring VSO. The wiring VCN4 and the wiring VSO may be combined into one wiring.

[0130] The circuit IVTR (circuit IVTRr) shown in FIG. 6A is a switch SWR3 (switch SWR 3B) to the ON state, the wiring OL[j] (wiring OLB[j]) and wiring VCN4 The wiring OL[j] (wiring OLB[j]) can be connected to wiring VCN4 A constant voltage of VCN4 can be applied to the wiring OL[j] (wiring OLB[j]). The operation of applying a constant voltage is performed by receiving information (current, voltage) from the circuits MP[1,j] to MP[m,j]. This corresponds to the initial operation for reading out the voltage, etc. This corresponds to the operation of initializing the accumulated charge. By turning off the switch SWR3 (switch SWR3B), The amount of current flowing through the wiring OL[j] (wiring OLB[j]) is used as charge and is the first terminal of the capacitance CRT. That is, the potential of the first terminal of the capacitor CRT is It is determined according to the amount of current flowing through the line OLB[j].

[0131] In addition, the amount of current flowing through the wiring OL[j] (wiring OLB[j]) is, for example, [1,j] to the circuit MP[m,j] and the wiring OL[j] (wiring OLB[j]) Therefore, the sum of the currents in the circuits MP[1,j] to MP[m,j ] and wiring OL[j] (wiring OLB[j]) for a certain period of time. By draining the charge from the first terminal of the capacitor CRT, the charge stored in the first terminal of the capacitor CRT is ] (wiring OLB[j]) and the certain time. The circuit IVTRr (circuit IVTRr) is connected to the first terminal of the switch SWR1 (switch SWR1B). The voltage applied to the element is determined by the amount of current flowing through each of the circuits MP[1,j] to MP[m,j]. It is determined by time.

[0132] By the way, the parasitic resistance or parasitic capacitance of the wiring OL[j] (wiring OLB[j]) When the current flowing through the wiring OL[j] (wiring OLB[j]) is converted into a voltage, the circuit I The VTR (circuit IVTRr) can have the circuit configuration shown in FIG. 6B. In the circuit IVTR (circuit IVTRr) of A, the capacitance CRT (capacitor CRTB) can be omitted. This can be done.

[0133] The circuit IVTR (circuit IVTRr) shown in FIG. 6C is a circuit diagram of a switch SWR3 (switch SWR 3B) and resistor RRT (resistor RRTB). ]) is the first terminal of the switch SWR3 (switch SWR3B) and the resistor RRT (resistor RR TB) and the first terminal of switch SWR3 (switch SWR3 The second terminal of B) is electrically connected to the second terminal of resistor RRT (resistor RRTB) and wiring VCN4. is connected.

[0134] The circuit IVTR (circuit IVTRr) shown in FIG. 6C is a circuit diagram of a switch SWR3 (switch SWR 3B) to the ON state, the wiring OL[j] (wiring OLB[j]) and wiring VCN4 The wiring OL[j] (wiring OLB[j]) can be connected to wiring VCN4 A constant voltage of VCN4 can be applied to the wiring OL[j] (wiring OLB[j]). The operation of applying a constant voltage is performed by receiving information (current, voltage) from the circuits MP[1,j] to MP[m,j]. This corresponds to the initial operation for reading out the voltage, etc. IVTRr) is distributed by turning switch SWR3 (switch SWR3B) off. The amount of current flowing through the line OL[j] (wiring OLB[j]) is This current flows to the wiring VCN4 via the resistor RRT (resistor RRTB) and not via the resistor R3B. When the resistor RRT (resistor RRTB) is turned on, the resistor RRT (resistor RRTB) is turned on. A voltage is generated according to the resistance value of the capacitor CRT (RRTB) and the amount of current. The potential of terminal 1 is determined by the amount of current flowing through the wiring OL[j] (wiring OLB[j]) and the resistance RRT( The resistance of the switch SWR3 (switch S WR3B) is not necessarily provided.

[0135] Next, we will introduce the ACTF[j] circuit in Figure 2, which is different from the ACTF[j] circuit in Figure 5. An example of the circuit configuration will be described.

[0136] The circuit ACTF[j] shown in FIG. 7A is a modified version of the circuit ACTF[j] shown in FIG. 5. This is a configuration example. Specifically, the second terminal of the switch SWR2 is connected to the terminal mbt of the circuit AC. 1 is electrically connected, and the wiring VCN3 is electrically connected to the second terminal of the switch SWR2B. This circuit differs from the circuit ACTF[j] in FIG. 5 in that

[0137] As a circuit configuration applicable to the circuit ACTF[j] in FIG. 2, for example, the circuit shown in FIG. 7B The circuit ACTF[j] in FIG. 7B can be a circuit ACTF[j] that switches the switch S WR2, switch SWR2B, switch SWR6, switch SWR6B, and switch Switch SWR7, switch SWR7B, capacitor CRE, circuit IVTR, and circuit IVTRR and a circuit AC.

[0138] The first terminal of the switch SWR6 is electrically connected to the terminal T1, and the third terminal of the switch SWR6 is electrically connected to the terminal T2. The two terminals are the first terminal of the switch SWR7, the first terminal of the switch SWR2, and the capacitance CRE The second terminal of the switch SWR7 is electrically connected to the first terminal of the circuit IVT The second terminal of switch SWR2 is electrically connected to wire VCN3. The first terminal of the switch SWR6B is electrically connected to the terminal T2, and the switch SW The second terminal of R6B is the first terminal of switch SWR7B and the first terminal of switch SWR2B. and the second terminal of the capacitor CRE. The terminal of the switch SWR2B is electrically connected to the circuit IVT R, and the second terminal of the switch SWR2B is electrically connected to the circuit AC. are electrically connected.

[0139] Switch SWR6, switch SWR6B, switch SWR7, and switch SWR7B For example, the above-mentioned switches SWR1, SWR1B, and Switch SWR2 and switch SWR2B can be used as applicable switches. .

[0140] For each of the circuit AC, the circuit IVTR, and the circuit IVTRr, Please refer to the explanation of the circuits AC, IVTR, and IVTRr included in TF[j]. do.

[0141] In addition, as a circuit configuration that can be applied to the circuit ACTF[j] in FIG. 2A, for example, The circuit ACTF[j] in FIG. 7C can be the circuit ACTF[j] shown in FIG. The circuit ACTF[j] does not have the switch SWR7 and the switch SWR2B. That is, in the circuit ACTF[j] of FIG. 7C, the second terminal of the switch SWR6 is electrically connected to the circuit IVTR, and the terminal mbt1 of the circuit AC is connected to the second terminal of the capacitance CRE. the second terminal of switch SWR6B and the first terminal of switch SWR7B. is connected.

[0142] 7A to 7C is replaced with the circuit ACTF[j] of FIG. By applying this, the first data and the second data are obtained in the same manner as the circuit ACTF[j] in FIG. As a result of the sum of products of j (k) can be output.

[0143] <Operation example 2 of the arithmetic circuit> Next, an example of the operation of the circuit ACTF[j] in FIG. As an example, the arithmetic circuit 110A shown in FIG. 8 is used. The arithmetic circuit 110A is The circuit ACTF[j] shown in FIG. 6A includes the circuits IVTR and IVTRr. This configuration applies the circuit IVTR (circuit IVTRr).

[0144] FIG. 8 also shows, as an example, a switch SWR1 included in the circuit ACTF[J]. Switch SWR2, Switch SWR3, Switch SWR1B, Switch SWR2B, Switch The wiring for switching the SWR3B between on and off is as follows: The wiring SRL1, wiring SRL2-1, wiring SRL2-2, and wiring SRL3 are shown. Specifically, the wiring SRL1 is connected to the control terminal of the switch SWR1 and the control terminal of the switch SWR1B. The wiring SRL2-1 is electrically connected to the control terminal of the switch SWR2. The wire SRL2-2 is electrically connected to the control terminal of the switch SWR2B. The wiring SRL3 is connected to the control terminal of the switch SWR3 and the control terminal of the switch SWR3B. , are electrically connected to the switches SWR1, SWR2, and Switch SWR3, Switch SWR1B, Switch SWR2B, or Switch SWR3 B may omit some of them depending on the circumstances. That is, for example, switch SWR1, switch SWR2, switch SWR1B, switch The SWR2B is designed so that some of these switches are always on. Alternatively, for example, by using another switch, the switch SWR3 , switch SWR3B is in a circuit where some of these switches are always in the off state. Alternatively, for example, the switch SWR1, the switch SWR2, the switch Switch SWR3, switch SWR1B, switch SWR2B, and switch SWR3B are connected It is also possible to change a part of the configuration. For example, the wiring SRL1, wiring SRL2- 1. Wiring SRL2-2 or wiring SRL3 may be For example, the wiring SRL2-1 and the wiring SRL2- 2 can be combined into one wire. By reversing the on / off polarity of switch SWR2 (switch SWR2B), wiring SR It is okay to combine L1 and wiring SRL2-1 (wiring SRL2-2) into one wiring. This allows you to connect the switch SWR1 and switch SWR2 (switch SWR 2B) can be turned on and off alternately.

[0145] FIG. 8 also shows a first terminal of the switch SWR1, a first terminal of the capacitor CRT, and a Node n4 is shown as an electrical connection point between the first terminal of switch SWR3 and the second terminal of switch SWR1. B, the first terminal of the capacitor CRTB, and the first terminal of the switch SWR3B. The node n4r is shown as a connection point. The first terminal of the capacitor CRE and the first terminal of the switch SWR2 are electrically connected to each other. The second terminal of the switch SWR1B, the second terminal of the capacitor CRE, and the A node n5r is shown as an electrical connection point with the first terminal of SWR2B.

[0146] FIG. 9 is a timing chart showing an example of the operation of the circuit ACTF[j] of the arithmetic circuit 110A of FIG. The timing chart shows the period from time T01 to time T08 and the period thereafter. In the vicinity of the wiring XLS[1] to the wiring XLS[m], the wiring SRL1, and the wiring SRL2 -1, wiring SRL2-2, wiring SRL3, node n4, node n4r, node n5, The figure shows the fluctuation of the potential of the node n5r. and low indicates a low level potential.

[0147] In this operation example, the switches SWR1, SWR2, and SWR1B and switch SWR2B are turned on when a high-level potential is input to the control terminal. When a low-level potential is input to the control terminal, the transistor is in the ON state, and when a low-level potential is input to the control terminal, the transistor is in the OFF state.

[0148] The timing chart of FIG. 9 shows the wirings XLS[1] to XLS[m] collectively. In the timing chart of FIG. 9, the wiring XLS[1] to the wiring XLS The period in which the second data is input is indicated by hatching in [m].

[0149] In this example, current flows from the wiring OL[j] to the circuit MP, and current flows from the wiring OLB[ j] to the circuit MP. Therefore, the circuit MP has VSS (low level The wiring that provides the potential) (for example, the wiring VE and wiring VEr described in the second embodiment) 8) are electrically connected (not shown in FIG. 8) and the wiring VC The constant voltage given by N4 is VDD (high level potential). The amount of current flowing through P and the amount of current flowing from wiring OLB[j] to circuit MP are stored in circuit MP. It is determined by the first data stored in the device and the second data input from the wiring XLS. , the amount of current flowing from the wiring OL[j] to the circuit MP, and / or the amount of current flowing from the wiring OLB[j] to the circuit M The amount of current flowing through P may be zero. Also, the constant voltage provided by the wiring VCN3 is Let's call it S.

[0150] Before time T01, each of the circuits MP[1,j] to MP[m,j] is the first data, and the weighting coefficient w1 (k-1) j (k) Or even w m(k-1) j (k) Guaranteed It is assumed that the information is held.

[0151] Also, before time T01, the wirings XLS[1] to XLS[m] are connected to low-level A bell potential is input, and the wiring SRL1, the wiring SRL2-1, the wiring SRL2-2, and the wiring S A low level potential is input to RL3. The potentials of the node n5 and the node n5r are set to VSS.

[0152] Between time T01 and time T02, the wiring SRL1 and the wiring SRL3 are When a high level potential is input to the wiring SRL1, Switch SWR1 and switch SWR1B are turned on, and a high-level potential is applied to wiring SRL3. When this signal is input, the switches SWR3 and SWR3B are turned on. .

[0153] In addition, between time T01 and time T02, the wiring SRL2-1 and the wiring SR A low level potential is input to the wiring SRL2-1 and the wiring SRL2-2. When a level potential is input, the switches SWR2 and SWR2B are turned on. It becomes a non-operational state.

[0154] As a result, the first The wiring VCN4 and the wiring OLB[j] are in a conductive state. There is a continuity between CN4 and the second terminal of the capacitor CRE, and between the wiring VCN4 and the terminal mbt1. Also, there is no conduction between the wiring VCN3 and the first terminal of the capacitor CRE. , the potentials of the nodes n4, n4r, n5, and n5r are VD It becomes D.

[0155] Between time T02 and time T03, a low-level potential is input to the wiring SRL3. When a low-level potential is input to the wiring SRL3, the switches SWR3 and SWR4 are turned on. Therefore, the line VCN4 and the line OL[j] are connected to each other. This results in a non-conducting state, and the line VCN4 and the line OLB[j] are in a non-conducting state. The nodes n4, n5, n4r, and n5r are in a floating state.

[0156] Between time T03 and time T04, the circuit MP[1,j] of the array unit ALP For each of the circuits MP[m,j], the neuron signal z1 is used as the second data. (k -1) ~z m (k-1) will be sent.

[0157] As a result, in the circuit MP[i,j], the weight coefficient w i (k-1) j (k) Tonew Ron's signal z1 (k-1) Depending on the wiring, either wiring OL[j] or wiring OLB[j] is connected. A current flows between the wiring OL[j] or wiring OLB[j] and the circuit MCr. Here, a current flows between each of the circuits MP[1,j] to MP[m,j]. The total current flowing between the wiring OL[j] and out [j], and the circuit MP[1,j] The sum of the currents flowing between each of the circuits MP[m,j] and the wiring OLB[j] is I Bo ut Let's say [j].

[0158] At this time, the potentials of the nodes n4 and n5 are changed by the current flowing through the wiring OL[j]. The potentials of the nodes n4r and n5r decrease as the current flowing through the wiring OLB[j] decreases. It decreases by

[0159] In this example, I Bout I rather than [j] out Let [j] be large. Therefore, the potentials of the nodes n4 and n5 between time T03 and time T04 The decrease in the potential of the node n4r is larger than the decrease in the potential of the node n5r. In the timing chart, at time T04, the potentials of the nodes n4 and n5 are V I out The potential V IBout Decreased to It states that:

[0160] At time T04, a low-level potential is input to the wiring SRL1. When a low-level potential is input to switch SWR1 and switch SWR1B, Therefore, there is no conduction between the first terminal of the capacitor CRE and the line OL[j]. This results in a non-conductive state between the second terminal of the capacitor CRE and the wiring OLB[j]. Therefore, the potential at the first terminal (node ​​n5) of the capacitor CRE stops decreasing, and the potential at the first terminal (node ​​n6) of the capacitor CRE stops decreasing. The potential at the second terminal (node ​​n5r) of the capacitor CRE stops decreasing. The voltage between the second terminal (node ​​n5) of the capacitor CRE and the second terminal (node ​​n5r) of the capacitor CRE is maintained. The potentials of the node n4 and the node n4r continue to decrease from before time T04.

[0161] Between time T05 and time T06, the wiring XLS[1] to the wiring XLS[m] As a result, a low level potential is input to each of the circuits MP[1, j] to the circuit MP[m,j], the signal of the neuron according to the second data z1 (k-1) ~z m (k-1) This stops the supply of power from the wiring OL[j]. The current flowing from wiring OLB[j] to circuit MP stops, and the current flowing from wiring OLB[j] to circuit MP stops. Therefore, the potentials of the nodes n4 and n4r stop decreasing.

[0162] Between time T06 and time T07, a high-level potential is input to the wiring SRL2-1. When a high-level potential is input to the wiring SRL2-1, the switch SWR 2 is turned on. Therefore, a state of conduction is established between the first terminal of the capacitor CRE and the wiring VCN3. As a result, the potential of the first terminal (node ​​n5) of the capacitor CRE becomes VSS.

[0163] By the way, since the second terminal (node ​​n5r) of the capacitor CRE is in a floating state, The potential of the first terminal (node ​​n5) of the capacitor CRE is V Iout The change from VSS to Therefore, the potential of the second terminal (node ​​n5r) of the capacitor CRE also changes due to capacitive coupling. The amount of change in potential due to capacitive coupling is determined according to the capacitive coupling coefficient. To explain it simply, let us assume that the potential of the first terminal of the capacitor CRE is V Iout When it changes from , the potential of the second terminal of the capacitor CRE is V IBout -(V Iout -VSS) (Figure 9 In the timing chart, V OPIn other words, this change in potential is , which corresponds to the case where the capacitance coupling coefficient determined depending on the capacitance CRE and the surrounding circuit elements is set to 1. .

[0164] Between time T07 and time T08, a high-level potential is input to the wiring SRL2-2. When a high-level potential is input to the wiring SRL2-2, the switch SWR 2B is turned on. Therefore, the second terminal (node ​​n5r) of the capacitor CRE and the terminal mbt 1 is in a conductive state.

[0165] At this time, the potential of the second terminal (node ​​n5r) of the capacitor CRE is applied to the terminal mbt1 of the circuit AC. V OP is entered.

[0166] As a result, the circuit AC is at the potential V input to the terminal mbt1. OP Digital signal according to As, z j (k) A signal with a value of is output.

[0167] z j (k) is the potential V according to the amount of current flowing through the wiring OL[j] Iout and wiring OLB [j] corresponds to the amount of current flowing through IBout The value output based on the potential difference between In other words, the potential V Iout , potential V IBout I out [j] and I Bout [ j] and the time when the switches SWR1 and SWR2 are in the on state (time T0 (the time from time T03 to time T04) and out [j] and I Bout [j] is the first number stored in each of the circuits MP[1,j] to MP[m,j]. The first data w1 (k-1) j (k) Or even w m (k-1) j (k) and circuit M The value z1 of the signal which is the second data input to the circuits P[1,j] to MP[m,j] (k- 1) ~z m (k-1) The result of the multiplication and addition operation of and, that is, u in equation (1.2) j (k) Depending on On the other hand, the potential V Iout , potential V IBout switch SWR1 and switch Depending on the time that switch SWR2 is in the on state (the time from time T03 to time T04), Since this time varies depending on the AC power supply, it is preferable that the time be set appropriately according to the AC power supply. .

[0168] In this example, the current amount I out [j] and I Bout [j] are converted into potentials. In other words, when the potential difference between them is input to the AC circuit, z j (k) The value of is output. In other words, the AC circuit is the activation function circuit in a hierarchical neural network. By doing so, the z output as a digital signal j (k) The value of z in equation (1.4) j (k ) The potential can be set to a value corresponding to:

[0169] By the way, between time T07 and time T08, switch SWR2B is in the ON state. At this stage, strictly speaking, taking into consideration the effects of parasitic resistance and parasitic capacitance, the The potential input to t1 is V OP In this case, the circuit AC may vary from Considering the resistance of the wiring between the second terminal of RE and terminal mbt1, It is preferable that the device is designed to appropriately correct the potential that occurs.

[0170] In addition, in the above example, I Bout I rather than [j] out Explain the case when [j] is large On the other hand, I out I rather than [j] Bout When [j] is large, at time T04 , the potential V of node n5 Iout The potential of node n5r is V IBout This Therefore, between time T06 and time T07, switch SWR2 is in the on state. When this happens, the potential of node n5r becomes lower than VSS due to the capacitive coupling of the capacitor CRE. Between time T07 and time T08, VSS is applied to the terminal mbt1. At this time, as the configuration of the circuit AC, for example, the terminal mbt2 Output signal z j (k) It may be configured to output a digital signal corresponding to 0 as a result. is the activation function f(u j (k) ) but u j (k ) is equivalent to functioning as a ramp function that outputs 0 when is negative.

[0171] <Configuration example 3 of an arithmetic circuit> Note that one embodiment of the present invention is a circuit configuration of the circuit ACTF[j] in FIG. 5 included in the arithmetic circuit. For example, the semiconductor device (arithmetic circuit) of one embodiment of the present invention may include The circuit ACTF[j] in Fig. 5 can be changed to the circuit configuration shown in the circuit ACTF[j] in Fig. 10. The circuit ACTF[j] in FIG. 10 is composed of switches SWR1 and SWR1B. , switch SWR2, switch SWR2B, switch SWR3, switch SWR3 B, switch SWR4, switch SWR4B, load LE, load LEB, and op amp The circuit AC shown in FIG. The explanation of the parts that overlap with F[j] will be omitted.

[0172] Switch SWR3, switch SWR3B, switch SWR4, switch SWR4B For example, switch SWR1, switch SWR1B, switch SWR2, and can be a switch that can be applied in the same manner as switch SWR2B.

[0173] The first terminal of switch SWR3 is connected to terminal T1, the first terminal of switch SWR4, and the load L The second terminal of the switch SWR3 is electrically connected to the first terminal of the wiring VC The non-inverting input terminal of the operational amplifier OP is electrically connected to the Vref1L wire. The inverting input terminal of the operational amplifier OP is electrically connected to the second terminal of the switch SWR4. The output terminal of the operational amplifier OP is electrically connected to the second terminal of the load LE and the second terminal of the switch SW. The first terminal of R1 is electrically connected to the first terminal of R2.

[0174] The first terminal of switch SWR3B is connected to terminal T2, the first terminal of switch SWR4B, and the negative The first terminal of the switch SWR3B is electrically connected to the first terminal of the load LEB. The non-inverting input terminal of the operational amplifier OPB is electrically connected to the wiring V The inverting input terminal of the operational amplifier OPB is electrically connected to ref2L. The output terminal of the operational amplifier OPB is electrically connected to the second terminal of the load LEB. and a first terminal of the switch SWR1B.

[0175] The wiring Vref1L and the wiring Vref2L may have the same voltage or different voltages. Therefore, the wiring Vref1L and wiring Vref2 L can sometimes be combined into a single wire.

[0176] The circuit ACTF[j] in FIG. 10 turns on the switch SWR3 (switch SWR3B). and switch SWR4 (switch SWR4B) is turned off. Similarly, the initial operation of applying a constant voltage of the wiring VCN4 to the wiring OL[j] (wiring OLB[j]) It is possible to perform the work.

[0177] In the circuit ACTF[j] of FIG. 10, the loads LE and LEB are, for example, resistors In particular, by using capacitance as the load LE and the load LEB, Therefore, the operational amplifier OP and the load LE, and the operational amplifier OPB and the load LEB are the integral circuits, respectively. In other words, the switches SWR3 and SWR3B are turned off, and the By turning on the switch SWR4 and the switch SWR4B, the wiring OL[j] and Depending on the amount of current flowing through the wiring OLB[j], the capacitance of each (load LE, load LEB ) charges are stored. In other words, the current flowing from wiring OL[j] and OLB[j] is expressed as the integral The circuit converts these voltages into voltages, and the voltages are the operational amplifiers OP and OPB. It is output from the output terminal.

[0178] By using the loads LE and LEB as capacitances, the circuit ACTF[j] in FIG. The amount of charge flowing through the line OL[j] is converted into a voltage value, and the voltage value is applied to the first The charge flowing through the wiring OLB[j] can be converted into a voltage value. This voltage value can be applied to a first terminal of switch SWR1B.

[0179] The circuit ACTF[j] in FIG. 5 has the same circuit configuration as the circuit ACTF[j] in FIG. 11A. The circuit ACTF[j] in FIG. 11A includes a switch SWR3 and a switch Switch SWR3B, switch SWR4, switch SWR4B, switch SWR5, and negative The load LEA, the load LEAB, the operational amplifier OPA, and the circuit AC.

[0180] Switch SWR3, Switch SWR3B, Switch SWR4, Switch SWR4B, Switch For example, the switches SWR1, SWR1B, It can be used as a switch similar to the switch SWR2 and switch SWR2B. Cut.

[0181] The first terminal of switch SWR3 is connected to terminal T1, the first terminal of switch SWR4, and the load L The first terminal of the switch SWR3 is electrically connected to the wiring V The inverting input terminal of the operational amplifier OP is electrically connected to the switch SWR4. The second terminal of the load LEA is electrically connected to the first terminal of the switch SWR5. The first terminal of switch SWR3B is electrically connected to terminal T2 and the second terminal of switch SWR3B. The first terminal of the switch SWR4B and the first terminal of the load LEAB are electrically connected to each other. The second terminal of the switch SWR3B is electrically connected to the wiring VCN4. The non-inverting input terminal of OP is electrically connected to the second terminal of switch SWR4B. The second terminal of the load LEAB is electrically connected to the wiring VCN5. The power terminal is electrically connected to the second terminal of the switch SWR5 and to the terminal mbt1 of the circuit AC. It has been done.

[0182] The wiring VCN5 functions as a wiring that applies a constant voltage. For example, it may be a ground potential or a low-level potential.

[0183] The circuit ACTF[j] in FIG. 11A turns on the switch SWR3 (switch SWR3B). switch SWR4 (switch SWR4B) to the OFF state, and switch SWR5 to By turning it off, the same as in Figure 10, An initial operation can be performed to apply a constant voltage to the wiring VCN4.

[0184] In the circuit ACTF[j] of FIG. 11A, the loads LEA and LEAB are, for example, , resistor, capacitance, etc. Also, a subtraction circuit can be constructed using an operational amplifier (OPA). In this case, resistors can be used as the loads LEA and LEAB. A, by using a resistor for the load LEAB, the first terminal and second terminal of the load LEA and the negative The voltage corresponding to the difference between the first and second terminals of the load LEAB and the current flowing through This allows the output from the OPA output terminal. Turn SWR3B off, turn on switch SWR4 and switch SWR4B, By turning on the switch SWR5, the The voltage corresponding to the difference in the current flowing through each of them is output from the output terminal of the operational amplifier OPA. can be done.

[0185] In addition, the voltage output from the output terminal of the operational amplifier OPA is input to the input terminal of the circuit AC. This allows the analog voltage output from the output terminal of the operational amplifier OPA to be C can be converted into a digital signal. The calculated value of Ron's signal z j (k) As a result, AC can be output from terminal mbt2 of the circuit. do.

[0186] Also, the circuit configuration of the circuit ACTF[j] in FIG. 11A is changed to the circuit ACTF in FIG. 11B. The circuit ACTF[j] in FIG. 11B may be the circuit ACTF[j] in FIG. 11A. This configuration does not include a circuit AC at the output terminal of the operational amplifier OPA. The analog voltage output from the neuron is converted into the calculated value z j (k) It is possible to Cut.

[0187] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0188] (Embodiment 2) In this embodiment, the arithmetic circuit 110, the arithmetic circuit 110A, The peripheral circuit configuration of the arithmetic circuit 120 and an example of the operation of the arithmetic circuit will be described. .

[0189] <Configuration example 1 of an arithmetic circuit> The arithmetic circuit 130 shown in FIG. 12 includes, for example, an array section ALP, a circuit ILD, and a circuit The semiconductor device includes a circuit WLD, a circuit XLD, and a circuit AFP. , the k-th layer neuron N1 in Figures 1A and 1B (k) Neuron N n (k) to Input signal z1 (k-1) ~z m (k-1) and neuron N1 (k) No To Neuron N n (k) The signal z1 output from each (k) ~z n (k) Generate This is a circuit that:

[0190] In addition, the entire arithmetic circuit 130 or a part thereof may be implemented as a neural network or It may be used for purposes other than AI, such as graphics calculations or scientific calculations. In the case of performing sum-of-products calculation or matrix calculation, the entire calculation circuit 130 or In other words, it can be used not only for AI calculations but also for general For practical calculations, the entire arithmetic circuit 130 or a part thereof may be used. For example, the entire arithmetic circuit 130 or a part of it may be used for a storage device or the like. Good too.

[0191] The circuit ILD includes, for example, wirings IL[1] to IL[n] and wirings ILB[1]. The circuit WLD is electrically connected to the wirings WL[n] to ILB[n]. The circuit XLD is electrically connected to wirings S[1] to WLS[m]. The circuit AFP is electrically connected to the wiring XLS[1] to the wiring XLS[m]. The wiring OL[1] to wiring OL[n], the wiring OLB[1] to wiring OLB[n], is electrically connected to

[0192] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. are arranged in a matrix of m rows and n columns in the array section ALP. In FIG. 12, the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) The circuit MP located at i,j is expressed as circuit MP[i,j]. In 2, circuit MP[1,1], circuit MP[m,1], circuit MP[i,j], circuit MP[1 ,n] and circuit MP[m,n] are shown in the figure.

[0193] For example, the circuit MP[i,j] includes a wiring IL[j], a wiring ILB[j], and a wiring W LS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j] are electrically is connected to.

[0194] The circuit MP[i,j] is, for example, the circuit MP[1,j] described in the above embodiment. ] to the circuit MP[m,j]. Furthermore, the circuit MP[i,j] has the same function as the circuit M The weight coefficient (first data) held in P[i,j] is used for the wiring IL[j] and wiring ILB[ j]. In FIG. 12, the wiring IL[j] and the wiring ILB[j ] is arranged, one embodiment of the present invention is not limited to this. Only one of the wiring IL[j] and the wiring ILB[j] may be arranged.

[0195] The circuits MP[1,1] to MP[m,n] will be described in detail later. .

[0196] <<Circuit XLD>> The circuit XLD in FIG. 12 is, for example, , for each of the circuits MP[1,1] to MP[m,n], neuron N1 (k -1) Neuron N m (k) z1, the calculated value output from (k-1) ~z m ( k-1) (It may be called first data or second data. Here, we will use second data.) Specifically, the circuit XLD has a function of supplying the circuits MP[i,1] to MP[i,1]. For MP[i,n], neuron N i (k-1) The second data z output from i (k -1) The corresponding information (e.g., potential, current value, etc.) is supplied by the wiring XLS[i]. Although an example in which the wiring XLS[i] is arranged is shown, one embodiment of the present invention is For example, in the arithmetic circuit 130 of FIG. 12, the wiring XLS[i] is A plurality of wires may be used.

[0197] <<Circuit WLD>> The circuit WLD in FIG. 12 is, for example, a circuit for calculating a weighting coefficient (first data In this case, it is referred to as the first data.) It has the function of selecting the circuit MP to which data (e.g., potential, resistance, current, etc.) is written. For example, the circuits MP[i,1] to MP[i,n] located in the i-th row of the array unit ALP When writing information (for example, potential, resistance, current, etc.) to the For example, the write switching elements included in the circuits MP[i,1] to MP[i,n] A signal for turning on or off the element is supplied to the wiring WLS[i], and all the elements except the i-th row are turned on or off. The potential for turning off the write switching element included in the circuit MP is applied to the wiring WLS. Although an example in which the wiring WLS[i] is arranged has been shown, In addition to the wiring WLS[i], for example, the wiring WLS[i] A wiring for transmitting an inverted signal of the signal input to the WLS[i] may be replaced with multiple wirings. Note that the circuit WLD is connected to the circuit XLD. The circuit may be arranged as a separate circuit, but one embodiment of the present invention is not limited to this. For example, the circuit WLD may be integrated into the circuit XLD.

[0198] <<Circuit AFP>> The circuit AFP in FIG. 12 includes, for example, circuits ACTF[1] to ACTF[n]. The circuits ACTF[1] to ACTF[n] are, for example, the circuits ACTF[1] to ACTF[n] shown in the above embodiment. The circuit ACTF[j] described in can be applied. This allows the circuit ACTF[1 ] to the circuit ACTF[n], for example, input from the wiring OL[j] and the wiring OLB[j]. It is possible to generate signals corresponding to the respective information (for example, potential, current value, etc.) For example, the information input from wiring OL[j] and wiring OLB[j] ( For example, potential, current value, etc.) and generate a signal according to the comparison result. is a neuron N j (k) The signal z output from j(k) That is, the AC circuit TF[1] to ACTF[n] are, for example, the neural network It functions as a circuit that calculates the activation function.

[0199] <<Circuit MP>> Here, an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 130 will be described.

[0200] FIG. 13A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 130. The circuit MP[i,j] includes, for example, a circuit MC and a circuit MCr. The circuit MCr is a circuit for calculating the product of the first data and the second data in the circuit MP. The circuit MC may have the same configuration as the circuit MCr or a different configuration from the circuit MCr. Therefore, the circuit MCr has an "r" added to its symbol to distinguish it from the circuit MC. The circuit elements included in the circuit MCr, which will be described later, also have the letter "r" attached to their reference symbols. There are.

[0201] For example, the circuit MC has a holding unit HC, and the circuit MCr has a holding unit HCr. The holding unit HC and the holding unit HCr each store information (for example, potential, resistance value, current value, etc.) ) is stored in the circuit MP[i,j]. i (k -1) j (k) is the information (for example, , potential, resistance value, current value, etc.). Each of the first data w i (k-1) j (k)Each piece of information (e.g., potential, Resistance value, current value, etc.) are supplied to the wiring OL[j] and wiring OLB[j]. It is being done.

[0202] In FIG. 13A, the circuit MP[i,j] includes a wiring VE[j], a wiring VEn[j], The wiring VE[j] and wiring VEr[j] are wirings that supply a constant voltage. In addition, the wiring VE[j] is connected to the wiring OL In addition, a current flows from the wiring VEr[j] via the circuit MCr, for example. Current flows from line OLB.

[0203] The wiring WL[i] shown in FIG. 13A corresponds to the wiring WLS[i] in FIG. The line WL[i] is electrically connected to each of the holding parts HC and HCr. The first data w is stored in the storage unit HC and the storage unit HCr included in the path MP[i,j]. i (k-1) j (k) When writing information (for example, potential, resistance value, current value, etc.) according to the wiring WL By supplying a predetermined potential to [i], conduction is established between the wiring OL[j] and the holding unit HC. state, and the wiring OLB[j] and the holding unit HCr are brought into a conductive state. The first data w is stored in IL[j] and ILB[j]. i (k-1) j (k) Potential according to By supplying the above, the potentials of the holding unit HC and the holding unit HCr are respectively applied. Then, a predetermined potential is applied to the wiring WL[i], and the wiring IL[ and the holding unit HC is in a non-conductive state, and the wiring ILB[j] and the holding unit HCr are in a non-conductive state. Then, the first data w i (k-1) j (k) Each current according to the above is maintained.

[0204] For example, the first data i (k-1) j (k) is one of the three values ​​"-1", "0" or "1". Consider the case where either of the first data w i (k-1) j (k) If is "1", for example As a result, a current corresponding to "1" flows from the wiring IL[j] to the wiring VE[j] via the circuit MC. In order to achieve this, a predetermined potential is held in the holding unit HC, and the wiring ILB[j] is connected to the circuit MC The potential V0 is maintained in the holding part HCr so that current does not flow to the wiring VEr[j] via r. In addition, the first data w i (k-1) j (k) is "-1", for example, To prevent current from flowing from the wiring IL[j] to the wiring VE[j] via the circuit MC, the holding part H The potential V0 is maintained at C, and the potential V is transferred from the wiring ILB[j] to the wiring VEr[ A predetermined potential is maintained in the holding unit HCr so that a current corresponding to "-1" flows through the And the first data i (k-1) j (k) is "0", for example, wiring I To prevent current from flowing from L[j] to the wiring VE[j] via the circuit MC, the holding part HC is The potential V0 is maintained, and the potential V is transferred from the wiring ILB[j] to the wiring VEr[j] via the circuit MCr. The potential V0 is held in the holding section HCr so that the current does not flow. In the description of FIG. 14A, this can be the potential applied by the wiring VCN.

[0205] As another example, the first data w i (k-1) j (k) is the analog value, specifically, Consider the case where the analog value is a negative value, a zero value, or a positive value. Data w i (k-1) j (k) is a "positive analog value", as an example, An analog current corresponding to the "positive analog value" flows from the wire VE[j] through the circuit MC to the wire VE[j]. A predetermined potential is held in the holding unit HC, and the wiring ILB[j] is connected to the circuit M The potential V0 is maintained in the holding part HCr so that current does not flow to the wiring VEr[j] via Cr. Also, the first data w i (k-1) j (k) If is a "negative analog value", For example, we can prevent current from flowing from wiring IL[j] to wiring VE[j] via circuit MC. The potential V0 is held in the holding unit HC, and the potential V1 is applied from the wiring ILB[j] through the circuit MCr. The holding section H Cr is held at a predetermined potential. i (k-1) j (k) is "0" In this case, for example, a current flows from the wiring IL[j] to the wiring VE[j] via the circuit MC. To prevent this, the potential V0 is held in the holding unit HC, and the potential V1 is transferred from the wiring ILB[j] to the circuit MC The potential V0 is held in the holding part HCr so that no current flows through r to the wiring VEr[j]. As in the previous example, the potential V0 is set to the potential V1 of the wiring VC It can be the potential given by N.

[0206] Also, as an example, the circuit MC stores information (for example, potential, resistance value) stored in the storage unit HC. , or current value, etc.) according to the wiring OL[j] or wiring OLB[j ], and the circuit MCr outputs the information (for example, , potential, resistance value, or current value) according to the wiring OL[j] or For example, the first potential is held in the holding unit HC. When the first voltage is applied to the wiring VE from the wiring OL[j] or wiring OLB[j], the circuit MC When the second potential is held in the holding section HC, the circuit MC flows a current having a second current value from wiring OL[j] or wiring OLB[j] to wiring VE. Similarly, when the first potential is held in the holding unit HCr, the circuit MCr is connected to the wiring OL[ A current having a first current value is passed from the wiring OLB[j] or the wiring OLB[j] to the wiring VEr, and the holding When the second potential is held in the circuit HCr, the circuit MCr is connected to the wiring OL[j] or the wiring OLB A current having a second current value is passed from [j] to the wiring VE. The magnitude of each current value is the first data w i (k-1) j (k) is determined by the value of For example, the first current value may be greater than or less than the second current value. Furthermore, as an example, one of the first current value and the second current value is zero current, that is, the current value may be 0. Or, the current may be a current with a first current value and a current with a second current value. The flow direction may be different.

[0207] In particular, for example, the first data w i (k-1) j (k) Three values: "-1", "0", and "1" When either of the first current value or the second current value is zero, the circuit MC , it is preferable to configure the circuit MCr. i (k-1) j (k) Ana Logarithmic values, e.g., "negative analog value", "0", or "positive analog value" In addition, the first current value or the second current value may also be an analog value, for example. Cut.

[0208] By the way, from the wiring OL[j] or wiring OLB[j] (from the wiring IL[j]), The current flowing through the wiring VE[j] via C and the current flowing through the wiring OL[j] or wiring OLB[j] ( The current flowing from the line ILB[j] to the wiring VEr[j] via the circuit MCr is made equal to In this case, the characteristics of the transistor may vary due to the manufacturing process of the transistor. Therefore, the potential held in the circuit MC and the potential held in the circuit MCr are not equal. In the semiconductor device of one embodiment of the present invention, the characteristics of the transistors may vary. Even if the power is supplied from the wiring OL[j] or wiring OLB[j] (from the wiring IL[j]) through the circuit MC, The amount of current flowing through the wiring VE[j] is determined by the wiring OL[j] or wiring OLB[j] (wiring ILB[j]), is approximately equal to the amount of current flowing through the circuit MCr to the wiring VEr[j]. It may be possible to reduce the

[0209] In this specification, the information held in the holding unit HC and the holding unit HCr (for example, The current or voltage depending on the potential, resistance, or current value is a positive current or voltage. It may be a negative voltage or current, or a zero current or voltage. It may be a voltage or may be a mixture of positive, negative and zero values.

[0210] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 13A are the same as the wiring X in FIG. LS[i]. The second data z input to the circuit MP[i,j] i (k-1 ) For example, the potentials of the wiring X1L[i] and the wiring X2L[i] or Therefore, the circuit MC and the circuit MCr are provided with, for example, wiring X1 L[i] and the second data z i (k-1) Each potential is input according to Be encouraged.

[0211] The circuit MC and the circuit MCr are, for example, connected to the wiring X1L[i] and the wiring X2L[i]. The first wiring OL[j] and the wiring OLB[j] are connected in accordance with the input potential or current. Data W i (k-1) j (k) and the second data z i (k-1) The current or voltage depending on the product of As a specific example, the output destination of the current from the circuit MC and the circuit MCr is determined by the potentials of the wiring X1L[i] and the wiring X2L[i]. For example, in the circuit M C, and the circuit MCr are connected to the wiring OL[j] or the wiring OLB[ j], and the current output from the circuit MCr flows through either the wiring OL[j] or the wiring OLB[j ] is configured to flow to the other side of the circuit. The output currents do not flow through the same wiring, but through different wirings. For example, the wiring OL[j] or the wiring OLB[j] may be connected from the circuit MC and the circuit MCr. In some cases, no current flows at all.

[0212] For example, the second data z i (k-1) can take one of three values: "-1", "0", or "1". As an example, consider the case where the second data z i (k-1) If is "1", the circuit MP puts the circuit MC and the wiring OL[j] into a conductive state, and puts the circuit MCr and the wiring OLB[j] into a conductive state. In addition, as an example, the second data z i (k-1) is "-1" In this case, the circuit MP makes the circuit MC and the wiring OLB[j] conductive, and the circuit MCr and the wiring OLB[j] conductive. The second data z i (k-1) but If it is "0", the current output by each of the circuits MC and MCr is In order to prevent the current from flowing to either the circuit MC or the wiring OLB[j], the circuit MP OL[j] and between the circuit MC and the wiring OLB[j], and Between Cr and wiring OL[j], and between circuit MC and wiring OLB[j], a non-conductive state is established. do.

[0213] An example of the above operations is shown below. i (k-1) j (k) is "1" In this case, the wiring OL[j] or wiring OLB[j] is connected to the wiring VE[j] via the circuit MC. Current may flow through the circuit MCr to the wiring OL[j] or wiring OLB[j]. No current flows from the first data w i (k-1) j (k) is "-1" In this case, the wiring OL[j] or wiring OLB[j] is connected to the wiring VE[j ], and current flows from wiring OL[j] or wiring OLB[j] through circuit MCr. There is a case where a current flows through VEr[j]. Then, the second data z i (k-1) is "1" In this case, between the circuit MC and the wiring OL[j], and between the circuit MCr and the wiring OLB[j], The second data z i (k-1) If is "-1", the circuit MC and the Conduction is established between the line OLB[j] and the circuit MCr and the wiring OL[j]. From the above, the first data i (k-1) j (k) and the second data z i (k-1) The product of If the value is positive, current flows from wiring OL[j] to wiring VE[j] via circuit MCr. Or, current flows from wiring OL[j] to wiring VEr[j] via circuit MCr. On the other hand, the first data w i (k-1) j (k) and the second data z i (k-1) The product of is negative In the case of value, current flows from wiring OL[j] to wiring VEr[j] via circuit MCr. , or current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MC. The first data w i (k-1) j (k) and the second data z i (k-1) The product of these is zero In this case, no current flows from wiring OL[j] or wiring OLB[j] to wiring VE[j]. , no current flows from wiring OL[j] or wiring OLB[j] to wiring VEr[j].

[0214] To take the above example as a specific example, the first data w i (k-1) j (k) is "1" And the second data z i (k-1) is "1", for example, from the circuit MC to the wiring OL A current I1[i, j] with a first current value flows through the wiring OLB[j] from the circuit MCr. A current I2[i, j] having a second current value flows through the first current I2[i, j]. At this time, the magnitude of the second current value is For example, assume that the current is zero, that is, no current flows from the circuit MCr to the wiring OLB[j]. The first data w i (k-1) j (k) is "-1", and the second data z i (k-1) When is "1", for example, the second current value is sent from the circuit MC to the wiring OL[j]. A current I1[i, j] having a first current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, zero. In other words, it can be assumed that no current flows from the circuit MC to the wiring OL[j]. Ta w i (k-1) j (k) is "0", and the second data z i(k-1) is "1" In this case, a current I1[i, j] with a second current value flows from the circuit MC to the wiring OL[j], and the circuit A current I2[i, j] having a second current value flows from MCr to the wiring OLB[j]. , the magnitude of the second current value is, for example, zero, that is, from the circuit MC to the wiring OL[j]. Assume that no current flows and that no current flows from the circuit MCr to the wiring OLB[j]. It is possible.

[0215] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1 ) is "-1", a current I1[ i, j] flows from the circuit MCr to the wiring OL[j], and a current I2[i, j] with a second current value flows At this time, the magnitude of the second current value is, for example, zero, that is, the current flowing through the circuit MCr Therefore, it is possible to prevent current from flowing through the wiring OL[j]. i (k-1 ) j (k) is "-1", and the second data z i (k-1) If is "-1", the circuit A current I1[i, j] with a second current value flows from MC to wiring OLB[j], and a current I2[i, j] flows from circuit MCr to wiring OLB[j]. A current I2[i, j] having a first current value flows through the wiring OL[j]. For example, the magnitude of the value is zero, that is, no current flows from the circuit MC to the wiring OLB[j]. The first data w i (k-1) j (k) is "0", Second data z i (k-1) If is "-1", the second A current I1[i, j] with a current value flows, and a second current value is sent from the circuit MCr to the wiring OL[j]. At this time, the magnitude of the second current value is, for example, zero. In other words, no current flows from the circuit MC to the wiring OLB[j], and the circuit MCr Therefore, it is possible to make it so that no current flows through the wiring OL[j].

[0216] Also, the second data z i (k-1) When is "0", for example, the circuit MC and the wiring OL[j] and between the circuit MC and the wiring OLB[j]. , between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j] Therefore, the first data w i (k-1) j (k) Whatever the value of No current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j]. stomach.

[0217] In this way, as an example, the first data w i (k-1) j (k) and the second data z i (k -1) If the product of is positive, then from either circuit MC or circuit MCr, A current flows through the wiring OL[j]. At this time, the first data w i (k-1) j (k) is a positive value In this case, a current flows from the circuit MC to the wiring OL[j], and the first data w i(k-1) j ( k) When is a negative value, current flows from the circuit MCr to the wiring OL[j]. Data w i (k-1) j (k) and the second data z i (k-1) When the product of In this case, a current flows from either the circuit MC or the circuit MCr to the wiring OLB[j]. At this time, the first data w i (k-1) j (k) If is a positive value, the wire O Current flows through LB[j], and the first data w i (k-1) j (k) If is negative, the circuit Current flows from MCr to wiring OLB[j]. The sum of the currents output from multiple circuits MC or MCr flows through wiring OL[j]. In other words, the current that flows through the wiring OL[j] is the sum of positive values. On the other hand, the output from multiple circuits MC or MCr connected to wiring OLB[j] The sum of the currents flowing through the wiring OLB[j]. In this case, a current with a value equal to the sum of the negative values ​​will flow. The total current value flowing through the wiring OL[j], that is, the sum of the positive values, and the current flowing through the wiring OLB[j] By using the total current value, that is, the sum of negative values, it is possible to perform product-sum calculations. For example, the total current flowing through wiring OL[j] is larger than the total current flowing through wiring OLB[j]. If the value is greater than the current value, it can be determined that the result of the multiplication and accumulation operation will be a positive value. The total current value flowing through the wiring OL[j] is greater than the total current value flowing through the wiring OLB[j]. If σ is also small, it can be determined that the result of the product-sum operation will be a negative value. The total current value flowing through the wire OL[j] and the total current value flowing through the wire OLB[j] are approximately the same value. In some cases, it can be determined that the result of the multiply-and-accumulate operation will be zero. , and as an activation function, the result of the multiplication and addition operation is a negative If it is determined that the wiring OL[j] takes a value, it may be output as a zero value. Only when the total current value flowing through wiring OLB[j] is approximately the same as the total current value flowing through wiring OLB[j] The total current value flowing through wiring OL[j] is greater than the total current value flowing through wiring OLB[j]. Even if the sum of products is smaller than the sum of products, it may be determined that the result of the sum of products is zero.

[0218] In addition, the second data z i (k-1) is one of two values: "-1", "0", or "1" For example, the binary values ​​"-1" and "1" or the binary values ​​"0" and "1" are also the same. Similarly, the first data w i (k-1) j (k) is "-1", In the case of two values, for example, "-1" and "1", Alternatively, the same operation can be performed in the case of two values, "0" and "1".

[0219] In addition, the first data i (k-1) j (k) is an analog value or multi-bit (multi-valued) A specific example is to use "negative analog" instead of "-1". value” and “positive analog value” instead of “1”. In this case, the circuit M The magnitude of the current flowing from C or the circuit MCr is also, for example, the first data w i (k-1 ) j (k) It becomes an analog value according to the absolute value of the value.

[0220] Next, an example of a modification of the circuit MP[i,j] in FIG. 13A will be described. The modified example of P[i,j] will be mainly explained with respect to the parts different from the circuit MP[i,j] of FIG. 13A. 13A. Therefore, explanation of the parts common to the circuit MP[i,j] in FIG. 13A may be omitted. do.

[0221] The circuit MP[i,j] shown in FIG. 13B is the circuit MP[i,j] shown in FIG. 13A, except that the wiring IL[i] and wiring ILB[i] are combined into wiring IL[j].

[0222] The wirings W1L[i] and W2L[i] shown in FIG. 13B are the wirings WLS[i] The wiring W1L[i] is electrically connected to the holding unit HC, and the wiring W2L[i] is It is electrically connected to the holder HCr.

[0223] The wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr. .

[0224] In the circuit MP[i,j] of FIG. 13B, different holding units HC and HCr are used. When holding information (for example, voltage, resistance, current, etc.), the holding section HC and the holding section HCr It is preferable to store information in the circuits MP[i, The first data w of j i (k-1)j (k) The first information is stored in the storage unit HC, and the second information is stored in the storage unit HCr. Let us consider the case where the second information can be expressed by holding the wiring W1L[i]. and the wiring W2L[i], a predetermined potential is applied to each of the holding unit HC and the wiring IL[j]. and the holding unit HCr and the wiring IL[j] are brought into a non-conductive state. By supplying a current, a voltage, or the like according to the first information to the wiring IL[j], the holding unit HC The first information can be given. After that, the wiring W1L[i] and the wiring W2L[i] A predetermined potential is applied to each of them to make the holding unit HC and the wiring IL[j] non-conductive, In addition, the holding unit HCr and the wiring IL[j] are brought into a conductive state. By supplying a current, a voltage, or the like according to the second information, the second information is given to the holding unit HCr. As a result, the circuit MP[i,j] receives w as the first data. i (k-1) j (k) can be set.

[0225] The holding unit HC and the holding unit HCr each hold approximately the same information (for example, voltage, Resistance value, current, etc.) (first data w of circuit MP[i,j] i (k-1) j (k) is set by storing approximately equal information in the storage section HC and the storage section HCr. When the holding unit HC is connected to the wiring IL[j], the holding unit HC and the wiring IL[j] are electrically connected to each other. The wiring W1L[i] and the wiring W2L[i] are connected to the wiring IL[j] so that they are in a conductive state. A predetermined potential is applied to each of the wiring IL[j] and the holding unit HC and the holding unit H Current, voltage, etc. according to the information may be supplied to Cr.

[0226] The circuit MP[i,j] in FIG. 13B stores the first data w in the holding unit HC and the holding unit HCr. i (k- 1) j (k) The potential corresponding to the second data z i (k-1) Wire X1 to the potential according to L[i] and wiring X2L[i], the circuit MP[i,j] in FIG. 13A Similarly, the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0227] The circuit MP[i,j] shown in FIG. 13C is a modification of the circuit MP[i,j] of FIG. 13A. The circuit MP[i,j] in FIG. 13C is similar to the circuit MP[i,j] in FIG. 13A in that it is a circuit MC 13C and the circuit MP[i,j] in FIG. 13A. P[i,j] has a different configuration of electrically connected wiring.

[0228] Specifically, the circuit MP[i,j] in FIG. 13C is the same as the circuit MP[i,j] in FIG. 13A. Therefore, the wiring OL[j] and the circuit MCr are not electrically connected, and the wiring OLB[j] and the circuit MC are not electrically connected. The circuit MP[i,j] is the same as the wiring X1L[i] and The wiring X2L[i] and the wiring X2L[i] are replaced with wiring XL[i]. 12 corresponds to the wiring XLS[i] in FIG. 12, and is electrically connected to the circuit MC and the circuit MCr. are actively connected.

[0229] In the circuit MP[i,j] of FIG. 13C, the wiring OL[j] and the circuit MCr are electrically connected. Since the wiring OLB[j] and the circuit MC are not electrically connected, The second data (value of the neuron signal) to be output may be different from that of the circuit MP[i,j] in FIG. 13A. For example, when a high-level potential is applied to the line XL, the second data (new When the signal value of the second line is set to "+1" and a low-level potential is applied to the line XL, The data (the value of the neuron's signal) can be set to "0".

[0230] The circuit MP[i,j] shown in FIG. 13D includes the wiring OL[j] and the wiring O LB[j] contains the first data w i (k-1) j (k) and the second data z i (k-1) The product of The circuit MP[i,j] in FIG. 13D is a circuit that can output a current according to the , can be applied to the arithmetic circuit 130 in FIG. 12, for example.

[0231] The circuit MP[i,j] in FIG. 13D includes a circuit MC and a circuit MCr, as well as a transistor. It has a MZ.

[0232] The first terminal of the transistor MZ is connected to the first terminal of the circuit MC and the first terminal of the circuit MCr. The second terminal of the transistor MZ is electrically connected to the wiring VL. The gate of the transistor MZ is electrically connected to the wiring XL[i].

[0233] The wiring VL may be, for example, the wiring VE[j] and the wiring Similar to VEr[j], it functions as a wiring that provides a constant voltage. It is preferable to determine the constant voltage by the configuration of the arithmetic circuit 130, etc. For example, VDD is a high-level potential, VSS is a low-level potential, or the ground potential. It is possible.

[0234] 13D is the same as the wiring WL[i] in the arithmetic circuit 130 in FIG. The wiring WL[i] is electrically connected to the holding unit HC and the holding unit HCr. It continues.

[0235] The wiring OL[j] is electrically connected to the second terminal of the circuit MC. OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0236] The wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HC. It is electrically connected to the HCr part.

[0237] In the circuit MP[i,j] of FIG. 13D, the first holding unit HC and the first holding unit HCr are The operation when holding the potential according to the data is shown in the circuit MP[i,j] of FIG. Please refer to the description of the operation of holding the potential according to the first data in the above.

[0238] In the circuit MP[i,j] of FIG. 13D, the circuit MC is connected to the first terminal of the circuit MC via the wiring VL When a constant voltage given by is supplied, a current according to the potential held in the holding section HC is The circuit MCr has a function of passing current between the first terminal and the second terminal of the circuit M. When a constant voltage is applied to the first terminal of C via the wiring VL, the voltage held by the holding unit HCr is The circuit MCr has a function of passing a current corresponding to the applied potential between the first terminal and the second terminal of the circuit MCr. That is, the first data w is stored in each of the holding unit HC and the holding unit HCr of the circuit MP[i,j]. i ( k-1) j (k) By maintaining a potential according to and the amount of current flowing between the first and second terminals of the circuit MCr. The constant voltage applied to the first terminal of the circuit MC (circuit MCr) by the wiring VL is If not supplied, the circuit MC (circuit MCr) may, for example, It is also possible that no current flows between the first terminal and the second terminal.

[0239] For example, if the first data w of "1" is stored in each of the storage units HC and HCr, i (k-1) j (k) When the potential according to is maintained, a constant voltage is applied to the circuit MC from the wiring VL. By this, the circuit MC flows a predetermined current between the first terminal and the second terminal of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. does not allow current to flow between the first and second terminals of the circuit MCr. No current flows between MCr and the wiring OLB. The first data w of "-1" for each of r i (k-1) j (k) The potential is maintained according to When the constant voltage given by the wiring VL is applied to the circuit MC, the circuit MCr , a predetermined current flows between the first terminal and the second terminal of the circuit MCr. At this time, the current flows between the first terminal of the circuit MC and the wiring OLB. Therefore, no current flows between the circuit MC and the wiring OL. For example, if the first data of "0" is stored in each of the holding parts HC and HCr, Ta w i (k-1) j (k) When the potential according to the circuit MC and the circuit MCr is maintained, Regardless of whether a constant voltage is applied to the wiring VL, the circuit MC is connected to the first terminal of the circuit MC. No current flows between the first and second terminals of the circuit MCr. In other words, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OL. No current flows between the lines OLB.

[0240] In the circuit MP[i,j] of FIG. 13D, the values ​​held in the holding units HC and HCr are First data i (k-1) j (k) For a specific example of the potential according to Please refer to the description of the circuit MP[i,j]. The holding unit HC and the holding unit HCr are not potentials but currents, as in the circuit MP[i,j] of FIG. 10A. The circuit MC and the circuit MCr have the function of storing information such as resistance values. It may have a function of flowing a current.

[0241] The wiring XL[i] shown in FIG. 13D is the wiring XLS[i] in the arithmetic circuit 130 in FIG. ]. The second data z input to the circuit MP[i,j] corresponds to i (k-1) is one For example, it is determined by the potential and current of the wiring XL[i]. The gate of the master MZ is connected to the second data z via the wiring XL[i]. i (k-1) to A potential corresponding to the voltage is input.

[0242] For example, the second data z i (k-1) Consider the case where takes either of the two values ​​"0" or "1". For example, the second data z i (k-1) If is "1", the wire XL[i] has a high level. At this time, the transistor MZ is turned on, so The circuit MP brings the wiring VL and the first terminal of the circuit MC into a conductive state, and the wiring VL and the circuit MC r and the first terminal of the second data z i (k-1) is "1" When this occurs, a constant voltage is applied to the circuit MC and the circuit MCr from the wiring VL. For example, the second data z i (k-1) When is "0", the wire XL[i] has a low level potential. In this case, the circuit MP is a non-transitory circuit between the circuit MC and the wiring OLB[j]. The second device is in a conductive state, and the second device is in a non-conductive state. Data z i (k-1) When is "0", the circuit MC and the circuit MCr are connected to the wiring VL. No constant voltage is given by these.

[0243] Here, for example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1)When is "1", current flows between the circuit MC and the wiring OL, and the circuit MC As a result, no current flows between r and the wiring OLB. i ( k-1) j (k) is "-1", and the second data z i (k-1) If is "1", No current flows between the circuit MC and the wiring OL, and current flows between the circuit MCr and the wiring OLB. For example, the first data w i (k-1) j (k) is "0" , second data z i (k-1) is "1", the line between the circuit MC and the wiring OL, and the line between the circuit MC and the wiring OL As a result, no current flows between MCr and the wiring OLB. i (k-1) is "0", the first data w i (k-1) j (k) is "-1", "0 " or "1", the circuit MC and the wiring OL, and the circuit MCr and the wiring O As a result, no current flows between LB.

[0244] That is, the circuit MP[i,j] in FIG. 13D, like the circuit MP[i,j] in FIG. 13C, As an example, the first data w i (k-1) j (k) The value can be one of three values: "-1", "0", or "1". Choose either one and use the second data z i (k-1) When takes two values, "0" and "1", In addition, the circuit MP[i,j] in FIG. 13C can be used to perform the same calculation. The path MP[i,j] is the first data w i (k-1) j (k) is "-1", "0", "1". If the value is one of two, for example, "-1" or "1", or "0" or "1" It can also be operated in the case of two values ​​of ". i (k-1) j (k) may take analog values ​​or multi-bit (multi-valued) digital values. For example, "negative analog value" instead of "-1" and "positive analog value" instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr For example, the first data i (k-1) j (k) Analog value according to the absolute value of This becomes:

[0245] <<Circuit ILD>> The circuit ILD includes, for example, wirings IL[1] to IL[n] and wirings ILB[1]. through wiring ILB[n] and the circuits MP[1,1] to MP[m,n]. For each of these, the first data w1 (k-1) 1 (k) Or even w m (k-1) n (k) The device has a function of inputting information (for example, potential, resistance value, current value, etc.) corresponding to the above. As a specific example, the circuit ILD is a first weighting coefficient for the circuit MP[i,j]. Data W i (k-1) j (k) Information corresponding to the potential, resistance, or current ) are supplied via wiring IL[j] and wiring ILB[j].

[0246] FIG. 14A shows an example of the circuit configuration of the circuit ILD that can be applied to the arithmetic circuit 130. In addition, in FIG. 14A, in order to explain the electrical connection between the circuit ILD and the array portion ALP, the wiring The line OL[j] and the wiring OLB[j] are also shown. The circuit ILD is connected to the current source circuit ISC. , switch SWIA, switch SWIAB, switch SWLA, and switch SWLA The wiring OL[j] is connected to the first terminal of the switch SWIA and the second terminal of the switch SWLA. The first terminal of the switch SWIAB is electrically connected to the wiring OLB[j]. The first terminal is electrically connected to the first terminal of the switch SWLAB. ISC is electrically connected to the second terminal of the switch SWIA and the second terminal of the switch SWIAB. The wiring VCN is connected to the second terminal of the switch SWLA and the and a second terminal of the

[0247] The current source circuit ISC has, for example, one or more constant current sources. In FIG. 14A, As an example, the plurality of constant current sources may include a constant current source circuit ISC1, a constant current source circuit ISC2, and a , and a constant current source circuit ISC3. The current source circuit ISC may include, for example, a plurality of In order to select the constant current source, a plurality of switches are provided. The switches include a switch SWC1, a switch SWC2, and a switch SWC3. When the current source circuit ISC has only one constant current source, the current source circuit ISC is a switch. Alternatively, the constant current source circuit ISC1, the constant current source circuit ISC2, and the constant When the current source circuit ISC1 and the current source circuit ISC2 each have a function of controlling whether or not to output a current. In this case, the switches SWC1, SWC2, and SWC3 are not required. Good too.

[0248] By the way, if the first data ( The weight coefficients are used to hold the currents in the wiring OL[j] and wiring OLB[j]. The currents are preferably generated by the same current source circuit ISC as shown in FIG. 14A. The currents flowing through the wiring OL[j] and wiring OLB[j] are generated by different current source circuits. In this case, variations in the characteristics of the transistor due to factors such as the manufacturing process of the transistor may occur. This can cause differences in performance between different current source circuits. When the same current source circuit is used, the same large current is applied to the wiring OL[j] and the wiring OLB[j]. This makes it possible to pass a current of a certain magnitude, thereby improving the accuracy of calculations.

[0249] Note that the switches SWIA, SWIAB, and SWLA described in FIG. 14A , switch SWLAB, switch SWC1, switch SWC2, switch SWC3, that For example, the above-mentioned switches SWR1, SWR1B, and SW R2 and a switch similar to switch SWR2B can be used.

[0250] Specific configuration examples of the constant current source circuits ISC1 to ISC3 are shown in FIG. 14B and FIG. 14C. The constant current source circuit ISC1 (constant current source circuit ISC2, constant current source The circuit ISC3) has a transistor PTr, which is a p-channel transistor. The first terminal of the transistor PTr is electrically connected to the wiring VSO, and the second terminal of the transistor PTr is The terminal is electrically connected to the second terminal of switch SWC1 (switch SWC2, switch SWC3). The gate of the transistor PTr is electrically connected to the wiring VB. , the constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3 shown in FIG. 14C ) has a transistor NTr which is an n-channel transistor, and the first The first terminal of the transistor NTr is electrically connected to the wiring VSO, and the second terminal of the transistor NTr is electrically connected to the switch It is electrically connected to the second terminal of SWC1 (switch SWC2, switch SWC3) and The gate of the transistor NTr is electrically connected to the wiring VB. The constant current source circuits ISC1 (constant current source circuits ISC2 and ISC3) In this case, the wiring VB is used to input a bias voltage to the gate of each transistor. It functions as a wiring. A pulse signal may be supplied to the wiring VB. It is possible to control whether or not a current is output from each constant current source circuit. The switches SWC1, SWC2, and SWC3 may not be provided. Alternatively, an analog voltage may be supplied to the wiring VB. A log current can be supplied.

[0251] The wiring VSO is connected to each of the constant current source circuits ISC1 to ISC3 as follows: It functions as a wiring that supplies a constant voltage. For example, from the circuit ILD (wiring VSO) to the wiring O When a current flows through L or wiring OLB, the constant voltage is a potential higher than the ground potential ( For example, VDD, and further, a constant current source circuit ISC1 shown in FIG. It is preferable to use the constant current source circuit ISC2 and the constant current source circuit ISC3. When a current flows from the wiring OL or the wiring OLB to the circuit ILD (wiring VSO), The voltage may be a potential higher than the ground potential but lower than the high-level potential, a ground potential, or a negative potential. It is preferable to use the constant current source circuit ISC1 (constant current source circuit ISC2) shown in FIG. It is preferable to use a constant current source circuit (SC2, constant current source circuit ISC3). The current flowing from the line ILD to the wiring OL or the wiring OLB may be referred to as a positive current. Therefore, the current flowing from the wiring OL or the wiring OLB to the circuit ILD is described as a negative current. There are cases where this happens.

[0252] By the way, the current flowing from the constant current source circuit ISC1 is I ut As an example, The current source circuit ISC2 flows is 2I ut It is preferable that the constant current source circuit ISC3 The current is 4I ut That is, it is preferable that the number of current source circuits ISC is P (P is 1 or more). (p is an integer between 1 and P) The current flowing from the constant current source is 2 (p-1) ×I ut That is, the switch By switching SWC1 to SWC3 etc. between the on and off states, This allows the magnitude of the current flowing from the current source circuit ISC to be changed.

[0253] For example, the number of constant current sources in the current source circuit ISC is three (P=3). To I ut If you want to pass a current of 100mV, turn on the switch SWIA and turn on the switch SWIAB. After turning it off, switch SWC1 is turned on, and switches SWC2 and Switch SWC3 should be turned off. Also, connect 5I to wire OL[j]. ut I want to pass a current of In this case, the switches SWC1 and SWC3 are turned on, and the switch SWC2 is turned on. In other words, the amount of current output from the current source circuit ISC is 8 values ​​(0 ", "I ut ", "2I ut ", "3I ut ", "4I ut ", "5I ut ", "6I u t ", "7I ut "). Note that the voltage value greater than 8 If you want to output a constant current, you need to use four or more constant current sources. By turning switch SWIA off and switch SWIAB on, wiring OL Any one of eight current values ​​can be applied to B[j]. When no current is output, the switches SWC1 to SWC3 of the current source circuit ISC are Instead of turning them off, the switches SWIA and SWIAB may be turned off. By arranging multiple constant current sources in this way, it is possible to generate current with multiple values. The circuit can be easily realized. In addition, it can be realized in an analog manner by arranging only one current source circuit. The current value output to the inverter may be changed.

[0254] The wiring VCN supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, a current (positive When a current flows, the constant voltage given by the wiring VCN is a low-level potential (for example, VSS For example, it is preferable that the wiring OL or the wiring OLB is connected to the circuit ILD. When a current (negative current) flows through the VCN line, the constant potential given by the VCN line is a high-level potential. It is preferable to use the following. As shown in the figure, a capacitor C1 is electrically connected to the source terminal of a transistor M1, etc., and the source If the terminal is connected to a power supply line, etc., the When a positive current flows through B, the constant voltage given by the wiring VCN is a low-level potential (for example, VSS, etc.) is preferable. In other words, when supplying a constant voltage from the wiring VCN, It is desirable to make the potential difference across the capacitor C1 close to zero. The potential at which no current is output from the circuit MC is approximately the same as the potential given by the wiring VE. It is desirable to supply the same potential to the wiring VCN.

[0255] Here, the first data (weighting coefficient) input to the circuit MP will be described.

[0256] When you want to input positive first data to the circuit MP, you can input a positive first data to the wiring OL[j]. The current is input, and the constant potential given by the wiring VCN is input to the wiring OLB[j]. As a result, the current source circuit ISC and the wiring OL[j] are connected to each other, and the current source circuit ISC and wiring OLB[j] in a non-conductive state, and wiring VCN and wiring OL[j] in a non-conductive state. By setting the wiring VCN and the wiring OLB[j] to a conductive state, the wiring VCN and the wiring OLB[j] are brought into a conductive state. The switches SWIA and SWLAB are turned on, and the switches SWIAB and By doing so, the current source circuits ISC and Since the line OL[j] is in a conductive state, the line OL[j] is connected to the current source circuit ISC. Current can be passed through the circuit MP via the constant current source of the current source circuit ISC. When the number of pieces is P, the current is 2 P -1 value (excluding zero current) The positive weighting coefficient input to the circuit MP is determined according to the current. is 2 P In addition, the wiring VCN and the wiring OLB[j] can be either one of the values ​​−1. Since the connection between these two is in a conductive state, a constant voltage is input from the wiring VCN to the wiring OLB[j]. do.

[0257] Also, when negative first data is to be input to the circuit MP, the first data is input to the wiring OLB[j]. Input a current according to the current value, and input the constant potential given by the wiring VCN to the wiring OL[j]. For example, the current source circuit ISC and the wiring OL[j] are brought into a non-conductive state, and the current source circuit The circuit ISC and the wiring OLB[j] are in a conductive state, and the circuit VCN and the wiring OL[j] are in a conductive state. is put into a conductive state, and the state between the wiring VCN and the wiring OLB[j] is put into a non-conductive state. That is, the switches SWIAB and SWLA are turned on, and the switches SWIA and SW LAB are turned off. This turns off the current source circuit ISC and the wiring OLB. Since the connection between [j] and ISC is established, the current source circuit ISC is connected to the wiring OLB[j]. , current can flow through the circuit MP. By the way, the number of constant current sources in the current source circuit ISC is When there are P, the current is 2 P -1 value (excluding zero current). The negative weighting factor input to the circuit MP is determined according to the current, so the weighting factor is 2 P In addition, the wiring VCN and the wiring OL[j] can be either one of the values ​​−1. Since the line OL[j] is in the ON state, a constant voltage is input from the line VCN to the line OL[j].

[0258] Also, when you want to input the first data of 0 to the circuit MP, wire OL[j], wire OLB[j ], the constant potential given by the wiring VCN can be input to each of them. The current source circuit ISC and the wiring OL[j] are in a non-conductive state, and the current source circuit ISC and the wiring OLB[j] and wire VCN and wire OL[j] are put into a non-conductive state, and wire VCN and wire OL[j] are put into a conductive state. N and the wiring OLB[j] are connected to each other. Switch SWLAB is turned on, and switches SWIA and SWIAB are turned on. This puts the wiring VCN and the wiring OL[j] into a conductive state. Therefore, the wiring VCN and wiring OLB[j] are in a conductive state, and the wiring OL[j] and wiring A constant voltage is input to OLB[j] from the line VCN.

[0259] In other words, by setting the number of constant current sources in the current source circuit ISC to P, The number of weighting factors that can be input (the sum of positive weighting factors, negative weighting factors, and 0 weighting factors) is 2. P+ 1 -1 piece.

[0260] In the above description, the circuit ILD has been described as having a current source circuit ISC. One embodiment of the present invention is not limited to this. For example, a circuit other than the current source circuit ISC may be used instead. Alternatively, a voltage source circuit may be arranged in place of the wiring OL[j ] and a circuit for wiring OLB[j], as separate circuits, At least one of each may be arranged. For a pair of wires, OL[j] and OLB[j], there is at least one The current source circuit ISC may be included. The circuit ILD may be provided as a separate circuit from the circuit AFP. However, one aspect of the present invention is not limited to this. may be an integral circuit with the circuit AFP.

[0261] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit 130 in Fig. 12 will be described. As an example, an arithmetic circuit 130A shown in FIG. 15 is used.

[0262] The arithmetic circuit 130A shown in FIG. 15 is the arithmetic circuit 130 shown in FIG. 12, which is provided with the circuit ACT shown in FIG. 12. F[j] is applied to the circuit located in the j-th column of the arithmetic circuit 130 in FIG. Therefore, the arithmetic circuit 130A in FIG. 15 is the same as that in FIG. 1A. Neuron N in the neural network 100 j (k) The input to the neuro N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k -1) (It may be referred to as first data or second data. Here, it is referred to as second data. ) and weighting coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) (First data or is sometimes called the second data. Here, it is called the first data.) and and calculating an activation function using the result of the product-sum operation.

[0263] 13. The circuit MP included in the array part ALP of the arithmetic circuit 130A of FIG. A circuit MP is applied, and wiring WL[ 1] to WL[m], and the wiring XLS[1] to XLS[m] are shown. 1L[1] to wiring X1L[m] and wiring X2L[1] to wiring X2L[m] are shown. In addition, the circuit I included in the circuit ACTF[j] of the arithmetic circuit 130A in FIG. As the VTR and the circuit IVTRr, the circuit IVTR (circuit IVTRr) shown in FIG. It is applied.

[0264] First, in the arithmetic circuit 130A, the circuits MP[1,j] to MP[m,j] are 1 data w1 (k-1) j (k) Or even w m (k-1) j (k) The first data is set. w i (k-1) j (k) The setting method is as follows: by the circuit WLD, wiring WLS[1] To the wiring WLS[m], a predetermined potential is input in order to the circuits MP[1,j] to MP[ m,j] in order, and then select the circuits MC and MCr included in the selected circuit MP. For the holding part HC and the holding part HCr, from the circuit ILD, the wiring OL[j] and the wiring OLB[ j], a potential, a current, etc. according to the first data are supplied. After the supply of the above, the circuit WLD supplies the circuits MP[1,j] to MP[m,j]. By deselecting the circuits MP[1,j] to MP[m,j], each of the circuits MP[1,j] to MP[m,j] is enabled. The holding unit HC of the circuit MC and the holding unit HCr of the circuit MCr store the first data w1 (k-1) j (k) Or even w m (k-1) j (k) It is possible to maintain a potential, current, etc. according to the As an example, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) Either If the value is positive, a value corresponding to the positive value is input to the holding unit HC. A value equivalent to zero is input to the holding unit HCr. (k-1) j ( k) Or even w m (k-1) j (k) If any of the values ​​is negative, the holding part H Enter a value equivalent to zero in C, and enter a value corresponding to the absolute value of the negative value in the holding part HCr. Also, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) Either If the value of 0 is to be taken, a value equivalent to zero is input to the holding part HC. In the part HCr, a value corresponding to the absolute value of zero is input.

[0265] Next, the wirings X1L[1] to X1L[m] and X2L[1 ] to wiring X2L[m], (k-1) ~z m(k-1) of As a specific example, the second data is supplied to the wiring X1L[i] and the wiring X2L[i]. z1 (k-1) is supplied.

[0266] Second data z1 input to each of the circuits MP[1,j] to MP[m,j] ( k-1) ~z m (k-1) According to the circuit MP[1,j] to the circuit MP[m,j], The conduction state between the circuit MC and the circuit MCr and the wiring OL[j] and wiring OLB[j] is determined. As a specific example, the circuit MP[i,j] receives the second data z i (k-1) Depending on The circuit MC and wiring OL[j] are in a conductive state, and the circuit MCr and wiring OLB[j] are in a conductive state. The two modes are "conduction between the circuit MC and the wiring OLB[j]" and "conduction between the circuit MC and the wiring OLB[j]". , circuit MCr and wiring OL[j] are in a conductive state, and Cr is in a non-conductive state with the wiring OL[j] and OLB[j], respectively. For example, the second data z1 (k-1) When it takes a positive value, , the wiring X1L[1] has a state where the circuit MC and the wiring OL[j] are in a conductive state, and the circuit A value that allows conduction between the circuit MCr and the wiring OLB[j] is input. , the wiring X2L[1] is in a non-conductive state between the circuit MC and the wiring OLB[j], and , a value that allows the circuit MCr and the wiring OL[j] to be in a non-conductive state is input. Then, the second data z1 (k-1) If the value is negative, connect the wire X1L[1] is a state in which the circuit MC and the wiring OLB[j] are in a conductive state, and the circuit MCr and the wiring OL Enter a value that allows conduction between [j] and wire X2L[1]. is a state in which the circuit MC and the wiring OL[j] are in a non-conductive state and the circuit MCr and the wiring OL B[j]. (k-1) If the value of , takes zero, the wiring X1L[1] has the circuit MC and the wiring OLB[j] is in a non-conductive state, and the circuit MCr and the wiring OL[j] are in a non-conductive state. Input a value that can be in a conductive state. Then, the wiring X2L[1] is connected to the circuit MC. The line between the circuit MCr and the wiring OL[j] is in a non-conductive state, and the line between the circuit MCr and the wiring OLB[j] is in a non-conductive state. Enter the value at which the switch can be in a non-conducting state.

[0267] The second data z input to the circuit MP[i,j] i (k-1) Depending on the circuit MP[i, Conduction between the circuit MC and the circuit MCr included in [j] and the wiring OL[j] and the wiring OLB[j] By determining the state, the circuit MC, the circuit MCr, the wiring OL[j], the wiring OLB[j] Furthermore, the amount of current is set in the circuit MP[i,j]. The first data i (k-1) j (k) and / or second data z i (k-1) Decided depending on circle.

[0268] For example, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MCr. Let I[i,j] be the current flowing through the wiring OLB[j] to the circuit MC or the circuit MCr. The current flowing through the B [i,j]. Then, the current flows from the circuit ACTF[j] to the wiring OL[j]. The current flowing through the out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] I Bout If [j], then I out [j] and I Bout [j] can be expressed by the following formula: This can be done.

[0269]

number

[0270] In the circuit MP[i,j], as an example, the first data w i (k-1) j (k) is "+ When the current is 1, there is a current I(+ 1) flows between the circuit MCr and the other of the wiring OL[j] or wiring OLB[j], and I(-1 ) flows, and the first data w i (k-1) j (k) When is "-1", the circuit M I(-1) flows between C and either the wiring OL[j] or the wiring OLB[j], and the circuit MCr I(+1) flows between the other of the wiring OL[j] and the wiring OLB[j]. 1 data w i (k-1) j (k) When is "0", the circuit MC and the wiring OL[j] or I(-1) flows between one side of the line OLB[j] and the circuit MCr and the wiring OL[j] or the wiring I(-1) flows between the other OLBs [j].

[0271] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) When is "+1", The circuit MC and wiring OL[j] are in a conductive state, and the circuit MCr and wiring OLB[j] are in a conductive state. The state between the circuit MC and the wiring OLB[j] becomes conductive, and the state between the circuit MC and the wiring OLB[j] becomes non-conductive. r and the wiring OL[j] are in a non-conductive state, and the second data z i (k-1) When is "-1", "the circuit MC and the wiring OLB[j] are in a conductive state, and the circuit The circuit MCr and the wiring OL[j] are in a conductive state, and the circuit MC and the wiring OL[j] are in a non-conductive state. The circuit MCr and the wiring OLB[j] are in a non-conductive state. , second data z i (k-1) When is "0", "between circuit MC and wiring OL[j]" , and between the circuit MC and OLB[j], there is no conduction, and between the circuit MCr and the wiring OL [j] and between the circuit MCr and OLB[j] are in a non-conductive state. It shall be taken.

[0272] At this time, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MC The current I[i,j] flowing through r and the current I[i,j] flowing from wiring OLB[j] to circuit MC or circuit MCr The current I B [i,j] is as shown in the table below. In some cases, I(- The circuit MP[i,j] may be configured so that the current amount of 1) is 0. i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] flows from the circuit MC or the circuit MCr to the wiring OLB[j]. It may also be a current.

[0273] [Table 1]

[0274] Then, the circuit ACTF[j] flows, for example, in the wiring OL[j] and the wiring OLB[j]. I out [j] and I Bout [j], and generate a voltage according to I o ut Voltage and I according to [j] Bout Depending on the difference between the voltages according to [j] and j (k) is the signal z sent to the (k+1)th layer neuron. j (k) Output.

[0275] The operation of the circuit ACTF[j] is the same as that of the arithmetic circuit 110A in FIG. 8 of the first embodiment. Please refer to the explanation of the operation example.

[0276] <Configuration example 2 of arithmetic circuit> The arithmetic circuit 130A shown in FIG. Bout I rather than [j] out [j] is big If (u j (k) is positive), the circuit AC will j (k) of Output, I out I rather than [j] Bout When [j] is large (u j (k) If is negative In this case, the circuit AC outputs a digital signal z j (k) The configuration is to output However, one embodiment of the present invention is not limited to this. out I rather than [j] Bout When [j] is large (u j (k) is negative), The path AC is the negative value of the output signal z j (k) The configuration may be changed to output the following.

[0277] An example of such an arithmetic circuit is shown in Fig. 16. The arithmetic circuit 140 shown in Fig. 16 performs the same calculation as the arithmetic circuit shown in Fig. 15. The circuit ACTF[j] included in the circuit AFP of the calculation circuit 130A is configured by changing the circuit ACTF[j]. The circuit configuration of the arithmetic circuit 140 is also an example of the arithmetic circuit 120 shown in FIG. The circuit ACTF[j] includes a switch SWR1M, a switch SWR1MB, and a switch SWR1P, switch SWR1PB, switch SWR2M, and switch SWR2MB , switch SWR2P, switch SWR2PB, capacitance CREM, capacitance CREP, , a circuit ACM, a circuit ACP, a circuit IVTR, and a circuit IVTRR. The circuit ACP has a terminal mbt1p and a terminal mbt2p, and the circuit ACM has a terminal mb t1m and terminal mbt2m.

[0278] The circuit ACTF[j] of the arithmetic circuit 140 includes the switches SWR1P and SWR2P. Switch SWR2P, Switch SWR1PB, Switch SWR2PB, Capacitor CREP, Circuit Each of the ACPs includes a switch SWR1, a switch SWR2, a switch SWR3, a switch SWR4, a switch SWR5, a switch SWR6, a switch SWR7, a switch SWR8, a switch SWR9, a switch SWR11, a switch SWR12, a switch SWR13, a switch SWR14, a switch SWR15, a switch SWR16, a switch SWR17, a switch SWR18, a switch SWR19, a switch S Switch SWR2, switch SWR1B, switch SWR2B, capacitance CRE, circuit AC In addition, the terminals mbt1p and mbt2p of the circuit ACP in FIG. These correspond to the terminals mbt1 and mbt2 of the circuit AC in FIG. , Switch SWR1P, Switch SWR2P, Switch SWR1PB, Switch SWR2 The connection configuration and functions of PB, capacitance CREP, and circuit ACP are shown in Figure 15. Please refer to the explanation of the circuit ACTF[j].

[0279] The first terminal of the switch SWR1M is connected to the circuit IVTR, the terminal T1, and the switch SWR1P. The first terminal of the switch SWR1M is electrically connected to the capacitor CR The first terminal of the switch SWR2MB is electrically connected to the first terminal of the switch EM. The second terminal of the switch SWR2MB is electrically connected to the terminal mbt1m of the circuit ACM. The first terminal of the switch SWR1MB is connected to the circuit IVT Rr, the terminal T2, and the switch SW The first terminal of switch R1PB is electrically connected to the second terminal of switch SWR1MB. , electrically connected to the second terminal of the capacitor CREM and the first terminal of the switch SWR2M. A second terminal of the switch SWR2M is electrically connected to the wiring VCN3.

[0280] The circuit ACM has the same circuit configuration as the circuit ACP, that is, the circuit AC in FIG. 15. The circuit ACP can also set a predetermined potential (for example, GND potential) to the terminal mbt1p. ), as an example, when a potential lower than Similarly, the circuit ACM outputs a predetermined voltage to the terminal mbt1m. For example, when a voltage lower than the GND voltage is input, A digital signal with a value of 0 may be output from m.

[0281] Also, switch SWR1M, switch SWR2M, switch SWR1MB, and switch For example, the above-mentioned switches SWR1 and SW2MB are Use the applicable switches R1B, SWR2, and SWR2B. In addition, here, the switches SWR1M, SWR2M, and SWR1MB, Switch SWR2MB, Switch SWR1P, Switch SWR2P, Switch The switch SWR1PB and the switch SWR2PB each have a high-level potential at their control terminals. When a low-level voltage is input to the control terminal, the device is in the ON state. When a low-level voltage is input to the control terminal, the device is in the OFF state. It shall be as follows.

[0282] Also, switch SWR1M, switch SWR1P, switch SWR1MB, switch S It is preferable that the control terminals of the WR1PB are electrically connected to the same wiring. That is, switch SWR1M, switch SWR1P, switch SWR1MB, switch Each of the SWR1PB switches operates to be on or off at the same time. It is preferable that

[0283] In addition, the control terminals of the switches SWR2M and SWR2P are the same. It is preferable that the switch SWR2M and the switch SWR2M are electrically connected to the wiring. Each SWR2P can be operated so that the other is in the on or off state at the same time. It is preferable that:

[0284] In addition, the control terminals of the switches SWR2MB and SWR2PB are the same. It is preferable that the switch SWR2MB, the switch Each of the SWR2PBs operates to be in the on or off state at the same time. It is preferable that

[0285] Here, in the arithmetic circuit 140 of FIG. 16, the circuit ACTF[j] is connected to the wiring OL[j]. Flowing from I out[j], I flowing from wiring OLB[j] Bout When reading [j] Consider the following. Switch SWR1M, switch SWR1P, switch SWR1MB, Each control terminal of the switch SWR1PB is electrically connected to the wiring SRL1. The control terminals of the switches SWR2M and SWR2P are electrically connected to the wiring SRL2-1. The control terminals of the switches SWR2MB and SWR2PB are connected to the It is assumed that the line SRL2-2 is electrically connected to the line SRL2-2.

[0286] current I out [j] is I Bout If it is greater than [j], as in the example above, At time T04, the potential V of the first terminal of the capacitor CREP Iout is the second end of the capacitance CREP potential V IBout Then, between time T04 and time T05, The voltage between the first and second terminals of the capacitor CREP is maintained from time T06 to time T Between 07 and 1007, the voltage at the second terminal of the capacitor CREP is After time T07, the potential at the end of the circuit ACP becomes higher than the GND potential. The digital signal corresponding to the potential is output from the terminal mbt2p of the circuit ACP. A signal is output.

[0287] On the other hand, at time T04, the potential V of the first terminal of the capacitor CREM Iout is the capacity CRE The potential V of the second terminal of M IBout Then, from time T04 to time T05 During this time, the voltage between the first terminal and the second terminal of the capacitor CREM is maintained, and at time T06 Between time T01 and time T07, the first capacitance of the capacitance CREM is The potential of terminal 1 becomes lower than the GND potential. After time T07, the potential A digital signal with a value of 0 is input to the ACM terminal mbt1m and output from the circuit ACM terminal mbt2m. A digital signal is output.

[0288] That is, the current I out [j] is I Bout When it is greater than [j], the terminals of the circuit ACP Digital signal from mbt2p according to the potential of terminal mbt1p Z is output, and the circuit ACM The GND potential is output from the terminal mbt2m. The positive output signal z output by the circuit ACTF[j] j (k) It can be said that:

[0289] Also, the current I out [j] is I Bout If it is smaller than [j], the same as in the previous example At time T04, the potential V of the first terminal of the capacitance CREP Iout is the capacity of CREP Second terminal potential V IBout Then, from time T04 to time T05 During this time, the voltage between the first and second terminals of the capacitor CREP is maintained, and from time T06 Until time T07, the capacitance of the second terminal of the capacitance CREP is increased by the capacitive coupling of the capacitance CREP. After time T07, the potential of the circuit AC A digital signal with a value of 0 is input to the terminal mbt1p of the P and output from the terminal mbt2p of the circuit ACP. A signal is output.

[0290] On the other hand, at time T04, the potential V of the first terminal of the capacitor CREM Iout is the capacity CRE The potential V of the second terminal of M IBoutThen, from time T04 to time T05 During this time, the voltage between the first terminal and the second terminal of the capacitor CREM is maintained, and at time T06 Between time T01 and time T07, the first capacitance of the capacitance CREM is The potential of terminal 1 becomes higher than the GND potential. After time T07, the potential The potential is input to the terminal mbt1m of the ACM and is output from the terminal mbt2m of the circuit ACM in response to the potential. The digital signal is output.

[0291] That is, the current I out [j] is I Bout When it is smaller than [j], the terminals of the circuit ACP The GND potential is output from mbt2p, and the ACM terminal mbt2m is connected to the terminal mbt1p. A digital signal corresponding to the potential of the two digital signals is output. The negative output signal z output by the circuit ACTF[j] j (k) It can be said that:

[0292] <Configuration example 3 of an arithmetic circuit> In the arithmetic circuit 130 shown in FIG. 12, the wiring IL[j ], wiring ILB[j], wiring OL[j], and wiring OL[j] are electrically connected. However, one embodiment of the present invention is not limited to this. L[j] and wiring OL[j] are collectively called wiring OL[j], and wiring ILB[j] and wiring O LB[j] can be combined into a wiring OLB[j].

[0293] An example of the configuration of this arithmetic circuit is shown in Fig. 17. The arithmetic circuit 150 shown in Fig. 17 is a circuit diagram of the arithmetic circuit 13. 0, the wiring IL[j] and the wiring OL[j] are collectively referred to as wiring OL[j], and the wiring I LB[j] and wiring OLB[j] are combined into wiring OLB[j].

[0294] The arithmetic circuit 150 also includes switching circuits TW[1] to TW[n]. Each of the switching circuits TW[1] to TW[n] has a terminal TSa and a terminal TSaB. , a terminal TSb, a terminal TSbB, a terminal TSc, and a terminal TScB. Sa is electrically connected to the wiring OL[j], and the terminal TSbB is electrically connected to the circuit ILD. The terminal TSc is electrically connected to the circuit ACTF[i]. LB[j], terminal TSbB is electrically connected to circuit ILD, and terminal T ScB is electrically connected to the circuit ACTF[j].

[0295] The switching circuit TW[j] connects the terminal TSa to either the terminal TSb or the terminal TSc. and put terminal TSa into a conductive state and put terminal TSa into a non-conductive state with the other of terminal TSb and terminal TSc. The switching circuit TW[j] has a function of switching between the terminal TSaB and the terminal TSbB or and one of the terminals TScB, and cB and the other terminal cB.

[0296] That is, the weighting coefficient 1 is added to one of the circuits MP[1,j] to MP[m,j]. 1 data w1 (k-1) 1 (k) Or even w m (k-1) n (k) Information corresponding to (e.g., If you want to input a value such as potential, resistance, or current, in the switching circuit TW[j], The TSa and TSb terminals are connected to each other, and the TSaB and TSbB terminals are connected to each other. By setting the circuit ILD to ON, the first data is transmitted from the circuit ILD to the wiring OL[j] and the wiring OLB[j]. Ta w1 (k-1) 1 (k) Or even w m (k-1) n (k) Information corresponding to (e.g., potential, Resistance, current, etc.) can be supplied.

[0297] Also, the circuit ACTF[j] is calculated by the circuits MP[1,j] to MP[m,j]. We want to obtain the result of the sum of products (equation (1.2)) of the weight coefficients and the neuron signal values. In this case, the switching circuit TW[j] makes the terminals TSa and TSc conductive. , and by bringing the terminals TSaB and TScB into a conductive state, the wiring OL[j] and The wiring OLB[j] sends information according to the result of the sum of products (for example, In addition, in the circuit ACTF[j], the input The activation function value is calculated from the sum of products, and is used as the output signal of the neuron. signal z j (k) can be obtained.

[0298] Next, regarding the switching circuit TW[j] and the circuit ILD included in the arithmetic circuit 150, FIG. 18A shows a switching circuit TW[ j] and the circuit ILD. In FIG. 18A, the switching circuit TW In order to show the electrical connection configuration between the wiring OL[j] and the circuit ILD, LB[j] and the circuit AFP are also shown.

[0299] The switching circuit TW[j] includes, for example, a switch SWI, a switch SWIB, and a switch switch SWO, switch SWOB, switch SWL, and switch SWLB. do.

[0300] The circuit ILD includes, for example, a current source circuit ISC. The configuration can be the same as that of the current source circuit ISC of the circuit ILD in FIG. 14A. Therefore, the current source circuit ISC in FIG. 18A is a circuit included in the circuit ILD in FIG. 14A. Please refer to the explanation of ISC.

[0301] The switches SWI, SWIB, SWO, and The switches SWOB, SWL, and SWLB are, for example, the switches SWR1, switch SWR1B, switch SWR2, and switch SWR2B are also applicable. Any switch that can be used can be used.

[0302] In one example of the switching circuit TW[j], the terminal TSa is connected to the first terminal of the switch SWI. , electrically connected to a first terminal of the switch SWO and a first terminal of the switch SWL. The terminal TSaB is connected to the first terminal of the switch SWIB, the first terminal of the switch SWOB, A first terminal of the switch SWLB is electrically connected to a second terminal of the switch SWI. The second terminal of the switch SWIB is electrically connected to the terminal TSb1. The second terminal of the switch SWO is electrically connected to the terminal TSc. The second terminal of switch SWOB is electrically connected to terminal TScB. The second terminal of the switch SWL is electrically connected to the terminal TSb2. The second terminal of WLB is electrically connected to the terminal TSbB2.

[0303] The terminals TSb1 and TSb2 shown in FIG. 18A are the same as the terminals shown in FIG. The terminals TSbB1 and TSbB2 shown in FIG. 2 corresponds to the terminal TSbB shown in FIG.

[0304] The wiring VCN is the wiring OL[j] and / or the wiring OL[j] in the same manner as the wiring VCN of the circuit ILD in FIG. 14A. functions as a wiring that supplies a constant voltage to the wiring OLB[j]. For the wiring VCN of A, please refer to the description of the wiring VCN in FIG. 14A.

[0305] The switching circuit TW[j] consists of switches SWI, SWIB, SWO, and Switch SWOB, switch SWL, and switch SWLB are each in the on or off state. By switching to the can be changed.

[0306] For example, when you want to input a positive weighting coefficient to the circuit MP, you can input the weighting coefficient to the wiring OL[j]. A current according to the voltage Vc is input, and a constant potential given by the wiring VCN is input to the wiring OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] are brought into a conductive state, and the current source circuit I The connection between SC and wiring OLB[j] is made non-conductive, and the connection between circuit AFP and wiring OL[j] is made non-conductive. The circuit AFP and the wiring OLB[j] are in a non-conducting state, and the wiring VCN and The wiring OL[j] is in a non-conductive state, and the wiring VCN and wiring OLB[j] are in a conductive state. That is, in the switching circuit TW[j], the switches SWI and Switch SWLB is turned on, and switches SWIB, SWO, and SWOB are turned on. , and the switch SWL are turned off. Since the connection between C and the wiring OL[j] is established, the current source circuit ISC ], current can flow through the circuit MP. Also, the wiring VCN and wiring OLB[j] Since the line between them is in a conductive state, a constant voltage is input from the line VCN to the line OLB[j]. can be.

[0307] Also, for example, when a negative weighting coefficient is to be input to the circuit MP, the corresponding weighting coefficient is input to the wiring OLB[j]. If you input a current according to the load coefficient and input the constant potential given by the wiring VCN to the wiring OL[j], As an example, the current source circuit ISC and the wiring OL[j] are brought into a non-conductive state, and the current The power supply circuit ISC and the wiring OLB[j] are in a conductive state, and the circuit AFP and the wiring OL[j] are in a conductive state. and the circuit AFP and the wiring OLB[j] are in a non-conductive state, and the wiring V The connection between CN and wiring OL[j] is made conductive, and the connection between wiring VCN and wiring OLB[j] is made non-conductive. That is, in the switching circuit TW[j], the switch SWIB , and switch SWL are turned on, and switches SWI, SWO, and SW OB and the switch SWLB are turned off. Since the current source circuit ISC and the wiring OLB[j] are in a conductive state, Current can flow through the circuit MP via OLB[j]. Since the line between L[j] and OL[j] is in a conductive state, a constant voltage from the line VCN is applied to the line OL[j]. is entered.

[0308] Also, for example, when you want to input a weight coefficient of 0 to the circuit MP, wiring OL[j], wiring OL The constant potential given by the wiring VCN can be input to each of B[j]. The current source circuit ISC and the wiring OL[j] are in a non-conductive state, and the current source circuit ISC and the wiring OLB [j] is put into a non-conductive state, and the circuit AFP and wiring OL[j] are put into a non-conductive state, The circuit AFP and the wiring OLB[j] are in a non-conductive state, and the wiring VCN and the wiring OL[j] are in a non-conductive state. and the wiring VCN and the wiring OLB[j] should be in a conductive state. That is, in the switching circuit TW[j], the switches SWL and SWLB are turned on. The states of the switches SWI, SWIB, SWO, and SWOB are By doing so, the conduction between the wiring VCN and the wiring OL[j] is Since the wiring VCN and wiring OLB[j] are in a conductive state, the wiring OL[ A constant voltage is input from the line VCN to the line OLB[j] and the line OLB[j].

[0309] Also, for example, information (e.g., potential, current, etc.) from circuit MP[i,j] to circuit AFP When supplying current, for example, the current source circuit ISC and the wiring OL[j] are in a non-conductive state. The current source circuit ISC and the wiring OLB[j] are in a non-conductive state, and the circuit AFP and the wiring OLB[j] are in a non-conductive state. Establish a state of continuity between the line OL[j] and the circuit AFP and the wiring OLB[j]. Then, the wiring VCN and the wiring OL[j] are disconnected, and the wiring VCN and the wiring OLB[j ] is in a non-conductive state. Switch SWO and switch SWOB are turned on, and switches SWI and SWIB are turned on. In this case, the switches SWL and SWLB are turned off. Therefore, the circuit AFP and the circuit MP[i,j] are in a conductive state, and the circuit MP[i,j] The circuit AFP can be supplied with information (e.g., potential, current, etc.).

[0310] Note that the switching circuit TW[j] and the circuit The circuit ILD is not limited to the circuit configuration shown in FIG. The circuit configuration of each of the circuits ILD can be changed depending on the situation. For example, Switches SWH and SWHB are added to the switching circuit TW[j] shown in 8A, The circuit ILD may be provided with a wiring VCN2. An example of such a configuration is shown in FIG.

[0311] In FIG. 18B, the first terminal of the switch SWH is electrically connected to the wiring OL[j]. The second terminal of the switch SWH is electrically connected to the wiring VCN2. The first terminal of the switch SWHB is electrically connected to the wiring OLB[j], and the The two terminals are electrically connected to the wiring VCN2.

[0312] The line VCN2 supplies a constant voltage to the line OL[j] and / or the line OLB[j]. For example, the wiring from the circuit ILD through the switching circuit TW[j] When a current (positive current) flows through the line OL or the wiring OLB, the constant voltage given by the wiring VCN2 is It is preferable to set the potential to a high level (for example, VDD). A current (negative current) flows from OL or wiring OLB to the circuit ILD via the switching circuit TW[j]. ) flows, the constant potential given by the wiring VCN2 is the ground potential or a low level potential ( In particular, the voltage applied by the wiring VCN4 is preferably VSS or the like. It is preferable to use the wiring VCN4 explained with reference to FIG. 6C.

[0313] In the circuit configuration of FIG. 18B, the switches SWI, SWIB, and SWO, Switches SWOB, SWL, and SWLB are turned off, and switch S By turning on the switch WH and the switch SWHB, the wiring OL[j] and the wiring O LB[J] and the voltage given by the wiring VCN2 can be input to each of them. For example, the voltage applied by the wiring VCN2 may be the same as that applied by the wiring VCN4 described with reference to FIGS. 6A to 6C. When the voltage is the same, from time T01 to time T02 in the operation example of the timing chart of Figure 9 During this time, the switches SWR3 and SWR3B are not in the on state, but in the By turning on the switches SWH and SWHB, the wiring OL[j] and wiring O The same voltage as that of the wiring VCN4 can be applied to LB[j]. In other words, the circuit in FIG. By applying the configuration to the arithmetic circuit 140, the circuit IVTR (circuit The switch SWR3 (switch SWR3B) shown in the figure can be omitted. do.

[0314] Here, an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 150 will be described.

[0315] FIG. 19A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 150. Specifically, the circuit MP[i,j] in FIG. 19A has the configuration of the circuit MP[i,j] in FIG. 13A. The modified circuit is the wiring IL[j] and wiring OL[j] of the circuit MP[i,j] in FIG. 13A. ] and wiring ILB[j] and wiring OLB[j] are combined into one Therefore, for the circuit MP[i,j] in FIG. 19A, the circuit M in FIG. Please refer to the explanation of P[i,j].

[0316] Next, an example of a modification of the circuit MP[i,j] in FIG. 19A will be described. The modified example of P[i,j] will be mainly explained with respect to the parts different from the circuit MP[i,j] of FIG. 19A. 19A. Therefore, explanation of the parts common to the circuit MP[i,j] in FIG. 19A may be omitted. do.

[0317] The circuit MP[i,j] shown in FIG. 19B is the circuit MP[i,j] shown in FIG. 19A. The wiring X1L[i] is replaced with the wiring WX1L[i]. In the circuit MP[i,j], the wiring WX1L[i] and the wiring WL[i] are connected to the wiring OL[j ] and the holding part HC, and the wiring OLB[j] and the holding part HC are switched to a conductive state or a non-conductive state. A predetermined potential is supplied to switch the state between the holding part HCr and the conductive state or the non-conductive state. In the circuit MP[i,j] of FIG. 19B, the wiring WX1 L[i] and the wiring X2L[i] are connected to the second data z i (k- 1) It functions as a wiring that supplies a current, voltage, etc. according to the The path configuration will be explained in the third embodiment.

[0318] Next, an example of a modification of the circuit MP[i,j] in FIG. 19A, which is different from that in FIG. 19B, will be explained. The circuit MP[i,j] shown in FIG. 19C is a modified example of the circuit MP[i,j] shown in FIG. The circuit MP[i,j] in FIG. 19C is similar to the circuit MP[i,j] in FIG. 19C includes a circuit MC and a circuit MCr. It differs from the circuit MP[i,j] in FIG. 19A in that r does not include the holding unit HCr.

[0319] Also, since the circuit MCr does not have the holding unit HCr, the circuit MP[i,j] in FIG. The arithmetic circuit to which this is applied does not have wiring for supplying the potential to be held to the holding unit HCr. In addition, the circuit MCr may not be electrically connected to the wiring WL[i].

[0320] In the circuit MP[i,j] of FIG. 19C, the holding unit HC included in the circuit MC r. That is, the circuit MP[i,j] in FIG. 19C is electrically connected to the circuit MCr. The circuit MC and the holding unit HC are configured to share the holding unit HC. The inverted signal of the signal held in the holding unit HC is supplied from the holding unit HC to the circuit MCr. This allows the circuits MC and MCr to operate differently. Alternatively, the internal circuit configurations of the circuits MC and MCr may be different. As a result, the same signal held in the holding unit HC is output by the circuit MC and the circuit MCr. It is also possible to make the magnitude of the current flowing through the holding unit HC different. w i (k-1) j (k) and holds the potential according to the second data z i (k-1) Potential according to to the wiring X1L[i] and the wiring X2L[i], the circuit MP[i,j] is the first data w i (k-1) j (k) and the second Data z i (k-1) It is possible to output a current according to the product of The specific circuit configuration will be explained in the third embodiment.

[0321] The circuit MP[i,j] shown in FIG. 19D is a modification of the circuit MP[i,j] in FIG. 19A. , which is a modification of the circuit MP[i,j] of FIG. 13C. Specifically, the circuit MP[i,j] of FIG. In FIG. 13C, the wiring IL[j] and the wiring OL[j] are connected to one wiring OL[j ] and combine the wiring ILB[j] and wiring OLB[j] into one wiring OLB[j] Therefore, the circuit MP[i,j] in FIG. 19D is Please refer to the description of the circuit MP[i,j] in FIG. 13C.

[0322] The circuit MP[i,j] shown in FIG. 19E is a modified example of the circuit MP[i,j] in FIG. 19A. , which is a modification of the circuit MP[i,j] of FIG. 13D. Specifically, the circuit MP[i,j] of FIG. i,j] is a configuration in which the wiring IL[j] and the wiring ILB[j] are not provided in FIG. 13D. Therefore, the circuit MP[i,j] in FIG. 19D is configured as the circuit in FIG. 13D. Please refer to the explanation of MP[i,j].

[0323] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0324] (Embodiment 3) In this embodiment, a specific configuration of the circuit MP described in the first and second embodiments will be described. An example will be described.

[0325] In the first and second embodiments, the reference numerals of the circuits MP are used to indicate the positions within the array unit ALP. Although notations such as [1,1], [i,j], and [m,n] are used to indicate the positions, in this embodiment, Unless otherwise specified, the symbols for circuit MP are written as [1,1], [i,j], [m,n], etc. Omitted.

[0326] <Configuration example 1> First, an example of a circuit configuration that can be applied to the circuit MP of FIG. 13A will be described. The circuit MP shown in FIG. 13A is an example of the configuration of the circuit MP of FIG. 20A. The circuit MC includes, for example, a transistor M1 and switches S2 to S5. For example, the switch S2, the switch S5, and the capacitance C1 The holding portion HC is configured by these.

[0327] The switches S2 to S5 may be electrical switches or mechanical switches. The electrical switch may be, for example, a transistor. That is, the switches S2 to S5 are transistors similar to the transistor M1. In particular, the switch S2 has a function to hold the potential at the first terminal of the capacitor C1 for a long time. Therefore, it is preferable to use an OS transistor with extremely low off-state current. The transistor will be described in detail in the fifth embodiment.

[0328] In the circuit MP of FIG. 20A, the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are To distinguish it from the above, the symbol is prefixed with "r."

[0329] The transistor M1 shown in FIG. 20A has, as an example, gates above and below the channel. The transistor M1 is an n-channel transistor with a multi-gate structure having It has a first gate and a second gate. However, in this specification and the like, for convenience, as an example, The first gate is the gate (sometimes referred to as the front gate), and the second gate is the back gate. Although the gates are listed to distinguish them as separate gates, the first gate and the second gate are interchangeable. Therefore, in this specification, the term "gate" is used to mean "back gate." " can be written interchangeably with the phrase "back gate." can be written interchangeably with the word "gate." is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring. The connection configuration is such that "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring." For example, the connection configuration shown in Figure 20 can be replaced with "electrically connected." As shown in B, the back gate of the transistor M1 is connected to the first terminal of the capacitor C1 and the switch S The second terminal may be electrically connected to the first terminal of the first power supply.

[0330] Furthermore, the semiconductor device of one embodiment of the present invention can be used without depending on the connection structure of the back gate of the transistor. The transistor M1 shown in FIG. 20A has a back gate. Although the connection configuration of the back gate is not shown, the electrical connection of the back gate is The connection destination can be determined at the design stage. For example, a transistor with a back gate In order to increase the on-current of the transistor, the gate and back gate are electrically connected. That is, for example, the gate and back gate of the transistor M1 may be electrically connected. For example, in a transistor having a back gate, In order to change the threshold voltage of the transistor, or to change the off-current of the transistor, In order to reduce the noise, wiring electrically connected to an external circuit is provided. A potential may be applied to the back gate of the transistor by a path or the like. 20A as well as transistors described elsewhere in the specification or other figures. The same is true for the transistors shown on the surface.

[0331] In addition, a semiconductor device according to one embodiment of the present invention may include a transistor having a structure For example, the transistor M1 shown in FIG. 20A is Therefore, it is a transistor with a single gate structure, which does not have a back gate. In addition, some of the transistors may have a back gate, and another The transistors in the second embodiment may have a configuration without a back gate. is a transistor described in the circuit diagram shown in FIG. 20A as well as elsewhere in the specification. , or the transistors shown in other figures.

[0332] In this specification and the like, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples include transistors with single crystal silicon, or transistors with amorphous silicon, polycrystalline silicon, etc. Silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) A transistor having a non-single-crystal semiconductor film, such as a silicon nitride film, can be used. Alternatively, thin film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, it is Since it can be manufactured at a very low temperature, it is possible to reduce manufacturing costs and increase the size of manufacturing equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, they can be manufactured at low cost. Therefore, a substrate having low heat resistance can be used. Alternatively, a transistor on a light-transmitting substrate can be used to manufacture a display element. It is possible to control the light transmission. Also, because the film thickness of the transistor is thin, A part of the film that forms the photodiode can transmit light, which improves the aperture ratio. It is possible.

[0333] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having a material such as n-Sn-Zn-O can be used. These compound semiconductors or thin film transistors made by thinning these oxide semiconductors These can lower the manufacturing temperature, so that, for example, As a result, it is possible to manufacture a resistor on a substrate with low heat resistance, such as a plastic The transistor can be formed directly on a substrate or a film substrate. Compound semiconductors or oxide semiconductors are used not only for the channel portion of transistors but also for For example, these compound semiconductors or oxide semiconductors can be used for other purposes. It can be used as a wiring, a resistor element, a pixel electrode, or a light-transmitting electrode. These can be deposited or formed simultaneously with the transistor, thereby reducing costs.

[0334] An example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, manufacturing at low vacuum, or can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. Or, since it is possible to apply the film only to the necessary parts, it is possible to apply the film only to the necessary parts after forming the film on the entire surface. This method wastes less material and can be produced at a lower cost than the etching method.

[0335] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. This allows transistors to be mounted on a flexible substrate. Transistors using organic semiconductors and carbon nanotubes can be formed. The device using this can be made shock resistant.

[0336] Note that transistors with various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A MOS transistor can be used as the transistor. By using this, the size of the transistor can be reduced. It is possible to mount a bipolar transistor as a transistor. This allows a large current to flow, making it possible to operate the circuit at high speed. It is also possible to combine MOS transistors and bipolar transistors on the same substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc. can.

[0337] An example of a transistor is a structure in which gate electrodes are arranged above and below an active layer. The transistor can be applied to a structure in which gate electrodes are arranged above and below the active layer. This results in a circuit configuration in which multiple transistors are connected in parallel. Since the channel forming region increases, the current value can be increased. The structure in which gate electrodes are arranged above and below makes it easier for a depletion layer to form. , the S value can be improved.

[0338] An example of a transistor is a structure in which a gate electrode is disposed on an active layer. A structure in which a gate electrode is placed under an active layer, a normal staggered structure, an inverted staggered structure, a channel A structure in which the region is divided into multiple regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series Alternatively, a transistor having a structure such as a pre-transistor may be used. NA type, FIN type, TRI-GATE type, top gate type, bottom gate type, double gate type (gates are placed above and below the channel), etc. A variety of configurations can be used.

[0339] An example of a transistor is a transistor in which a source electrode or a drain electrode is formed in the active layer (or a part thereof). A transistor with an overlapping active layer (or its equivalent) can be used. By using a structure in which the source electrode and drain electrode overlap with part of the active layer, This can prevent the operation from becoming unstable due to accumulation of electric charges.

[0340] As an example of a transistor, a structure provided with an LDD region can be applied. By providing a region, the off-state current can be reduced or the withstand voltage of the transistor can be improved (reliability can be improved). Alternatively, by providing an LDD region, it is possible to , the drain current does not change much even if the voltage between the drain and source changes. The current characteristics can be obtained.

[0341] For example, in this specification and the like, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, sapphire glass substrate, metal substrate, stainless steel substrate, stainless Substrate with less steel foil, tungsten substrate, tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, base film, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Glass or soda lime glass. Flexible substrates, laminating films, base film Examples of films include polyethylene terephthalate. Polyethylene naphthalate (PET), Polyethersulfone (PES) ), and polytetrafluoroethylene (PTFE) are typical plastics. For example, synthetic resin such as acrylic resin is used. Examples include polyethylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and the like. In particular, transistors are manufactured using semiconductor substrates, single crystal substrates, or SOI substrates. By manufacturing the capacitors, there is little variation in characteristics, size, or shape, and current capacity is This allows for the production of high-power, small-sized transistors. By configuring a circuit using a capacitor, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit. Cut.

[0342] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic film such as a tungsten film and a silicon oxide film. It uses a laminated film structure or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0343] That is, a transistor is formed using one substrate, and then a transistor is formed on another substrate. The transistor may be transposed onto another substrate. For example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more flexible device.

[0344] All circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate such as a silicon substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. This reduces the cost by reducing the number of components, or reduces the number of connections to circuit components. This can improve reliability.

[0345] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function can be formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a given function can be Another part of the circuitry required to realize a specific function is formed on the single crystal substrate. It can be formed on a substrate (or SOI substrate) and realizes a predetermined function. The single crystal substrate (also called an IC chip) on which another part of the circuitry required for (Chip On Glass) connects to the glass substrate and Alternatively, the IC chip can be mounted on a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology) or a printed circuit board. In this way, part of the circuit is formed on the same substrate as the pixel section. This reduces the number of components, thereby reducing costs, and This reduces the number of circuits, which improves reliability. Also, circuits with high drive frequencies often consume a lot of power. Therefore, such a circuit is formed on a substrate (for example, a single crystal substrate) separate from the pixel section, and By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0346] In the circuit MP of FIG. 20A, a first terminal of the transistor M1 is electrically connected to the wiring VE. The second terminal of transistor M1 is connected to the first terminal of switch S3 and the second terminal of switch S4. The first terminal of the transistor S4 is electrically connected to the first terminal of the switch S5. The gate of M1 is electrically connected to a first terminal of a capacitor C1 and a first terminal of a switch S2. The second terminal of the capacitor C1 is electrically connected to the wiring VE. The second terminal is electrically connected to the second terminal of the switch S5 and the line IL. The control terminal of switch S2 is electrically connected to line WL. The second terminal of switch S3 is electrically connected to line WL. The control terminal of switch S3 is electrically connected to line OL, and the control terminal of switch S4 is electrically connected to wire X1L. The second terminal of the switch S4 is electrically connected to the wiring OLB. The terminal is electrically connected to the wiring X2L.

[0347] The circuit MCr has a different connection configuration from the circuit MC. The second terminal is electrically connected to the wiring OLB instead of the wiring OL, and the second terminal of the switch S4r The first terminal of the transistor M1r is electrically connected to the wiring OL, not to the wiring OLB. The first terminal and the first terminal of the capacitor C1r are electrically connected to the wiring V Er.

[0348] The configuration of the circuit MP in FIG. 20A may be changed to the configuration of the circuit MP in FIG. 21A. Specifically, the first terminal of the transistor M1 is electrically connected to another wiring VEm, not to the wiring VE. The first terminal of the transistor M1r is connected to another wiring VEmr instead of the wiring VEr. It should be noted that the circuit MP in FIG. 20A may be electrically connected to the circuit in other drawings. In the circuit diagram, the first terminal of transistor M1 is connected to another wire VEm, not to wire VE. and / or the first terminal of the transistor M1r is electrically connected to the wiring V It may be configured so that it is electrically connected to another wiring VEmr instead of Er.

[0349] In the holding unit HC shown in FIG. 20A, the gate of the transistor M1 and the The electrical connection point between the first terminal and the first terminal of the switch S2 is referred to as a node n1.

[0350] As described in the first embodiment, the holding unit HC holds, for example, an electric current corresponding to the first data. The potential to the holding unit HC included in the circuit MC of FIG. When the switches S2 and S5 are turned on, a potential is input from the wiring IL. This is done by inputting a voltage to write into the capacitor C1, and then turning off the switch S2. This allows the potential of the node n1 to be maintained as a potential according to the first data. At this time, a current is input from the wiring OL, and a potential of a magnitude corresponding to the magnitude of the current is generated. Therefore, the influence of the variation in the current characteristics of the transistor M1 can be suppressed. This can reduce the noise.

[0351] In addition, since the transistor M1 holds the potential of the node n1 for a long time, the off-state current is small. It is preferable to use a transistor with a low off-state current. For example, an OS transistor can be used. A transistor having a gate is applied, and a low level potential is applied to the back gate to obtain a threshold voltage. Alternatively, the voltage may be shifted to the positive side to reduce the off-state current.

[0352] In the operation example described later, in order to simply explain the current flowing in and out of the circuit MP, One end of the wiring IL shown in 20A is the node ina, and one end of the wiring OL is the node outa. One end of the wiring ILB is a node inb, and one end of the wiring OLB is a node outb.

[0353] The wiring VE functions as a wiring for supplying a constant voltage, for example. switch S3, switch S3r, switch S4, or switch S4r is n-channel In the case where the transistor is a quartz-type transistor, and / or the wiring VSO is provided in FIGS. 14A to 14C, If the potential to be applied is a high level potential, for example, VSS, which is a low level potential, or ground potential , or other low level potentials. The wiring VEr and wiring VEmr are voltage lines that supply a constant voltage, just like the wiring VE. The constant voltage includes VSS, which is a low-level potential, a low-level potential other than VSS, The constant voltage may be a high level potential VD In this case, the circuit IVTR (circuit IVTRr) of the arithmetic circuit 110 may be When any of the circuits ACTF[1] to ACTF[2] is applied, the circuit ACTF[3] is applied. The constant voltage applied by the wiring VCN4 electrically connected to [n] is It is preferable that the potential be higher than the potential VDD given by Er.

[0354] In addition, the constant voltages supplied by the wiring VE, wiring VEm, wiring VEr, and wiring VEmr are The pressures may be different from each other, or some or all of them may be the same. If the wires supply the same voltage, select them and treat them as the same wire. For example, the wiring VE, wiring VEm, wiring VEr, and wiring VEmr are given When the constant voltages are almost equal, as shown in the circuit MP of Figure 21B, the wiring VEm, wiring VEr, and wiring VEmr can be the same wiring as wiring VE. Or, for example, wiring VE, wiring When the constant voltages applied to the wiring VE and the wiring VEr are almost equal, Alternatively, in FIG. 21A, for example, the wiring VE and the wiring V Er is considered to be one and the same wiring, and wiring VEm and wiring VEmr are considered to be one and the same wiring. Alternatively, for example, the wiring VE and the wiring VEmr may be treated as one and the same wiring, and the wiring V Em and the wiring VEr may be one and the same wiring (not shown).

[0355] The configuration of the circuit MP in Figure 20A can be changed depending on the situation. For example, As shown in FIG. 22A, the transistors M1 and M1r in the circuit MP of FIG. 20A The transistors M1p and M1pr are p-channel transistors, respectively. In this case, the constant voltage given by the wiring VE and wiring VEr is In addition to this case, it is preferable to set the voltage to VDD, which is the voltage of the arithmetic circuit 110. The circuits IVTR and IVTRR included in the circuits ACTF[1] to ACTF[n] 6A to 6C is applied, the constant voltage applied by the wiring VCN4 is It is preferable to set the potential of the wiring to ground potential or VSS. This also changes the direction of current flow.

[0356] 22B, for example, the switches S3 and S4 of the circuit MP of FIG. 20A 3r, switch S4, and switch S4r are respectively referred to as analog switch AS3, analog switch AS4, and analog switch AS5. The analog switches may be analog switches AS4, AS3r, and AS4r. In FIG. 22B, analog switches AS3, AS4, and To operate the analog switch AS3r and analog switch AS4r, wires X1LB and X2LB are also The wiring X1LB supplies power to the analog switches AS3 and AS3r. The wiring X2LB is electrically connected to the analog switch AS4 and analog switch AS4r. The wiring X1LB is electrically connected to the inverted signal of the signal input to the wiring X1L. is input to the line X2LB, and an inverted signal of the signal input to the line X2L is input to the line X2LB. In addition, wires X1L and X2L are combined into one wire, and wires X1LB and X2LB are combined into one wire. Alternatively, the analog switch may be connected to a single wiring (not shown). switch AS3, analog switch AS4, analog switch AS3r, and analog switch The AS4r is a CMO using n-channel and p-channel transistors. It may also be configured as an S configuration.

[0357] Also, the switch S3 shown in FIGS. 20A to 20C, 21A, 21B, and 22A, When transistors are applied to the switches S3r, S4, and S4r, It is preferable that the respective sizes, for example, the channel length and the channel width, are equal to each other. By using such a circuit configuration, it is possible to achieve an efficient layout. The currents flowing through the switches S3, S3r, S4, and S4r are made uniform. Similarly, it is possible to make the following changes in the configuration shown in FIGS. 20A to 20C, 21A, and 21B. It is preferable that the sizes of the transistors M1 and M1r shown in FIG. Similarly, the switch S2 shown in FIGS. 20A to 20C, 21A, and 21B When transistors are applied to the switch S2r, the size of each transistor is Preferably, they are equal to each other. <<Example 1>> Next, an example of the operation of the circuit MP shown in Figure 20A will be described. 24A to 24C and 25A to 25C are timing diagrams showing an example of the operation of the circuit MP. The charts are for the wire WL, the wire X1L, the wire X2L, the node n1, and the node n. 23A to 23C, 24A to 24C, In each of FIGS. 25A to 25C, "high" indicates a high level potential, and "low" indicates a low level potential. indicates a low level potential. In this operation example, the voltage ( Or, the amount of current input from the wiring IL to the node ina is I IL Then, from node inb The amount of current input from the wire ILB to the node inb is I ILB Also, from wiring OL to node outa (or from node outa to wiring OL) ) The amount of current output is I OL Then, from wiring OLB to node outb (or node o The amount of current output from utb to wiring OLB is I OLB 23A to 23 In the timing charts shown in FIGS. 24A to 24C and 25A to 25C, the current Quantity I IL , I ILB , I OL , I OLB The change in the

[0358] In this operation example, the constant voltages given by the wiring VE, wiring VEm, wiring VEr, and wiring VEmr In this case, in FIG. 14A, the wiring VSO is connected to a high level. A bell potential is applied, and a current flows from the wiring VSO through the wiring OL to the wiring VE or the wiring VEr. Similarly, the current flows from the wiring VSO through the wiring OLB to the wiring VE or wiring V In the circuit configuration shown in FIG. 14A, the wiring VCN The potential to be applied is VSS. When the line VCN and the second terminal of the transistor M1 are in a conductive state, By doing so, the second terminal of transistor M1 is connected to VSS. At this time, the potential of the gate of transistor M1 also becomes VSS, Similarly, the line VCN and the second terminal of the transistor M1r are connected to each other. By making the transistor M1r conductive, the potential of the second terminal and gate of the transistor M1r is VSS. Therefore, the transistor M1r is turned off.

[0359] In this operation example, the circuit IVTR (circuit IVTRr) included in the circuit ACTF is , the circuit IVTR (circuit IVTRr) shown in FIG. 6A. In R (circuit IVTRr), the potential given by the wiring VCN4 is VDD.

[0360] In the circuit MP shown in FIG. 20A, when the switches S2 and S5 are in the on state, The transistor M1 is configured as a diode. Therefore, the current from the wiring OL to the circuit MC is When a current flows, the second terminal of the transistor M1 and the gate of the transistor M1 are connected to each other. The potentials are almost equal. The potentials are determined by the amount of current flowing from the wiring OL to the circuit MC and the The potential of the first terminal of transistor M1 (here, VSS) is determined by the The potential of the gate of the transistor M1 is held by the capacitor C1, and then the switch S2 is turned off. By this, the transistor M1 outputs a current according to the potential of the gate of the transistor M1. Therefore, it functions as a current source that can reduce the influence of variations in the current characteristics of transistor M1. can be reduced.

[0361] For example, when the switches S2 and S5 are in the ON state, When a current of I1 flows through the wiring VE, the voltage of the gate (node ​​n1) of the transistor M1 is Here, by turning off the switch S2, V1 is held by the holding unit HC. The potential VSS of the first terminal of the transistor M1 and the current I 1 can be passed between the source and drain of the transistor M1. Such an operation is called "transistor M1 is a transistor that operates by controlling the current flowing between the source and drain of transistor M1." This is referred to as "the flow rate has been set (programmed) to I1".

[0362] In this operation example, the amount of current flowing from the wiring OL to the circuit MC is set to three levels: 0, I1, and I2. Therefore, the amount of current set to the transistor M1 is 0, I1, and I2. For example, if the potential of the gate of the transistor M1 held in the holding unit HC is VSS, Since the potentials of the first and second terminals of the transistor M1 are also VSS, If the threshold voltage of transistor M1 is higher than 0, transistor M1 is in an off state. Therefore, no current flows between the source and drain of transistor M1. It can be said that the amount of current flowing between the source and drain of 1 is set to 0. For example, if the potential of the gate of the transistor M1 held in the holding unit HC is V1, When the threshold voltage of transistor M1 is lower than V1-VSS, M1 is turned on. At this time, the amount of current flowing through the transistor M1 is I1. Therefore, when the potential of the gate of transistor M1 is V1, the source of transistor M1 is It can be said that the amount of current flowing between the drains is set to I1. When the potential of the gate of the transistor M1 held in the holding unit HC is V2, If the threshold voltage of transistor M1 is lower than V2-VSS, transistor M1 is on. At this time, the amount of current flowing through the transistor M1 is I2. When the gate potential of the transistor M1 is V2, the source-drain It can be said that the amount of current flowing through is set to I2.

[0363] The current amount I1 is greater than 0 and less than I2. The threshold voltage of transistor M1 is set to be higher than VSS and lower than V2. The value voltage is higher than 0 and lower than V1-VSS. In the explanation of FIG. 14A, I generated by the constant current source circuit ISC1 ut can be replaced with In addition, I2 is, for example, the current generated by the constant current source circuit ISC2 in the description of FIG. 14A. 2I ut can be replaced with

[0364] Before explaining the operation example, the first data (for example, weight The coefficient is defined as follows: VSS is set to node n1 of the holding unit HC, and the holding unit HCr When VSS is held at node n1r, circuit MP uses the first data (weighting coefficient) The node n1 of the holding unit HC holds V1, and the node n2 of the holding unit HCr holds V2. When VSS is held in the node n1r, the circuit MP uses " +1” is stored in node n1 of the storage unit HC. When VSS is held in node n1r, circuit MP uses "+" as the first data (weighting coefficient). 2” is held at node n1 of the holding unit HC and VSS at node n2 of the holding unit HCr. When V1 is held in node n1r, circuit MP sets "-1" as the first data (weighting coefficient). " is held at node n1 of the holding unit HC, VSS is held at node n2 of the holding unit HCr, and When V2 is held in n1r, circuit MP sets "-2" as the first data (weighting coefficient). It is assumed that the following is held:

[0365] Also, the second data input to the circuit MP (for example, the value of the neuron signal (operation ) is defined as follows as an example: high level potential is applied to the wiring X1L, and When a low level potential is applied to 2L, the circuit MP receives the second data (neuron signal "+1" is input as the value of the signal. A low level potential is input to the wire X1L, and a high level potential is input to the wire X2L. When the level potential is applied, the circuit MP stores the second data (the value of the neuron's signal) A low-level potential is input to the wire X1L, and a low-level potential is input to the wire X2L. When the potential is applied, the circuit MP receives the second data (value of the neuron signal) 0” is input. As an example, the high level potential is VDD or Or, the potential shall be 10% or more, or 20% or more higher than VDD.

[0366] In this specification and the like, the transistors M1 and M1r are If there is no such case, the on-state includes the case where the device finally operates in the saturated region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are , including when it is properly biased to a voltage in the range in which it operates in the saturation region. However, one embodiment of the present invention is not limited to this. Therefore, the transistors M1 and M1r may operate in the linear region. When the first data (weighting coefficient) is an analog value, the magnitude of the first data (weighting coefficient) For example, if transistor M1 and transistor M1r operate in the linear region, The operation may be in both the saturated region and the non-saturated region.

[0367] In this specification, the switches S2, S2r, S3, and Switch S3r, switch S4, switch S4r, switch S5, and switch S5r are If there is no control terminal, when a high level potential is input to the control terminal, the device will be in the ON state. When a low-level potential is input to the terminal, the terminal is set to the off state.

[0368] In the following, the first data (for example, a weighting coefficient) and the second data (for example, For example, in the following, we will consider the combination of values ​​that each neuron signal (operation value) can take. An example of the operation of the circuit MP will be explained for each combination.

[0369] [Condition 1] First, as an example, the first data (weighting coefficient) is "0" and is input to the circuit MP. Let us consider the case where the second data (the neuron signal value (calculated value)) is “+1.” 3A is a timing chart of the circuit MP in this case.

[0370] Between time T11 and time T12, the holding parts HC and HCr are held at the initial potential In FIG. 23A, for example, the node n1 and the node n1r are held at the initial potential It is assumed that a potential higher than the potential VSS is maintained.

[0371] A low level potential is applied to the wiring WL, the wiring X1L, and the wiring X2L. By this, switch S2, switch S2r, switch S3, switch S3r, switch S 4. The control terminals of the switches S4r, S5, and S5r are connected to low Since a level potential is input, the switches S2, S2r, S3, and switch S3r, switch S4, switch S4r, switch S5, and switch S5r is in the off state.

[0372] Between time T12 and time T13, a high level potential is applied to the wiring WL. As a result, the switches S2, S2r, S5, and S5r Since a high-level potential is input to each control terminal, switch S2, switch S2 Switch S5r, switch S5r, and switch S5r are turned on.

[0373] Although not shown in FIG. 23A, the wiring IL and the wiring ILB each have an initialization V as potential ini is applied to the switches S2, S2r, S5, and Since each of the switches S5r is in the on state, the nodes n1 and n2 of the holding unit HC and The potential of each node n1r of the holding unit HCr is V ini In other words, from time T12 From time T10 to time T13, the node n1 of the holding unit HC and the node n1r of the holding unit HCr The potentials of the respective elements are initialized.

[0374] In addition, the initialization potential V ini For example, it is preferable to set the potential to the ground. , the initialization potential V ini The potentials are VSS, higher than ground potential, or higher than ground potential. The initial potential V ini The wirings IL and ILB may have different potentials. potential V ini It is not necessary to input the time from time T12 to time T13. Alternatively, the period from time T12 to time T13 may not necessarily be set. In this case, initialization may not be performed. ini A wiring that provides the signal and a switch that connects the wiring to the wiring IL and the wiring ILB. Although the switch is not shown, in this operation example, the circuit ILD shown in FIG. 14A is connected to the wiring IL and Initialization potential V ini It shall have the function of providing the following.

[0375] Between time T13 and time T14, the potential VSS is input to the circuit MC from the wiring IL. The potential VSS is input to the circuit MCr from the wiring ILB. Then, switch SWLA and switch SWLAB are turned on, and switch SWIA and switch This is done by turning off the switch SWIAB. This is done by turning off SWR3 (switch SWR3B). Therefore, the potential of the node n1 of the holding unit HC becomes VSS, and the potential of the node n1r of the holding unit HCr becomes VSS. As a result, in the circuit MC, the transistor M1 has a current of 0. Since the current is set to flow, no current flows from the wiring OL to the wiring VE via the circuit MC. In addition, in the circuit MCr, the transistor M1r is set so that the current amount is 0. Therefore, no current flows from the wiring OLB to the wiring VEr via the circuit MCr. Between time T13 and time T14, the transistors M1 and M1r Since the power supply is turned off, there is no conduction between the wiring OL and the wiring VE, and there is no conduction between the wiring OLB and the wiring There is no conduction between VEr and the transistor.

[0376] Between time T14 and time T15, the wiring WL and the wiring X1L are connected to a low level This causes the switches S2, S2r, S5, and Since a low-level potential is input to each control terminal of the switch S2 and the switch S5r, , the switches S2r, S5, and S5r are each turned off. When the switch S2 and the switch S2r are turned off, the node n1 of the holding unit HC The potential VSS of the node n1r of the holding unit HCr is held, and the potential VSS of the node n1r of the holding unit HCr is held. , when the switch S5 is turned off, the line IL is connected to the line VE through the circuit MC. Similarly, when the switch S5r is turned off, The current stops flowing from the wiring ILB to the wiring VEr via the circuit MCr. Between time T15 and time T16, the switches SWR3 and SWR3B shown in FIG. may be turned on to initialize the potentials of the wirings OL and OLB. , and the potential of the wiring OLB is initialized, so that after time T15, The potential of the wiring OL and wiring OLB is changed by the current output from P. can be done.

[0377] The operation from time T11 to time T15 determines the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, In FIG. 14A, switches SWIA, SWIAB, SWLA, and The switch SWLAB may be turned off. After the weighting coefficient is set in the circuit MP, 6A, the switches SWR3 and SWR3B are turned on, and the wiring OL The potentials of the wirings OL and OLB may be initialized. After that, the switches SWR3 and SWR3B may be turned off.

[0378] After time T15, the neuron signal (operation value) “+1” is input to the circuit MP. A high-level potential is input to the wiring X1L, and a low-level potential is input to the wiring X2L. A high-level potential is input to the control terminals of the switches S3 and S3r. A low level potential is input to the control terminals of the switches S4 and S4r. The switches S3 and S3r are turned on, and the switches S4 and S 4r are turned off. In other words, this operation and between the circuit MCr and the wiring OLB. As a result, the circuit MC and the wiring OL are in a non-conductive state. A state of conduction is established between the circuit MCr and the circuit AFP, and a state of conduction is established between the circuit MCr and the circuit AFP. .

[0379] Since the transistor M1 is in the off state (the amount of current is set to 0), In the circuit MC, a current flows from the wiring OL and OLB to the wiring VE. Similarly, since the transistor M1r is in the off state (the amount of current is 0), In the circuit MCr, the wiring OL and OLB are connected to the wiring V From the above, the current I output from node outa of wiring OL OL , and the current I output from node outb of wiring OLB OLB before time T15 Therefore, the current I between the circuit AFP and the wiring OL OL does not flow, and Between the circuit AFP and the wiring OLB, a current I OLB does not flow.

[0380] By the way, this condition is that the first data (weighting coefficient) is set to "0" and the first data input to the circuit MP is Since the 2nd data (neuron signal value (calculated value)) is set to "+1", equation (1.1) Using this, the product of the first data (weight coefficient) and the second data (neuron signal value) is 0”. The product of the first data (weight coefficient) and the second data (neuron signal value) is “0 " As a result, in the operation of the circuit MP, the current I OL and current I O LB This corresponds to the case where the first data (weighting coefficient) and the second data do not change. The result of the product of the data (the signal value of the neuron) being "0" is shown in Figure 15 as Signal z j (k) is output as

[0381] Once the first data (for example, weighting coefficients) is input, the value is not updated. By changing only the second data (such as the neuron signal value or the calculation value), In this case, the first data (weighting coefficient) may not be updated. Therefore, power consumption can be reduced. In order to reduce this, it is necessary to store the first data (weighting coefficient) for a long period of time. For example, when an OS transistor is used, the off-state current is low, and therefore the first data ( It is possible to retain the weighting coefficient for a long period of time.

[0382] [Condition 2] Next, as an example, the first data (weighting coefficient) is "+1" and is input to the circuit MP. Let us consider the case where the second data (the neuron signal value (calculated value)) is “+1.” 3B is a timing chart of the circuit MP in this case.

[0383] Regarding the operation from time T11 to time T13, Since the operation from time T11 to time T13 under condition 1 is the same as that under condition 1, Please refer to the description of the work.

[0384] Between time T13 and time T14, the current amount from the wiring IL to the circuit MC is I 1 is input, and the potential VSS is input to the circuit MCr from the wiring ILB. In this state, the switches SWIA and SWLAB are turned on, and the switch SWIA This is done by turning off switch B and switch SWLA. The potential of the node n1 of the holding unit HC becomes V1, and the potential of the node n1r of the holding unit HCr becomes VSS. As a result, in the circuit MC, the transistor M1 flows a current of I1. Therefore, current I1 flows from wiring IL to wiring VE via circuit MC. In addition, in the circuit MCr, the transistor M1r is set to pass 0 current. Therefore, no current flows from the wiring ILB to the wiring VEr via the circuit MCr.

[0385] Between time T14 and time T15, a low level potential is applied to the wiring WL. As a result, the switches S2, S2r, S5, and S5r Since a low-level potential is input to each control terminal, switch S2, switch S2 The switches S2, S3, and S5r are turned off. When the switch S2r is turned off, the potential V1 of the node n1 of the holding unit HC is held. The potential VSS of the node n1r of the holding unit HCr is held. By turning off the circuit, no current flows from the wiring OL to the wiring VE via the circuit MC. Similarly, when the switch S5r is turned off, the circuit is disconnected from the wiring OLB. The current does not flow through the wiring VEr via the path MCr. During this period, the switches SWR3 and SWR3B shown in FIG. 6A are turned on. The potentials of the wirings OL and OLB may be initialized. By initializing the potential of This allows the potentials of the wirings OL and OLB to be changed.

[0386] The operation from time T11 to time T15 determines the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, , in FIG. 14A, switches SWIA, SWIAB, SWLA, and The switch SWLAB may be turned off. The first data (weighting coefficient) is input to the circuit MP. After this is set, turn on the switches SWR3 and SWR3B and then The potentials of the wirings OL and OLB may be initialized. After the initialization, the switches SWR3 and SWR3B may be turned off.

[0387] After time T15, the second data (the neuron signal value (calculated value)) is sent to the circuit MP. ) As the "+1" input, high level potential is input to wire X1L and low level potential is input to wire X2L. At this time, a high level is applied to the control terminals of the switches S3 and S3r. A potential is input, and a low-level voltage is applied to the control terminals of the switches S4 and S4r. Therefore, the switches S3 and S3r are both in the ON state. The switches S4 and S4r are turned off. By this operation, the circuit MC and the wiring OL, and the circuit MCr and the wiring OLB are in a conductive state. The circuit MC and the wiring OLB, and the circuit MCr and the wiring OL are in a non-conductive state. This brings the circuit MC and the circuit AFP into a conductive state, and the circuit MCr and the circuit AFP are in a conductive state.

[0388] In the circuit MC, the switch S3 is in the on state and the transistor M1 is in the off state. Since the power is on (current I1 is set to flow), A current flows from L to the wiring VE. In the circuit MC, the switch S4 is turned off. Since the current is in the ON state, no current flows between the wiring OLB and the wiring VE. In MCr, the switch S3r is on, but the transistor M1r is off. Since the current is set to 0, the wiring is OLB. No current flows between the switch S4r and the wiring VEr. is in the off state, no current flows between the wiring OL and the wiring VEr. Therefore, the current I output from the node outa of the wiring OL OL After time T15, I 1, and the current I output from node outb of wiring OLB OLB before time T15 Therefore, a current I of magnitude I1 flows between the circuit AFP and the wiring OL. OL but The current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0389] By the way, this condition is that the first data (weighting coefficient) is set to "+1" and input to the circuit MP. Since the second data (the value of the neuron's signal) is set to "+1", we use equation (1.1) The product of the first data (weight coefficient) and the second data (neuron signal value) is "+1". The product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1". As a result, in the operation of the circuit MP, the current I OL I1 increases, and the Flow I OLB This corresponds to the case where the first data (weighting coefficient) and the second data ( The result of the product of the neuron's signal value) being "+1" is shown in Figure 15, from the circuit AFP signal z j (k) is output as

[0390] In addition, during the period from time T13 to time T14 under this condition, for example, By setting the current flowing through the circuit MC to I2 instead of I1, V2 can be held in the holding section HC. As a result, "+2" is set as the first data (weighting coefficient) of the circuit MP. The first data (weighting coefficient) is set to "+2", and the neuron signal input to the circuit MP is By setting "+1", the first data (weighting coefficient) and the second data ( The product of the first data (weighting coefficient) and the second data (value of the neuron signal) is "+2". The result of the product of (the neuron's signal value) being "+2" is that, in the operation of the circuit MP, at time T1 5 and later, current I OL increases, and the current I OLB This corresponds to the case where In the circuit MCr, VSS is held in the holding unit HCr, and the voltage By setting a flow rate other than I1, the first data (weighting coefficient) of the circuit MP can be set to a value other than "+1". A positive value of can be set.

[0391] [Condition 3] Next, as an example, the first data (weighting coefficient) w is "-1" and is input to the circuit MP. Let us consider the case where the second data (the value of the neuron signal (calculated value)) is "+1." 23C is a timing chart of the circuit MP in this case.

[0392] Regarding the operation from time T11 to time T13, Since the operation from time T11 to time T13 under condition 1 is the same as that under condition 1, Please refer to the description of the work.

[0393] Between time T13 and time T14, the potential VSS is input to the circuit MC from the wiring IL. The current I1 is input from the wiring ILB to the circuit MCr. In this state, the switches SWIAB and SWLA are turned on, and the switch SWIA This is done by turning off the switch SWLAB. The potential of the node n1 of the holding unit HC becomes VSS, and the potential of the node n1r of the holding unit HCr becomes V1. As a result, in the circuit MCr, the transistor M1 is set so that the amount of current is 0. Therefore, no current flows from the wiring IL to the wiring VE via the circuit MC. In Cr, the transistor M1r is set to pass a current of I1, so the A current I1 flows from the line ILB through the circuit MCr to the wiring VEr.

[0394] Between time T14 and time T15, a low level potential is applied to the wiring WL. As a result, the switches S2, S2r, S5, and S5r Since a low-level potential is input to each control terminal, switch S2, switch S2 The switches S2, S5, and S5r are turned off. When the switch S2r is turned off, the potential VSS of the node n1 of the holding unit HC is held. The potential V1 of the node n1r of the holding unit HCr is held. When this happens, current will no longer flow from the wiring OL to the wiring VE via the circuit MC. Similarly, when the switch S5r is turned off, the line OLB is connected to the circuit M The current does not flow through the wiring VEr via Cr. During this time, the switches SWR3 and SWR3B shown in FIG. 6A are turned on. The potentials of the wirings OL and OLB may be initialized. By initializing the value, the current output from the circuit MP after time T15 This allows the potentials of the wirings OL and OLB to be changed.

[0395] The operation from time T11 to time T15 determines the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, In FIG. 14, switches SWIA, SWIAB, SWLA, and The switch SWLAB may be turned off. After setting, turn on the switches SWR3 and SWR3B and connect the wiring O After initializing the potentials of the wirings OL and OLB, Alternatively, the switches SWR3 and SWR3B may be turned off.

[0396] After time T15, the second data (neuron signal (calculated value)) to the circuit MP is As the +1" input, a high level potential is input to the wire X1L and a low level potential is input to the wire X2L. At this time, a high level potential is applied to the control terminals of the switches S3 and S3r. is input, and a low level potential is applied to the control terminals of the switches S4 and S4r. Therefore, the switches S3 and S3r are both turned on. , the switch S4, and the switch S4r are each turned off. Therefore, the circuit MC and the wiring OL, and the circuit MCr and the wiring OLB are in a conductive state. This results in a non-conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL. This brings the circuit MC and the circuit AFP into a conductive state, and also brings the circuit MCr and the circuit The connection between the AFP and the road is established.

[0397] In the circuit MC, the switch S3 is in the on state, but the transistor M1 is in the off state (set to pass 0 current), No current flows between OL and the wiring VE. Also, in the circuit MC, the switch S4 Since it is in the off state, no current flows between the wiring OLB and the wiring VE. In the circuit MCr, the switch S3r is in the on state, and the transistor M1r is in the on state (the current is set to I1), A current flows from the line OLB to the wiring VEr. Also, in the circuit MCr, the switch Since S4r is in the off state, no current flows between wire OL and wire VEr. From the above, the current I output from node outa of wiring OL OL is around time T15 The current I output from node outb of wiring OLB does not change. OLB is the time T15 After a certain time, I1 increases. Therefore, the current I OL Does not flow , and a current I of current magnitude I1 flows between the circuit AFP and the wiring OLB. OLB is playing.

[0398] By the way, this condition is that the first data (weighting coefficient) is set to "-1" and input to the circuit MP. Since the second data (neuron signal value (calculated value)) is set to "+1", the formula (1.1 ), the product of the first data (weight coefficient) and the second data (neuron signal value) is The product of the first data (weighting coefficient) and the second data (neuron signal value) is The result of "-1" is that in the operation of the circuit MP, the current I OL Changes current I OLBcorresponds to the case where I1 increases. Note that the first data (weighting coefficient) and the The result of the product of two data (neuron signal values) being "-1" is shown in Figure 15 by the circuit AFP to signal z j (k) is output as

[0399] In addition, during the period from time T13 to time T14 under this condition, for example, By setting the current flowing through the circuit MCr to I2 instead of I1, V2 is held in the holding section HCr. As a result, "-2" is set as the first data (weighting coefficient) of the circuit MP. The first data (weighting coefficient) is set to "-2", and the second data ( By setting the value of the neuron signal) to "+1", the first data ( The product of the weighting coefficient and the second data (the neuron signal value) is "-2". The result of the product of (weight coefficient) and the second data (value of the neuron signal) being "-2" is In the operation of MP, the current I OL does not change, and the current I OLB Increased by I2 In this way, in the circuit MC, VSS is held in the holding section HC, and By setting a current amount other than I1 in the circuit MCr, the weight coefficient of the circuit MP can be calculated. You can set a positive value other than "+1" by using the

[0400] [Condition 4] In this condition, for example, the first data (weighting coefficient) is set to "0" and the input to the circuit MP is The behavior of the circuit MP when the second data (value of the neuron signal (calculated value)) is set to "-1" Fig. 24A is a timing chart of the circuit MP in this case.

[0401] Regarding the operation from time T11 to time T15, The behavior from time T11 to time T15 in condition 1 is the same as that from time T11 to time T15 in condition 1. Please refer to the description of the work.

[0402] After time T15, the second data (the neuron signal value (calculated value)) is sent to the circuit MP. ) For the "-1" input, low level potential is input to wire X1L and high level potential is input to wire X2L. At this time, a low level is applied to the control terminals of the switches S3 and S3r. A high-level voltage is applied to the control terminals of the switches S4 and S4r. Therefore, the switches S3 and S3r are both in the OFF state. The switches S4 and S4r are turned on. This operation causes a non-conduction between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB. The state is changed to a conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL. This brings the circuit MC and the circuit AFP into a conductive state, and the circuit MCr and the circuit AFP are in a conductive state.

[0403] Since the transistor M1 is in the off state (the amount of current is set to 0), In the circuit MC, between the wiring OL and the wiring OLB and the wiring VE, No current flows. In other words, the current I output from node outa of wiring OL OL , and distribution The current I output from node outb of line OLB OLB does not change before and after time T15. Similarly, since the transistor M1r is in the off state (so that the amount of current is 0), In the circuit MCr, wiring OL and wiring OLB are connected to wiring V In other words, the current I output from node outa of wiring OL O L , and the current I output from node outb of wiring OLB OLB Also, around time T15 Therefore, the current I OL does not flow and Between the AFP and OLB wiring, a current I OLB does not flow.

[0404] By the way, this condition is that the first data (weighting coefficient) is set to "0" and the first data input to the circuit MP is Since the 2 data (neuron signal value (calculated value)) is set to "-1", equation (1.1) Using this, the product of the first data (weight coefficient) and the second data (neuron signal value) is 0”. The product of the first data (weight coefficient) and the second data (neuron signal value) is “0 " As a result, in the operation of the circuit MP, the current I OL and current I O LB This corresponds to the case where none of the above changes, which is consistent with the circuit operation result for condition 1. In addition, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As in condition 1, the result is that the signal z j (k) Output as will be done.

[0405] [Condition 5] In this condition, for example, the first data (weighting coefficient) is set to "+1" and input to the circuit MP. The second data (value of the neuron signal (calculated value)) to be calculated is "-1". Fig. 24B is a timing chart of the circuit MP in this case.

[0406] Regarding the operation from time T11 to time T15, The behavior from time T11 to time T15 in condition 2 is the same as that from time T11 to time T15 in condition 2. Please refer to the description of the work.

[0407] After time T15, the second data (the neuron signal value (calculated value)) is sent to the circuit MP. ) For the "-1" input, low level potential is input to wire X1L and high level potential is input to wire X2L. At this time, a low level is applied to the control terminals of the switches S3 and S3r. A high-level voltage is applied to the control terminals of the switches S4 and S4r. Therefore, the switches S3 and S3r are both in the OFF state. The switches S4 and S4r are turned on. This operation causes a non-conduction between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB. The state is changed to a conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL. This brings the circuit MC and the circuit AFP into a conductive state, and the circuit MCr and the circuit AFP are in a conductive state.

[0408] In the circuit MC, the switch S3 is in the off state, so the line OL to the line VE In the circuit MC, the switch S4 is in the ON state. Since the transistor M1 is in the on state (current I1 flows), On the other hand, current flows from the wiring OLB to the wiring VE. In MCr, switch S3r is in the off state, so the line from OLB to VE No current flows between the first and second terminals. Also, in the circuit MCr, the switch S4r is in the ON state. However, since the transistor M1 is in the off state (the current is 0), (This is because the wiring is set to be shorted to the OL wiring.) No current flows between the OL wiring and the VE wiring. From above, the current I output from node outa of wiring OL OL changes around time T15. The current I is output from node outb of wiring OLB. OLB is the time T15 After that, I1 increases. Therefore, the current I OL Does not flow, Between the circuit AFP and the wiring OLB, a current I OLB is playing.

[0409] By the way, this condition is that the first data (weighting coefficient) is set to "+1" and input to the circuit MP. Since the second data (neuron signal value (calculated value)) is set to "-1", the formula (1.1 ), the product of the first data (weight coefficient) and the second data (neuron signal value) is The product of the first data (weighting coefficient) and the second data (neuron signal value) is The result of "-1" is that in the operation of the circuit MP, the current I OL Changes current I OLB corresponds to the case where I1 increases, which is consistent with the circuit operation results for condition 3. The product of the first data (weighting coefficient) and the second data (neuron signal value) is "- 1” is obtained by the same condition as in condition 3, when the signal z j (k) and and output.

[0410] As described in Condition 2, during the period from time T13 to time T14 under this condition, For example, the current flowing from the wiring OL to the circuit MC is set to I2 instead of I1, and the holding unit HC V2 may be stored in the circuit MP. The first data (weighting coefficient) is set to "+2", and the new data input to the circuit MP is By setting the Ron signal to "-1", the first data (weighting coefficient) and The product of the second data (neuron signal value) and the first data (weighting coefficient) is "-2". The product of the second data (the neuron's signal value) is "-2", which is the result of the operation of the circuit MP. After time T15, the current I OL does not change, and the current I OLB When I2 increases In this way, in the circuit MCr, VSS is held in the holding unit HCr, and By setting a current amount other than I1 in C, the weighting coefficient of the circuit MP can be set to a value other than "+1". A positive value can be set.

[0411] [Condition 6] In this condition, for example, the first data (weighting coefficient) is set to "-1" and input to the circuit MP. The second data (value of the neuron signal (calculated value)) to be calculated is "-1". Fig. 24C is a timing chart of the circuit MP in this case.

[0412] Regarding the operation between time T11 and time T15, The behavior from time T11 to time T15 in condition 3 is the same as that from time T11 to time T15 in condition 3. Please refer to the description of the work.

[0413] After time T15, the second data (the neuron signal value (calculated value)) is sent to the circuit MP. ) For the "-1" input, low level potential is input to wire X1L and high level potential is input to wire X2L. At this time, a low level is applied to the control terminals of the switches S3 and S3r. A high-level voltage is applied to the control terminals of the switches S4 and S4r. Therefore, the switches S3 and S3r are both in the OFF state. The switches S4 and S4r are turned on. This operation causes a non-conduction between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB. The state is changed to a conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL. This brings the circuit MC and the circuit AFP into a conductive state, and the circuit MCr and the circuit AFP are in a conductive state.

[0414] In the circuit MC, the switch S3 is in the off state, so the line OL to the line VE In the circuit MC, the switch S4 is in the ON state. However, since transistor M1 is in the off state (set to pass 0 current), On the other hand, the current does not flow between the wiring OLB and the wiring VE. In Cr, since the switch S3r is in the off state, the line OLB is connected to the line V In the circuit MCr, the switch S4r is turned on. Since the transistor M1 is in the ON state (current I1 flows), (Since the wiring is set as shown in Fig. 1), current flows from the wiring OL to the wiring VEr. The current I output from the node outa of the wiring OL OL After time T15, I1 The current I output from node outb of wiring OLB increases. OLB is around time T15 Therefore, a current I of magnitude I1 flows between the circuit AFP and the wiring OL. OL Flow And the current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0415] By the way, this condition is that the first data (weighting coefficient) is set to "-1" and input to the circuit MP. Since the second data (neuron signal value (calculated value)) is set to "-1", the formula (1.1 ), the product of the first data (weight coefficient) and the second data (neuron signal value) is The product of the first data (weighting coefficient) and the second data (neuron signal value) is The result of "+1" is that in the operation of the circuit MP, the current I OL Changes and the current I OLB This corresponds to the case where does not change, which is consistent with the circuit operation result for condition 2. The product of the first data (weight coefficient) and the first data (neuron signal value) is "+1" As in condition 2, the result is that in FIG. 15, the signal z j (k) as is output.

[0416] As described in Condition 3, during the period from time T13 to time T14 under this condition, For example, the current flowing from the wiring OLB to the circuit MCr is set to I2 instead of I1, and the holding part V2 may be stored in HC. This allows " The first data (weighting coefficient) is set to "-2", and the second data input to the circuit MP is set to "-2". By setting the second data (the value of the neuron's signal) to "-1", the The product of the first data (weighting coefficient) and the second data (neuron signal value) is "+2". The product of the first data (weighting coefficient) and the second data (neuron signal value) is "+2". As a result, in the operation of the circuit MP, the current I OL does not change, and the current I OL B In this way, in the circuit MC, VSS is applied to the holding section HC. By setting a current amount other than I1 in the circuit MCr, the weight coefficient of the circuit MP A positive value other than "+1" can be set as the value.

[0417] [Condition 7] In this condition, for example, the first data (weighting coefficient) is "0" and the input to the circuit MP is Condition 7 is when the second data (the neuron signal value (calculated value)) is "0". Consider the operation of the circuit MP in this case. It is a route.

[0418] Regarding the operation from time T11 to time T15, The behavior from time T11 to time T15 in condition 1 is the same as that from time T11 to time T15 in condition 1. Please refer to the description of the work.

[0419] After time T15, the second data (the neuron signal value (calculated value)) is sent to the circuit MP. ) As a "0" input, a low level potential is input to the wire X1L and a low level potential is input to the wire X2L. At this time, the switches S3, S3r, S4, and S4r A low level potential is input to each control terminal. Switch S3r, switch S4, and switch S4r are all in the OFF state. By this operation, the circuit MC and the wiring OL, the circuit MCr and the wiring OLB, the circuit MC and the wiring There is a non-conduction state between the circuit MCr and the line OLB, and between the circuit MCr and the wiring OL. The circuit MC and the circuit AFP are in a non-conductive state, and the circuit MCr and the circuit AFP are in a non-conductive state. It becomes non-conductive.

[0420] Therefore, in the circuit MC, regardless of the amount of the set current flowing through the transistor M1, Therefore, no current flows from the wiring OL to either the wiring VE or the wiring VEr. In the circuit MCr, regardless of the amount of current that is set to flow through the transistor M1r, No current flows between the line OLB and the other of the wiring VE or wiring VEr. The current I output from node outa of OL OL , and from node outb of wiring OLB The current I OLB Each of these does not change before and after time T15. Between the circuit AFP and the wiring OL, a current I OL does not flow, and the current between the circuit AFP and the wiring OLB Between them, there is a current I OLB does not flow.

[0421] By the way, this condition is that the first data (weighting coefficient) is set to "0" and the first data input to the circuit MP is Since the 2 data (neuron signal value (calculated value)) is set to "0", we change equation (1.1) to When using this function, the product of the first data (weight coefficient) and the second data (neuron signal value) is "0 " The product of the first data (weight coefficient) and the second data (neuron signal value) is "0" As a result, in the operation of the circuit MP, the current I OL and current I OL BThis corresponds to the case where none of the above changes, which is consistent with the circuit operation results for conditions 1 and 4. Note that the product of the first data (weight coefficient) and the second data (neuron signal value) is 0 The result of " is the same as in Condition 1 and Condition 4, in FIG. 15, when the signal z j ( k) is output as

[0422] [Condition 8] In this condition, for example, the first data (weighting coefficient) is "+1" and the input to the circuit MP is Condition 8 is when the second data (neuron signal value (calculated value)) is "0". Then, consider the operation of the circuit MP. FIG. 25B shows the timing chart of the circuit MP in this case. It is a chart.

[0423] Regarding the operation from time T11 to time T15, The behavior from time T11 to time T15 in condition 2 is the same as that from time T11 to time T15 in condition 2. Please refer to the description of the work.

[0424] After time T15, the second data (the neuron signal value (calculated value)) is sent to the circuit MP. ) As a "0" input, a low level potential is input to the wire X1L and a low level potential is input to the wire X2L. At this time, the switches S3, S3r, S4, and S4r A low level potential is input to each control terminal. Switch S3r, switch S4, and switch S4r are all in the OFF state. Similarly, this operation causes the currents flowing through the transistors M1 and M1r. Regardless of the amount of current that is set, the current between the circuit MC and the wiring OL, and the current between the circuit MCr and the wiring OLB During this time, there is no conduction between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL. This causes a non-conductive state between the circuit MC and the circuit AFP, and also causes a non-conductive state between the circuit MCr and the circuit AFP. Therefore, the wiring OL is disconnected from the wiring VE or the wiring V No current flows between the wiring OLB and the other of the wiring VE or VElectron Since current also flows between OL , and and the current I output from node outb of wiring OLB. OLB Each of these is at time T15 Therefore, the current I between the circuit AFP and the wiring OL OL Does not flow , and a current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0425] By the way, this condition is that the first data (weighting coefficient) is set to "+1" and input to the circuit MP. Since the second data (neuron signal (calculated value)) is set to "0", we use equation (1.1). Then, the product of the first data (weight coefficient) and the second data (neuron signal value) is "0" The product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As a result, in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the above changes, and this is the result of the circuit operation under conditions 1, 4, and 7. The product of the first data (weighting coefficient) and the second data (neuron signal value) is The result of "0" is the same as in conditions 1, 4, and 7, as shown in FIG. 15, when the circuit AFP From signal z j (k) is output as

[0426] [Condition 9] In this condition, for example, the first data (weighting coefficient) is "-1" and the input to the circuit MP Condition 9 is when the second data (the neuron signal value (calculated value)) is "0". Consider the operation of the circuit MP in this case. It is a route.

[0427] Regarding the operation between time T11 and time T15, The behavior from time T11 to time T15 in condition 3 is the same as that from time T11 to time T15 in condition 3. Please refer to the description of the work. ...

Claims

1. a cell and a first circuit, the first circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a first integrating circuit, a second integrating circuit, and a second circuit; the first integration circuit includes a first operational amplifier and a first load; the second integration circuit includes a second operational amplifier and a second load; the cell is electrically connected to one terminal of the third switch via a first wiring; the cell is electrically connected to one terminal of the fourth switch via the first wiring, the cell is electrically connected to one terminal of the first load via the first wiring; the cell is electrically connected to one terminal of the seventh switch via a second wiring; the cell is electrically connected to one terminal of the eighth switch via the second wiring, the cell is electrically connected to one terminal of the second load via the first wiring; the other terminal of the third switch is electrically connected to a third wiring to which a constant voltage is supplied; the other terminal of the fourth switch is electrically connected to the first input terminal of the first operational amplifier; the other terminal of the first load is electrically connected to one terminal of the first switch; a second input terminal of the first operational amplifier is electrically connected to a fourth wiring; an output terminal of the first operational amplifier is electrically connected to one terminal of the first switch; the other terminal of the seventh switch is electrically connected to the third wiring, the other terminal of the eighth switch is electrically connected to the first input terminal of the second operational amplifier; the other terminal of the second load is electrically connected to one terminal of the fifth switch; a second input terminal of the second operational amplifier is electrically connected to a fifth wiring; an output terminal of the second operational amplifier is electrically connected to one terminal of the fifth switch; the other terminal of the first switch is electrically connected to one terminal of the first capacitor; the other terminal of the first switch is electrically connected to one terminal of the second switch, the other terminal of the fifth switch is electrically connected to the other terminal of the first capacitor, the other terminal of the fifth switch is electrically connected to one terminal of the sixth switch, the other terminal of the second switch is electrically connected to a sixth wiring to which a reference potential is supplied; the other terminal of the sixth switch is electrically connected to the second circuit; the fourth wiring and the fifth wiring have a function of supplying the same voltage or different voltages to each other, the cell has a function of holding first data and a function of causing a first current corresponding to the first data and the second data to flow between the cell and the first wiring and a second current corresponding to the first data and the second data to flow between the cell and the second wiring when second data is input to the cell; the first integration circuit has a function of outputting a first potential in response to the first current input to the first integration circuit; the second integration circuit has a function of outputting a second potential in response to the second current input to the second integration circuit; the first capacitor has a function of holding a differential voltage between the first potential and the second potential, The second circuit is a semiconductor device having a function of outputting a signal corresponding to the differential voltage.

2. In claim 1, the first load has a second capacitance; The second load is a semiconductor device having a third capacitance.

3. A semiconductor device according to claim 1 or 2, and a housing, An electronic device that performs neural network calculations using the semiconductor device.

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