Semiconductor device

Abstract

To provide a semiconductor device with high reliability and excellent electric characteristics.SOLUTION: A semiconductor device 100 includes a semiconductor layer 108, a second insulating layer 110, a metal oxide layer 114, and a conductive layer 112 that are stacked on a first insulating layer 103 in this order. An end part of the second insulating layer exists on the inside relative to an end part of the semiconductor layer. An end part of each of the conductive layer and the metal oxide layer exists on the inside relative to the end part of the second insulating layer. A third insulating layer 116 is in contact with an upper surface of the first insulating layer, an upper surface and a side surface of the semiconductor layer, an upper surface and a side surface of the second insulating layer, a side surface of the metal oxide layer, and an upper surface and a side surface of the conductive layer. A first region of the semiconductor layer overlaps with the first insulating layer and the metal oxide layer. A second region holds the first region, overlaps with the second insulating layer, and does not overlap with the metal oxide layer. A third region holds the first region and a pair of the second regions, does not overlap with the second insulating layer, and includes a part with lower resistance than those of the first region and the second region in contact with the third insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, and a , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof A semiconductor device functions by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used for transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called the mobility A semiconductor device having improved mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed by using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. The company plans to improve some of its production facilities for transistors using polycrystalline silicon and amorphous silicon. This allows the use of metal oxide transistors, which reduces capital investment. Since the [certain material] has a higher field-effect mobility compared to the case of using amorphous silicon, a high-performance display device provided with a drive circuit can be realized.

[0005] In display devices, the screen size has a tendency to increase, and development has been carried out with a view to screen sizes of 60 inches or more in diagonal, and even screen sizes of 120 inches or more in diagonal are being considered. In addition, the screen resolution is also tending towards high definition, such as full high vision (pixel count 1920×1080, also referred to as "2K", etc.), ultra high vision (pixel count 3840×2160, also referred to as "4K", etc.), super high vision (pixel count 7680×4320, also referred to as "8K", etc.).

[0006] The increase in screen size and high definition tend to increase the wiring resistance within the display unit. In Patent Document 2, a technique for forming a low-resistance wiring layer using copper (Cu) is disclosed in order to suppress the increase in wiring resistance in a liquid crystal display device using amorphous silicon transistors.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a semiconductor device with good electrical characteristics as one of the problems. Or, one aspect of the present invention is to provide a highly reliable semiconductor device as one of the problems. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device.

[0009] Note that the description of these problems does not preclude the existence of other problems. In addition, one aspect of the present invention does not necessarily need to solve all of these problems. Other problems can be extracted from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention is a semiconductor device having a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the second insulating layer, the metal oxide layer, and the conductive layer are laminated in this order on the first insulating layer. In a cross-section in the channel length direction, the end of the second insulating layer is located inside the end of the semiconductor layer, and the ends of the conductive layer and the metal oxide layer are each located inside the end of the second insulating layer. The third insulating layer is in contact with the upper surface of the first insulating layer, the upper surface and side surfaces of the semiconductor layer, the upper surface and side surfaces of the second insulating layer, the side surface of the metal oxide layer, and the upper surface and side surfaces of the conductive layer. The semiconductor layer has a first region, a pair of second regions, and a pair of third regions. The first region overlaps with the first insulating layer and the metal oxide layer. The second regions sandwich the first region, overlap with the second insulating layer, and do not overlap with the metal oxide layer. The third regions sandwich the first region and the pair of second regions and do not overlap with the second insulating layer. Further, the third region is in contact with the third insulating layer and includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.

[0011] In the semiconductor device described above, it is preferable that the second insulating layer has a portion where the film thickness of the region that does not overlap with the metal oxide layer is thinner than the film thickness of the region that overlaps with the metal oxide layer.

[0012] In the semiconductor device described above, it is preferable that the second region includes a portion where the sheet resistance is 1×10 3 Ω / □ or more and 1×1 0 9 Ω / □ or less.

[0013] In the semiconductor device described above, the electrical resistance of the first region is preferably 1×1 0 0 times or more and 1×10 9 times or less of the electrical resistance of the second region.

[0014] In the semiconductor device described above, the electrical resistance of the second region is preferably 1×1 0 0 times or more and 1×10 9 times or less of the electrical resistance of the third region.

[0015] In the semiconductor device described above, it is preferable that the width of the second region in the cross section in the channel length direction is 100 nm or more and 2 μm or less.

[0016] In the semiconductor device described above, it is preferable that the first insulating layer contains a nitride and the third insulating layer contains a nitride.

[0017] In the semiconductor device described above, it is preferable to further have a fourth insulating layer. The fourth insulating layer preferably contacts the upper surface of the third insulating layer and contains a nitride.

[0018] In the semiconductor device described above, it is preferable that the third insulating layer has a region where the hydrogen concentration is lower than that of the fourth insulating layer.

[0019] ​In the semiconductor device described above, the third insulating layer has a region with a higher film density than the fourth insulating layer. This is preferable.

[0020] In the semiconductor device described above, it is preferable that the upper surface shapes of the conductive layer and the metal oxide layer substantially coincide. Or, it is preferable that the end portion of the conductive layer is located inside the end portion of the metal oxide layer. This is preferable. This is preferable.

[0021] In the semiconductor device described above, the end portions of the second insulating layer and the metal oxide layer preferably each have a tapered shape. This is preferable.

[0022] In the semiconductor device described above, it is preferable that the semiconductor layer and the metal oxide layer each contain the same metal element. This is preferable.

[0023] In the semiconductor device described above, the metal element is preferably at least one of indium and zinc. This is preferable.

Advantages of the Invention

[0024] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, a semiconductor device with high reliability can be provided. Or, a novel semiconductor device can be provided. This is not meant to preclude the existence of other effects. One aspect of the present invention does not necessarily have all of these effects. Other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

[0025] This is not meant to preclude the existence of other effects. One aspect of the present invention does not necessarily have all of these effects. Other effects can be extracted from the descriptions in the specification, drawings, claims, etc. One aspect of the present invention does not necessarily have all of these effects. Other effects can be extracted from the descriptions in the specification, drawings, claims, etc. This is not meant to preclude the existence of other effects. One aspect of the present invention does not necessarily have all of these effects. Other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0026]

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Modes for Carrying Out the Invention

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0028] In each of the figures described in this specification, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity.

[0029] The ordinal numbers "first", "second", "third", etc. used in this specification and the like are attached to avoid confusion of components and are not numerically limiting.

[0030] In this specification and the like, terms indicating arrangements such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0031] In this specification and the like, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are employed or when the direction of current changes in a circuit operation. For this reason, the terms source and drain can be used interchangeably.

[0032] In this specification and the like, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source region and the drain region at the shortest distance. That is, the channel length direction is 、corresponding to one of the directions of the current flowing through the semiconductor layer when the transistor is in the on state . Further, the channel width direction refers to a direction orthogonal to the channel length direction. Note that , depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be uniquely determined .

[0033] In this specification and the like, "electrically connected" includes the case where it is connected through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the exchange of electrical signals between the connection targets. For example, , "something having some electrical action" includes electrodes, wirings, switching elements such as transistors , resistance elements, inductors, capacitors, and other elements having various functions .

[0034] In this specification and the like, the term "film" and the term "layer" can be interchanged with each other . For example, terms such as "conductive layer" and "insulating layer" may be mutually exchanged with terms such as "conductive film" and "insulating film".

[0035] In this specification and the like, "substantially matching upper surface shapes" means that at least a part of the contours overlap between the stacked layers. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern, or partially by the same mask pattern. However, strictly speaking, the contours do not exactly overlap, and the end of the upper layer may be located inside the end of the lower layer, or the end of the upper layer may be located outside the end of the lower layer. In this case as well, it is said that "the upper surface shapes are substantially matching".

[0036] In this specification and the like, unless otherwise specified, the off-state current is the current that flows when a transistor is in an off state ( The drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise stated, for n-channel transistors, the voltage between the gate and source, V gs but Threshold voltage V th (For p-channel transistors, V th (higher than It refers to one's attitude.

[0037] In this specification, a display panel, which is one aspect of a display device, displays (outputs) images on a display surface. Therefore, the display panel is one aspect of an output device.

[0038] In this specification, for example, a flexible printed circuit (FPC) is attached to the substrate of the display panel. ed Circuit) or TCP (Tape Carrier Package) Connectors such as COG (Chip On Glass) are attached to the board. ss) method, etc., are called display panel modules, display modules, It may also be simply called a display panel.

[0039] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images, etc. on a display surface. The function of displaying information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. The touch panel also functions as a touch sensor that detects the touch of the touch panel. A card is one form of input / output device.

[0040] The touch panel is, for example, a display panel (or display device) with a touch sensor, A touch panel can also be called a display panel (or display device) with touch function. It can also be configured to include a panel and a touch sensor panel. Alternatively, it can be configured to have a function as a touch sensor inside or on the surface of the display panel.

[0041] In this specification and the like, a substrate of a touch panel with a connector or an IC mounted thereon may be referred to as a touch panel module, a display module, or simply a touch panel.

[0042] (Embodiment 1) In this embodiment, a semiconductor device according to an aspect of the present invention will be described. Hereinafter, as an example of the semiconductor device, a configuration example of a transistor and an example of a manufacturing method thereof will be described.

[0043] One aspect of the present invention is a semiconductor device having a semiconductor layer in which a channel is formed, a second insulating layer functioning as a gate insulating layer, and a conductive layer functioning as a gate electrode on a first insulating layer. The semiconductor layer is preferably configured to include a metal oxide exhibiting semiconductor characteristics (hereinafter also referred to as an oxide semiconductor).

[0044] A metal oxide layer is provided between the second insulating layer and the conductive layer. The metal oxide layer preferably has conductivity, and at this time, the metal oxide layer functions as a part of the gate electrode.

[0045] In a cross-section in the channel length direction, the end (outline) of the second insulating layer is preferably located inside the end (outline) of the semiconductor layer. Further, in a cross-section in the channel length direction, the ends (outlines) of the conductive layer and the metal oxide layer are preferably located inside the end (outline) of the second insulating layer.

[0046] A semiconductor device according to one aspect of the present invention further includes a third insulating layer. The third insulating layer is preferably provided so as to be in contact with the upper surface of the first insulating layer, the upper surface and side surfaces of the semiconductor layer, the upper surface and side surfaces of the second insulating layer, the side surface of the metal oxide layer, and the upper surface and side surfaces of the conductive layer. Each of the first insulating layer and the third insulating layer preferably uses a material that suppresses impurity diffusion. For example, each of the first insulating layer and the third insulating layer can use a nitride. Further, by providing a region where the first insulating layer and the third insulating layer are in contact, it is possible to suppress the diffusion of impurities into the transistor, and a transistor with high reliability can be obtained. The semiconductor layer has a first region where a channel is formed, a pair of second regions sandwiching the first region, and a pair of third regions sandwiching the first region and the second regions and functioning as source and drain regions. The first region is a region overlapping with the first insulating layer and the metal oxide layer. The second region is a region overlapping with the second insulating layer and not overlapping with the metal oxide layer. The third region is a region not overlapping with the second insulating layer. Further, the third region preferably includes a portion in contact with the third insulating layer and having a lower resistance than the first region. The second region preferably includes a portion having a higher resistance than the third region. The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage. Hereinafter, more specific examples will be described with reference to the drawings. For example, each of the first insulating layer and the third insulating layer can use a nitride. Further, by providing a region where the first insulating layer and the third insulating layer are in contact, it is possible to suppress the diffusion of impurities into the transistor, and a transistor with high reliability can be obtained. The semiconductor layer has a first region where a channel is formed, a pair of second regions sandwiching the first region, and a pair of third regions sandwiching the first region and the second regions and functioning as source and drain regions. The first region is a region overlapping with the first insulating layer and the metal oxide layer. The second region is a region overlapping with the second insulating layer and not overlapping with the metal oxide layer. The third region is a region not overlapping with the second insulating layer. Further, the third region preferably includes a portion in contact with the third insulating layer and having a lower resistance than the first region. The second region preferably includes a portion having a higher resistance than the third region. The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage.

[0047] The semiconductor layer has a first region where a channel is formed, a pair of second regions sandwiching the first region, and a pair of third regions sandwiching the first region and the second regions and functioning as source and drain regions. The first region is a region overlapping with the first insulating layer and the metal oxide layer. The second region is a region overlapping with the second insulating layer and not overlapping with the metal oxide layer. The third region is a region not overlapping with the second insulating layer. Further, the third region preferably includes a portion in contact with the third insulating layer and having a lower resistance than the first region. The second region preferably includes a portion having a higher resistance than the third region. The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage. The semiconductor layer has a first region where a channel is formed, a pair of second regions sandwiching the first region, and a pair of third regions sandwiching the first region and the second regions and functioning as source and drain regions. The first region is a region overlapping with the first insulating layer and the metal oxide layer. The second region is a region overlapping with the second insulating layer and not overlapping with the metal oxide layer. The third region is a region not overlapping with the second insulating layer. Further, the third region preferably includes a portion in contact with the third insulating layer and having a lower resistance than the first region. The second region preferably includes a portion having a higher resistance than the third region. The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage. The semiconductor layer has a first region where a channel is formed, a pair of second regions sandwiching the first region, and a pair of third regions sandwiching the first region and the second regions and functioning as source and drain regions. The first region is a region overlapping with the first insulating layer and the metal oxide layer. The second region is a region overlapping with the second insulating layer and not overlapping with the metal oxide layer. The third region is a region not overlapping with the second insulating layer. Further, the third region preferably includes a portion in contact with the third insulating layer and having a lower resistance than the first region. The second region preferably includes a portion having a higher resistance than the third region. The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage. The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage.

[0048] The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage. The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage. The second region functions as an LDD (Lightly Doped Drain) region. By having the second region, the drain electric field can be relaxed, and a transistor with high reliability can be obtained even when driven at a high voltage.

[0049] Hereinafter, more specific examples will be described with reference to the drawings.

[0050] <Example Configuration 1> FIG. 1A is a top view of the transistor 100, and FIG. 1B corresponds to a cross-sectional view of the cutting plane along the dashed-dotted line A1 -A2 shown in FIG. 1A, and FIG. 1C corresponds to a cross-sectional view of the cutting plane along the dashed-dotted line B1-B2 shown in FIG. 1A. In FIG. 1A, a part of the components (such as the protective layer) of the transistor 100 is omitted in the drawing. Also, the direction of the dashed-dotted line A1-A2 corresponds to the channel length direction, and the direction of the dashed-dotted line B1-B2 corresponds to the channel width direction. Also, for the top view of the transistor, in the following drawings, as in FIG. 1A, a part of the components will be omitted in the drawing for illustration.

[0051] The transistor 100 is provided on a substrate 102 and has an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, an insulating layer 118, etc. The island-shaped semiconductor layer 108 is provided on the insulating layer 103. The insulating layer 110 is provided to cover a part of the top surface of the insulating layer 103 and a part of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are laminated in this order on the insulating layer 110 and have a portion that overlaps with the semiconductor layer 108. An enlarged view of the region P surrounded by the dashed-dotted line in FIG. 1B is shown in FIG. 2A.

[0052] The ends of the conductive layer 112 and the metal oxide layer 114 are located inside the ends of the insulating layer 110. In other words, the insulating layer 110 has a portion that protrudes outside the ends of the conductive layer 112 and the metal oxide layer 114 at least on the semiconductor layer 108.

[0053] The semiconductor layer 108 includes a region 108C that functions as a channel formation region and a region that surrounds the region ​It has a pair of regions 108L that sandwich, and a pair of regions 108N outside thereof. Region 108L is , in the semiconductor layer 108, a region that overlaps with the insulating layer 110 and does not overlap with the conductive layer 112 . In FIG. 2A, the width of region 108C in the channel length direction of transistor 100 is shown as L1, and the width of region 108L is shown as L2.

[0054] Region 108C functions as a channel formation region. Here, when the metal oxide layer 114 has conductivity, since it functions as a part of the gate electrode, an electric field is applied from the gate electrode to region 108C through the insulating layer 110 that functions as a gate insulating layer, and a channel is formed . .

[0055] Region 108L has a function as a buffer region for relaxing the drain electric field. Since region 108L is a region that does not overlap with the conductive layer 112 and the metal oxide layer 114, it is a region where almost no channel is formed even when a gate voltage is applied to the conductive layer 112. It is preferable that the carrier concentration in region 108L is higher than that in region 108C. Thus, region 108L can function as an LDD region. . .

[0056] Region 108L can also be said to be a region having the same or lower resistance, the same or higher carrier concentration, the same or higher oxygen defect density, and the same or higher impurity concentration compared to region 108C. . .

[0057] Region 108L can also be said to be a region having the same or higher resistance, the same or lower carrier concentration, the same or lower oxygen defect density, and the same or lower impurity concentration compared to region 108N. . . ​

[0058] Thus, by providing the region 108L that functions as the LDD region between the region 108C that is the channel formation region and the region 108N that is the source region or the drain region it is possible to realize a highly reliable transistor that has both a high drain breakdown voltage and a high on-current.

[0059] The region 108N functions as the source region or the drain region and is the lowest resistance region compared to the other regions of the semiconductor layer 108. Or, the region 108N can also be said to be the region with the highest carrier concentration, the highest oxygen defect density, or the highest impurity concentration compared to the other regions of the semiconductor layer 108.

[0060] It is more preferable that the electrical resistance of the region 108N is lower. For example, the sheet resistance value of the region 108N is 1 Ω / □ or more and less than 1×10 3 Ω / □, preferably 1 Ω / □ or more and 8×10 2 Ω / □ or less.

[0061] It is more preferable that the electrical resistance of the region 108C in the state where no channel is formed is higher. For example, the sheet resistance value of the region 108C is 1×10 9 Ω / □ or more, preferably 5×10 9 Ω / □ or more, more preferably 1×10 10 Ω / □ or more.

[0062] It is more preferable that the electrical resistance of the region 108C in the state where no channel is formed is higher so there is no particular need to provide an upper limit value. However, if an upper limit value is provided, for example, the sheet resistance value of the region 108C is 1×10 Ω / □ or more and 1×10 9 Ω / □ or less 12 ​​​​​​Ω / sq or less, preferably 5×1 0 9 Ω / sq or more and 1×10 12 Ω / sq or less, more preferably 1×10 10 Ω / sq or more and 1×1 0 12 It is preferably Ω / sq or less.

[0063] The sheet resistance value of region 108L is, for example, 1×10 3 Ω / sq or more and 1×10 9 Ω / sq or less , preferably 1×10 3 Ω / sq or more and 1×10 8 Ω / sq or less, more preferably 1×10 3 Ω / sq or more and 1×10 7 Ω / sq. By setting the resistance within such a range, a transistor with good electrical characteristics and high reliability can be obtained. Note that the sheet resistance can be calculated from the resistance value. By providing such a region 108L between region 108N and region 108C, the source-drain breakdown voltage of transistor 100 can be increased. The electrical resistance of region 108C in a state where no channel is formed is 1×10 times or more and 1×10 times or less of the electrical resistance of region 108N, preferably 1×10 .

[0064] The electrical resistance of region 108C in a state where no channel is formed is 1×10 times or more and 1×10 6 times or less of the electrical resistance of region 108L, preferably 1×10 12 times or more and 1×10 6 times or less, more preferably 1×10 11 times or more and 1×10 6 times or less and can be set as such. 10 The electrical resistance of region 108C in a state where no channel is formed is 1×10

[0065] times or more and 1×10 times or less of the electrical resistance of region 108L, preferably 1×10 0 times or more and 1×10 9 times or less, more preferably 1×10 1 times or more and 1×108 times or less, more preferably 1×10 2 more than 1x10 7 It can be up to twice as much.

[0066] The electrical resistance of region 108L is 1×10 0 more than 1x10 9 Double Less than or equal to 1×10 1 more than 1x10 8 times or less, more preferably 1×10 1 more than twice 1×10 7 It can be up to twice as much.

[0067] The region 108L having the above-mentioned resistance is provided between the region 108N and the channel forming region. This makes it possible to increase the source-drain breakdown voltage of the transistor 100.

[0068] The carrier concentration in the semiconductor layer 108 is lowest in the region 108C, followed by the regions 108L and It is preferable that the distribution is such that the concentration of the ion in the region 108C increases in the order of the concentration of the ion in the region 108N. By providing the region 108L between the region 108N, for example, Even if impurities such as hydrogen diffuse from the region 108C, the carrier concentration in the region 108C can be kept extremely low. It can be kept safe.

[0069] The carrier concentration in the region 108C functioning as a channel forming region is preferably as low as possible. 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 Is less than or equal to More preferably, 1×10 16 cm -3 More preferably, it is 1×10 13 cm -3More preferably, it is as follows: 1×10 12 cm -3 or less, which is even more preferable. There is no particular limitation on the lower limit value of the carrier concentration in region 108C. For example, it can be 1×10 cm -9 cm -3 or less.

[0070] On the other hand, the carrier concentration in region 108N is, for example, 5×10 18 cm -3 or more, preferably 1×10 19 cm -3 or more, and more preferably 5×10 19 cm -3 or more. There is no particular limitation on the upper limit value of the carrier concentration in region 108N. For example, it can be 5×10 cm 21 cm -3

[0071] 22 cm -3 or the like.

[0072] The carrier concentration in region 108L can be a value between that in region 108C and that in region 108N. For example, it can be a value in the range of 1×10 14 cm -3 or more and 1×10 20 cm -3 less than. Note that the carrier concentration in region 108L does not have to be uniform. There may be a gradient such that the carrier concentration decreases from the region 108N side to the channel formation region. For example, either one or both of the hydrogen concentration or the oxygen deficiency concentration in region 108L may have a gradient such that the concentration decreases from the region 108N side to the channel formation region side.

[0073] ​​​​​​​​ The semiconductor layer 108 preferably contains a metal oxide. Also, for the insulating layer 103 and the insulating layer 110 that are in contact with the channel formation region of the semiconductor layer 108, it is preferable to use an oxide film. For example, oxide films such as a silicon oxide film, a silicon oxynitride film, and an aluminum oxide film can be used. Thereby, in the heat treatment or the like in the manufacturing process of the transistor 100, oxygen desorbed from the insulating layer 103 or the insulating layer 110 is supplied to the channel formation region of the semiconductor layer 108, and oxygen vacancies in the semiconductor layer 108 can be reduced.

[0074] A part of the end portion of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 overlaps with the conductive layer 112 and has a portion that functions as a gate insulating layer and a portion that does not overlap with the conductive layer 112 and the metal oxide layer 114 (that is, a portion that overlaps with the region 108L).

[0075] The insulating layer 110 may have a laminated structure of two or more layers. FIGS. 1B, 1C, and 2A show an example in which the insulating layer 110 has a three-layer structure of an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. Note that since the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can use insulating films of the same material, there are cases where the interfaces of the insulating layer 1 10a, the insulating layer 110b, and the insulating layer 110c cannot be clearly confirmed. Therefore, in the present embodiment, the interfaces of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are illustrated by broken lines.

[0076] The insulating layer 110a has a region in contact with the channel formation region of the semiconductor layer 108. The insulating layer 110c has a region in contact with the metal oxide layer 114. The insulating layer 110b is the insulating layer 11 It is located between 0a and the insulating layer 110c.

[0077] The insulating layers 110a, 110b, and 110c preferably are each an insulating film containing an oxide. At this time, the insulating layers 110a, 110b, and 110c are preferably formed continuously by the same film-forming apparatus.

[0078] For example, as the insulating layers 110a, 110b, and 110c, insulating layers containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used.

[0079] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a laminated structure of an oxide insulating film, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 has an insulating film capable of releasing oxygen. For example, oxygen can also be supplied into the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, etc. in an oxygen atmosphere on the insulating layer 110 after film formation, or forming an oxide film in an oxygen atmosphere on the insulating layer 110.

[0080] For example, the insulating layers 110a, 110b, and 110c can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, methods such as chemical vapor deposition (CVD) method and atomic layer deposition (ALD) method can be used for formation. Also, the CVD method includes plasma enhanced chemical vapor deposition (PECVD D: Plasma Enhanced CVD) method and thermal CVD method, etc.

[0081] In particular, the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are preferably formed by the plasma CVD method

[0082] Since the insulating layer 110a is formed on the semiconductor layer 108, it is preferably a film formed under conditions that do not damage the semiconductor layer 108 as much as possible. For example, it can be formed under conditions where the film formation rate (also referred to as the film formation rate) is sufficiently low

[0083] For example, when forming the insulating layer 110a by the plasma CVD method, forming under low power conditions can extremely reduce the damage to the semiconductor layer 108

[0084] When using a silicon oxynitride film as the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c, the film formation gas used for forming the silicon oxynitride film includes, for example, deposition gases containing silicon such as silane and disilane and oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. A raw material gas containing these can be used. In addition to the raw material gas, it may include dilution gases such as argon, helium um, and nitrogen

[0085] For example, by reducing the ratio of the flow rate of the deposition gas to the total flow rate of the film formation gas (hereinafter also simply referred to as the flow rate ratio) the film formation rate can be lowered, and a dense film with few defects can be formed

[0086] ​​​​​​ The insulating layer 110b is a film formed under conditions of a higher film formation rate than the insulating layer 110a. This makes it possible to improve productivity.

[0087] For example, the insulating layer 110b is formed under the condition that the flow rate ratio of the deposition gas is higher than that of the insulating layer 110a. This allows the film to be formed under conditions with an increased film formation rate.

[0088] The insulating layer 110c has reduced surface defects and is resistant to impurities such as water contained in the air. For example, similar to the insulating layer 110a, The film can be formed under conditions where the film formation rate is sufficiently low.

[0089] Since the insulating layer 110c is formed on the insulating layer 110b, the insulating layer 110c is thinner than the insulating layer 110a. The insulating layer 110c has little effect on the semiconductor layer 108 during the formation of the insulating layer 110c. The deposition layer 110a can be formed under a higher power condition than the insulating layer 110b. By reducing the power consumption and depositing the film at a relatively high power, a dense film with reduced surface defects can be obtained. can be done.

[0090] That is, in order from the highest deposition rate, the insulating layer 110b is the insulating layer 110a, and the insulating layer 110c is the insulating layer 110c. A laminated film formed under the conditions in which the above order is satisfied can be used for the insulating layer 110. The insulating layer 110 is formed by wet-insulating the insulating layer 110b, the insulating layer 110a, and the insulating layer 110c in this order. The etching rate is high under the same conditions for etching or dry etching.

[0091] The insulating layer 110b is preferably formed thicker than the insulating layers 110a and 110c. By forming the insulating layer 110b, which has the fastest film-forming speed, thick, the film-forming process of the insulating layer 110 is The time related to the process can be shortened.

[0092] Here, since the boundaries between the insulating layer 110a and the insulating layer 110b, and between the insulating layer 110b and the insulating layer 110 c may be unclear, in FIG. 1A and the like, these boundaries are illustrated by dashed lines. Note that since the insulating layer 110a and the insulating layer 110b have different film densities, in the transmission electron microscope (TEM) image of the cross-section of the insulating layer 110 and the like, these boundaries can be observed as differences in contrast. Similarly, the boundary between the insulating layer 110b and the insulating layer 110c can also be observed in some cases. When forming the conductive layer 112 and the metal oxide layer 114, the film thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112 may become thinner. FIGS. 1B, 1C, and 2A show a configuration in which the insulating layer 110c in the region that does not overlap with the conductive layer 1

[0093] 12 is removed and the insulating layer 110a and the insulating layer 110b remain. Also, compared with the insulating layer 110b in the region that overlaps with the conductive layer 112 the thickness of the insulating layer 110b in the region that does not overlap with the conductive layer 112 may become thinner. By thinning the film thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112, the amount of hydrogen supplied from the insulating layer 1 16 increases, and the resistance of the region 108L can be lowered. Also by adjusting the film thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112, the amount of hydrogen supplied from the insulating layer 1

[0094] 16 can be adjusted, and the resistance of the region 108L can be controlled. By thinning the film thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112, the amount of hydrogen supplied from the insulating layer 1 16 increases, and the resistance of the region 108L can be lowered. Also by adjusting the film thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112, the amount of hydrogen supplied from the insulating layer 1

[0095] By thinning the film thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112, the insulating layer 1 The step at the end 10 becomes smaller, and the layer formed on the insulating layer 110 (for example, the insulating layer 116) has improved step coverage, and it is possible to suppress the occurrence of defects such as step cuts and looseness in the layer.

[0096] FIG. 2B shows a configuration in which the insulating layers 110a, 110b, and insulating layer 110c remain in a region that does not overlap with the conductive layer 112. Also, compared with the insulating layer 110c in the region that overlaps with the conductive layer 112, there are cases where the thickness of the insulating layer 110c in the region that does not overlap with the conductive layer 112 becomes thinner. As shown in FIG. 2B, it is particularly preferable that the insulating layer 110c remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110c remains in the region that does not overlap with the conductive layer 112, it is possible to suppress the adsorption of water to the insulating layer 110. The thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less. and the insulating layer 1 10c in the region that does not overlap with the conductive layer 112 is thinner. As shown in FIG. 2B, it is particularly preferable that the insulating layer 110c remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110c remains in the region that does not overlap with the conductive layer 112, it is possible to suppress the adsorption of water to the insulating layer 110. The thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less. exists. As shown in FIG. 2B, it is particularly preferable that the insulating layer 110c remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110c remains in the region that does not overlap with the conductive layer 112, it is possible to suppress the adsorption of water to the insulating layer 110. The thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less. exists. As shown in FIG. 2B, it is particularly preferable that the insulating layer 110c remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110c remains in the region that does not overlap with the conductive layer 112, it is possible to suppress the adsorption of water to the insulating layer 110. The thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less. and the insulating layer 110c in the region that does not overlap with the conductive layer 112 is thinner. As shown in FIG. 2B, it is particularly preferable that the insulating layer 110c remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110c remains in the region that does not overlap with the conductive layer 112, it is possible to suppress the adsorption of water to the insulating layer 110. The thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less. and the insulating layer 110c in the region that does not overlap with the conductive layer 112 is thinner. As shown in FIG. 2B, it is particularly preferable that the insulating layer 110c remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110c remains in the region that does not overlap with the conductive layer 112, it is possible to suppress the adsorption of water to the insulating layer 110. The thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less. and more preferably 3 nm or more and 30 nm or less.

[0097] FIG. 2C shows an example in which the insulating layers 110a, 110b, and insulating layer 110c remain in a region that does not overlap with the conductive layer 112, and the thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is approximately equal to the thickness of the insulating layer 110c in the region that does not overlap with the conductive layer 112. exists, and the thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is approximately equal to the thickness of the insulating layer 110c in the region that does not overlap with the conductive layer 112. exists, and the thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is approximately equal to the thickness of the insulating layer 110c in the region that does not overlap with the conductive layer 112.

[0098] In addition, the insulating layer 110 may have a two-layer structure of the insulating layer 110a and the insulating layer 110c on the insulating layer 110a. Alternatively, the insulating layer 110 may have a single-layer structure. As the insulating layer 110, any one of the aforementioned insulating layer 110a, insulating layer 110b, or insulating layer 110c can be appropriately selected according to the purpose. In addition, the insulating layer 110 may have a single-layer structure. As the insulating layer 110, any one of the aforementioned insulating layer 110a, insulating layer 110b, or insulating layer 110c can be appropriately selected according to the purpose. In addition, the insulating layer 110 may have a single-layer structure. As the insulating layer 110, any one of the aforementioned insulating layer 110a, insulating layer 110b, or insulating layer 110c can be appropriately selected according to the purpose. In addition, the insulating layer 110 may have a single-layer structure. As the insulating layer 110, any one of the aforementioned insulating layer 110a, insulating layer 110b, or insulating layer 110c can be appropriately selected according to the purpose.

[0099] The insulating layer 116 covers the upper surface and the side surface of the conductive layer 112, the side surface of the metal oxide layer 114, the upper surface and the side surface of the insulating layer 1 10, the upper surface and the side surface of the semiconductor layer 108, and the upper surface of the insulating layer 103. The insulating layer 118 is provided to cover the insulating layer 116. The insulating layer 116 and the insulating layer 118 function as a protective layer and can suppress the diffusion of impurity elements from the outside.

[0100] The insulating layer 116 has a function of suppressing the diffusion of impurities from above the insulating layer 116 into the semiconductor layer 108. In addition, the insulating layer 116 has a function of reducing the resistance of the semiconductor layer 108 in contact with the insulating layer 116 during film formation. The insulating layer 116 is provided in contact with the upper surface and the side surface of the region 108N. The insulating layer 116 can use an insulating film that can supply impurities into the region 108N by heating during or after the film formation of the insulating layer 116. Alternatively, an insulating film that can cause oxygen deficiency in the region 108N can be used by heating during or after the film formation of the insulating layer 116. Alternatively, an insulating film that can cause oxygen deficiency in the region 108N can be used by heating during or after the film formation of the insulating layer 116. The insulating layer 116 is preferably a film formed using a film formation gas containing an impurity element such as hydrogen during film formation. For example, silane, ammonia, etc. can be used as the gas containing hydrogen. Also, by lowering the film formation temperature of the insulating layer 116, more impurity elements can be effectively supplied to the semiconductor

[0101] layer 108. The film formation temperature of the insulating layer 116 is preferably, for example, 200 °C or higher and 500 °C or lower, more preferably 220 °C or higher and 450 °C or lower, more preferably 230 °C or higher and 430 °C or lower, and even more preferably 250 °C or higher and 400 °C or lower. The film formation temperature of the insulating layer 116 is preferably, for example, 200 °C or higher and 500 °C or lower, more preferably 220 °C or higher and 450 °C or lower, more preferably 230 °C or higher and 430 °C or lower, and even more preferably 250 °C or higher and 400 °C or lower, and even more preferably 250 °C or higher and 400 °C or lower.

[0102] By forming the insulating layer 116 under reduced pressure and with heating, the desorption of oxygen from the region 1 in the semiconductor layer 108 can be promoted. By supplying impurities such as hydrogen to the semiconductor layer 108 in which many oxygen deficiencies are formed, the carrier concentration in the region 108N can be increased, and the region 108N can be made lower in resistance more effectively. The insulating layer 116 can preferably be an insulating film containing a nitride such as silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, or aluminum oxynitride. In particular, since silicon nitride has a blocking property against hydrogen and oxygen, it can prevent both the diffusion of hydrogen from the outside into the semiconductor layer 108 and the desorption of oxygen from the semiconductor layer 108 to the outside, and a highly reliable transistor can be realized. The insulating layer 116 can also be an insulating film having a function of attracting oxygen in the semiconductor layer 108 and generating oxygen deficiencies. In particular, it is particularly preferable to use a metal nitride such as aluminum nitride for the insulating layer 116. When a metal nitride is used for the insulating layer 116, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to contain aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using an aluminum sputtering target and a gas containing nitrogen as a film-forming gas has extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas with respect to the total flow rate of the film-forming gas.

[0103] By forming the insulating layer 116 under reduced pressure and with heating, the desorption of oxygen from the region 1 in the semiconductor layer 108 can be promoted. By supplying impurities such as hydrogen to the semiconductor layer 108 in which many oxygen deficiencies are formed, the carrier concentration in the region 108N can be increased, and the region 108N can be made lower in resistance more effectively. The insulating layer 116 can preferably be an insulating film containing a nitride such as silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, or aluminum oxynitride. In particular, since silicon nitride has a blocking property against hydrogen and oxygen, it can prevent both the diffusion of hydrogen from the outside into the semiconductor layer 108 and the desorption of oxygen from the semiconductor layer 108 to the outside, and a highly reliable transistor can be realized. The insulating layer 116 can also be an insulating film having a function of attracting oxygen in the semiconductor layer 108 and generating oxygen deficiencies. In particular, it is particularly preferable to use a metal nitride such as aluminum nitride for the insulating layer 116. When a metal nitride is used for the insulating layer 116, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to contain aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using an aluminum sputtering target and a gas containing nitrogen as a film-forming gas has extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas with respect to the total flow rate of the film-forming gas. The insulating layer 116 can also be an insulating film having a function of attracting oxygen in the semiconductor layer 108 and generating oxygen deficiencies. In particular, it is particularly preferable to use a metal nitride such as aluminum nitride for the insulating layer 116.

[0104] The insulating layer 116 can also be an insulating film having a function of attracting oxygen in the semiconductor layer 108 and generating oxygen deficiencies. In particular, it is particularly preferable to use a metal nitride such as aluminum nitride for the insulating layer 116. When a metal nitride is used for the insulating layer 116, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to contain aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using an aluminum sputtering target and a gas containing nitrogen as a film-forming gas has extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas with respect to the total flow rate of the film-forming gas. The insulating layer 116 can also be an insulating film having a function of attracting oxygen in the semiconductor layer 108 and generating oxygen deficiencies. In particular, it is particularly preferable to use a metal nitride such as aluminum nitride for the insulating layer 116.

[0105] When a metal nitride is used for the insulating layer 116, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to contain aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using an aluminum sputtering target and a gas containing nitrogen as a film-forming gas has extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas with respect to the total flow rate of the film-forming gas. The insulating layer 116 can also be an insulating film having a function of attracting oxygen in the semiconductor layer 108 and generating oxygen deficiencies. In particular, it is particularly preferable to use a metal nitride such as aluminum nitride for the insulating layer 116. When a metal nitride is used for the insulating layer 116, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to contain aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using an aluminum sputtering target and a gas containing nitrogen as a film-forming gas has extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas with respect to the total flow rate of the film-forming gas. The insulating layer 116 can also be an insulating film having a function of attracting oxygen in the semiconductor layer 108 and generating oxygen deficiencies. In particular, it is particularly preferable to use a metal nitride such as aluminum nitride for the insulating layer 116. When a metal nitride is used for the insulating layer 116, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to contain aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using an aluminum sputtering target and a gas containing nitrogen as a film-forming gas has extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas with respect to the total flow rate of the film-forming gas. The insulating layer 116 can also be an insulating film having a function of attracting oxygen in the semiconductor layer 108 and generating oxygen deficiencies. In particular, it is particularly preferable to use a metal nitride such as aluminum nitride for the insulating layer 116. It can be a film. Therefore, by providing such an insulating film containing a metal nitride in contact with the semiconductor layer 1 08, not only can the semiconductor layer 108 be made to have a lower resistance, but also the desorption of oxygen from the semiconductor layer 10 8 and the diffusion of hydrogen into the semiconductor layer 108 can be preferably prevented .

[0106] When aluminum nitride is used as the metal nitride, the thickness of the insulating layer containing the aluminum nitride is preferably 5 nm or more. Even such a thin film can achieve both high blocking properties against hydrogen and oxygen and the function of reducing the resistance of the semiconductor layer. Note that although there is no particular upper limit to the thickness of the insulating layer, considering productivity, it is preferably 500 nm or less, more preferably 20 0 nm or less, and even more preferably 50 nm or less .

[0107] When an aluminum nitride film is used for the insulating layer 116, a film having a composition formula of AlN x (x is a real number greater than 0 and less than or equal to 2, preferably, x is a real number greater than 0.5 and less than or equal to 1.5) is preferably used . This can make a film excellent in both insulation and heat conductivity, so that the heat dissipation when driving the transistor 100 can be enhanced . .

[0108] Alternatively, an aluminum nitride titanium film, a titanium nitride film, etc. can be used as the insulating layer 116 .

[0109] By providing such an insulating layer 116 in contact with the region 108N, the insulating layer 116 can attract oxygen in the region 1 08N and form oxygen vacancies in the region 108N. Also, after forming such an insulating layer 116, by performing a heat treatment, more oxygen vacancies can be formed in the region 108N It is possible to form oxygen deficiencies, which can promote a reduction in resistance. Also, when a film containing a metal oxide is used for the insulating layer 1 16, as a result of the insulating layer 116 attracting oxygen in the semiconductor layer 108 a layer containing an oxide of a metal element (for example, aluminum) contained in the insulating layer 116 may be formed between the insulating layer 116 and the region 108N. Since the region 108L does not contact the insulating layer 116 because the insulating layer 110 is present in between, the amount of hydrogen supplied from the insulating layer 116 is less than that of the region 108N. Furthermore, since the impurity concentration is also smaller than that of the region 108N, the region 108L can be in a higher resistance state than the region 108N.

[0110] As will be described later, since it is possible to form the region 108L self-alignedly, a photomask for forming the region 108L is not required, and the manufacturing cost can be reduced. Also, by forming the region 108L self-alignedly, since there is no relative displacement between the region 108L and the conductive layer 112, the widths of the regions 108L in the semiconductor layer 108 can be made to substantially coincide. Since the region 108L functions as an offset region where the electric field of the gate does not act (or acts less than in the channel formation region) between the channel formation region and the low-resistance region 108N in the semiconductor layer 108, the region 108L can be formed stably without variation. As a result, the source-drain breakdown voltage of the transistor can be improved, and a highly reliable transistor can be realized. The width L2 of the region 108L is preferably 100 nm or more and 2 μm or less, and more preferably 150 nm or less.

[0111]

[0112]

[0113] ​​​​​​​​​​It is preferably 1 μm or less, more preferably 200 nm or more and 1 μm or less. Region 108L By providing , the concentration of the electric field near the drain is alleviated, and in particular, the deterioration of the transistor in a state where the drain voltage is high can be suppressed. Further, in particular, by making the width L2 of the region 108L larger than the thickness of the insulating layer 110, the concentration of the electric field near the drain can be effectively suppressed On the other hand, if the width L2 is longer than 2 μm, the source-drain resistance increases , and the driving speed of the transistor may become slow. By setting the width L2 within the above-mentioned range, a transistor and a semiconductor device with high reliability and fast driving speed can be obtained. Note that the width L2 of the region 108L can be determined according to the thickness of the semiconductor layer 108, the thickness of the insulating layer 110, and the magnitude of the voltage applied between the source and the drain when driving the transistor 1 00.

[0114] By providing the region 108L between the channel formation region and the low-resistance region 108N, the current density at the boundary between the channel formation region and the region 108N can be alleviated, and the heat generation at the boundary between the channel and the source or the drain can be suppressed, and a highly reliable transistor and semiconductor device can be obtained

[0115] The insulating layer 103 can have a laminated structure. In FIG. 1, an example is shown in which the insulating layer 103 has a structure in which an insulating layer 103a, an insulating layer 103b, an insulating layer 103c, and an insulating layer 103d are laminated in this order from the substrate 102 side. The insulating layer 103a is in contact with the substrate 102. Also the insulating layer 103d is in contact with the semiconductor layer 108.

[0116] The insulating layer 103 has high withstand voltage, low film stress, and is difficult to release hydrogen and water ​​​​​​​In addition, there are few defects in the film, the diffusion of impurities contained in the substrate 102 is suppressed, and It is preferable that one or more of these conditions are satisfied, and it is most preferable that all of these conditions are satisfied.

[0117] Among the four insulating films of the insulating layer 103, the insulating layer 103a located on the substrate 102 side, The insulating layer 103b and the insulating layer 103c are preferably formed using an insulating film containing nitrogen. On the other hand, it is preferable to use an insulating film containing oxygen for the insulating layer 103d in contact with the semiconductor layer . In addition, the four insulating films of the insulating layer 103 are each formed using a plasma CVD apparatus. In particular, it is preferable to form the films continuously without exposing them to the air.

[0118] The insulating layer 103a, the insulating layer 103b, and the insulating layer 103c are, for example, a silicon nitride film, a nitride The insulating film containing nitrogen, such as a silicon oxide film, an aluminum nitride film, or a hafnium nitride film, is preferably used. The insulating layer 103d can be used as the insulating layer 110. The description of the insulating film can be used.

[0119] The insulating layers 103a and 103c can prevent the diffusion of impurities from below. The insulating layer 103a is preferably a dense film. The insulating layer 103c is a film that can block hydrogen and water contained in the insulating layer 103b. Therefore, it is preferable that the insulating layer 103a and the insulating layer 103c have a thickness of 100 nm or less. An insulating film formed under conditions of a lower film formation rate than that of b can be used.

[0120] On the other hand, the insulating layer 103b is made of an insulating film that is formed under conditions of low stress and high film formation speed. In addition, the insulating layer 103b is preferably made of a material other than the insulating layer 103a and the insulating layer 103c. It is preferably formed thickly.

[0121] For example, even when a silicon nitride film formed by plasma CVD is used for each of the insulating layer 103a, the insulating layer 103b, and the insulating layer 103c, the insulating layer 103b becomes a film with a lower film density than the other two insulating films. Therefore, in a transmission electron microscope image of the cross-section of the insulating layer 103, etc., it may be observed as a difference in contrast. Note that since the boundaries between the insulating layer 103a and the insulating layer 103b, and between the insulating layer 103b and the insulating layer 10 3c may be unclear, in FIG. 1 etc., these boundaries are indicated by dashed lines for clarity.

[0122] The insulating layer 103d in contact with the semiconductor layer 108 is preferably a dense insulating film on whose surface impurities such as water are difficult to adsorb. Also, it is preferred to use an insulating film with as few defects as possible and with reduced impurities such as water and hydrogen. For example, as the insulating layer 103d, an insulating film similar to the insulating layer 110c of the above-described insulating layer 110 can be used. With the insulating layer 103 having such a laminated structure, a highly reliable transistor can be

[0123] realized.

[0124] As shown in FIGS. 1B and 1C, the transistor 100 preferably has a region where the insulating layer 103c and the insulating layer 11 6 are in contact. An enlarged view of the region Q surrounded by the dashed line in FIG. 1B is shown in FIG. 3A, and an enlarged view of the region R surrounded by the dashed line in FIG. 1C is shown in FIG. 3B.

[0125] As shown in FIGS. 1B and 3A, in the channel length direction, it does not overlap with the semiconductor layer 108 The insulating layer 116 in the i region is provided in contact with the insulating layer 103c. Also, the end portion of the insulating layer 103d substantially coincides with the end portion of the semiconductor layer 108.

[0126] As shown in FIG. 3B, in the channel width direction, the insulating layer 116 in the region that does not overlap with the insulating layer 110 is provided in contact with the insulating layer 103c. Also, the end portion of the insulating layer 103d substantially coincides with the end portion of the insulating layer 110. For example, when forming the insulating layer 110, by removing the insulating film that becomes the insulating layer 103d in the region that does not overlap with the insulating layer 110, the end portion of the insulating layer 103d and the end portion of the insulating layer 110 can be made to substantially coincide. By having the insulating layer 103c and the region where the insulating layer 116 is in contact, diffusion of impurities from outside the transistor 100 into the transistor 100 can be suppressed. In particular, as the insulating layer 116 and the insulating layer 103c, insulating films each containing nitrogen can be suitably used.

[0127] By having the insulating layer 103c and the region where the insulating layer 116 is in contact, diffusion of impurities from outside the transistor 100 into the transistor 100 can be suppressed. In particular, as the insulating layer 116 and the insulating layer 103c, insulating films each containing nitrogen can be suitably used. and the insulating layer 103c, insulating films each containing nitrogen can be suitably used.

[0128] As shown in FIG. 3C, the end portion of the insulating layer 103d may be configured to substantially coincide with the end portion of the semiconductor layer 108. For example, when forming the semiconductor layer 108, by removing the insulating film that becomes the insulating layer 103d in the region that does not overlap with the semiconductor layer 108, the end portion of the insulating layer 103d and the semiconductor layer 108 can be made to substantially coincide. In the channel length direction, the film thickness of the insulating layer 103c in the region that does not overlap with the semiconductor layer 108 may be thinner than the film thickness of the insulating layer 103c in the region that overlaps with the semiconductor layer 108. An enlarged view of the region Q surrounded by the dashed-dotted line in FIG. 1B is shown in FIG. 4A. FIG. 4A shows that the film thickness of the insulating layer 103c in the region that does not overlap with the semiconductor layer 108 is thinner than the film thickness of the insulating layer 103c in the region that overlaps with the semiconductor layer 108. layer 108 can be made to substantially coincide.

[0129] In the channel length direction, the film thickness of the insulating layer 103c in the region that does not overlap with the semiconductor layer 108 may be thinner than the film thickness of the insulating layer 103c in the region that overlaps with the semiconductor layer 108. An enlarged view of the region Q surrounded by the dashed-dotted line in FIG. 1B is shown in FIG. 4A. FIG. 4A shows that the film thickness of the insulating layer 103c in the region that does not overlap with the semiconductor layer 108 is thinner than the film thickness of the insulating layer 103c in the region that overlaps with the semiconductor layer 108. As shown in FIG. 4A, the film thickness of the insulating layer 103c in the region that does not overlap with the semiconductor layer 108 is thinner than the film thickness of the insulating layer 103c in the region that overlaps with the semiconductor layer 108. An enlarged view of the region Q surrounded by the dashed-dotted line in FIG. 1B is shown in FIG. 4A. FIG. 4A shows that the film thickness of the insulating layer 103c in the region that does not overlap with the semiconductor layer 108 is thinner than the film thickness of the insulating layer 103c in the region that overlaps with the semiconductor layer 108. than the film thickness of the insulating layer 103c in the region that overlaps with the semiconductor layer 108. The film thickness is thin, and in a region where the film thickness of the insulating layer 103c is thin, an example where the insulating layer 103c and the insulating layer 116 are in contact is shown.

[0130] In the channel width direction, the film thickness of the insulating layer 103c in the region overlapping with the insulating layer 110 may be thinner than the film thickness of the insulating layer 103c in the region not overlapping with the insulating layer 110. An enlarged view of the region R surrounded by the dashed-dotted line in FIG. 1C is shown in FIGS. 4B and 4C. FIGS. 4B and 4C show that the film thickness of the insulating layer 103c in the region not overlapping with the insulating layer 110 is thinner than the film thickness of the insulating layer 103c in the region overlapping with the insulating layer 110, and in a region where the film thickness of the insulating layer 103c is thin, an example where the insulating layer 1 03c and the insulating layer 116 are in contact is shown. Also, in FIG. 4B, the end of the insulating layer 103d substantially coincides with the end of the insulating layer 110. In FIG. 4C, the end of the insulating layer 103d substantially coincides with the end of the semiconductor layer 108. Note that in FIGS. 4A, 4B, and 4C, an example where the insulating layer 103c and the insulating layer 116 are in contact is shown, however, one aspect of the present invention is not limited thereto. The insulating layer 103b may be exposed, and the insulating layer 103b and the insulating layer 116 may be in contact. Also, the insulating layer 103a may be exposed, and the insulating

[0131] layer 103a and the insulating layer 116 may be in contact. The ends of the insulating layer 110 and the metal oxide layer 114 preferably have a tapered shape, respectively. With such a configuration, the coverage of the layer (for example, the insulating layer 116) formed on the insulating layer 110 and the metal oxide layer 114 is improved, and it is possible to suppress the occurrence of defects such as steps and looseness in the layer.

[0132]

[0133] ​​​​​​A part of the conductive layer 112 functions as a gate electrode. A part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top-gate type transistor in which a gate electrode is provided on the semiconductor layer 108.

[0134] As shown in FIGS. 1A and 1B, the transistor 100 may have a conductive layer 120a and a conductive layer 120b on the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as source electrodes or drain electrodes. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108N through openings 141a or 141b provided in the insulating layer 118 and the insulating layer 116, respectively.

[0135] The semiconductor layer 108 preferably contains a metal oxide.

[0136] For example, the semiconductor layer 108 preferably has indium and one or more elements M (the element M is selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) and zinc. In particular, the element M is preferably one or more elements selected from aluminum, gallium, indium, or tin.

[0137] In particular, it is preferable to use an oxide containing indium, gallium, and zinc as the semiconductor layer 108.

[0138] As the semiconductor layer 108, layers with different compositions, or layers with different crystallinities, or impurity concentrations ​​​​​​​​It may be a laminated structure in which different layers are laminated.

[0139] For the conductive layer 112, it is preferable to use a material with low resistance. By using a material with low resistance for the conductive layer 112, the parasitic resistance can be reduced, and a transistor with a high on-current can be obtained, and a semiconductor device with a high on-current can be obtained. Further, in a large display device or a high-definition display device, by reducing the wiring resistance, signal delay can be suppressed, and high-speed driving becomes possible. As the conductive layer 112, copper, silver, gold, aluminum, or the like can be used. In particular, in addition to having low resistance, copper is preferable because of its excellent mass productivity. The conductive layer 112 may have a laminated structure. When the conductive layer 112 has a laminated structure, a second conductive layer is provided above or below, or both above and below, the first conductive layer with low resistance. As the second conductive layer, it is preferable to use a conductive material that is less likely to be oxidized (has oxidation resistance) than the first conductive layer. Further, as the second conductive layer, it is preferable to use a material that suppresses the diffusion of the components of the first conductive layer. As the second conductive layer, for example, indium oxide, indium zinc oxide, indium tin oxide (ITO), indium tin oxide containing silicon (ITSO), metal oxides such as zinc oxide, or metal nitrides such as titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride can be preferably used. The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film to prevent oxygen contained in the insulating layer 110 from diffusing to the conductive layer 112 side. Further, the metal oxide layer 114 prevents hydrogen or water contained in the conductive layer 112 from diffusing to the insulating layer 110 side. It can be a laminated structure. It is preferably a laminated structure.

[0140] The conductive layer 112 may have a laminated structure. When the conductive layer 112 has a laminated structure, a second conductive layer is provided above or below, or both above and below, the first conductive layer with low resistance. As the second conductive layer, it is preferable to use a conductive material that is less likely to be oxidized (has oxidation resistance) than the first conductive layer. Further, as the second conductive layer, it is preferable to use a material that suppresses the diffusion of the components of the first conductive layer. As the second conductive layer, for example, indium oxide, indium zinc oxide, indium tin oxide (ITO), indium tin oxide containing silicon (ITSO), metal oxides such as zinc oxide, or metal nitrides such as titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride can be preferably used. Above or below, or both above and below, the first conductive layer with low resistance, a second conductive layer is provided. As the second conductive layer, it is preferable to use a conductive material that is less likely to be oxidized (has oxidation resistance) than the first conductive layer. Further, as the second conductive layer, it is preferable to use a material that suppresses the diffusion of the components of the first conductive layer. As the second conductive layer, for example, indium oxide, indium zinc oxide, indium tin oxide (ITO), indium tin oxide containing silicon (ITSO), metal oxides such as zinc oxide, or metal nitrides such as titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride can be preferably used. It can be preferably used. It can be preferably used. It can be preferably used.

[0141] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film to prevent oxygen contained in the insulating layer 110 from diffusing to the conductive layer 112 side. Furthermore, the metal oxide layer 114 prevents hydrogen or water contained in the conductive layer 112 from diffusing to the insulating layer 110 side. It can be preferably used. It also functions as a barrier film to prevent [diffusion]. The metal oxide layer 114 can be made of a material that is less permeable to oxygen and hydrogen than, for example, at least the insulating layer 11 0.

[0142] Even when a metal material that easily attracts oxygen, such as aluminum or copper, is used for the conductive layer 112, the metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112. In addition, even when the conductive layer 112 contains hydrogen, it is possible to prevent hydrogen from diffusing from the conductive layer 112 through the insulating layer 110 to the semiconductor layer 108. As a result, the carrier concentration in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0143] As the metal oxide layer 114, an insulating material or a conductive material can be used. When the metal oxide layer 114 has insulating properties, it functions as part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductivity, it functions as part of the gate electrode.

[0144] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide as the metal oxide layer 114. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminide film is preferable because the driving voltage can be reduced.

[0145] As the metal oxide layer 114, metal oxides can be used. For example, oxides containing indium such as indium oxide, indium zinc oxide, indium tin oxide (ITO), and indium tin oxide containing silicon (ITSO) can be used. Conductive oxides containing indium are preferable because of their high conductivity. Also, ITSO contains silicon ​​​​​​​​​​​By containing it, it is difficult to crystallize and has high flatness, so it is formed on the ITSO The adhesion with the film increases. As the metal oxide layer 114, metal oxides such as zinc oxide and zinc oxide containing gallium can be used. Also, as the metal oxide layer 114, a structure in which these are laminated may be used.

[0146] As the metal oxide layer 114, it is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. At this time, by applying a metal oxide film formed using the same sputtering ring target as the semiconductor layer 108 as the metal oxide layer 114, the apparatus can be shared which is preferable.

[0147] Or, when using a metal oxide material containing indium and gallium for both the semiconductor layer 108 and the metal oxide layer 114, using a material with a higher gallium composition (content ratio) than the semiconductor layer 108 is preferable because the blocking property against oxygen can be further enhanced. At this time, by using a material with a higher indium composition than the metal oxide layer 114 for the semiconductor layer 108 the field effect mobility of the transistor 100 can be increased.

[0148] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example , when forming an oxide film using a sputtering apparatus, by forming it in an atmosphere containing oxygen gas oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0149] The semiconductor layer 108 is a channel formation region that overlaps with the conductive layer 112 via the insulating layer 110 ​It has. Further, the semiconductor layer 108 has a pair of regions 108N sandwiching the channel formation region. The region 108N is a region of the semiconductor layer 108 that does not overlap with either the conductive layer 112 or the insulating layer 110 and is in contact with the insulating layer 116.

[0150] The region 108N can also be referred to as a region having a lower resistance than the channel formation region, a region having a high carrier concentration, a region having a high oxygen defect density, a region having a high impurity concentration, or an n-type region.

[0151] The region 108N is a region containing an impurity element (first element). Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, or a noble gas. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to contain boron, phosphorus, magnesium, or aluminum. It may also contain two or more of these elements.

[0152] Here, the impurity concentration in the region 108N preferably has a concentration gradient such that the concentration increases as it approaches the insulating layer 116. Thereby, compared to the case of making the concentration uniform throughout the region 108N, the total amount of impurity elements in the region 108N can be reduced, so that the amount of impurities that can diffuse into the channel formation region due to the influence of heat or the like during the manufacturing process can be kept low. Also, since the upper part of the region 108N has a lower resistance, the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be more effectively reduced.

[0153] As will be described later, the process of adding an impurity element to the region 108N uses the insulating layer 110 as a mask. It can be performed as such. Thereby, the region 108N can be formed self-alignedly.

[0154] The region 108N has an impurity concentration of 1×10 19 atoms / cm 3 or more and 1×10 23 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or more and 5×10 2 2 atoms / cm 3 or less, more preferably 1×10 20 atoms / cm 3 or more and 1× 10 22 atoms / cm 3 or less, and preferably includes a region having such an impurity concentration.

[0155] The concentration of impurities contained in the region 108N can be analyzed by, for example, secondary ion mass spectrometry (SIMS: S econdary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), etc. When using XPS analysis, by combining ion sputtering from the front side or the back side with XPS analysis, the concentration distribution in the depth direction can be known.

[0156] In the region 108N, it is preferable that the impurity element exists in an oxidized state. For example, it is preferable to use elements such as boron, phosphorus, magnesium, aluminum, and silicon that are easily oxidized as the impurity element. Such easily oxidized elements can stably exist in an oxidized state by combining with oxygen in the semiconductor layer 108 because they can combine with oxygen in the semiconductor layer 108 and exist stably in an oxidized state. Therefore, in subsequent processes at a high temperature (for example, Even when a temperature of 400 °C or higher, 600 °C or higher, or 800 °C or higher is applied, the desorption is suppressed. Also, when impurity elements deprive oxygen in the semiconductor layer 108, a large number of oxygen vacancies (V ) are generated in the region 108N. Hydrogen in the film enters these oxygen vacancies (V ), creating defects (hereinafter referred to as V O H) that serve as carrier sources, causing the region 108N to become in a state of extremely low resistance. O When performing a process that involves a high temperature in a later step, if a large amount of oxygen is supplied to the region 108N from the outside or from the film near the region 108N, the resistance may increase. Therefore, when performing a process involving a high temperature, it is preferable to perform the process with the semiconductor layer 108 covered with the insulating layer 116 that has a high barrier property against oxygen. O The insulating layer 116 is provided in contact with the region 108N of the semiconductor layer 108. The insulating layer 116 functions as a hydrogen supply source for the region 108N. For example, the insulating layer 116 is preferably a film that releases hydrogen upon heating. By providing such an insulating layer 116 in contact with the region 108N and performing a heat treatment after the formation of the insulating layer 116, hydrogen can be supplied to the region 108N to reduce the resistance.

[0157] When performing a process that involves a high temperature in a later step, if a large amount of oxygen is supplied to the region 108N from the outside or from the film near the region 108N, the resistance may increase. Therefore, when performing a process involving a high temperature, it is preferable to perform the process with the semiconductor layer 108 covered with the insulating layer 116 that has a high barrier property against oxygen. The insulating layer 116 is provided in contact with the region 108N of the semiconductor layer 108. The insulating layer 116 functions as a hydrogen supply source for the region 108N. For example, the insulating layer 116 is preferably a film that releases hydrogen upon heating. By providing such an insulating layer 116 in contact with the region 108N and performing a heat treatment after the formation of the insulating layer 116, hydrogen can be supplied to the region 108N to reduce the resistance.

[0158] The insulating layer 116 is provided in contact with the region 108N of the semiconductor layer 108.

[0159] The insulating layer 116 functions as a hydrogen supply source for the region 108N. For example, the insulating layer 116 is preferably a film that releases hydrogen upon heating. By providing such an insulating layer 116 in contact with the region 108N and performing a heat treatment after the formation of the insulating layer 116, hydrogen can be supplied to the region 108N to reduce the resistance. The insulating layer 116 is preferably a film formed using a film-forming gas containing hydrogen when forming the film. This enables effective supply of hydrogen to the region 108N even during the formation of the insulating layer 116. By providing such an insulating layer 116 in contact with the region 108N and performing a heat treatment after the formation of the insulating layer 116, hydrogen can be supplied to the region 108N to reduce the resistance. The insulating layer 116 is preferably a film formed using a film-forming gas containing hydrogen when forming the film. This enables effective supply of hydrogen to the region 108N even during the formation of the insulating layer 116.

[0160] The insulating layer 116 is preferably a film formed using a film-forming gas containing hydrogen when forming the film. This enables effective supply of hydrogen to the region 108N even during the formation of the insulating layer 116. This enables effective supply of hydrogen to the region 108N even during the formation of the insulating layer 116. This enables effective supply of hydrogen to the region 108N even during the formation of the insulating layer 116.

[0161] The insulating layer 116 may be, for example, silicon nitride, silicon oxynitride, silicon oxynitride, or nitride. An insulating film of aluminum, aluminum nitride oxide, or the like can be used.

[0162] The region 108N contains many oxygen vacancies due to the addition of impurity elements as described above. Therefore, in addition to the hydrogen contained in the semiconductor layer 108, the hydrogen is further absorbed from the insulating layer 116. By supplying hydrogen to the semiconductor, the carrier concentration can be further increased.

[0163] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, an inorganic insulating material such as an oxide or a nitride can be used. Examples include silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, Aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium aluminate, etc. Any inorganic insulating material can be used. In addition, the insulating layer 118 can be used as a planarizing layer. In that case, the insulating layer 118 can be made of an organic resin material.

[0164] In this example, a laminated structure of an insulating layer 116 and an insulating layer 118 is used as the protective layer. However, if the insulating layer 118 is unnecessary, it may not be provided. A laminated structure may also be used.

[0165] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described. I will explain it below.

[0166] The oxygen vacancies formed in the channel formation region of the semiconductor layer 108 affect the transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, the oxygen Hydrogen can enter the defect to serve as a carrier source. When a carrier source is generated in the channel formation region, variations in the electrical characteristics of the transistor 100, typically a shift in the threshold voltage occur. Therefore, in the channel formation region, it is preferable that the oxygen deficiency is less.

[0167] Therefore, in one aspect of the present invention, the insulating film near the channel formation region of the semiconductor layer 108 , specifically, the insulating layer 110 located above the channel formation region and the insulating layer 103 located below are configured to include an oxide film. By moving oxygen from the insulating layer 103 and the insulating layer 110 to the channel formation region due to heat during the manufacturing process or the like, it becomes possible to reduce the oxygen deficiency in the channel formation region.

[0168] The semiconductor layer 108 preferably has a region where the atomic ratio of In to element M is greater than 1. The higher the In content, the more the field-effect mobility of the transistor can be improved.

[0169] Here, in the case of a metal oxide containing In, Ga, and Zn, the binding force between In and oxygen is weaker than the binding force between Ga and oxygen. Therefore, when the In content is high, oxygen deficiency is likely to be formed in the metal oxide film. Also, even when the metal element represented by M is used instead of Ga, there is a similar tendency. If there are many oxygen deficiencies in the metal oxide film, the electrical characteristics of the transistor deteriorate , and the reliability decreases.

[0170] However, in one aspect of the present invention, since a very large amount of oxygen can be supplied to the channel formation region of the semiconductor layer 108 containing a metal oxide, a metal oxide material with a high In content is used. This becomes possible. As a result, a transistor can be realized that combines extremely high field-effect mobility, stable electrical characteristics, and high reliability.

[0171] For example, a metal oxide in which the atomic ratio of In to element M is 1.5 or more, or 2 or more, or 3 or more, or 3.5 or more, or 4 or more can be preferably used.

[0172] In particular, it is preferable that the ratio of the number of atoms of In, M, and Zn in the semiconductor layer 108 is In:M:Zn = 4:2 :3 or in the vicinity thereof. Alternatively, it is preferable that the ratio of the number of atoms of In, M, and Zn is , In:M:Zn = 5:1:6 or in the vicinity thereof. Further, as the composition of the semiconductor layer 1 08, the ratio of the number of atoms of In, element M, and Zn in the semiconductor layer 108 may be approximately equal . That is, a material in which the ratio of the number of atoms of In, element M, and Zn is In:M:Zn = 1: 1:1 or in the vicinity thereof may be included.

[0173] For example, by using the above transistor with high field-effect mobility as a gate driver that generates a gate signal, a display device with a narrow frame width (also referred to as a narrow frame) can be provided. Also, by using the above transistor with high field-effect mobility as a source driver (particularly, a demultiplexer connected to the output terminal of the shift register included in the source driver), a display device with a small number of wirings connected to the display device can be provided.

[0174] Note that even if the semiconductor layer 108 has a region where the atomic ratio of In to element M is greater than 1, when the crystallinity of the semiconductor layer 108 is high, the field-effect mobility may decrease. The crystallinity of the semiconductor layer 108 is, for example, X-ray diffraction (XRD: X-Ray Diffracti on)​​ It is analyzed using X-ray photoelectron spectroscopy (XPS) or analyzed using a transmission electron microscope (TEM). It can be analyzed.

[0175] Here, the channel formation region of the semiconductor layer 108 has a low impurity concentration and a low defect level density (with few oxygen deficiencies), so that the carrier concentration in the film can be lowered. By using such a metal oxide film for the channel formation region of the semiconductor layer, the carrier concentration in the film can be lowered. A transistor using such a metal oxide film for the channel formation region of the semiconductor layer rarely has electrical characteristics (also called normally-on) in which the threshold voltage becomes negative. Also A transistor using such a metal oxide film can obtain characteristics in which the off-current is extremely small. A transistor using such a metal oxide film can obtain characteristics in which the off-current is extremely small. It can be achieved.

[0176] When a highly crystalline metal oxide film is used for the semiconductor layer 108, damage during processing of the semiconductor layer 108 or during film formation of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. When a highly crystalline metal oxide film is used for the semiconductor layer 108, damage during processing of the semiconductor layer 108 or during film formation of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. On the other hand, by using a metal oxide film with relatively low crystallinity for the semiconductor layer 108, electrical conductivity can be improved, and a transistor with high field-effect mobility can be realized. On the other hand, by using a metal oxide film with relatively low crystallinity for the semiconductor layer 108, electrical conductivity can be improved, and a transistor with high field-effect mobility can be realized.

[0177] The semiconductor layer 108 preferably uses a metal oxide film having a CAAC (c-axis aligned crystal) structure, a metal oxide film having an nc (nano crystal) structure, or a metal oxide film in which the CAAC structure and the nc structure are mixed. The semiconductor layer 108 preferably uses a metal oxide film having a CAAC (c-axis aligned crystal) structure, a metal oxide film having an nc (nano crystal) structure, or a metal oxide film in which the CAAC structure and the nc structure are mixed. The semiconductor layer 108 preferably uses a metal oxide film having a CAAC (c-axis aligned crystal) structure, a metal oxide film having an nc (nano crystal) structure, or a metal oxide film in which the CAAC structure and the nc structure are mixed. It is preferable.

[0178] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0179] For example, it is possible to use the semiconductor layer 108 in which two or more metal oxide films having different compositions are stacked. It is possible. For example, when using an In-M-Zn oxide, the atomic number ratios of In, element M, and Zn are In:M:Zn = 5:1:6, In:M:Zn = 4:2:3, In:M:Zn = 1:1:1, In:M:Zn = 2:2:1, In:M:Zn = 1:3:4, In:M: Zn = 1:3:2, or a sputtering target in the vicinity thereof, it is preferable to use a film formed by laminating two or more of them.

[0180] A semiconductor layer 108 in which two or more metal oxide films having different crystallinities are laminated can be used. In that case, by using the same oxide target and varying the film formation conditions, it is preferably formed continuously without being exposed to the atmosphere.

[0181] At this time, the semiconductor layer 108 can have a laminated structure of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Or, it may be a laminated structure of a metal oxide film having an nc structure and a metal oxide film having an nc structure. Note that, regarding the function of the metal oxide that can be suitably used for the metal oxide film or the composition of the material, the description of CAC (Cloud-Aligned Composite) described later can be incorporated. For example, the oxygen flow rate ratio during the film formation of the first metal oxide film formed first is made smaller than the oxygen flow rate ratio during the film formation of the second metal oxide film formed later. Or, during the film formation of the first metal oxide film, the condition is such that oxygen is not passed. Thereby, oxygen can be effectively supplied during the film formation of the second metal oxide film. Also, the first metal oxide film can be a film having lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, the second metal acid

[0182] oxide film provided on the upper part ​​​​​​​​By making the oxide film a film with higher crystallinity than the first metal oxide film, the processing of the semiconductor layer 108 during the time or the damage during the film formation of the insulating layer 110 can be suppressed.

[0183] More specifically, the oxygen flow rate ratio during the film formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10% is set. Also, the oxygen flow rate ratio during the film formation of the second metal oxide film is 50% or more and 100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 100% or less, even more preferably 90% or more and 100% or less, and typically 100%. Also, the first metal oxide film and the second metal oxide film may have different conditions such as pressure, temperature, and power during film formation. However, by setting the conditions other than the oxygen flow rate ratio to be the same, the time required for the film formation process can be shortened, which is preferable .

[0184] By adopting such a configuration, a transistor 100 with excellent electrical characteristics and high reliability can be realized.

[0185] Hereinafter, a configuration example of a transistor in which some configurations are different from those in Configuration Example 1 will be described . In the following, parts that overlap with Configuration Example 1 may be omitted from the description. Also, hereinafter in the drawings shown, parts having the same functions as those in the above configuration example may have the same hatching pattern and may not be labeled.

[0186] <Configuration Example 2> FIG. 5A is a top view of the transistor 100A, FIG. 5B is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 5C is a cross-sectional view of the transistor 100A in the channel width direction That is. An enlarged view of the region P surrounded by the dashed-dotted line in FIG. 5B is shown in FIG. 6A. The dashed-dotted line in FIG. 5C An enlarged view of the surrounded region R is shown in FIG. 6B.

[0187] The transistor 100A is mainly different from the transistor 100 in that the end of the conductive layer 112 is located inside the end of the metal oxide layer 114. Also, the insulating layer 116 is provided in contact with the upper surface and the side surface of the metal oxide layer. In the transistor 100A, the end of the conductive layer 112 is located inside the end of the metal oxide layer 114. In other words, the metal oxide layer 114 has a portion protruding outside the end of the conductive layer 112 at least on the insulating layer 110.

[0188] In the transistor 100A, the end of the conductive layer 112 is located inside the end of the metal oxide layer 114. That is, the metal oxide layer 114 has a portion protruding outside the end of the conductive layer 112 at least on the insulating layer 110.

[0189] Since the end of the conductive layer 112 is located inside the end of the metal oxide layer 114, the step on the side surface of the conductive layer 112 and the metal oxide layer 114 becomes gentle, and the step coverage of the layer (for example, the insulating layer 116) formed on the conductive layer 112 and the metal oxide layer 114 is improved, and it is possible to suppress the occurrence of defects such as step breakage and looseness in the layer.

[0190] For the formation of the conductive layer 112 and the metal oxide layer 114, a wet etching method can be preferably used. Also, by using a material with a slower etching rate than the conductive layer 112 for the metal oxide layer 114, the end of the conductive layer 112 can be made inside the end of the metal oxide layer 114. Furthermore, the metal oxide layer 114 and the conductive layer 112 can be formed in the same process, and the productivity can be improved.

[0191] The above is the description of Configuration Example 2.

[0192] ​​​​​​​​​<Configuration Example 3> FIG. 7A is a top view of the transistor 100B, and FIG. 7B is a cross-sectional view of the transistor 100B taken along the channel length direction, and FIG. 7C is a cross-sectional view of the transistor 100B taken along the channel width direction is. An enlarged view of the region P surrounded by the dashed line in FIG. 7B is shown in FIG. 8A. A dashed line in FIG. 7B An enlarged view of the surrounded region Q is shown in FIG. 8B. An enlarged view of the region R surrounded by the dashed line in FIG. 7C is shown in FIG. 8C.

[0193] The transistor 100B is mainly different from the transistor 100A in that the insulating layer 116 has a laminated structure. The insulating layer 116 can have a laminated structure of two or more layers. When the insulating layer 116 has a laminated structure, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. When the insulating layer 116 has a laminated structure, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0194] FIGS. 7B, 7C, 8A, 8B, and 8C show an example in which the insulating layer 116 has a two-layer structure of an insulating layer 116a and an insulating layer 116b on the insulating layer 116a. As the insulating layer 116a and the insulating layer 116b, materials that can be used for the insulating layer 116 can be used. The insulating layer 116a and the insulating layer 116b may use the same material or different materials. Since the insulating layer 116a and the insulating layer 116b can use insulating films of the same type of material, there may be cases where the interfaces of the insulating layer 116a and the insulating layer 116b cannot be clearly confirmed. Therefore, in the present embodiment, the interfaces of the insulating layer 116a and the insulating layer 116b are illustrated by broken lines. Since the insulating layer 116a and the insulating layer 116b can use insulating films of the same type of material, there may be cases where the interfaces of the insulating layer 116a and the insulating layer 116b cannot be clearly confirmed. Therefore, in the present embodiment, the interfaces of the insulating layer 116a and the insulating layer 116b are illustrated by broken lines. are illustrated by broken lines.

[0195] As shown in FIGS. 8A and 8B, the insulating layer 116 is in contact with the region 108N and is in the region 108N functions as a hydrogen supply source for. For example, the insulating layer 116 is preferably a film that releases hydrogen when heat is applied.

[0196] The insulating layer 116 can be formed in an atmosphere containing hydrogen. For example, the insulating layer 116 is preferably formed by plasma CVD using a film-forming gas containing hydrogen. For example as the insulating layer 116, a silicon nitride film can be formed using a film-forming gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen can be contained in the insulating layer 116. Also, during the formation of the insulating layer 116 it is possible to supply hydrogen to the exposed portion of the semiconductor layer 108.

[0197] However, when the insulating layer 116 is formed in an atmosphere containing hydrogen, the exposed region of the semiconductor layer 108 may be reduced during the formation of the insulating layer 116. When the surface of the semiconductor layer 108 is reduced, the roughness of the surface of the semiconductor layer 108 increases, and defects such as steps and looseness may occur in the layer formed on the semiconductor layer 108 (for example, the insulating layer 116, etc.).

[0198] Therefore, the hydrogen contained in the atmosphere used for the formation of the insulating layer 116a located on the semiconductor layer 108 side is preferably less than the hydrogen contained in the atmosphere used for the formation of the insulating layer 116b. For example, a mixed gas of silane, nitrogen, and ammonia can be used for the formation of each of the insulating layer 116a and the insulating layer 116b, and the flow rate of ammonia used for the formation of the insulating layer 116a can be made less than the flow rate of ammonia used for the formation of the insulating layer 116b. Or, for the insulating layer 1 16b, 16b, ​​​​​​​A mixed gas of silane and nitrogen is used for the formation of 16a, and a mixed gas of silane, nitrogen and ammonia can be used for the formation of the insulating layer 116b. Further, compared with the insulating layer 116b, the insulating layer 116a preferably has a region with a low hydrogen concentration. With such a configuration, reduction of the surface of the semiconductor layer 108 can be suppressed.

[0199] For example, even when a silicon nitride film formed by plasma CVD is used for the insulating layer 116a and the insulating layer 116b, since the film densities are different, these boundaries can be observed as differences in contrast in a transmission type electron microscope (TEM) image or the like of the cross section of the insulating layer 110. For example, compared with the insulating layer 116b, the insulating layer 116a may have a region with a high film density. In TEM observation, when the film density is high, the transmission electron (TE) image becomes dark (dense), and when the film density is low, the transmission electron (TE) image becomes light (bright). Therefore, in the transmission electron (TE) image, the insulating layer 116a may become a dark (dense) image compared with the insulating layer 116b. Also, compared with the insulating layer 116b, the insulating layer 116a may have a region with a low hydrogen concentration in the film. The difference in the hydrogen concentration between the insulating layer 116a and the insulating layer 116b can be evaluated, for example, by secondary ion mass spectrometry (SIMS).

[0200] It is preferable to use a material having blocking properties against hydrogen, water, and oxygen for the insulating layer 116b. Also, it is preferable that the insulating layer 116b has higher blocking properties against hydrogen, water, and oxygen than the insulating layer 116a. Since the insulating layer 116b provided on the insulating layer 116a has blocking properties against hydrogen, water, and oxygen, from the outside to the semiconductor layer 1 ​Diffusion of hydrogen to 08 and diffusion of water are suppressed, and desorption of oxygen from the semiconductor layer 108 to the outside can be suppressed, and a highly reliable transistor can be realized. It is possible to realize a highly reliable transistor.

[0201] The insulating layer 116 in contact with the semiconductor layer 108 preferably has few defects in the film. For example When silicon nitride is used as the insulating layer 116, typical defects in the silicon nitride film include K centers and the like. The K center is caused by the dangling bond of silicon and can be evaluated by the electron spin resonance method (ESR: Electron Spin Resonance). It can be done.

[0202] By making the hydrogen contained in the atmosphere used for forming the insulating layer 116a less than the hydrogen contained in the atmosphere used for forming the insulating layer 116b, the defects in the insulating layer 116a may be more than those in the insulating layer 116 b. Therefore, when the insulating layer 116 has a single-layer structure of only the insulating layer 116a, the defects in the film as a whole of the insulating layer 116 increase. Therefore If the insulating layer 116 has a single-layer structure of only the insulating layer 116a, the defects in the film as a whole of the insulating layer 116 will increase. Therefore When the insulating layer 116 has a single-layer structure of only the insulating layer 116a, the defects in the film as a whole of the insulating layer 116 will increase. Therefore Therefore, by forming the insulating layer 116 into a laminated structure of the insulating layer 116a and the insulating layer 116b, the defects in the film as a whole of the insulating layer 116 can be reduced.

[0203] The film thickness of the insulating layer 116b is preferably 0.5 times or more and 30 times or less the film thickness of the insulating layer 116a , more preferably 1 time or more and 25 times or less, still more preferably 2 times or more and 20 times or less, and still more preferably 3 times or more and 10 times or less, and still more preferably 4 times or more and 5 times or less. By forming the insulating layer 1 16 into a laminated structure, the insulating layer 116 has a blocking property against hydrogen, water, and oxygen and suppresses the reduction of the surface of the semiconductor layer 108 during the formation of the insulating layer 116 At the same time, the amount of defects in the insulating layer 116 can be reduced.

[0204] The insulating layer 116a and the insulating layer 116b are preferably formed continuously without being exposed to the atmosphere using a plasma CVD apparatus respectively. By forming the films continuously, the adhesion of impurities to the interface between the insulating layer 116a and the insulating layer 116b can be suppressed. Further, the insulating layer 116a, the insulating layer 116b, and the insulating layer 118 are preferably formed continuously without being exposed to the atmosphere using a plasma CVD apparatus respectively. By forming the films continuously, the adhesion of impurities to the interface between the insulating layer 116a and the insulating layer 116b and the interface between the insulating layer 116b and the insulating layer 118 can be suppressed.

[0205] The above is the description of Configuration Example 3.

[0206] <Configuration Example 4> FIG. 9A is a top view of the transistor 100C, FIG. 9B is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. 9C is a cross-sectional view of the transistor 100C in the channel width direction.

[0207] The transistor 100C mainly differs from the transistor 100 in that it has a conductive layer 106 between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with the channel formation region of the semiconductor layer 108, the metal oxide layer 114, and the conductive layer 112.

[0208] In the transistor 100C, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode). Further, a part of the insulating layer 103 serves as the first gate insulating layer and ​​​​​​​​​ functions, and a part of the insulating layer 110 functions as a second gate insulating layer.

[0209] The portion of the semiconductor layer 108 that overlaps at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. For ease of explanation below, the portion of the semiconductor layer 10 8 that overlaps the conductive layer 112 may be referred to as the channel formation region, but actually, a channel can also be formed in the portion that overlaps the conductive layer 106 (the portion including the region 108N) without overlapping the conductive layer 112.

[0210] As shown in FIGS. 9A and 9C, the conductive layer 106 may be electrically connected to the conductive layer 112 through the opening 142 provided in the metal oxide layer 114, the insulating layer 110, , and the insulating layer 103. Thereby, the same potential can be applied to the conductive layer 106 and the conductive layer 112.

[0211] The conductive layer 106 can use the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, using a material containing copper for the conductive layer 106 is preferable because it can reduce the wiring resistance. Also, using a material containing a high melting point metal such as tungsten or molybdenum for the conductive layer 106 enables processing at a high temperature in a later process.

[0212] As shown in FIGS. 9A and 9C, in the channel width direction, it is preferable that the conductive layer 112 and the conductive layer 1 06 protrude outside the end of the semiconductor layer 108. At this time, as shown in FIG. 9C, the entire channel width direction of the semiconductor layer 108 is covered by the conductive layer 112 and the conductive layer 106 through the insulating layer 110 and the insulating layer 1 03.

[0213] With such a configuration, the semiconductor layer 108 can be electrically surrounded by the electric field generated by the pair of gate electrodes. At this time, in particular, it is preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. Thereby, since the electric field for inducing a channel in the semiconductor layer 108 can be effectively applied, the on-current of the transistor 100C can be increased. Therefore, it is also possible to miniaturize the transistor 100C.

[0214] Note that the conductive layer 112 and the conductive layer 106 may not be connected. At this time, a fixed potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100C may be applied to the other. At this time, the threshold voltage when driving the transistor 100C with the other electrode can also be controlled by the potential applied to one electrode.

[0215] The insulating layer 103 may have a stacked structure. FIGS. 9B and 9C show an example having a structure in which the insulating layer 103a, the insulating layer 103b, the insulating layer 103c, and the insulating layer 103d are stacked in this order from the conductive layer 106 side. The insulating layer 103a is in contact with the conductive layer 106. The insulating layer 103a is preferably a film that can block the metal elements contained in the conductive layer 106. Since the above description can be referred to for the insulating layer 103a, the insulating layer 103b, the insulating layer 103c, and the insulating layer 103d, detailed description thereof is omitted.

[0216] Note that in the case of using a metal film or an alloy film that is difficult to diffuse into the insulating layer 103 as the conductive layer 106, etc., a configuration in which three insulating films of the insulating layer 103b, the insulating layer 103c, and the insulating layer 103d are stacked without providing the insulating layer 103a may be adopted.

[0217] The insulating layer 103 having such a laminated structure can realize a highly reliable transistor.

[0218] The above is the description of Configuration Example 4.

[0219] <Fabrication Method Example 1> Hereinafter, a method for manufacturing a semiconductor device according to an aspect of the present invention will be described with reference to the drawings. Here, the transistor 100C illustrated in the above configuration example will be described as an example.

[0220] Note that the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like. The CVD method includes plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. Further, one of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD).

[0221] The thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by spin coating, dip coating, spray coating, inkjet, dispensing, screen printing, offset printing, doctor blade, slit coating, roll coating, curtain coating, knife coating, or the like.

[0222] When processing the thin films constituting the semiconductor device, processing can be performed using photolithography or the like. Alternatively, the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like. Further, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask. ​​​​

[0223] There are typically two methods for photolithography. One is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask. Another is to form a photosensitive thin film and then perform exposure and development to process the thin film into a desired shape. In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.

[0224] Moreover, immersion exposure technology can be used for exposure. Also, extreme ultraviolet light (EUV), X-rays, etc. can be used instead of the light used for exposure. In addition, an electron beam can be used instead of the light used for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because extremely fine processing becomes possible. When performing exposure by scanning a beam such as an electron beam, a photomask is not required. For the etching of the thin film, a dry etching method, a wet etching method, a sandblasting method, etc. can be used. Figs. 10 to 14 show cross-sections at each stage of the manufacturing process of the transistor 100C. In each figure, cross-sections in the channel length direction are arranged on the left side of the central dashed line, and cross-sections in the channel width direction are arranged on the right side.

[0225]

[0226]

[0227] ​​​​​​​​​[Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a first gate electrode. A conductive layer 106 is formed to function as a conductive layer (FIG. 10A).

[0228] [Formation of insulating layer 103] Subsequently, an insulating layer 103 is formed covering the substrate 102 and the conductive layer 106 (FIG. 10B). The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0229] Here, the insulating layer 103 includes an insulating layer 103a, an insulating layer 103b, an insulating layer 103c, In particular, each of the insulating layers constituting the insulating layer 103 is made of P It is preferable to form it by the ECVD method.

[0230] The insulating layer 103a preferably has a function of blocking impurities. By providing 3a, impurities from the layer below the insulating layer 103 can be prevented from reaching the layer above the insulating layer 103. The insulating layer 103b has a low stress and a high dielectric strength. By providing the insulating layer 103b, it is possible to obtain an insulating layer having a small stress and a high withstand voltage. The insulating layer 103c releases less impurities having hydrogen and is It is preferable that the insulating layer 103c has a function of blocking impurities having hydrogen. By providing the insulating layer 10, it is possible to suppress diffusion of hydrogen into the channel formation region. It is preferable that 3d has a low defect density and emits little hydrogen-containing impurities.

[0231] The insulating layers 103a, 103b, and 103c are made of silicon nitride films. The case where a silicon oxynitride film is used for the insulating layer 103d will be described. The insulating layer is then formed by plasma CVD using a mixture of fluorine, nitrogen and ammonia gas. A mixed gas having a higher ammonia flow rate than that of the edge layer 103a is used, and the stress is small and the dielectric strength is high. Next, a mixture having a lower ammonia flow rate than the insulating layer 103b is formed. By using gas, the release of hydrogen-containing impurities is small and hydrogen-containing impurities are blocked. Next, a mixed gas of silane and dinitrogen monoxide is deposited on the insulating layer 103c. The insulating layer 103d is formed by using a silicon nitride film, which has a low defect density and emits less hydrogen-containing impurities. By changing the film forming conditions in the same chamber, the insulating layer 103 can be formed. As a result, the insulating layers 103a, 103b, 103c, and 103d are formed in a vacuum. Since the films can be formed successively, the insulating layer 103 can be formed with high productivity.

[0232] Alternatively, after the insulating layer 103c is formed, a plasma treatment is performed in an atmosphere containing oxygen to form an insulating film. The surface of the edge layer 103c is oxidized to form an insulating layer 103d on the insulating layer 103c. It is possible.

[0233] In comparison with the insulating layer 103a and the insulating layer 103c, the insulating layer 103b may have a lower film density. The difference in film density between the insulating layer 103a, the insulating layer 103b, and the insulating layer 103c may be, for example, For example, it can be evaluated by the density (brightness) of a TEM image. In contrast, the insulating layer 103b may have a higher hydrogen concentration in the film. The difference in hydrogen concentration between the edge layer 103b and the insulating layer 103c can be determined by, for example, secondary ion mass spectrometry ( This can be evaluated using SIMS.

[0234] After forming the insulating layer 103, a process of supplying oxygen to the insulating layer 103 may be performed. This is acceptable. For example, plasma treatment or heat treatment in an oxygen atmosphere can be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method, an ion implantation method, or the like. This is acceptable.

[0235] 〔Formation of semiconductor layer 108〕 Subsequently, a metal oxide film 108f that will become the semiconductor layer 108 is formed on the insulating layer 103 ( FIG. 10C).

[0236] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. This is preferable.

[0237] When forming the metal oxide film 108f, in addition to oxygen gas, an inert gas (for example, helium gas, argon gas, xenon gas, etc.) may be mixed. Note that the higher the ratio of oxygen gas in the entire film-forming gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the metal oxide film can be enhanced, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and a transistor with a higher on-current can be obtained. This is acceptable. This is acceptable.

[0238] When the semiconductor layer 108 has a laminated structure, it is preferable to continuously form films in the same film-forming chamber using the same sputtering target because the interface can be made good. In particular, as the film-forming conditions for each metal oxide film, conditions such as the pressure, temperature, and power during film formation may be different, but it is preferable to set the conditions other than the oxygen flow rate ratio to be the same because the time required for the film-forming process can be shortened. Also, when laminating metal oxide films with different compositions, exposure to the atmosphere is avoided, and the film-forming conditions for each layer are adjusted to ensure good adhesion between the layers. is avoided, and the film-forming conditions for each layer are adjusted to ensure good adhesion between the layers. It is preferably formed continuously without interruption.

[0239] The metal oxide film 108f is a metal oxide film having a CAAC structure, a metal oxide film having an nc structure, or a metal oxide film in which the CAAC structure and the nc structure are mixed, it is preferable to set the film-forming conditions. Note that the film-forming conditions for the metal oxide film to have a CAAC structure and the film-forming conditions for the nc structure vary depending on the composition of the sputtering target used. Therefore, in addition to the substrate temperature and the oxygen flow rate ratio, pressure, power, etc. may be appropriately set according to the composition. The film-forming conditions for the nc structure vary depending on the composition of the sputtering target used. Therefore, in addition to the substrate temperature and the oxygen flow rate ratio, pressure, power, etc. may be appropriately set according to the composition. Since they are different depending on the composition of the sputtering target to be used, in addition to the substrate temperature and the oxygen flow rate ratio, pressure, power, etc. may be appropriately set according to the composition. That's all.

[0240] The film formation of the metal oxide film 108f is carried out at a substrate temperature of room temperature or higher and 450 ° C or lower, preferably room temperature or higher and 300 ° C or lower, more preferably room temperature or higher and 200 ° C or lower, and even more preferably room temperature or higher and 14 0 ° C or lower. For example, when a large glass substrate or a resin substrate is used for the substrate 102, if the film formation temperature is set to be higher than room temperature and lower than 140 ° C, the productivity will be high, which is preferable. In addition, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be lowered. the crystallinity can be lowered. That's all.

[0241] Before forming the metal oxide film 108f, it is preferable to perform a treatment for desorbing water, hydrogen, organic substances, etc. adsorbed on the surface of the insulating layer 103, or a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70 ° C or higher and 200 ° C or lower in a reduced-pressure atmosphere. Or, plasma treatment in an atmosphere containing oxygen may be performed. Also, when plasma treatment containing nitrous oxide gas is performed, the organic substances on the surface of the insulating layer 103 can be preferably removed. This can be achieved. After such processing, without exposing the surface of the insulating layer 103 to the atmosphere, it is preferable to continuously form a metal oxide film.

[0242] Subsequently, the metal oxide film 108f is processed to form an island-shaped semiconductor layer 108 (FIG. 10D ).

[0243] For processing the metal oxide film, either one or both of a wet etching method and a dry etching method may be used. At this time, a part of the insulating layer 103d that does not overlap with the semiconductor layer 108 may be etched and removed. By removing a part of the insulating layer 103d, the upper surface shapes of the semiconductor layer 108 and the insulating layer 103d substantially coincide. Also, by removing a part of the insulating layer 103d, a part of the insulating layer 103c is exposed, and a configuration can be adopted in which the insulating layer 116 formed later is in contact with the insulating layer 103c.

[0244] After forming the metal oxide film or after processing the semiconductor layer 108, a heat treatment may be performed to remove hydrogen or water in the metal oxide film or the semiconductor layer 108. The temperature of the heat treatment is typically 150°C or higher and lower than the distortion point of the substrate, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower. Note that after forming the metal oxide film or after processing the semiconductor layer 108, the heat treatment may not be necessary. Also, the heat treatment may be performed at any stage as long as it is after forming the metal oxide film. Also, it may be combined with a later heat treatment or a process where heat is applied.

[0245] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Or, after heating in such an atmosphere, it may be heated in an atmosphere containing oxygen. An atmosphere containing nitrogen or an atmosphere containing oxygen As the atmosphere, ultra-dry air (CDA: Clean Dry Air) may be used. In addition, it is preferable that the atmosphere of the heat treatment does not contain hydrogen, water, etc. The dew point is -60 ℃ or lower, preferably -100℃ or lower. By using a highly purified gas, the incorporation of hydrogen, water, etc. into the semiconductor layer 10 8 can be prevented as much as possible. The heat treatment can be performed using an electric furnace, a rapid thermal annealing (RTA) apparatus, etc. By using an RTA apparatus, the heat treatment time can be shortened.

[0246] In addition, it is preferable to form the insulating film 110f promptly after the formation of the semiconductor layer 108. When the surface of the semiconductor layer 108 is exposed, water may be adsorbed on the surface of the semiconductor layer 108. When water is adsorbed on the surface of the semiconductor layer 108, hydrogen diffuses into the semiconductor layer 10 8 due to subsequent heat treatment or the like, and V O H may be formed. V O H can be a carrier generation source, so it is preferable that the adsorbed water on the semiconductor layer 108 is less. 〔Formation of Insulating Film 110f〕

[0247] Subsequently, an insulating film 110f is formed to cover the insulating layer 103 and the semiconductor layer 108 (Fig. 1 1A). 1A).

[0248] The insulating film 110f is a film that will later become the insulating layer 110. The insulating film 110f is, for example, an oxide film such as a silicon oxide film or a silicon oxynitride film, and is preferably formed using a plasma chemical vapor deposition apparatus (P ECVD apparatus, or simply referred to as a plasma CVD apparatus). Alternatively, it may be formed using a PECVD method using microwaves. ECVD apparatus, or simply referred to as a plasma CVD apparatus). It is also possible to form it using a PECVD method using microwaves.

[0249] Here, an insulating film 110A serving as the insulating layer 110a, an insulating film 110B serving as the insulating layer 110b, and an insulating film 110C serving as the insulating layer 110c are laminated in this order to be formed. In particular, each insulating film constituting the insulating film 110f is preferably formed by the PECVD method. B, and the insulating film 110C serving as the insulating layer 110c are laminated in this order to be formed. In particular, each insulating film constituting the insulating film 110f is preferably formed by the PECVD method.

[0250] A case where a silicon oxynitride film is used for the insulating film 110A, the insulating film 110B, and the insulating film 110C will be described. For example, the insulating film 110A is formed by the plasma CVD method using a mixed gas of silane and dinitrogen monoxide. Next, a mixed gas with a higher silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film 110A is used, and the insulating film 110B is formed under conditions of high power. Next, a mixed gas with a lower silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film 110B is used, and the insulating film 110C is formed under conditions of low pressure, and the insulating film 110f can be formed. Also, by switching the film formation conditions in the same chamber, the insulating film 110A, the insulating film 110B, and the insulating film 110C can be continuously formed in a vacuum, and the insulating film 110f can be formed with high productivity. A case where a silicon oxynitride film is used for the insulating film 110A, the insulating film 110B, and the insulating film 110C will be described. For example, the insulating film 110A is formed by the plasma CVD method using a mixed gas of silane and dinitrogen monoxide. Next, a mixed gas with a higher silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film 110A is used, and the insulating film 110B is formed under conditions of high power. Next, a mixed gas with a lower silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film 110B is used, and the insulating film 110C is formed under conditions of low pressure, and the insulating film 110f can be formed. Also, by switching the film formation conditions in the same chamber, the insulating film 110A, the insulating film 110B, and the insulating film 110C can be continuously formed in a vacuum, and the insulating film 110f can be formed with high productivity. Here, an insulating film 110A serving as the insulating layer 110a, an insulating film 110B serving as the insulating layer 110b, and an insulating film 110C serving as the insulating layer 110c are laminated in this order to be formed. In particular, each insulating film constituting the insulating film 110f is preferably formed by the PECVD method. Next, a mixed gas with a higher silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film 110A is used, and the insulating film 110B is formed under conditions of high power. Next, a mixed gas with a lower silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film 110B is used, and the insulating film 110C is formed under conditions of low pressure, and the insulating film 110f can be formed. Also, by switching the film formation conditions in the same chamber, the insulating film 110A, the insulating film 110B, and the insulating film 110C can be continuously formed in a vacuum, and the insulating film 110f can be formed with high productivity. Next, a mixed gas with a lower silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film 110B is used, and the insulating film 110C is formed under conditions of low pressure, and the insulating film 110f can be formed. Also, by switching the film formation conditions in the same chamber, the insulating film 110A, the insulating film 110B, and the insulating film 110C can be continuously formed in a vacuum, and the insulating film 110f can be formed with high productivity. After the formation of the insulating film 110f, a heat treatment may be performed. By performing the heat treatment, impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f can be removed. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and rare gases. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Also, it may be combined with a subsequent heat treatment or a process where heat is applied. After the formation of the insulating film 110f, a heat treatment may be performed. By performing the heat treatment, impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f can be removed. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and rare gases. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Also, it may be combined with a subsequent heat treatment or a process where heat is applied. After the formation of the insulating film 110f, a heat treatment may be performed. By performing the heat treatment, impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f can be removed. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and rare gases. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Also, it may be combined with a subsequent heat treatment or a process where heat is applied.

[0251] After the formation of the insulating film 110f, a heat treatment may be performed. By performing the heat treatment, impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f can be removed. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and rare gases. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Also, it may be combined with a subsequent heat treatment or a process where heat is applied. After the formation of the insulating film 110f, a heat treatment may be performed. By performing the heat treatment, impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f can be removed. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and rare gases. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Also, it may be combined with a subsequent heat treatment or a process where heat is applied. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and rare gases. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Also, it may be combined with a subsequent heat treatment or a process where heat is applied. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Also, it may be combined with a subsequent heat treatment or a process where heat is applied. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Also, it may be combined with a subsequent heat treatment or a process where heat is applied.

[0252] Before forming the insulating film 110f, a plasma treatment is performed on the surface of the semiconductor layer 108. By the plasma treatment, impurities such as water adsorbed on the surface of the semiconductor layer 108 are removed. Therefore, the amount of the insulating film 110f at the interface between the semiconductor layer 108 and the insulating film 110f can be reduced. Since the impurities can be reduced, a highly reliable transistor can be realized. The surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the insulating film 110f to the formation of the insulating film 110f. Plasma treatment is preferably performed using, for example, oxygen, ozone, nitrogen, nitrous oxide, arsenic, etc. The plasma treatment and the formation of the insulating film 110f can be performed in an atmosphere of, for example, fluorine. is preferably carried out continuously without exposure to the atmosphere.

[0253] Here, it is preferable to perform a heat treatment after forming the insulating film 110f. As a result, hydrogen or water contained in the insulating film 110f or adsorbed on the surface of the insulating film 110f can be removed. In addition, defects in the insulating film 110f can be reduced.

[0254] The heat treatment conditions may be as described above.

[0255] After the insulating film 110f is formed, or after the heat treatment for removing the hydrogen or water is performed, After that, a process of supplying oxygen to the insulating film 110f may be performed. The plasma treatment or heat treatment can be carried out in an atmosphere containing oxygen. Oxygen may be supplied to the insulating film 110f by ion doping or ion implantation. For example, a PECVD apparatus can be suitably used for the plasma processing. In the case where the insulating film 110f is formed using the D apparatus, after the insulating film 110f is formed, It is preferable to perform plasma treatment continuously. By performing the formation of the insulating film 110f and the plasma treatment continuously in a vacuum, productivity can be improved.

[0256] When performing a heat treatment after performing a treatment of supplying oxygen to the insulating film 110f, it is preferable to perform the heat treatment after forming a film (for example, a metal oxide film 114f) on the insulating film 11 0f. When performing the heat treatment with the insulating film 110f exposed, the oxygen supplied to the insulating film 110f may desorb outside the insulating film 110f. By performing the heat treatment after forming a film (for example, a metal oxide film 114f) on the insulating film 110f, it is possible to suppress the desorption of the oxygen supplied to the insulating film 110f outside the insulating film 110f.

[0257] [Formation of Metal Oxide Film 114f] Subsequently, a metal oxide film 114f is formed covering the insulating film 110f (FIG. 11B).

[0258] The metal oxide film 114f is a film that will later become the metal oxide layer 114. The metal oxide film 11 4f is preferably formed, for example, by a sputtering method in an atmosphere containing oxygen. Thereby, oxygen can be supplied to the insulating film 110f during the film formation of the metal oxide film 114f.

[0259] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing the same metal oxide as in the case of the semiconductor layer 108, the above can be applied.

[0260] The metal oxide film 114f may be formed by a reactive sputtering method using oxygen in the film formation gas and using a metal target. Aluminum is used for the metal target. When used, an aluminum oxide film can be formed.

[0261] During the formation of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the film-forming gas introduced into the film-forming chamber of the film-forming apparatus (oxygen flow rate ratio), or the higher the oxygen partial pressure in the film-forming chamber, the more oxygen can be supplied to the insulating layer 1 10, which is preferable. The oxygen flow rate ratio or the oxygen partial pressure is For example, it is higher than 0% and 100% or less, preferably 10% or more and 100% or less, more preferably 100% or less, and even more preferably 30% or more and 100% or less, and even more preferably 40% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and make the oxygen partial pressure as close to 100% as possible.

[0262] In this way, by forming the metal oxide film 114f by sputtering in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110f during the formation of the metal oxide film 114f while preventing oxygen from desorbing from the insulating film 110f. As a result, a very large amount of oxygen can be confined in the insulating film 110f. Then, by subsequent heat treatment, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108, and the oxygen deficiency in the channel formation region can be reduced, and a highly reliable transistor can be realized.

[0263] The metal oxide film 114f should have a substrate temperature of room temperature or higher and 450 °C or lower, preferably a substrate temperature of room temperature or higher and 300 °C or lower, more preferably room temperature or higher and 200 °C or lower, and even more preferably room temperature or higher 140 °C or lower. For example, when a large glass substrate or a resin substrate is used for the substrate 102, when the film-forming temperature is room temperature or higher and less than 140 °C, the productivity is high, which is preferable. Also , when the film formation temperature of the metal oxide film 114f is high, the crystallinity of the metal oxide film 114f becomes high, and the etching rate may become slow. When the film formation temperature of the metal oxide film 114f is low, the crystallinity of the metal oxide film 114f becomes low, and the etching rate may become fast. In order to obtain a desirable etching rate for the etchant used when processing the metal oxide film 114f, the film formation temperature of the metal oxide film 114f may be appropriately selected.

[0264] After the formation of the metal oxide film 114f, by performing a heat treatment, oxygen may be supplied from the insulating film 110f to the semiconductor layer 108. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and noble gases. Note that after the formation of the metal oxide film 114f, the heat treatment may not be necessary. Also, the heat treatment may be performed at any stage as long as it is after the film formation of the metal oxide film 114f. Further, it may be combined with a subsequent heat treatment or a process where heat is applied.

[0265] 〔Formation of conductive film 112f〕 Subsequently, a part of the metal oxide film 114f, the insulating film 110f, and the insulating layer 103 is etched to form an opening 142 reaching the conductive layer 106. Thereby, the conductive layer 112 to be formed later and the conductive layer 106 can be electrically connected through the opening 142.

[0266] Subsequently, a conductive film 112f serving as the conductive layer 112 is formed on the metal oxide film 114f ( FIG. 11C). The conductive film 112f is preferably formed by a sputtering method using a sputtering target of a metal or an alloy.

[0267] 〔Formation of insulating layer 110, metal oxide layer 114, and conductive layer 112〕 Subsequently, a resist mask 115 is formed on the conductive film 112f (Fig. 12A). Then, In the regions not covered by the resist mask 115, the conductive film 112f and the metal oxide film 114f are removed to form the conductive layer 112 and the metal oxide layer 114 (Fig. 12B).

[0268] For the formation of the conductive layer 112 and the metal oxide layer 114, a wet etching method can be preferably used. As the wet etching method, for example, an etchant containing hydrogen peroxide can be used. For example, an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, or sulfuric acid can be used. In particular, when a material containing copper is used for the conductive layer 112, an etchant containing phosphoric acid, acetic acid, and nitric acid can be preferably used.

[0269] The ends of the conductive layer 112 and the metal oxide layer 114 are processed so as to be located inside the contour of the resist mask 115. For the formation of the conductive layer 112 and the metal oxide layer 114, it is preferable to use the wet etching method. By adjusting the etching time, the width L2 of the region 108L can be controlled.

[0270] For the formation of the conductive layer 112 and the metal oxide layer 114, after etching the conductive film 112f and the metal oxide film 114f using an anisotropic etching method, the sides of the conductive film 112f and the metal oxide film 114f can be etched using an isotropic etching method to retreat the end faces (also referred to as side etching). This allows the formation of the conductive layer 112 and the metal oxide layer 114 located inside the insulating layer 110 in a plan view.

[0271] As shown in Fig. 12B, when forming the conductive layer 112 and the metal oxide layer 114, the conductive layer 1​​​​​ The thickness of the insulating film 110f in the region overlapping with 12 is smaller than that of the insulating film in the region not overlapping with the conductive layer 112 The thickness of the insulating film 110f may become thinner.

[0272] Note that different etching conditions or methods may be used to form the conductive layer 112 and the metal oxide layer 114, and etching may be performed at least twice separately. For example, the conductive film 112f may be etched first, and then the metal oxide film 114f may be etched under different etching conditions. For example, the conductive film 112f may be etched first, and then the metal oxide film 114f may be etched under different etching conditions. For example, the conductive film 112f may be etched first, and then the metal oxide film 114f may be etched under different etching conditions. It is also acceptable.

[0273] Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 12C). To form the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can suppress a reduction in the thickness of the conductive layer 112. Also, when forming the insulating layer 110, the insulating layer 103d in the region not covered by the resist mask 115 may also be removed. Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 12C). To form the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can suppress a reduction in the thickness of the conductive layer 112. Also, when forming the insulating layer 110, the insulating layer 103d in the region not covered by the resist mask 115 may also be removed. Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 12C). To form the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can suppress a reduction in the thickness of the conductive layer 112. Also, when forming the insulating layer 110, the insulating layer 103d in the region not covered by the resist mask 115 may also be removed. Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 12C). To form the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can suppress a reduction in the thickness of the conductive layer 112. Also, when forming the insulating layer 110, the insulating layer 103d in the region not covered by the resist mask 115 may also be removed. Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 12C). To form the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can suppress a reduction in the thickness of the conductive layer 112. Also, when forming the insulating layer 110, the insulating layer 103d in the region not covered by the resist mask 115 may also be removed. Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 12C). To form the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can suppress a reduction in the thickness of the conductive layer 112. Also, when forming the insulating layer 110, the insulating layer 103d in the region not covered by the resist mask 115 may also be removed. Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 12C). To form the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can suppress a reduction in the thickness of the conductive layer 112. Also, when forming the insulating layer 110, the insulating layer 103d in the region not covered by the resist mask 115 may also be removed.

[0274] By adjusting the formation conditions of the insulating layer 110, the width L2 of the region 108L can be controlled. For example, by using conditions under which the resist mask 115 recedes when forming the insulating layer 110, the width of the resist mask 115 is made smaller. By making the width of the resist mask 115 smaller, the distance between the end of the resist mask 115 and the end of the conductive layer 112 becomes closer, and as a result, the width L2 of the region 108L can be made smaller. For example, by using conditions under which the resist mask 115 recedes when forming the insulating layer 110, the width of the resist mask 115 is made smaller. By making the width of the resist mask 115 smaller, the distance between the end of the resist mask 115 and the end of the conductive layer 112 becomes closer, and as a result, the width L2 of the region 108L can be made smaller. For example, by using conditions under which the resist mask 115 recedes when forming the insulating layer 110, the width of the resist mask 115 is made smaller. By making the width of the resist mask 115 smaller, the distance between the end of the resist mask 115 and the end of the conductive layer 112 becomes closer, and as a result, the width L2 of the region 108L can be made smaller. For example, by using conditions under which the resist mask 115 recedes when forming the insulating layer 110, the width of the resist mask 115 is made smaller. By making the width of the resist mask 115 smaller, the distance between the end of the resist mask 115 and the end of the conductive layer 112 becomes closer, and as a result, the width L2 of the region 108L can be made smaller.

[0275] After forming the insulating layer 110, the resist mask 115 is removed.

[0276] Here, cleaning may be performed to remove impurities. By performing cleaning, impurities adhering to the exposed regions of the insulating layer 1 10 and the semiconductor layer 108 can be removed, and a decrease in the electrical characteristics and reliability of the transistor can be suppressed. Examples of the impurities include components of the etching gas or etchant that adhere during the etching of the insulating film 110f, components of the conductive film 112 f, components of the metal oxide film 114f, and the like.

[0277] As the cleaning method, wet cleaning using a cleaning liquid or the like, or plasma treatment can be used. Also, these cleanings may be appropriately combined. For wet cleaning, a cleaning liquid containing acetic acid, phosphoric acid, aqueous ammonia, hydrofluoric acid, or the like can be used.

[0278] 〔Formation of Insulating Layer 116 and Region 108N (Hydrogen Supply Process)〕 Subsequently, a process of supplying hydrogen is performed on the exposed region of the semiconductor layer 108. Here, by forming an insulating layer 116 containing hydrogen in contact with the exposed region of the semiconductor layer 108, hydrogen is supplied (FIG. 13A).

[0279] The insulating layer 116 is preferably formed by plasma CVD using a film-forming gas containing hydrogen. For example, a silicon nitride film is formed using a film-forming gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen can be contained in the film. Also, during film formation, hydrogen can be supplied to the exposed portion of the semiconductor layer 108.

[0280] After the formation of the insulating layer 116, by performing a heat treatment, hydrogen released from the insulating layer 116​​​​​ It is preferable to supply a part of to a part of the semiconductor layer 108. The heat treatment is carried out in an atmosphere containing one or more of nitrogen, oxygen, and rare gas at a temperature of 150 °C or higher and 450 °C or lower, preferably 200 °C or higher and 400 °C or lower.

[0281] By supplying hydrogen in this way, an extremely low-resistance region 108N can be formed in the semiconductor layer 108. It can be formed.

[0282] By the heat treatment, oxygen can be supplied from the insulating layer 110 to the channel formation region of the semiconductor layer 108. It can be done.

[0283] 〔Formation of insulating layer 118〕 Subsequently, an insulating layer 118 is formed on the insulating layer 116 (Fig. 13B).

[0284] When the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, depending on the impurities contained in the region 1 08N or the like, there is a risk that the impurities will diffuse to the peripheral portion including the channel formation region of the semiconductor layer 108. As a result, there is a risk that the resistance of the channel formation region will decrease or the resistance of the region 108N will increase. The film formation temperature of the insulating layer 116 or the insulating layer 118 is, for example, 150 °C or higher and 400 °C or lower, preferably 180 °C or higher and 360 °C or lower, more preferably 200 °C or higher and 250 °C or lower. By forming the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length. By forming the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0285] Heat treatment may be performed after the formation of the insulating layer 118.

[0286] 〔Formation of openings 141a and 141b〕 Subsequently, after forming a mask by lithography at a desired position of the insulating layer 118, the insulating layer 118 and a part of the insulating layer 116 are etched to form openings 1 41a and 141b reaching the region 108N.

[0287] 〔Formation of Conductive Layers 120a and 120b〕 Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b and the conductive film is processed into a desired shape to form the conductive layers 120a and 120b (Fig. 13C).

[0288] Through the above steps, the transistor 100C can be fabricated.

[0289] <Fabrication Method Example 2> Hereinafter, taking as an example the configuration in which the end of the conductive layer 112 in the transistor 100A of the above configuration example is located inside the end of the metal oxide layer 114, an explanation will be given.

[0290] Up to forming the resist mask 115 on the conductive film 112f, it is the same as the aforementioned <Fabrication Method Example 1> (see Fig. 12A).

[0291] 〔Formation of Insulating Layer 110, Metal Oxide Layer 114, and Conductive Layer 112〕 Subsequently, in the region not covered by the resist mask 115, the conductive film 112f and the gold metal oxide film 114f are removed to form the conductive layer 112 and the metal oxide layer 114 (Fig. 14 A).

[0292] For the formation of the conductive layer 112 and the metal oxide layer 114, a wet etching method can be preferably used At this time, the end of the metal oxide layer 114 is from the contour of the resist mask 115 It is also located inside, and the end of the conductive layer 112 is located inside the contour of the metal oxide layer 114 and processed in this way. Also, by adjusting the etching time, the width L2 of the region 108L can be controlled.

[0293] For the formation of the conductive layer 112 and the metal oxide layer 114, an anisotropic etching method is used to etch the conductive film 112f and the metal oxide film 114f, and then an isotropic etching method is used to etch the side surfaces of the conductive film 112f and the metal oxide film 114f to recess the end surfaces if necessary.

[0294] As shown in FIG. 14A, when forming the conductive layer 112 and the metal oxide layer 114, the thickness of the insulating film 110f in the region overlapping the metal oxide layer 114 may be thinner than the thickness of the insulating film 110f in the region not overlapping the metal oxide layer 114.

[0295] When forming the conductive layer 112 and the metal oxide layer 114, the end of the conductive layer 112 retreats from the end of the metal oxide layer 114, and the thickness of the metal oxide layer 114 in the region not overlapping the conductive layer 112 may be thinner than the thickness of the metal oxide layer 114 in the region overlapping the conductive layer 112.

[0296] Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 14B). For the formation of the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but by leaving the resist mask 115, it is possible to suppress a reduction in the thickness of the conductive layer 112.

[0297] ​​ After forming the insulating layer 110, the resist mask 115 is removed.

[0298] Thereafter, for the processes after forming the insulating layer 116, since the description of <Manufacturing Method Example 1> can be referred to , the details are omitted.

[0299] <Components of the Semiconductor Device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0300] 〔Substrate〕 There are no major restrictions on the material of the substrate 102, etc., but it is necessary to have at least heat resistance to withstand subsequent heat treatment . For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 102 . Also, those with semiconductor elements provided on these substrates may be used as the substrate 102 .

[0301] As the substrate 102, a flexible substrate may be used, and transistors 100, etc. may be directly formed on the flexible substrate . Alternatively, a release layer may be provided between the substrate 102 and the transistors 100, etc. . The release layer can be used to separate from the substrate 102 after partially or completely completing the semiconductor device thereon and transfer it to another substrate. At that time, the transistors 100, etc. can also be transferred to substrates with poor heat resistance or flexible substrates.

[0302] 〔Insulating Layer 103〕 The insulating layer 103 can be formed by appropriately using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition (PLD ) method, etc. Also, the insulating layer 103 is, for example, an oxide insulating film or a nitride A chemical oxide insulating film can be formed as a single layer or as a laminate. In addition, in order to improve the interface characteristics with the semiconductor layer 108, at least the region of the insulating layer 103 in contact with the semiconductor layer 108 is preferably formed of a chemical oxide insulating film. Further, it is preferable to use a film that releases oxygen by heating for the insulating layer 103.

[0303] As the insulating layer 103, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide etc. can be used, and they can be provided as a single layer or as a laminate.

[0304] When a film other than a chemical oxide film such as a silicon nitride film is used on the side of the insulating layer 103 in contact with the semiconductor layer 108, it is preferable to perform a pretreatment such as oxygen plasma treatment on the surface in contact with the semiconductor layer 108 and oxidize the surface or the vicinity of the surface.

[0305] 〔Conductive film〕 The conductive layer 106, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements, etc.

[0306] In the conductive layer 106, the conductive layer 120a, and the conductive layer 120b, oxide conductors such as indium-tin oxide, indium- tungsten oxide, indium-tungsten-zinc oxide, indium-titanium oxide, indium-titanium-tin oxide, indium- zinc oxide, indium-tin-silicon oxide, indium-gallium-zinc oxide, etc. or ​​​​​A metal oxide film can also be applied.

[0307] Here, the oxide conductor (OC: Oxide Conductor) will be described. For example, when oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. The metal oxide that has become conductive can be referred to as an oxide conductor.

[0308] As the conductive layer 106 or the like, a laminated structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy may be used. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced. At this time, it is preferable to apply a conductive film containing an oxide conductor on the side in contact with the insulating layer that functions as a gate insulating film.

[0309] Among the above-mentioned metal elements, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b particularly preferably have any one or a plurality selected from titanium, tungsten, tantalum, and molybdenum. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film has conductivity and high barrier properties against copper, oxygen, or hydrogen, and since the release of hydrogen from itself is small, it can be preferably used as a conductive film in contact with the semiconductor layer 108 or a conductive film near the semiconductor layer 108.

[0310] 〔Insulating layer 110〕 The insulating layer 110 that functions as a gate insulating film of the transistor 100 or the like can be formed by a PECVD method, a sputtering method, or the like. The insulating layer 110 is a silicon oxide film, a silicon oxynitride film, A silicon nitride film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film , a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film, and one or more of these can be used as the insulating layer. Note that the insulating layer 110 may have a two-layer laminated structure or a three-layer or more laminated structure. The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is an insulating film capable of releasing oxygen. For example, by forming the insulating layer 110 in an oxygen atmosphere, heat-treating the insulating layer 110 after film formation in an oxygen atmosphere, performing plasma treatment, etc., or forming an oxide film on the insulating layer 110 in an oxygen atmosphere, oxygen can also be supplied into the insulating layer 110.

[0311] As the insulating layer 110, materials such as hafnium oxide having a higher relative dielectric constant than silicon oxide or silicon oxynitride can also be used. This can increase the film thickness of the insulating layer 110 and suppress leakage current due to tunneling current. In particular, crystalline hafnium oxide is preferable because it has a higher relative dielectric constant than amorphous hafnium oxide.

[0312]

[0313] 〔Semiconductor layer〕 When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used for forming the In-M-Zn oxide preferably has an atomic ratio of In to element M of 1 or more. As the atomic ratio of the metal elements of such a sputtering target, In ​​​​​​​​​​​:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1: 3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4: 2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Z n = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, etc. can be mentioned.

[0314] When using a target containing a polycrystalline oxide as the sputtering target, it is preferable because it becomes easy to form a semiconductor layer 108 having crystallinity. Note that the atomic ratio of the semiconductor layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. When the composition of the target is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio].

[0315] When the atomic ratio is described as In:Ga:Zn = 4:2:3 or in its vicinity, when In is 4, it includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Also, when the atomic ratio is described as In:Ga:Zn = 5:1:6 or in its vicinity, when I n is 5, it includes the case where Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Also, when the atomic ratio is described as In:Ga:Zn = 1:1:1 or in its vicinity, when In is 1, it includes the case where Ga is greater than 0.1 and 2 or less, and Zn is 0. It includes the case where it is greater than 1 and 2 or less.

[0316] ​​The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon in this way, the off-current of the transistor can be reduced.

[0317] It is preferable to use a metal oxide with a low carrier concentration for the semiconductor layer 108. When reducing the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be reduced and the density of defect energy levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect energy levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Incidentally, impurities in the metal oxide include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0318] In particular, hydrogen contained in the metal oxide may react with oxygen bonded to metal atoms to form water, thus forming oxygen vacancies in the metal oxide. If the channel formation region in the metal oxide contains oxygen vacancies, the transistor may have normally-on characteristics. Furthermore, defects with hydrogen in oxygen vacancies may function as donors, and electrons as carriers may be generated. In addition, a part of hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics.

[0319] Defects with hydrogen in oxygen vacancies may function as donors of the metal oxide. However, it is difficult to quantitatively evaluate such defects. Therefore, in the metal oxide, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, the metal As a parameter of the oxide, instead of the donor concentration, we use the capacitance assuming a state in which no electric field is applied. In other words, the "carrier concentration" described in this specification is the "dop This can sometimes be rephrased as "ner concentration."

[0320] Therefore, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. In the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than , more preferably 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 The metal oxide with sufficiently reduced impurities such as hydrogen is used as a trasfer catalyst. By using it in the channel formation region of a transistor, stable electrical characteristics can be achieved. .

[0321] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 The following is and preferably 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 It is even better if it is less than 1×10 12 cm -3 It is more preferable that the channel formation region is less than 100 nm. The lower limit of the carrier concentration of the metal oxide in the region is not particularly limited. For example, 0-9 cm -3 can be set to

[0322] The semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure includes, for example, the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described later. Among the non-single crystal structures, the amorphous structure has the highest density of defect levels, and the CAAC structure has the lowest density of defect levels.

[0323] Hereinafter, CAAC (c-axis aligned crystal) will be described. CAAC represents an example of a crystal structure.

[0324] The CAAC structure is one of the crystal structures such as a thin film having a plurality of nanocrystals (crystal regions with a maximum diameter of less than 10 nm). Each nanocrystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nanocrystals are continuously connected without forming grain boundaries with each other. In particular, a thin film having a CAAC structure has the characteristic that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film.

[0325] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, since clear grain boundaries cannot be confirmed in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of the oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, CAAC- ​​​​​​​​​The oxide semiconductor having an OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability.

[0326] Here, in crystallography, it is common to take a unit cell with a specific axis as the c-axis among the three axes of the a-axis, b-axis, and c-axis (crystal axes) that make up the unit cell. In particular, in a crystal having a layered structure, it is common to use two axes parallel to the plane direction of the layer as the a-axis and b-axis, and the axis intersecting the layer as the c-axis. As a typical example of a crystal having such a layered structure, there is graphite classified into the hexagonal system, and the a-axis and b-axis of its unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, the crystal of InGaZnO4 having a YbFe2O4-type crystal structure which is a layered structure can be classified into the hexagonal system, and the a-axis and b-axis of its unit cell are parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (that is, the a-axis and b-axis).

[0327] In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film). The crystal part contained in the microcrystalline oxide semiconductor film is often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) which are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Further, in the observation image by TEM, for example, it may not be possible to clearly confirm the grain boundaries in the nc-OS film.

[0328] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is observed in the whole film. Accordingly, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. The nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier concentration and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the region.

[0329] The nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier concentration and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility. The nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier concentration and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility. The nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier concentration and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility. The nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier concentration and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility. The nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier concentration and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility.

[0330] The nc-OS film can be formed by reducing the oxygen flow rate ratio during film formation as compared with the CAAC-OS film. Also, the nc-OS film can be formed by reducing the substrate temperature during film formation as compared with the CAAC-OS film. For example, the nc-OS film can be formed even when the substrate temperature is relatively low (for example, a temperature of 130 °C or lower) or when the substrate is not heated. Therefore, it is suitable for use with large glass substrates, resin substrates, etc., and can improve productivity.

[0331] An example of the crystal structure of a metal oxide will be described. Hereinafter, a metal oxide formed by a sputtering ring method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) will be described as an example. Using the above target, the substrate temperature is set to 100 °C or higher and 130 °C or lower, and the metal oxide formed by sputtering is likely to have either an nc (nano crystal) structure or a CAAC structure, or a structure in which these are mixed. On the other hand, when the substrate temperature is room temperature (R.T.), the metal oxide formed by sputtering is likely to have an nc crystal structure. Note that the room temperature (R.T.) referred to here includes the temperature when the substrate is not heated.

[0332] <Configuration of Metal Oxide> Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS that can be used in a transistor disclosed in one aspect of the present invention will be described.

[0333] In this specification, etc., when referring to CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite), There is one. Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or the composition of a material.

[0334] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is the function of flowing electrons (or holes) serving as carriers, and the insulating function is the function of not flowing electrons serving as carriers. By causing the conductive function and the insulating function to act complementarily respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be enhanced to the maximum extent.

[0335] CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material respectively. Also, there are cases where the conductive region is observed to be blurred at the periphery and connected in a cloud shape.

[0336] In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less. ​​​​​​​​​​​​​​ may be dispersed throughout the material in sizes of

[0337] CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxide The lattice consists of a wide gap component due to the insulating region and a narrow gap component due to the conductive region. In the case of this configuration, when the carrier flows, the nano-particles are Carriers mainly flow in the low gap component. The component with a wide gap acts complementary to the component with a narrow gap. In conjunction with the component, carriers also flow to the component with a wide gap. -OS or CAC-metal oxide is used for the channel formation region of a transistor. In this case, the transistor has a high current driving capability in the on-state, i.e., a large on-current, and High field effect mobility can be obtained.

[0338] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a composite matrix.

[0339] The above is a description of the components.

[0340] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0341] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. We will explain about this.

[0342] <Configuration example> FIG. 15A shows a top view of a display device 700. The display device 700 is provided with a sealant 712. The semiconductor device has a first substrate 701 and a second substrate 705 bonded together. In the region sealed by the second substrate 705 and the sealant 712, A pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided. The pixel portion 702 is provided with a plurality of display elements.

[0343] An FPC 716 (FPC: FPC) is attached to a portion of the first substrate 701 that does not overlap with the second substrate 705. The FPC terminal portion 708 to which the flexible printed circuit (FPC) is connected is The FPC 716 is provided via the FPC terminal portion 708 and the signal line 710. , the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706. Various signals are supplied to each of them.

[0344] A plurality of gate driver circuit sections 706 may be provided. The path portion 706 and the source driver circuit portion 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is mounted on the first substrate 70. It can be mounted on FPC716 or FPC716.

[0345] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor which is a semiconductor device of one embodiment of the present invention can be used as the transistor.

[0346] The display elements provided in the pixel section 702 include liquid crystal elements, light emitting elements, etc. The liquid crystal element can use a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, etc. Also, the light emitting element includes self-luminous light emitting elements such as LED (Light Emitting Diode), OL ED (Organic LED), QLED (Quantum-dot LED), and semiconductor lasers. Further, MEMS (Micro Electro Mechanical Systems ) elements of the shutter type or the optical interference type, display elements applying the microcapsule method, the electrophoresis method, the electro-wetting method, or also the electron ink (registered trademark) method, etc. can also be used.

[0347] The display device 700A shown in Fig. 15B is an example of a display device that can be used as a flexible display, in which a resin layer 743 having flexibility is applied instead of the first substrate 701.

[0348] In the display device 700A, the pixel section 702 does not have a rectangular shape but has an arc-shaped corner. Also, as shown in the region P1 in Fig. 15B, the pixel section 702 and a part of the resin layer 743 have a cutout portion that is cut out. The pair of gate driver circuit sections 706 are provided on both sides with the pixel section 702 interposed therebetween. Also, the gate driver circuit section 706 is provided along an arc-shaped contour at the corner of the pixel section 702.

[0349] The resin layer 743 has a shape in which the portion where the FPC terminal section 708 is provided protrudes. Also, a part of the resin layer 743 including the FPC terminal section 708 is folded to the back side in the region P2 in Fig. 15B. ​​It can be repeated. By folding back a part of the resin layer 743, the FPC 716 can be mounted on the electronic device in a state of being overlapped on the back side of the pixel portion 70 2, and the space saving of the electronic device can be achieved.

[0350] An IC 717 is mounted on the FPC 716 connected to the display device 700A. The IC 717 has, for example, a function as a source driver circuit. At this time, the source driver circuit portion 704 in the display device 700 A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, etc.

[0351] The display device 700B shown in FIG. 15C is a display device that can be suitably used for an electronic device having a large screen. The display device 700B is, for example, a television device, a monitor device, a personal computer (including laptop or desktop), a tablet terminal, a de signed for use in digital signage and the like.

[0352] The display device 700B has a plurality of source driver ICs 721 and a pair of gate driver circuit

[0353] units 722. The plurality of source driver ICs 721 are each attached to an FPC 723. Also the plurality of FPCs 723 have one terminal connected to the first substrate 701 and the other terminal connected to the printed substrate 724, respectively. By bending the FPC 723, the printed substrate 7 24 can be arranged on the back side of the pixel portion 702 and mounted on the electronic device, and the space saving of the electronic device can be achieved.

[0354] ​​​On one hand, the gate driver circuit unit 722 is formed on the first substrate 701. Thus, a narrow bezel electronic device can be realized.

[0355] With such a configuration, a large-sized and high-resolution display device can be realized. For example, a display device with a panel size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonal can be realized. Also, a display device with an extremely high resolution such as 4K2K or 8K4K can be realized.

[0356] <Cross-sectional configuration example> Hereinafter, a configuration using a liquid crystal element as a display element and a configuration using an EL element will be described with reference to FIGS. 16 to 19. FIGS. 16 to 18 are cross-sectional views taken along the dashed-dotted line Q-R shown in FIG. 15A, respectively. Also, FIG. 19 is a cross-sectional view taken along the dashed-dotted line S-T in the display device 7 00A shown in FIG. 15B. FIGS. 16 and 17 show a configuration using a liquid crystal element as a display element, and FIGS. 18 and 19 show a configuration using an EL element. <Explanation regarding the common part of the display device> The display devices shown in FIGS. 16 to 19 include a routing wiring part 711, a pixel part 702, a source driver circuit part 704, and an FPC terminal part 708. The routing wiring part 711

[0357] has signal lines 710. The pixel part 702 has transistors 750 and capacitor elements 790. The source driver circuit part 704 has a transistor 752. FIG. 17 shows a case where there is no capacitor element 790. The transistors 750 and 752 can be the transistors exemplified in Embodiment 1.

[0358] ​​​

[0359] The transistor used in this embodiment is an oxide semiconductor film with high purity and suppression of the formation of oxygen vacancies. It has a semiconductor film. This transistor can reduce the off-current. Therefore, the holding time of an electrical signal such as an image signal can be extended, and the writing interval of an image signal or the like can also be set longer. Thus, the frequency of the refresh operation can be reduced, resulting in an effect of reducing power consumption.

[0360] The transistor used in this embodiment can obtain a relatively high field-effect mobility, enabling high-speed driving. For example, by using such a transistor capable of high-speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driving circuit portion can be formed on the same substrate. That is, a configuration that does not apply a driving circuit formed of a silicon wafer or the like is also possible, and the number of components of the display device can be reduced. Also, in the pixel portion, by using a transistor capable of high-speed driving, a high-quality image can be provided.

[0361] The capacitor element 790 shown in FIGS. 16, 18, and 19 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has a reduced resistance similar to the source region and the drain region of the transistor 750. Also, between the lower electrode and the upper electrode, a part of the insulating film that functions as the first gate insulating layer of the transistor 750 is provided. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. Further, a wiring obtained by processing the same film as the source electrode and the drain electrode of the transistor is connected to the upper electrode. ​​​​​​​​​​​​​​

[0362] On the transistor 750, the transistor 752, and the capacitive element 790, a planarized insulating film 7 70 is provided.

[0363] The transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 may use transistors with different structures. For example, a top-gate type transistor may be applied to one of them, and a bottom-gate type transistor may be applied to the other. Note that the gate driver circuit portion 706 is the same as the source driver circuit portion 704. For example, a configuration in which a top-gate type transistor is applied to one side and a bottom-gate type transistor is applied to the other side may be used. Note that the gate driver circuit portion 706 is the same as the source driver circuit portion 704. For the above gate driver circuit portion 706, it is the same as the source driver circuit portion 704. For the above gate driver circuit portion 706, it is the same as the source driver circuit portion 704.

[0364] The signal line 710 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752. At this time, using a low-resistance material such as a material containing copper element is preferable because signal delay due to wiring resistance is small and display on a large screen becomes possible. When a low-resistance material such as a material containing copper element is used, signal delay due to wiring resistance is small and display on a large screen becomes possible, which is preferable. When a low-resistance material such as a material containing copper element is used, signal delay due to wiring resistance is small and display on a large screen becomes possible, which is preferable.

[0365] The FPC terminal portion 708 has a wiring 760 that partially functions as a connection electrode, an anisotropic conductive film 78 0, and an FPC 716. The wiring 760 is electrically connected to the terminal included in the FPC 71 6 via the anisotropic conductive film 780. Here, the wiring 760 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752. The wiring 760 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752.

[0366] The first substrate 701 and the second substrate 705 may use a flexible substrate such as a glass substrate or a plastic substrate. When a flexible substrate is used for the first substrate 701, it is preferable to provide an insulating layer having a barrier property against water and hydrogen between the first substrate 701 and the transistor 750 or the like. When a flexible substrate is used for the first substrate 701, it is preferable to provide an insulating layer having a barrier property against water and hydrogen between the first substrate 701 and the transistor 750 or the like. When a flexible substrate is used for the first substrate 701, it is preferable to provide an insulating layer having a barrier property against water and hydrogen between the first substrate 701 and the transistor 750 or the like. When a flexible substrate is used for the first substrate 701, it is preferable to provide an insulating layer having a barrier property against water and hydrogen between the first substrate 701 and the transistor 750 or the like.

[0367] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 7 34 in contact with these are provided.

[0368] 〔Configuration Example of Display Device Using Liquid Crystal Element〕 The display device 700 shown in FIG. 16 has a liquid crystal element 775 and a spacer 778. The liquid crystal element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. Also, the conductive layer 772 is electrically connected to the source electrode or drain electrode of the transistor 750. The conductive layer 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0369] For the conductive layer 772, a material that is transparent or reflective to visible light can be used. As the transparent material, for example, an oxide material containing indium, zinc, tin, etc. can be used. As the reflective material, for example, a material containing aluminum, silver, etc. can be used.

[0370] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a transparent material is used for the conductive layer 772, it becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal

[0371] display device, a pair of polarizing plates is provided so as to sandwich the liquid crystal element. The display device 700 shown in FIG. 17 shows an example using a liquid crystal element 77 5 of the horizontal electric field mode (for example, FFS mode). On the conductive layer 772, via an insulating layerA conductive layer 774 is provided. The electric field generated between the conductive layer 772 and the conductive layer 774 can control the alignment state of the liquid crystal layer 776.

[0372] In FIG. 17, a capacitance can be formed by the laminated structure of the conductive layer 774, the insulating layer 773, and the conductive layer 772. Therefore, it is not necessary to separately provide a capacitive element, and the aperture ratio can be increased.

[0373] Although not shown in FIGS. 16 and 17, a configuration in which an alignment film in contact with the liquid crystal layer 776 may be provided. Also, optical members (optical substrates) such as polarizing members, retardation members, and antireflection members, and light sources such as backlights and side lights can be appropriately provided.

[0374] For the liquid crystal layer 776, thermotropic liquid crystals, low-molecular liquid crystals, high-molecular liquid crystals, polymer-dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystals (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. Also, when adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used. The modes of the liquid crystal element include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode.

[0375] ce) mode, ECB (Electrically Controlled Biref ringence) mode, guest-host mode, etc. can be used.

[0376] For the liquid crystal layer 776, a polymer-dispersed liquid crystal, a polymer network liquid crystal, etc. can be used, and a scattering type liquid crystal can also be used. At this time, a configuration for performing black-and-white display without providing the color filter 736 may be adopted, or a configuration for performing color display using the color filter 736 may be adopted.

[0377] As a driving method of the liquid crystal element, a time-division display method (also referred to as a field sequential driving method) for performing color display based on the sequential addition color mixing method may be applied. In that case, a configuration without providing the color filter 736 can be adopted. When the time-division display method is used, for example, it is not necessary to provide sub-pixels that exhibit each color of R (red), G (green), and B (blue), so there are advantages such as improving the aperture ratio of the pixel and enhancing the fineness.

[0378] [Display device using a light-emitting element] The display device 700 shown in FIG. 18 has a light-emitting element 782. The light-emitting element 782 has a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 has an organic compound or an inorganic compound such as quantum dots.

[0379] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. Examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc.

[0380] In the display device 700 shown in FIG. 18, an insulating film 730 is provided to cover a part of the conductive layer 772 on the planarization insulating film 770. Here, the light-emitting element 782 has a translucent conductive film 788 and is a top emission type light-emitting element. Note that the light-emitting element 782 may have a bottom emission structure that emits light toward the conductive layer 772 side, or a dual emission structure that emits light toward both the conductive layer 772 side and the conductive film 788 side.

[0381] The color filter 736 is provided at a position overlapping the light-emitting element 782, and the light-shielding film 738 is provided at positions overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Also, the color filter 736 and the light-shielding film 738 are covered with the insulating film 734. Further, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel column, that is, when formed by painting, the color filter 736 may not be provided.

[0382] FIG. 19 shows a configuration of a display device that can be suitably applied to a flexible display. FIG. 19 is a cross-sectional view taken along the chain double-dashed line S-T in the display device 700A shown in FIG. 15B.

[0383] The display device 700A shown in FIG. 19 has a structure in which a support substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated instead of the first substrate 701 shown in FIG. 18. Transistors 750, capacitor elements 790, etc. are provided on the insulating layer 744 provided on the resin layer 743.

[0384] The support substrate 745 contains an organic resin, glass, or the like, and is a thin substrate having flexibility. 。The resin layer 743 is a layer containing an organic resin such as a polyimide resin or an acrylic resin. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 7 43 is preferably thinner than the support substrate 745.

[0385] The display device 700 shown in FIG. 19 has a protective layer 740 instead of the substrate 705 shown in FIG. 18. The protective layer 740 is bonded to the sealing film 732. As the protective layer 740, a glass substrate or a resin film can be used. Further, as the protective layer 740, an optical member such as a polarizing plate or a diffuser plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be applied.

[0386] The EL layer 786 of the light-emitting element 782 is provided in an island shape on the insulating film 730 and the conductive layer 772. By making the EL layer 786 have different emission colors for each sub-pixel, color display can be realized without using the color filter 736. Further, a protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably formed of an inorganic insulating film. More preferably, it has a laminated structure including one or more

[0387] In FIG. 19, a foldable region P2 is shown. In the region P2, in addition to the support substrate 745 and the adhesive layer 742, there is a portion where an inorganic insulating film such as the insulating layer 744 is not provided. Further, in the region P2, a resin layer 746 is provided to cover the wiring 760. The foldable The inorganic insulating film is not provided in the capable region P2 as much as possible, and a conductive layer containing a metal or an alloy, and only a layer containing an organic material are laminated, so that cracks can be prevented from occurring when bent. Further, by not providing the support substrate 745 in the region P2, a part of the display device 700A can be bent with an extremely small bending radius.

[0388] 〔Configuration example of providing an input device in a display device〕 An input device may be provided in the display device shown in FIGS. 16 to 19. As the input device, for example, a touch sensor or the like can be mentioned.

[0389] For example, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure sensitive method can be used for the sensor method. Or, two or more of these can be combined and used.

[0390] Note that the configuration of the touch panel includes a so-called in-cell type touch panel in which the input device is formed between a pair of substrates, a so-called on-cell type touch panel in which the input device is formed on the display device, or a so-called out-cell type touch panel that is used by being bonded to the display device.

[0391] The configuration examples illustrated in this embodiment, and the drawings and the like corresponding thereto can be implemented by appropriately combining at least a part thereof with other configuration examples, or drawings and the like.

[0392] This embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0393] (Embodiment 3) In this embodiment, regarding a display device having a semiconductor device according to an aspect of the present invention, FIG. 20 is This will be described using it.

[0394] The display device shown in Fig. 20A includes a pixel section 502, a drive circuit section 504, a protection circuit 506 , and a terminal section 507. Note that the protection circuit 506 may not be provided.

[0395] The transistors included in the pixel section 502 and the drive circuit section 504 can be applied with the transistor of one aspect of the present invention. Further, the transistor of one aspect of the present invention may also be applied to the protection circuit 506.

[0396] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently natural numbers of 2 or more).

[0397] The drive circuit section 504 includes a gate driver 504a that outputs a scan signal to scan lines GL_1 to GL_X, a source driver 50 4b that supplies a data signal to data lines DL_1 to DL_Y, and other drive circuits. The gate driver 504a may be configured to have at least a shift register. Further, the source driver 504b may be configured using, for example, a plurality of analog switches. Alternatively, the source driver 504b may be configured using a shift register or the like.

[0398] The terminal section 507 refers to a portion where terminals for inputting power, a control signal, an image signal, etc. from an external circuit to the display device are provided.

[0399] The protection circuit 506 is a circuit that makes a wiring and another wiring in a conductive state when a potential outside a certain range is applied to the wiring to which it is connected. The protection circuit 506 shown in Fig. 20A is, for example, ​​​​​​Then, it is connected to various wirings such as the scanning lines GL_1 to GL _X, which is the wiring between the gate driver 504a and the pixel circuit 501, or the data lines DL_ 1 to DL_Y, etc.

[0400] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel section 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (for example, a driving circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0401] The plurality of pixel circuits 501 shown in FIG. 20A can have, for example, the configurations shown in FIGS. 20B and 20C.

[0402] The pixel circuit 501 shown in FIG. 20B includes a liquid crystal element 570, a transistor 550, and a capacitor element 560. Further, a data line DL_n, a scanning line GL_m, a potential supply line VL, etc. are connected to the pixel circuit 501.

[0403] One potential of a pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The liquid crystal element 570 has its alignment state set by the data to be written. Note that a common potential (common potential) may be applied to one of a pair of electrodes of the liquid crystal elements 570 included in each of the plurality of pixel circuits 501. Also, different potentials may be applied to one of a pair of electrodes of the liquid crystal elements 570 of the pixel circuits 501 in each row.

[0404] The pixel circuit 501 shown in FIG. 20C includes a transistor 552, a transistor 554, and a capacitor It includes an element 562 and a light-emitting element 572. Further, data lines DL_ n, scanning lines GL_m, potential supply lines VL_a, potential supply lines VL_b, etc. are connected to the pixel circuit 501.

[0405] Note that a high power supply potential VDD is applied to one of the potential supply lines VL_a and the potential supply lines VL_b, and a low power supply potential VSS is applied to the other. According to the potential applied to the gate of the transistor 554, the current flowing through the light-emitting element 572 is controlled, and thus the emission luminance from the light-emitting element 5 72 is controlled.

[0406] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc. can be implemented by appropriately combining at least a part thereof with other configuration examples, or drawings, etc.

[0407] This embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0408] (Embodiment 4) Hereinafter, a pixel circuit including a memory for correcting the gradation displayed on a pixel, and a display device having the same will be described. The transistor illustrated in Embodiment 1 can be applied to the transistor used in the pixel circuit illustrated below.

[0409] <Circuit Configuration> FIG. 21A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. Further, wiring S1, wiring S2, wiring G1, and wiring G2 are connected to the pixel circuit 400.

[0410] The gate of the transistor M1 is connected to the wiring G1, and one of the source and the drain is connected to the wiring S1,​ The other of the source and the drain is connected to one electrode of the capacitor C1, respectively. Transistor For M2, one of the gate is connected to the wiring G2, one of the source and the drain is connected to the wiring S2, and the other of the source and the drain is connected to the other electrode of the capacitor C1 and the circuit 401, respectively.

[0411] The circuit 401 is a circuit including at least one display element. The display element can be various elements, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems ) element or the like can be applied.

[0412] Let the node connecting the transistor M1 and the capacitor C1 be the node N1, and the node connecting the transistor M2 and the circuit 401 be the node N2.

[0413] The pixel circuit 400 can hold the potential of the node N1 by turning off the transistor M1. Also, the potential of the node N2 can be held by turning off the transistor M2. Further, with the transistor M2 turned off, by writing a predetermined potential to the node N1 through the transistor M1, the potential of the node N2 can be changed according to the displacement of the potential of the node N1 due to capacitive coupling through the capacitor C1. Here, for one or both of the transistor M1 and the transistor M2, the transistor to which the oxide semiconductor exemplified in the first

[0414] embodiment is applied can be applied. Therefore, the potentials of the node N1 and the node N2 can be held for a long period with an extremely low off-current. Note that when the period for holding the potential of each node is short (specifically, when the frame frequency is 30 Hz or more ), In cases such as the above, a transistor using a semiconductor such as silicon may be applied.

[0415] <Example of driving method> Subsequently, an example of the operation method of the pixel circuit 400 will be described with reference to FIG. 21B. FIG. 21B is , a timing chart related to the operation of the pixel circuit 400. Here, for ease of explanation , various resistances such as wiring resistance, parasitic capacitances of transistors and wirings, and the influence of the threshold voltage of transistors are not considered.

[0416] In the operation shown in FIG. 21B, one frame period is divided into a period T1 and a period T2. Period T1 is a period for writing a potential to node N2, and period T2 is a period for writing a potential to node N1 .

[0417] 〔Period T1〕 In period T1, a potential for turning on the transistors is applied to both of the wirings G1 and G2. Further, a potential V ref which is a fixed potential is supplied to the wiring S1, and a first data potential V w is supplied to the wiring S2.

[0418] To node N1, a potential V ref is applied from the wiring S1 via the transistor M1. Also, to node N2, a first data potential V w is applied from the wiring S2 via the transistor M2. Thus, a potential difference V -V w -V ref is held in the capacitor C1.

[0419] 〔Period T2〕 Subsequently, in period T2, a potential for turning on the transistor M1 is applied to the wiring G1, and the wiring A potential for turning off the transistor M2 is applied to the line G2. Also, a second data potential V data is supplied to the wiring S1. A predetermined fixed potential may be applied to the wiring S2, or it may be in a floating state.

[0420] At the node N1, the second data potential V data is supplied from the wiring S1 via the transistor M1. At this time, due to capacitive coupling by the capacitor C1, the potential of the node N2 changes by the potential dV in response to data the second data potential V . That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401. Note that in FIG. 21B, the potential dV is shown as a positive value, but it may be a negative value. That is, the second data potential V data may be lower than the potential V ref .

[0421] Here, the potential dV is generally determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes a potential close to the second data potential V data .

[0422] In this way, the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including the display element by combining two types of data signals, so that gradation correction can be performed within the pixel circuit 400. This becomes possible.

[0423] The pixel circuit 400 can also generate a potential exceeding the maximum potential that can be supplied to the wiring S1 and the wiring S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Also, when a liquid crystal element is used, overdrive driving can be performed. It is possible to realize movement and the like.

[0424] <Application Example> [Example using a liquid crystal element] The pixel circuit 400LC shown in Fig. 21C has a circuit 401LC. The circuit 401LC has a liquid crystal element LC and a capacitor C2.

[0425] One electrode of the liquid crystal element LC is connected to the other electrode of the capacitor C1, the other electrode of the source and drain of the transistor M2, and one electrode of the capacitor C2, and the other electrode is connected to a wiring to which a potential V is applied. co m2 The capacitor C2 is connected to a wiring to which a potential V com1 is applied. is applied and is connected to a wiring.

[0426] The capacitor C2 functions as a holding capacitor. If the capacitor C2 is not necessary, it can be omitted.

[0427] Since the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example, it is possible to realize high-speed display by overdrive driving, and to apply a liquid crystal material with a high driving voltage. Moreover, by supplying a correction signal to the wiring S1 or the wiring S2, it is also possible to correct the gradation according to the use temperature, the deterioration state of the liquid crystal element LC, and the like.

[0428] [Example using a light-emitting element] The pixel circuit 400EL shown in Fig. 21D has a circuit 401EL. The circuit 401EL has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0429] One electrode of the capacitor C2 is connected to the gate of the transistor M3, one of the source and drain is connected to a wiring to which a potential VH is applied, and the other is connected to one electrode of the light-emitting element EL. ​​​。The capacitance C2 has the other electrode at potential V com connected to a wiring to which is applied. The light-emitting element EL is connected to a wiring to which the other electrode at potential V L is applied.

[0430] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitance C2 functions as a holding capacitance. The capacitance C2 can be omitted if not necessary.

[0431] Here, a configuration is shown in which the anode side of the light-emitting element EL is connected to the transistor M3 but the transistor M3 may be connected to the cathode side. In that case, the potential V H and the potential V L can be appropriately changed.

[0432] The pixel circuit 400EL can supply a large current to the light-emitting element EL by applying a high potential to the gate of the transistor M3, so that, for example, HDR display or the like can be realized. Also by supplying a correction signal to the wiring S1 or the wiring S2, it is also possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL. Note that the present invention is not limited to the circuits illustrated in FIGS. 21C and 21D, and a configuration in which transistors, capacitances, etc. are separately added may be used.

[0433] This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

[0434]

[0435] can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

[0435] (Embodiment 5) In this embodiment, a display module that can be manufactured using one aspect of the present invention will be described.

[0436] ​The display module 6000 shown in Fig. 22A includes an upper cover 6001 and a lower cover 6002 Therebetween, there are a display device 6006 to which an FPC 6005 is connected, a frame 6009, a printed circuit board 6010, and a battery 6011.

[0437] For example, a display device manufactured using an aspect of the present invention can be used for the display device 6006 In this way, a display module with extremely low power consumption can be realized by the display device 6006

[0438] The upper cover 6001 and the lower cover 6002 can be appropriately changed in shape and dimensions according to the size of the display device 6006

[0439] The display device 6006 may have a function as a touch panel.

[0440] The frame 6009 may have functions such as a protection function for the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, and a function as a heat sink.

[0441] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, etc.

[0442] Fig. 22B is a schematic cross-sectional view of a display module 6000 including an optical touch sensor

[0443] The display module 6000 has a light emitting portion 6015 and a light receiving portion 6016 provided on the printed circuit board 6010. Also, there are a pair of light guide portions (light guide portion 6017a, light guide portion 6017b) in the region surrounded by the upper cover 6001 and the lower cover 6002

[0444] ​​​​​​​The display device 6006 is provided overlapping a printed circuit board 6010 and a battery -6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guide part 6 017a and a light guide part 6017b.

[0445] The light 6018 emitted from the light emitting part 6015 passes through the upper part of the display device 600 6 via the light guide part 6017a, and reaches the light receiving part 6016 through the light guide part 6017b. For example, when the light 6018 is blocked by a detected object such as a finger or a stylus , a touch operation can be detected.

[0446] A plurality of light emitting parts 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving parts 6016 are provided at positions facing the light emitting parts 6015. Thereby, information on the position where a touch operation is performed can be obtained.

[0447] As the light emitting part 6015, a light source such as an LED element can be used, and in particular, it is preferable to use a light source that emits infrared rays. As the light receiving part 6016, a photoelectric element that receives the light emitted from the light emitting part 6015 and converts it into an electric signal can be used. Preferably, a photodiode that can receive infrared rays can be used.

[0448] The light guide part 6017a and the light guide part 6017b that transmit the light 6018 allow the light emitting part 6015 and the light receiving part 6016 to be arranged below the display device 6006, and it is possible to suppress external light from reaching the light receiving part 601 6 and causing the touch sensor to malfunction. In particular, when a resin that absorbs visible light and transmits infrared rays is used, malfunction of the touch sensor can be more effectively suppressed.

[0449] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification. It can be implemented in combination.

[0450] (Embodiment 6) In this embodiment, an example of an electronic device to which a display device according to one aspect of the present invention can be applied will be described. It will be described.

[0451] The electronic device 6500 shown in FIG. 23A is a portable information terminal that can be used as a smartphone. It is a terminal.

[0452] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, buttons 6 504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display unit 6502 has a touch panel function.

[0453] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0454] FIG. 23B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0455] A protective member 6510 having translucency is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, and the like are arranged in the space surrounded by the housing 650 1 and the protective member 6510. They are arranged.

[0456] On the protective member 6510, the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed by an adhesive layer (not shown).

[0457] In a region outside the display unit 6502, a part of the display panel 6511 is folded back. It exists. Further, an FPC6515 is connected to the folded portion. FPC651 5 has an IC6516 mounted thereon. Further, FPC6515 is connected to a terminal provided on a printed circuit board 6517 .

[0458] The display panel 6511 can apply the flexible display panel of one aspect of the present invention . Therefore, an extremely lightweight electronic device can be realized. Further, since the display panel 6511 is extremely thin, it is possible to mount a large-capacity battery 6518 while suppressing the thickness of the electronic device . Further, by folding back a part of the display panel 6511 and arranging the connection portion with FPC6515 on the back side of the pixel portion, an electronic device with a narrow bezel can be realized .

[0459] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification .

[0460] (Embodiment 7) In this embodiment, an electronic device including a display device manufactured using one aspect of the present invention will be described .

[0461] The electronic device exemplified below includes a display device of one aspect of the present invention in a display portion . Therefore, it is an electronic device that realizes a high resolution. Further, it can be an electronic device that achieves both a high resolution and a large screen .

[0462] In the display portion of the electronic device of one aspect of the present invention, for example, video having a resolution of full high vision, 4K2K, 8K4 K, 16K8K, or higher can be displayed

[0463] The electronic device is, for example, a television device, a notebook personal computer, a monitor Electronic devices equipped with relatively large screens such as devices, digital signage, pachinko machines, and game machines In addition to digital cameras, digital video cameras, digital photo frames, mobile phones Devices, portable game machines, portable information terminals, audio playback devices, and the like can be mentioned.

[0464] The electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of the inner wall or outer wall of a house or building, or the interior or exterior of an automobile or the like. It can be incorporated along a flat or curved surface of the interior or exterior of an automobile or the like.

[0465] FIG. 24A is a view showing the appearance of the camera 8000 with the viewfinder 8100 attached. It is.

[0466] The camera 8000 has a housing 8001, a display unit 8002, operation buttons 8003, a shutter Button 8004 and the like. The camera 8000 also has a detachable lens 8006 attached It is.

[0467] Note that the lens 8006 and the housing of the camera 8000 may be integrated.

[0468] The camera 8000 can be imaged by pressing the shutter button 8004 or touching the display unit 8002 that functions as a touch panel. It can be imaged by pressing the shutter button 8004 or touching the display unit 8002 that functions as a touch panel.

[0469] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, a strobe Device and the like can be connected.

[0470] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc. It has.

[0471] The housing 8101 is engaged with the mount of the camera 8000 by a mount, and the camera 800 It is attached to 0. The viewfinder 8100 can display the video and the like received from the camera 8000 on the display unit 8102.

[0472] The button 8103 has a function as a power button or the like.

[0473] The display device according to an aspect of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0474] FIG. 24B is a diagram showing the appearance of the head-mounted display 8200.

[0475] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display unit 8204, a cable 8205, etc. The mounting portion 8201 has a battery 8206 built therein.

[0476] The cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like and can display the received video information on the display unit 8204. Further, the main body 8203 includes a camera and can be used as an input means for information on the movement of the user's eyeballs and eyelids.

[0477] The mounting portion 8201 may be provided with a plurality of electrodes capable of detecting the current flowing along with the movement of the user's eyeballs at a position where it touches the user, and may have a function of recognizing the line of sight. Further, it may have a function of monitoring the user's pulse by the current flowing through the electrodes. Further, the mounting portion 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. It may also have a function of displaying the user's biological information on the display unit 8204, or a function of changing the video displayed on the display unit 8204 in accordance with the movement of the user's head. It may have a function of changing the video displayed on the display unit 8204 in accordance with the movement of the user's head.

[0478] The display device according to an aspect of the present invention can be applied to the display unit 8204.

[0479] FIGS. 24C, 24D, and 24E are diagrams showing the appearance of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0480] The user can visually recognize the display on the display unit 8302 through the lenses 8305. When the display unit 8302 is curved and arranged, the user can feel a high sense of presence, which is preferable. In addition, by visually recognizing different images displayed in different regions of the display unit 8302 through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the display unit 8302 is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided and one display unit may be arranged for each eye of the user. In addition, by visually recognizing different images displayed in different regions of the display unit 8302 through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the display unit 8302 is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided and one display unit may be arranged for each eye of the user. In addition, by visually recognizing different images displayed in different regions of the display unit 8302 through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the display unit 8302 is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided and one display unit may be arranged for each eye of the user. In addition, by visually recognizing different images displayed in different regions of the display unit 8302 through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the display unit 8302 is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided and one display unit may be arranged for each eye of the user. In addition, by visually recognizing different images displayed in different regions of the display unit 8302 through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the display unit 8302 is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided and one display unit may be arranged for each eye of the user.

[0481] Note that the display device according to an aspect of the present invention can be applied to the display unit 8302. Since the display device having the semiconductor device according to an aspect of the present invention has extremely high definition, even when enlarged using the lenses 8305 as shown in FIG. 24E, a more realistic image can be displayed without the user visually recognizing the pixels. Note that the display device according to an aspect of the present invention can be applied to the display unit 8302. Since the display device having the semiconductor device according to an aspect of the present invention has extremely high definition, even when enlarged using the lenses 8305 as shown in FIG. 24E, a more realistic image can be displayed without the user visually recognizing the pixels. Note that the display device according to an aspect of the present invention can be applied to the display unit 8302. Since the display device having the semiconductor device according to an aspect of the present invention has extremely high definition, even when enlarged using the lenses 8305 as shown in FIG. 24E, a more realistic image can be displayed without the user visually recognizing the pixels. Note that the display device according to an aspect of the present invention can be applied to the display unit 8302. Since the display device having the semiconductor device according to an aspect of the present invention has extremely high definition, even when enlarged using the lenses 8305 as shown in FIG. 24E, a more realistic image can be displayed without the user visually recognizing the pixels.

[0482] The electronic device shown in FIGS. 25A to 25G includes a housing 9000, a display unit 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), and a connection terminal 900. The electronic device shown in FIGS. 25A to 25G includes a housing 9000, a display unit 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), and a connection terminal 900. 6. Sensor 9007 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity , inclination, vibration, odor, or infrared rays), microphone 900 8, etc.

[0483] The electronic devices shown in FIGS. 25A to 25G have various functions. For example, functions for displaying various information ( still images, moving images, text images, etc.) on the display unit, touch panel function, calendar , function for displaying date or time, etc., function for controlling processing by various software (programs), wireless communication function, function for reading and processing programs or data recorded on a recording medium, etc. Note that the functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have a plurality of display units. Also, a camera or the like may be provided in the electronic device to capture still images and moving images and save them in a recording medium (external or built into the camera), function for displaying the captured images on the display unit, etc.

[0484] Details of the electronic devices shown in FIGS. 25A to 25G will be described below.

[0485] FIG. 25A is a perspective view showing a television device 9100. The television device 910 0 can incorporate a large display unit 9001, for example, 50 inches or more, or 100 inches or more.

[0486] FIG. 25B is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as, for example, a smartphone. Note that the portable information terminal 9101 has a speaker You may provide a camera 9003, connection terminals 9006, a sensor 9007, etc. Also, the portable information terminal 9101 can display character and image information on its multiple surfaces. In FIG. 25B, an example of displaying three icons 9050 is shown. Also, the information 9051 indicated by the dashed rectangle can be displayed on other surfaces of the display unit 90 01. As an example of the information 9051, there are notifications of incoming calls such as e-mails, SNS , titles of e-mails and SNS, sender names, dates, times, remaining battery levels, antenna reception strengths, etc. Or, icons 9050, etc. may be displayed at the position where the information 9051 is displayed .

[0487] FIG. 25C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example where the information 9052, the information 9053, and the information 9054 are respectively displayed on different surfaces is shown. For example, the user can also confirm the information 9053 displayed at a position that can be observed from above while the portable information terminal 9102 is stored in the breast pocket of a piece of clothing. The user can check the display without taking the portable information terminal 9102 out of the pocket and, for example, determine whether to answer a call .

[0488] FIG. 25D is a perspective view showing the wristwatch-type portable information terminal 9200. The portable information terminal 92 00 can be used, for example, as a smartwatch (registered trademark). Also, the display unit 9001 is provided with a curved display surface, and display can be performed along the curved display surface . Also, the portable information terminal 9200 can communicate with, for example, a wirelessly communicable headset ​​By doing so, it is also possible to make a hands-free call. Further, the portable information terminal 9200 can perform data transmission and charging mutually with other information terminals through the connection terminal 9006. Note that the charging operation may be performed by wireless power supply.

[0489] Figs. 25E, 25F and 25G are perspective views showing the foldable portable information terminal 9201. Fig. 25E shows the portable information terminal 9201 in the unfolded state, Fig. 25G shows the folded state, and Fig. 25F is a perspective view of the state in the middle of changing from one of Fig. 25E and Fig. 25G to the other. The portable information terminal 9201 has excellent portability in the folded state and excellent display comprehensibility due to a seamless and wide display area in the unfolded state. The display unit 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0490] An example of a television device is shown in Fig. 26A. The television device 7100 has a display unit 7500 incorporated in a housing 7101. Here, a configuration in which the housing 7101 is supported by a stand 7103 is shown.

[0491] The operation of the television device 7100 shown in Fig. 26A can be performed by operation switches provided in the housing 7101 or by a separate remote control operation unit 7111. Alternatively, a touch panel may be applied to the display unit 7500 and the television device 7100 may be operated by touching it. The remote control operation unit 7111 may have a display unit in addition to operation buttons.

[0492] Note that the television device 7100 may have a television broadcast receiver and a communication device for network connection.

[0493] FIG. 26B shows a notebook personal computer 7200. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7500 is incorporated in the housing 7211.

[0494] FIGS. 26C and 26D show an example of digital signage.

[0495] The digital signage 7300 shown in FIG. 26C has a housing 7301, a display unit 7500, a speaker 7303, etc. Further, it can have an LED lamp, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0496] FIG. 26D shows digital signage 7400 attached to a cylindrical column 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the column 7401.

[0497] The larger the display unit 7500 is, the more information can be provided at once, and it is easier to catch people's eyes. For example, it has the effect of enhancing the advertising effect.

[0498] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. Thereby, not only for advertising purposes, but also for route information, traffic information, guidance information of commercial facilities, etc. ​​​​​​​​​​​​It can also be used for the purpose of providing the information required by the user.

[0499] As shown in FIGS. 26C and 26D, the digital signage 7300 or the digital signage 7400 is preferably capable of wireless communication with the information terminal 7311 such as a smartphone held by the user. For example, by displaying the information of the advertisement displayed on the display unit 7500 on the screen of the information terminal 7311 or by operating the information terminal 7311, the display of the display unit 7500 can be switched.

[0500] A game can also be executed on the digital signage 7300 or the digital signage 7400 using the information terminal 731 1 as an operation means (controller). As a result, a large number of unspecified users can participate in the game and enjoy it simultaneously.

[0501] The display device according to an aspect of the present invention can be applied to the display unit 7500 in FIGS. 26A to 26D.

[0502] Although the electronic device of the present embodiment has a configuration having a display unit, an aspect of the present invention can also be applied to an electronic device having no display unit.

[0503] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

Example

[0504] In this example, samples (sample A1 to sample A6) corresponding to the transistor 100C shown in FIG. 9 were fabricated, and the drain current-drain voltage characteristics ( Id-Vd characteristics) of the transistor were evaluated.

[0505] <Fabrication of Sample> First, a titanium film with a thickness of 30 nm and a copper film with a thickness of 100 nm were sequentially sputtered onto a glass substrate by a patterning method, and this was processed to obtain a first gate electrode (bottom gate). .

[0506] Next, as the first gate insulating layer, a first silicon nitride film with a thickness of 50 nm, a second silicon nitride film with a thickness of 15 0 nm, a third silicon nitride film with a thickness of 100 nm, and a first silicon oxynitride film with a thickness of 3 n m were deposited in this order.

[0507] The first silicon nitride film and the third silicon nitride film were each deposited by PECVD using a mixed gas of silane at a flow rate of 200 sccm, nitrogen gas at a flow rate of 2000 sccm, and ammonia gas at a flow rate of 100 sccm. The pressure during film deposition was 100 Pa, the film deposition power was 2000 W, and the substrate temperature was 350 °C. Note that the first silicon nitride film corresponds to the insulating layer 103a shown in Embodiment 1, and the third silicon nitride film corresponds to the insulating layer 103c shown in Embodiment 1. layer 103c shown in Embodiment 1.

[0508] The second silicon nitride film was deposited by PECVD using a mixed gas of silane at a flow rate of 290 sccm, nitrogen gas at a flow rate of 2000 sccm, and ammonia gas at a flow rate of 2000 sccm. The pressure during film deposition was 200 Pa, the film deposition power was 3000 W, and the substrate temperature was 350 °C. Note that the second silicon nitride film corresponds to the insulating layer 103b shown in Embodiment 1. to.

[0509] The first silicon oxynitride film was formed using silane gas at a flow rate of 20 sccm and a flow rate of 3000 sc A film was formed by the PECVD method using a mixed gas of nitrous oxide gas of cm. The pressure during film formation was 40 Pa, the film formation power was 3000 W, and the substrate temperature was 350 °C. The first

[0510] nitrided silicon film corresponds to the insulating layer 103d shown in Embodiment 1. Subsequently, a first metal oxide film with a thickness of 25 nm was formed on the first nitrided silicon film. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4 :2:4.1 [atomic ratio]). The pressure during film formation was 0.3 Pa, the power supply power was 4.5 kW, and the substrate temperature was room temperature. As the film formation gas, a mixed gas of oxygen gas and argon gas was used, and the ratio of the flow rate of oxygen gas to the total flow rate of the film formation gas (hereinafter referred to as the oxygen flow ratio) was 10%. The film

[0511] composition of the sample formed using a target with a composition of In:Ga:Zn = 4:2:4.1 [atomic ratio]

[0512] is generally In:Ga:Zn = 4:2:3 [atomic ratio]. Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0513] Subsequently, after heat treatment at 370 °C for 1 hour in a nitrogen atmosphere, heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0514] The second silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 24 sccm and dinitrogen monoxide gas with a flow rate of 18000 s ccm. The pressure during film formation was 200 Pa, the film formation power was 130 W, and the substrate temperature was 350 °C. The second silicon oxynitride film corresponds to the insulating layer 110a shown in Embodiment 1.

[0515] The third silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 200 sccm and dinitrogen monoxide gas with a flow rate of 10000 sccm. The pressure during film formation was 300 Pa, the film formation power was 750 W, and the substrate temperature was 350 °C. The third silicon oxynitride film corresponds to the insulating layer 110b shown in Embodiment 1.

[0516] The fourth silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 20 sccm and dinitrogen monoxide gas with a flow rate of 3000 sc cm. The pressure during film formation was 40 Pa, the film formation power was 500 W, and the substrate temperature was 350 °C. The fourth silicon oxynitride film corresponds to the insulating layer 110c shown in Embodiment 1.

[0517] Subsequently, a heat treatment was performed at 370 °C for 1 hour in a nitrogen atmosphere. An oven apparatus was used for the heat treatment.

[0518] Subsequently, a second metal oxide film with a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4 :2:4.1 [atomic ratio]). The pressure during film formation was 0.8 Pa, the power supply power was 3.5 kW, and the substrate temperature was room temperature. Oxygen gas was used as the film formation gas ( ​​​​​​The oxygen flow ratio of 100%) was used.

[0519] Subsequently, in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1) , heat treatment was performed at 370 °C for 1 hour. An oven device was used for the heat treatment.

[0520] Subsequently, on the second metal oxide film, an ITSO film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed in this order. The ITSO film and the copper film were formed by sputtering. ITS O film formation used an ITSO target (In2O3:SnO2:SiO2 = 85:10: 5 [weight ratio]). A Cu target was used for the formation of the copper film.

[0521] Subsequently, a resist mask was formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film were processed to form a second metal oxide layer, an ITSO layer, and a copper layer. The processing used the wet etching method. Two chemicals, Chemical A and Chemical B, were used as the etchant. The chemicals were mixed at 5: 1 [volume ratio] immediately before use. Chemical A was an aqueous solution of phosphoric acid (less than 5 wt%), hydrofluoric acid (less than 1 wt%), nitric acid (less than 10 wt%), and an additive (less than 22 wt%). Chemical B was an aqueous solution of hydrogen peroxide (31 wt%) . The etchant temperature during etching was 30 °C.

[0522] The wet etching treatment time was varied for each of sample A1 to sample A6, and the width L2 of region 108L was varied. For sample A1, the wet etching treatment time was 60 sec, for sample A2 the wet etching treatment time was 75 se c, for sample A3 the wet etching treatment time was 90 sec, for sample A ... For 4, the wet etching processing time was 105 sec, for sample A5 the wet etching processing time was 120 sec, and for sample A6 the wet etching processing time was 13 5 sec.

[0523] Subsequently, washing was performed. For the washing, an aqueous solution obtained by diluting 85 weight% phosphoric acid 500-fold was used. The etchant temperature during etching was room temperature, and the processing time was 15 sec.

[0524] Subsequently, using the aforementioned resist mask as a mask, the second to fourth silicon oxynitride films were processed to form a second gate insulating layer. Also, when forming the second gate insulating layer, the first silicon oxynitride film in the region that did not overlap with the resist mask was removed, exposing a part of the third silicon nitride film. The processing used a dry etching method. After this, the resist mask was removed.

[0525] Subsequently, as a protective layer covering the transistor, a fourth silicon nitride film with a thickness of 100 nm and a fifth silicon oxynitride film with a thickness of 300 nm were formed in this order.

[0526] The fourth silicon nitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350 °C.

[0527] The fifth silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 290 sccm and dinitrogen monoxide gas with a flow rate of 4000 s ccm. The pressure during film formation was​​​​​​​​ The force was 133 Pa, the film-forming power was 1000 W, and the substrate temperature was 350 °C.

[0528] Subsequently, a part of the protective layer covering the transistor was opened, and a titanium film with a thickness of 30 nm, a copper film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm were deposited in this order by sputtering. After that, it was processed to obtain source and drain electrodes. Then, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a temperature of 250 °C for 1 hour in a nitrogen atmosphere. The transistors (sample A1 to sample A6) formed on the glass substrate were obtained through the above steps.

[0529]

[0530] <Id-Vd Characteristic Evaluation> Subsequently, the Id-Vd characteristics of the transistors fabricated above were measured.

[0531] The Id-Vd characteristics of the transistor were measured by sweeping the drain voltage (Vd) from 0 V to 30 V at intervals of 0.25 V with the source potential set to the ground potential (GND). The gate voltage (Vg) was set to 0 V, 2 V, 4 V, and 6 V, and the Id-Vd measurement was continuously performed using the same transistor. The transistor had a channel length of 3 μm and a channel width of 10 μm.

[0532] The Id-Vd characteristics of sample A1 to sample A6 are shown in FIGS. 27 and 28. In FIGS. 27 and 28, the horizontal axis represents the drain voltage (Vd), and the vertical axis represents the drain current (Id).

[0533] In FIGS. 27 and 28, the results of sample A1 to sample A6 are shown horizontally. is. Note that sample A1 has a width L2 of about 200 nm, sample A2 has a width L2 of about 300 nm, sample A3 has a width L2 of about 400 nm, sample A4 has a width L2 of about 500 nm, sample A5 has a width L2 of about 600 nm, sample A6 had a width L2 of about 700 nm.

[0534] Figures 27 and 28 show conditions where the transistor structure varies in the vertical direction. Sin gle Gate is marked to indicate the result of performing an Id-Vd measurement by applying a gate voltage (Vg) to the conductive layer 112 in a transistor that does not have the conductive layer 106. Source Sync. is marked to indicate the result of performing an Id-Vd measurement by applying a gate voltage (Vg) to the conductive layer 112 in a transistor that has the conductive layer 106, where the conductive layer 106 (bottom gate electrode) is electrically connected to the source electrode (GND). Top Gate Sync. is marked to indicate the result of performing an Id-Vd measurement by applying a gate voltage (Vg) to the conductive layer 112 in a transistor that has the conductive layer 106, where the conductive layer 106 (bottom gate electrode) is electrically connected to the conductive layer 112 (top gate electrode), and a gate voltage (Vg ) is applied to the conductive layer 112 (top gate electrode). As shown in Figures 27 and 28, in Single Gate, good Id-Vd characteristics were shown under any conditions. In Source Sync. and Top Gat e Sync., a decrease in the on-current was confirmed when the width L2 was about 200 nm, about 300 nm, and about 400 nm, but no decrease in the on-current was confirmed when the width L2 was about 500 nm or more. gate electrode), and a gate voltage (Vg ) is applied to the conductive layer 112 (top gate electrode).

[0535] As shown in Figures 27 and 28, in Single Gate, good Id-Vd characteristics were shown under any conditions. In Source Sync. and Top Gat e Sync., a decrease in the on-current was confirmed when the width L2 was about 200 nm, about 300 nm, and about 400 nm, but no decrease in the on-current was confirmed when the width L2 was about 500 nm or more. e Sync., a decrease in the on-current was confirmed when the width L2 was about 200 nm, about 300 nm, and about 400 nm, but no decrease in the on-current was confirmed when the width L2 was about 500 nm or more. e Sync., a decrease in the on-current was confirmed when the width L2 was about 200 nm, about 300 nm, and about 400 nm, but no decrease in the on-current was confirmed when the width L2 was about 500 nm or more. It did not show any problems and exhibited good Id-Vd characteristics. By increasing the width L2, it was confirmed that the decrease in the on-current when a high drain voltage was applied could be suppressed.

Example

[0536] In this example, samples (sample B1 to sample B3) corresponding to the regions 108C, 108L, and 108N shown in FIG. 2 were fabricated, and the resistances of the regions 108C, 108L, and 108N were evaluated. Sample B1 corresponds to the region 108C, sample B2 corresponds to the region 108L, and sample B3 corresponds to the region 108N.

[0537] <Fabrication of Samples - sample B1> First, a first metal oxide film with a thickness of 25 nm was formed on a glass substrate. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power of the power source was 2.5 kW, and the substrate temperature was room temperature. As the film-forming gas, a mixed gas of oxygen gas and argon gas was used, and the oxygen flow ratio was 10%.

[0538] Subsequently, after performing a heat treatment at 370 °C for 1 hour in a nitrogen atmosphere, a heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0539] Subsequently, a first silicon oxynitride film with a thickness of 5 nm, a second silicon oxynitride film with a thickness of 130 nm, and a third silicon oxynitride film with a thickness of 5 nm were formed in this order.

[0540] ​​​​​​​​​​​​The first silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 24 sccm and dinitrogen monoxide gas with a flow rate of 18000 s ccm. The pressure during film formation was 200 Pa, the film formation power was 130 W, and the substrate temperature was 350 °C.

[0541] The second silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 200 sccm and dinitrogen monoxide gas with a flow rate of 10000 sccm. The pressure during film formation was 300 Pa, the film formation power was 750 W, and the substrate temperature was 350 °C.

[0542] The third silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 20 sccm and dinitrogen monoxide gas with a flow rate of 300 0 sccm. The pressure during film formation was 40 Pa, the film formation power was 500 W, and the substrate temperature was 350 °C.

[0543] Subsequently, heat treatment was performed at 370 °C for 1 hour in a nitrogen atmosphere. An oven device was used for the heat treatment.

[0544] Subsequently, a second metal oxide film with a thickness of 20 nm was formed on the third silicon oxynitride film. The second metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4 :2:4.1 [atomic ratio]). The pressure during film formation was 0.8 Pa, the power supply power was 3.5 kW, and the substrate temperature was room temperature. Oxygen gas ( oxygen flow rate ratio 100%) was used as the film formation gas.

[0545] Subsequently, heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0546] Subsequently, on the second metal oxide film, an ITSO film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed in this order. The ITSO film and the copper film were formed by sputtering. The formation of the ITSO film used an ITSO target (In2O3:SnO2:SiO2 = 85:10: 5 [weight ratio]). A Cu target was used for the formation of the copper film.

[0547] Subsequently, a silicon nitride film with a thickness of 100 nm was formed.

[0548] The silicon nitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350 °C.

[0549] Subsequently, the silicon nitride film, the copper film, the ITSO film, and the second metal oxide film were removed to expose the third silicon oxynitride film.

[0550] Subsequently, openings reaching the first metal oxide film were formed in the first silicon oxynitride film, the second silicon oxynitride film, and the third silicon oxynitride film, and terminals were provided.

[0551] <Fabrication of sample B2> First, on the glass substrate, the first metal oxide film, the first silicon oxynitride film, the second silicon oxynitride film, the third silicon oxynitride film, the second metal oxide film, the ITSO film, and the copper film were formed. Until the formation of the copper film, reference can be made to the description of <Fabrication of sample B1>, so detailed description is omitted.

[0552] ​​​Subsequently, the copper film, the ITSO film, and the second metal oxide film were removed to expose the third silicon oxynitride film.

[0553] Subsequently, a 100-nm-thick silicon nitride film was formed.

[0554] The silicon nitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350°C.

[0555] Subsequently, openings reaching the first metal oxide film were formed in the first silicon oxynitride film, the second silicon oxynitride film, the third silicon oxynitride film, and the silicon nitride film, and terminals were provided. .

[0556] <Fabrication of sample B3> First, a first metal oxide film, a first silicon oxynitride film, a second silicon oxynitride film, a third silicon oxynitride film, a second metal oxide film, an ITSO film, and a copper film were formed on a glass substrate. Refer to the description of <Fabrication of sample B1> for the formation of the copper film , and detailed description is omitted.

[0557] Subsequently, the copper film, the ITSO film, the second metal oxide film, the first silicon oxynitride film, the second silicon oxynitride film, and the third silicon oxynitride film were removed to expose the first metal oxide film.

[0558] Subsequently, a 100-nm-thick silicon nitride film was formed.

[0559] The silicon nitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas A film was formed by PECVD using a mixed gas of ammonia gas with a flow rate of 100 sccm. During film formation, the pressure was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350 °C.

[0560] Subsequently, an opening reaching the first metal oxide film was formed in the silicon nitride film, and terminals were provided. .

[0561] <Sheet Resistance Measurement> Subsequently, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the first metal oxide film. did.

[0562] The values of the sheet resistance of samples B1 to B3 are shown in FIG. 29. FIG. 29 In, the horizontal axis represents the sample name, and the vertical axis represents the sheet resistance Rs.

[0563] As shown in FIG. 29, the sheet resistance of sample B1 corresponding to region 108C was approximately 1.5×10 11 Ω / □. The sheet resistance of sample B2 corresponding to region 108L was 4.6×10 5 Ω / □. The sheet resistance of sample B3 corresponding to region 108N was 8.0×10 2 Ω / □.

Example

[0564] In this example, samples (sample C1 and sample C2) corresponding to the transistor 100A shown in FIG. 5 were prepared, and the cross-sectional shape was evaluated.

[0565] <Preparation of Sample> First, a titanium film with a thickness of 30 nm and a copper film with a thickness of 100 nm were sequentially sputtered on a glass substrate by sputtering method, and this was processed to obtain a first gate electrode (bottom gate). .

[0566] Next, as the first gate insulating layer, a first silicon nitride film with a thickness of 50 nm, a second silicon nitride film with a thickness of 15 0 nm, a third silicon nitride film with a thickness of 100 nm, and a first silicon oxynitride film with a thickness of 3 n m were formed in this order. Since the description of Example 1 can be referred to for the first silicon nitride film to the third silicon nitride film and the first silicon oxynitride film, detailed description is omitted.

[0567] Subsequently, a first metal oxide film with a thickness of 25 nm was formed on the first silicon oxynitride film. Since the description of Example 1 can be referred to for the first metal oxide film, detailed description is omitted

[0568] Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0569] Subsequently, after heat treatment at 370 °C for 1 hour in a nitrogen atmosphere, heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0570] Subsequently, as the second gate insulating layer, a second silicon oxynitride film with a thickness of 5 nm, a third silicon oxynitride film with a thickness of 1 30 nm, and a fourth silicon oxynitride film with a thickness of 5 nm were formed in this order. Since the description of Example 1 can be referred to for the second silicon oxynitride film to the fourth silicon oxynitride film, detailed description is omitted.

[0571] Subsequently, heat treatment was performed at 370 °C for 1 hour in a nitrogen atmosphere. An oven device was used for the heat treatment.

[0572] ​​​​​Subsequently, a second metal oxide film with a thickness of 20 nm was formed on the fourth silicon oxynitride film. Since the description of the second metal oxide film can be referred to in Example 1, a detailed explanation is omitted.

[0573] Subsequently, heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0574] Subsequently, a 10-nm-thick ITSO film and a 100-nm-thick copper film were formed on the second metal oxide film in this order. Since the description of the ITSO film and the copper film can be referred to in Example 1, a detailed explanation is omitted.

[0575] Subsequently, a resist mask was formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film were processed to form a second metal oxide layer, an ITSO layer, and a copper layer. Wet etching was used for the processing. Since the description of the etchant can be referred to in Example 1, a detailed explanation is omitted. The wet etching time was 60 sec.

[0576] Subsequently, using the aforementioned resist mask as a mask, the second to fourth silicon oxynitride films were processed to form a second gate insulating layer. Dry etching was used for the processing. Here, the dry etching conditions were different between sample C1 and sample C2. For sample C1, C4F8 was used as the etching gas. The ICP high-frequency power was 6000 W, the Bias high-frequency power was 1000 W, the pressure was 0.67 Pa, the C4F8 gas flow rate was 100 sccm, the etching time was 140 sec, and the lower electrode temperature was 10 °C.

[0577] ​​

[0578] For sample C2, CF4 was used as the etching gas. The ICP high-frequency power was 600 0 W, the Bias high-frequency power was 750 W, the pressure was 0...

Claims

【Claim 1】 An oxide semiconductor device having an oxide semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a metal oxide layer, and a conductive layer, wherein the oxide semiconductor layer, the second insulating layer, the metal oxide layer, and the conductive layer are stacked in this order on the first insulating layer, in a cross-section in the channel length direction, an end portion of the second insulating layer is located inside an end portion of the oxide semiconductor layer, end portions of the conductive layer and the metal oxide layer are each located inside an end portion of the second insulating layer, the third insulating layer is in contact with an upper surface of the first insulating layer, an upper surface and side surfaces of the oxide semiconductor layer, an upper surface and side surfaces of the second insulating layer, side surfaces of the metal oxide layer, and an upper surface and side surfaces of the conductive layer, the oxide semiconductor layer has a first region, a pair of second regions, and a pair of third regions, the first region overlaps with the first insulating layer and the metal oxide layer, the second regions sandwich the first region, overlap with the second insulating layer, and do not overlap with the metal oxide layer, the third regions sandwich the first region and the pair of second regions and do not overlap with the second insulating layer, the third regions are in contact with the third insulating layer, the third regions include a portion having a lower resistance than the first region, the second regions include a portion having a higher resistance than the third regions, a semiconductor device.

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