Semiconductor device

Abstract

To provide, among others, a pulse signal output circuit capable of operating stably, and a shift register including the pulse signal output circuit.SOLUTION: In an embodiment of the pulse signal output circuit, the channel length of a transistor forming a node connecting to an output terminal is longer than the channel length of a transistor functioning as an output terminal. Thereby, the amount of a leakage current from the node can be reduced, and the potential can be kept stably for a long period of time, so that a malfunction of the pulse signal output circuit can be prevented.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosed invention relates to a pulse signal output circuit and a shift register.

Background Art

[0002] Transistors formed on a flat plate such as a glass substrate, which are used in liquid crystal display devices and the like, are mainly manufactured using a semiconductor material such as amorphous silicon or polycrystalline silicon. Amo Although transistors using rphous silicon have a low field-effect mobility, they can cope with the large area of the glass substrate. On the other hand, transistors using polycrystalline silicon have a high field-effect mobility, but require a crystallization process such as laser annealing and do not necessarily adapt to the large area of the glass substrate.

[0003] On the other hand, transistors using an oxide semiconductor as the semiconductor material have attracted attention. For example, techniques for manufacturing transistors using zinc oxide or an In-Ga-Zn-O-based oxide semiconductor as the semiconductor material and using them as switching elements in image display devices are disclosed in Patent Document 1 and Patent Document 2.

[0004] Transistors using an oxide semiconductor in the channel formation region have obtained a higher field-effect mobility than transistors using amorphous silicon. In addition, since the oxide semiconductor film can be formed at a temperature of 300°C or lower by a sputtering method or the like, transistors using an oxide semiconductor are easier to manufacture than transistors using polycrystalline silicon.

[0005]

[0005] It is expected to be applied to the pixel portion and the drive circuit of a display device such as a trolluminescence display or electronic paper. For example, a technology for configuring the pixel portion and the drive circuit of a display device by a transistor manufactured using the above oxide semiconductor is disclosed in Non-Patent Document 1. However, all of the transistors manufactured using the above oxide semiconductor are n-channel type transistors. Therefore, when configuring a drive circuit using a transistor manufactured using an oxide semiconductor, the drive circuit will be configured only by n-channel type transistors.

Prior Art Documents

[0006]

Patent Documents

Patent Document 1

Patent Document 2

Non-Patent Documents

[0007]

Non-Patent Document 1

[0008]

Summary of the Invention

Problems to be Solved by the Invention

[0009] The drive circuit is configured by a shift register including a pulse signal output circuit or the like. When the shift register is configured by unipolar transistors, problems such as unstable operation may occur.

[0010] ​​​​​​​​In view of the above problems, one aspect of the present invention aims to provide a pulse signal output circuit that can operate stably and a shift register including the same. This is one of the problems.

Means for Solving the Problems

[0011] One of the problems is to provide a pulse signal output circuit that can operate stably and a shift register including the same. In one form of the pulse signal output circuit, the source terminal or drain terminal of one transistor is connected to the gate electrode of another transistor, and the source terminal or drain terminal of the other transistor forms the output terminal of the pulse signal output circuit. The channel length of the one transistor is made larger than the channel length of the other transistor. This can suppress the leakage current that changes the gate potential of the other transistor and prevent malfunction of the pulse signal output circuit. Specifically, for example, the following configuration can be adopted.

[0012]

[0013] One aspect of the present invention includes first to ninth transistors, a first input signal generation circuit, and a second input signal generation circuit. The first terminal of the first transistor and the first terminal of the second transistor are electrically connected to a first output terminal. The first terminal of the third transistor and the first terminal of the fourth transistor are electrically connected to a second output terminal. The first input signal generation circuit includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor and the first terminal of the sixth transistor are electrically connected and function as the output terminal of the first input signal generation circuit. The second input signal generation circuit includes seventh to ninth transistors. ​​​​​​having a transistor, the second terminal of the seventh transistor, the second terminal of the eighth transistor, and the first terminal of the ninth transistor are electrically connected to function as the output terminal of the second input signal generation circuit, the gate terminal of the first transistor, the gate terminal of the third transistor, and the output terminal of the first input signal generation circuit are electrically connected, the gate terminal of the second transistor, the gate terminal of the fourth transistor, and the output terminal of the second input signal generation circuit are electrically connected, the channel length of the sixth transistor is greater than the channel lengths of the third transistor and the fourth transistor, and the channel length of the ninth transistor is greater than the channel lengths of the third transistor and the fourth transistor, which is a pulse signal output circuit. Further, in the above pulse signal output circuit, the second terminal of the first transistor and the second terminal of the third transistor receive the first clock signal, the second terminal of the second transistor, the second terminal of the fourth transistor, the second terminal of the sixth transistor and the second terminal of the ninth transistor are given the first potential, the second terminal of the fifth transistor, the first terminal of the seventh transistor, and the first terminal of the eighth transistor

[0014] are given a second potential higher than the first potential, the gate terminal of the fifth transistor and the gate terminal of the ninth transistor receive the first pulse signal, the gate terminal of the sixth transistor receives the output signal of the second input signal generation circuit, the gate terminal of the seventh transistor receives the third pulse signal, the gate terminal of the eighth transistor receives the second clock signal, and the second pulse signal is output from the first output terminal or the second output terminal ​ It is preferable to output.

[0015] Also, in the above pulse signal output circuit, at least one of the sixth transistor or the ninth transistor may be a multi-gate transistor having at least two gates arranged in series.

[0016] Another aspect of the present invention includes the first to eleventh transistors, a first input signal generation circuit and a second input signal generation circuit. The first terminal of the first transistor and the first terminal of the second transistor are electrically connected to the first output terminal. The first terminal of the third transistor and the first terminal of the fourth transistor are electrically connected to the second output terminal. The first input signal generation circuit includes the fifth to seventh transistors. The first terminal of the fifth transistor, the first terminal of the sixth transistor, and the first terminal of the seventh transistor are electrically connected. The second terminal of the seventh transistor functions as the output terminal of the first input signal generation circuit. The second input signal generation circuit includes the eighth to eleventh transistors. The second terminal of the eleventh transistor and the first terminal of the ninth transistor are electrically connected. The second terminal of the ninth transistor, the second terminal of the eighth transistor, and the first terminal of the tenth transistor are electrically connected to function as the output terminal of the second input signal generation circuit. The gate terminal of the first transistor, the gate terminal of the third transistor, and the output terminal of the first input signal generation circuit are electrically connected. The gate terminal of the second transistor, the gate terminal of the fourth transistor, and the output terminal of the second input ​The output terminal of the signal generation circuit is electrically connected, and the channel length of the sixth transistor is greater than the channel lengths of the third transistor and the fourth transistor, and the channel length of the tenth transistor is greater than the channel lengths of the third transistor and the fourth transistor, and it is a pulse signal output circuit.

[0017] Also, in the above pulse signal output circuit, the second terminal of the first transistor and the third transistor receive the first clock signal at their second terminals, and the second terminal of the second transistor, the second terminal of the fourth transistor, the second terminal of the sixth transistor and the second terminal of the tenth transistor are given the first potential, and the second terminal of the fifth transistor, the gate terminal of the seventh transistor, the first terminal of the eighth transistor and the first terminal of the eleventh transistor are given a second potential higher than the first potential The gate terminals of the fifth transistor and the tenth transistor receive the first pulse signal, the gate terminal of the sixth transistor receives the output signal of the second input signal generation circuit the gate terminal of the eighth transistor receives the third pulse signal, the gate terminal of the ninth transistor receives the second clock signal, the gate terminal of the eleventh transistor receives the third clock signal, and it is preferable to output the second pulse signal from the first output terminal or the second output terminal.

[0018] Also, in the above pulse signal output circuit, at least one of the sixth transistor or the tenth transistor may be a multi-gate transistor having at least two gates arranged in series. ​

[0019] Also, in the pulse signal output circuit according to one aspect of the present invention described above, one terminal is electrically connected to a node where the gate terminal of the second transistor, the gate terminal of the fourth transistor, and the output terminal of the second input signal generation circuit are electrically connected, and a capacitive element may further be provided. Also, in the above, it is preferable to use an oxide semiconductor for any of the plurality of transistors. Further, a shift register can be configured by using a plurality of the above pulse signal output circuits. Note that, in the above, a transistor may be configured using an oxide semiconductor, but the disclosed invention is not limited thereto. In this specification and the like, terms such as "above" and "below" do not limit the positional relationship of components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", components other than those between the gate insulating layer and the gate electrode are not excluded.

[0020] In this specification and the like, terms such as "electrode" and "wiring" do not limit these components functionally. For example, an "electrode" may be used as part of a "wiring", and vice versa. Further, terms such as "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. Also, the functions of "source" and "drain" may be different when transistors with different polarities are employed.

[0021]

[0022]

[0023]

[0024] ​​​​​​​​​​​​In some cases where the direction of the current changes during the circuit operation, etc., it may be switched. Therefore , in this specification, the terms "source" and "drain" can be used interchangeably .

[0025] Note that in this specification etc., "electrically connected" includes the case where it is connected via "something having some electrical action ". Here, "something having some electrical action " is not particularly limited as long as it enables the exchange of electrical signals between the connection targets.

[0026] For example, "something having some electrical action" includes electrodes, wirings, switching elements such as transistors , resistance elements, inductors, capacitors, and other elements having various functions .

Advantages of the Invention

[0027] Provided is a pulse signal output circuit capable of operating stably and a shift register including the same .

Brief Description of the Drawings

[0028]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiment for Carrying Out the Invention

[0029] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below.

[0030] Note that the position, size, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, range, etc. for the sake of easy understanding. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like. Note that ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0031] Note that ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting. Note that ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0032] (Embodiment 1) In the present embodiment, a pulse signal output circuit and a shift register including the pulse signal output circuit With reference to FIGS. 1 to 4, a configuration example of the [object] and its operation will be described. <Circuit Configuration>

[0033] First, a circuit configuration example of a pulse signal output circuit and a shift register including the pulse signal output circuit will be described with reference to FIG. 1.

[0034] The shift register shown in this embodiment includes a first pulse signal output circuit 10 _1 ~ an nth pulse signal output circuit 10 _n (n ≧ 2), and first to fourth signal lines 11 to 14 for transmitting a clock signal (see FIG. 1(A)). The first clock signal ( CLK1) is applied to the first signal line 11, the second clock signal (CLK2) is applied to the second signal line 12, the third clock signal (CLK3) is applied to the third signal line 13, and the fourth clock signal (CLK4) is applied to the fourth signal line 1 4.

[0035] The clock signal is a signal that repeats an H signal (high potential) and an L signal (low potential) at regular intervals. Here, the first to fourth clock signals (CLK1 to CLK4) are signals delayed by 1 / 4 cycle each. In this embodiment, the above clock signals are used to control the pulse signal output circuit and the like.

[0036] The first to nth pulse signal output circuits 10 _1 ~ the nth pulse signal output circuit 10 _n each have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 1(B)).

[0037] ​​The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first signal line 11 ~ the fourth signal line 14. For example, in the first pulse signal output circuit path 10 _1 the first input terminal 21 is electrically connected to the first signal line 11, the second input terminal 22 is electrically connected to the second signal line 12, and the third input terminal 23 is electrically connected to the third signal line 1 3. Also, in the second pulse signal output circuit 10 _2 the first input terminal 21 is electrically connected to the second signal line 12, the second input terminal 22 is electrically connected to the third signal line 1 3, and the third input terminal 23 is electrically connected to the fourth signal line 14 . Here, the case where the signal lines connected to the n-th pulse signal output circuit 10 _n are the second signal line 12, the third signal line 13, and the fourth signal line 14 is shown, but the signal lines to be connected will be different depending on the value of n. Therefore, it should be noted that the configuration shown here is merely an example.

[0038] Also, in the m-th pulse signal output circuit (m ≥ 2) of the shift register shown in this embodiment, the fourth input terminal 24 is electrically connected to the first output terminal 26 of the (m - 1)-th pulse signal output circuit, the fifth input terminal 25 is electrically connected to the first output terminal 26 of the (m + 2)-th pulse signal output circuit, the first output terminal 26 is electrically connected to the fourth input terminal 24 of the (m + 1)-th pulse signal output circuit, and the second output terminal 27 outputs a signal to OUT(m).

[0039] For example, in the third pulse signal output circuit 10 _3 the fourth input terminal 24 is the second pulse signal output circuit 10​​_2 is electrically connected to the first output terminal 26, and the fifth input terminal 25 is the first output terminal 26 of the fifth pulse signal output circuit 10 _5 and is electrically connected to the first output terminal 26, and the first output _4 terminal 26 is connected to the fourth input terminal 24 of the fourth pulse signal output circuit 10 and the first pulse signal output circuit 10 _1 and is electrically connected to the fifth input terminal 25.

[0040] Also, in the first pulse signal output circuit 10 _1 , the first start pulse (SP1) from the fifth wiring 15 is input to the fourth input terminal 24. Also, in the k-th pulse signal output circuit 1 0 0 _k (where k is a natural number from 2 to n), the output pulse of the previous stage is input to the fourth input terminal 24. Also, in the (n - 1)-th pulse signal output circuit 10 , the second start pulse (SP2) is input to the fifth input _(nー1) terminal 25. Also, in the n-th pulse signal output circuit 10 circuit 10 _n , the third start pulse (SP3) is input to the fifth input terminal 25 . Note that the second start pulse (SP2) and the third start pulse (SP3) may be signals input from the outside or signals generated inside the circuit.

[0041] Next, the specific _1 configuration of the first pulse signal output circuit 10 _n to the n-th pulse signal output circuit 10 will be described.

[0042] Each of the first pulse signal output circuit 10 _1 to the n-th pulse signal output circuit 10 _n is composed of a pulse signal generation circuit composed of the first transistor 101 to the fourth transistor 104, and The first input signal generation circuit composed of the fifth transistor 105 to the seventh transistor 107 and the second input signal generation circuit composed of the eighth transistor 108 to the eleventh transistor 111 are included (see FIG. 1(C)). In addition to the first input terminal 21 to the fifth input terminal 25 described above, signals are supplied from the first power supply line 31 and the second power supply line 32 to the first transistor 101 to the eleventh transistor 111.

[0043] A specific configuration example of the pulse signal generation circuit is as follows.

[0044] One of the first terminals (either the source terminal or the drain terminal) of the first transistor 101 is electrically connected to one of the first terminals of the second transistor 102 through the first output terminal 26. Similarly, one of the first terminals of the third transistor 103 and one of the first terminals of the fourth transistor 104 are electrically connected to the second output terminal 27. And the gate terminal of the first transistor 101, the gate terminal of the third transistor 103, and the output terminal of the first input signal generation circuit are electrically connected. Also, the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, and the output terminal of the second input signal generation circuit are electrically connected.

[0045] The second terminal (the other of the source terminal and the drain terminal) of the first transistor 101 receives the first clock signal. Also, the second terminal of the first transistor 101 functions as the first input terminal 21 of the pulse signal output circuit. The second terminal of the second transistor 102 receives the first potential (for example, low potential VSS) through the first power supply line 31. ​​​​​​​​​​​is provided. A first clock signal is input to the second terminal of the third transistor 103, which also functions as the first input terminal 21 of the pulse signal output circuit. A first potential is provided to the second terminal of the fourth transistor 104 via the first power supply line 31. The specific configuration example of the first input signal generation circuit is as follows. The first terminal of the fifth transistor 105, the first terminal of the sixth transistor 106, and the first terminal of the seventh transistor 107 are electrically connected. Also, the second terminal of the seventh transistor 107 functions as the output terminal of the first input signal generation circuit.

[0046] The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32.

[0047] Note that in this embodiment, the seventh transistor 107 is provided, but the seventh transistor The second terminal of the seventh transistor 107 functions as the output terminal of the first input signal generation circuit. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32.

[0048] The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32. The second potential is provided to the second terminal of the fifth transistor 105 via the second power supply line 32, the first potential is provided to the second terminal of the sixth transistor 106 via the first power supply line 31, and a pulse signal (including the start pulse signal in the first pulse signal output circuit) from the previous stage is input to the gate terminal of the fifth transistor 105. Also, the gate terminal of the fifth transistor 105 functions as the first input terminal of the first input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The output signal of the second input signal generation circuit is input to the gate terminal of the sixth transistor 106. Also, the gate terminal of the sixth transistor 106 functions as the second input terminal of the first input signal generation circuit. The second potential is provided to the gate terminal of the seventh transistor 107 via the second power supply line 32.

[0049] Note that in this embodiment, the seventh transistor 107 is provided, but the seventh transistor It is also possible to adopt a configuration without the Ta107. When the seventh transistor 107 is provided, the potential rise of the first terminal of the fifth transistor 105 that may occur due to the bootstrapping operation can be suppressed. That is, since it is possible to prevent a large bias voltage from being applied between the gate and the source (or between the gate and the drain) of the fifth transistor 105, deterioration of the fifth transistor 105 can be suppressed. The specific configuration example of the second input signal generation circuit is as follows. The second terminal of the eleventh transistor 111 and the first terminal of the ninth transistor 109 are electrically connected. Also, the second terminal of the ninth transistor, the second terminal of the eighth transistor, and the first terminal of the tenth transistor are electrically connected to function as the output terminal of the second input signal generation circuit. The first terminal of the eighth transistor 108 and the first terminal of the eleventh transistor 111 are supplied with a second potential via the second power supply line 32. The second terminal of the tenth transistor 110 is supplied with a first potential via the first power supply line 31. A pulse signal two stages behind is input to the gate terminal of the eighth transistor 108. Also, the gate terminal of the eighth transistor 108 functions as the first input terminal of the second input signal generation circuit and also as the fifth input terminal 25 of the pulse signal output circuit. The second clock signal is input to the gate terminal of the ninth transistor 109. Also, the gate terminal of the ninth transistor 109 functions as the second input terminal of the second input signal generation circuit.

[0050]

[0051]

[0052] ​​​​​​​​​​​​​​also functions as the second input terminal 22 of the pulse signal output circuit. The tenth transistor 1 A pulse signal from the previous stage (start pulse signal in the first pulse signal output circuit) is input to the gate terminal of 10. Further, the gate terminal of the tenth transistor 110 functions as the third input terminal of the second input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. A third clock signal is input to the gate terminal of the eleventh transistor 111. Further, the gate terminal of the tenth transistor 110 functions as the third input terminal of the second input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. A third clock signal is input to the gate terminal of the eleventh transistor 111. Further, the gate terminal of the tenth transistor 110 functions as the third input terminal of the second input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. A third clock signal is input to the gate terminal of the eleventh transistor 111. Further, the gate terminal of the tenth transistor 110 functions as the third input terminal of the second input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. A third clock signal is input to the gate terminal of the eleventh transistor 111. Further, the gate terminal of the tenth transistor 110 functions as the third input terminal of the second input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. A third clock signal is input to the gate terminal of the eleventh transistor 111. Further, the gate terminal of the tenth transistor 110 functions as the third input terminal of the second input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. A third clock signal is input to the gate terminal of the eleventh transistor 111.

[0053] In the pulse signal output circuit shown in this embodiment, the channel length of the sixth transistor 106 is larger than the channel lengths of the third transistor 103 and the fourth transistor 104. Also, the channel length of the tenth transistor 110 is larger than the channel lengths of the third transistor 103 and the fourth transistor 104. In the pulse signal output circuit shown in this embodiment, the channel length of the sixth transistor 106 is larger than the channel lengths of the third transistor 103 and the fourth transistor 104. Also, the channel length of the tenth transistor 110 is larger than the channel lengths of the third transistor 103 and the fourth transistor 104. In the pulse signal output circuit shown in this embodiment, the channel length of the sixth transistor 106 is larger than the channel lengths of the third transistor 103 and the fourth transistor 104. Also, the channel length of the tenth transistor 110 is larger than the channel lengths of the third transistor 103 and the fourth transistor 104. In the pulse signal output circuit shown in this embodiment, the channel length of the sixth transistor 106 is larger than the channel lengths of the third transistor 103 and the fourth transistor 104. Also, the channel length of the tenth transistor 110 is larger than the channel lengths of the third transistor 103 and the fourth transistor 104. As a result, the shift amount of the threshold voltage of the sixth transistor 106 and the tenth transistor 110 can be reduced, and deterioration can be suppressed. As a result, the shift amount of the threshold voltage of the sixth transistor 106 and the tenth transistor 110 can be reduced, and deterioration can be suppressed.

[0054] Note that each configuration of the pulse signal output circuit described above (such as the configuration example of the pulse signal generation circuit, the first input signal generation circuit, and the second input signal generation circuit) is merely an example, and the disclosed invention is not limited thereto. Note that each configuration of the pulse signal output circuit described above (such as the configuration example of the pulse signal generation circuit, the first input signal generation circuit, and the second input signal generation circuit) is merely an example, and the disclosed invention is not limited thereto. Note that each configuration of the pulse signal output circuit described above (such as the configuration example of the pulse signal generation circuit, the first input signal generation circuit, and the second input signal generation circuit) is merely an example, and the disclosed invention is not limited thereto.

[0055] In the following description of this embodiment, in the pulse signal output circuit shown in Fig. 1(C), the first transistor The node formed by connecting the gate terminal of the transistor 101, the gate terminal of the third transistor 103, and the output terminal of the first input signal generation circuit is defined as node A. Also, the node formed by connecting the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104 and the output terminal of the second input signal generation circuit is defined as node B.

[0056] A capacitor element may be provided between the above node A and the first output terminal 26 to preferably perform a bootstrap operation. Also, a capacitor element electrically connected to node B may be provided to hold the potential of node B.

[0057] Note that it is preferable to use an oxide semiconductor for the first transistor 101 to the eleventh transistor 111. By using an oxide semiconductor, the off-current of the transistor can be reduced. Also, compared with amorphous silicon or the like, the on-current and the field-effect mobility can be increased. Further, deterioration of the transistor can be suppressed. As a result, an electronic circuit with low power consumption, capable of high-speed operation, and enhanced operation accuracy can be realized. Note that the transistor using an oxide semiconductor will be described in detail in later embodiments, so it is omitted here.

[0058] <Operation> Next, the operation of the shift register shown in FIG. 1 will be described with reference to FIGS. 2 to 4. Specifically, the operations in each period from the first period 51 to the sixth period 56 in the timing chart shown in FIG. 2 will be described using FIGS. 3 and 4. In the timing chart, CLK1 to CLK6 are input signals, and the operations in each period are as follows. ​​​​CLK4 indicates a clock signal respectively, SP1 indicates a first start pulse, and OUT 1 to OUT4 are outputs from the second output terminals of the first pulse signal output circuit 10 _1 to the fourth pulse signal output circuit 10 _ 4, node A and node B indicate the potentials of node A and node B respectively, and SROUT1 to SROUT4 are from the first output terminals of the first pulse signal output circuit 1 0 0 _1 to the fourth pulse signal output circuit 10 _4 are outputs.

[0059] In the following description, it is assumed that the first transistor 101 to the eleventh transistor 111 are all n-channel type transistors. Also, in FIGS. 3 and 4, when a transistor is represented by a solid line, it means that the transistor is in a conductive state (on state ), and when it is represented by a broken line, it means that the transistor is in a non-conductive state ( off state). ) shall be represented.

[0060] Typically, the operation of the first pulse signal output circuit 10 _1 will be described. The first pulse signal output circuit 10 _1 is configured as described above. Also, the relationship between each input signal and each supplied potential is as described above. In the following description, the high potential (also referred to as H level, H signal, etc.) applied to each input terminal and each power supply line is all VDD, and the low potential ( also referred to as L level, L signal, etc.) is all VSS. In the first period 51, since SP1 is at the H level, the first pulse signal output circuit 10 _1

[0061] In the first period 51, since SP1 is at the H level, the first pulse signal output circuit 10 _1The gate terminal of the fifth transistor 105 that functions as the fourth input terminal 24 and the first A high potential is applied to the gate terminal of the transistor 110 of 0, and the fifth transistor 105 and The tenth transistor 110 becomes conductive. In the first period 51, since CLK3 is also at the H level, the eleventh transistor 111 also turns on. Also, since a high potential is applied to the gate terminal of the seventh transistor 107, the seventh transistor 107 also turns on (see Fig. 3(A)). When the fifth transistor 105 and the seventh transistor 107 turn on, the potential of node A rises. Also, when the tenth transistor 110 turns on,

[0062] the potential of node B drops. Since the potential of the second terminal of the fifth transistor 105 is VDD, the potential of the first terminal of the fifth transistor 105 is a value (VDD - Vth105) that has dropped by the threshold voltage of the fifth transistor 105 from the potential of the second terminal. And, since the potential of the gate terminal of the seventh transistor 107 is VDD, when the threshold voltage Vth107 of the seventh transistor 107 is greater than or equal to Vth105, the potential of node A becomes (VDD - Vth107) and the seventh transistor 107 turns off. On the other hand, when Vth107 is less than Vth105, the seventh transistor 107 remains on, and the potential of node A rises to (VDD - Vth105). Hereinafter, the arrival point of the potential of node A in the first period 51 is V Let's call it. Here, Vth105 and Vth107 are the threshold voltages of the fifth transistor 105 and the seventh transistor 10 respectively. And when Vth107 is greater than or equal to Vth105, the potential of node A becomes (VDD - Vth107) and the seventh transistor 107 turns off. On the other hand, when Vth107 is less than Vth105, the seventh transistor 107 remains on, and the potential of node A rises to (VDD - Vth105). Hereinafter, the arrival point of the potential of node A in the first period 51 is V Let's call it. Here, Vth105 and Vth107 are the threshold voltages of the fifth transistor 105 and the seventh transistor 10 respectively. Let's call it. Here, Vth105 and AH Vth107 are, respectively, the threshold voltages of the fifth transistor 105 and the seventh transistor 10 7, respectively, and It is the threshold voltage of 7. The same applies to other transistors below. The voltage of node A reaches V AH When this happens, the fifth transistor 105 and the seventh transistor 107 turn off, and node A becomes floating while maintaining V AH .

[0063] When the potential of node A reaches V AH , the first transistor 101 and the third transistor 103 turn on. Here, since CLK1 is at the L level, an L level is output from the first output terminal 26 and the second output terminal 27.

[0064] In the second period 52, CLK1 switches from the L level to the H level. Here, since the first transistor 101 and the third transistor 103 are on, the potential of the first output terminal 26 and the potential of the second output terminal 27 increase. Furthermore, there is a capacitance between the gate terminal and the source terminal (or drain terminal) of the first transistor 101, and due to this, the gate terminal and the source terminal (or drain terminal) are capacitively coupled. Similarly, there is a capacitance between the gate terminal and the source terminal (or drain terminal) of the third transistor 103, and due to this, the gate terminal and the source terminal (or drain terminal) are capacitively coupled. Therefore, as the potential of the first output terminal 26 and the potential of the second output terminal 27 increase, the potential of floating node A also increases (bootstrap operation). The potential of node A finally becomes higher than VDD + Vth101, and the potential of the first output terminal 26 and the potential of the second output terminal 27 become VDD (H level) (see FIGS. 2 and 3(B)). terminal 26 and the potential of the second output terminal 27 become VDD (H level) (see FIGS. 2 and 3(B)).

[0065] Also, in the second period 52, since the tenth transistor 110 is in the on state, node B is also maintained at the L level. Therefore, when the first output terminal 26 changes from the L level to the H level, the potential fluctuation of node B due to capacitive coupling is suppressed, and the occurrence of malfunctions caused thereby can be prevented.

[0066] In the third period 53, SP1 becomes the L level, and the fifth transistor 105 and the first tenth transistor 110 become the off state. Also, since CLK1 is maintained at the H level and the potential of node A does not change, VDD (H level) is output from the first output terminal 26 and the second output terminal 27 (see Fig. 3(C)). Note that in the third period 53, node B is in a floating state, but since the potential of the first output terminal 26 does not change, the malfunction due to capacitive coupling is negligible. In the fourth period 54, since CLK2 and CLK3 become the H level, the potential of node B

[0067] rises in a short time. Also, CLK1 becomes the L level. As a result, the second transistor 102 and the fourth transistor 104 become the on state, and the potentials of the first output terminal 26 and the second output terminal 27 drop in a short time (see Fig. 4(A)). In the fifth period 55, by maintaining the fifth input terminal 25 (i.e., SROUT3) at the H level, the potential of node B is maintained. Therefore, the on states of the second transistor 102,

[0068] the fourth transistor 104, and the sixth transistor 106 are maintained, and the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level (see Fig. 4(B ). )).

[0069] In the sixth period 56, the fifth input terminal 25 (i.e., SROUT3) becomes the L level, and the eighth transistor 108 turns off. At this time, node B becomes a floating state while holding the above potential. As a result, the on states of the second transistor 102, the fourth transistor 104, and the sixth transistor 106 continue (see FIG. 4(C)). Note that the potential of node B normally decreases due to the off-current of the transistor or the like, but when a transistor with a sufficiently small off-current (for example, a transistor using an oxide semiconductor) is applied, such a problem does not occur, so the decrease in the potential of node B can be suppressed. In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized.

[0070] Note that the potential of node B normally decreases due to the off-current of the transistor or the like, but when a transistor with a sufficiently small off-current (for example, a transistor using an oxide semiconductor) is applied, such a problem does not occur, so the decrease in the potential of node B can be suppressed. In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized.

[0071] In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. In the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. It is possible. That is, by applying the configuration of the present embodiment, the potential of node A and the potential of node B can be maintained over a long period of time. Therefore, for example, malfunction can be prevented even when applied to a circuit with a low frequency. Even when applied to a circuit with a low frequency, malfunction can be prevented because the potential of node A and the potential of node B can be maintained over a long period of time.

[0072] In addition, in order to further mitigate the potential drop of node B, as shown in Fig. 5(A), a capacitive element 120 with one electrode electrically connected to node B may be provided separately. The other electrode of the capacitive element 120 may be electrically connected to, for example, the first power supply line 31. In addition, in order to further mitigate the potential drop of node B, as shown in Fig. 5(A), a capacitive element 120 with one electrode electrically connected to node B may be provided separately. The other electrode of the capacitive element 120 may be electrically connected to, for example, the first power supply line 31.

[0073] Also, as shown in Fig. 5(B), the potential drop of node B can be further mitigated by configuring the sixth transistor 106 or the tenth transistor 110 as a multi-gate transistor having at least two gates arranged in series. Note that Fig. 5(B) shows an example in which both the sixth transistor 106 and the tenth transistor 110 are multi-gate transistors, but only one of the sixth transistor 106 or the tenth transistor 110 may be a multi-gate transistor. Of course, the configuration shown in Fig. 5(A) and the configuration shown in Fig. 5(B) may be used in combination. Also, as shown in Fig. 5(B), the potential drop of node B can be further mitigated by configuring the sixth transistor 106 or the tenth transistor 110 as a multi-gate transistor having at least two gates arranged in series. Note that Fig. 5(B) shows an example in which both the sixth transistor 106 and the tenth transistor 110 are multi-gate transistors, but only one of the sixth transistor 106 or the tenth transistor 110 may be a multi-gate transistor. Of course, the configuration shown in Fig. 5(A) and the configuration shown in Fig. 5(B) may be used in combination. Also, as shown in Fig. 5(B), the potential drop of node B can be further mitigated by configuring the sixth transistor 106 or the tenth transistor 110 as a multi-gate transistor having at least two gates arranged in series. Note that Fig. 5(B) shows an example in which both the sixth transistor 106 and the tenth transistor 110 are multi-gate transistors, but only one of the sixth transistor 106 or the tenth transistor 110 may be a multi-gate transistor. Of course, the configuration shown in Fig. 5(A) and the configuration shown in Fig. 5(B) may be used in combination.

[0074] As shown in Fig. 5(B), by applying a multi-gate transistor, the redundancy of the transistor can be achieved, so that the yield of the pulse signal output circuit can be improved. As shown in Fig. 5(B), by applying a multi-gate transistor, the redundancy of the transistor can be achieved. Therefore, the yield of the pulse signal output circuit can be improved.

[0075] In addition, in a subsequent period, when both CLK2 and CLK3 are at the H level, the ninth transistor 109 and the eleventh transistor 111 are turned on, and node is periodically ​​A potential is applied to B. Therefore, even when a transistor with a relatively large off-current is used it is possible to prevent malfunction of the pulse signal output circuit.

[0076] Note that the shift register shown in this embodiment outputs a pulse from the m-th pulse signal output circuit and a drive method is adopted in which the pulse output from the (m + 1)-th pulse signal output circuit overlaps by half. Therefore, compared with the case where this drive method is not adopted, the time available for charging the wiring can be lengthened. That is, this drive method provides a pulse signal output circuit that can withstand a large load and operates at a high frequency.

[0077] (Embodiment 2) In this embodiment, a configuration example and its operation of a mode different from the pulse signal output circuit and the shift register shown in the previous embodiment will be described with reference to FIGS. 6 to 9. 〈Circuit configuration〉

[0078] First, a circuit configuration example of a pulse signal output circuit and a shift register including the pulse signal output circuit will be described with reference to FIG. 6.

[0079] The configuration of the shift register shown in this embodiment is approximated to the configuration of the shift register shown in the previous embodiment. One difference is that the first pulse signal output circuit 10 to the n-th _1 pulse signal output circuit 10 _n does not have a third input terminal 23 (see FIGS. 6(A) to 6(C)). That is, two types of clock signals are input to one pulse signal output circuit. The other configurations are the same as those in the previous embodiment.

[0080] ​​​​​​​The first pulse signal output circuit 10 _1 ~the nth pulse signal output circuit 10 _n does not have the third input terminal 23, and thus does not have the 11th transistor connected thereto (see Fig. 6(C ). Accordingly, the connection relationship within the second input signal generation circuit is partially changed .

[0081] A specific configuration example of the second input signal generation circuit is as follows.

[0082] The second terminal of the ninth transistor 109, the second terminal of the eighth transistor 108, and the first terminal of the tenth transistor 110 are electrically connected to function as the output terminal of the second input signal generation circuit.

[0083] The first terminal of the eighth transistor 108 and the first terminal of the ninth transistor 109 are given a second potential via the second power supply line 32. The second terminal of the tenth transistor 110 is given a first potential via the first power supply line 31. A pulse signal is input to the gate terminal of the eighth transistor 108. Also, the gate terminal of the eighth transistor 108 functions as the first input terminal of the second input signal generation circuit and also as the fifth input terminal 25 of the pulse signal output circuit. A second clock signal is input to the gate terminal of the ninth transistor 109. Also, the gate terminal of the ninth transistor 109 functions as the second input terminal of the second input signal generation circuit and also as the second input terminal 22 of the pulse signal output circuit. A pulse signal is input to the gate terminal of the tenth transistor 110. Also, the gate terminal of the tenth transistor 110 is the second ​​​​functions as the third input terminal of the input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit.

[0084] In the pulse signal output circuit shown in this embodiment, the channel length of the sixth transistor 106 is greater than the channel length of the third transistor 103 and the channel length of the fourth transistor 104. Also, the channel length of the tenth transistor 110 is greater than the channel length of the third transistor 103 and the channel length of the fourth transistor 104. As a result, the shift amount of the threshold voltages of the sixth transistor 106 and the tenth transistor 110 can be reduced, and deterioration can be suppressed.

[0085] Note that the above-described configuration is merely an example, and the disclosed invention is not limited thereto.

[0086] In the following description of this embodiment, as in the previous embodiment, in the pulse signal output circuit shown in FIG. 6(C), a node formed by connecting the gate terminal of the first transistor 101, the gate terminal of the third transistor 103, and the output terminal of the first input signal generation circuit is designated as node A. Also, a node formed by connecting the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, and the output terminal of the second input signal generation circuit is designated as node B.

[0087] A capacitive element may be provided between the node A and the first output terminal 26 to preferably perform a bootstrap operation. Also, a capacitive element electrically connected to the node B may be provided to hold the potential of the node B.

[0088] Note that it is preferable to use an oxide semiconductor for the first transistor 101 to the tenth transistor 110. By using an oxide semiconductor, the off-current of the transistor can be reduced. Also, compared with amorphous silicon or the like, the on-current and the field-effect mobility can be increased. Further, deterioration of the transistor can be suppressed. As a result, an electronic circuit with low power consumption, capable of high-speed operation, and enhanced operation accuracy can be realized. Note that the transistor using an oxide semiconductor will be described in detail in a later embodiment, and thus will be omitted here. It is preferable to use an oxide semiconductor. By using an oxide semiconductor, the off-current of the transistor can be reduced. Also, compared with amorphous silicon or the like, the on-current and the field-effect mobility can be increased. Further, deterioration of the transistor can be suppressed. As a result, an electronic circuit with low power consumption, capable of high-speed operation, and enhanced operation accuracy can be realized. Note that the transistor using an oxide semiconductor will be described in detail in a later embodiment, and thus will be omitted here.

[0089] <Operation> Next, the operation of the shift register shown in FIG. 6 will be described with reference to FIGS. 7 to 9. Specifically, the operations in each of the first period 51 to the fifth period 55 in the timing chart shown in FIG. 7 will be described using FIGS. 8 and 9. In the timing chart, CLK1 to CLK4 each indicate a clock signal, SP1 indicates a first start pulse, OUT 1 to OUT4 indicate the outputs from the second output terminals of the first pulse signal output circuit 10 to the fourth pulse signal output circuit 10 _1 _ _1

[0090] _4 _1 _4 to the fourth pulse signal output circuit 10, and the outputs from the first output terminals of the first pulse signal output circuit 10

[0090] Note that in the following description, it is assumed that the first transistor 101 to the tenth transistor 110 are all n-channel type transistors. Also, in FIGS. 8 and 9, it is assumed that all are n-channel type transistors. Also, in FIGS. 8 and 9, ​When a transistor is represented by a solid line, it indicates that the transistor is in a conducting state (on state ), and when it is represented by a dashed line, it indicates that the transistor is in a non-conducting state ( off state).

[0091] Typically, the operation of the first pulse signal output circuit 10 _1 will be described. The first pulse output circuit 10 _1 is configured as described above. Also, the relationship of each input signal and each supplied electric potential is as described above. In the following description, all high potentials (referred to as H level, H signal, etc.) applied to each input terminal and each power supply line are set to VDD, and all low potentials ( referred to as L level, L signal, etc.) are set to VSS.

[0092] In the first period 51, since SP1 is at the H level, the gate terminals of the fifth transistor 105, which functions as the fourth input terminal 24 of the first pulse output circuit 10 _1 , and the tenth transistor 110 are supplied with a high potential, and the fifth transistor 105 and the first tenth transistor 110 become conductive. Also, since the gate terminal of the seventh transistor 107 is supplied with a high potential, the seventh transistor 107 also becomes on (see Fig. 8 (A)). Since the fifth transistor 105 and the seventh transistor 107 are in the on state, the potential of node A rises. Also, since the tenth transistor 110 is in the on state, the potential of node B drops. Since the potential of the second terminal of the fifth transistor 105 is VDD

[0093] , the potential of the first terminal of the fifth transistor 105 is from the potential of the second terminal minus the potential of the first terminal of the fifth transistor 105 is from the potential of the second terminal minus the potential of the first terminal of the fifth transistor 105 is from the potential of the second terminal minus the potential of the first terminal of the fifth transistor 105 is from the potential of the second terminal minus the It becomes a value (VDD - Vth105) that is lower by the threshold voltage of the fifth transistor 105 by 5. And since the potential of the gate terminal of the seventh transistor 107 is VDD, when the threshold voltage Vth107 of the seventh transistor 107 is equal to or higher than Vth105, the potential of node A becomes (VDD - Vth107) and the seventh transistor 107 turns off. On the other hand, when Vth107 is less than Vth105, the seventh transistor 107 remains in the on state, and the potential of node A rises to (VDD - Vth105). Hereinafter, the arrival point of the potential of node A in the first period 51 is defined as V . When the potential of node A reaches V AH , AH to When it reaches, the fifth transistor 105 and the seventh transistor 107 turn off, and node A becomes a floating state while maintaining V . AH

[0094] When the potential of node A becomes V AH , the first transistor 101 and the third transistor 103 turn on. Here, since CLK1 is at the L level, an L level is output from the first output terminal 26 and the second output terminal 27.

[0095] In the second period 52, CLK1 switches from the L level to the H level. Here, since the first transistor 101 and the third transistor 103 are on, the potential of the first output terminal 26 and the potential of the second output terminal 27 rise. Further, there is a capacitance between the gate terminal and the source terminal (or drain terminal) of the first transistor 101, and due to this, the gate terminal and the source terminal (or drain terminal) are capacitively coupled. Similarly, Similarly, there is a capacitance between the gate terminal and the source terminal (or drain terminal) of the third transistor 103, whereby the gate terminal and the source terminal (or drain terminal) are capacitively coupled. Therefore, as the potential of the first output terminal 26 and the potential of the second output terminal 27 increase, the potential of the floating node A will increase (bootstrapping operation). The potential of node A will finally become higher than VDD + Vth101, and the potential of the first output terminal 26 and the potential of the second output terminal 27 will become VDD (H level) (see FIGS. 7 and 8(B)). In the third period 53, CLK2 becomes the H level, and the ninth transistor 109 becomes on. As a result, the potential of node B increases. Due to the increase in the potential of node B, the second transistor 102, the fourth transistor 104, and the sixth transistor 10

[0096] 6 turn on, and the potential of node A decreases. For this reason, the potential of the first output terminal 26 and the potential of the second output terminal 27 become the L level (see FIG. 8(C)). In the fourth period 54, CLK2 becomes the L level, and the ninth transistor 109 becomes off. However, since the fifth input terminal 25 (i.e., SROUT3) becomes the H level, the eighth transistor 108 turns on. For this reason, the potential of node A and the potential of node B are held, and the potential of the first output terminal 26 and the potential of the second output terminal 27 are held at the L level (see FIG. 9(A)).

[0097] In the fifth period 55, the fifth input terminal 25 (i.e., SROUT3) becomes the L level but the eighth transistor 108 turns on because the fifth input terminal 25 (i.e., SROUT3) becomes the H level. For this reason, the potential of node A and the potential of node B are held, and the potential of the first output terminal 26 and the potential of the second output terminal 27 are held at the L level (see FIG. 9(A)). are held, and the potential of the first output terminal 26 and the potential of the second output terminal 27 are held at the L level (see FIG. 9(A)). In the fifth period 55, the fifth input terminal 25 (i.e., SROUT3) becomes the L level

[0098] and the eighth transistor 108 turns off because the fifth input terminal 25 (i.e., SROUT3) becomes the L level. Thus, the potential of node B is held. For this reason, the on-states of the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are held, and the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level (see Fig. 9(B)). The potential of node B normally drops due to the off-current of the transistor or the like, but when a transistor with a sufficiently small off-current (for example, a transistor using an oxide semiconductor) is applied, such a problem does not occur. Also, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (when the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency

[0099] Moreover, the potential of node B is normally lowered due to the off-current of the transistor or the like. However, when a transistor with a sufficiently small off-current (for example, a transistor using an oxide semiconductor) is applied, such a problem does not occur. When a transistor with a sufficiently small off-current (for example, a transistor using an oxide semiconductor) is applied, such a problem does not occur. such a problem does not occur.

[0100] In addition, a transistor using a wide-gap semiconductor such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (when the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (when the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency such as an oxide semiconductor cannot apply threshold control by doping like a transistor using silicon. Therefore, even when no bias is applied to the gate (when the gate and the source are at the same potential), a current may flow between the source and the drain. However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency However, in the pulse signal output circuit shown in this embodiment, by making the channel length of the tenth transistor 110 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node B can be suppressed, so that the potential of node B can be stably held. Furthermore, by making the channel length of the sixth transistor 106 larger than the channel lengths of the third transistor 103 and the fourth transistor 104, the leakage of current from node A can be suppressed, so that the bootstrap operation at node A can be stabilized. That is, by applying the configuration of this embodiment, the potentials of node A and node B can be held over a long period of time. Therefore, for example, in a circuit with a low frequency It is also possible to prevent malfunction even when applied.

[0101] In addition, in order to further mitigate the potential drop at Node B, as shown in Fig. 10(A), a capacitive element 120 with one electrode electrically connected to Node B may be provided separately. The other electrode of the capacitive element 120 may be electrically connected to, for example, the first power line 31.

[0102] Also, as shown in Fig. 10(B), the sixth transistor 106 or the tenth transistor 110 can be configured as a multi-gate transistor having at least two gates arranged in series to further mitigate the potential drop at Node B. Note that in Fig. 10(B ), an example is shown where both the sixth transistor 106 and the tenth transistor 110 are multi-gate transistors, but only one of the sixth transistor 106 or the tenth transistor 110 may be a multi-gate transistor. Of course, the configuration shown in Fig. 10( A) and the configuration shown in Fig. 10(B) may be used in combination.

[0103] As shown in Fig. 10(B), by applying a multi-gate transistor, redundancy of the transistor can be achieved, thus improving the yield of the pulse signal output circuit.

[0104] Note that in a subsequent period, when CLK2 is at the high level, the ninth transistor 109 is turned on, and a potential is periodically applied to Node B. Therefore, even when using a transistor with a relatively large off-current, malfunction of the pulse signal output circuit can be prevented.

[0105] ​​​As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments. It can be used in appropriate combination with those shown in other embodiments.

[0106] (Embodiment 3) In this embodiment, an example of a transistor applicable to the pulse signal output circuit and the shift register described in the above embodiment will be described with reference to FIG. 11. Note that the structure of the transistor is not particularly limited, and for example, an appropriate structure such as a top gate structure or a bottom gate structure, a staggered type or a planar type can be adopted. Also, the transistor may have a single gate structure having one channel formation region or a multi-gate structure having two or more channel formation regions. Further, a structure having two gate electrode layers disposed via a gate insulating layer above and below the channel region may also be used. Examples of transistors applicable to the pulse signal output circuit and the shift register described in the above embodiment will be described with reference to FIG. 11. Note that the structure of the transistor is not particularly limited, and for example, an appropriate structure such as a top gate structure or a bottom gate structure, a staggered type or a planar type can be adopted. Also, the transistor may have a single gate structure having one channel formation region or a multi-gate structure having two or more channel formation regions. Further, a structure having two gate electrode layers disposed via a gate insulating layer above and below the channel region may also be used. is not particularly limited, and for example, an appropriate structure such as a top gate structure or a bottom gate structure, a staggered type or a planar type can be adopted. Also, the transistor may have a single gate structure having one channel formation region or a multi-gate structure having two or more channel formation regions. Further, a structure having two gate electrode layers disposed via a gate insulating layer above and below the channel region may also be used. is not particularly limited, and for example, an appropriate structure such as a top gate structure or a bottom gate structure, a staggered type or a planar type can be adopted. Also, the transistor may have a single gate structure having one channel formation region or a multi-gate structure having two or more channel formation regions. Further, a structure having two gate electrode layers disposed via a gate insulating layer above and below the channel region may also be used. is not particularly limited, and for example, an appropriate structure such as a top gate structure or a bottom gate structure, a staggered type or a planar type can be adopted. Also, the transistor may have a single gate structure having one channel formation region or a multi-gate structure having two or more channel formation regions. Further, a structure having two gate electrode layers disposed via a gate insulating layer above and below the channel region may also be used. is not particularly limited, and for example, an appropriate structure such as a top gate structure or a bottom gate structure, a staggered type or a planar type can be adopted. Also, the transistor may have a single gate structure having one channel formation region or a multi-gate structure having two or more channel formation regions. Further, a structure having two gate electrode layers disposed via a gate insulating layer above and below the channel region may also be used. is not particularly limited, and for example, an appropriate structure such as a top gate structure or a bottom gate structure, a staggered type or a planar type can be adopted. Also, the transistor may have a single gate structure having one channel formation region or a multi-gate structure having two or more channel formation regions. Further, a structure having two gate electrode layers disposed via a gate insulating layer above and below the channel region may also be used.

[0107] FIGS. 11(A) to 11(D) show examples of the cross-sectional structure of the transistor. The transistor shown in FIGS. 11(A) to 11(D) uses an oxide semiconductor as the semiconductor. The merits of using an oxide semiconductor are that a high mobility and a low off-current can be realized with a simple process and a low-temperature process. The merits of using an oxide semiconductor are that a high mobility and a low off-current can be realized with a simple process and a low-temperature process. The merits of using an oxide semiconductor are that a high mobility and a low off-current can be realized with a simple process and a low-temperature process.

[0108] The transistor 410 shown in FIG. 11(A) is an example of a transistor having a bottom gate structure, and is also called an inverse staggered transistor. The transistor 410 shown in FIG. 11(A) is an example of a transistor having a bottom gate structure, and is also called an inverse staggered transistor.

[0109] The transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Also, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. The transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Also, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. The transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Also, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. A protective insulating layer 409 is further formed on the layer 407.

[0110] The transistor 420 shown in FIG. 11(B) is an example of a transistor with a bottom gate structure called a channel protection type (also referred to as a channel stop type), and is also called an inverse staggered transistor. The transistor 420 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, an insulating layer 427 that functions as a channel protection layer, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Also, a protective insulating layer 409 is provided.

[0111] The transistor 420 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, an insulating layer 427 that functions as a channel protection layer, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Also, a protective insulating layer 409 is provided. The transistor 420 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, an insulating layer 427 that functions as a channel protection layer, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Also, a protective insulating layer 409 is provided. The transistor 420 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, an insulating layer 427 that functions as a channel protection layer, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Also, a protective insulating layer 409 is provided. The transistor 420 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, an insulating layer 427 that functions as a channel protection layer, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. Also, a protective insulating layer 409 is provided.

[0112] The transistor 430 shown in FIG. 11(C) is an example of a bottom gate type transistor. The transistor 430 includes a gate electrode layer 401, a gate insulating layer 402, a source electrode layer 405a, a drain electrode layer 405b, and an oxide semiconductor layer 403 on a substrate 400 having an insulating surface. Also, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. A protective insulating layer 409 is further formed on the insulating layer 407. The transistor 430 includes a gate electrode layer 401, a gate insulating layer 402, a source electrode layer 405a, a drain electrode layer 405b, and an oxide semiconductor layer 403 on a substrate 400 having an insulating surface. Also, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. A protective insulating layer 409 is further formed on the insulating layer 407. The transistor 430 includes a gate electrode layer 401, a gate insulating layer 402, a source electrode layer 405a, a drain electrode layer 405b, and an oxide semiconductor layer 403 on a substrate 400 having an insulating surface. Also, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. A protective insulating layer 409 is further formed on the insulating layer 407. A protective insulating layer 409 is further formed on the insulating layer 407.

[0113] In the transistor 430, the gate insulating layer 402 is provided in contact with the substrate 400 and the gate electrode layer 401, and the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the gate insulating layer 402. Then, the oxide semiconductor layer 403 is provided on the gate insulating layer 402, the source electrode layer 405a, and the drain electrode layer 405b. In the transistor 430, the gate insulating layer 402 is provided in contact with the substrate 400 and the gate electrode layer 401, and the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the gate insulating layer 402. Then, the oxide semiconductor layer 403 is provided on the gate insulating layer 402, the source electrode layer 405a, and the drain electrode layer 405b. In the transistor 430, the gate insulating layer 402 is provided in contact with the substrate 400 and the gate electrode layer 401, and the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the gate insulating layer 402. Then, the oxide semiconductor layer 403 is provided on the gate insulating layer 402, the source electrode layer 405a, and the drain electrode layer 405b. In the transistor 430, the gate insulating layer 402 is provided in contact with the substrate 400 and the gate electrode layer 401, and the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the gate insulating layer 402. Then, the oxide semiconductor layer 403 is provided on the gate insulating layer 402, the source electrode layer 405a, and the drain electrode layer 405b.

[0114] The transistor 440 shown in FIG. 11(D) is an example of a transistor with a top gate structure. ​It is. The transistor 440 is on a substrate 400 having an insulating surface, with an insulating layer 437, an oxide semi- conductor layer 403, a source electrode layer 405a, a drain electrode layer 405b, a gate insulating layer 402, and a gate electrode layer 401. And wiring layers 436a and 436b are respectively provided in contact with the source electrode layer 405a and the drain electrode layer 405 b.

[0115] In this embodiment, as described above, an oxide semiconductor layer 403 is used as the semiconductor layer. As the oxide semiconductor used for the oxide semiconductor layer 403, there are quaternary metal oxides such as In-Sn- Ga-Zn-O, ternary metal oxides such as In-Ga-Zn-O, In-Sn-Z n-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O , Sn-Al-Zn-O, binary metal oxides such as In-Zn-O, Sn-Zn- O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, Zn-O, etc. Also, SiO2 may be added to the above oxide semiconductor. Here, for example, an In-Ga-Zn-O-based oxide semiconductor is an oxide containing at least In, Ga, and Zn, and there is no particular limitation on its composition ratio. Also, elements other than In, G a, and Zn may be included.

[0116] Also, for the oxide semiconductor layer 403, an oxide semiconductor represented by the chemical formula InMO3(ZnO) m (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, G a and Mn, or Ga and Co, etc.

[0117] Transistors 410, 420, and transistors 430 and 440 can have an extremely small off-current. Therefore, , by using these in a pulse signal output circuit or a shift register, the potential holding of each node becomes easy, and the probability of malfunction of the pulse signal output circuit or the shift register can be extremely low suppressed.

[0118] There are no major restrictions on the substrate that can be used for the substrate 400 having an insulating surface. For example, a glass substrate used in a liquid crystal display device or the like, a quartz substrate, or the like can be used. Also , a substrate having an insulating layer formed on a silicon wafer may be used.

[0119] In transistors 410, 420, and 430 having a bottom gate structure, an underlying insulating layer may be provided between the substrate and the gate electrode layer. The insulating layer has a function of preventing the diffusion of impurity elements from the substrate and can be formed by one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film.

[0120] The gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum neodymium, copper, neodymium, scandium, or an alloy material having these as the main components . Also, its structure may be a single-layer structure or a laminated structure .

[0121] The gate insulating layer 402 can be formed into a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a nitride An aluminum film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film It can be formed by one or more films selected from the like. For example, as the first gate insu lation layer, a silicon nitride film ( SiN y (y>0)) with a film thickness of 50 nm or more and 200 nm or less is formed by plasma CVD method on the first gate insulation layer, and as the second gate insulation layer on the first gate insulation layer, a silicon oxide film (SiO (x>0)) with a film thickness of 5 nm or more and 300 nm or less is formed by sputtering method, and a gate insulation layer with a total film thickness of about 300 nm can be obtained. x (x>0)) is formed.

[0122] The source electrode layer 405a and the drain electrode layer 405b can be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these. For example, a laminated structure with a metal layer such as aluminum or copper and a high melting point metal layer such as titanium, molybdenum, or tungsten can be formed. By using an aluminum material added with an element (such as silicon, neodymium, scandium, etc.) that prevents the generation of hillocks and whiskers, the heat resistance can be improved as well.

[0123] In addition, a conductive metal oxide film may be used as the conductive film that becomes the source electrode layer 405a and the drain electrode layer 405b (including the wiring layer formed of the same layer). As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium tin oxide alloy (In2O3―SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3―ZnO), or these metal oxide materials ) can be used. ) Those containing silicon oxide, etc. can be used.

[0124] For the wiring layer 436a and the wiring layer 436b in contact with the source electrode layer 405a and the drain electrode layer 405b, the same materials as those of the source electrode layer 405a and the drain electrode layer 405b can be used for formation. For the wiring layer 436a and the wiring layer 436b in contact with the source electrode layer 405a and the drain electrode layer 405b, the same materials as those of the source electrode layer 405a and the drain electrode layer 405b can be used for formation. It can be formed.

[0125] As the insulating layer 407, the insulating layer 427, and the insulating layer 437, typically, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, or an aluminum oxynitride film can be used. As the insulating layer 407, the insulating layer 427, and the insulating layer 437, typically, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, or an aluminum oxynitride film can be used. It can be used.

[0126] As the protective insulating layer 409, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film can be used. As the protective insulating layer 409, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film can be used.

[0127] Further, a planarizing insulating film for reducing surface irregularities caused by transistors may be formed on the protective insulating layer 409. As the planarizing insulating film, an organic material such as polyimide, acrylic, or benzocyclobutene can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), etc. can be used. Note that a planarizing insulating film may be formed by laminating a plurality of insulating films formed of these materials. Further, a planarizing insulating film for reducing surface irregularities caused by transistors may be formed on the protective insulating layer 409. As the planarizing insulating film, an organic material such as polyimide, acrylic, or benzocyclobutene can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), etc. can be used. Note that a planarizing insulating film may be formed by laminating a plurality of insulating films formed of these materials. Further, a planarizing insulating film for reducing surface irregularities caused by transistors may be formed on the protective insulating layer 409. As the planarizing insulating film, an organic material such as polyimide, acrylic, or benzocyclobutene can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), etc. can be used. Note that a planarizing insulating film may be formed by laminating a plurality of insulating films formed of these materials. Further, a planarizing insulating film for reducing surface irregularities caused by transistors may be formed on the protective insulating layer 409. As the planarizing insulating film, an organic material such as polyimide, acrylic, or benzocyclobutene can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), etc. can be used. Note that a planarizing insulating film may be formed by laminating a plurality of insulating films formed of these materials. It can be formed by laminating a plurality of insulating films formed of these materials.

[0128] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0129] (Embodiment 4) In this embodiment, an example of a transistor including an oxide semiconductor layer and a method for manufacturing the same will be described in detail with reference to FIG. 12. In this embodiment, an example of a transistor including an oxide semiconductor layer and a method for manufacturing the same will be described in detail with reference to FIG. 12.

[0130] FIGS. 12(A) to 12(E) are cross-sectional views showing a manufacturing process of a transistor. Note that the transistor 510 shown here is the same reverse stagger type transistor as the transistor 410 shown in FIG. 11(A).

[0131] The oxide semiconductor used for the semiconductor layer of the present embodiment is obtained by removing hydrogen, which is an n-type impurity, from the oxide semiconductor and purifying it to a high purity so that impurities other than the main component of the oxide semiconductor are not contained as much as possible. Thus, it is an i-type (intrinsic) oxide semiconductor or an oxide semiconductor that is extremely close to the i-type (intrinsic).

[0132] Note that in the highly purified oxide semiconductor, carriers are extremely few, and the carrier concentration is less than 1× 10 14 / cm 3 , preferably less than 1×10 12 / cm 3 , more preferably less than 1×1 0 11 / cm 3 . Also, due to the small number of carriers, the current (off-current) in the off state becomes sufficiently small.

[0133] Specifically, in the transistor including the above-described oxide semiconductor layer, at room temperature (25° C.), the off-current density per 1 μm of channel width is 100 zA / μm (1 ×10 A / μm) or less, and further 10 zA / μm (1×10 ×10 -19 A / μm) or less -20 under the condition that the channel length L of the transistor is 10 μm and the voltage between the source and drain of the transistor is 3V. It is possible to make it.

[0134] Also, the transistor 510 including the highly purified oxide semiconductor layer has the temperature of the on-current ​​​​​There is almost no dependency, and the off-current remains very small.

[0135] Hereinafter, a process of manufacturing the transistor 510 on the substrate 505 will be described with reference to FIGS. 12(A) to 12(E). The process will be described.

[0136] First, after forming a conductive film on the substrate 505 having an insulating surface, a gate electrode layer 511 is formed by a first photolithography process. Note that the resist mask used in the photolithography process may be formed by an inkjet method. Forming the resist mask by the inkjet method does not require the use of a photomask, so the manufacturing cost can be reduced.

[0137] As the substrate 505 having an insulating surface, the same substrate as the substrate 400 in the above embodiment can be used. In this embodiment, a glass substrate is used as the substrate 505.

[0138] Note that an underlying insulating layer may be provided between the substrate 505 and the gate electrode layer 511. The insulating layer has a function of preventing the diffusion of impurity elements from the substrate 505, and is a silicon nitride film, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or the like, and can be formed by one or a plurality of films selected therefrom.

[0139] Also, the gate electrode layer 511 can be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material having these as main components. Further, its structure may be a single-layer structure or a stacked layer structure.

[0140] Next, a gate insulating layer 507 is formed on the gate electrode layer 511. The gate insulating layer 507 , it can be formed by using a plasma CVD method, a sputtering method, or the like. Further, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film , an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, or the like can be formed by one or more films selected therefrom.

[0141] Note that in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the gate insulating layer 507 and the oxide semiconductor film 530, as a pretreatment for forming the oxide semiconductor film 530, a substrate 505 on which the gate electrode layer 511 is formed in the preheating chamber of a sputtering apparatus, or a substrate 505 on which up to the gate insulating layer 507 is formed is preheated to desorb impurities such as hydrogen and moisture adsorbed on the substrate 505. Further, the exhaust means provided in the preheating chamber is preferably a cryopump. Also, the preheating may be performed on the substrate 505 on which the source electrode layer 515a and the drain electrode layer 515b are formed. Note that this preheating treatment can be omitted.

[0142]

[0143] Next, an oxide semiconductor film 530 having a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less, is formed on the gate insulating layer 507 (see FIG. 12(A)).

[0144] For the oxide semiconductor film 530, the quaternary metal oxide, ternary metal oxide, binary metal oxide, In - O system, Sn - O system, Zn - O system, etc. shown in the above embodiments can be used. .

[0144] As a target for producing the oxide semiconductor film 530 by a sputtering method, in particular, In: Those represented by a composition ratio of Ga:Zn = 1:x:y (where x is 0 or more and y is 0.5 or more and 5 or less) are preferably used. For example, a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio] can be used. Also, a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio], a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:4 [mole ratio], or a target having a composition ratio of In2O3:ZnO = 1:2 [mole ratio] can be used.

[0145] In this embodiment, the oxide semiconductor layer having an amorphous structure is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target.

[0146] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more, and more preferably 99.9% or more. By using a metal oxide target having a high relative density, it is possible to form an oxide semiconductor layer having a dense structure.

[0147] The formation atmosphere of the oxide semiconductor film 530 is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of 1 ppm or less (desirably 10 ppb or less).

[0148] When forming the oxide semiconductor film 530, for example, the object to be processed is placed in a processing chamber maintained in a reduced pressure state. ​​​​​​​​​​​​Hold an object and heat the object to be processed so that the temperature of the object to be processed is 100 °C or higher and lower than 550 °C, preferably 200 °C or higher and 4 0 °C or lower. Alternatively, the temperature of the object to be processed during the formation of the oxide semiconductor film 530 may be room temperature (25 °C ± 10 °C). Then, while removing moisture in the processing chamber, introduce a sputtering gas from which hydrogen, water, etc. have been removed, and form an oxide semiconductor film 530 using the above target. By forming the oxide semiconductor film 530 while heating the object to be processed, the impurities contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering can be reduced. To remove moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. Also, damage due to sputtering can be reduced. To remove moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced.

[0149] As the formation conditions of the oxide semiconductor film 530, for example, the distance between the object to be processed and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, the atmosphere is an oxygen (oxygen 100%) atmosphere, or an argon (argon 100%) atmosphere, or a mixed atmosphere of oxygen and argon, and the like can be applied. When a pulsed direct current (DC) power supply is used, powdery substances (also called particles, dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. The thickness of the oxide semiconductor film 530 is 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 10 nm or less. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor film 530 can be reduced. By using an oxide semiconductor film 530 with such a thickness, the short-channel effect associated with miniaturization can be suppressed. However, since the appropriate thickness varies depending on the oxide semiconductor material to be applied, the use of the semiconductor device, etc., the thickness can be selected according to the material used, the application, etc.

[0150] Before forming the oxide semiconductor film 530 by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove deposits on the formation surface (e.g., the surface of the gate insulating layer 507). Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, which is the opposite of the normal sputtering method where ions are collided with the sputtering target. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the object to be processed. Note that an atmosphere of nitrogen, helium, oxygen, etc. may be applied instead of the argon atmosphere.

[0151] Next, the oxide semiconductor film 530 is processed into island-shaped oxide semiconductor layers by a second photolithography process. Note that the resist mask used in the photolithography process may be formed by the ink jet method. When the resist mask is formed by the ink jet method, since a photomask is not used, the manufacturing cost can be reduced.

[0152] When forming a contact hole in the gate insulating layer 507, the process can be performed simultaneously with the processing of the oxide semiconductor film 530.

[0153] ​​​​​​The etching of the oxide semiconductor film 530 may be dry etching, wet etching, or both may be used. For example, as the etching solution for wet etching of the oxide semiconductor film 530, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used. After that, the oxide semiconductor layer is subjected to a heat treatment (first heat treatment) to obtain the oxide semiconductor layer 531 (see Fig. 12(B)). By this first heat treatment, excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor layer is removed, the structure of the oxide semiconductor layer is adjusted, and the defect levels in the energy gap can be reduced. The temperature of the first heat treatment is, for example, 300°C or higher and less than 550°C, or 400°C or higher and 500°C or lower. The heat treatment can be performed, for example, by introducing the object to be treated into an electric furnace using a resistance heating element or the like, and under a nitrogen atmosphere, at 450°C for 1 hour. During this time, the oxide semiconductor layer is not allowed to come into contact with the atmosphere to prevent the mixing of water and hydrogen.

[0154] The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp,

[0155] The heat treatment can be performed, for example, by introducing the object to be treated into an electric furnace using a resistance heating element or the like, and under a nitrogen atmosphere, at 450°C for 1 hour. During this time, the oxide semiconductor layer is not allowed to come into contact with the atmosphere to prevent the mixing of water and hydrogen. The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp,

[0156] The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, An apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a lamp . The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas. As the gas, noble gases such as argon, or an inert gas such as nitrogen that does not react with the object to be processed by heat treatment is used.

[0157] For example, as the first heat treatment, the object to be processed may be put into a heated inert gas atmosphere, heated for several minutes , and then a GRTA treatment may be performed to take out the object to be processed from the inert gas atmosphere. Using the GRTA treatment enables high-temperature heat treatment in a short time. Also, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the object to be processed. During the process, the inert gas may be switched to a gas containing oxygen. By performing the first heat treatment in an atmosphere containing oxygen, it is possible to reduce the defect levels in the energy gap caused by oxygen deficiency. This is because .

[0158] Note that as the inert gas atmosphere, an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc. ) and containing no water, hydrogen, etc. is preferably applied. For example, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). In any case, by reducing impurities by the first heat treatment and forming an i-type (intrinsic) semiconductor or an oxide semiconductor layer extremely close to the i-type,

[0159] a transistor with extremely excellent characteristics can be realized.

[0160] By the way, since the above heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc., this heat treatment can also be referred to as a dehydration treatment, a dehydrogenation treatment, etc. This dehydration treatment and the dehydrogenation treatment can also be performed after the formation of the oxide semiconductor film 530 and before processing into an island-shaped oxide semiconductor layer . Also, such dehydration treatment and dehydrogenation treatment may be performed not once but a plurality of times.

[0161] In addition to the above, the first heat treatment can be performed at timings such as after forming the source electrode layer and the drain electrode layer and after forming an insulating layer on the source electrode layer and the drain electrode layer.

[0162] Next, a conductive film that will become the source electrode layer and the drain electrode layer (including wiring formed of the same layer) is formed on the gate insulating layer 507 and the oxide semiconductor layer 531. As the conductive film used for the source electrode layer and the drain electrode layer, the materials shown in the above embodiment can be used.

[0163] A resist mask is formed on the conductive film by the third photolithography process, and selective etching is performed to form the source electrode layer 515a and the drain electrode layer 515b, and then the resist mask is removed (see FIG. 12(C)).

[0164] For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light may be used. Note that the channel length (L) of the transistor is determined by the distance between the source electrode layer and the drain electrode layer. Therefore, for the exposure during the formation of the mask used for manufacturing a transistor with a channel length (L) of less than 25 nm, several nm to several tens of n m m may be used. It is desirable to use m and extreme ultraviolet rays with a short wavelength. Exposure with extreme ultraviolet rays has high resolution and a large depth of focus. Therefore, the channel length (L) of the transistor to be formed later can be set to 10 nm or more and 1000 nm (1 μm) or less, which makes it possible to increase the operating speed of the circuit. Also, miniaturization can reduce the power consumption of the semiconductor device.

[0165] In addition, in order to reduce the number of photomasks and the number of processes used in the photolithography process, the etching process may be performed using a resist mask formed by a multi-tone mask. The resist mask formed using a multi-tone mask has regions with different thicknesses, and since the shape can be further deformed by performing etching, it can be used in a plurality of etching processes for processing different patterns. Therefore, a resist mask corresponding to at least two or more different patterns can be formed using a single multi-tone mask. As a result, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, enabling the simplification of the process.

[0166] Note that when etching the conductive film, it is desirable to optimize the etching conditions so that the oxide semiconductor layer 531 is not divided by etching. However, it is difficult to obtain a condition where only the conductive film is etched and the oxide semiconductor layer 531 is not etched at all. During the etching of the conductive film, a part of the oxide semiconductor layer 531 may be etched to form grooves (recesses).

[0167] For the etching of the conductive film, either wet etching or dry etching may be used. From the perspective of device miniaturization, it is preferable to use dry etching. For the etching gas and etching solution, they can be appropriately selected according to the material to be etched. In this embodiment, since a titanium film is used as the conductive film and an In-Ga-Zn-O-based material is used for the oxide semiconductor layer 531, for example, when applying wet etching, aqueous hydrogen peroxide ammonia (a mixed solution of ammonia, water, and hydrogen peroxide solution) can be used as the etchant.

[0168] Next, plasma treatment using a gas such as N2O, N2, or Ar is performed to remove hydrogen, water, etc. attached to the surface of the exposed oxide semiconductor layer. When performing such plasma treatment, after the treatment, under conditions where it does not come into contact with the atmosphere, an insulating layer 516 that serves as a protective insulating film is formed.

[0169] The insulating layer 516 should have a film thickness of at least 1 nm or more, and it is desirable to form it using a method such as sputtering that does not mix impurities such as water and hydrogen into the insulating layer 516. If hydrogen is contained in the insulating layer 516, the intrusion of hydrogen into the oxide semiconductor layer and the extraction of oxygen in the oxide semiconductor layer by hydrogen may occur, resulting in a decrease in the back channel resistance of the oxide semiconductor layer (n-type conversion) and the possible formation of a parasitic channel. Also, for the insulating layer 516, it is

[0170] preferable to use a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, It is formed using [specific method]. The substrate temperature during film formation may be from room temperature (25°C) to 300°C, and in this embodiment, it is 100°C. Film formation of the silicon oxide film by sputtering can be carried out in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of an inert gas and oxygen. Also, a silicon oxide target or a silicon target can be used as the target.

[0171] Similar to the film formation of the oxide semiconductor film 530, in order to remove residual moisture in the film formation chamber of the insulating layer 516, it is preferable to use an adsorption-type vacuum pump (such as a cryopump). By forming a film in a film formation chamber evacuated using a cryopump, the concentration of impurities contained in the insulating layer 516 can be reduced. Also, as an evacuation step for removing residual moisture in the film formation chamber of the insulating layer 516, a turbo molecular pump with a cold trap added may be used.

[0172] The sputtering gas used for the film formation of the insulating layer 516 is desirably a high-purity gas from which impurities such as hydrogen and water have been removed.

[0173] Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is from 200°C to 450°C, preferably from 250°C to 350°C. For example, a heat treatment at 250°C for 1 hour in a nitrogen atmosphere may be performed. By performing the second heat treatment, the variation in the electrical characteristics of the transistor can be reduced. Also, by supplying oxygen from the insulating layer 516 to the oxide semiconductor layer 531, the oxygen deficiency in the oxide semiconductor layer 531 can be compensated to form an i-type (intrinsic) semiconductor or an oxide semiconductor layer that is extremely close to the i-type.

[0174] In this embodiment, a second heat treatment is performed after the formation of the insulating layer 516. However, the timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed following the first heat treatment, or the first heat treatment may also serve as the second heat treatment.

[0175] As described above, by the first heat treatment and the second heat treatment, the oxide semiconductor layer 531 can be made highly pure and i-type (intrinsic) with as few impurities as possible other than its main components. This can be achieved.

[0176] The transistor 510 is formed through the above steps (see FIG. 12(D)).

[0177] It is desirable to further form a protective insulating layer 506 on the insulating layer 516 (see FIG. 12( E)). The protective insulating layer 506 prevents intrusion from the outside, such as hydrogen and water. As the protective insulating layer 506, for example, a silicon nitride film, an aluminum nitride film, or the like can be used. The film formation method is not particularly limited, but the RF sputtering method is suitable as the film formation method for the protective insulating layer 506 because of its good mass productivity.

[0178] After the formation of the protective insulating layer 506, further heat treatment may be performed under the conditions of 100°C or higher and 200°C or lower in the atmosphere for 1 hour or more and 30 hours or less.

[0179] As described above, the transistor including the highly purified oxide semiconductor layer fabricated using this embodiment has the characteristic that its off-current is extremely small. Therefore, by using this, it becomes easy to hold the potential of the node. Thus, when used in a pulse signal output circuit or a shift register, etc., ​​By using it in a register, the probability of malfunction in a pulse signal output circuit or a shift register can be extremely reduced to a very low level.

[0180] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined and used with those shown in other embodiments.

[0181] (Embodiment 5) Using the shift register exemplified in the above Embodiment 1 or Embodiment 2, a semiconductor device (also referred to as a display device) having a display function can be manufactured. Further, a part or all of the drive circuit can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0182] As the display element used in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be applied. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. Further, a display medium such as electronic ink, whose contrast changes by an electric action, can also be applied.

[0183] In FIG. 13(A), a sealing material 4005 is provided so as to surround a pixel portion 4002 provided on a first substrate 4001, and is sealed by a second substrate 4006. In FIG. 13(A), a scanning line drive circuit 4004 and a signal line drive circuit 4003 are mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Further, a separately formed signal line drive circuit 4003 and a scanning line drive The various signals and potentials supplied to the circuit 4004 or the pixel section 4002 are supplied from FPC (Flex ible printed circuit) 4018a and 4018b.

[0184] In FIGS. 13(B) and 13(C), a sealing material 4005 is provided so as to surround the pixel section 40 02 provided on the first substrate 4001 and the scanning line driving circuit 4004. Further, a second substrate 4006 is provided on the pixel section 4002 and the scanning line driving circuit 4004. Therefore, the pixel section 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001 , the sealing material 4005, and the second substrate 4006. In FIGS. 13(B) and 13(C), a signal line driving circuit 40 03 is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. In FIGS. 13(B) and 13(C), the various signals and potentials supplied to the separately formed signal line driving circuit 4003 and the scanning line driving circuit 4004 or the pixel section 4002 are supplied from the FPC 4018.

[0185] Also, in FIGS. 13(B) and 13(C), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0186] Note that the connection method of the separately formed driving circuit is not particularly limited, and COG (Ch ip On Glass) method, wire bonding method, or TAB (Tape A​​ Methods such as automated bonding can be used. Figure 13(A) is an example of implementing the signal line driving circuit 4003 and the scanning line driving circuit 4004 by the COG method ; Figure 13(B) is an example of implementing the signal line driving circuit 4003 by the COG method; Figure 1 3(C) is an example of implementing the signal line driving circuit 4003 by the TAB method.

[0187] Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel.

[0188] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a module with a connector, such as an FPC or a TAB tape or a TCP attached, a module with a printed wiring board provided at the tip of the TAB tape or TCP, or a module with an IC (integrated circuit) directly mounted on the display element by the COG method are all included in the display device.

[0189] Also, the pixel portion provided on the first substrate has a plurality of transistors, and as the transistors, the transistors exemplified in the previous embodiments may be applied.

[0190] When using a liquid crystal element as the display element, thermotropic liquid crystals, low molecular liquid crystals, high molecular liquid crystals, polymer dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. are used. These liquid crystal materials show, depending on the conditions, a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc.

[0191] Alternatively, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears just before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when heated. Since the blue phase appears only within a narrow temperature range, it is advisable to use a liquid crystal composition containing a chiral agent of several weight percent or more in the liquid crystal layer to improve the temperature range. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required. Therefore, electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Thus, it becomes possible to improve the productivity of the liquid crystal display device. Also, the liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required. Therefore, electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Thus, it becomes possible to improve the productivity of the liquid crystal display device. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required. Therefore, electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Thus, it becomes possible to improve the productivity of the liquid crystal display device. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required. Therefore, electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Thus, it becomes possible to improve the productivity of the liquid crystal display device. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required. Therefore, electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Thus, it becomes possible to improve the productivity of the liquid crystal display device. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required. Therefore, electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Thus, it becomes possible to improve the productivity of the liquid crystal display device. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required. Therefore, electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Thus, it becomes possible to improve the productivity of the liquid crystal display device.

[0192] Also, the intrinsic resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. Note that the value of the intrinsic resistance in this specification is the value measured at 20°C. Also, the intrinsic resistance of the liquid crystal material is 1×10

[0193] The size of the holding capacitance provided in the liquid crystal display device is set so that it can hold charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. The size of the holding capacitance can be set in consideration of the off-current of the transistor and the like. The size of the holding capacitance can be set in consideration of the off-current of the transistor and the like.

[0194] The liquid crystal display device includes a TN (Twisted Nematic) mode, an IPS (In-Plane Switching) mode, an FFS (Fringe Field Switching) mode lane-Switching) mode, an FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid uid Crystal) mode, AFLC(AntiFerroelectric L Use iquid Crystal mode, etc.

[0195] In addition, normally black type liquid crystal display devices, such as those using a vertical alignment (VA) mode, The liquid crystal display device may be a transmission type liquid crystal display device. There are several types of vertical alignment modes, including: For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV mode, etc. can be used.

[0196] The present invention can also be applied to VA type liquid crystal display devices. VA type LCDs are a type of display that controls the arrangement of liquid crystal molecules in LCD panels. In this method, the liquid crystal molecules are oriented vertically to the panel surface when no voltage is applied. In addition, a pixel is divided into several regions (subpixels), each of which is illuminated in a different direction. It is said to be a multi-domain or multi-domain design that is designed to defeat molecules. The method can be used.

[0197] In addition, in display devices, they are used as black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, etc. Optical members (optical substrates) such as a prevention member are provided as appropriate. For example, a polarizing substrate and a retardation substrate Circular polarization using a plate may also be used. Also, a backlight, a side light, etc. may be used as the light source. It may be used.

[0198] Also, as the display method in the pixel portion, a progressive method, an interlace method, etc. may be used. When performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white), or there are those in which one or more of yellow, cyan, magenta, etc. are added to RGB. Note that the size of the display area may be different for each dot of the color elements. However, the disclosed invention is not limited to a color display device, and can also be applied to a monochrome display device. It can also be applied.

[0199] Also, as the display element included in the display device, a light-emitting element using electroluminescence can be applied. The light-emitting element using electroluminescence is distinguished by whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0200] In an organic EL element, by applying a voltage to the light-emitting element, electrons and holes are respectively injected into the layer containing the light-emitting organic compound from a pair of electrodes, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From this mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0201] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element configurations. They are classified. The distributed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. It is what has, and the light-emitting mechanism is donor-acceptor recombination light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as the same readability as paper, lower power consumption compared to other display devices, and a thin and light shape.

[0202] Although various forms of electrophoretic display devices can be considered, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute. By applying an electric field to the microcapsule, only the color of the particles that have moved in opposite directions and gathered on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). In this way, the electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0203] The above-mentioned microcapsules dispersed in a solvent are called electronic ink.

[0204]

[0204]

[0205]

[0205] The electronic ink can be printed on the surfaces such as glass, plastic, cloth, paper, etc. Also color display is also possible by using color filters and particles having dyes.

[0206] Note that the first particles and the second particles in the microcapsules can be made of a conductor material, an insulator material , a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, a material selected from these, or a composite material of these can be used.

[0207] Also, as the electronic paper, a display device using the twist ball display method can also be applied. The twist ball display method is a method of arranging spherical particles painted white and black between a first electrode layer and a second electrode layer which are electrode layers using the display elements, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles to perform display. There is.

[0208] By applying the pulse signal output circuit shown in Embodiment 1 or Embodiment 2 to the display device exemplified above, a display device having various functions can be provided.

[0209] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0210] (Embodiment 6) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of the electronic device include a television device (TV or television (also referred to as a receiver), monitors for computers, digital cameras, digital video cameras such as cameras, digital photo frames, mobile phones (also referred to as mobile phones and mobile phone devices), portable game machines, personal digital assistants, audio playback devices, and large game machines such as pachinko machines and the like can be mentioned.

[0211] Figure 14(A) is a notebook personal computer manufactured by mounting at least some components of the semiconductor device disclosed in this specification, and is composed of a main body 3001, a housing 3002, a display unit 3 003, a keyboard 3004, and the like.

[0212] Figure 14(B) is a personal digital assistant (PDA) manufactured by mounting at least some components of the semiconductor device disclosed in this specification. A display unit 3023, an external interface face 3025, operation buttons 3024, etc. are provided on the main body 3021. Also, as an accessory for operation there is a stylus 3022.

[0213] In addition, the semiconductor device disclosed in this specification can be applied as electronic paper. Figure 14(C) is an e-book manufactured by mounting the electronic paper as a component. Figure 14( C) shows an example of an e-book. For example, the e-book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft part 2711, and can perform an opening and closing operation with the shaft part 2711 as an axis. With such a configuration, it becomes possible to perform operations like a paper book.

[0214] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. ​​​​is incorporated. The display unit 2705 and the display unit 2707 may be configured to display a subsequent screen or may be configured to display different screens. In the case of configuring to display different screens for example, text can be displayed on the right display unit (display unit 2705 in FIG. 14(C)), and an image can be displayed on the left display unit (display unit 2707 in FIG. 14(C)).

[0215] In addition, FIG. 14(C) shows an example in which the housing 2701 is provided with an operation unit or the like. For example, the housing 2701 is provided with a power supply 2721, operation keys 2723, a speaker 2725, etc. Pages can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, the back surface or side surface of the housing may be configured to be provided with external connection terminals (such as earphone terminals, USB terminals), a recording medium insertion part, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0216] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is also possible to configure to purchase and download desired book data, etc. from an electronic book server.

[0217] FIG. 14(D) is a mobile phone manufactured by mounting at least some components of the semiconductor device disclosed in this specification, and is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 is provided with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, external connection terminals 2808, etc. is provided. Further, the housing 2800 is equipped with a solar cell 28 for charging the portable information terminal 10, an external memory slot 2811, etc. Also, the antenna is inside the housing 2801 is built in.

[0218] Also, the display panel 2802 has a touch panel, and a plurality of operation keys 2805 being video-displayed in FIG. 14(D) are indicated by dotted lines. Note that a boosting circuit for boosting the voltage output by the solar cell 2810 to the voltage required for each circuit is also implemented. The voltage output by the solar cell 2810 is boosted to the voltage required for each circuit. Also, a boosting circuit for boosting the voltage output by the solar cell 2810 to the voltage required for each circuit is implemented. is also implemented.

[0219] The display panel 2802 changes the display direction as appropriate according to the usage form. Also, since a camera lens 2807 is provided on the same plane as the display panel 2802, a videophone is possible Speaker 2803 and microphone 2804 are not limited to voice calls, but are also capable of videophone, recording, playback, etc. Further, the housing 2800 and the housing 2801 can be slid from the unfolded state as shown in FIG. 14(D) to an overlapping state, enabling miniaturization suitable for portability and can be made smaller for portability. is possible.

[0220] The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable and enables charging and data communication with a personal computer, etc. Also, by inserting a recording medium into the external memory slot 2811, it is possible to handle larger amounts of data storage and transfer and can handle larger amounts of data storage and transfer.

[0221] Also, in addition to the above functions, it may be equipped with an infrared communication function, a TV reception function, etc. is fine.

[0222] FIG. 14(E) is manufactured by mounting at least some components of the semiconductor device disclosed in this specification It is a digital video camera, which is composed of a main body 3051, a first display unit 3057, an eyepiece 3053 , an operation switch 3054, a second display unit 3055, a battery 3056, etc. It is configured.

[0223] Figure 14(F) shows an example of a television device in which the semiconductor device disclosed in this specification is mounted as at least a part. In the television device 9600, a display unit 9603 is incorporated in a housing 9601. The display unit 9603 can display an image. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. .

[0224] The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit. In addition, the remote control unit may be configured to include a display unit for displaying information output from the remote control unit.

[0225] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and by connecting to a communication network by wire or wirelessly via a modem, it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0226] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined with those shown in other embodiments and used.

Description of Signs

[0227] 11 Signal line 12 Signal line 13 Signal line 14 signal lines 21 input terminals 22 input terminals 23 input terminals 24 input terminals 25 input terminals 26 output terminals 27 output terminals 31 power lines 32 power lines 51 periods 52 periods 53 periods 54 periods 55 periods 56 periods 101 transistors 102 transistors 103 transistors 104 transistors 105 transistors 106 transistors 107 transistors 108 transistors 109 transistors 110 transistors 111 transistors 120 capacitive elements 400 substrates 401 gate electrode layers 402 gate insulating layers 403 oxide semiconductor layers 405a source electrode layers 405b drain electrode layers 407 insulating layers 409 protective insulating layers 410 transistors 420 transistors 427 insulating layers 430 transistors 436a wiring layers 436b wiring layers 437 insulating layers 440 transistors 505 substrates 506 protective insulating layers 507 gate insulating layers 510 Transistor 511 Gate electrode layer 515a Source electrode layer 515b Drain electrode layer 516 Insulating layer 530 Oxide semiconductor film 531 Oxide semiconductor layer 2700 E-book 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft portion 2721 Power supply 2723 Operation key 2725 Speaker 2800 Housing 2801 Housing 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation key 2806 Pointing device 2807 Camera lens 2808 External connection terminal 2810 Solar cell 2811 External memory slot 3001 Main body 3002 Housing 3003 Display unit 3004 Keyboard 3021 Main body 3022 Stylus 3023 Display unit 3024 Operation button 3025 External interface 3051 Main body 3053 Eyepiece portion 3054 Operation switch 3055 Second display unit 3056 Battery 3057 First display unit 4001 Substrate 4002 Pixel portion 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4018 FPC 9600 Television device 9601 Housing 9603 Display unit 9605 Stand

Claims

1. having the first to seventh transistors and a capacitive element, one of the source or drain of the first transistor is always in conduction with the output signal wiring, the other of the source or drain of the first transistor is always in conduction with the clock signal line, one of the source or drain of the second transistor is always in conduction with the power supply line, the other of the source or drain of the second transistor is always in conduction with the output signal wiring, the gate of the third transistor is always in conduction with the gate of the second transistor, one of the source or drain of the fourth transistor is always in conduction with the power supply line, the other of the source or drain of the fourth transistor is always in conduction with the gate of the second transistor, the gate of the fourth transistor is always in conduction with the signal line, the gate of the fifth transistor is always in conduction with the signal line, one of the source or drain of the sixth transistor is always in conduction with the gate of the second transistor, the other of the source or drain of the sixth transistor is always in conduction with the first wiring, the gate of the sixth transistor is always in conduction with the second wiring, one of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor, the other of the source or drain of the seventh transistor is always in conduction with the first wiring, the gate of the seventh transistor is always in conduction with the third wiring, one of the electrodes of the capacitive element is always in conduction with the gate of the second transistor, the other of the electrodes of the capacitive element is always in conduction with the power supply line, when one of the source or drain of the third transistor is in a conductive state with the gate of the first transistor through at least the channel formation region of the third transistor, a potential at which the first transistor turns off is input to the gate of the first transistor through at least the channel formation region of the third transistor, when one of the source or drain of the fifth transistor is in a conductive state with the gate of the first transistor through at least the channel formation region of the fifth transistor, a potential at which the first transistor turns on is input to the gate of the first transistor through at least the channel formation region of the fifth transistor, To the first wiring, the potential at which the second transistor turns on and the potential at which the third transistor turns on are input via the channel formation region of the sixth transistor or via the channel formation region of the seventh transistor. To the second wiring, signals having a high-level potential and a low-level potential are input. To the third wiring, signals having a high-level potential and a low-level potential are input. The third transistor has a single-gate type transistor structure. The fourth transistor is a semiconductor device having a multi-gate type transistor structure.

2. A semiconductor device having first to seventh transistors and a capacitor element, One of the source or drain of the first transistor is always in conduction with an output signal wiring. The other of the source or drain of the first transistor is always in conduction with a first clock signal line. One of the source or drain of the second transistor is always in conduction with a power supply line. The other of the source or drain of the second transistor is always in conduction with the output signal wiring. The gate of the third transistor is always in conduction with the gate of the second transistor. One of the source or drain of the fourth transistor is always in conduction with the power supply line. The other of the source or drain of the fourth transistor is always in conduction with the gate of the second transistor. The gate of the fourth transistor is always in conduction with a first signal line. The gate of the fifth transistor is always in conduction with the first signal line. One of the source or drain of the sixth transistor is always in conduction with the gate of the second transistor. The other of the source or drain of the sixth transistor is always in conduction with a wiring. The gate of the sixth transistor is always in conduction with a second signal line. One of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor. The other of the source or drain of the seventh transistor is always in conduction with the wiring. The gate of the seventh transistor is always in conduction with a second clock signal line. One of the electrodes of the capacitor element is always in conduction with the gate of the second transistor. The other of the electrodes of the capacitor element is always in conduction with the power supply line. When one of the source or drain of the third transistor is in conduction with the gate of the first transistor through at least the channel formation region of the third transistor, the potential at which the first transistor turns off is input to the gate of the first transistor through at least the channel formation region of the third transistor. When one of the source or drain of the fifth transistor is in conduction with the gate of the first transistor through at least the channel formation region of the fifth transistor, the potential at which the first transistor turns on is input to the gate of the first transistor through at least the channel formation region of the fifth transistor. To the wiring, the potential at which the second transistor turns on and the potential at which the third transistor turns on are input through the channel formation region of the sixth transistor or through the channel formation region of the seventh transistor. The third transistor has a single-gate type transistor structure. The fourth transistor is a semiconductor device having a multi-gate type transistor structure.

3. A semiconductor device having first to seventh transistors and a capacitive element, One of the source or drain of the first transistor is always in conduction with the output signal wiring. The other of the source or drain of the first transistor is always in conduction with the clock signal line. One of the source or drain of the second transistor is always in conduction with the power supply line. The other of the source or drain of the second transistor is always in conduction with the output signal wiring. The gate of the third transistor is always in conduction with the gate of the second transistor. One of the source or drain of the fourth transistor is always in conduction with the power supply line. The other of the source or drain of the fourth transistor is always in conduction with the gate of the second transistor. The gate of the fourth transistor is always in conduction with the signal line. The gate of the fifth transistor is always in conduction with the signal line. One of the source or drain of the sixth transistor is always in conduction with the gate of the second transistor. The other of the source or drain of the sixth transistor is always in conduction with the first wiring. The gate of the sixth transistor is always in conduction with the second wiring. One of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor. The other of the source or drain of the seventh transistor is always in conduction with the first wiring. The gate of the seventh transistor is always in conduction with the third wiring. One of the electrodes of the capacitive element is always in conduction with the gate of the second transistor. The other of the electrodes of the capacitive element is always in conduction with the power supply line. When one of the source or drain of the third transistor is in a conductive state with the gate of the first transistor through at least the channel formation region of the third transistor, the potential at which the first transistor turns off is input to the gate of the first transistor through at least the channel formation region of the third transistor. When one of the source or drain of the fifth transistor is in a conductive state with the gate of the first transistor through at least the channel formation region of the fifth transistor, the potential at which the first transistor turns on is input to the gate of the first transistor through at least the channel formation region of the fifth transistor. To the first wiring, the potential at which the second transistor turns on and the potential at which the third transistor turns on are input through the channel formation region of the sixth transistor or through the channel formation region of the seventh transistor. To the second wiring, a signal having a high-level potential and a low-level potential is input. To the third wiring, a signal having a high-level potential and a low-level potential is input. The third transistor has a single-gate type transistor structure. The fourth transistor has a multi-gate type transistor structure. At least one of the first to seventh transistors has a first insulating layer, a semiconductor layer having a region on the first insulating layer and having a region that functions as a channel formation region, a second insulating layer having a region on the semiconductor layer, and a first conductive layer having a region on the second insulating layer and having a region that functions as a gate electrode. The first insulating layer has oxygen and silicon. The second insulating layer has oxygen and silicon, a semiconductor device.

4. having first to seventh transistors and a capacitive element, One of the source or drain of the first transistor is always in conduction with the output signal wiring. The other of the source or drain of the first transistor is always in conduction with the first clock signal line. One of the source or drain of the second transistor is always in conduction with the power supply line. The other of the source or drain of the second transistor is always in conduction with the output signal wiring. The gate of the third transistor is always in conduction with the gate of the second transistor. One of the source or drain of the fourth transistor is always in conduction with the power supply line. The other of the source or drain of the fourth transistor is always in conduction with the gate of the second transistor. The gate of the fourth transistor is always in conduction with the first signal line. The gate of the fifth transistor is always in conduction with the first signal line. One of the source or drain of the sixth transistor is always in conduction with the gate of the second transistor. The other of the source or drain of the sixth transistor is always in conduction with the wiring. The gate of the sixth transistor is always in conduction with the second signal line. One of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor. The other of the source or drain of the seventh transistor is always in conduction with the wiring. The gate of the seventh transistor is always in conduction with the second clock signal line. One of the electrodes of the capacitive element is always in conduction with the gate of the second transistor. The other of the electrodes of the capacitive element is always in conduction with the power supply line. When one of the source or drain of the third transistor is in a conductive state with the gate of the first transistor at least via the channel formation region of the third transistor, the potential at which the first transistor turns off is input to the gate of the first transistor at least via the channel formation region of the third transistor. When one of the source or drain of the fifth transistor is in a conductive state with the gate of the first transistor at least via the channel formation region of the fifth transistor, the potential at which the first transistor turns on is input to the gate of the first transistor at least via the channel formation region of the fifth transistor. The potential at which the second transistor is turned on and the potential at which the third transistor is turned on are input to the wiring through the channel formation region of the sixth transistor or through the channel formation region of the seventh transistor. The third transistor has a single-gate transistor structure. The fourth transistor has a multi-gate transistor structure. At least one of the first to seventh transistors has a first insulating layer, a semiconductor layer having a region on the first insulating layer and having a region functioning as a channel formation region, a second insulating layer having a region on the semiconductor layer, and a first conductive layer having a region on the second insulating layer and having a region functioning as a gate electrode. The first insulating layer contains oxygen and silicon. The second insulating layer contains oxygen and silicon. A semiconductor device.

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