Display device and source driver

Abstract

PURPOSE: To provide a display device capable of preventing the occurrence of display abnormality by quickly detecting the occurrence of communication abnormality.CONSTITUTION: A source driver includes: a still image determination section that calculates a CRC value for a pixel data piece corresponding to each of a plurality of horizontal scanning lines constituting a video data signal for one frame, sequentially compares the CRC value for each corresponding horizontal scanning line between a signal carrying display of one frame of the video data signal and a signal carrying display of another frame that is a frame subsequent to the one frame, and determines whether it is a still image display state in which a still image is displayed on a display panel by the video data signal on the basis of whether the CRC values match; and a data processing section that temporarily stops operation of a gate driver until timing at which a video of any subsequent frame subsequent to the other frame is displayed on the display panel in a case where it is determined that the CRC values between the one frame and the other frame do not match for any of the plurality of horizontal scanning lines when the still image determination section determines the still image display state.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a display device and a source driver.

Background Art

[0002] In recent years, liquid crystal panels have been widely adopted in in-vehicle display devices, and resistance to malfunction in the panel ESD test is required. In order to detect a failure occurring in a liquid crystal display device, a display device having a configuration for determining an abnormal state by comparing a signal voltage supplied to an output voltage monitor line with a preset reference voltage has been proposed (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a small display device for in-vehicle use or the like, video data is transmitted from an LSI on the transmission side to a source driver using a transmission technology such as LVDS (Low Voltage Differential Signaling). In such image communication as LVDS, when a communication abnormality occurs instantaneously, there is an increasing demand to prevent the occurrence of a display abnormality in the liquid crystal display device. In particular, when displaying a still image, when noise of about several lines caused by a communication abnormality occurs, it is preferable to prevent the occurrence of a display abnormality caused thereby.

[0005] When determining communication anomalies in frame units using CRC symbols, the PLL / DLL of the receiving unit may become unlocked between the occurrence of noise and the anomaly determination, and unstable operation may continue due to misreceiving the synchronization signal, making it impossible to prevent abnormal display. Although it is conceivable to prevent the occurrence of display anomalies by delaying the display by one frame, in that case, a frame memory is required for the display device on the receiving side, resulting in an increase in the device scale.

[0006] In addition, in in-vehicle display devices and the like, video data is transmitted from the LSI on the transmitting side to the source driver using transmission technologies such as LVDS (Low Voltage Differential Signaling). However, in the LVDS data format, only the 8-bit image data for each of RGB and the synchronization signals of DE / HS / VS are defined in the data area corresponding to the data packet for one pixel, and no error detection code is defined. For this reason, there has been a problem that it is difficult to perform anomaly determination in LVDS communication in line units.

[0007] The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device that can quickly detect the occurrence of communication anomalies and prevent the occurrence of display anomalies in a display device that receives video data transmission and displays video.

Means for Solving the Problems

[0008] The display device according to the present invention includes a plurality of data lines, a plurality of gate lines, and a plurality of pixel portions provided in a matrix at each intersection of the plurality of data lines and the plurality of gate lines, a display panel having the same, a gate driver that supplies a gate signal to the plurality of gate lines, and a source driver that receives a video data signal including a series of a plurality of pixel data pieces and indicating a video to be displayed on the display panel, supplies a gradation voltage signal to the plurality of pixel portions via the plurality of data lines, and controls the operation of the gate driver, and a video data transmission unit that transmits the video data signal to the source driver. The source driver calculates a CRC value for each of the pixel data pieces corresponding to each of the plurality of horizontal scanning lines constituting the video data signal for one frame, and sequentially compares the CRC values for each of the corresponding horizontal scanning lines between a signal responsible for displaying one frame of the video data signal and a signal responsible for displaying another frame which is a frame subsequent to the one frame. A still image determination unit that determines whether or not a still image is being displayed on the display panel by the video data signal based on whether or not the CRC values match, and when it is determined by the still image determination unit that the still image display state is present, if it is determined that a mismatch in the CRC value has occurred between the one frame and the other frame for any one of the plurality of horizontal scanning lines, a data processing unit that temporarily stops the operation of the gate driver until the timing of displaying the video of any subsequent frame following the other frame on the display panel. It is characterized by including the same.

[0009] In addition, the source driver according to the present invention is connected to a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of pixel portions provided in a matrix at each intersection of the plurality of data lines and the plurality of gate lines, receives a video data signal including a series of a plurality of pixel data pieces, generates a gradation voltage signal based on the received video data signal, and supplies the gradation voltage signal to the plurality of pixel portions. The source driver calculates a CRC value for each of the pixel data pieces corresponding to each of a plurality of horizontal scanning lines constituting the video data signal for one frame, sequentially compares the CRC values for each of the corresponding horizontal scanning lines between a signal responsible for displaying one frame of the video data signal and a signal responsible for displaying another frame which is a frame subsequent to the one frame, and determines whether a still image is being displayed on the display panel by the video data signal based on whether the CRC values match. When it is determined by the still image determination unit that the still image display state is present, and when it is determined that a mismatch in the CRC value has occurred between the one frame and the other frame for any one of the plurality of horizontal scanning lines, a data processing unit temporarily stops the operation of a gate driver that supplies a gate signal to the plurality of gate lines until a timing at which a video of any subsequent frame following the other frame is displayed on the display panel.

Advantages of the Invention

[0010] According to the display device of the present invention, in a display device that receives transmission of video data and displays a video, it is possible to promptly detect the occurrence of a communication abnormality and prevent the occurrence of a display abnormality.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of the embodiments and the accompanying drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

[0013] FIG. 1 is a block diagram showing the configuration of a display device 100 according to the present invention. The display device 100 is a liquid crystal display device using an active matrix driving method, and in this embodiment, it is configured as a small-sized liquid crystal display device for in-vehicle use. The display device 100 includes a display panel 11, a transmission-side LSI 12, a gate driver 13, and source drivers 14A and 14B.

[0014] The display panel 11 is composed of a semiconductor substrate in which a plurality of pixel portions P11 to Pnm and pixel switches M11 to Mnm (n and m are natural numbers of 2 or more) are arranged in a matrix. The display panel 11 has n gate lines GL1 to GLn, each of which is a scanning line extending in the horizontal direction, and m source lines SL1 to SLm, which are data lines arranged so as to intersect with them. The pixel portions P11 to Pnm and the pixel switches M11 to Mnm are provided at the intersections of the gate lines GL1 to GLn and the source lines SL1 to SLm.

[0015] The pixel switches M11 to Mnm are controlled to be turned on or off according to the gate signals Vg1 to Vgn supplied from the gate driver 13. The pixel portions P11 to Pnm receive the supply of the gradation voltage signals Vd1 to Vdm corresponding to the video data from the source drivers 14A and 14B. When the pixel switches M11 to Mnm are each turned on, the gradation voltage signals Vd1 to Vdm are applied to the respective pixel electrodes of the pixel portions P11 to Pnm, and each pixel electrode is charged. The luminance of the pixel portions P11 to Pnm is controlled according to the gradation voltage signals Vd1 to Vdm at the respective pixel electrodes of the pixel portions P11 to Pnm, and display is performed.

[0016] In other words, by the operation of the gate driver 13, m pixel portions arranged along the extending direction of the gate line (i.e., in a horizontal row) are selected as the supply targets of the gradation voltage signals Vd1 to Vdm. The source drivers 14A and 14B apply the gradation voltage signals Vd1 to Vdm to the selected pixel portions in a horizontal row, and display a color corresponding to the voltage. By selectively switching the pixel portions in a horizontal row selected as the supply targets of the gradation voltage signals Vd1 to Vdm and repeating in the extending direction of the data line (i.e., in the vertical direction), the screen display for one frame is performed.

[0017] Each of the pixel portions P11 to Pnm includes liquid crystal encapsulated between a transparent electrode connected to a data line via a pixel switch, and a counter substrate provided to face the semiconductor substrate and having one transparent electrode formed over the entire surface. Display is performed by the transmittance of the liquid crystal changing according to the voltage difference between the gradation voltage signals Vd1 to Vdm supplied to the pixel portions P11 to Pnm and the counter substrate voltage with respect to the backlight inside the display device.

[0018] The transmitting - side LSI 12 is a transmitting - side LSI (Large Scale Integration) that transmits video data in the LVDS (Low Voltage Differential Signaling) format. The transmitting - side LSI 12 receives the supply of video data VD, and based on this, generates video data signals VS1 and VS2 that consist of a series (serial signal) of a plurality of pixel data pieces PD representing the luminance level of each pixel in, for example, 256 luminance gradations of 8 - bit. The transmitting - side LSI 12 supplies the video data signal VS1 to the source driver 14A and the video data signal VS2 to the source driver 14B respectively using the LVDS interface.

[0019] Also, the transmitting - side LSI 12 receives the supply of the synchronization signal FD, and based on this, generates a frame synchronization signal FS indicating the timing for each frame of the video data signals VS1 and VS2. The transmitting - side LSI 12 supplies the frame synchronization signal FS to the source drivers 14A and 14B using the LVDS interface.

[0020] Also, the transmitting - side LSI 12 receives the supply of setting data SD, which is data regarding various settings of the source drivers 14A and 14B. The transmitting - side LSI 12 generates a setting communication signal SS based on the setting data SD and supplies it to the source drivers 14A and 14B using the LVDS interface.

[0021] The gate driver 13 receives the supply of the gate control signal GS from the source driver 14A, and based on the clock timing included in the gate control signal GS, sequentially supplies gate signals Vg1~Vgn to the gate lines GL1~GLn.

[0022] By supplying the gate signals Vg1~Vgn, pixel portions P11~Pnm are selected for each pixel row. For the selected pixel portions, gradation voltage signals Vd1~Vdm are applied from the source drivers 14A and 14B, thereby writing the gradation voltage to the pixel electrodes. By repeatedly supplying the gradation voltage signals Vd1~Vdm while selectively switching the pixel portions for one horizontal row, the screen display for one frame is performed.

[0023] Further, the gate driver 13 receives the supply of the gate reset signal GRS from the source driver 14A. When the signal level of the gate reset signal GRS is at the logic level 1 (H level), the gate driver 13 enters the so-called "reset state" accordingly. At this time, the supply of the gate control signal GS to the gate driver 13 is temporarily stopped. In response to this, the gate driver 13 stops the output of the gate signals Vg1 to Vgn to the gate lines GL1 to GLn, and resumes the output of the gate signals Vg1 to Vgn at the timing of displaying the video of the next frame.

[0024] The source drivers 14A and 14B are arranged adjacent to each other along the horizontal direction (i.e., the extending direction of the gate lines GL1 to GLn) and are cascade-connected. The source drivers 14A and 14B are formed on separate semiconductor IC (Integrated Circuit) chips (driver ICs). The source driver 14A is a source driver responsible for driving the data lines DL1 to DLi arranged at the left position closer to the gate driver 13 among the data lines DL1 to DLm. The source driver 14B is a source driver responsible for driving the data lines DLi+1 to DLm arranged at the right position farther from the gate driver 13.

[0025] The source driver 14A receives the supply of the frame synchronization signal FS and the video data signal VS1 from the transmission-side LSI 12, generates gradation voltage signals Vd1 to Vdi corresponding to multi-value level gradation voltages corresponding to the number of gradation levels indicated by the video data signal VS1, and supplies them to the data lines DL1 to DLi. Further, the source driver 14 generates a gate control signal GS for controlling the operation timing of the gate driver 13 and supplies it to the gate driver 13.

[0026] The source driver 14B receives the supply of the frame synchronization signal FS and the video data signal VS2 from the transmission-side LSI 12, generates gradation voltage signals Vdi+1 to Vdm corresponding to multi-value level gradation voltages corresponding to the number of gradation levels indicated by the video data signal VS2, and supplies them to the data lines DLi+1 to DLm.

[0027] Further, the source driver 14A has a function of determining whether the video data signal VS1 supplied from the transmission-side LSI 12 indicates a still image based on the CRC code. The source driver 14A supplies a still image determination signal SCS indicating the determination result to the source driver 14B via the connection wiring of the cascade connection.

[0028] Similarly, the source driver 14B has a function of determining whether the video data signal VS2 supplied from the transmission-side LSI 12 indicates a still image, and supplies a still image determination signal SCS indicating the determination result to the source driver 14A via the connection wiring of the cascade connection.

[0029] FIG. 2 is a block diagram showing the internal configuration of the source driver 14A. The source driver 14A includes a reception unit (PLL) 21, a data processing unit 22, a setting register 23, a source control unit 24, a data latch group 25, a DAC 26, a gate control unit 27, and a still image determination unit 28.

[0030] The reception unit 21 receives the video data signal VS1 and the frame synchronization signal FS transmitted from the transmission-side LSI 12 in the LVDS format. The reception unit 21 includes a PLL (Phase Locked Loop) circuit, and generates a clock signal CLK based on the video data signal VS1 and the frame synchronization signal FS. Further, the reception unit 21 generates a serial data signal DS synchronized with the clock signal CLK, and supplies it to the data processing unit 22.

[0031] The data processing unit 22 performs serial-parallel conversion on the data signal DS to generate parallel pixel data pieces PD. Further, the data processing unit 22 generates a horizontal synchronization signal LS based on the clock signal CLK and the data signal DS. The data processing unit 22 supplies the generated pixel data pieces PD and the horizontal synchronization signal LS to the source control unit 24 and the still image determination unit 28.

[0032] Further, the data processing unit 22 generates a timing signal TS used for controlling the gate driver 13 based on the clock signal CLK and supplies it to the gate control unit 27.

[0033] Furthermore, the data processing unit 22 receives the supply of the still image determination signal SCS from the still image determination unit 28, and in response thereto, generates a gate reset signal GRS for resetting the operation of the gate driver 13. Also, the data processing unit 22 receives the supply of the still image determination signal SCS from the source driver of another chip (in this embodiment, the source driver 14B) disposed adjacent to the source driver 14A, and based on this, generates a gate reset signal GRS in the same manner as when receiving the supply of the still image determination signal SCS from the still image determination unit 28.

[0034] The setting register 23 is a register that stores source control data SSD, which is setting data for controlling the operation of the source driver 14A, and gate control data GSD, which is setting data for controlling the operation of the gate driver 13. Writing the source control data SSD and the gate control data GSD to the setting register 23 and reading them from the setting register 23 are performed based on setting communication (setting communication signal SS) from the transmission-side LSI 12.

[0035] The source control unit 24 supplies the parallel pixel data pieces PD supplied from the data processing unit 22 to the first latch of the data latch group 25. Also, the source control unit 24 supplies the horizontal synchronization signal LS to the data latch group 25, and causes the data latch group 25 to store the pixel data pieces PD using the horizontal synchronization signal LS as the capture clock. The source control unit 24 performs these operations based on the source control data SSD read from the setting register 23.

[0036] The data latch group 25 is composed of a plurality of latch circuits including a first latch and a second latch (not shown). The first latch takes in pixel data pieces PD for each row according to the control of the source control unit 24. The second latch takes in the pixel data pieces PD stored in the first latch for each pixel in response to the rising edge of the horizontal synchronization signal LS.

[0037] The DA converter (DAC) 26 selects a gradation voltage corresponding to the pixel data piece PD output from the data latch group 25, performs digital-to-analog conversion, and generates an analog gradation voltage signal Vd. The generated analog gradation voltage signal Vd is amplified by an output amplifier (not shown) and output.

[0038] The gate control unit 27 generates a gate control signal GS based on the timing signal TS supplied from the data processing unit 22 and controls the gate driver 13. The gate control unit 27 performs a control operation of the gate driver 13 based on the gate control data GSD read from the setting register 23.

[0039] The still image determination unit 28 calculates the CRC based on the pixel data piece PD supplied from the data processing unit 22, and determines whether the image displayed based on the pixel data piece PD is a still image or not based on the calculation result. The still image determination unit 28 generates a still image determination signal SCS for switching on and off the still image display mode based on the determination result and supplies it to the data processing unit 22.

[0040] Note that the source driver 14B also has the same configuration as the source driver 14A. However, in the source driver 14B, the function of the gate control unit 27 and the output function of the gate reset signal GRS by the data processing unit 22 are disabled.

[0041] Figure 3 is a block diagram showing the internal configurations of the data processing unit 22 and the still image determination unit 28.

[0042] The data processing unit 22 includes a serial-parallel conversion unit 31, a synchronization signal / image data generation unit 32, and a timing control unit 33.

[0043] The serial-parallel conversion unit 31 acquires the video data signal VS1 transmitted from the transmission-side LSI 12 as a serial data signal DS via the reception unit 21 (not shown in FIG. 3). The serial-parallel conversion unit 31 performs serial-parallel conversion on the data signal DS.

[0044] Based on the data signal DS parallel-converted by the serial-parallel conversion unit 31, the synchronization signal / image data generation unit 32 generates parallel image data (pixel data pieces PD) and a horizontal synchronization signal LS.

[0045] The timing control unit 33 receives the supply of the pixel data pieces PD and the horizontal synchronization signal LS from the synchronization signal / image data generation unit 32, and also receives the supply of a still image determination signal SCS from the still image determination unit 28. The timing control unit 33 outputs the pixel data pieces PD and the horizontal synchronization signal LS to the source control unit 24. Further, the timing control unit 33 generates a timing signal TS based on the pixel data pieces PD and the horizontal synchronization signal LS, and outputs it to the gate control unit 27.

[0046] Furthermore, the timing control unit 33 outputs a gate reset signal GRS based on the still image determination signal SCS. Specifically, when the still image determination signal changes from the logical level 1 (H level) to the logical level 0 (L level), the timing control unit 33 outputs a gate reset signal GRS of logical level 1 for resetting the gate driver. At that time, the timing control unit 33 changes the signal level of the timing signal TS, and temporarily stops (until the display timing of the next frame) the output of the gate control signal GS by the gate control unit 27.

[0047] The still image determination unit 28 includes a line CRC calculation unit 41, a CRC holding unit 42, and a CRC comparison unit 43.

[0048] The line CRC calculation unit 41 calculates CRC for each pixel data piece PD for one line (i.e., for one horizontal scanning line) based on the parallel image data (pixel data piece PD) generated by the synchronization signal / image data generation unit 53. The line CRC calculation unit 41 sequentially supplies the CRC value CV, which is the calculation result, to the CRC holding unit 42 and the CRC comparison unit 43.

[0049] The CRC holding unit 42 holds the CRC value CV for each pixel data piece PD for one line supplied from the line CRC calculation unit 41 for the signal (pixel data piece PD) responsible for displaying one frame, and then supplies it to the CRC comparison unit 43.

[0050] The CRC comparison unit 43 compares the CRC value CV of the signal responsible for displaying a certain frame held by the CRC holding unit 42 with the CRC value CV of the signal responsible for displaying the next frame newly calculated by the line CRC calculation unit 41 for each corresponding line, and determines whether they match. When it is determined that the CRC values CV between frames match for all lines, the CRC comparison unit 43 outputs a still image determination signal SCS with a logical level 1 (i.e., H level) indicating that the display panel 11 is in a state where a still image is being displayed (hereinafter referred to as the still image display state). On the other hand, when it is determined that the CRC values CV do not match in any line, the CRC comparison unit 43 outputs a still image determination signal SCS with a logical level 0 (i.e., L level). The still image determination signal SCS is supplied to the timing control unit 33 of the data processing unit 22 and also supplied to the source driver 14B.

[0051] Next, the display control operation in the display device 100 of this embodiment will be described with reference to the flowchart of FIG. 4. Here, among the source drivers 14A and 14B, the operation of the source driver 14A will be described with focus.

[0052] First, the source driver 14A outputs a gradation voltage signal Vd and controls the gate driver 13 based on the video data signal VS1 and the frame synchronization signal FS supplied from the transmission - side LSI 12. As a result, normal video display is performed on the display panel 11 (STEP101).

[0053] The still - image determination unit 28 of the source driver 14A calculates the CRC value CV for each line based on the pixel data piece PD obtained from the video data signal VS1, and determines whether the CRC values CV for all lines between adjacent frames match and whether this state continues for two or more frames (STEP102).

[0054] When it is determined that the state where the CRC values CV match does not continue for two or more frames (STEP102: NO), the still - image determination unit 28 of the source driver 14A outputs a still - image determination signal SCS with a logic level of 0 (L level). The still - image determination signal SCS is supplied to the data processing unit 22 and also to the source driver 14B. Based on this, the source drivers 14A and 14B continue to output the gradation voltage signal Vd for normal video display.

[0055] On the other hand, when it is determined that the state where the CRC values CV match continues for two or more frames (STEP102: YES), the still - image determination unit 28 of the source driver 14A outputs a still - image determination signal SCS with a logic level of 1 (H level). The still - image determination signal SCS is supplied to the data processing unit 22 and the source driver 14B. The source drivers 14A and 14B output the gradation voltage signal Vd and control the gate driver 13 based on the video data signals VS1, VS2 corresponding to the still - image and the frame synchronization signal FS. As a result, still - image display is performed on the display panel 11, and it enters the still - image display state (STEP103).

[0056] The still - image determination unit 28 of the source driver 14A sequentially compares the CRC values CV between frames for each line in the CRC comparison unit 43, and determines whether there is a mismatch in the CRC value CV in any line (STEP104).

[0057] When it is determined that there is no discrepancy in the CRC value CV (STEP104: NO), the process returns to STEP103, and the still image determination unit 28 continues to output a still image determination signal SCS at a logical level 1 (H level). The source drivers 14A and 14B continue the display control for still image display.

[0058] On the other hand, when it is determined that a discrepancy has occurred in the CRC value CV (STEP104: YES), the still image determination unit 28 of the source driver 14A changes the signal level of the still image determination signal SCS from the logical level 1 (H level) to the logical level 0 (L level). In response to this, each data processing unit 22 of the source drivers 14A and 14B outputs a gate reset signal GRS at the logical level 1. Further, the data processing unit 22 controls the gate control unit 27 to temporarily stop the output of the gate control signal GS. As a result, the gate driver 13 enters a reset state, and the output of the gate signals Vg1 to Vgn is temporarily stopped until the display timing of the next frame (STEP105).

[0059] The gate driver 13 resumes the output of the gate signals Vg1 to Vgn at the timing of the image display of the next frame. The source drivers 14A and 14B output a gradation voltage signal Vd for normal video display.

[0060] FIG. 5A is a time chart showing the operations of the respective parts of the source driver 14A when a communication error due to ESD noise or the like temporarily occurs in the transmission of the video data signal VS1 from the transmission-side LSI 12 in the still image display state. FIG. 5B is a diagram showing an example of the screen displayed on the display panel 11 when a communication error temporarily occurs. Here, the case where a communication error occurs during the communication of the video data signal VS1 of frame C is shown. Also, here, the display device 100 is an in-vehicle display device, and the case where the video of an instrument such as a speedometer is displayed as a still image is shown as an example.

[0061] In frame A and frame B, it is in the still image display state, and the CRC value CV for each line of one frame calculated based on the video data signal VS1 received from the transmission-side LSI 12 matches the CRC values CV of all lines of the previous frame. Therefore, the still image determination unit 28 outputs a still image determination signal SCS of logical level 1 (H level). In response to this, the data processing unit 22 outputs a gate reset signal GRS of logical level 0 (L level).

[0062] Since the gate reset signal GRS is at the L level, the gate driver 13 continues the output operation of the normal gate signals Vg1 to Vgn. The source driver 14A outputs a gradation voltage signal Vd based on the video data signal VS1 corresponding to the still image. As a result, a still image is displayed on the display panel 11.

[0063] In frame C, due to the occurrence of a communication error, the CRC value CV in a certain line becomes inconsistent with the CRC value CV of the same line in the previous frame. The still image determination unit 28 outputs a still image determination signal SCS of logical level 0 (L level) based on the comparison result of the CRC comparison unit 43. In response to this, the data processing unit 22 outputs a gate reset signal GRS of logical level 1 (H level). As a result, the gate driver 13 enters the reset state. The gate control unit 27 temporarily stops the supply of the gate control signal GS and stops the supply of the gate signals Vg1 to Vgn by the gate driver 13. As a result, on the display screen of frame C, the screen of the previous frame is fixedly displayed.

[0064] In frame D, the gate control unit 27 resumes the supply of the gate control signal GS, and in response to this, the gate driver 13 outputs the gate signals Vg1 to Vgn. As a result, in frame D, normal video display is performed again.

[0065] As described above, in the source driver 14A of this embodiment, the comparison of the CRC value CV is performed for each line, and the gate driver 13 is reset based on whether the CRC value CV of the current frame matches the CRC value CV of the previous frame. Therefore, for example, when a temporary communication error due to noise occurs in the communication of the video data signal VS1 of frame C, the gate driver 13 can be set to the reset state during the image display of frame C to perform stuck display.

[0066] FIGS. 6A and 6B are diagrams showing, as a comparative example, a time chart and an example of a display screen of the operation of a source driver when it is assumed that the comparison of the CRC value CV is performed not for each line (line unit) but for each frame, different from the source driver 14A of this embodiment.

[0067] In the comparative example, even when a communication error occurs during frame C, a mismatch in the CRC value CV is detected only at the timing after the video display of frame C is performed. Therefore, as shown in FIG. 6B, display abnormalities occur in the video display of frame C.

[0068] On the other hand, in the source driver 14A of this embodiment, the comparison of the CRC value CV is sequentially performed for each line, and the gate driver 13 is reset when it is determined that a mismatch has occurred. Therefore, when a communication abnormality occurs during the display of frame C, the same video as that of frame B can be fixedly displayed in frame C. Therefore, according to the source driver 14A of this embodiment, it is possible to prevent display abnormalities as shown in FIG. 6B.

[0069] As described above, in the display device 100 of the present embodiment, the still image determination units 28 provided in the source drivers 14A and 14B sequentially determine whether the CRC values between frames match or not for each line. Then, in the still image display state, when it is determined that a CRC mismatch has occurred in any line, the gate driver 13 is controlled to be in a reset state to temporarily stop the operation. As a result, when a communication error occurs while displaying the video of a certain frame, the video of that frame is fixedly displayed, so that the occurrence of display abnormalities can be prevented.

[0070] Therefore, according to the display device 100 of the present embodiment, in a display device that receives video data transmission and displays video, it is possible to quickly detect a transmission abnormality (communication abnormality) that occurs during the display of a still image and prevent the occurrence of display abnormalities.

[0071] Note that the present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the source drivers are composed of the source drivers 14A and 14B formed on different IC chips is described as an example. However, the number of driver ICs constituting the source driver is not limited to this, and it is only necessary that the still image determination signal SCS can be shared among a plurality of source drivers.

[0072] Also, in the above embodiment, the configuration in which only the source driver 14A is connected to the gate driver 13 and the gate driver 13 is controlled including the supply of the gate reset signal GRS is described. However, different from this, for example, two gate drivers 13A and 13B may be provided on both the left and right sides of the display panel 11, and the source driver 14A may be configured to control the operation of the gate driver 13A and the source driver 14B may be configured to control the operation of the gate driver 13B, respectively.

[0073] In the above embodiment, when it is determined that a CRC value CV mismatch has occurred in the still image display state, the case where the video is fixedly displayed until the video of the next frame is displayed is described as an example. However, the period of the fixed display is not limited to this, and the fixed display may be continued until the next next frame or even the next frame. That is, when it is determined that a CRC value CV mismatch has occurred while a video of one frame is being displayed, the operation of the gate driver 13 may be temporarily stopped until the timing of displaying the video of any subsequent frame on the display panel.

Explanation of Signs

[0074] 100 Display device 11 Display panel 12 Transmission-side LSI 13 Gate driver 14A, 14B Source driver 21 Receiver 22 Data processing unit 23 Setting register 24 Source control unit 25 Data latch group 26 DAC 27 Gate control unit 28 Still image determination unit 31 Serial-parallel conversion unit 32 Synchronization signal / image data generation unit 33 Timing control unit 41 Line CRC calculation unit 42 CRC holding unit 43 CRC comparison unit

Claims

1. A display panel having a plurality of data lines, a plurality of gate lines, and a plurality of pixel portions provided in a matrix at each intersection of the plurality of data lines and the plurality of gate lines; A gate driver that supplies a gate signal to the plurality of gate lines; A source driver that receives a video data signal including a series of a plurality of pixel data pieces and indicating a video to be displayed on the display panel, supplies a gradation voltage signal to the plurality of pixel portions via the plurality of data lines based on the video data signal, and controls the operation of the gate driver; A video data transmission unit that transmits the video data signal to the source driver; characterized by comprising: The source driver calculates a CRC value for each of the pixel data pieces corresponding to each of a plurality of horizontal scanning lines constituting the video data signal for one frame, and sequentially compares the CRC values for each of the corresponding horizontal scanning lines between a signal responsible for displaying one frame of the video data signal and a signal responsible for displaying another frame which is a frame subsequent to the one frame, and determines whether a still image is being displayed on the display panel by the video data signal based on whether the CRC values match, a still image determination unit; When it is determined by the still image determination unit that the still image display state is present, if it is determined that a CRC value mismatch has occurred between the one frame and the other frame for any of the plurality of horizontal scanning lines, a data processing unit that temporarily stops the operation of the gate driver until the timing of displaying the video of any subsequent frame following the other frame on the display panel; A display device characterized by including the above.

2. The source driver is composed of a plurality of driver ICs, each of the plurality of driver ICs has the still image determination unit, at least one of the plurality of driver ICs is connected to the gate driver, and when it is determined that a CRC value mismatch has occurred in any one of the plurality of driver ICs, supplies a gate reset signal to the gate driver to temporarily stop the operation, the display device according to Claim 1.

3. The display device according to claim 2, wherein the plurality of driver ICs are cascade-connected to each other adjacent driver ICs, and the determination results of the respective still image determination units are shared via the connection wiring of the cascade connection.

4. The still image determination unit a CRC calculation unit that calculates the CRC value for each horizontal scanning line based on the video data signal; a CRC holding unit that sequentially holds the CRC values for each horizontal scanning line for each frame; a CRC comparison unit that compares the CRC value calculated by the CRC calculation unit with the CRC value held by the CRC holding unit for each corresponding horizontal scanning line; The display device according to claim 1, characterized by comprising:

5. Connected to a display panel having a plurality of data lines and a plurality of gate lines, and a plurality of pixel portions provided in a matrix at each intersection of the plurality of data lines and the plurality of gate lines, receiving a video data signal including a series of a plurality of pixel data pieces, generating a gradation voltage signal based on the received video data signal, and supplying the gradation voltage signal to the plurality of pixel portions, a source driver calculates a CRC value for each of the pixel data pieces corresponding to each of the plurality of horizontal scanning lines constituting the video data signal for one frame, and sequentially compares the CRC values for each corresponding horizontal scanning line between a signal responsible for displaying one frame of the video data signal and a signal responsible for displaying another frame that is a frame subsequent to the one frame, and determines whether or not a still image is being displayed on the display panel by the video data signal based on whether or not the CRC values match, a still image determination unit; When it is determined by the still image determination unit that the still image display state is present, when it is determined that a mismatch in the CRC value has occurred between the one frame and the other frame for any of the plurality of horizontal scanning lines, until the timing of displaying the video of any subsequent frame following the other frame on the display panel, a data processing unit that temporarily stops the operation of the gate driver that supplies a gate signal to the plurality of gate lines; A source driver characterized by comprising:

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