Load device for testing multichannel power supply system and test method

Abstract

To provide a device for testing a multichannel power supply system in a state close to actual operation.SOLUTION: A plurality of current sources 110_1 to 110_n are connected to a plurality of outputs of a multichannel power supply. In each current source 110 a current amount is digitally controllable. A controller 120 independently controls the current amount generated by the plurality of current sources 110.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a test load device.

Background Art

[0002] A microcontroller includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), peripheral circuits, etc. The microcontroller is configured to operate by receiving independent power supply voltages for each block. In order to supply a plurality of power supply voltages to such a microcontroller, a multi-channel power supply system is used.

[0003] Also, many electronic devices include circuit components such as a CPU (Central Processing Unit), a memory, an SSD (Solid State Disk), various ICs (Integrated Circuit), and a display. In order to supply appropriate power supply voltages to these circuit components, a multi-channel power supply system is mounted on the electronic device.

[0004] The multi-channel power supply system is composed of a control IC called a power management circuit (PMIC; Power Management IC) and its peripheral circuits. The PMIC has functions such as starting and stopping multi-channel power blocks in a determined order, or stopping only the power blocks of some channels in a specific operation mode.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] [Summary] During the actual operation of an electronic device, the load current of a multi-channel power supply system varies randomly for each channel. When testing the power supply system by operating and testing each channel one by one, phenomena that can occur during actual operation, such as interference between channels, cannot be captured. Therefore, even if the test passes, there is a possibility of malfunction in the actual device.

[0007] The present disclosure has been made in view of such problems, and an exemplary purpose of one of its aspects is to provide an apparatus for testing a multi-channel power supply system in a state close to actual operation.

[0008] A test load device according to an aspect of the present disclosure includes a plurality of current sources to be connected to a plurality of outputs of a multi-channel power supply system, each current source having a digitally controllable current amount, and a controller capable of independently controlling the current amounts generated by the plurality of current sources.

[0009] Another aspect of the present disclosure relates to a test method for a multi-channel power supply system. This test method includes a step of connecting a plurality of current sources to a plurality of outputs of a multi-channel power supply system, each current source having a digitally controllable current amount, and a step of independently controlling the current amounts generated by the plurality of current sources.

[0010] In addition, combinations of the above components arbitrarily, and those obtained by mutually replacing the components and expressions of the present disclosure between methods, apparatuses, systems, etc. are also effective as aspects of the present invention.

Brief Description of the Drawings

[0011]

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[0012] [Detailed Description] (Overview of Embodiment) An overview of some exemplary embodiments of the present disclosure will be described. This overview is provided as a prelude to the detailed description that follows and is intended to provide a basic understanding of the embodiments by simplifying and explaining some concepts of one or more embodiments, and is not intended to limit the scope of the invention or disclosure. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variation) or a plurality of embodiments (examples or variations) disclosed herein.

[0013] This overview is not an exhaustive overview of all possible embodiments, nor is it intended to identify important elements of all embodiments or to delineate the scope of some or all aspects. Its sole purpose is to present, in a simplified form, some concepts of one or more embodiments as a prelude to the more detailed description presented later.

[0014] A test load device according to one embodiment includes a plurality of current sources to be connected to a plurality of outputs of a multi-channel power system, each current source being digitally controllable in current amount, and a controller capable of independently controlling the current amounts generated by the plurality of current sources.

[0015] According to this configuration, it is possible to test a multi-channel power system under conditions close to an actual machine.

[0016] In one embodiment, the controller may include a random number generator that generates a pseudo-random pattern, and in a first mode, control the current amounts of the plurality of current sources based on the pseudo-random pattern.

[0017] In one embodiment, the controller may further include a memory for storing the pseudo-random pattern generated by the random number generator.

[0018] In one embodiment, in response to the assertion of an alert signal from a power management circuit of a multi-channel power system, the controller may store in a memory the time of the assertion in association with a pseudo-random pattern generated by a random number generator. Thereby, the current waveform at the time of an error occurrence can be verified.

[0019] In one embodiment, in the second mode, the controller may be able to control the current amounts of a plurality of current sources based on the pseudo-random pattern held in the memory. Thereby, the test can be performed again with the same current waveform.

[0020] In one embodiment, the controller may include an RTC (Real Time Clock). The controller may use the date and time data generated by the RTC as a seed for the pseudo-random pattern.

[0021] In one embodiment, in the third mode, the controller may control the current amounts of a plurality of current sources based on a predefined waveform pattern.

[0022] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate. Also, the embodiments are illustrative and not restrictive of the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention.

[0023] In this specification, the phrase "member A is in a state of being connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their coupling.

[0024] Similarly, the state where "member C is provided between member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0025] FIG. 1 is a block diagram of a test load device 100 according to an embodiment. The test load device 100 is connected to a multi-channel power supply system 200 which is a system under test.

[0026] The multi-channel power supply system 200 includes a PMIC 210 and a plurality of power blocks 220_1 to 220_m (m≥2). Each of the power blocks 220_1 to 220_m (m≥2) can be any one of a buck converter, a boost converter, a buck-boost converter, and a linear regulator. The PMIC 210 controls each power block 220_i (i = 1, 2... m) and stabilizes the output voltage V OUTi to a predetermined target level V REFi .

[0027] When an abnormality occurs in any one of the power blocks 220_1 to 220_m or inside the PMIC 210, the PMIC 210 asserts an alert signal ALART. The alert signal ALART is supplied to the test load device 100.

[0028] The test load device 100 includes a plurality of current sources 110_1 to 110_m and a controller 120.

[0029] The plurality of current sources 110_1 to 110_m are connected to the plurality of outputs of the power blocks 220_1 to 220_m of the multi-channel power supply system 200. Each current source 110_i sinks a load current I OUTi . Each current source 110_i is configured to be digitally controllable such that the amount of the load current I OUT[i] corresponds to a digital control signal ICTRL[i].

[0030] The controller 120 supplies control signals ICTRL[1] to ICTRL[m] to a plurality of current sources 110_1 to 110_m, and independently controls the amounts of load current I OUT1 ~I OUTm .

[0031] The above is the configuration of the test load device 100. Next, its operation will be described.

[0032] FIG. 2 is a waveform diagram for explaining the operation of the test load device 100. At time t0, the operation of the test load device 100 starts. The controller 120 controls a plurality of current sources 110_1 to 110_m, and randomly changes the amounts of a plurality of load currents I OUT1 ~I OUTm . Thereby, the state of the actual load of the multi-channel power supply system 200 can be simulated. Note that the load fluctuation test by the test load device 100 can be executed over several hours to several days.

[0033] At time t1, when the combination of the amounts and waveforms of the amounts of a plurality of load currents I OUT1 ~I OUTm satisfies a certain specific condition, some abnormality occurs in the multi-channel power supply system 200, and an alert signal ALART is asserted. It is desirable that the test load device 100 records the time t1 when the alert signal ALART is asserted in association with the position of the current waveform. Thereby, the load conditions that cause an abnormality in the multi-channel power supply system 200 can be specified.

[0034] FIG. 3 is a block diagram showing a configuration example of the controller 120. The controller 120 includes a random number generator 130, an RTC 132, a distributor 140, an arbitrary waveform generator 150, and a control logic circuit 160. The control logic circuit 160 integrally controls the entire controller 120.

[0035] The controller 120 operates in a first mode to a third mode. In the figure, it is assumed that the mode control signal MODE takes 1 in the first mode, 2 in the second mode, and 3 in the third mode.

[0036] (First mode) In the first mode, the random number generator 130, the RTC 132, and the distributor 140 mainly operate. The random number generator 130 generates a pseudo-random pattern PRBS using the seed SEED. As the seed SEED, the time information generated by the RTC 132 can be used. In the first mode, the pseudo-random pattern PRBS generated by the random number generator 130 is supplied to the distributor 140.

[0037] The distributor 140 extracts the bit sequence of the pseudo-random pattern PRBS at a predetermined rate and generates a plurality of control signals ICTRL[1] to ICTRL[m]. The controller 120 periodically updates the seed of the random number generator 130 using the time information of the RTC 132.

[0038] As a result, a plurality of load currents I OUT1 ~I OUTm can be randomly changed.

[0039] The pseudo-random pattern PRBS generated by the random number generator 130 during the test is written into the waveform memory 152. The waveform memory 152 may be a storage medium such as an SD card. Thereby, after the load fluctuation test, it is possible to verify what load current has flowed.

[0040] An alert signal ALART is input to the control logic circuit 160. The control logic circuit 160 records the time of assertion of the alert signal ALART in association with the pseudo-random pattern PRBS. Thereby, after the load fluctuation test, it is possible to verify what load current causes an abnormality in the multi-channel power supply system 200.

[0041] (Second mode) The second mode is a mode that reproduces the load fluctuation test in the first mode that has already been performed. As described above, the pseudo-random pattern PRBS generated by the random number generator 130 is stored in the waveform memory 152.

[0042] In the second mode, the waveform regenerator 154 reads the pseudo-random pattern PRBS from the waveform memory 152 and supplies it as the waveform pattern PTN to the distributor 140. In the second mode, the distributor 140 extracts the waveform pattern PTN supplied from the arbitrary waveform generator 150 at a predetermined rate and generates a plurality of control signals ICTRL[1] to ICTRL[m].

[0043] According to the second mode, the same load fluctuation as in the first mode that has already been performed can be reproduced.

[0044] As described above, the time when the alert signal ALART is asserted is recorded in the waveform memory 152. Therefore, the pseudo-random pattern PRBS may be read from a little before the assertion time of this alert signal ALART. Thereby, in a situation where an abnormality is likely to occur, the multi-channel power supply system 200 can be repeatedly tested.

[0045] (Third mode) The third mode is a mode in which the load currents I OUT1 ~I OUTn change according to a pattern predetermined by the tester of the test, rather than randomly. An arbitrary waveform generator 150 is provided with a waveform memory 156 in relation to the third mode. Waveform data WAVE describing the waveforms of the load currents I OUT1 ~I OUTn of a plurality of channels can be written into the waveform memory 156. The waveform may be based on an arbitrary function such as a sine wave or a triangular wave, or may be a waveform captured from the actual load current of the multi-channel power supply system 200.

[0046] In the third mode, the waveform regenerator 154 reads the waveform data WAVE from the waveform memory 156 and supplies it as the waveform pattern PTN to the distributor 140. In the third mode, the distributor 140 extracts the waveform pattern PTN supplied from the arbitrary waveform generator 150 at a predetermined rate and generates a plurality of control signals ICTRL[1] to ICTRL[m].

[0047] Figure 4 is a circuit diagram showing a configuration example of the current source 110_i. The current source 110_i includes a D / A converter 112 and a V / I converter 114. The D / A converter 112 converts the control signal ICTRL[i] into an analog control voltage V CTRL [i]. The V / I converter 114 converts the control voltage V CTRL [i] into a load current I OUTi .

[0048] The V / I converter 114 includes an NMOS transistor M1, a sense resistor Rs, an amplifier 116, and a sense amplifier 118. The amplifier 116 amplifies the control voltage V CTRL [i] and supplies it to the gate of the NMOS transistor M1. The NMOS transistor M1 operates as a source follower circuit, and a voltage V S = V CTRL[i] - V TH(gs) is generated at the source of the NMOS transistor M1. V TH(gs) is the threshold voltage of the NMOS transistor M1. A bipolar transistor may be used instead of the NMOS transistor M1, in which case it becomes an emitter follower circuit.

[0049] The load current I OUTi flowing through the sense resistor Rs is expressed by the following equation and changes linearly with respect to the control signal ICTRL[i]. I OUTi = Vs / Rs = (V CTRL[i] - V TH(gs) ) / Rs

[0050] Note that the threshold voltage V TH(gs) is affected by variations and temperature fluctuations. Therefore, it is preferable that the amount of the load current I OUTi can be monitored. For current monitoring, a sense amplifier 118 is provided. The sense amplifier 118 amplifies the voltage drop Vs of the sense resistor Rs and generates a current detection signal ISENSE. By using the current detection signal ISENSE, the load current I OUTi can be calibrated.

[0051] FIG. 5 is a circuit diagram showing another configuration example of the current source 110_i. The V / I converter 114 includes an error amplifier 119 instead of the amplifier 116. The error amplifier 119 amplifies the error between the current detection signal ISENSE and the control voltage V CTRL [i] and supplies it to the gate of the NMOS transistor M1. Due to the error amplifier 119, feedback is applied so that the current detection signal ISENSE approaches the control voltage V CTRL [i]. According to this configuration, a highly reproducible load current I TH(gs) can be generated without being affected by variations or fluctuations in the threshold voltage V OUTi of the NMOS transistor M1.

[0052] The embodiments are illustrative, and those skilled in the art will understand that various modifications are possible for each component and combination of each processing process, and such modifications are also within the scope of the present disclosure or the present invention. Hereinafter, such modifications will be described.

[0053] The current source 110 may be a current output type D / A converter.

[0054] In the embodiment, the test load device 100 is operable in the first mode to the third mode, but it may be configured to operate only in the first mode or the third mode, or alternatively, it may be configured such that the first mode and the second mode are switchable, or the first mode and the third mode are switchable.

[0055] The embodiments described using specific terms merely show the principles and applications of the present invention, and many modifications and arrangement changes are allowed in the embodiments without departing from the idea of the present invention defined in the claims.

[0056] (Appendix) The following techniques are disclosed in this specification.

[0057] (Item 1) A plurality of current sources to be connected to a plurality of outputs of a multi-channel power supply system, each current source being digitally controllable in terms of the amount of current, and a plurality of current sources, A controller capable of independently controlling the amount of current generated by the plurality of current sources, A test load device comprising the same.

[0058] (Item 2) The controller includes a random number generator that generates a pseudo-random pattern, and in a first mode, controls the amount of current of the plurality of current sources based on the pseudo-random pattern. The test load device according to Item 1.

[0059] (Item 3) The controller further includes a memory for storing the pseudo-random pattern generated by the random number generator. The test load device according to Item 2.

[0060] (Item 4) In response to the assertion of an alert signal from the power management circuit of the multi-channel power supply system, the controller stores the time of the assertion in the memory in association with the pseudo-random pattern generated by the random number generator. The test load device according to Item 3.

[0061] (Item 5) In a second mode, the controller is capable of controlling the amount of current of the plurality of current sources based on the pseudo-random pattern held in the memory. The test load device according to Item 3 or 4.

[0062] (Item 6) The controller includes an RTC (Real Time Clock), The controller uses the date and time data generated by the RTC as a seed for the pseudo-random pattern. The test load device according to any one of Items 2 to 5.

[0063] (Item 7) The controller controls the current amounts of the plurality of current sources based on a predefined waveform pattern in the third mode, and the test load device according to any one of items 1 to 6.

[0064] (Item 8) A test method for a multi-channel power supply system, A step of connecting a plurality of current sources to a plurality of outputs of the multi-channel power supply system, wherein each current source has a digitally controllable current amount, A step of independently controlling the current amounts generated by the plurality of current sources, A test method comprising:

[0065] (Item 9) Further comprising a step of generating a pseudo-random pattern, The test method according to item 8, wherein in the first mode, the current amounts of the plurality of current sources are controlled based on the pseudo-random pattern.

[0066] (Item 10) The test method according to item 9, further comprising a step of storing the pseudo-random pattern in a memory.

[0067] (Item 11) The test method according to item 10, further comprising a step of storing the time of the assertion in the memory in association with the pseudo-random pattern in response to the assertion of an alert signal from the power management circuit of the multi-channel power supply system.

[0068] (Item 12) The test method according to item 10 or 11, further comprising a step of being able to control the current amounts of the plurality of current sources based on the pseudo-random pattern held in the memory in the second mode.

[0069] (Item 13) Further comprising a step of counting the date and time by an RTC (Real Time Clock), The test method according to any one of Items 9 to 12, wherein date and time data generated by the RTC is used as a seed for the pseudo-random pattern.

Explanation of Signs

[0070] 100 Test load device 110 Current source 112 D / A converter 114 V / I converter M1 NMOS transistor Rs Sense resistor 116 Amplifier 118 Sense amplifier 120 Controller 200 Multi-channel power supply system 210 PMIC 220 Power supply block 130 Random number generator 132 RTC 140 Distributor 150 Arbitrary waveform generator 152 Waveform memory 154 Waveform reproducer 156 Waveform memory 160 Control logic circuit

Claims

1. A plurality of current sources to be connected to a plurality of outputs of a multi-channel power supply system, each current source having a digitally controllable current amount, and a plurality of current sources, A controller capable of independently controlling the current amounts generated by the plurality of current sources, A test load device comprising:

2. The test load device according to claim 1, wherein the controller includes a random number generator that generates a pseudo-random pattern, and in a first mode, controls the current amounts of the plurality of current sources based on the pseudo-random pattern.

3. The test load device according to claim 2, wherein the controller further includes a memory that stores the pseudo-random pattern generated by the random number generator.

4. The test load device according to claim 3, wherein the controller stores, in the memory, the time of the assertion in association with the pseudo-random pattern generated by the random number generator in response to the assertion of an alert signal from a power management circuit of the multi-channel power supply system.

5. The test load device according to claim 3 or 4, wherein the controller is capable of controlling the current amounts of the plurality of current sources based on the pseudo-random pattern held in the memory in a second mode.

6. The controller includes an RTC (Real Time Clock), The test load device according to any one of claims 2 to 4, wherein the controller uses date and time data generated by the RTC as a seed for the pseudo-random pattern.

7. The test load device according to any one of claims 1 to 4, wherein the controller controls the current amounts of the plurality of current sources based on a predefined waveform pattern in a third mode.

8. A test method for a multi-channel power supply system, Connecting a plurality of current sources to a plurality of outputs of the multi-channel power supply system, each current source having a digitally controllable current amount, Independently controlling the current amounts generated by the plurality of current sources, A test method comprising:

9. Further comprising a step of generating a pseudo-random pattern, The test method according to claim 8, wherein in a first mode, the current amounts of the plurality of current sources are controlled based on the pseudo-random pattern.

10. The test method according to claim 9, further comprising a step of storing the pseudo-random pattern in a memory.

11. The test method according to claim 10, further comprising the step of storing, in the memory, the time of the assertion in association with the pseudo-random pattern in response to the assertion of an alert signal from a power management circuit of the multi-channel power system.

12. The test method according to claim 10 or 11, further comprising, in a second mode, the step of being able to control the amount of current of the plurality of current sources based on the pseudo-random pattern held in the memory.

13. further comprising the step of counting the date and time by an RTC (Real Time Clock), The test method according to any one of claims 9 to 11, wherein date and time data generated by the RTC is used as a seed of the pseudo-random pattern.

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