Fault diagnosis circuit, vibration device, and physical quantity sensor

Abstract

To provide a fault diagnosis circuit that, even if a reference voltage temporarily varies, reduces the possibility that it makes a wrong diagnosis that a failure occurs in a circuit for generating the reference voltage.SOLUTION: A failure diagnosis circuit carrying out a failure diagnosis of a reference voltage generation circuit monitors a reference voltage to be supplied to a first circuit from the reference voltage generation circuit, and when a state where the reference voltage is not included in a predetermined range continues for a predetermined time, diagnoses that a failure occurs in the reference voltage generation circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a fault diagnosis circuit, a vibration device, and a physical quantity sensor.

Background Art

[0002] Currently, in various systems and electronic devices, physical quantity sensors capable of detecting various physical quantities, such as gyro sensors for detecting angular velocity and acceleration sensors for detecting acceleration, are widely used. In recent years, for example, in order to construct a system that requires high reliability, such as a system mounted on a vehicle, a physical quantity sensor may be required to have a function of diagnosing its own faults. In addition, in recent years, in order to construct a highly reliable system, a physical quantity sensor that outputs detection information of a physical quantity as digital data with high noise resistance is used. Generally, such a physical quantity sensor includes a physical quantity detection element and a physical quantity detection circuit that generates an analog signal corresponding to the detected physical quantity based on the signal output from the physical quantity detection element, converts it into a digital signal by an analog / digital conversion circuit, and then performs digital signal processing.

[0003] Patent Document 1 describes a power supply monitoring circuit that monitors whether the power supply voltage is within a predetermined range. For example, by applying the power supply monitoring circuit described in Patent Document 1, a physical quantity sensor that diagnoses its own faults can be realized.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the physical quantity sensor to which the power supply monitoring circuit described in Patent Document 1 is applied, when the reference voltage temporarily fluctuates outside a predetermined range due to the operation of a signal processing circuit that processes a signal output from a physical quantity detection element or an analog / digital conversion circuit that converts the output signal of the signal processing circuit into a digital signal, there is a risk of misjudging that the circuit that generates the reference voltage has failed.

Means for Solving the Problems

[0006] One aspect of the failure diagnosis circuit according to the present invention is a failure diagnosis circuit that diagnoses the failure of a reference voltage generation circuit, monitors the reference voltage supplied from the reference voltage generation circuit to the first circuit, and diagnoses that the reference voltage generation circuit has failed when a state where the reference voltage is not included in a predetermined range continues for a predetermined time.

[0007] One aspect of the vibration device according to the present invention is equipped with one aspect of the failure diagnosis circuit.

[0008] One aspect of the physical quantity sensor according to the present invention is equipped with one aspect of the failure diagnosis circuit.

Brief Description of the Drawings

[0009]

Figure 1

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Figure 12

Embodiments for Carrying Out the Invention

[0010] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0011] Hereinafter, a physical quantity sensor that detects angular velocity and acceleration as physical quantities will be described as an example.

[0012] 1. First Embodiment 1-1. Configuration of the Physical Quantity Sensor FIG. 1 is a functional block diagram of the physical quantity sensor according to the first embodiment. The physical quantity sensor 1 according to the first embodiment includes a physical quantity detection circuit 2, an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y.

[0013] The acceleration detection elements 4X and 4Y are physical quantity detection elements that detect acceleration as a physical quantity. The acceleration detection element 4X detects the acceleration in the X-axis direction, and the acceleration detection element 4Y detects the acceleration in the Y-axis direction orthogonal to the X-axis. For example, the acceleration detection elements 4X and 4Y may be elements that have a capacitance in which drive electrodes and detection electrodes (not shown) are arranged, the charge amount of the capacitance changes according to the acceleration, and a signal corresponding to the charge amount is output. The acceleration detection elements 4X and 4Y may be, for example, MEMS (Micro Electro Mechanical Systems) elements.

[0014] The angular velocity detection element 3 is a physical quantity detection element that detects angular velocity as a physical quantity. In the present embodiment, the angular velocity detection element 3 detects the angular velocity around the Z-axis orthogonal to the X-axis and the Y-axis. For example, the angular velocity detection element 3 may be an element that has a vibrating piece in which drive electrodes and detection electrodes (not shown) are arranged, the magnitude of the vibration of the vibrating piece changes according to the angular velocity, and a signal corresponding to the magnitude of the vibration is output. The angular velocity detection element 3 may be, for example, an element that has a so-called double T-shaped crystal vibrating piece having two T-shaped drive vibrating arms.

[0015] The physical quantity detection circuit 2 includes an angular velocity signal processing circuit 10, an acceleration signal processing circuit 20, a temperature sensor 30, a reference voltage generation circuit 40, a selection circuit 50, an analog / digital conversion circuit 60, a digital signal processing circuit 70, a failure diagnosis circuit 80, a control circuit 90, a storage unit 100, an interface circuit 110, and an oscillation circuit 120. The physical quantity detection circuit 2 may be realized, for example, by a one-chip integrated circuit. Note that the physical quantity detection circuit 2 may have a configuration in which some of these elements are omitted or changed, or other elements are added.

[0016] The reference voltage generation circuit 40 generates various reference voltages based on the power supply voltage VDD and the ground voltage VSS supplied from outside the physical quantity detection circuit 2. In the present embodiment, the reference voltage generation circuit 40 generates a power supply voltage VGR and a common voltage VCMGR as reference voltages to be supplied to the angular velocity signal processing circuit 10. Further, the reference voltage generation circuit 40 generates a power supply voltage VACC and a common voltage VCMACC as reference voltages to be supplied to the acceleration signal processing circuit 20. Further, the reference voltage generation circuit 40 generates a full-scale voltage VFSAD and a common voltage VCMAD as reference voltages to be supplied to the analog / digital conversion circuit 60. Further, the reference voltage generation circuit 40 generates a power supply voltage VTS and a common voltage VCMTS as reference voltages to be supplied to the temperature sensor 30. Further, the reference voltage generation circuit 40 generates a power supply voltage VLGC as a reference voltage to be supplied to the logic circuit 200. Further, the reference voltage generation circuit 40 generates a power supply voltage VOSC as a reference voltage to be supplied to the oscillation circuit 120.

[0017] The oscillation circuit 120 operates based on the power supply voltage VOSC supplied from the reference voltage generation circuit 40 and generates a clock signal MCK. The oscillation circuit 120 may be configured as, for example, a ring oscillator or a CR oscillation circuit.

[0018] The angular velocity signal processing circuit 10 includes a drive circuit 11 and a detection circuit 12, and operates based on the power supply voltage VGR and the common voltage VCMGR supplied from the reference voltage generation circuit 40.

[0019] The drive circuit 11 generates a drive signal DRVGR for exciting and vibrating the angular velocity detection element 3, and supplies it to the angular velocity detection element 3. For example, the drive signal DRVGR is a rectangular wave signal with the power supply voltage VGR at a high level and the ground voltage VSS at a low level. Also, the drive circuit 11 receives the oscillation current generated by the excitation vibration of the angular velocity detection element 3, and feedback-controls the amplitude level of the drive signal so that the amplitude of this oscillation current is kept constant. When an angular velocity around the Z-axis is applied while the angular velocity detection element 3 is in an excited and vibrating state, the angular velocity detection element 3 detects the angular velocity and outputs a signal corresponding to the angular velocity. In the present embodiment, the signal output from the angular velocity detection element 3 is a differential signal.

[0020] The detection circuit 12 is a detection signal generation circuit that generates a detection signal corresponding to the angular velocity around the Z-axis based on the output signal of the angular velocity detection element 3. Specifically, the detection circuit 12 detects the angular velocity component included in the signal output from the angular velocity detection element 3, and generates and outputs an angular velocity detection signal GRO1 with a voltage level corresponding to the magnitude of the angular velocity component. Also, the detection circuit 12 detects the vibration leakage component included in the signal output from the angular velocity detection element 3, and generates and outputs a vibration leakage signal GRO2 with a voltage level corresponding to the magnitude of the vibration leakage component. In the present embodiment, the angular velocity detection signal GRO1 and the vibration leakage signal GRO2 are differential signals respectively referenced to the common voltage VCMGR.

[0021] Thus, the angular velocity signal processing circuit 10 is a physical quantity signal processing circuit that outputs a drive signal DRVGR for driving the angular velocity detection element 3, and generates a detection signal corresponding to the angular velocity around the Z-axis, which is one of the physical quantities, based on the output signal of the angular velocity detection element 3.

[0022] The acceleration signal processing circuit 20 includes a drive circuit 21, a detection circuit 22X, and a detection circuit 22Y, and operates based on the power supply voltage VACC and the common voltage VCMACC supplied from the reference voltage generation circuit 40. Also, the acceleration signal processing circuit 20 is controlled based on n control signals CTL1 to CTLn supplied from the control circuit 90. n is an integer of 1 or more.

[0023] The drive circuit 21 generates a drive signal DRVACC and outputs it to the acceleration detection elements 4X and 4Y to drive the acceleration detection elements 4X and 4Y. For example, the drive signal DRVACC is a rectangular wave signal with the power supply voltage VACC at a high level and the ground voltage VSS at a low level. When an acceleration in the X-axis direction is applied in this state, the acceleration detection element 4X detects the acceleration and outputs a signal corresponding to the acceleration. Also, when an acceleration in the Y-axis direction is applied, the acceleration detection element 4Y detects the acceleration and outputs a signal corresponding to the acceleration. In this embodiment, the signals respectively output from the acceleration detection elements 4X and 4Y are differential signals.

[0024] The detection circuit 22X is a detection signal generation circuit that generates a detection signal corresponding to the acceleration in the X-axis direction based on the output signal of the acceleration detection element 4X. Specifically, the detection circuit 22X detects the acceleration component included in the signal output from the acceleration detection element 4X, and generates and outputs an X-axis acceleration detection signal AXO with a voltage level corresponding to the magnitude of the acceleration component. In this embodiment, the X-axis acceleration detection signal AXO is a differential signal with respect to the common voltage VCMACC.

[0025] The detection circuit 22Y is a detection signal generation circuit that generates a detection signal corresponding to the acceleration in the Y-axis direction based on the output signal of the acceleration detection element 4Y. Specifically, the detection circuit 22Y detects the acceleration component included in the signal output from the acceleration detection element 4Y, and generates and outputs a Y-axis acceleration detection signal AYO with a voltage level corresponding to the magnitude of the acceleration component. In this embodiment, the Y-axis acceleration detection signal AYO is a differential signal with respect to the common voltage VCMACC.

[0026] Thus, the acceleration signal processing circuit 20 is a physical quantity signal processing circuit that outputs a drive signal DRVACC for driving the acceleration detection elements 4X and 4Y, generates a detection signal corresponding to the acceleration in the X-axis direction, which is one of the physical quantities, based on the output signal of the acceleration detection element 4X, and generates a detection signal corresponding to the acceleration in the Y-axis direction, which is one of the physical quantities, based on the output signal of the acceleration detection element 4Y.

[0027] The temperature sensor 30 detects the temperature based on the power supply voltage VTS and the common voltage VCMTS supplied from the reference voltage generation circuit 40, and outputs a temperature detection signal TSO with a voltage level corresponding to the temperature. The temperature sensor 30 may be, for example, a circuit that utilizes the temperature characteristics of a bandgap reference circuit. In the present embodiment, the temperature detection signal TSO is a differential signal with respect to the common voltage VCMTS.

[0028] The selection circuit 50 selects and outputs any one of the angular velocity detection signal GRO1, the vibration leakage signal GRO2, the X-axis acceleration detection signal AXO, the Y-axis acceleration detection signal AYO, and the temperature detection signal TSO based on the selection signal SEL from the control circuit 90. In the present embodiment, the output signal MXO of the selection circuit 50 is a differential signal.

[0029] The analog / digital conversion circuit 60 operates based on the full-scale voltage VFSAD and the common voltage VCMAD supplied from the reference voltage generation circuit 40. The analog / digital conversion circuit 60 converts the analog signal MXO output from the selection circuit 50 into a digital signal ADO based on various control signals supplied from the control circuit 90 and outputs the digital signal ADO. Specifically, the analog / digital conversion circuit 60 converts the differential signal MXO into a digital signal ADO using the voltage difference between the full-scale voltage VFSAD and the ground voltage VSS as the full scale.

[0030] The digital signal processing circuit 70 processes the digital signal ADO output from the analog / digital conversion circuit 60 based on various control signals supplied from the control circuit 90. For example, the digital signal processing circuit 70 outputs a digital signal DSPO obtained by performing digital filter processing or correction calculation processing on the digital signal ADO.

[0031] The failure diagnosis circuit 80 diagnoses the failure of the reference voltage generation circuit 40. Specifically, the failure diagnosis circuit 80 monitors the common voltage VCMAD, which is the reference voltage supplied from the reference voltage generation circuit 40 to the analog / digital conversion circuit 60, and diagnoses that the reference voltage generation circuit 40 has failed when the state where the common voltage VCMAD is not within the predetermined range continues for a predetermined time. Note that the analog / digital conversion circuit 60 is an example of the "first circuit".

[0032] In this embodiment, the failure diagnosis circuit 80 includes an abnormality determination circuit 81 and a failure diagnosis signal output circuit 82.

[0033] The abnormality determination circuit 81 determines whether the common voltage VCMAD is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result. For example, the abnormality determination signal FLG1 may be a flag signal that is at a high level when the common voltage VCMAD is abnormal and at a low level when the common voltage VCMAD is normal.

[0034] The failure diagnosis signal output circuit 82 diagnoses whether the reference voltage generation circuit 40 has failed based on the abnormality determination signal FLG1 and outputs a failure diagnosis signal FLG2 indicating the diagnosis result. In this embodiment, the common voltage VCMAD fluctuates temporarily at least one of the timing when the analog / digital conversion circuit 60 starts sampling the output signal MXO of the selection circuit 50 and the timing when the sampling ends. Therefore, even if the reference voltage generation circuit 40 has not failed, the abnormality determination circuit 81 may temporarily output an abnormality determination signal FLG1 indicating that the common voltage VCMAD is abnormal. Thus, so as not to misjudge that the reference voltage generation circuit 40 has failed, the failure diagnosis signal output circuit 82 diagnoses that the reference voltage generation circuit 40 has failed when the abnormality determination signal FLG1 continues for a predetermined time indicating that the common voltage VCMAD is abnormal. For example, the failure diagnosis signal FLG2 may be a flag signal that is at a high level when the reference voltage generation circuit 40 has failed and at a low level when the reference voltage generation circuit 40 has not failed.

[0035] The control circuit 90 generates and outputs various control signals, selection signal SEL, and control signals CTL1 to CTLn for controlling the operations of the analog / digital conversion circuit 60, digital signal processing circuit 70, etc. to control the operation of the acceleration signal processing circuit 20.

[0036] The storage unit 100 has a non-volatile memory (not shown), and various trimming data for the angular velocity signal processing circuit 10, acceleration signal processing circuit 20, etc., and coefficient data used for processing by the digital signal processing circuit 70 are stored in the non-volatile memory. The non-volatile memory may be configured as, for example, a MONOS (Metal Oxide Nitride Oxide Silicon) type memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory). Further, the storage unit 100 has a register (not shown), and when the physical quantity detection circuit 2 is powered on, that is, when the voltage of the VDD terminal rises from 0V to a desired voltage, various data stored in the non-volatile memory are transferred to and held in the register, and the various data held in the register may be configured to be supplied to each circuit.

[0037] The interface circuit 110 performs processing to output the digital signal DSPO and the fault diagnosis signal FLG2 in response to a request from an external device. Further, the interface circuit 110 performs processing to read and output data stored in the non-volatile memory and register of the storage unit 100 in response to a request from an external device of the physical quantity detection circuit 2, and processing to write data input from the external device to the non-volatile memory and register of the storage unit 100, etc. The interface circuit 110 may be, for example, an interface circuit of an SPI (Serial Peripheral Interface) bus or an I 2 C (Inter-Integrated Circuit) bus interface circuit.

[0038] The digital signal processing circuit 70, the fault diagnosis signal output circuit 82, the control circuit 90, the memory unit 100, and the interface circuit 110 constitute the logic circuit 200. The logic circuit 200 operates based on the clock signal MCK with the power supply voltage VLGC supplied from the reference voltage generation circuit 40.

[0039] 1-2. Configuration of the Selection Circuit and the Analog / Digital Conversion Circuit FIG. 2 is a diagram showing a configuration example of the selection circuit 50 and the analog / digital conversion circuit 60. In the example of FIG. 2, the selection circuit 50 includes ten low-pass filters 51p, 51n, 52p, 52n, 53p, 53n, 54p, 54n, 55p, 55n and a multiplexer 56.

[0040] The differential signals GRO1_P and GRO1_N that constitute the angular velocity detection signal GRO1 are each subjected to low-pass filter processing by the low-pass filters 51p and 51n and input to the multiplexer 56.

[0041] The differential signals GRO2_P and GRO2_N that constitute the vibration leakage signal GRO2 are each subjected to low-pass filter processing by the low-pass filters 52p and 52n and input to the multiplexer 56.

[0042] The differential signals AXO_P and AXO_N that constitute the X-axis acceleration detection signal AXO are each subjected to low-pass filter processing by the low-pass filters 53p and 53n and input to the multiplexer 56.

[0043] The differential signals AYO_P and AYO_N that constitute the Y-axis acceleration detection signal AYO are each subjected to low-pass filter processing by the low-pass filters 54p and 54n and input to the multiplexer 56.

[0044] The differential signals TSO_P and TSO_N that constitute the temperature detection signal TSO are each subjected to low-pass filter processing by the low-pass filters 55p and 55n and input to the multiplexer 56.

[0045] The multiplexer 56 selects any one of the differential signals of the low-pass filtered differential signals GRO1_P, GRO1_N, the low-pass filtered differential signals GRO2_P, GRO2_N, the low-pass filtered differential signals AXO_P, AXO_N, the low-pass filtered differential signals AYO_P, AYO_N, and the low-pass filtered differential signals TSO_P, TSO_N in response to the selection signal SEL, and outputs them as differential signals MXO_P, MXO_N.

[0046] In the example of FIG. 2, the analog / digital conversion circuit 60 includes a precharge circuit 61, a programmable gain amplifier 62, a successive approximation register (SAR) type analog / digital converter 63, and an SAR control circuit 64.

[0047] The precharge circuit 61 assists the charge by the differential signals MXO_P, MXO_N by charging the input node of the programmable gain amplifier 62 before the conversion process by the successive approximation type analog / digital converter 63 is started in response to the control signal supplied from the control circuit 90.

[0048] The programmable gain amplifier 62 outputs differential signals PO_P, PO_N obtained by amplifying the differential signals MXO_P, MXO_N. The gain of the programmable gain amplifier 62 is variably set according to the type of the differential signal selected as the differential signals MXO_P, MXO_N in response to the control signal supplied from the control circuit 90.

[0049] The successive approximation type analog / digital converter 63 converts the voltage difference of the differential signals PO_P, PO_N into a digital signal ADO with the voltage difference between the full-scale voltage VFSAD and the ground voltage VSS as the full scale, and outputs it.

[0050] The SAR control circuit 64 operates based on the clock signal MCK, and performs processes such as selecting the voltage serving as the comparison reference according to the timing of successive comparison by the successive approximation type analog / digital converter 63 and the comparison result.

[0051] 1-3. Channel Configuration of Time Division Processing As described above, the analog / digital conversion circuit 60 converts the differential signal selected by the selection circuit 50 based on the selection signal SEL into a digital signal ADO and outputs it. That is, the analog / digital conversion circuit 60 processes the angular velocity detection signal GRO1, the vibration leakage signal GRO2, the X-axis acceleration detection signal AXO, the Y-axis acceleration detection signal AYO, and the temperature detection signal TSO in a time division manner and converts them into digital signals respectively.

[0052] FIG. 3 is a diagram showing an example of the channel configuration of the time division processing by the analog / digital conversion circuit 60.

[0053] As shown in FIG. 3, in the first channel, the 3-bit selection signal SEL is "000", and the angular velocity detection signal GRO1 is selected as the input signal of the analog / digital conversion circuit 60 by the selection circuit 50. Therefore, the analog / digital conversion circuit 60 converts the angular velocity detection signal GRO1, specifically the voltage difference between the differential signals GRO1_P and GRO1_N, into a digital signal ADO during the period of the first channel. Thus, in the first channel, processing for the angular velocity detection signal GRO1 is performed.

[0054] In the second channel following the first channel, the 3-bit selection signal SEL is "001", and the vibration leakage signal GRO2 is selected as the input signal of the analog / digital conversion circuit 60 by the selection circuit 50. Therefore, the analog / digital conversion circuit 60 converts the vibration leakage signal GRO2, specifically the voltage difference between the differential signals GRO2_P and GRO2_N, into a digital signal ADO during the period of the second channel. Thus, in the second channel, processing for the vibration leakage signal GRO2 is performed.

[0055] In the third channel following the second channel, the 3-bit selection signal SEL is "010", and the X-axis acceleration detection signal AXO is selected as the input signal of the analog / digital conversion circuit 60 by the selection circuit 50. Therefore, during the period of the third channel, the analog / digital conversion circuit 60 converts the X-axis acceleration detection signal AXO, specifically the voltage difference between the differential signals AXO_P and AXO_N, into the digital signal ADO. Thus, in the third channel, processing for the X-axis acceleration detection signal AXO is performed.

[0056] In the fourth channel following the third channel, the 3-bit selection signal SEL is "011", and the Y-axis acceleration detection signal AYO is selected as the input signal of the analog / digital conversion circuit 60 by the selection circuit 50. Therefore, during the period of the fourth channel, the analog / digital conversion circuit 60 converts the Y-axis acceleration detection signal AYO, specifically the voltage difference between the differential signals AYO_P and AYO_N, into the digital signal ADO. Thus, in the fourth channel, processing for the Y-axis acceleration detection signal AYO is performed.

[0057] In the fifth channel following the fourth channel, the 3-bit selection signal SEL is "100", and the temperature detection signal TSO is selected as the input signal of the analog / digital conversion circuit 60 by the selection circuit 50. Therefore, during the period of the fifth channel, the analog / digital conversion circuit 60 converts the temperature detection signal TSO, specifically the voltage difference between the differential signals TSO_P and TSO_N, into the digital signal ADO. Thus, in the fifth channel, processing for the temperature detection signal TSO is performed.

[0058] After the fifth channel, it returns to the first channel. That is, a plurality of periods from the first channel to the fifth channel are repeated in order. In the digital signal processing circuit 70, the order of the digital filter, the coefficient values, the type of correction operation, the coefficient values, etc. are changed according to the signal to be processed for each channel.

[0059] 1-4. Configuration of Fault Diagnosis Circuit FIG. 4 is a diagram showing a configuration example of a part of a reference voltage generation circuit 40 and a failure diagnosis circuit 80. In the example of FIG. 4, the reference voltage generation circuit 40 includes a bandgap reference circuit 141, resistors 142 and 143, and an operational amplifier 144.

[0060] The bandgap reference circuit 141 is a circuit that uses the bandgap voltage of a semiconductor element to generate a constant full-scale voltage VFSAD that is stable against fluctuations in temperature and power supply voltage VDD. Since the configuration of the bandgap reference circuit is well-known, its illustration and description are omitted.

[0061] The resistors 142 and 143 have the same resistance value R, and the voltage obtained by dividing the full-scale voltage VFSAD by half by the resistors 142 and 143 is supplied to the non-inverting input terminal of the operational amplifier 144.

[0062] The inverting input terminal of the operational amplifier 144 is connected to the output terminal of the operational amplifier 144, and the operational amplifier 144 functions as a voltage follower. Therefore, the output terminal of the operational amplifier 144 has a voltage that is half of the full-scale voltage VFSAD, and this voltage is output from the reference voltage generation circuit 40 as the common voltage VCMAD.

[0063] The failure diagnosis circuit 80 includes comparators 181 and 182, an OR circuit 183, a counter 184, a flag mask circuit 185, and a D-type flip-flop 186.

[0064] The common voltage VCMAD is supplied to the inverting input terminal of the comparator 181, and a predetermined threshold voltage VL is supplied to the non-inverting input terminal of the comparator 181. The output terminal of the comparator 181 becomes a low level when the common voltage VCMAD is equal to or higher than the threshold voltage VL, and becomes a high level when the common voltage VCMAD is lower than the threshold voltage VL.

[0065] A common voltage VCMAD is supplied to the non-inverting input terminal of the comparator 182, and a predetermined threshold voltage VH higher than the threshold voltage VL is supplied to the inverting input terminal of the comparator 182. The output terminal of the comparator 182 becomes low level when the common voltage VCMAD is equal to or lower than the threshold voltage VH, and becomes high level when the common voltage VCMAD is higher than the threshold voltage VH.

[0066] The OR circuit 183 receives the output signals of the comparator 181 and the comparator 182 and outputs a logical OR signal of these signals. That is, the output signal of the OR circuit 183 becomes low level when the output signals of the comparator 181 and the comparator 182 are both low level, and becomes high level when at least one of the output signals of the comparator 181 and the comparator 182 is high level.

[0067] Therefore, the output signal of the OR circuit 183 becomes low level when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, and becomes high level when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH. The comparator 181, 182 and the OR circuit 183 constitute an abnormality determination circuit 81, and the output signal of the OR circuit 183 becomes an abnormality determination signal FLG1. That is, the abnormality determination circuit 81 determines that the common voltage VCMAD is normal when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, and determines that the common voltage VCMAD is abnormal when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH, and outputs an abnormality determination signal FLG1 indicating the determination result.

[0068] Note that the threshold voltages VL and VH may be fixed values or may be variably set in the storage unit 100.

[0069] Counter 184 resets the count value CNT to 0 at the rising edge timing of the clock signal MCK when the abnormality determination signal FLG1 is at the low level, and increments the count value CNT by 1 when the abnormality determination signal FLG1 is at the high level. That is, counter 184 measures the time during which the abnormality determination signal FLG1 remains at the high level in terms of the period of the clock signal MCK, and outputs the count value CNT indicating the measurement result.

[0070] Flag mask circuit 185 compares the count value CNT with the threshold value DTH, and outputs a flag signal FLG1X indicating the comparison result. Specifically, flag mask circuit 185 outputs a low-level flag signal FLG1X when the count value CNT is less than the threshold value DTH, and outputs a high-level flag signal FLG1X when the count value CNT is greater than or equal to the threshold value DTH.

[0071] As described above, even if the reference voltage generation circuit 40 is not faulty, the abnormality determination circuit 81 may temporarily output an abnormality determination signal FLG1 indicating that the common voltage VCMAD is abnormal. Therefore, the threshold value TH is set to a value larger than the value obtained by dividing the maximum time during which the common voltage VCMAD may temporarily become abnormal by the period of the clock signal MCK. Note that the threshold value DTH may be a fixed value or may be variably set in the storage unit 100.

[0072] D flip-flop 186 has the power supply voltage VLGC input to the data input terminal D and the flag signal FLG1X input to the clock input terminal. D flip-flop 186 captures the power supply voltage VLGC at the rising edge timing of the flag signal FLG1X and outputs a high-level fault diagnosis signal FLG2.

[0073] Note that the D-type flip-flop 186 outputs a low-level fault diagnosis signal FLG2 in the initial state after power-on. The fault diagnosis signal FLG2 keeps the high level once it becomes high level. Therefore, the external device can read the fault diagnosis signal FLG2 and determine that the reference voltage generation circuit 40 is faulty if the fault diagnosis signal FLG2 is high level, and the reference voltage generation circuit 40 is not faulty if the fault diagnosis signal FLG2 is low level.

[0074] In the example of FIG. 4, since the common voltage VCMAD is the voltage obtained by dividing the full-scale voltage VFSAD by 2 by the resistors 142 and 143, if the full-scale voltage VFSAD is always abnormal, the common voltage VCMAD will also be always abnormal, and the abnormality determination signal FLG1 will always be high level. Therefore, even when the operational amplifier 144 fails and the common voltage VCMAD becomes always abnormal, or when the bandgap reference circuit 141 fails and the full-scale voltage VFSAD becomes always abnormal, the fault diagnosis signal FLG2 becomes high level, and the fault diagnosis circuit 80 can diagnose that the reference voltage generation circuit 40 is faulty.

[0075] FIG. 5 is a diagram showing an example of waveforms of various signals including the common voltage VCMAD, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generation circuit 40 is not faulty. FIG. 6 is a diagram showing an example of waveforms of various signals including the common voltage VCMAD, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generation circuit 40 is faulty.

[0076] In the examples of FIGS. 5 and 6, the state signal CONV becomes low level during the sampling period in which the analog / digital conversion circuit 60 samples the voltage of the output signal MXO of the selection circuit 50, and the state signal CONV is high level during the conversion period in which the analog / digital conversion circuit 60 holds the sampled voltage and converts it into a digital signal ADO. As shown in FIGS. 5 and 6, in synchronization with the repetition of the first channel to the fifth channel, the analog / digital conversion circuit 60 alternately repeats the sampling period and the conversion period. In FIGS. 1 and 2 described above, the illustration of the state signal CONV is omitted.

[0077] In the present embodiment, in order to reduce the area of the reference voltage generation circuit 40, it is assumed that the supply ability of the full-scale voltage VFSAD to the analog / digital conversion circuit 60 is not always sufficient. Therefore, when switching between the sampling period and the conversion period of the analog / digital conversion circuit 60, the full-scale voltage VFSAD fluctuates greatly, and accordingly, as shown in FIGS. 5 and 6, the common voltage VCMAD also fluctuates greatly. The timing of switching from the conversion period to the sampling period is the timing at which the analog / digital conversion circuit 60 starts sampling the output signal MXO of the selection circuit 50. Also, the timing of switching from the sampling period to the conversion period is the timing at which the analog / digital conversion circuit 60 finishes sampling the output signal MXO of the selection circuit 50.

[0078] In the example of FIG. 5, at the timing when the periodically arriving sampling period and conversion period are switched, the common voltage VCMAD becomes lower than the threshold voltage VL, and as a result, the phenomenon that the abnormality determination signal FLG1 becomes high level only for one period of the clock signal MCK is periodically repeated. Even if the common voltage VCMAD temporarily becomes lower than the threshold voltage VL at the timing when the sampling period and the conversion period are switched, since it does not affect the operation of the analog / digital conversion circuit 60, the reference voltage generation circuit 40 is not malfunctioning. However, if the common voltage VCMAD fluctuates temporarily and the failure diagnosis signal output circuit 82 captures the abnormality determination signal FLG1 at the timing when the abnormality determination signal FLG1 temporarily becomes high level, a high-level failure diagnosis signal FLG2 will be output. And if an external device reads out the high-level failure diagnosis signal FLG2 via the interface circuit 110, the external device will misjudge that the reference voltage generation circuit 40 is malfunctioning.

[0079] Also, in the example of FIG. 6, the reference voltage generation circuit 40 malfunctions and the common voltage VCMAD becomes higher than the threshold voltage VH. Actually, as in the example of FIG. 5, since the common voltage VCMAD fluctuates greatly at the switching between the sampling period and the conversion period of the analog / digital conversion circuit 60, the common voltage VCMAD temporarily falls within the range of not less than the threshold voltage VL and not more than the threshold voltage VH. Therefore, in the example of FIG. 6, contrary to the example of FIG. 5, at the timing when the sampling period and the conversion period are switched, the abnormality determination signal FLG1 temporarily becomes low level. Therefore, if the failure diagnosis signal output circuit 82 captures the abnormality determination signal FLG1 at the timing when the abnormality determination signal FLG1 temporarily becomes low level, a low-level failure diagnosis signal FLG2 will be output. And if an external device reads out the low-level failure diagnosis signal FLG2 via the interface circuit 110, the external device will misjudge that the reference voltage generation circuit 40 is not malfunctioning.

[0080] In contrast, in the present embodiment, when the abnormality determination signal FLG1 remains at a high level continuously for a predetermined time, the failure diagnosis signal output circuit 82 diagnoses that the reference voltage generation circuit 40 has failed and outputs a high-level failure diagnosis signal FLG2.

[0081] Therefore, in the example of FIG. 5, even if the abnormality determination signal FLG1 temporarily becomes high level, the failure diagnosis signal FLG2 continues to maintain a low level. Therefore, even if the external device reads the failure diagnosis signal FLG2 via the interface circuit 110 at an arbitrary timing, it can correctly determine that the reference voltage generation circuit 40 has not failed.

[0082] Also, in the example of FIG. 6, after the failure diagnosis signal FLG2 first becomes high level, even if the abnormality determination signal FLG1 temporarily becomes low level, the failure diagnosis signal FLG2 continues to maintain a high level. Therefore, even if the external device reads the failure diagnosis signal FLG2 via the interface circuit 110 at an arbitrary timing, it can correctly determine that the reference voltage generation circuit 40 has failed.

[0083] 1-5. Procedure of the failure diagnosis circuit processing FIG. 7 is a flowchart showing an example of the procedure of the processing of the failure diagnosis circuit 80. In the flowchart of FIG. 7, the processing of each step may be appropriately interchanged.

[0084] As shown in FIG. 7, first, in step S1, the failure diagnosis signal output circuit 82 of the failure diagnosis circuit 80 sets the failure diagnosis signal FLG2 to no failure. Specifically, the failure diagnosis signal output circuit 82 sets the failure diagnosis signal FLG2 to a low level.

[0085] Next, in step S2, the abnormality determination circuit 81 of the failure diagnosis circuit 80 determines whether or not the common voltage VCMAD is within a predetermined range. In step S2, when the common voltage VCMAD is within the predetermined range, that is, when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, in step S3, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to normal. Specifically, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to a low level.

[0086] On the other hand, in step S2, when the common voltage VCMAD is not within the predetermined range, that is, when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH, in step S4, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to abnormal. Specifically, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to a high level.

[0087] Next, if the common voltage VCMAD returns to within the predetermined range in step S6 before the elapse of the predetermined time in step S5, in step S3, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to normal. Then, the failure diagnosis circuit 80 performs the processing after step S1 again.

[0088] On the other hand, if the common voltage VCMAD does not return to within the predetermined range in step S6 before the elapse of the predetermined time in step S5, in step S7, the failure diagnosis signal output circuit 82 sets the failure diagnosis signal FLG2 to a failure state. Specifically, the failure diagnosis signal output circuit 82 sets the failure diagnosis signal FLG2 to a high level.

[0089] 1-6. Operational Effects In the physical quantity sensor 1 of the first embodiment described above, the physical quantity detection circuit 2 monitors the common voltage VCMAD generated by the reference voltage generation circuit 40 and supplied to the analog / digital conversion circuit 60 to perform a failure diagnosis of the reference voltage generation circuit 40, and includes a failure diagnosis circuit 80 that outputs a failure diagnosis signal FLG2 indicating the result of the failure diagnosis. The failure diagnosis circuit 80 diagnoses that the reference voltage generation circuit 40 has failed when a state where the common voltage VCMAD is not within a predetermined range continues for a predetermined time. Further, when the common voltage VCMAD temporarily fluctuates due to the operation of the analog / digital conversion circuit 60 and is in a state where it is not within the predetermined range, the failure diagnosis circuit 80 diagnoses that the reference voltage generation circuit 40 has not failed unless this state continues for a predetermined time. Therefore, according to the physical quantity sensor 1 of the first embodiment, the failure diagnosis circuit 80 can reduce the risk of misdiagnosing that the reference voltage generation circuit 40 has failed even when the common voltage VCMAD temporarily fluctuates. In particular, the failure diagnosis circuit 80 can reduce the risk of misjudging that the reference voltage generation circuit 40 has failed even when the common voltage VCMAD temporarily fluctuates at the timing when the analog / digital conversion circuit 60 starts sampling or ends sampling of the signal MXO which is an analog signal. For example, even if the supply capacity of the common voltage VCMAD by the reference voltage generation circuit 40 is relatively low, the risk of misjudgment by the failure diagnosis circuit 80 is reduced, so it is possible to reduce the size of the reference voltage generation circuit 40, which is advantageous for cost reduction.

[0090] Specifically, the fault diagnosis circuit 80 includes an abnormality determination circuit 81 that determines whether the common voltage VCMAD is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result, and a fault diagnosis signal output circuit 82 that diagnoses whether the reference voltage generation circuit 40 is faulty based on the abnormality determination signal FLG1 and outputs a fault diagnosis signal FLG2 indicating the diagnosis result. When the abnormality determination signal FLG1 continuously indicates that the common voltage VCMAD is abnormal for a predetermined time, the fault diagnosis signal output circuit 82 diagnoses that the reference voltage generation circuit 40 is faulty. Therefore, when the common voltage VCMAD fluctuates temporarily, even if the abnormality determination circuit 81 temporarily outputs an abnormality determination signal FLG1 indicating that the common voltage VCMAD is abnormal, the possibility that the fault diagnosis signal output circuit 82 erroneously outputs a fault diagnosis signal FLG2 indicating that the reference voltage generation circuit 40 is faulty can be reduced.

[0091] Also, in the physical quantity sensor 1 of the first embodiment, when the reference voltage generation circuit 40 is faulty, the fault diagnosis signal output circuit 82 can promptly output a fault diagnosis signal FLG2 indicating that the reference voltage generation circuit 40 is faulty. For example, the upper system can meet the requirement of a short FTTI. FTTI is an abbreviation for Fault Tolerant Time Interval, which is the time from when an abnormality occurs in the system until it transitions to a safe state.

[0092] Thus, according to this embodiment, the fault diagnosis circuit 80 can reduce the risk of misjudging that the reference voltage generation circuit 40 is faulty, thereby enhancing the reliability of the physical quantity sensor 1.

[0093] 2. Second Embodiment Hereinafter, for the physical quantity sensor of the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, the description of the content overlapping with the first embodiment is omitted or simplified, and mainly the content different from the first embodiment will be described.

[0094] 2-1. Configuration of the Physical Quantity Sensor FIG. 8 is a functional block diagram of the physical quantity sensor according to the second embodiment. The physical quantity sensor 1 according to the second embodiment includes a physical quantity detection circuit 2, an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y, similar to the first embodiment.

[0095] Since the functions of the angular velocity detection element 3, the acceleration detection element 4X, and the acceleration detection element 4Y are the same as those in the first embodiment, the description thereof is omitted.

[0096] Similar to the first embodiment, the physical quantity detection circuit 2 includes an angular velocity signal processing circuit 10, an acceleration signal processing circuit 20, a temperature sensor 30, a reference voltage generation circuit 40, a selection circuit 50, an analog / digital conversion circuit 60, a digital signal processing circuit 70, a control circuit 90, a storage unit 100, an interface circuit 110, an oscillation circuit 120, and a fault diagnosis circuit 130, and may be implemented by, for example, a one-chip integrated circuit. Note that the physical quantity detection circuit 2 may have a configuration in which some of these elements are omitted or changed, or other elements are added.

[0097] Since the functions of the angular velocity signal processing circuit 10, the acceleration signal processing circuit 20, the temperature sensor 30, the reference voltage generation circuit 40, the selection circuit 50, the analog / digital conversion circuit 60, the digital signal processing circuit 70, the control circuit 90, the storage unit 100, the interface circuit 110, and the oscillation circuit 120 are the same as those in the first embodiment, the description thereof is omitted.

[0098] The fault diagnosis circuit 130 performs fault diagnosis of the reference voltage generation circuit 40. Specifically, the fault diagnosis circuit 130 monitors the common voltage VCMACC, which is a reference voltage supplied from the reference voltage generation circuit 40 to the acceleration signal processing circuit 20, which is one of the physical quantity signal processing circuits, and diagnoses that the reference voltage generation circuit 40 is faulty when a state where the common voltage VCMACC is not within a predetermined range continues for a predetermined time. Note that the acceleration signal processing circuit 20 is an example of the "first circuit".

[0099] In the present embodiment, the fault diagnosis circuit 130 includes an abnormality determination circuit 131 and a fault diagnosis signal output circuit 132.

[0100] Based on the abnormality determination signal FLG1, the abnormality determination circuit 131 diagnoses whether the reference voltage generation circuit 40 is faulty and outputs a fault diagnosis signal FLG2 indicating the diagnosis result. It determines whether the common voltage VCMACC is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result. For example, the abnormality determination signal FLG1 may be a flag signal that is at a high level when the common voltage VCMACC is abnormal and at a low level when the common voltage VCMACC is normal.

[0101] Based on the abnormality determination signal FLG1, the fault diagnosis signal output circuit 132 diagnoses whether the reference voltage generation circuit 40 is faulty and outputs a fault diagnosis signal FLG2 indicating the diagnosis result. In this embodiment, at least one of the rising edge and the falling edge of the drive signal DRVACC that drives the acceleration detection elements 4X and 4Y, the common voltage VCMACC fluctuates temporarily. Also, at least one of the rising edge and the falling edge of the control signals CTL1 to CTLn that control the acceleration signal processing circuit 20, the common voltage VCMACC fluctuates temporarily. Therefore, even if the reference voltage generation circuit 40 is not faulty, there is a possibility that the abnormality determination circuit 131 temporarily outputs an abnormality determination signal FLG1 indicating that the common voltage VCMACC is abnormal. Thus, so as not to misjudge that the reference voltage generation circuit 40 is faulty, when the abnormality determination signal FLG1 continuously indicates that the common voltage VCMACC is abnormal for a predetermined time, the fault diagnosis signal output circuit 132 diagnoses that the reference voltage generation circuit 40 is faulty. For example, the fault diagnosis signal FLG2 may be a flag signal that is at a high level when the reference voltage generation circuit 40 is faulty and at a low level when the reference voltage generation circuit 40 is not faulty.

[0102] 2-2. Configuration of the Fault Diagnosis Circuit FIG. 9 is a diagram showing a configuration example of a part of the reference voltage generation circuit 40 and the fault diagnosis circuit 130. In the example of FIG. 9, the reference voltage generation circuit 40 includes a bandgap reference circuit 145, resistors 146 and 147, and an operational amplifier 148.

[0103] The bandgap reference circuit 145 is a circuit that generates a stable and constant power supply voltage VACC against fluctuations in temperature and power supply voltage VDD by utilizing the bandgap voltage of semiconductor elements. Since the configuration of the bandgap reference circuit is well-known, its illustration and description are omitted.

[0104] Resistors 146 and 147 have the same resistance value R, and the voltage obtained by dividing the power supply voltage VACC in half by resistors 146 and 147 is supplied to the non-inverting input terminal of operational amplifier 148.

[0105] The inverting input terminal of operational amplifier 148 is connected to the output terminal of operational amplifier 148, and operational amplifier 148 functions as a voltage follower. Therefore, the voltage at the output terminal of operational amplifier 148 is half of the power supply voltage VACC, and this voltage is output from the reference voltage generation circuit 40 as the common voltage VCMACC.

[0106] The fault diagnosis circuit 130 includes comparators 231 and 232, an OR circuit 233, a counter 234, a flag mask circuit 235, and a D-type flip-flop 236.

[0107] The common voltage VCMACC is supplied to the inverting input terminal of comparator 231, and a predetermined threshold voltage VL is supplied to the non-inverting input terminal of comparator 231. The output terminal of comparator 231 becomes a low level when the common voltage VCMACC is equal to or higher than the threshold voltage VL, and becomes a high level when the common voltage VCMACC is lower than the threshold voltage VL.

[0108] The common voltage VCMACC is supplied to the non-inverting input terminal of comparator 232, and a predetermined threshold voltage VH higher than the threshold voltage VL is supplied to the inverting input terminal of comparator 232. The output terminal of comparator 232 becomes a low level when the common voltage VCMACC is equal to or lower than the threshold voltage VH, and becomes a high level when the common voltage VCMACC is higher than the threshold voltage VH.

[0109] The logical OR circuit 233 receives the output signal of the comparator 231 and the output signal of the comparator 232, and outputs the logical OR signal of these signals. That is, the output signal of the logical OR circuit 233 becomes low level when both the output signal of the comparator 231 and the output signal of the comparator 232 are low level, and becomes high level when at least one of the output signal of the comparator 231 and the output signal of the comparator 232 is high level.

[0110] Therefore, the output signal of the logical OR circuit 233 becomes low level when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, and becomes high level when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH. The comparator circuits 231, 232 and the logical OR circuit 233 constitute the abnormality determination circuit 131, and the output signal of the logical OR circuit 233 becomes the abnormality determination signal FLG1. That is, the abnormality determination circuit 131 determines that the common voltage VCMACC is normal when the common voltage VCMACC is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, determines that the common voltage VCMACC is abnormal when the common voltage VCMACC is lower than the threshold voltage VL or higher than the threshold voltage VH, and outputs the abnormality determination signal FLG1 indicating the determination result.

[0111] Note that the threshold voltages VL and VH may be fixed values, or may be variably set in the storage unit 100.

[0112] The counter 234 resets the count value CNT to 0 when the abnormality determination signal FLG1 is low level at the rising edge timing of the clock signal MCK, and increments the count value CNT by 1 when the abnormality determination signal FLG1 is high level. That is, the counter 234 measures the time during which the abnormality determination signal FLG1 continues to be high level in the period of the clock signal MCK, and outputs the count value CNT indicating the measurement result.

[0113] The flag mask circuit 235 compares the count value CNT with the threshold value DTH and outputs a flag signal FLG1X indicating the comparison result. Specifically, when the count value CNT is less than the threshold value DTH, the flag mask circuit 235 outputs a low-level flag signal FLG1X, and when the count value CNT is greater than or equal to the threshold value DTH, the flag mask circuit 235 outputs a high-level flag signal FLG1X.

[0114] As described above, even if the reference voltage generation circuit 40 is not faulty, the abnormality determination circuit 131 may temporarily output an abnormality determination signal FLG1 indicating that the common voltage VCMACC is abnormal. Therefore, the threshold value TH is set to a value greater than the value obtained by dividing the maximum time during which the common voltage VCMACC may temporarily become abnormal by the period of the clock signal MCK. Note that the threshold value DTH may be a fixed value or may be variably set in the storage unit 100.

[0115] The D flip-flop 236 has the power supply voltage VLGC input to the data input terminal D and the flag signal FLG1X input to the clock input terminal. The D flip-flop 236 captures the power supply voltage VLGC at the timing of the rising edge of the flag signal FLG1X and outputs a fault diagnosis signal FLG2.

[0116] Note that the D flip-flop 236 outputs a low-level fault diagnosis signal FLG2 in the initial state after power-on. Then, once the fault diagnosis signal FLG2 becomes high level, it continues to hold the high level. Therefore, the external device can read the fault diagnosis signal FLG2 and determine that the reference voltage generation circuit 40 is faulty if the fault diagnosis signal FLG2 is high level, and that the reference voltage generation circuit 40 is not faulty if the fault diagnosis signal FLG2 is low level.

[0117] In the example of Fig. 9, since the common voltage VCMACC is the voltage obtained by dividing the power supply voltage VACC in half by resistors 146 and 147, if the power supply voltage VACC is always abnormal, the common voltage VCMACC will also always be abnormal, and the abnormality determination signal FLG1 will always be at a high level. Therefore, even when the operational amplifier 148 fails and the common voltage VCMACC always becomes abnormal, or when the bandgap reference circuit 145 fails and the power supply voltage VACC always becomes abnormal, the fault diagnosis signal FLG2 becomes high level, and the fault diagnosis circuit 130 can diagnose that the reference voltage generation circuit 40 has failed.

[0118] Fig. 10 is a diagram showing an example of waveforms of various signals including the common voltage VCMACC, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generation circuit 40 is not faulty. Fig. 11 is a diagram showing an example of waveforms of various signals including the common voltage VCMACC, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generation circuit 40 is faulty.

[0119] In the present embodiment, in order to reduce the area of the reference voltage generation circuit 40, it is assumed that the supply ability of the power supply voltage VACC to the acceleration signal processing circuit 20 is not always sufficient. Since the high level of the drive signal DRVACC is the power supply voltage VACC, at the timings of the rising edge and falling edge of the drive signal DRVACC, the power supply voltage VACC fluctuates greatly, and accordingly, as shown in Figs. 10 and 11, the common voltage VCMACC also fluctuates greatly. Similarly, since the high level of the control signals CTL1 to CTLn is the power supply voltage VACC, at the timings of the rising edge and falling edge of each of the control signals CTL1 to CTLn, the power supply voltage VACC fluctuates greatly, and accordingly, as shown in Figs. 10 and 11, the common voltage VCMACC also fluctuates greatly.

[0120] In the example of FIG. 10, at the rising edge and falling edge timings of the drive signal DRVACC and at the rising edge and falling edge timings of each of the control signals CTL1 to CTLn, the common voltage VCMACC becomes lower than the threshold voltage VL. As a result, the phenomenon that the abnormality determination signal FLG1 becomes high level for only one period of the clock signal MCK is periodically repeated. Even if the common voltage VCMACC temporarily becomes lower than the threshold voltage VL at the timings of these edges, since it does not affect the operation of the acceleration signal processing circuit 20, the reference voltage generation circuit 40 is not malfunctioning. However, if the common voltage VCMACC temporarily fluctuates and the failure diagnosis signal output circuit 132 captures the abnormality determination signal FLG1 at the timing when the abnormality determination signal FLG1 temporarily becomes high level, a high-level failure diagnosis signal FLG2 will be output. And if an external device reads out the high-level failure diagnosis signal FLG2 via the interface circuit 110, the external device will erroneously determine that the reference voltage generation circuit 40 is malfunctioning.

[0121] Also, in the example of FIG. 11, the reference voltage generation circuit 40 malfunctions and the common voltage VCMACC becomes higher than the threshold voltage VH. Actually, similar to the example of FIG. 10, since the common voltage VCMACC fluctuates greatly at the rising edge and falling edge timings of the drive signal DRVACC and at the rising edge and falling edge timings of each of the control signals CTL1 to CTLn, the common voltage VCMACC temporarily falls within the range of equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH. Therefore, in the example of FIG. 11, contrary to the example of FIG. 10, at the timings of these edges, the abnormality determination signal FLG1 temporarily becomes low level. Therefore, if the failure diagnosis signal output circuit 132 captures the abnormality determination signal FLG1 at the timing when the abnormality determination signal FLG1 temporarily becomes low level, a low-level failure diagnosis signal FLG2 will be output. And if an external device reads out the low-level failure diagnosis signal FLG2 via the interface circuit 110, the external device will erroneously determine that the reference voltage generation circuit 40 is not malfunctioning.

[0122] On the other hand, in this embodiment, when the abnormality determination signal FLG1 continues to be at a high level for a predetermined time, the failure diagnosis signal output circuit 132 diagnoses that the reference voltage generation circuit 40 has failed and outputs a high-level failure diagnosis signal FLG2.

[0123] Therefore, in the example of FIG. 10, even if the abnormality determination signal FLG1 temporarily becomes high level, the failure diagnosis signal FLG2 continues to maintain a low level. Therefore, even if the external device reads the failure diagnosis signal FLG2 via the interface circuit 110 at an arbitrary timing, it can make a correct determination that the reference voltage generation circuit 40 is not faulty.

[0124] Also, in the example of FIG. 11, after the failure diagnosis signal FLG2 first becomes high level, even if the abnormality determination signal FLG1 temporarily becomes low level, the failure diagnosis signal FLG2 continues to maintain a high level. Therefore, even if the external device reads the failure diagnosis signal FLG2 via the interface circuit 110 at an arbitrary timing, it can make a correct determination that the reference voltage generation circuit 40 has failed.

[0125] 2-3. Procedure of the failure diagnosis circuit processing FIG. 12 is a flowchart showing an example of the procedure of the processing of the failure diagnosis circuit 130. In the flowchart of FIG. 12, the processing of each step may be appropriately interchanged.

[0126] As shown in FIG. 12, first, in step S11, the failure diagnosis signal output circuit 132 of the failure diagnosis circuit 130 sets the failure diagnosis signal FLG2 to no failure. Specifically, the failure diagnosis signal output circuit 132 sets the failure diagnosis signal FLG2 to a low level.

[0127] Next, in step S12, the abnormality determination circuit 131 of the failure diagnosis circuit 130 determines whether the common voltage VCMACC is within a predetermined range. In step S12, when the common voltage VCMACC is within the predetermined range, that is, when the common voltage VCMACC is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, in step S13, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to normal. Specifically, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to a low level.

[0128] On the other hand, in step S12, when the common voltage VCMACC is not within the predetermined range, that is, when the common voltage VCMACC is lower than the threshold voltage VL or higher than the threshold voltage VH, in step S14, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to abnormal. Specifically, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to a high level.

[0129] Next, if the common voltage VCMACC returns within the predetermined range in step S16 before the elapse of the predetermined time in step S15, in step S13, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to normal. Then, the failure diagnosis circuit 130 performs the processing after step S11 again.

[0130] On the other hand, if the common voltage VCMAD does not return within the predetermined range in step S16 before the elapse of the predetermined time in step S15, in step S17, the failure diagnosis signal output circuit 132 sets the failure diagnosis signal FLG2 to a failure state. Specifically, the failure diagnosis signal output circuit 132 sets the failure diagnosis signal FLG2 to a high level.

[0131] In the physical quantity sensor 1 of the second embodiment described above, the physical quantity detection circuit 2 monitors the common voltage VCMACC generated by the reference voltage generation circuit 40 and supplied to the acceleration signal processing circuit 20 to perform a failure diagnosis of the reference voltage generation circuit 40, and includes a failure diagnosis circuit 130 that outputs a failure diagnosis signal FLG2 indicating the result of the failure diagnosis. When the state where the common voltage VCMACC is not included in the predetermined range continues for a predetermined time, the failure diagnosis circuit 130 diagnoses that the reference voltage generation circuit 40 has failed. Further, when the common voltage VCMACC temporarily fluctuates due to the operation of the acceleration signal processing circuit 20 and is not included in the predetermined range, the failure diagnosis circuit 130 diagnoses that the reference voltage generation circuit 40 has not failed unless the state continues for a predetermined time. Therefore, according to the physical quantity sensor 1 of the second embodiment, the failure diagnosis circuit 130 can reduce the risk of misdiagnosing that the reference voltage generation circuit 40 has failed even when the common voltage VCMACC temporarily fluctuates. In particular, the failure diagnosis circuit 130 can reduce the risk of misjudging that the reference voltage generation circuit 40 has failed even when the common voltage VCMACC temporarily fluctuates at the rising edge and falling edge of the drive signal DRVACC for driving the acceleration detection elements 4X and 4Y and at the rising edge and falling edge of each of the control signals CTL1 to CTLn for controlling the acceleration signal processing circuit 20. For example, even if the supply capacity of the common voltage VCMACC by the reference voltage generation circuit 40 is relatively low, the risk of misjudgment by the failure diagnosis circuit 130 is reduced, so that the size of the reference voltage generation circuit 40 can be reduced, which is advantageous for cost reduction.

[0132] Specifically, the fault diagnosis circuit 130 includes an abnormality determination circuit 131 that determines whether the common voltage VCMACC is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result, and a fault diagnosis signal output circuit 132 that diagnoses whether the reference voltage generation circuit 40 has failed based on the abnormality determination signal FLG1 and outputs a fault diagnosis signal FLG2 indicating the diagnosis result. And when the abnormality determination signal FLG1 continuously indicates that the common voltage VCMACC is abnormal for a predetermined time, the fault diagnosis signal output circuit 132 diagnoses that the reference voltage generation circuit 40 has failed. Therefore, when the common voltage VCMACC fluctuates temporarily, even if the abnormality determination circuit 131 temporarily outputs an abnormality determination signal FLG1 indicating that the common voltage VCMACC is abnormal, the possibility that the fault diagnosis signal output circuit 132 erroneously outputs a fault diagnosis signal FLG2 indicating that the reference voltage generation circuit 40 has failed can be reduced.

[0133] Also, in the physical quantity sensor 1 of the first embodiment, when the reference voltage generation circuit 40 has failed, the fault diagnosis signal output circuit 132 can quickly output a fault diagnosis signal FLG2 indicating that the reference voltage generation circuit 40 has failed. Thus, for example, the upper system can meet the requirement of short FTTI.

[0134] As described above, according to this embodiment, the fault diagnosis circuit 130 can reduce the possibility of misjudging that the reference voltage generation circuit 40 has failed, so the reliability of the physical quantity sensor 1 can be improved.

[0135] 3. Modification For example, in the above first embodiment, the fault diagnosis circuit 80 monitors the common voltage VCMAD, and in the above second embodiment, the fault diagnosis circuit 130 monitors the common voltage VCMACC. However, the fault diagnosis circuit may monitor both the common voltage VCMAD and the common voltage VCMACC. That is, the physical quantity sensor 1 may have a configuration combining the first embodiment and the second embodiment.

[0136] Also, in the above-described first embodiment, the failure diagnosis circuit 80 monitors the common voltage VCMAD, but it may monitor the full-scale voltage VFSAD, or may monitor any voltage that varies with the variation of the full-scale voltage VFSAD. Also, in the above-described second embodiment, the failure diagnosis circuit 130 monitors the common voltage VCMACC, but it may monitor the power supply voltage VACC, or may monitor any voltage that varies with the variation of the power supply voltage VACC. Alternatively, the failure diagnosis circuit may monitor any voltage that varies with the variation of the power supply voltage VGR such as the common voltage VCMGR, or may monitor the power supply voltage VGR.

[0137] Also, in each of the above embodiments, the physical quantity sensor 1 detects both the angular velocity and the acceleration as physical quantities, but it may detect either one of the angular velocity and the acceleration. Also, the physical quantity sensor 1 may detect a physical quantity other than the angular velocity and the acceleration as the physical quantity.

[0138] Also, in each of the above embodiments, the analog / digital conversion circuit 60 receives a differential signal and converts the differential signal into a digital signal ADO, but a single-ended signal may be input and the single-ended signal may be converted into a digital signal ADO.

[0139] Also, in each of the above embodiments, the physical quantity sensor 1 includes the angular velocity detection element 3, the acceleration detection element 4X, and the acceleration detection element 4Y. However, a sensor having only a part of these physical quantity detection elements may also be used. Further, in each of the above embodiments, the angular velocity detection element is only the angular velocity detection element 3 that detects the angular velocity around the Z axis. However, one or both of an angular velocity detection element that detects the angular velocity around the X axis and an angular velocity detection element that detects the angular velocity around the Y axis may be added, and a drive circuit and a detection circuit may be connected to each of the angular velocity detection elements. Also, in each of the above embodiments, two acceleration detection elements, i.e., the acceleration detection element 4X that detects the acceleration in the X-axis direction and the acceleration detection element 4Y that detects the acceleration in the Y-axis direction, are provided. However, an acceleration detection element that detects the acceleration in the Z-axis direction may be further added, and a drive circuit and a detection circuit may be connected to each of the acceleration detection elements. Further, the physical quantity sensor 1 may include a physical quantity detection element that detects a physical quantity other than angular velocity and acceleration, for example, a physical quantity detection element that detects physical quantities such as angular acceleration, velocity, and force.

[0140] Also, in each of the above embodiments, an example in which the vibrating piece of the angular velocity detection element 3 is a double-T-shaped crystal vibrating piece was given. However, the vibrating pieces of the physical quantity detection elements that detect various physical quantities may be, for example, a tuning fork type or a comb tooth type, or a vibrating piece type having a shape such as a triangular prism, a quadrangular prism, or a cylindrical column. Further, as the material of the vibrating piece of the physical quantity detection element, instead of quartz (SiO2), for example, a piezoelectric material such as a piezoelectric single crystal such as lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), or a piezoelectric ceramic such as lead zirconate titanate (PZT) may be used, or a silicon semiconductor may be used. Also, the vibrating piece of the physical quantity detection element may have a structure in which, for example, a piezoelectric thin film such as zinc oxide (ZnO) or aluminum nitride (AlN) sandwiched between drive electrodes is disposed on a part of the surface of the silicon semiconductor.

[0141] In addition, in each of the above embodiments, the piezoelectric angular velocity detection element 3 and the capacitive acceleration detection elements 4X and 4Y have been exemplified. However, the physical quantity detection elements for detecting various physical quantities are not limited to piezoelectric or capacitive elements, and may be elements such as electromagnetic, eddy current, optical, and strain gauge types. Further, the detection method of the physical quantity detection element is not limited to the vibration type, and may be, for example, optical, rotational, or fluidic types.

[0142] In addition, in each of the above embodiments, the physical quantity sensors for detecting angular velocity and acceleration have been exemplified. However, the fault diagnosis circuit of the present invention is applicable to any physical quantity sensor that operates based on a reference voltage generated by a reference voltage generation circuit such as a regulator. Examples of such physical quantity sensors include, for example, FOG (Fiber Optic Gyroscope), temperature sensors, pressure sensors, gas sensors, humidity sensors, etc. Further, the fault diagnosis circuit of the present invention is applicable not only to physical quantity sensors but also to vibration devices. Vibration devices include, for example, vibration type physical quantity sensors in which a physical quantity detection element vibrates, and oscillators that oscillate an oscillator to generate an oscillation signal. Examples of such oscillators include oscillators including crystal oscillators and silicon MEMS (Micro Electro Mechanical Systems) resonators. Since these vibration devices are provided with the fault diagnosis circuit of the present invention, high reliability can be realized.

[0143] The above-described embodiments and modifications are merely examples and are not necessarily limited thereto. For example, it is also possible to appropriately combine each embodiment and each modification.

[0144] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations having the same functions, methods, and results, or configurations having the same objectives and effects. Further, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Further, the present invention includes configurations that exhibit the same operational effects as the configurations described in the embodiments or configurations that can achieve the same objectives. Further, the present invention includes configurations in which known techniques are added to the configurations described in the embodiments.

[0145] The following content is derived from the above-described embodiments and modifications.

[0146] One aspect of the failure diagnosis circuit is a failure diagnosis circuit that performs failure diagnosis of a reference voltage generation circuit, monitors the reference voltage supplied from the reference voltage generation circuit to the first circuit, and diagnoses that the reference voltage generation circuit has failed when the state where the reference voltage is not included in a predetermined range continues for a predetermined time.

[0147] This failure diagnosis circuit diagnoses that the reference voltage generation circuit has failed when the state where the reference voltage is not included in a predetermined range continues for a predetermined time.

[0148] Further, when the reference voltage temporarily fluctuates and is not included in a predetermined range, this failure diagnosis circuit does not diagnose that the reference voltage generation circuit has failed unless the state continues for a predetermined time. Therefore, according to this failure diagnosis circuit, it is possible to reduce the risk of misdiagnosing that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates. For example, even if the supply ability of the reference voltage by the reference voltage generation circuit is relatively low, the risk of misjudgment by the failure diagnosis circuit is reduced, so it is possible to reduce the size of the reference voltage generation circuit.

[0149] In one aspect of the failure diagnosis circuit, the first circuit may be an analog / digital conversion circuit that converts an analog signal into a digital signal.

[0150] According to this failure diagnosis circuit, it is possible to reduce the risk of misjudging that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates due to the operation of the analog / digital conversion circuit.

[0151] In one aspect of the failure diagnosis circuit, The first circuit may be a physical quantity signal processing circuit that outputs a drive signal for driving a physical quantity detection element that detects a physical quantity, and generates a detection signal corresponding to the physical quantity based on the output signal of the physical quantity detection element.

[0152] According to this fault diagnosis circuit, even if the reference voltage temporarily fluctuates due to the operation of the physical quantity signal processing circuit, it is possible to reduce the risk of misjudging that the reference voltage generation circuit has failed.

[0153] In one aspect of the fault diagnosis circuit, The reference voltage may temporarily fluctuate at least one of the timing at which the analog / digital conversion circuit starts sampling the analog signal and the timing at which the sampling ends.

[0154] According to this fault diagnosis circuit, even if the reference voltage temporarily fluctuates at the timing when the analog / digital conversion circuit starts sampling the analog signal or the timing when the sampling ends, it is possible to reduce the risk of misjudging that the reference voltage generation circuit has failed.

[0155] In one aspect of the fault diagnosis circuit, The reference voltage may temporarily fluctuate at least one of the rising edge and the falling edge of the drive signal.

[0156] According to this fault diagnosis circuit, even if the reference voltage temporarily fluctuates at the rising edge or the falling edge of the drive signal of the physical quantity detection element, it is possible to reduce the risk of misjudging that the reference voltage generation circuit has failed.

[0157] In one aspect of the fault diagnosis circuit, The reference voltage may temporarily fluctuate at least one of the rising edge and the falling edge of the control signal for controlling the physical quantity signal processing circuit.

[0158] According to this fault diagnosis circuit, even if the reference voltage temporarily fluctuates at the rising edge or falling edge of the control signal of the physical quantity signal processing circuit, the possibility of misjudging that the reference voltage generation circuit has failed can be reduced.

[0159] One aspect of the fault diagnosis circuit is an abnormality determination circuit that determines whether the reference voltage is abnormal and outputs an abnormality determination signal indicating the determination result, and a fault diagnosis signal output circuit that diagnoses whether the reference voltage generation circuit has failed based on the abnormality determination signal and outputs a fault diagnosis signal indicating the diagnosis result, The fault diagnosis signal output circuit may diagnose that the reference voltage generation circuit has failed when the abnormality determination signal continuously indicates that the reference voltage is abnormal for a predetermined time.

[0160] According to this fault diagnosis circuit, when the reference voltage temporarily fluctuates, even if the abnormality determination circuit temporarily outputs an abnormality determination signal indicating that the reference voltage is abnormal, the possibility that the fault diagnosis signal output circuit erroneously outputs a fault diagnosis signal indicating that the reference voltage generation circuit has failed can be reduced.

[0161] Also, according to this fault diagnosis circuit, when the reference voltage generation circuit has failed, the fault diagnosis signal output circuit can quickly output a fault diagnosis signal indicating that the reference voltage generation circuit has failed. Therefore, for example, the upper system can meet the requirement of short FTTI.

[0162] One aspect of the vibration device is equipped with one aspect of the fault diagnosis circuit.

[0163] According to this vibration device, since it is equipped with a fault diagnosis circuit that can reduce the possibility of misdiagnosing that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates, high reliability can be achieved.

[0164] One aspect of the physical quantity sensor is It includes one aspect of the failure diagnosis circuit.

[0165] According to this physical quantity sensor, since it is equipped with a failure diagnosis circuit that can reduce the risk of misdiagnosing that the reference voltage generation circuit has failed even when the reference voltage fluctuates temporarily, high reliability can be achieved.

Explanation of symbols

[0166] 1... Physical quantity sensor, 2... Physical quantity detection circuit, 3... Angular velocity detection element, 4X... Acceleration detection element, 4Y... Acceleration detection element, 10... Angular velocity signal processing circuit, 11... Drive circuit, 12... Detection circuit, 20... Acceleration signal processing circuit, 21... Drive circuit, 22X... Detection circuit, 22Y... Detection circuit, 30... Temperature sensor, 40... Reference voltage generation circuit, 50... Selection circuit, 51p, 51n, 52p, 52n, 53p, 53n, 54p, 54n, 55p, 55n... Low-pass filter, 56... Multiplexer, 60... Analog / digital conversion circuit, 61... Precharge circuit, 62... Programmable gain amplifier, 63... Successive approximation analog / digital converter, 64... SAR control circuit, 70... Digital signal processing circuit, 80... Failure diagnosis circuit, 81... Abnormality determination circuit, 82... Failure diagnosis signal output circuit, 90... Control circuit, 100... Memory unit, 110... Interface circuit, 120... Oscillation circuit, 130... Failure diagnosis circuit, 131... Abnormality determination circuit, 132... Failure diagnosis signal output circuit, 141... Bandgap reference circuit, 142... Resistor, 143... Resistor, 144... Operational amplifier, 145... Bandgap reference circuit, 146... Resistor, 147... Resistor, 148... Operational amplifier, 181... Comparator, 182... Comparator, 183... OR circuit, 184... Counter, 185... Flag mask circuit, 186... D-type flip-flop, 200... Logic circuit, 231... Comparator, 232... Comparator, 233... OR circuit, 234... Counter, 235... Flag mask circuit, 236... D-type flip-flop

Claims

1. A fault diagnosis circuit for performing fault diagnosis of a reference voltage generation circuit, which monitors a reference voltage supplied from the reference voltage generation circuit to a first circuit, and diagnoses that the reference voltage generation circuit is faulty when a state where the reference voltage is not within a predetermined range continues for a predetermined time.

2. In claim 1, the first circuit is an analog / digital conversion circuit that converts an analog signal into a digital signal, and the fault diagnosis circuit.

3. In claim 1, the first circuit is a physical quantity signal processing circuit that outputs a drive signal for driving a physical quantity detection element that detects a physical quantity, and generates a detection signal corresponding to the physical quantity based on an output signal of the physical quantity detection element, and the fault diagnosis circuit.

4. In claim 2, the reference voltage temporarily fluctuates at least one of a timing when the analog / digital conversion circuit starts sampling the analog signal and a timing when the sampling ends, and the fault diagnosis circuit.

5. In claim 3, the reference voltage temporarily fluctuates at least one of a rising edge timing and a falling edge timing of the drive signal, and the fault diagnosis circuit.

6. In claim 3, the reference voltage temporarily fluctuates at least one of a rising edge timing and a falling edge timing of a control signal for controlling the physical quantity signal processing circuit, and the fault diagnosis circuit.

7. In any one of claims 1 to 6, an abnormality determination circuit that determines whether the reference voltage is abnormal and outputs an abnormality determination signal indicating the determination result; and a fault diagnosis signal output circuit that diagnoses whether the reference voltage generation circuit is faulty based on the abnormality determination signal and outputs a fault diagnosis signal indicating the diagnosis result, wherein the fault diagnosis signal output circuit diagnoses that the reference voltage generation circuit is faulty when the abnormality determination signal continues for a predetermined time indicating that the reference voltage is abnormal, and the fault diagnosis circuit.

8. A vibration device including the fault diagnosis circuit according to any one of claims 1 to 6.

9. A physical quantity sensor including the fault diagnosis circuit according to any one of claims 1 to 6.

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