Magnetic memory

Abstract

To provide a magnetic memory to improve operational reliability.SOLUTION: A magnetic memory of an embodiment includes: a magnetic body configured to store data and shift the data from a first area to a second area by moving a magnetic domain wall due to a shift operation; a wiring spaced from the magnetic body, and applying a write magnetic field to the magnetic body during a write operation; and a control circuit that passes a shift current through the magnetic body to shift the data and passes a write current for generating the write magnetic field to the wiring. A write current Iw includes a first pulse 91 supplied to the wiring and a second pulse 92 supplied to the wiring after the first pulse 91. A pulse width W2 of the second pulse 92 is smaller than a pulse width W1 of the first pulse 91.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to magnetic memories. [Background technology]

[0002] 2. Description of the Related Art Magnetic memories are known that function as memory devices by moving domain walls in a magnetic material when a current is passed through the magnetic material. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0076723 [Patent Document 2] Japanese Patent Publication No. 2023-37504 [Non-patent literature]

[0004] [Non-Patent Document 1] MP Proenca, et al., “Deterministic and time resolved thermo-magnetic switching in a nickel nanowire”, Scientific reports, Volume 9, P1-8, November 22, 2019 Summary of the Invention [Problem to be solved by the invention]

[0005] Improves operational reliability. [Means for solving the problem]

[0006] The magnetic memory of the embodiment includes a magnetic body configured to store data and shift the data from a first area to a second area by moving a domain wall due to a shift operation, a wiring spaced apart from the magnetic body and applying a write magnetic field to the magnetic body during a write operation, and a control circuit that passes a shift current through the magnetic body to shift the data and a write current through the wiring to generate the write magnetic field, wherein the write current includes a first pulse supplied to the wiring and a second pulse supplied to the wiring after the first pulse, and the pulse width of the second pulse is smaller than the pulse width of the first pulse. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a magnetic memory according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing the basic configuration of a memory unit of the magnetic memory according to the first embodiment. [Figure 3] FIG. 3 is a waveform diagram showing a write current of the magnetic memory according to the first embodiment. [Figure 4] FIG. 3 is a diagram schematically showing the magnetization state of the magnetic body during a write operation of the magnetic memory according to the first embodiment. [Figure 5] FIG. 4 is a diagram showing temperature changes of a magnetic body during a write operation of the magnetic memory according to the first embodiment. [Figure 6] FIG. 3 is a diagram showing an example of the operation of the magnetic memory according to the first embodiment. [Figure 7] FIG. 4 is a diagram showing experimental results of the magnetic memory according to the first embodiment. [Figure 8] FIG. 10 is a waveform diagram showing a write current of the magnetic memory according to the second embodiment. [Figure 9] FIG. 10 is a plan view showing a structural example of a magnetic memory according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a structural example of a magnetic memory according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] 1 to 10, magnetic memories according to embodiments will be described. In the following description, elements having the same function and configuration will be given the same reference numerals. Furthermore, in the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) that are given reference numerals with distinguishing numbers / letters at the end are not necessarily distinguished from one another, the reference numerals will be omitted.

[0009] (1) First embodiment The magnetic memory of the first embodiment will be described with reference to FIGS.

[0010] (a) Configuration example FIG. 1 is a block diagram showing an example of the configuration of a magnetic memory according to an embodiment.

[0011] As shown in FIG. 1, the magnetic memory 1 of the embodiment includes a memory core circuit 10 and a control circuit 20.

[0012] The memory core circuit 10 stores data. The memory core circuit 10 includes a plurality of magnetic bodies 100, a plurality of wirings FL and BL, etc. The magnetic bodies 100 are components of a memory unit MU that functions as a data storage section. The internal configuration of the memory core circuit 10 will be described later.

[0013] The control circuit 20 is electrically connected to the memory core circuit 10. The control circuit 20 controls various memory operations of the memory core circuit 10. For example, the control circuit 20 controls the execution of write operations, shift operations, and read operations on the memory core circuit 10.

[0014] The magnetic memory 1 of this embodiment is a magnetic memory that realizes the function of a memory device by utilizing the movement (shift) of domain walls. The magnetic memory 1 of this embodiment is also called a domain wall shift memory or a racetrack memory.

[0015] 2 is a schematic diagram for explaining a configuration example of the memory core circuit 10 of the magnetic memory 1 of the embodiment. In FIG. 2, the basic configuration of a memory unit MU including a magnetic body 100 is illustrated.

[0016] The memory unit MU includes at least a magnetic body 100 and a read element 120. A field line FL, a bit line BL, and a source line SL are provided for the memory unit MU.

[0017] The magnetic body 100 is provided above the substrate 190. The magnetic body 100 is a data storage unit. The magnetic body 100 is also called an MML (Magnetic Memory Line). The magnetic body 100 has a plate-like structure extending in the X direction. The X direction is a direction parallel to the surface of the substrate 190. The magnetic body 100 has perpendicular magnetic anisotropy. The magnetization of the magnetic body 100 is oriented in a direction perpendicular to the surface of the substrate 190 (Z direction).

[0018] The magnetic body 100 includes a plurality of areas 101, 102, and 103. The plurality of areas 101, 102, and 103 are arranged in the X direction. The plurality of areas 101, 102, and 103 are continuous.

[0019] Area 101 is provided at one end of magnetic body 100 in the X direction. Area 101 is a write area. A magnetic field is applied to write data to write area 101. The magnetization direction of write area 101 is controlled according to the data to be written.

[0020] The area 102 is provided at the other end of the magnetic body 100 in the X direction. The area 103 is a read area. Data to be read is transferred into the read area 102.

[0021] A plurality of areas 103 are provided between the write area 101 and the read area 102. The areas 103 are cell areas. Each of the cell areas 103 functions as a memory cell that stores one bit of data. Each cell area 103 includes one magnetic domain. A domain wall DW is formed at the boundary between adjacent magnetic domains (the boundary between two areas with different magnetization directions). Depending on the data to be stored, one magnetic domain may span two or more adjacent cell areas 103.

[0022] The magnetic body 100 may include a constricted portion 109 at the boundary between each of the areas 101, 102, and 103. The dimension of the constricted portion 109 in the Y direction is smaller than the dimension of the cell area 103 in the Y direction. The dimension of the constricted portion 109 in the X direction is smaller than the dimension of the cell area 103 in the X direction. The domain wall DW is likely to stop at the position of the constricted portion 109, which has a relatively small volume inside the magnetic body 100. When data is stored, the domain wall DW exists within the constricted portion 109. When data is shifted, the domain wall DW passes through the cell area 103 and moves from one constricted portion 109 to another constricted portion 109.

[0023] A field line FL serving as wiring is provided below the write area 101 of the magnetic body 100 in the Z direction. The field line FL extends in the Y direction parallel to the surface of the substrate 190. The Y direction is, for example, perpendicular to the X direction. The field line FL is spaced apart from the magnetic body 100. A certain gap is provided between the field line FL and the magnetic body 100. During a data write operation, a write current is supplied into the field line FL. The supply of the write current generates a magnetic field (write magnetic field) applied to the write area 101, centered around the field line FL. The field line FL is also called a write wiring.

[0024] The field line FL includes a metal wiring 30, a yoke (magnetic body) 31, and a thermal resistance layer 32. For example, the surfaces of the metal wiring 30 other than the surface facing the magnetic body 100 are covered with the thermal resistance layer 32. However, the entire surface of the metal wiring 30 may be covered with the thermal resistance layer 32. The yoke 31 is provided between the metal wiring 30 and the thermal resistance layer 32. The metal wiring 30 includes, for example, copper (Cu), tungsten (W), or aluminum (Al). The yoke 31 includes, for example, iron (Fe), nickel (Ni), copper (Cu), or molybdenum (Mo). The thermal resistance layer 32 is formed of, for example, a material having high thermal resistance. The thermal resistance layer 32 is formed of, for example, silicon oxide (SiO2), aluminum oxide (AlO X ), or silicon nitride (SiN), etc.

[0025] By covering the surface of the metal wiring 30 that does not face the magnetic body 100 with the thermal resistance layer 32, heat generated from the field line FL can be efficiently propagated to the magnetic body 100. This allows the temperature of the write area 101 of the magnetic body 100 to be increased by a write current Iw of a relatively small current value. As a result, the magnetic memory 1 of this embodiment can write data using a write current Iw of a low current value based on the principle described below. Therefore, the magnetic memory 1 of this embodiment can reduce power consumption.

[0026] A read element (reproducing element) 120 is provided above the read area 102 of the magnetic body 100 in the Z direction. For example, a non-magnetic conductive layer 129 is provided between the read element 120 and the read area 102. The read element 120 is electrically connected to the read area 102 via the non-magnetic conductive layer 129. The read element 120 reads data shifted within the read area 102.

[0027] The read element 120 is a magnetoresistive effect element such as an MTJ element. When the read element 120 is an MTJ element, the MTJ element 120 includes at least a storage layer 121, a tunnel barrier layer 122, and a reference layer 123. The storage layer 121 and the reference layer 123 form a magnetic tunnel junction (MTJ) via the tunnel barrier layer 122. The storage layer 121 and the reference layer 123 are magnetic layers. The storage layer 121 and the reference layer 123 include, for example, cobalt, iron, boron, or the like. The tunnel barrier layer 122 is a non-magnetic layer. The tunnel barrier layer 122 includes, for example, magnesium oxide.

[0028] The memory layer 121 is provided above the read area 102 of the magnetic body 100 in the Z direction, with a nonmagnetic conductive layer 129 interposed therebetween. The reference layer 123 is provided above the memory layer 121 in the Z direction. The tunnel barrier layer 122 is provided between the memory layer 121 and the reference layer 123.

[0029] The magnetization direction of the storage layer 121 is variable and changes depending on the leakage magnetic field of the magnetization of the read area 102.

[0030] The magnetization direction of the reference layer 123 is invariable. "The magnetization direction of the reference layer 123 is invariable" means that the magnetization direction of the reference layer 123 does not change due to the leakage magnetic field from the magnetic body 100.

[0031] The bit line BL is connected to the read element 120. For example, the bit line BL is connected to the reference layer 123 of the MTJ element 120 via a contact portion CP.

[0032] A source line SL is connected to the magnetic body 100. For example, the source line SL is connected to one end of the magnetic body 100 on the write area 101 side. In response to the operation of the magnetic memory 1, a current flows between the bit line BL and the source line SL.

[0033] The magnetic memory 1 of this embodiment is manufactured by a well-known technique, and therefore, a description of the manufacturing method of the magnetic memory 1 of this embodiment will be omitted.

[0034] In the magnetic memory 1 of this embodiment, during a shift operation, the control circuit 20 passes a shift current (drive current) Is through the magnetic body 100. For example, when the shift current Is flows through the magnetic body 100 from the read area 102 to the write area 101, the domain wall DW in the magnetic body 100 moves from the write area 101 side toward the read area 102 side. The distance the domain wall DW moves is controlled according to the pulse width (supply period of the shift current Is) and current value of the shift current Is. Note that, in this example, the domain wall DW moves in the opposite direction to the direction in which the shift current Is flows. However, depending on the material of the magnetic body 100, the members stacked on the magnetic body 100, or the manufacturing conditions of the magnetic body 100, the domain wall DW can also be controlled to move in the same direction as the direction in which the shift current Is flows.

[0035] The data in the cell area 103 to be read is shifted to the read area 102 by a shift operation caused by supplying the shift current Is.

[0036] During a read operation, a read current Ir is supplied to the read element 120. In the MTJ element 120, which is the read element, the magnetization direction of its memory layer 121 corresponds to the magnetization direction of the read area 102 based on the leakage magnetic field of the magnetic body 100. The resistance value of the MTJ element 120 changes depending on the relative relationship (magnetization arrangement state) between the magnetization of the memory layer 121 and the magnetization of the reference layer 123. The magnetoresistance of the MTJ element 120 when the magnetization direction of the memory layer 121 is the same as the magnetization direction of the reference layer 123 is different from the magnetization direction of the MTJ element 120 when the magnetization direction of the memory layer 121 is different from the magnetization direction of the reference layer 123. The resistance value of the MTJ element 120 changes depending on the data read to the read area 102. Based on the determination result of the resistance value of the MTJ element 120, the data in the read area 102 is read. The data in the read area 102 is determined based on the amount of change in the read current Ir or the magnitude of the voltage, which corresponds to the magnitude of the magnetic resistance of the MTJ element 120.

[0037] When writing data, a write current Iw is supplied to the field line FL. The write current generates a write magnetic field centered on the field line FL. The write magnetic field is applied to the write area 101. This sets the direction of magnetization in the write area 101 depending on the direction of the write magnetic field. The direction of the write magnetic field depends on the direction of the write current Iw. The direction of the write current Iw is controlled depending on the data to be written.

[0038] In the magnetic memory 1 of this embodiment, during a write operation, the control circuit 20 passes a write current Iw including a plurality of pulses through the field line FL.

[0039] This allows the magnetic memory 1 of this embodiment to improve reliability when writing data.

[0040] (b) Example of operation An example of the operation of the magnetic memory of this embodiment will be described with reference to FIGS.

[0041] (b-1) Basic example of write current 3 is a waveform diagram showing a basic example of the write current Iw used in the write operation of the magnetic memory 1 of this embodiment. The horizontal axis of the waveform diagram in FIG. 3 corresponds to time (pulse width). The vertical axis of the waveform diagram in FIG. 3 corresponds to the absolute value of the current value (pulse height) i of the write current Iw.

[0042] 3, in the magnetic memory 1 of this embodiment, the write current Iw includes multiple pulses 91 and 92. In the example of Fig. 3, the write current Iw includes two pulses 91 and 92. However, the number of pulses included in the write current Iw may be three or more.

[0043] In the write current Iw including two pulses 91 and 92, first, a first pulse 91 is supplied into the field line FL After the first pulse 91 is supplied, a second pulse 92 is supplied into the field line FL.

[0044] The first pulse 91 and the second pulse 92 have a current value i0. The current value of the second pulse 92 is substantially equal to the current value of the first pulse 91. However, the current value of the second pulse 92 may be different from the current value of the first pulse 91. For example, the current value of the second pulse 92 may be set to a current value within a range from a value 10% higher than the current value of the first pulse 91 to a value 10% lower than the current value of the first pulse 91.

[0045] The pulse width of the first pulse 91 is, for example, 100 ns (nanoseconds) or less. The pulse width W2 of the second pulse 92 is smaller than the pulse width W1 of the first pulse 91. The pulse width W2 has a magnitude within a range of 2.5% to 30% of the pulse width W1. For example, when the pulse width W1 is 100 ns, the pulse width W2 is 2.5 ns to 30 ns.

[0046] In this embodiment, the pulse width of the current is defined based on the full width at half maximum (FWHM). That is, the pulse width at half the maximum value (i0) of the write current Iw (i0 / 2) is considered to be the pulse width of that current (pulse). The comparison of the magnitude relationship between the pulse width W1 of the first pulse 91 and the pulse width W2 of the second pulse 92 can be performed as long as the reference current value is the same. For example, the pulse width may be the maximum current value, the pulse width at 80% of the current value, or the pulse width at 30% of the current value. Regardless of the reference current value used to define the pulse width, the pulse width of the second pulse 92 is smaller than the pulse width of the first pulse 91.

[0047] An interval T1 is provided between the first pulse 91 and the second pulse 92. The current value of the write current Iw during the interval T1 is substantially zero. The interval T1 is smaller than the pulse width W1 of the first pulse 91. For example, the interval T1 is preferably equal to or larger than the pulse width W2 of the second pulse 92. The interval T1 has a size within a range of 5% to 75% of the pulse width W1. For example, when the pulse width W1 is 100 ns, the interval T1 is equal to or larger than 5 ns and equal to or smaller than 75 ns. In this case, the interval T1 is more preferably 30 ns to 50 ns. However, the interval T1 may also be smaller than the pulse width W2.

[0048] At time t1, the pulse 91 begins to rise. At time t2, the current value of the pulse 91 reaches "i0". From time t2 to time t3, the current value of the pulse 91 is maintained at "i0". At time t3, the pulse 91 begins to fall. At time t4, the current value of the pulse 91 becomes zero.

[0049] During the period from time t4 to time t5, the current value of the write current Iw is preferably substantially zero. Note that during the period from time t4 to time t5, if the control circuit 20 is configured with transistors, the current value of the write current Iw may be determined according to the leakage current of the transistors, and may be set within a range of, for example, 10% or less of +i0 and 10% or more of -i0.

[0050] At time t5, the pulse 92 begins to rise. At time t6, the current value of the pulse 92 reaches "i0". From time t6 to time t7, the current value of the pulse 92 is maintained at "i0". At time t7, the pulse 92 begins to fall. At time t8, the current value of the pulse 92 becomes zero.

[0051] The period from time t5 to time t8 is shorter than the period from time t1 to time t4, and the period from time t6 to time t7 is shorter than the period from time t2 to just before time t3.

[0052] At the rising edge of each of the pulses 91 and 92, the current value of the pulses 91 and 92 may overshoot to "i0" or more.

[0053] 3, the current values of the pulses 91 and 92 of the write current Iw are shown as absolute values. However, depending on the data to be written to the magnetic body 100, the write current Iw has a positive polarity (positive current value) or a negative polarity (negative current value).

[0054] For example, when writing first data (e.g., data "0"), a write current Iw of positive polarity is supplied to the field line FL. When writing second data (e.g., data "1") different from the first data, a write current Iw of negative polarity is supplied to the field line FL. The direction in which the write current Iw for writing the second data flows in the field line FL is opposite to the direction in which the write current Iw for writing the first data flows in the field line FL.

[0055] <Principle> With reference to FIGS. 4 and 5, a phenomenon occurring in the magnetic memory 1 of this embodiment due to the supply of the write current Iw to the field line FL will be described.

[0056] FIG. 4 is a diagram illustrating a phenomenon occurring in the magnetic body 100 due to a write current Iw including multiple pulses 91 and 92 in this embodiment. FIG. 5 is a graph illustrating the temperature state of the magnetic body 100. In the graph of FIG. 5, the horizontal axis corresponds to time. In the graph of FIG. 5, the vertical axis represents normalized temperature. In FIG. 5, the pulse waveform of the write current Iw is shown for comparison with the temperature change of the magnetic body 100. In the write current Iw of the example of FIG. 5, the pulse width of the first pulse 91 is set to 100 ns, the pulse width of the second pulse 92 is set to 20 ns, and the interval T1 between the two pulses 91 and 92 is set to 30 ns. The current value i0 of each pulse 91 and 92 is 19 mA.

[0057] As shown in FIG. 4(a), before the start of a write operation, the write area 101 of the magnetic body 100 has magnetization 199 in a certain direction.

[0058] When the write operation starts, a write current Iw is supplied to the field line FL. Of the multiple pulses 91 and 92 contained in the write current Iw, a first pulse 91 flows through the field line FL. The supply of the write current Iw causes the field line FL to generate heat. The temperature of the field line FL rises.

[0059] A write magnetic field is generated around the field line FL by supplying the first pulse 91. The generated write magnetic field is applied to the write area 101 of the magnetic body 100.

[0060] 5, the temperature of the magnetic body 100 changes in response to the supply of current to the field line FL (application of the generated write magnetic field). When the supply of the first pulse 91 to the field line FL starts, the temperature of the magnetic body 100 (write area 101) rises.

[0061] 4(b), the applied write magnetic field causes the direction of magnetization 199 in the write area 101 to align with the direction of the write magnetic field. For example, the magnetization direction in the write area 101 is reversed from the magnetization direction in the initial state.

[0062] At a certain time tx during the supply of the first pulse 91 of the write current Iw, the supply of the first pulse 91 causes the temperature of the write area 101 to reach a high temperature exceeding a certain threshold temperature (critical temperature) Qa.

[0063] The supply of the first pulse 91 is stopped after a period corresponding to the pulse width W1 of the first pulse 91 has elapsed. When the supply of the first pulse 91 is stopped and the current value of the write current Iw becomes zero, the write magnetic field disappears.

[0064] 4(c), when the supply of the first pulse 91 is stopped and the magnetic field applied to the magnetic body 100 becomes zero, the magnetic field in the write area 101 in a high temperature state fluctuates. As a result, the anisotropy of the magnetization 199x in the write area 101 of the magnetic body 100 disappears.

[0065] During the interval T1 between the two pulses 91 and 92, the temperature of the write area 101 drops below the threshold temperature Qa. During this interval T1, the state of magnetization in the write area 101 becomes relaxed. As shown in Figure 4(d), the direction of magnetization 199 in the write area 101 becomes unstable due to the influence of magnetic field fluctuations.

[0066] After a period T1 has elapsed since the supply of the first pulse 91 was stopped, a second pulse 92 flows through the field line FL.

[0067] By supplying the second pulse 92, a write magnetic field is generated again around the field line FL. The generated write magnetic field is applied to the write area 101. The application of the write magnetic field caused by the supply of the second pulse 92 causes the temperature of the write area 101 to rise again.

[0068] As shown in FIG. 4( e ), the direction of magnetization 199 in write area 101 is set to a direction corresponding to the direction of the write magnetic field generated by second pulse 92 .

[0069] The supply of the second pulse 92 is stopped after a period corresponding to the pulse width W2 of the second pulse 92 has elapsed, and as a result, the write magnetic field applied to the write area 101 disappears.

[0070] During the supply period of the second pulse 92 corresponding to the pulse width W2, the temperature of the write area 101 does not exceed the threshold temperature Qa because the pulse width W2 is smaller than the pulse width W1. When the second pulse 92 is supplied, the field line FL and the write area 101 do not become hot. Therefore, when the second pulse 92 is supplied, the magnetization 199 of the write area 101 is fixed in the direction corresponding to the direction of the write magnetic field, without the magnetic field of the magnetic body 100 fluctuating due to a high temperature.

[0071] In this way, when the second pulse 92 is supplied, the direction of the magnetization 199 in the write area 101 is set to a direction corresponding to the data to be written at a relatively low temperature.

[0072] As described above, the magnetic memory 1 of this embodiment can write predetermined data using the write current Iw including the two pulses 91 and 92.

[0073] According to this embodiment, even if a write error occurs with a certain probability due to the supply of the first pulse 91, the supply of the second pulse 92 suppresses the temperature rise of the magnetic body 100 and writes data into the magnetic body 100.

[0074] Therefore, the magnetic memory 1 of this embodiment can suppress the occurrence of write errors caused by a rise in temperature of the magnetic body 100.

[0075] (b-2) Operation sequence FIG. 6 is a timing chart for explaining the operation sequence of the magnetic memory of this embodiment.

[0076] One cycle in the operation sequence includes a write operation, a shift operation, and a read operation, and in each cycle, multiple operations are executed in the order of a write operation, a shift operation, and a read operation.

[0077] 6, when a certain cycle SY1 is executed, the magnetic memory 1 of this embodiment executes a write operation. The control circuit 20 causes a write current Iw including a plurality of pulses 91, 92, and 93 to flow through the field line FL.

[0078] 6, the write current Iw-1 includes three pulses 91p, 92p, and 93p. For example, when "0" data is written in the write area 101, the write current Iw-1 has a positive polarity.

[0079] When the write current Iw-1 is supplied, a pulse 91p is supplied into the field line FL, and then a pulse 92p is supplied into the field line FL. After the supply of the pulse 92p, a pulse 93p is supplied into the field line FL. The pulse width W2 of the pulse 92p is smaller than the pulse width W1 of the pulse 91p. The pulse width W3 of the pulse 93p is smaller than the pulse width W1 of the pulse 91p and the pulse width W2 of the pulse 92p. The current values of the pulses 91p, 92p, and 93p are substantially equal. A certain interval T1 is provided between the pulse 91p and the pulse 92p. A certain interval T2 is provided between the pulse 92p and the pulse 93p. For example, the interval T2 is equal to or smaller than the interval T1.

[0080] By supplying the write current Iw-1 including the three pulses 91p, 92p, and 93p, predetermined data (here, "0" data) is written into the write area 101 based on the above-mentioned principle.

[0081] Following the write operation, the magnetic memory 1 of this embodiment executes a shift operation. The control circuit 20 causes a shift current Is including one pulse to flow through the magnetic body 100. The shift current Is has positive polarity.

[0082] As the domain wall moves due to the supply of the shift current Is, the data in the write area 101 and the data in the cell area 103 move, for example, a distance corresponding to the size of one cell area 103 from the write area 101 side to the read area 102 side.

[0083] After the shift operation, the magnetic memory 1 of this embodiment executes a read operation. The control circuit 20 supplies a read current Ir including one pulse to the MTJ element 120, which is a read element. The read current Ir has a positive polarity. The maximum current value of the read current Ir is smaller than the maximum current value of the shift current Is.

[0084] By supplying a read current Ir to the MTJ element 120, data in the read area 102 is read.

[0085] After a read operation in a cycle SY1, the magnetic memory 1 of this embodiment performs a write operation in another cycle SY2. The control circuit 20 passes a write current Iw-2 through the field line FL. When "1" data is written into the write area 101, the write current Iw-2 has negative polarity. The write current Iw-2 flows in the opposite direction to the direction of the write current Iw-1. The write current Iw-2 includes three pulses 91n, 92n, and 93n of negative polarity. The direction of the magnetic field generated by the write current Iw-2 is opposite to the direction of the magnetic field generated by the write current Iw-1.

[0086] When the write current Iw-2 is supplied, after pulse 91n is supplied into the field line FL, pulse 92n is supplied into the field line FL. After pulse 92n is supplied, pulse 93n is supplied into the field line FL. The pulse width W2 of pulse 92n is smaller than the pulse width W1 of pulse 91n. The pulse width W3 of pulse 93n is smaller than the pulse width W1 of pulse 91n and the pulse width W2 of pulse 92p. The current values of pulses 91n, 92n, and 93n are substantially equal. A certain interval T1 is provided between pulse 91n and pulse 92n. A interval T2 equal to or smaller than interval T1 is provided between pulse 92n and pulse 93n.

[0087] Even if the polarity of the write current Iw is negative, by supplying the write current Iw-2 including three pulses 91n, 92n, and 93n, predetermined data (here, "1" data) is written into the write area 101 based on the above-mentioned principle.

[0088] Following the write operation, the magnetic memory 1 of this embodiment executes a shift operation. The control circuit 20 passes a positive shift current Is through the magnetic body 100. As a result, as described above, the data in the magnetic body 100 is shifted toward the read area 102.

[0089] After the shift operation, the magnetic memory 1 of this embodiment executes a read operation. The control circuit 20 supplies a read current Ir of positive polarity to the MTJ element 120. As a result, the data in the read area 102 is read, as described above.

[0090] In this way, the magnetic memory 1 of this embodiment executes one or more cycles SY1 and SY2.

[0091] (c) Summary In the magnetic memory 1 of this embodiment, during a write operation, a write current Iw including a plurality of pulses 91 and 92 flows through the field line FL.

[0092] 7 is a graph showing experimental results of the write operation of the magnetic memory of this embodiment. In the graph of FIG. 7, the horizontal axis represents the voltage for generating the write current (hereinafter referred to as the write voltage). In the graph of FIG. 7, the vertical axis represents the success rate of data writing (hereinafter referred to as the write probability).

[0093] In the graph of Figure 7, the plots of black circles and the characteristics of the solid line show the results of a write operation using a write current including two pulses in this embodiment. The pulse width of the first of the two pulses is set to 100 ns. The pulse width of the second pulse supplied after the first pulse is set to 15 ns. The interval between the first and second pulses is set to 20 ns.

[0094] 7, the plots of white squares and the characteristics of the solid line show the results of a write operation using a write current of one pulse, where the pulse width of the write current is set to 100 ns.

[0095] As the write voltage (write current) increases, the magnetic material enters a high temperature state. Therefore, as shown in Figure 7, when the number of pulses included in the write current is one, the write probability becomes lower than 100% as the write voltage increases due to the influence of magnetic field fluctuations in the magnetic material in a high temperature state.

[0096] In contrast, when the number of pulses included in the write current is two, as in this embodiment, the write probability is maintained at 100% even when the write voltage increases, due to the magnetization being set at a low temperature by supplying a second pulse with a small pulse width.

[0097] In this way, the magnetic memory 1 of this embodiment can suppress data write errors even if a write magnetic field caused by a write current having a large current value is applied to the magnetic material due to ensuring a margin in the current value of the write current Iw or due to variations in the characteristics of the magnetic material.

[0098] Therefore, the magnetic memory 1 of this embodiment can improve the reliability of data writing by using the multiple pulses 91 and 92 of the write current Iw.

[0099] As described above, the magnetic memory 1 of this embodiment can improve the reliability of the operation of the magnetic memory that utilizes the movement of domain walls.

[0100] (2) Second embodiment A magnetic memory according to a second embodiment will be described with reference to FIG.

[0101] In this embodiment, the polarity of the first pulse 91x of the write current Iw-2 for writing the second data is opposite to the polarity of the second pulse 92n of the write current Iw-2 for writing the second data. The pulse width W2 of the second pulse 92n is smaller than the pulse width W1 of the first pulse 91x. An interval T1 is provided between the two pulses 91x and 92n.

[0102] The polarity of the first pulse 91x of the write current Iw-2 for writing the second data is the same as the polarity of the first pulse 91p of the write current Iw-1 for writing the first data. In the write current Iw-1 for writing the first data, the polarity of the second pulse 92p is the same as the polarity of the first pulse 91p.

[0103] The pulse width W1 of pulse 91x is substantially equal to the pulse width W1 of pulse 91p. The absolute value of the current value (+i0) of pulse 91x is substantially equal to the absolute value of the current value (+i0) of pulse 91p. The pulse width W2 of pulse 92n is substantially equal to the pulse width W2 of pulse 92p. The absolute value of the current value (-i0) of pulse 92n is substantially equal to the absolute value of the current value (+i0) of pulse 92p.

[0104] As described above, the first pulse 91x acts to raise the temperature of the magnetic body 100 and fluctuate the magnetic field of the magnetic body 100. Since the second pulse 92n substantially determines the direction of magnetization in the magnetic body 100, the polarity of the first pulse 91x does not need to contribute to determining the data to be written. For example, it is sufficient for the first pulse 91x to temporarily relax the magnetic field in the magnetic body 100.

[0105] Therefore, as in this embodiment, if the second pulse 92n has a polarity corresponding to the data to be written, the first pulse 91x does not need to have a polarity corresponding to the data to be written.

[0106] According to this embodiment, it is possible to omit the design and arrangement of a circuit for generating the first pulse 91x having negative polarity, and as a result, the magnetic memory 1 of this embodiment can suppress an increase in the manufacturing cost of the magnetic memory.

[0107] The magnetic memory 1 of this embodiment can improve the reliability of data writing even if the polarity of the first pulse 91 is different from the polarity of the second pulse 92.

[0108] (3) Third embodiment A magnetic memory according to a third embodiment will be described with reference to FIGS.

[0109] 9 and 10 are schematic diagrams showing examples of the structure of the magnetic memory 1 of this embodiment.

[0110] Fig. 9 is a plan view of a memory core circuit 10 in the magnetic memory of this embodiment, viewed from a direction perpendicular to the surface of the substrate. Fig. 10 is a cross-sectional view showing a cross section taken along line AA in Fig. 9. In Fig. 9, a partial region of the memory core circuit 10 is extracted and shown.

[0111] 9 and 10, the memory core circuit 10 includes a plurality of magnetic bodies 100z. In the plurality of memory units MU, the plurality of magnetic bodies 100z are arranged two-dimensionally in a plane (XY plane) parallel to the surface of the substrate 190. Each magnetic body 100z extends in a direction (Z direction) perpendicular to the surface of the substrate 190. The magnetic body 100z has a tubular (e.g., cylindrical or elliptical cylindrical) structure.

[0112] A plurality of cell areas 103 are provided in the magnetic body 100z. The plurality of cell areas 103 are aligned in the Z direction. A write area 101 is provided on the upper end (one end) side of the magnetic body 100z in the Z direction. A read area 102 is provided on the lower end (other end) side of the magnetic body 100z in the Z direction.

[0113] In the magnetic body 100z, a constricted portion 109 is provided between two areas 101, 102, and 103 adjacent to each other in the Z direction. The dimension (cylinder diameter) of the constricted portion 109 in a direction parallel to the surface of the substrate 190 is smaller than the dimension (cylinder diameter) of the cell area 103 in a direction parallel to the surface of the substrate 190. The dimension of the constricted portion 109 in the Z direction is smaller than the dimension of the cell area 103 in the Z direction.

[0114] The yoke (magnetic body) 111 is adjacent to the outer surface of the upper end of the magnetic body 100z via the insulating layer 119. The yoke 111 faces the lower surface of the field line FL in the Z direction.

[0115] The yoke (magnetic body) 112 is provided above the magnetic body 100z in the Z direction. The yoke 112 may extend in the x direction, or may extend in a plane in the x and y directions.

[0116] The yoke (magnetic body) 113 is provided between the magnetic body 100z and the yoke 112 in the Z direction. The yoke 113 has a columnar structure. The yoke 113 extends inside the cylindrical magnetic body 100z. The yoke 113 contacts the inner surface of the upper end of the magnetic body 100z. The yokes 112 and 113 are continuous members. The yokes 111, 112, and 113 form a magnetic circuit.

[0117] The upper end of the magnetic body 100z in the Z direction (part of the write area 101) is sandwiched between the yoke 111 and the yoke 113. A magnetic gap is provided between the yoke 111 and the yoke 113. This magnetic gap acts as a magnetic resistance in the magnetic circuit.

[0118] The insulating layer 119 is provided between the magnetic body 100z and the yoke 111. An insulator may be provided inside the cylindrical magnetic body 100z.

[0119] The field lines FL (FLa, FLb) extend in the Y direction. The field lines FL are provided in the space between the yokes 111 and 112. The two field lines FL sandwich the yoke 113 in the X direction. The field lines FL are surrounded by the yokes 111, 112, and 113. The field lines FL include a metal wiring 30 and an insulating layer 32. The surfaces of the metal wiring 30 other than the surface facing the magnetic body 100z are covered with the insulating layer 32. The entire metal wiring 30 may be covered with the insulating layer 32. The insulating layer 32 is in direct contact with the metal wiring 30.

[0120] The source line (plate electrode) SL may extend in the X direction, or may extend in a plane in the x and y directions. The source line SL is provided on the upper surface of the yoke 112 in the Z direction.

[0121] The MTJ element 120, which is a read element, is provided between the lower end of the magnetic body 100z in the Z direction and the substrate 190. The memory layer 121 is connected to the lower end (read area 102) of the magnetic body 100z via a nonmagnetic conductive layer 129. The reference layer 123 is provided between the memory layer 121 and the substrate 190. The tunnel barrier layer 122 is provided between the memory layer 121 and the reference layer 123.

[0122] The bit line BL is provided between the MTJ element 120 and the substrate 190. The bit line BL extends in the X direction and is electrically connected to the multiple MTJ elements 120 arranged in the X direction.

[0123] In each memory unit MU, a select transistor 150 may be provided between the MTJ element 120 and the bit line BL. The select transistor 150 is a vertical thin film transistor (TFT). By controlling the on and off of the select transistor 150, electrical connection and separation between the MTJ element 120 and the bit line BL is controlled. The on and off of the select transistor 150 is controlled by the control circuit 20.

[0124] The select transistor 150 includes a semiconductor layer 151, a gate insulating layer 152, and a gate electrode 153. The semiconductor layer 151 extends in the Z direction. The semiconductor layer 151 functions as a channel region of the transistor. Source / drain regions are provided at one end and the other end of the semiconductor layer 151, respectively. One end of the semiconductor layer 151 is electrically connected to the reference layer 123 via a nonmagnetic conductive layer 158. The other end of the semiconductor layer 151 is electrically connected to the bit line BL via a nonmagnetic conductive layer 159.

[0125] The gate insulating layer 152 covers the side surfaces of the semiconductor layer 151 in a direction parallel to the surface of the substrate 190 .

[0126] The gate electrode 153 faces a side surface of the semiconductor layer 151 via the gate insulating layer 152. The gate electrode 153 extends in the Y direction. The gate electrode 153 is shared by multiple select transistors 150 aligned in the Y direction. The gate electrode 153 functions as a select gate line SG. Multiple memory units MU connected to one select gate line SG can be collectively set to a selected state by control of the select gate line SG by the control circuit 20.

[0127] During a shift operation, a shift current Is flows through the magnetic body 100z in the memory unit MU that includes the select transistor 150 in the on state. When the shift current Is is supplied to the magnetic body 100z, the domain wall DW moves from one constriction 109 to another constriction 109. When the shift current Is is not supplied to the magnetic body 100z, the domain wall DW is located at the constriction 109.

[0128] During a read operation, the select transistor 150 corresponding to the selected memory unit MU is set to an ON state. A read current Ir flows between the bit line BL and the source line SL via the MTJ element 120, the magnetic body 100z, and the yokes 112 and 113. Data in the read area 102 is read based on fluctuations in current and voltage according to the resistance state of the MTJ element 120.

[0129] During a write operation, similarly to the other embodiments described above, a write current Iw (Iwa, Iwb) including a plurality of pulses 91, 92 is supplied to the field line FL (FLa, FLb).

[0130] In this embodiment, the control circuit 20 supplies a write current Iwa, which flows in a first direction corresponding to the data to be written, to one or more field lines FLa located on one end side of the yoke 113 of the selected memory unit MU. Simultaneously with supplying the write current Iwa, the control circuit 20 supplies a write current Iwb, which flows in a second direction opposite to the first direction, to one or more field lines FLb located on the other end side of the yoke 113 of the selected memory unit MU. When each write current Iw is supplied to multiple field lines FL, each write current Iw is divided and supplied to each field line FL.

[0131] A magnetic circuit is formed around the field line FL through which the write current Iw flows within the yokes 111, 112, and 113. This prevents the strength of the write magnetic field from deteriorating even when the write current Iw is divided and supplied to multiple field lines FL.

[0132] With the above configuration, the magnetic memory 1 of this embodiment can avoid magnetic saturation of the yokes 111, 112, and 113 during a write operation.

[0133] When the write current Iw is divided into multiple currents and the divided currents are respectively passed through multiple field lines FL, the magnetic memory 1 of this embodiment can reduce the current value of the current supplied to one field line FL. This allows the magnetic memory 1 of this embodiment to suppress the occurrence of electromigration in the field lines FL. As a result, the magnetic memory 1 of this embodiment can suppress disconnection of the field lines FL.

[0134] Even in the case where the memory core circuit 10 has a three-dimensional structure due to the magnetic material 100z extending in a direction perpendicular to the surface of the substrate 190, as in this embodiment, a write current Iw including multiple pulses 91, 92 can be used for the write operation of the magnetic memory 1.

[0135] Therefore, the magnetic memory 1 of this embodiment can improve the reliability of data writing.

[0136] (4) Other Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0137] 1: magnetic memory, 10: memory core circuit, 20: control circuit, 100, 100z: magnetic material, 101: write area, 102: read area, 120: read element, 150: select transistor, BL: bit line, FL: field line, SL: source line.

Claims

1. a magnetic body configured to store data and to shift the data from a first area to a second area by moving a domain wall due to a shift operation; a wiring spaced apart from the magnetic body and configured to apply a write magnetic field to the magnetic body during a write operation; a control circuit that causes a shift current for shifting the data to flow through the magnetic material and a write current for generating the write magnetic field to flow through the wiring; Equipped with the write current includes a first pulse supplied to the wiring and a second pulse supplied to the wiring after the first pulse; The pulse width of the second pulse is smaller than the pulse width of the first pulse. Magnetic memory.

2. a first interval is provided between the first pulse and the second pulse; the first interval is smaller than the pulse width of the first pulse and is equal to or larger than the pulse width of the second pulse; 2. The magnetic memory according to claim 1.

3. The current value of the second pulse is equal to the current value of the first pulse.

2. The magnetic memory according to claim 1.

4. the current value of the second pulse has a value within a range from a value 10% higher than the current value of the first pulse to a value 10% lower than the current value of the first pulse; 2. The magnetic memory according to claim 1.

5. The pulse width of the second pulse has a magnitude in the range of 2.5% to 30% of the pulse width of the first pulse.

2. The magnetic memory according to claim 1.

6. a first interval is provided between the first pulse and the second pulse; The first interval has a size in the range of 5% to 75% of the pulse width of the first pulse.

6. The magnetic memory according to claim 5.

7. The wiring includes a metal wiring and a heat resistance layer covering the metal wiring.

2. The magnetic memory according to claim 1.

8. When writing first data, the first and second pulses have a first polarity; When writing second data different from the first data, the first and second pulses have a second polarity different from the first polarity.

2. The magnetic memory according to claim 1.

9. When writing first data, the first and second pulses have a first polarity; When writing second data different from the first data, the first pulse has the first polarity and the second pulse has a second polarity different from the first polarity.

2. The magnetic memory according to claim 1.

10. the magnetic body is provided on a substrate, the magnetic body extends in a direction perpendicular to the surface of the substrate; 2. The magnetic memory according to claim 1.

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