Single-phase three-wire inverter and control method

Abstract

To suppress an overvoltage between a third phase and a second phase when an overcurrent load is connected between a first phase and the third phase.SOLUTION: A single-phase three-wire inverter includes: a first arm that outputs a first phase voltage and a first phase current; a second arm that outputs a second phase voltage and a second phase current; a third arm that outputs a third phase voltage and a third phase current; a filter; and a control unit that outputs a first switching signal to a third switching signal to a first arm to a third arm, respectively. The control unit suppresses a duty of the first switching signal when an absolute value of the first phase current is equal to or larger than a first threshold current, suppresses a duty of the second switching signal when an absolute value of the second phase current is equal to or larger than the first threshold current, and suppresses a duty of the third switching signal when an absolute value of the third phase current is equal to or larger than a second threshold current larger than the first threshold current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a single-phase three-wire inverter and a control method. [Background technology]

[0002] The single-phase three-wire inverter device described in Patent Document 1 reduces the AC voltage of phase A when a surge current is detected in phase A, thereby reducing the current in phase A, and at the same time, reduces the conduction rate of phase B to suppress overvoltage in phase B that may be induced by the surge current in phase A. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-2657 Summary of the Invention [Problem to be solved by the invention]

[0004] In the single-phase inverter, an overcurrent protection circuit is provided in front of each of the gate drive circuits for the U and V phases. The overcurrent protection circuit compares the current detection signal with a current threshold, performs a logical AND operation on the comparison result signal and the PWM signal, and outputs the logical AND result signal to the gate drive circuit, thereby suppressing the on-duty of the gate drive signal.

[0005] In a single-phase three-wire inverter, if the above-mentioned overcurrent protection circuit is provided in front of each of the gate drive circuits for the U, V, and N phases, and a load (overcurrent load) that activates overcurrent protection is connected between the U and V phases, a waveform similar to that of the above-mentioned single-phase inverter can be obtained.

[0006] However, when a first load, which is an overcurrent load, is connected between a first phase (e.g., U phase) and a third phase (e.g., N phase), a difference occurs between the voltage between the first phase and the third phase and the voltage between the third phase and the second phase (e.g., V phase). That is, the voltage between the first phase and the third phase decreases, and the voltage between the third phase and the second phase increases. As a result, a voltage higher than the withstand voltage may be applied to the second load connected between the third phase and the second phase. Therefore, a single-phase three-wire inverter requires an overcurrent protection configuration different from that of the single-phase inverter described above.

[0007] The present disclosure aims to suppress an overvoltage between the third phase and the second phase when an overcurrent load is connected between the first phase and the third phase. [Means for solving the problem]

[0008] A single-phase three-wire inverter according to one embodiment of the present disclosure includes: a first arm connected between the first input terminal and the second input terminal, and outputting a first phase voltage and a first phase current from a first connection point between the first switching element and the second switching element; a second arm connected between the first input terminal and the second input terminal, and outputting a second phase voltage and a second phase current from a second connection point between a third switching element and a fourth switching element; a third arm connected between the first input terminal and the second input terminal, and outputting a third phase voltage and a third phase current from a third connection point between a fifth switching element and a sixth switching element; filters provided between the first connection point and a first output terminal, between the second connection point and a second output terminal, and between the third connection point and a third output terminal; a control unit that outputs a first switching signal, a second switching signal, and a third switching signal from the first arm to the third arm, respectively; Including, the control unit suppresses the duty of the first switching signal when the absolute value of the first phase current is equal to or greater than a first threshold current, suppresses the duty of the second switching signal when the absolute value of the second phase current is equal to or greater than the first threshold current, and suppresses the duty of the third switching signal when the absolute value of the third phase current is equal to or greater than a second threshold current that is greater than the first threshold current. It is characterized by:

[0009] In the single-phase three-wire inverter, The control unit a first voltage control unit that generates the first switching signal so that a first inter-phase voltage between the first connection point and the third connection point becomes a first command voltage; a second voltage control unit that generates the second switching signal so that a second inter-phase voltage between the third connection point and the second connection point becomes a second command voltage; a third voltage control unit that generates the third switching signal so that the third phase voltage is constant; Including, It is characterized by:

[0010] In the single-phase three-wire inverter, The first voltage control unit a first protection circuit including a first comparator that compares the detected value of the first phase current with a first threshold value, and a first AND circuit that performs a logical AND operation on an output signal of the first comparator and the first switching signal; The second voltage control unit a second protection circuit including a second comparator that compares the detected value of the second phase current with the first threshold value, and a second AND circuit that performs a logical AND operation on an output signal of the second comparator and the second switching signal; The third voltage control unit is a third protection circuit including a third comparator that compares the detected value of the third phase current with a second threshold value that is greater than the first threshold value, and a third AND circuit that performs a logical AND operation on an output signal of the third comparator and the third switching signal; It is characterized by:

[0011] In the single-phase three-wire inverter, the second threshold current is smaller than the current withstand capacity of the fifth switching element and the sixth switching element; It is characterized by:

[0012] A control method according to one aspect of the present disclosure includes: a first arm connected between a first input terminal and a second input terminal, and outputting a first phase voltage and a first phase current from a first connection point between a first switching element and a second switching element; a second arm connected between the first input terminal and the second input terminal, and outputting a second phase voltage and a second phase current from a second connection point between a third switching element and a fourth switching element; a third arm connected between the first input terminal and the second input terminal, and outputting a third phase voltage and a third phase current from a third connection point between a fifth switching element and a sixth switching element; and filters provided between the first connection point and a first output terminal, between the second connection point and a second output terminal, and between the third connection point and a third output terminal, suppressing a duty of a first switching signal of the first arm when an absolute value of the first phase current is equal to or greater than a first threshold current, suppressing a duty of a second switching signal of the second arm when an absolute value of the second phase current is equal to or greater than the first threshold current, and suppressing a duty of a third switching signal of the third arm when an absolute value of the third phase current is equal to or greater than a second threshold current that is greater than the first threshold current; It is characterized by: [Effects of the Invention]

[0013] According to the present disclosure, when an overcurrent load is connected between the first phase and the third phase, an overvoltage between the third phase and the second phase can be suppressed. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a single-phase three-wire inverter according to an embodiment. [Figure 2]FIG. 2 is a diagram showing the configuration of the control unit for each phase of the first comparative example. [Figure 3] FIG. 3 is a diagram showing the measurement results of the first comparative example. [Figure 4] FIG. 4 is a diagram showing the measurement results of the first comparative example. [Figure 5] FIG. 5 is a diagram showing the measurement results of the second comparative example. [Figure 6] FIG. 6 is a diagram showing the measurement results of the second comparative example. [Figure 7] FIG. 7 is a diagram showing the overall configuration of a control unit of a single-phase three-wire inverter according to an embodiment. [Figure 8] FIG. 8 is a diagram illustrating the configuration of the U-phase control unit and the V-phase control unit according to the embodiment. [Figure 9] FIG. 9 is a diagram illustrating a configuration of the N-phase control unit according to the embodiment. [Figure 10] FIG. 10 is a diagram showing the results of a circuit simulation according to the embodiment. [Figure 11] FIG. 11 is a diagram showing the results of a circuit simulation according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited to these embodiments, and in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted.

[0016] <Embodiment> (Overall composition) FIG. 1 is a diagram showing the overall configuration of a single-phase three-wire inverter according to an embodiment. In the single-phase three-wire inverter 1, a DC input voltage Vin output from a power source 2 and smoothed by a smoothing capacitor 3 is input between a first input terminal 1a and a second input terminal 1b. The single-phase three-wire inverter 1 generates a U-phase-to-N-phase voltage V UN is output to the load 4 from between the first output terminal 1c and the third output terminal 1e. The single-phase three-wire inverter 1 outputs the N-phase-V inter-phase voltage V NVis output from between the third output terminal 1e and the second output terminal 1d to the load 5. The single-phase three-wire inverter 1 outputs the U-phase-V interphase voltage V UV is output to the load 6 from between the first output terminal 1c and the second output terminal 1d.

[0017] The single-phase three-wire inverter 1 has a U-phase arm 11 U and V-phase arm 11 V and N-phase arm 11 N , a filter 12, a control unit 13, current detectors 41 to 43, and voltage detectors 44 to 46.

[0018] U-phase arm 11 U corresponds to an example of the "first arm" in the present disclosure. V corresponds to an example of the "second arm" in the present disclosure. N corresponds to an example of the "third arm" of the present disclosure.

[0019] U-phase arm 11 U The V-phase arm 11 includes a first transistor 21 and a second transistor 22. V The N-phase arm 11 includes a third transistor 23 and a fourth transistor 24. N includes a fifth transistor 25 and a sixth transistor 26.

[0020] In the embodiment, each transistor is a MOSFET, but the present disclosure is not limited to this. Each transistor may be a silicon power device, a GaN power device, a SiC power device (e.g., an IGBT (Insulated Gate Bipolar Transistor)), or the like.

[0021] Each transistor has a parasitic diode (body diode) that can actively conduct current, or has a diode connected in anti-parallel: the pn junction between the back gate and the source and drain of the MOSFET.

[0022] The first transistor 21 corresponds to an example of a "first switching element" in the present disclosure. The second transistor 22 corresponds to an example of a "second switching element" in the present disclosure. The third transistor 23 corresponds to an example of a "third switching element" in the present disclosure. The fourth transistor 24 corresponds to an example of a "fourth switching element" in the present disclosure. The fifth transistor 25 corresponds to an example of a "fifth switching element" in the present disclosure. The sixth transistor 26 corresponds to an example of a "sixth switching element" in the present disclosure.

[0023] The drain of the first transistor 21 is electrically connected to the first input terminal 1a. The source of the first transistor 21 is electrically connected to the first node N1. The drain of the second transistor 22 is electrically connected to the first node N1. The source of the second transistor 22 is electrically connected to the second input terminal 1b.

[0024] The first node N1 corresponds to an example of a "first connection point" in the present disclosure.

[0025] U-phase arm 11 U When the first transistor 21 is on and the second transistor 22 is off, the U-phase arm 11 outputs a high-level voltage (DC input voltage Vin) from the first node N1. U When the first transistor 21 is off and the second transistor 22 is on, a low-level voltage (0 V) is output from the first node N1.

[0026] The drain of the third transistor 23 is electrically connected to the first input terminal 1a. The source of the third transistor 23 is electrically connected to the second node N2. The drain of the fourth transistor 24 is electrically connected to the second node N2. The source of the fourth transistor 24 is electrically connected to the second input terminal 1b.

[0027] The second node N2 corresponds to an example of a "second connection point" in the present disclosure.

[0028] V-phase arm 11 VWhen the third transistor 23 is on and the fourth transistor 24 is off, the V-phase arm 11 outputs a high-level voltage (the DC input voltage Vin) from the second node N2. V When the third transistor 23 is off and the fourth transistor 24 is on, a low-level voltage (0 V) is output from the second node N2.

[0029] The drain of the fifth transistor 25 is electrically connected to the first input terminal 1a. The source of the fifth transistor 25 is electrically connected to the third node N3. The drain of the sixth transistor 26 is electrically connected to the third node N3. The source of the sixth transistor 26 is electrically connected to the second input terminal 1b.

[0030] The third node N3 corresponds to an example of a "third connection point" in the present disclosure.

[0031] N-phase arm 11 N When the fifth transistor 25 is on and the sixth transistor 26 is off, the N-phase arm 11 outputs a high-level voltage (the DC input voltage Vin) from the third node N3. N When the fifth transistor 25 is off and the sixth transistor 26 is on, a low-level voltage (0 V) is output from the third node N3.

[0032] The filter 12 includes inductors 31 through 33 and capacitors 34 through 36 .

[0033] One end of the inductor 31 is electrically connected to the first node N1. The other end of the inductor 31 is electrically connected to the first output terminal 1c. One end of the inductor 32 is electrically connected to the second node N2. The other end of the inductor 32 is electrically connected to the second output terminal 1d. One end of the inductor 33 is electrically connected to the third node N3. The other end of the inductor 33 is electrically connected to the third output terminal 1e.

[0034] One end of capacitor 34 is electrically connected to the other end of inductor 31. The other end of capacitor 34 is electrically connected to the other end of inductor 33. One end of capacitor 35 is electrically connected to the other end of inductor 32. The other end of capacitor 35 is electrically connected to the other end of inductor 33. One end of capacitor 36 is electrically connected to the other end of inductor 31. The other end of capacitor 36 is electrically connected to the other end of inductor 32.

[0035] The current detector 41 is electrically connected between the other end of the inductor 31 and one end of the capacitor 34. The current detector 41 detects the U-phase current I U and detects the U-phase current I U The signal SI representing U is output to the control unit 13.

[0036] U phase current I U corresponds to an example of the "first phase current" in the present disclosure.

[0037] The current detector 42 is electrically connected between the other end of the inductor 32 and the other end of the capacitor 35. The current detector 42 detects the V-phase current I V and detects the V-phase current I V The signal SI representing V is output to the control unit 13.

[0038] V phase current I V corresponds to an example of the "second phase current" of the present disclosure.

[0039] The current detector 43 is electrically connected between the other end of the inductor 33 and the other end of the capacitor 34. The current detector 43 detects the N-phase current I N and detects the N-phase current I N The signal SI representing N is output to the control unit 13.

[0040] N phase current I N corresponds to an example of the "third phase current" of the present disclosure.

[0041] The voltage detector 44 is electrically connected between the first node N1 and the third node N3. The voltage detector 44 detects the U-phase-to-N-phase voltage V UN Detects the U-phase to N-phase voltage V UN The signal SV UN is output to the control unit 13.

[0042] The voltage detector 45 is electrically connected between the second node N2 and the third node N3. The voltage detector 45 detects the N-phase-V-phase voltage V NV Detects the N-phase to V-phase voltage V NV The signal SV NV is output to the control unit 13.

[0043] The voltage detector 46 is electrically connected between the first node N1 and the second node N2. The voltage detector 46 detects the U-phase-V-phase voltage V UV Detects the U-phase-V phase voltage V UV The signal SV UV is output to the control unit 13.

[0044] The control unit 13 outputs the signal SI U , signal SI V , signal SI N , signal SV UN , signal SV NV , and signal SV UV Based on this, the switching control signal S U U-phase arm 11 U and outputs the switching control signal S V V-phase arm 11 V and outputs the switching control signal S N N-phase arm 11 N Output to.

[0045] (Control unit of first comparative example) 2 is a diagram showing the configuration of the control units for each phase of the first comparative example. U The V-phase control unit 101 V and N-phase control unit 101 N The configuration is a U-phase control unit 101 U Since the configuration is the same as that of the first embodiment, a separate description will be omitted.

[0046] U-phase control unit 101 U The switching signal output unit 111 U and an overcurrent protection unit 112 U and drive unit 113 U and an overcurrent protection unit 112. U is the threshold output unit 121 U and the comparison unit 122 U and AND circuit 123 U and,

[0047] Switching signal output unit 111 U is a pulse width modulation signal (PWM signal) S1 U AND circuit 123 U The switching signal output unit 111 outputs the signal to one of the input terminals of the switching signal output unit 111. U For example, the voltage between U and N phases V UN is the command value voltage. U Output.

[0048] Threshold output unit 121 U The phase current threshold value Th is compared with the comparison unit 122. U The output is sent to one of the input terminals.

[0049] In the first comparative example, the phase current threshold value Th is the same for the U phase, V phase, and N phase.

[0050] Comparison unit 122 U The other input terminal of U The signal SI representing U is input to the comparison unit 122. U is the U-phase current I U The absolute value of the phase current is compared with the phase current threshold value Th. U is the U-phase current I U If the absolute value of is less than the phase current threshold value Th, a high-level comparison result signal S2 U AND circuit 123 U The comparison unit 122 outputs the signal to the other input terminal of the comparison unit 122. U is the U-phase current I UIf the absolute value of is equal to or greater than the phase current threshold value Th, a low-level comparison result signal S2 U AND circuit 123 U The other input terminal of the

[0051] AND circuit 123 U is the pulse width modulated signal S1 U and comparison result signal S2 U A logical AND operation is performed on these two signals, and a logical AND result signal S3 U Drive unit 113 U Output to.

[0052] Drive unit 113 U is the logical product result signal S3 U The voltage level of the switching control signal S U U-phase arm 11 U Output to.

[0053] That is, the U-phase control unit 101 U is the U-phase current I U When the absolute value of is equal to or greater than the phase current threshold Th, the switching control signal S U The on-duty (duty at which the first transistor 21 is turned on) is suppressed.

[0054] Similarly, the V-phase control unit 101 V is the V-phase current I V When the absolute value of is equal to or greater than the phase current threshold Th, the switching control signal S V The on-duty (the duty at which the third transistor 23 is turned on) is suppressed.

[0055] Similarly, the N-phase control unit 101 N is the N-phase current I N When the absolute value of is equal to or greater than the phase current threshold Th, the switching control signal S N The on-duty (the duty at which the fifth transistor 25 is turned on) is suppressed.

[0056] (Measurement results of the first comparative example) Fig. 3 is a diagram showing the results of measurements taken in the first comparative example. Specifically, Fig. 3 is a diagram showing the results of measurements taken in the single-phase three-wire inverter of the first comparative example when an overcurrent flows through the load 6 electrically connected between the U phase and the V phase.

[0057] In FIG. 3, line 201 represents the U-phase-V phase inter-voltage V UV and line 202 indicates the U-phase-N-phase voltage V UN and line 203 indicates the N-phase-V phase voltage V NV The line 204 indicates the U-phase current I U and line 205 indicates the N-phase current I N Shows.

[0058] In this example, an overcurrent flows through load 6, so as shown in Figure 3, the U-phase to V-phase voltage V UV (line 201) is limited. Also, the U-phase to N-phase voltage V UN (line 202) and the N-phase to V-phase voltage V NV (line 203) is also limited. UN (wire 202) and the N-phase to V-phase voltage V NV (wire 203) is at the same voltage.

[0059] Fig. 4 is a diagram showing the results of measurements taken in the first comparative example. Specifically, Fig. 4 is a diagram showing the results of measurements taken in the single-phase three-wire inverter of the first comparative example when an overcurrent flows through the load 4 electrically connected between the U phase and the N phase.

[0060] In FIG. 4, line 211 represents the U-phase-V phase voltage V UV and line 212 indicates the U-phase-N-phase voltage V UN and line 213 indicates the N-phase-V phase voltage V NV The line 214 indicates the U-phase current I U and line 215 indicates the N-phase current I N Shows.

[0061] (Issues in the first comparative example) In this example, an overcurrent flows through load 4, so as shown in Figure 4, the voltage between U and N phases V UNThe N-phase to V-phase voltage V NV (line 213) and the U-phase to V-phase voltage V UV (line 211) is also limited. However, the N-phase to V-phase voltage V NV (Line 213) is the voltage between U and N phases V UN Compared to (line 212), the voltage is high and the waveform is distorted.

[0062] This is U-phase arm 11 U and V-phase arm 11 V are connected in parallel to one DC input voltage Vin, and an overcurrent flows through the load 4, causing the overcurrent protection unit 112 N When this operates, the N-phase switching control signal S N This is thought to be because the duty of the N-phase switching control signal S N As a result of the unbalance in the duty, the N-phase to V-phase voltage V NV is likely to become higher.

[0063] (Control unit of second comparative example) U-phase control unit 101 of the second comparative example U and V-phase control unit 101 V The U-phase control unit 101 of the first embodiment U and V-phase control unit 101 V However, the N-phase control unit 101 of the second comparative example is the same as N overcurrent protection unit 112 N That is, the N-phase control unit 101 of the second comparative example does not have N is the switching control signal S N The on-duty of the

[0064] (Measurement results of the second comparative example) Fig. 5 is a diagram showing the results of measurements taken in the second comparative example. Specifically, Fig. 5 is a diagram showing the results of measurements taken in the single-phase three-wire inverter of the second comparative example when an overcurrent flows through the load 6 electrically connected between the U phase and the V phase.

[0065] In FIG. 5, a line 221 represents the U-phase-N-phase voltage V UN and line 222 indicates the N-phase-V phase voltage V NV and line 223 indicates the U-phase-V phase voltage V UV The line 224 indicates the U-phase current I U Shows.

[0066] In this example, an overcurrent flows through load 6, so as shown in Figure 5, the U-phase to V-phase voltage V UV (line 223) is limited. Also, the U-phase to N-phase voltage V UN (line 221) and the N-phase to V-phase voltage V NV (Line 222) also has restrictions.

[0067] Fig. 6 is a diagram showing the results of measurements taken in the second comparative example. Specifically, Fig. 6 is a diagram showing the results of measurements taken in the single-phase three-wire inverter of the second comparative example when an overcurrent flows through the load 4 between the U phase and the N phase.

[0068] In FIG. 6, a line 231 represents the U-phase-N-phase voltage V UN and line 232 indicates the N-phase-V phase voltage V NV and line 233 indicates the U-phase-V phase voltage V UV The line 234 indicates the U-phase current I U Shows.

[0069] In this example, an overcurrent flows through load 4, so as shown in Figure 6, the voltage between U and N phases V UN However, in the second comparative example, the N-phase control unit 101 N overcurrent protection unit 112 N and the switching control signal S N Therefore, the N-phase to V-phase voltage V NV (line 232) and the U-phase-V phase inter-phase voltage V UV (line 233) is not limited. N-phase to V-phase voltage V NV (line 232) and the U-phase-V phase voltage V UV (Line 233) is unconstrained, has a smooth sinusoidal waveform, and is preferred.

[0070] (Issues in the second comparative example) In the second comparative example, the N-phase control unit 101 N The overcurrent protection unit 112 N Since there is no N-phase current I N Therefore, there is no restriction on the N-phase arm 11 N In order to prevent damage to the fifth transistor 25 and the sixth transistor 26, the N-phase control unit 101 N The overcurrent protection unit 112 N It is desirable to have

[0071] (Control unit of embodiment) FIG. 7 is a diagram showing the overall configuration of a control unit of a single-phase three-wire inverter according to an embodiment.

[0072] The control unit 13 includes a U-phase control unit 51 U and the V-phase control unit 51 V and N-phase control unit 51 N and the interphase voltage command value output unit 52 U and the interphase voltage command value output unit 52 V and,

[0073] U-phase control unit 51 U This corresponds to an example of a "first voltage control unit" in the present disclosure. V This corresponds to an example of a "second voltage control unit" in the present disclosure. N corresponds to an example of a "third voltage control unit" in the present disclosure.

[0074] U-phase control unit 51 U is the voltage between U and N phases, V UN The signal SV UN is input from the voltage detector 44.

[0075] Phase-to-phase voltage command value output unit 52 U is the voltage command value between U and N phases, CV UN The U-phase control unit 51 U The phase-to-phase voltage command value output unit 52 outputs the command value to the phase-to-phase voltage command value output unit 52. Uis the U-phase current I U , DC input voltage Vin, etc., the U-phase to N-phase voltage command value CV UN However, the present disclosure is not limited to this.

[0076] U-phase control unit 51 U is the signal SV UN and U-phase to N-phase voltage command value CV UN Based on this, the switching control signal S U U-phase arm 11 U The U-phase control unit 51 U is the voltage between U and N phases, V UN is the voltage command value CV between U and N phases UN The switching control signal S U Output.

[0077] V-phase control unit 51 V is the N-phase to V-phase voltage V NV The signal SV NV is input from the voltage detector 45.

[0078] Phase-to-phase voltage command value output unit 52 V is the voltage command value between N phase and V phase, CV NV The V-phase control unit 51 V The phase-to-phase voltage command value output unit 52 outputs the command value to the phase-to-phase voltage command value output unit 52. V is the V-phase current I V , DC input voltage Vin, etc., the N-phase to V-phase voltage command value CV NV However, the present disclosure is not limited to this.

[0079] V-phase control unit 51 V is the signal SV NV and N-phase to V-phase voltage command value CV NV Based on this, the switching control signal S V V-phase arm 11 V V-phase control unit 51 V is the N-phase to V-phase voltage V NV is the voltage command value between N phase and V phase VC NV The switching control signal S V Output.

[0080] In this way, the U-phase control unit 51 U and V-phase control unit 51 V and are independent of each other and are switched by the switching control signal S U and the switching control signal S V For example, the voltage between U and N phases V UN When a limiter is applied to the N-phase to V-phase voltage V NV This is to prevent any impact on the

[0081] N-phase control unit 51 N is set to the switching control signal S so that the N-phase potential becomes the midpoint potential. N N-phase arm 11 N Output to.

[0082] This means that the N-phase potential is equal to the U-phase-N-phase voltage V UN and N-phase to V-phase voltage V NV This is because it affects both.

[0083] 8 is a diagram showing the configuration of a U-phase control unit and a V-phase control unit according to the embodiment. U The V-phase control unit 51 V The configuration of the U-phase control unit 51 U Since the configuration is the same as that of the first embodiment, a separate description will be omitted.

[0084] U-phase control unit 51 U The switching signal output unit 61 U and overcurrent protection unit 62 U and drive unit 63 U and an overcurrent protection unit 62. U is the threshold output unit 71 U and the comparison unit 72 U and AND circuit 73 U and,

[0085] Overcurrent protection section 62 U This corresponds to an example of the "first protection circuit" of the present disclosure. VThis corresponds to an example of a "second protection circuit" in the present disclosure. U This corresponds to an example of a "first comparator" in the present disclosure. V corresponds to an example of the "second comparator" of the present disclosure. U This corresponds to an example of a "first AND circuit" in the present disclosure. V corresponds to an example of a "second AND circuit" in the present disclosure.

[0086] Switching signal output unit 61 U is a pulse width modulation signal (PWM signal) S1 U AND circuit 73 U The switching signal output unit 61 outputs the signal to one of the input terminals. U For example, the U-phase to N-phase voltage command value CV UN and the voltage between U and N phases V UN The proportional-integral-derivative (PID) calculation is performed on the deviation between the U-phase and N-phase voltage V UN is the voltage command value CV between U and N phases UN so that the pulse width modulation signal S1 U Output.

[0087] Threshold output unit 71 U The phase current threshold value Th1 is compared with the phase current threshold value Th1 by the comparator 72. U The output is sent to one of the input terminals.

[0088] In this embodiment, the phase current threshold value Th1 is the same for the U phase and the V phase.

[0089] The phase current threshold value Th1 corresponds to an example of a "first threshold value" in the present disclosure.

[0090] Comparison unit 72 U The other input terminal of U The signal SI representing U is input to the comparison unit 72. U is the U-phase current I U The absolute value of the phase current is compared with the phase current threshold value Th1. U is the U-phase current I U If the absolute value of is less than the phase current threshold value Th1, a high-level comparison result signal S2U AND circuit 73 U The comparison unit 72 outputs the signal to the other input terminal of the comparison unit 72. U is the U-phase current I U If the absolute value of is equal to or greater than the phase current threshold value Th1, a low-level comparison result signal S2 U AND circuit 73 U The other input terminal of the

[0091] AND circuit 73 U is the pulse width modulated signal S1 U and comparison result signal S2 U A logical AND operation is performed on these two signals, and a logical AND result signal S3 U Drive unit 63 U Output to.

[0092] Drive unit 63 U is the logical product result signal S3 U The voltage level of the switching control signal S U U-phase arm 11 U Output to.

[0093] That is, the U-phase control unit 51 U is the U-phase current I U When the absolute value of is equal to or greater than the phase current threshold value Th1, the switching control signal S U The on-duty (duty at which the first transistor 21 is turned on) is suppressed.

[0094] Similarly, the V-phase control unit 51 V is the V-phase current I V When the absolute value of is equal to or greater than the phase current threshold value Th1, the switching control signal S V The on-duty (the duty at which the third transistor 23 is turned on) is suppressed.

[0095] FIG. 9 is a diagram illustrating a configuration of the N-phase control unit according to the embodiment.

[0096] N-phase control unit 51 N The switching signal output unit 61 N and overcurrent protection unit 62 N and drive unit 63 Nand an overcurrent protection unit 62. N is the threshold output unit 71 N and the comparison unit 72 N and AND circuit 73 N and,

[0097] Overcurrent protection section 62 N This corresponds to an example of a "third protection circuit" in the present disclosure. N This corresponds to an example of the "third comparator" of the present disclosure. N corresponds to an example of the "third AND circuit" of the present disclosure.

[0098] Switching signal output unit 61 N is a pulse width modulation signal (PWM signal) S1 N AND circuit 73 N The switching signal output unit 61 outputs the signal to one of the input terminals. N is set to the midpoint potential by the pulse width modulation signal S1 N Output.

[0099] Threshold output unit 71 N The phase current threshold value Th2 is compared with the phase current threshold value Th2 by the comparator 72. N The output is sent to one of the input terminals.

[0100] The phase current threshold value Th2 corresponds to an example of the "second threshold value" of the present disclosure.

[0101] In this embodiment, the phase current threshold Th2 is greater than the phase current threshold Th1, i.e., the phase current threshold Th2>the phase current threshold Th1.

[0102] In the embodiment, the reason why the phase current threshold value Th2 is set to be larger than the phase current threshold value Th1 is as follows.

[0103] For example, if the phase current thresholds of the U phase, V phase, and N phase are set to be the same (phase current threshold Th2 = phase current threshold Th1), then when the power factor of the load 4 connected between the U phase and the N phase is opposite to the power factor of the load 5 connected between the N phase and the V phase, the power factor of the N phase overcurrent protection unit 62 is higher than when the loads 4 and 5 have the same resistance value (when the power factor of the load 4 = the power factor of the load 5 = 1). N is the U-phase overcurrent protection unit 62 U and V-phase overcurrent protection unit 62 V Overcurrent protection operates faster.

[0104] This is because the power factor of load 4 and the power factor of load 5 are opposite, so the current flowing between U phase and N phase and the current flowing between N phase and V phase are opposite in phase. Therefore, the N phase current is twice the U phase current (= twice the V phase current).

[0105] From the above, even if the power factor of the load 4 and the power factor of the load 5 are different, in order to output a current to the load 4 and the load 5 regardless of the power factor, the N-phase arm 11 N Although it depends on the current tolerance of the fifth transistor 25 and the sixth transistor 26, it is preferable to set the phase current threshold Th2 of the N phase higher than the phase current threshold Th1 of the U phase and the V phase.

[0106] The phase current threshold value Th2 is greater than the phase current threshold value Th1, and the N-phase arm 11 N It is more preferable that the current withstand capacity of the fifth transistor 25 and the sixth transistor 26 is smaller than that of the sixth transistor 26.

[0107] N-phase control unit 51 N Returning to the explanation of the comparison unit 72 N The other input terminal of N The signal SI representing N is input to the comparison unit 72. N is the N-phase current I N The absolute value of the phase current is compared with the phase current threshold value Th2. N is the N-phase current I N If the absolute value of is less than the phase current threshold value Th2, a high-level comparison result signal S2 N AND circuit 73N The comparison unit 72 outputs the signal to the other input terminal of the comparison unit 72. N is the N-phase current I N If the absolute value of is equal to or greater than the phase current threshold value Th2, a low-level comparison result signal S2 N AND circuit 73 N The other input terminal of the

[0108] Drive unit 63 N is the logical product result signal S3 N The voltage level of the switching control signal S N N-phase arm 11 N Output to.

[0109] That is, the N-phase control unit 51 N is the N-phase current I N When the absolute value of is equal to or greater than the phase current threshold value Th2, the switching control signal S N The on-duty (the duty at which the fifth transistor 25 is turned on) is suppressed.

[0110] (Circuit simulation results of the embodiment) Fig. 10 is a diagram showing the results of a circuit simulation of the embodiment. Specifically, Fig. 10 is a diagram showing the results of a circuit simulation of the single-phase three-wire inverter of the embodiment when an overcurrent flows through the load 6 between the U phase and the V phase.

[0111] In FIG. 10, a line 241 indicates the voltage V between the U phase and the N phase. UN and line 242 indicates the N-phase-V phase voltage V NV and line 243 indicates the U-phase-V phase voltage V UV Shows.

[0112] In this example, an overcurrent flows through the load 6, so as shown in Figure 10, the U-phase to V-phase voltage V UV (line 243) is limited. Also, the U-phase to N-phase voltage V UN (line 241) and the N-phase to V-phase voltage V NV (Line 242) also has restrictions.

[0113] Fig. 11 is a diagram showing the results of a circuit simulation of the embodiment. Specifically, Fig. 11 is a diagram showing the results of a circuit simulation of the single-phase three-wire inverter of the embodiment when an overcurrent flows through the load 4 between the U phase and the N phase.

[0114] In FIG. 11, a line 251 indicates the voltage V between the U phase and the N phase. UN and line 252 indicates the N-phase-V phase voltage V NV and line 253 indicates the U-phase-V phase voltage V UV Shows.

[0115] (Effects of the embodiment) [1] The circuit simulation results (FIG. 11) when an overcurrent flows through the load 4 of the embodiment are compared with the actual measurement results (FIG. 3) when an overcurrent flows through the load 4 of the first comparative example.

[0116] The single-phase three-wire inverter 1 of the embodiment is configured to generate an N-phase-V interphase voltage V NV (line 251) and the U-phase to V-phase voltage V UV (Line 253) does not become a high voltage, there is no restriction, and the waveform can be made sinusoidal without being distorted.

[0117] [2] The single-phase three-wire inverter 1 of the embodiment has an overcurrent protection unit 62 in the N phase as well, in comparison with the second comparative example. N is provided.

[0118] Therefore, the control unit 13 of the embodiment controls the N-phase arm 11 N This prevents overcurrent from flowing through N-phase arm 11. N This can prevent the fifth transistor 25 and the sixth transistor 26 from being damaged.

[0119] [3] In the single-phase three-wire inverter 1 according to the embodiment, the phase current threshold value Th2 of the N phase is greater than the phase current threshold value Th1 of the U phase and the V phase.

[0120] Therefore, the single-phase three-wire inverter 1 of the embodiment can output current to the load 4 and the load 5 regardless of the power factor, even if the power factor of the load 4 connected between the U phase and the N phase is different from the power factor of the load 5 connected between the N phase and the V phase.

[0121] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the contents of these embodiments. Furthermore, the above-described components include those that can be easily imagined by a person skilled in the art, those that are substantially the same, and those that are within the so-called equivalent range. Furthermore, the above-described components can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the components can be made without departing from the spirit of the above-described embodiments. [Explanation of symbols]

[0122] 1 Single-phase three-wire inverter 2 Power supply 3 smoothing capacitors 4, 5, 6 Load 11 U U-phase arm 11 V V-phase arm 11 N N-phase arm 12 Filters 13 Control Unit 21 First transistor 22 Second transistor 23 Third transistor 24 4th transistor 25 5th transistor 26 6th Transistor 51 U U-phase control section 51 V V-phase control unit 51 N N-phase control section 52 U , 52 V Phase-to-phase voltage command value output section 61 U , 61 V , 61 N Switching signal output section 62U , 62 V , 62 N Overcurrent protection section 63 U , 63 V , 63 N Drive unit 71 U , 71 V , 71 N Threshold Output Unit 72 U , 72 V , 72 N Comparison section 73 U , 73 V , 73 N logical product circuit

Claims

1. a first arm connected between the first input terminal and the second input terminal, and outputting a first phase voltage and a first phase current from a first connection point between the first switching element and the second switching element; a second arm connected between the first input terminal and the second input terminal, and outputting a second phase voltage and a second phase current from a second connection point between a third switching element and a fourth switching element; a third arm connected between the first input terminal and the second input terminal, and outputting a third phase voltage and a third phase current from a third connection point between a fifth switching element and a sixth switching element; filters provided between the first connection point and a first output terminal, between the second connection point and a second output terminal, and between the third connection point and a third output terminal; a control unit that outputs a first switching signal, a second switching signal, and a third switching signal from the first arm to the third arm, respectively; Including, the control unit suppresses the duty of the first switching signal when the absolute value of the first phase current is equal to or greater than a first threshold current, suppresses the duty of the second switching signal when the absolute value of the second phase current is equal to or greater than the first threshold current, and suppresses the duty of the third switching signal when the absolute value of the third phase current is equal to or greater than a second threshold current that is greater than the first threshold current. A single-phase three-wire inverter characterized by:

2. The control unit a first voltage control unit that generates the first switching signal so that a first inter-phase voltage between the first connection point and the third connection point becomes a first command voltage; a second voltage control unit that generates the second switching signal so that a second inter-phase voltage between the third connection point and the second connection point becomes a second command voltage; a third voltage control unit that generates the third switching signal so that the third phase voltage is constant; Including, 2. The single-phase three-wire inverter according to claim 1 .

3. The first voltage control unit a first protection circuit including a first comparator that compares the detected value of the first phase current with a first threshold value, and a first AND circuit that performs a logical AND operation on an output signal of the first comparator and the first switching signal; The second voltage control unit a second protection circuit including a second comparator that compares the detected value of the second phase current with the first threshold value, and a second AND circuit that performs a logical AND operation on an output signal of the second comparator and the second switching signal; The third voltage control unit a third protection circuit including a third comparator that compares the detected value of the third phase current with a second threshold value that is greater than the first threshold value, and a third AND circuit that performs a logical AND operation on an output signal of the third comparator and the third switching signal; 3. The single-phase three-wire inverter according to claim 2.

4. the second threshold current is smaller than the current withstand capacity of the fifth switching element and the sixth switching element; The single-phase three-wire inverter according to any one of claims 1 to 3, characterized in that

5. a first arm connected between a first input terminal and a second input terminal, the first arm outputting a first phase voltage and a first phase current from a first connection point between a first switching element and a second switching element; a second arm connected between the first input terminal and the second input terminal, the second arm outputting a second phase voltage and a second phase current from a second connection point between a third switching element and a fourth switching element; a third arm connected between the first input terminal and the second input terminal, the third arm outputting a third phase voltage and a third phase current from a third connection point between a fifth switching element and a sixth switching element; and filters provided between the first connection point and a first output terminal, between the second connection point and a second output terminal, and between the third connection point and a third output terminal, When the absolute value of the first phase current is equal to or greater than a first threshold current, the duty of the first switching signal of the first arm is suppressed; when the absolute value of the second phase current is equal to or greater than the first threshold current, the duty of the second switching signal of the second arm is suppressed; and when the absolute value of the third phase current is equal to or greater than a second threshold current that is greater than the first threshold current, the duty of the third switching signal of the third arm is suppressed. A control method comprising:

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